Commit | Line | Data |
---|---|---|
02bfc030 | 1 | /* |
7359154e | 2 | * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips |
02bfc030 | 3 | * |
7359154e | 4 | * Copyright (C) 2009-2010 Nokia Corporation |
02bfc030 PW |
5 | * Paul Walmsley |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * XXX handle crossbar/shared link difference for L3? | |
7359154e | 12 | * XXX these should be marked initdata for multi-OMAP kernels |
02bfc030 | 13 | */ |
ce491cf8 | 14 | #include <plat/omap_hwmod.h> |
02bfc030 | 15 | #include <mach/irqs.h> |
ce491cf8 TL |
16 | #include <plat/cpu.h> |
17 | #include <plat/dma.h> | |
046465b7 | 18 | #include <plat/serial.h> |
2004290f | 19 | #include <plat/i2c.h> |
aeac0e44 | 20 | #include <plat/gpio.h> |
02bfc030 | 21 | |
43b40992 PW |
22 | #include "omap_hwmod_common_data.h" |
23 | ||
02bfc030 | 24 | #include "prm-regbits-24xx.h" |
165e2161 | 25 | #include "cm-regbits-24xx.h" |
ff2516fb | 26 | #include "wd_timer.h" |
02bfc030 | 27 | |
7359154e PW |
28 | /* |
29 | * OMAP2430 hardware module integration data | |
30 | * | |
31 | * ALl of the data in this section should be autogeneratable from the | |
32 | * TI hardware database or other technical documentation. Data that | |
33 | * is driver-specific or driver-kernel integration-specific belongs | |
34 | * elsewhere. | |
35 | */ | |
36 | ||
02bfc030 | 37 | static struct omap_hwmod omap2430_mpu_hwmod; |
08072acf | 38 | static struct omap_hwmod omap2430_iva_hwmod; |
4a7cf90a | 39 | static struct omap_hwmod omap2430_l3_main_hwmod; |
02bfc030 | 40 | static struct omap_hwmod omap2430_l4_core_hwmod; |
165e2161 | 41 | static struct omap_hwmod omap2430_wd_timer2_hwmod; |
aeac0e44 VC |
42 | static struct omap_hwmod omap2430_gpio1_hwmod; |
43 | static struct omap_hwmod omap2430_gpio2_hwmod; | |
44 | static struct omap_hwmod omap2430_gpio3_hwmod; | |
45 | static struct omap_hwmod omap2430_gpio4_hwmod; | |
46 | static struct omap_hwmod omap2430_gpio5_hwmod; | |
82cbd1ae | 47 | static struct omap_hwmod omap2430_dma_system_hwmod; |
02bfc030 PW |
48 | |
49 | /* L3 -> L4_CORE interface */ | |
4a7cf90a KH |
50 | static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { |
51 | .master = &omap2430_l3_main_hwmod, | |
02bfc030 PW |
52 | .slave = &omap2430_l4_core_hwmod, |
53 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
54 | }; | |
55 | ||
56 | /* MPU -> L3 interface */ | |
4a7cf90a | 57 | static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = { |
02bfc030 | 58 | .master = &omap2430_mpu_hwmod, |
4a7cf90a | 59 | .slave = &omap2430_l3_main_hwmod, |
02bfc030 PW |
60 | .user = OCP_USER_MPU, |
61 | }; | |
62 | ||
63 | /* Slave interfaces on the L3 interconnect */ | |
4a7cf90a KH |
64 | static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = { |
65 | &omap2430_mpu__l3_main, | |
02bfc030 PW |
66 | }; |
67 | ||
68 | /* Master interfaces on the L3 interconnect */ | |
4a7cf90a KH |
69 | static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = { |
70 | &omap2430_l3_main__l4_core, | |
02bfc030 PW |
71 | }; |
72 | ||
73 | /* L3 */ | |
4a7cf90a | 74 | static struct omap_hwmod omap2430_l3_main_hwmod = { |
fa98347e | 75 | .name = "l3_main", |
43b40992 | 76 | .class = &l3_hwmod_class, |
4a7cf90a KH |
77 | .masters = omap2430_l3_main_masters, |
78 | .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters), | |
79 | .slaves = omap2430_l3_main_slaves, | |
80 | .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves), | |
2eb1875d KH |
81 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
82 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
83 | }; |
84 | ||
85 | static struct omap_hwmod omap2430_l4_wkup_hwmod; | |
046465b7 KH |
86 | static struct omap_hwmod omap2430_uart1_hwmod; |
87 | static struct omap_hwmod omap2430_uart2_hwmod; | |
88 | static struct omap_hwmod omap2430_uart3_hwmod; | |
2004290f PW |
89 | static struct omap_hwmod omap2430_i2c1_hwmod; |
90 | static struct omap_hwmod omap2430_i2c2_hwmod; | |
91 | ||
92 | /* I2C IP block address space length (in bytes) */ | |
93 | #define OMAP2_I2C_AS_LEN 128 | |
94 | ||
95 | /* L4 CORE -> I2C1 interface */ | |
96 | static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = { | |
97 | { | |
98 | .pa_start = 0x48070000, | |
99 | .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, | |
100 | .flags = ADDR_TYPE_RT, | |
101 | }, | |
102 | }; | |
103 | ||
104 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { | |
105 | .master = &omap2430_l4_core_hwmod, | |
106 | .slave = &omap2430_i2c1_hwmod, | |
107 | .clk = "i2c1_ick", | |
108 | .addr = omap2430_i2c1_addr_space, | |
109 | .addr_cnt = ARRAY_SIZE(omap2430_i2c1_addr_space), | |
110 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
111 | }; | |
112 | ||
113 | /* L4 CORE -> I2C2 interface */ | |
114 | static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = { | |
115 | { | |
116 | .pa_start = 0x48072000, | |
117 | .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, | |
118 | .flags = ADDR_TYPE_RT, | |
119 | }, | |
120 | }; | |
121 | ||
122 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { | |
123 | .master = &omap2430_l4_core_hwmod, | |
124 | .slave = &omap2430_i2c2_hwmod, | |
125 | .clk = "i2c2_ick", | |
126 | .addr = omap2430_i2c2_addr_space, | |
127 | .addr_cnt = ARRAY_SIZE(omap2430_i2c2_addr_space), | |
128 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
129 | }; | |
02bfc030 PW |
130 | |
131 | /* L4_CORE -> L4_WKUP interface */ | |
132 | static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { | |
133 | .master = &omap2430_l4_core_hwmod, | |
134 | .slave = &omap2430_l4_wkup_hwmod, | |
135 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
136 | }; | |
137 | ||
046465b7 KH |
138 | /* L4 CORE -> UART1 interface */ |
139 | static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = { | |
140 | { | |
141 | .pa_start = OMAP2_UART1_BASE, | |
142 | .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, | |
143 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
144 | }, | |
145 | }; | |
146 | ||
147 | static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { | |
148 | .master = &omap2430_l4_core_hwmod, | |
149 | .slave = &omap2430_uart1_hwmod, | |
150 | .clk = "uart1_ick", | |
151 | .addr = omap2430_uart1_addr_space, | |
152 | .addr_cnt = ARRAY_SIZE(omap2430_uart1_addr_space), | |
153 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
154 | }; | |
155 | ||
156 | /* L4 CORE -> UART2 interface */ | |
157 | static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = { | |
158 | { | |
159 | .pa_start = OMAP2_UART2_BASE, | |
160 | .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, | |
161 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
162 | }, | |
163 | }; | |
164 | ||
165 | static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { | |
166 | .master = &omap2430_l4_core_hwmod, | |
167 | .slave = &omap2430_uart2_hwmod, | |
168 | .clk = "uart2_ick", | |
169 | .addr = omap2430_uart2_addr_space, | |
170 | .addr_cnt = ARRAY_SIZE(omap2430_uart2_addr_space), | |
171 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
172 | }; | |
173 | ||
174 | /* L4 PER -> UART3 interface */ | |
175 | static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = { | |
176 | { | |
177 | .pa_start = OMAP2_UART3_BASE, | |
178 | .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, | |
179 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
180 | }, | |
181 | }; | |
182 | ||
183 | static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { | |
184 | .master = &omap2430_l4_core_hwmod, | |
185 | .slave = &omap2430_uart3_hwmod, | |
186 | .clk = "uart3_ick", | |
187 | .addr = omap2430_uart3_addr_space, | |
188 | .addr_cnt = ARRAY_SIZE(omap2430_uart3_addr_space), | |
189 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
190 | }; | |
191 | ||
02bfc030 PW |
192 | /* Slave interfaces on the L4_CORE interconnect */ |
193 | static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { | |
4a7cf90a | 194 | &omap2430_l3_main__l4_core, |
02bfc030 PW |
195 | }; |
196 | ||
197 | /* Master interfaces on the L4_CORE interconnect */ | |
198 | static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { | |
199 | &omap2430_l4_core__l4_wkup, | |
200 | }; | |
201 | ||
202 | /* L4 CORE */ | |
203 | static struct omap_hwmod omap2430_l4_core_hwmod = { | |
fa98347e | 204 | .name = "l4_core", |
43b40992 | 205 | .class = &l4_hwmod_class, |
02bfc030 PW |
206 | .masters = omap2430_l4_core_masters, |
207 | .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), | |
208 | .slaves = omap2430_l4_core_slaves, | |
209 | .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves), | |
2eb1875d KH |
210 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
211 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
212 | }; |
213 | ||
214 | /* Slave interfaces on the L4_WKUP interconnect */ | |
215 | static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = { | |
216 | &omap2430_l4_core__l4_wkup, | |
046465b7 KH |
217 | &omap2_l4_core__uart1, |
218 | &omap2_l4_core__uart2, | |
219 | &omap2_l4_core__uart3, | |
02bfc030 PW |
220 | }; |
221 | ||
222 | /* Master interfaces on the L4_WKUP interconnect */ | |
223 | static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { | |
224 | }; | |
225 | ||
226 | /* L4 WKUP */ | |
227 | static struct omap_hwmod omap2430_l4_wkup_hwmod = { | |
fa98347e | 228 | .name = "l4_wkup", |
43b40992 | 229 | .class = &l4_hwmod_class, |
02bfc030 PW |
230 | .masters = omap2430_l4_wkup_masters, |
231 | .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), | |
232 | .slaves = omap2430_l4_wkup_slaves, | |
233 | .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves), | |
2eb1875d KH |
234 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
235 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
236 | }; |
237 | ||
238 | /* Master interfaces on the MPU device */ | |
239 | static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = { | |
4a7cf90a | 240 | &omap2430_mpu__l3_main, |
02bfc030 PW |
241 | }; |
242 | ||
243 | /* MPU */ | |
244 | static struct omap_hwmod omap2430_mpu_hwmod = { | |
5c2c0296 | 245 | .name = "mpu", |
43b40992 | 246 | .class = &mpu_hwmod_class, |
50ebdac2 | 247 | .main_clk = "mpu_ck", |
02bfc030 PW |
248 | .masters = omap2430_mpu_masters, |
249 | .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters), | |
250 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
251 | }; | |
252 | ||
08072acf PW |
253 | /* |
254 | * IVA2_1 interface data | |
255 | */ | |
256 | ||
257 | /* IVA2 <- L3 interface */ | |
258 | static struct omap_hwmod_ocp_if omap2430_l3__iva = { | |
259 | .master = &omap2430_l3_main_hwmod, | |
260 | .slave = &omap2430_iva_hwmod, | |
261 | .clk = "dsp_fck", | |
262 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
263 | }; | |
264 | ||
265 | static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = { | |
266 | &omap2430_l3__iva, | |
267 | }; | |
268 | ||
269 | /* | |
270 | * IVA2 (IVA2) | |
271 | */ | |
272 | ||
273 | static struct omap_hwmod omap2430_iva_hwmod = { | |
274 | .name = "iva", | |
275 | .class = &iva_hwmod_class, | |
276 | .masters = omap2430_iva_masters, | |
277 | .masters_cnt = ARRAY_SIZE(omap2430_iva_masters), | |
278 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
279 | }; | |
280 | ||
165e2161 VC |
281 | /* l4_wkup -> wd_timer2 */ |
282 | static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { | |
283 | { | |
284 | .pa_start = 0x49016000, | |
285 | .pa_end = 0x4901607f, | |
286 | .flags = ADDR_TYPE_RT | |
287 | }, | |
288 | }; | |
289 | ||
290 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { | |
291 | .master = &omap2430_l4_wkup_hwmod, | |
292 | .slave = &omap2430_wd_timer2_hwmod, | |
293 | .clk = "mpu_wdt_ick", | |
294 | .addr = omap2430_wd_timer2_addrs, | |
295 | .addr_cnt = ARRAY_SIZE(omap2430_wd_timer2_addrs), | |
296 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
297 | }; | |
298 | ||
299 | /* | |
300 | * 'wd_timer' class | |
301 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
302 | * overflow condition | |
303 | */ | |
304 | ||
305 | static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = { | |
306 | .rev_offs = 0x0, | |
307 | .sysc_offs = 0x0010, | |
308 | .syss_offs = 0x0014, | |
309 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | | |
310 | SYSC_HAS_AUTOIDLE), | |
311 | .sysc_fields = &omap_hwmod_sysc_type1, | |
312 | }; | |
313 | ||
314 | static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = { | |
ff2516fb PW |
315 | .name = "wd_timer", |
316 | .sysc = &omap2430_wd_timer_sysc, | |
317 | .pre_shutdown = &omap2_wd_timer_disable | |
165e2161 VC |
318 | }; |
319 | ||
320 | /* wd_timer2 */ | |
321 | static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { | |
322 | &omap2430_l4_wkup__wd_timer2, | |
323 | }; | |
324 | ||
325 | static struct omap_hwmod omap2430_wd_timer2_hwmod = { | |
326 | .name = "wd_timer2", | |
327 | .class = &omap2430_wd_timer_hwmod_class, | |
328 | .main_clk = "mpu_wdt_fck", | |
329 | .prcm = { | |
330 | .omap2 = { | |
331 | .prcm_reg_id = 1, | |
332 | .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
333 | .module_offs = WKUP_MOD, | |
334 | .idlest_reg_id = 1, | |
335 | .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, | |
336 | }, | |
337 | }, | |
338 | .slaves = omap2430_wd_timer2_slaves, | |
339 | .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves), | |
340 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
341 | }; | |
342 | ||
046465b7 KH |
343 | /* UART */ |
344 | ||
345 | static struct omap_hwmod_class_sysconfig uart_sysc = { | |
346 | .rev_offs = 0x50, | |
347 | .sysc_offs = 0x54, | |
348 | .syss_offs = 0x58, | |
349 | .sysc_flags = (SYSC_HAS_SIDLEMODE | | |
350 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
351 | SYSC_HAS_AUTOIDLE), | |
352 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
353 | .sysc_fields = &omap_hwmod_sysc_type1, | |
354 | }; | |
355 | ||
356 | static struct omap_hwmod_class uart_class = { | |
357 | .name = "uart", | |
358 | .sysc = &uart_sysc, | |
359 | }; | |
360 | ||
361 | /* UART1 */ | |
362 | ||
363 | static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { | |
364 | { .irq = INT_24XX_UART1_IRQ, }, | |
365 | }; | |
366 | ||
367 | static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { | |
368 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, | |
369 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, | |
370 | }; | |
371 | ||
372 | static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { | |
373 | &omap2_l4_core__uart1, | |
374 | }; | |
375 | ||
376 | static struct omap_hwmod omap2430_uart1_hwmod = { | |
377 | .name = "uart1", | |
378 | .mpu_irqs = uart1_mpu_irqs, | |
379 | .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), | |
380 | .sdma_reqs = uart1_sdma_reqs, | |
381 | .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), | |
382 | .main_clk = "uart1_fck", | |
383 | .prcm = { | |
384 | .omap2 = { | |
385 | .module_offs = CORE_MOD, | |
386 | .prcm_reg_id = 1, | |
387 | .module_bit = OMAP24XX_EN_UART1_SHIFT, | |
388 | .idlest_reg_id = 1, | |
389 | .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, | |
390 | }, | |
391 | }, | |
392 | .slaves = omap2430_uart1_slaves, | |
393 | .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), | |
394 | .class = &uart_class, | |
395 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
396 | }; | |
397 | ||
398 | /* UART2 */ | |
399 | ||
400 | static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { | |
401 | { .irq = INT_24XX_UART2_IRQ, }, | |
402 | }; | |
403 | ||
404 | static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { | |
405 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, | |
406 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, | |
407 | }; | |
408 | ||
409 | static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { | |
410 | &omap2_l4_core__uart2, | |
411 | }; | |
412 | ||
413 | static struct omap_hwmod omap2430_uart2_hwmod = { | |
414 | .name = "uart2", | |
415 | .mpu_irqs = uart2_mpu_irqs, | |
416 | .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), | |
417 | .sdma_reqs = uart2_sdma_reqs, | |
418 | .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), | |
419 | .main_clk = "uart2_fck", | |
420 | .prcm = { | |
421 | .omap2 = { | |
422 | .module_offs = CORE_MOD, | |
423 | .prcm_reg_id = 1, | |
424 | .module_bit = OMAP24XX_EN_UART2_SHIFT, | |
425 | .idlest_reg_id = 1, | |
426 | .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, | |
427 | }, | |
428 | }, | |
429 | .slaves = omap2430_uart2_slaves, | |
430 | .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), | |
431 | .class = &uart_class, | |
432 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
433 | }; | |
434 | ||
435 | /* UART3 */ | |
436 | ||
437 | static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { | |
438 | { .irq = INT_24XX_UART3_IRQ, }, | |
439 | }; | |
440 | ||
441 | static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { | |
442 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, | |
443 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, | |
444 | }; | |
445 | ||
446 | static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { | |
447 | &omap2_l4_core__uart3, | |
448 | }; | |
449 | ||
450 | static struct omap_hwmod omap2430_uart3_hwmod = { | |
451 | .name = "uart3", | |
452 | .mpu_irqs = uart3_mpu_irqs, | |
453 | .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), | |
454 | .sdma_reqs = uart3_sdma_reqs, | |
455 | .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), | |
456 | .main_clk = "uart3_fck", | |
457 | .prcm = { | |
458 | .omap2 = { | |
459 | .module_offs = CORE_MOD, | |
460 | .prcm_reg_id = 2, | |
461 | .module_bit = OMAP24XX_EN_UART3_SHIFT, | |
462 | .idlest_reg_id = 2, | |
463 | .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, | |
464 | }, | |
465 | }, | |
466 | .slaves = omap2430_uart3_slaves, | |
467 | .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), | |
468 | .class = &uart_class, | |
469 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
470 | }; | |
471 | ||
2004290f PW |
472 | /* I2C common */ |
473 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
474 | .rev_offs = 0x00, | |
475 | .sysc_offs = 0x20, | |
476 | .syss_offs = 0x10, | |
477 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
478 | .sysc_fields = &omap_hwmod_sysc_type1, | |
479 | }; | |
480 | ||
481 | static struct omap_hwmod_class i2c_class = { | |
482 | .name = "i2c", | |
483 | .sysc = &i2c_sysc, | |
484 | }; | |
485 | ||
50ebb777 | 486 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
2004290f PW |
487 | .fifo_depth = 8, /* bytes */ |
488 | }; | |
489 | ||
50ebb777 BC |
490 | /* I2C1 */ |
491 | ||
2004290f PW |
492 | static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { |
493 | { .irq = INT_24XX_I2C1_IRQ, }, | |
494 | }; | |
495 | ||
496 | static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { | |
497 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, | |
498 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, | |
499 | }; | |
500 | ||
501 | static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { | |
502 | &omap2430_l4_core__i2c1, | |
503 | }; | |
504 | ||
505 | static struct omap_hwmod omap2430_i2c1_hwmod = { | |
506 | .name = "i2c1", | |
507 | .mpu_irqs = i2c1_mpu_irqs, | |
508 | .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), | |
509 | .sdma_reqs = i2c1_sdma_reqs, | |
510 | .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), | |
511 | .main_clk = "i2chs1_fck", | |
512 | .prcm = { | |
513 | .omap2 = { | |
514 | /* | |
515 | * NOTE: The CM_FCLKEN* and CM_ICLKEN* for | |
516 | * I2CHS IP's do not follow the usual pattern. | |
517 | * prcm_reg_id alone cannot be used to program | |
518 | * the iclk and fclk. Needs to be handled using | |
519 | * additonal flags when clk handling is moved | |
520 | * to hwmod framework. | |
521 | */ | |
522 | .module_offs = CORE_MOD, | |
523 | .prcm_reg_id = 1, | |
524 | .module_bit = OMAP2430_EN_I2CHS1_SHIFT, | |
525 | .idlest_reg_id = 1, | |
526 | .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, | |
527 | }, | |
528 | }, | |
529 | .slaves = omap2430_i2c1_slaves, | |
530 | .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves), | |
531 | .class = &i2c_class, | |
50ebb777 | 532 | .dev_attr = &i2c_dev_attr, |
2004290f PW |
533 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
534 | }; | |
535 | ||
536 | /* I2C2 */ | |
537 | ||
2004290f PW |
538 | static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { |
539 | { .irq = INT_24XX_I2C2_IRQ, }, | |
540 | }; | |
541 | ||
542 | static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { | |
543 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, | |
544 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, | |
545 | }; | |
546 | ||
547 | static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { | |
548 | &omap2430_l4_core__i2c2, | |
549 | }; | |
550 | ||
551 | static struct omap_hwmod omap2430_i2c2_hwmod = { | |
552 | .name = "i2c2", | |
553 | .mpu_irqs = i2c2_mpu_irqs, | |
554 | .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), | |
555 | .sdma_reqs = i2c2_sdma_reqs, | |
556 | .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), | |
557 | .main_clk = "i2chs2_fck", | |
558 | .prcm = { | |
559 | .omap2 = { | |
560 | .module_offs = CORE_MOD, | |
561 | .prcm_reg_id = 1, | |
562 | .module_bit = OMAP2430_EN_I2CHS2_SHIFT, | |
563 | .idlest_reg_id = 1, | |
564 | .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, | |
565 | }, | |
566 | }, | |
567 | .slaves = omap2430_i2c2_slaves, | |
568 | .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves), | |
569 | .class = &i2c_class, | |
50ebb777 | 570 | .dev_attr = &i2c_dev_attr, |
2004290f PW |
571 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
572 | }; | |
573 | ||
aeac0e44 VC |
574 | /* l4_wkup -> gpio1 */ |
575 | static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { | |
576 | { | |
577 | .pa_start = 0x4900C000, | |
578 | .pa_end = 0x4900C1ff, | |
579 | .flags = ADDR_TYPE_RT | |
580 | }, | |
581 | }; | |
582 | ||
583 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { | |
584 | .master = &omap2430_l4_wkup_hwmod, | |
585 | .slave = &omap2430_gpio1_hwmod, | |
586 | .clk = "gpios_ick", | |
587 | .addr = omap2430_gpio1_addr_space, | |
588 | .addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space), | |
589 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
590 | }; | |
591 | ||
592 | /* l4_wkup -> gpio2 */ | |
593 | static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { | |
594 | { | |
595 | .pa_start = 0x4900E000, | |
596 | .pa_end = 0x4900E1ff, | |
597 | .flags = ADDR_TYPE_RT | |
598 | }, | |
599 | }; | |
600 | ||
601 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { | |
602 | .master = &omap2430_l4_wkup_hwmod, | |
603 | .slave = &omap2430_gpio2_hwmod, | |
604 | .clk = "gpios_ick", | |
605 | .addr = omap2430_gpio2_addr_space, | |
606 | .addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space), | |
607 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
608 | }; | |
609 | ||
610 | /* l4_wkup -> gpio3 */ | |
611 | static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { | |
612 | { | |
613 | .pa_start = 0x49010000, | |
614 | .pa_end = 0x490101ff, | |
615 | .flags = ADDR_TYPE_RT | |
616 | }, | |
617 | }; | |
618 | ||
619 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { | |
620 | .master = &omap2430_l4_wkup_hwmod, | |
621 | .slave = &omap2430_gpio3_hwmod, | |
622 | .clk = "gpios_ick", | |
623 | .addr = omap2430_gpio3_addr_space, | |
624 | .addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space), | |
625 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
626 | }; | |
627 | ||
628 | /* l4_wkup -> gpio4 */ | |
629 | static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { | |
630 | { | |
631 | .pa_start = 0x49012000, | |
632 | .pa_end = 0x490121ff, | |
633 | .flags = ADDR_TYPE_RT | |
634 | }, | |
635 | }; | |
636 | ||
637 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { | |
638 | .master = &omap2430_l4_wkup_hwmod, | |
639 | .slave = &omap2430_gpio4_hwmod, | |
640 | .clk = "gpios_ick", | |
641 | .addr = omap2430_gpio4_addr_space, | |
642 | .addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space), | |
643 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
644 | }; | |
645 | ||
646 | /* l4_core -> gpio5 */ | |
647 | static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { | |
648 | { | |
649 | .pa_start = 0x480B6000, | |
650 | .pa_end = 0x480B61ff, | |
651 | .flags = ADDR_TYPE_RT | |
652 | }, | |
653 | }; | |
654 | ||
655 | static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { | |
656 | .master = &omap2430_l4_core_hwmod, | |
657 | .slave = &omap2430_gpio5_hwmod, | |
658 | .clk = "gpio5_ick", | |
659 | .addr = omap2430_gpio5_addr_space, | |
660 | .addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space), | |
661 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
662 | }; | |
663 | ||
664 | /* gpio dev_attr */ | |
665 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
666 | .bank_width = 32, | |
667 | .dbck_flag = false, | |
668 | }; | |
669 | ||
670 | static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = { | |
671 | .rev_offs = 0x0000, | |
672 | .sysc_offs = 0x0010, | |
673 | .syss_offs = 0x0014, | |
674 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
675 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
676 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
677 | .sysc_fields = &omap_hwmod_sysc_type1, | |
678 | }; | |
679 | ||
680 | /* | |
681 | * 'gpio' class | |
682 | * general purpose io module | |
683 | */ | |
684 | static struct omap_hwmod_class omap243x_gpio_hwmod_class = { | |
685 | .name = "gpio", | |
686 | .sysc = &omap243x_gpio_sysc, | |
687 | .rev = 0, | |
688 | }; | |
689 | ||
690 | /* gpio1 */ | |
691 | static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = { | |
692 | { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ | |
693 | }; | |
694 | ||
695 | static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { | |
696 | &omap2430_l4_wkup__gpio1, | |
697 | }; | |
698 | ||
699 | static struct omap_hwmod omap2430_gpio1_hwmod = { | |
700 | .name = "gpio1", | |
701 | .mpu_irqs = omap243x_gpio1_irqs, | |
702 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs), | |
703 | .main_clk = "gpios_fck", | |
704 | .prcm = { | |
705 | .omap2 = { | |
706 | .prcm_reg_id = 1, | |
707 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
708 | .module_offs = WKUP_MOD, | |
709 | .idlest_reg_id = 1, | |
710 | .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
711 | }, | |
712 | }, | |
713 | .slaves = omap2430_gpio1_slaves, | |
714 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), | |
715 | .class = &omap243x_gpio_hwmod_class, | |
716 | .dev_attr = &gpio_dev_attr, | |
717 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
718 | }; | |
719 | ||
720 | /* gpio2 */ | |
721 | static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = { | |
722 | { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ | |
723 | }; | |
724 | ||
725 | static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { | |
726 | &omap2430_l4_wkup__gpio2, | |
727 | }; | |
728 | ||
729 | static struct omap_hwmod omap2430_gpio2_hwmod = { | |
730 | .name = "gpio2", | |
731 | .mpu_irqs = omap243x_gpio2_irqs, | |
732 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs), | |
733 | .main_clk = "gpios_fck", | |
734 | .prcm = { | |
735 | .omap2 = { | |
736 | .prcm_reg_id = 1, | |
737 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
738 | .module_offs = WKUP_MOD, | |
739 | .idlest_reg_id = 1, | |
740 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
741 | }, | |
742 | }, | |
743 | .slaves = omap2430_gpio2_slaves, | |
744 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), | |
745 | .class = &omap243x_gpio_hwmod_class, | |
746 | .dev_attr = &gpio_dev_attr, | |
747 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
748 | }; | |
749 | ||
750 | /* gpio3 */ | |
751 | static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = { | |
752 | { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ | |
753 | }; | |
754 | ||
755 | static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { | |
756 | &omap2430_l4_wkup__gpio3, | |
757 | }; | |
758 | ||
759 | static struct omap_hwmod omap2430_gpio3_hwmod = { | |
760 | .name = "gpio3", | |
761 | .mpu_irqs = omap243x_gpio3_irqs, | |
762 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs), | |
763 | .main_clk = "gpios_fck", | |
764 | .prcm = { | |
765 | .omap2 = { | |
766 | .prcm_reg_id = 1, | |
767 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
768 | .module_offs = WKUP_MOD, | |
769 | .idlest_reg_id = 1, | |
770 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
771 | }, | |
772 | }, | |
773 | .slaves = omap2430_gpio3_slaves, | |
774 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), | |
775 | .class = &omap243x_gpio_hwmod_class, | |
776 | .dev_attr = &gpio_dev_attr, | |
777 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
778 | }; | |
779 | ||
780 | /* gpio4 */ | |
781 | static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = { | |
782 | { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ | |
783 | }; | |
784 | ||
785 | static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { | |
786 | &omap2430_l4_wkup__gpio4, | |
787 | }; | |
788 | ||
789 | static struct omap_hwmod omap2430_gpio4_hwmod = { | |
790 | .name = "gpio4", | |
791 | .mpu_irqs = omap243x_gpio4_irqs, | |
792 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs), | |
793 | .main_clk = "gpios_fck", | |
794 | .prcm = { | |
795 | .omap2 = { | |
796 | .prcm_reg_id = 1, | |
797 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
798 | .module_offs = WKUP_MOD, | |
799 | .idlest_reg_id = 1, | |
800 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
801 | }, | |
802 | }, | |
803 | .slaves = omap2430_gpio4_slaves, | |
804 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), | |
805 | .class = &omap243x_gpio_hwmod_class, | |
806 | .dev_attr = &gpio_dev_attr, | |
807 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
808 | }; | |
809 | ||
810 | /* gpio5 */ | |
811 | static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { | |
812 | { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ | |
813 | }; | |
814 | ||
815 | static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { | |
816 | &omap2430_l4_core__gpio5, | |
817 | }; | |
818 | ||
819 | static struct omap_hwmod omap2430_gpio5_hwmod = { | |
820 | .name = "gpio5", | |
821 | .mpu_irqs = omap243x_gpio5_irqs, | |
822 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs), | |
823 | .main_clk = "gpio5_fck", | |
824 | .prcm = { | |
825 | .omap2 = { | |
826 | .prcm_reg_id = 2, | |
827 | .module_bit = OMAP2430_EN_GPIO5_SHIFT, | |
828 | .module_offs = CORE_MOD, | |
829 | .idlest_reg_id = 2, | |
830 | .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, | |
831 | }, | |
832 | }, | |
833 | .slaves = omap2430_gpio5_slaves, | |
834 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), | |
835 | .class = &omap243x_gpio_hwmod_class, | |
836 | .dev_attr = &gpio_dev_attr, | |
837 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
838 | }; | |
839 | ||
82cbd1ae MK |
840 | /* dma_system */ |
841 | static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = { | |
842 | .rev_offs = 0x0000, | |
843 | .sysc_offs = 0x002c, | |
844 | .syss_offs = 0x0028, | |
845 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | | |
846 | SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | | |
847 | SYSC_HAS_AUTOIDLE), | |
848 | .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
849 | .sysc_fields = &omap_hwmod_sysc_type1, | |
850 | }; | |
851 | ||
852 | static struct omap_hwmod_class omap2430_dma_hwmod_class = { | |
853 | .name = "dma", | |
854 | .sysc = &omap2430_dma_sysc, | |
855 | }; | |
856 | ||
857 | /* dma attributes */ | |
858 | static struct omap_dma_dev_attr dma_dev_attr = { | |
859 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
860 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
861 | .lch_count = 32, | |
862 | }; | |
863 | ||
864 | static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = { | |
865 | { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ | |
866 | { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ | |
867 | { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ | |
868 | { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ | |
869 | }; | |
870 | ||
871 | static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = { | |
872 | { | |
873 | .pa_start = 0x48056000, | |
874 | .pa_end = 0x4a0560ff, | |
875 | .flags = ADDR_TYPE_RT | |
876 | }, | |
877 | }; | |
878 | ||
879 | /* dma_system -> L3 */ | |
880 | static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { | |
881 | .master = &omap2430_dma_system_hwmod, | |
882 | .slave = &omap2430_l3_main_hwmod, | |
883 | .clk = "core_l3_ck", | |
884 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
885 | }; | |
886 | ||
887 | /* dma_system master ports */ | |
888 | static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = { | |
889 | &omap2430_dma_system__l3, | |
890 | }; | |
891 | ||
892 | /* l4_core -> dma_system */ | |
893 | static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { | |
894 | .master = &omap2430_l4_core_hwmod, | |
895 | .slave = &omap2430_dma_system_hwmod, | |
896 | .clk = "sdma_ick", | |
897 | .addr = omap2430_dma_system_addrs, | |
898 | .addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs), | |
899 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
900 | }; | |
901 | ||
902 | /* dma_system slave ports */ | |
903 | static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = { | |
904 | &omap2430_l4_core__dma_system, | |
905 | }; | |
906 | ||
907 | static struct omap_hwmod omap2430_dma_system_hwmod = { | |
908 | .name = "dma", | |
909 | .class = &omap2430_dma_hwmod_class, | |
910 | .mpu_irqs = omap2430_dma_system_irqs, | |
911 | .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs), | |
912 | .main_clk = "core_l3_ck", | |
913 | .slaves = omap2430_dma_system_slaves, | |
914 | .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves), | |
915 | .masters = omap2430_dma_system_masters, | |
916 | .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters), | |
917 | .dev_attr = &dma_dev_attr, | |
918 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
919 | .flags = HWMOD_NO_IDLEST, | |
920 | }; | |
921 | ||
02bfc030 | 922 | static __initdata struct omap_hwmod *omap2430_hwmods[] = { |
4a7cf90a | 923 | &omap2430_l3_main_hwmod, |
02bfc030 PW |
924 | &omap2430_l4_core_hwmod, |
925 | &omap2430_l4_wkup_hwmod, | |
926 | &omap2430_mpu_hwmod, | |
08072acf | 927 | &omap2430_iva_hwmod, |
165e2161 | 928 | &omap2430_wd_timer2_hwmod, |
046465b7 KH |
929 | &omap2430_uart1_hwmod, |
930 | &omap2430_uart2_hwmod, | |
931 | &omap2430_uart3_hwmod, | |
2004290f PW |
932 | &omap2430_i2c1_hwmod, |
933 | &omap2430_i2c2_hwmod, | |
aeac0e44 VC |
934 | |
935 | /* gpio class */ | |
936 | &omap2430_gpio1_hwmod, | |
937 | &omap2430_gpio2_hwmod, | |
938 | &omap2430_gpio3_hwmod, | |
939 | &omap2430_gpio4_hwmod, | |
940 | &omap2430_gpio5_hwmod, | |
82cbd1ae MK |
941 | |
942 | /* dma_system class*/ | |
943 | &omap2430_dma_system_hwmod, | |
02bfc030 PW |
944 | NULL, |
945 | }; | |
946 | ||
7359154e PW |
947 | int __init omap2430_hwmod_init(void) |
948 | { | |
949 | return omap_hwmod_init(omap2430_hwmods); | |
950 | } |