Commit | Line | Data |
---|---|---|
02bfc030 | 1 | /* |
7359154e | 2 | * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips |
02bfc030 | 3 | * |
7359154e | 4 | * Copyright (C) 2009-2010 Nokia Corporation |
02bfc030 PW |
5 | * Paul Walmsley |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * XXX handle crossbar/shared link difference for L3? | |
7359154e | 12 | * XXX these should be marked initdata for multi-OMAP kernels |
02bfc030 | 13 | */ |
ce491cf8 | 14 | #include <plat/omap_hwmod.h> |
02bfc030 | 15 | #include <mach/irqs.h> |
ce491cf8 TL |
16 | #include <plat/cpu.h> |
17 | #include <plat/dma.h> | |
046465b7 | 18 | #include <plat/serial.h> |
2004290f | 19 | #include <plat/i2c.h> |
aeac0e44 | 20 | #include <plat/gpio.h> |
02bfc030 | 21 | |
43b40992 PW |
22 | #include "omap_hwmod_common_data.h" |
23 | ||
02bfc030 | 24 | #include "prm-regbits-24xx.h" |
165e2161 | 25 | #include "cm-regbits-24xx.h" |
02bfc030 | 26 | |
7359154e PW |
27 | /* |
28 | * OMAP2430 hardware module integration data | |
29 | * | |
30 | * ALl of the data in this section should be autogeneratable from the | |
31 | * TI hardware database or other technical documentation. Data that | |
32 | * is driver-specific or driver-kernel integration-specific belongs | |
33 | * elsewhere. | |
34 | */ | |
35 | ||
02bfc030 | 36 | static struct omap_hwmod omap2430_mpu_hwmod; |
08072acf | 37 | static struct omap_hwmod omap2430_iva_hwmod; |
4a7cf90a | 38 | static struct omap_hwmod omap2430_l3_main_hwmod; |
02bfc030 | 39 | static struct omap_hwmod omap2430_l4_core_hwmod; |
165e2161 | 40 | static struct omap_hwmod omap2430_wd_timer2_hwmod; |
aeac0e44 VC |
41 | static struct omap_hwmod omap2430_gpio1_hwmod; |
42 | static struct omap_hwmod omap2430_gpio2_hwmod; | |
43 | static struct omap_hwmod omap2430_gpio3_hwmod; | |
44 | static struct omap_hwmod omap2430_gpio4_hwmod; | |
45 | static struct omap_hwmod omap2430_gpio5_hwmod; | |
82cbd1ae | 46 | static struct omap_hwmod omap2430_dma_system_hwmod; |
02bfc030 PW |
47 | |
48 | /* L3 -> L4_CORE interface */ | |
4a7cf90a KH |
49 | static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { |
50 | .master = &omap2430_l3_main_hwmod, | |
02bfc030 PW |
51 | .slave = &omap2430_l4_core_hwmod, |
52 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
53 | }; | |
54 | ||
55 | /* MPU -> L3 interface */ | |
4a7cf90a | 56 | static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = { |
02bfc030 | 57 | .master = &omap2430_mpu_hwmod, |
4a7cf90a | 58 | .slave = &omap2430_l3_main_hwmod, |
02bfc030 PW |
59 | .user = OCP_USER_MPU, |
60 | }; | |
61 | ||
62 | /* Slave interfaces on the L3 interconnect */ | |
4a7cf90a KH |
63 | static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = { |
64 | &omap2430_mpu__l3_main, | |
02bfc030 PW |
65 | }; |
66 | ||
67 | /* Master interfaces on the L3 interconnect */ | |
4a7cf90a KH |
68 | static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = { |
69 | &omap2430_l3_main__l4_core, | |
02bfc030 PW |
70 | }; |
71 | ||
72 | /* L3 */ | |
4a7cf90a | 73 | static struct omap_hwmod omap2430_l3_main_hwmod = { |
fa98347e | 74 | .name = "l3_main", |
43b40992 | 75 | .class = &l3_hwmod_class, |
4a7cf90a KH |
76 | .masters = omap2430_l3_main_masters, |
77 | .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters), | |
78 | .slaves = omap2430_l3_main_slaves, | |
79 | .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves), | |
2eb1875d KH |
80 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
81 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
82 | }; |
83 | ||
84 | static struct omap_hwmod omap2430_l4_wkup_hwmod; | |
046465b7 KH |
85 | static struct omap_hwmod omap2430_uart1_hwmod; |
86 | static struct omap_hwmod omap2430_uart2_hwmod; | |
87 | static struct omap_hwmod omap2430_uart3_hwmod; | |
2004290f PW |
88 | static struct omap_hwmod omap2430_i2c1_hwmod; |
89 | static struct omap_hwmod omap2430_i2c2_hwmod; | |
90 | ||
91 | /* I2C IP block address space length (in bytes) */ | |
92 | #define OMAP2_I2C_AS_LEN 128 | |
93 | ||
94 | /* L4 CORE -> I2C1 interface */ | |
95 | static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = { | |
96 | { | |
97 | .pa_start = 0x48070000, | |
98 | .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, | |
99 | .flags = ADDR_TYPE_RT, | |
100 | }, | |
101 | }; | |
102 | ||
103 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { | |
104 | .master = &omap2430_l4_core_hwmod, | |
105 | .slave = &omap2430_i2c1_hwmod, | |
106 | .clk = "i2c1_ick", | |
107 | .addr = omap2430_i2c1_addr_space, | |
108 | .addr_cnt = ARRAY_SIZE(omap2430_i2c1_addr_space), | |
109 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
110 | }; | |
111 | ||
112 | /* L4 CORE -> I2C2 interface */ | |
113 | static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = { | |
114 | { | |
115 | .pa_start = 0x48072000, | |
116 | .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, | |
117 | .flags = ADDR_TYPE_RT, | |
118 | }, | |
119 | }; | |
120 | ||
121 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { | |
122 | .master = &omap2430_l4_core_hwmod, | |
123 | .slave = &omap2430_i2c2_hwmod, | |
124 | .clk = "i2c2_ick", | |
125 | .addr = omap2430_i2c2_addr_space, | |
126 | .addr_cnt = ARRAY_SIZE(omap2430_i2c2_addr_space), | |
127 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
128 | }; | |
02bfc030 PW |
129 | |
130 | /* L4_CORE -> L4_WKUP interface */ | |
131 | static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { | |
132 | .master = &omap2430_l4_core_hwmod, | |
133 | .slave = &omap2430_l4_wkup_hwmod, | |
134 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
135 | }; | |
136 | ||
046465b7 KH |
137 | /* L4 CORE -> UART1 interface */ |
138 | static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = { | |
139 | { | |
140 | .pa_start = OMAP2_UART1_BASE, | |
141 | .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, | |
142 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
143 | }, | |
144 | }; | |
145 | ||
146 | static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { | |
147 | .master = &omap2430_l4_core_hwmod, | |
148 | .slave = &omap2430_uart1_hwmod, | |
149 | .clk = "uart1_ick", | |
150 | .addr = omap2430_uart1_addr_space, | |
151 | .addr_cnt = ARRAY_SIZE(omap2430_uart1_addr_space), | |
152 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
153 | }; | |
154 | ||
155 | /* L4 CORE -> UART2 interface */ | |
156 | static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = { | |
157 | { | |
158 | .pa_start = OMAP2_UART2_BASE, | |
159 | .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, | |
160 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
161 | }, | |
162 | }; | |
163 | ||
164 | static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { | |
165 | .master = &omap2430_l4_core_hwmod, | |
166 | .slave = &omap2430_uart2_hwmod, | |
167 | .clk = "uart2_ick", | |
168 | .addr = omap2430_uart2_addr_space, | |
169 | .addr_cnt = ARRAY_SIZE(omap2430_uart2_addr_space), | |
170 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
171 | }; | |
172 | ||
173 | /* L4 PER -> UART3 interface */ | |
174 | static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = { | |
175 | { | |
176 | .pa_start = OMAP2_UART3_BASE, | |
177 | .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, | |
178 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
179 | }, | |
180 | }; | |
181 | ||
182 | static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { | |
183 | .master = &omap2430_l4_core_hwmod, | |
184 | .slave = &omap2430_uart3_hwmod, | |
185 | .clk = "uart3_ick", | |
186 | .addr = omap2430_uart3_addr_space, | |
187 | .addr_cnt = ARRAY_SIZE(omap2430_uart3_addr_space), | |
188 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
189 | }; | |
190 | ||
02bfc030 PW |
191 | /* Slave interfaces on the L4_CORE interconnect */ |
192 | static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { | |
4a7cf90a | 193 | &omap2430_l3_main__l4_core, |
02bfc030 PW |
194 | }; |
195 | ||
196 | /* Master interfaces on the L4_CORE interconnect */ | |
197 | static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { | |
198 | &omap2430_l4_core__l4_wkup, | |
199 | }; | |
200 | ||
201 | /* L4 CORE */ | |
202 | static struct omap_hwmod omap2430_l4_core_hwmod = { | |
fa98347e | 203 | .name = "l4_core", |
43b40992 | 204 | .class = &l4_hwmod_class, |
02bfc030 PW |
205 | .masters = omap2430_l4_core_masters, |
206 | .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), | |
207 | .slaves = omap2430_l4_core_slaves, | |
208 | .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves), | |
2eb1875d KH |
209 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
210 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
211 | }; |
212 | ||
213 | /* Slave interfaces on the L4_WKUP interconnect */ | |
214 | static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = { | |
215 | &omap2430_l4_core__l4_wkup, | |
046465b7 KH |
216 | &omap2_l4_core__uart1, |
217 | &omap2_l4_core__uart2, | |
218 | &omap2_l4_core__uart3, | |
02bfc030 PW |
219 | }; |
220 | ||
221 | /* Master interfaces on the L4_WKUP interconnect */ | |
222 | static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { | |
223 | }; | |
224 | ||
225 | /* L4 WKUP */ | |
226 | static struct omap_hwmod omap2430_l4_wkup_hwmod = { | |
fa98347e | 227 | .name = "l4_wkup", |
43b40992 | 228 | .class = &l4_hwmod_class, |
02bfc030 PW |
229 | .masters = omap2430_l4_wkup_masters, |
230 | .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), | |
231 | .slaves = omap2430_l4_wkup_slaves, | |
232 | .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves), | |
2eb1875d KH |
233 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
234 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
235 | }; |
236 | ||
237 | /* Master interfaces on the MPU device */ | |
238 | static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = { | |
4a7cf90a | 239 | &omap2430_mpu__l3_main, |
02bfc030 PW |
240 | }; |
241 | ||
242 | /* MPU */ | |
243 | static struct omap_hwmod omap2430_mpu_hwmod = { | |
5c2c0296 | 244 | .name = "mpu", |
43b40992 | 245 | .class = &mpu_hwmod_class, |
50ebdac2 | 246 | .main_clk = "mpu_ck", |
02bfc030 PW |
247 | .masters = omap2430_mpu_masters, |
248 | .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters), | |
249 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
250 | }; | |
251 | ||
08072acf PW |
252 | /* |
253 | * IVA2_1 interface data | |
254 | */ | |
255 | ||
256 | /* IVA2 <- L3 interface */ | |
257 | static struct omap_hwmod_ocp_if omap2430_l3__iva = { | |
258 | .master = &omap2430_l3_main_hwmod, | |
259 | .slave = &omap2430_iva_hwmod, | |
260 | .clk = "dsp_fck", | |
261 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
262 | }; | |
263 | ||
264 | static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = { | |
265 | &omap2430_l3__iva, | |
266 | }; | |
267 | ||
268 | /* | |
269 | * IVA2 (IVA2) | |
270 | */ | |
271 | ||
272 | static struct omap_hwmod omap2430_iva_hwmod = { | |
273 | .name = "iva", | |
274 | .class = &iva_hwmod_class, | |
275 | .masters = omap2430_iva_masters, | |
276 | .masters_cnt = ARRAY_SIZE(omap2430_iva_masters), | |
277 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
278 | }; | |
279 | ||
165e2161 VC |
280 | /* l4_wkup -> wd_timer2 */ |
281 | static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { | |
282 | { | |
283 | .pa_start = 0x49016000, | |
284 | .pa_end = 0x4901607f, | |
285 | .flags = ADDR_TYPE_RT | |
286 | }, | |
287 | }; | |
288 | ||
289 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { | |
290 | .master = &omap2430_l4_wkup_hwmod, | |
291 | .slave = &omap2430_wd_timer2_hwmod, | |
292 | .clk = "mpu_wdt_ick", | |
293 | .addr = omap2430_wd_timer2_addrs, | |
294 | .addr_cnt = ARRAY_SIZE(omap2430_wd_timer2_addrs), | |
295 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
296 | }; | |
297 | ||
298 | /* | |
299 | * 'wd_timer' class | |
300 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
301 | * overflow condition | |
302 | */ | |
303 | ||
304 | static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = { | |
305 | .rev_offs = 0x0, | |
306 | .sysc_offs = 0x0010, | |
307 | .syss_offs = 0x0014, | |
308 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | | |
309 | SYSC_HAS_AUTOIDLE), | |
310 | .sysc_fields = &omap_hwmod_sysc_type1, | |
311 | }; | |
312 | ||
313 | static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = { | |
314 | .name = "wd_timer", | |
315 | .sysc = &omap2430_wd_timer_sysc, | |
316 | }; | |
317 | ||
318 | /* wd_timer2 */ | |
319 | static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { | |
320 | &omap2430_l4_wkup__wd_timer2, | |
321 | }; | |
322 | ||
323 | static struct omap_hwmod omap2430_wd_timer2_hwmod = { | |
324 | .name = "wd_timer2", | |
325 | .class = &omap2430_wd_timer_hwmod_class, | |
326 | .main_clk = "mpu_wdt_fck", | |
327 | .prcm = { | |
328 | .omap2 = { | |
329 | .prcm_reg_id = 1, | |
330 | .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
331 | .module_offs = WKUP_MOD, | |
332 | .idlest_reg_id = 1, | |
333 | .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, | |
334 | }, | |
335 | }, | |
336 | .slaves = omap2430_wd_timer2_slaves, | |
337 | .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves), | |
338 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
339 | }; | |
340 | ||
046465b7 KH |
341 | /* UART */ |
342 | ||
343 | static struct omap_hwmod_class_sysconfig uart_sysc = { | |
344 | .rev_offs = 0x50, | |
345 | .sysc_offs = 0x54, | |
346 | .syss_offs = 0x58, | |
347 | .sysc_flags = (SYSC_HAS_SIDLEMODE | | |
348 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
349 | SYSC_HAS_AUTOIDLE), | |
350 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
351 | .sysc_fields = &omap_hwmod_sysc_type1, | |
352 | }; | |
353 | ||
354 | static struct omap_hwmod_class uart_class = { | |
355 | .name = "uart", | |
356 | .sysc = &uart_sysc, | |
357 | }; | |
358 | ||
359 | /* UART1 */ | |
360 | ||
361 | static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { | |
362 | { .irq = INT_24XX_UART1_IRQ, }, | |
363 | }; | |
364 | ||
365 | static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { | |
366 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, | |
367 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, | |
368 | }; | |
369 | ||
370 | static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { | |
371 | &omap2_l4_core__uart1, | |
372 | }; | |
373 | ||
374 | static struct omap_hwmod omap2430_uart1_hwmod = { | |
375 | .name = "uart1", | |
376 | .mpu_irqs = uart1_mpu_irqs, | |
377 | .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), | |
378 | .sdma_reqs = uart1_sdma_reqs, | |
379 | .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), | |
380 | .main_clk = "uart1_fck", | |
381 | .prcm = { | |
382 | .omap2 = { | |
383 | .module_offs = CORE_MOD, | |
384 | .prcm_reg_id = 1, | |
385 | .module_bit = OMAP24XX_EN_UART1_SHIFT, | |
386 | .idlest_reg_id = 1, | |
387 | .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, | |
388 | }, | |
389 | }, | |
390 | .slaves = omap2430_uart1_slaves, | |
391 | .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), | |
392 | .class = &uart_class, | |
393 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
394 | }; | |
395 | ||
396 | /* UART2 */ | |
397 | ||
398 | static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { | |
399 | { .irq = INT_24XX_UART2_IRQ, }, | |
400 | }; | |
401 | ||
402 | static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { | |
403 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, | |
404 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, | |
405 | }; | |
406 | ||
407 | static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { | |
408 | &omap2_l4_core__uart2, | |
409 | }; | |
410 | ||
411 | static struct omap_hwmod omap2430_uart2_hwmod = { | |
412 | .name = "uart2", | |
413 | .mpu_irqs = uart2_mpu_irqs, | |
414 | .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), | |
415 | .sdma_reqs = uart2_sdma_reqs, | |
416 | .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), | |
417 | .main_clk = "uart2_fck", | |
418 | .prcm = { | |
419 | .omap2 = { | |
420 | .module_offs = CORE_MOD, | |
421 | .prcm_reg_id = 1, | |
422 | .module_bit = OMAP24XX_EN_UART2_SHIFT, | |
423 | .idlest_reg_id = 1, | |
424 | .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, | |
425 | }, | |
426 | }, | |
427 | .slaves = omap2430_uart2_slaves, | |
428 | .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), | |
429 | .class = &uart_class, | |
430 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
431 | }; | |
432 | ||
433 | /* UART3 */ | |
434 | ||
435 | static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { | |
436 | { .irq = INT_24XX_UART3_IRQ, }, | |
437 | }; | |
438 | ||
439 | static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { | |
440 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, | |
441 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, | |
442 | }; | |
443 | ||
444 | static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { | |
445 | &omap2_l4_core__uart3, | |
446 | }; | |
447 | ||
448 | static struct omap_hwmod omap2430_uart3_hwmod = { | |
449 | .name = "uart3", | |
450 | .mpu_irqs = uart3_mpu_irqs, | |
451 | .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), | |
452 | .sdma_reqs = uart3_sdma_reqs, | |
453 | .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), | |
454 | .main_clk = "uart3_fck", | |
455 | .prcm = { | |
456 | .omap2 = { | |
457 | .module_offs = CORE_MOD, | |
458 | .prcm_reg_id = 2, | |
459 | .module_bit = OMAP24XX_EN_UART3_SHIFT, | |
460 | .idlest_reg_id = 2, | |
461 | .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, | |
462 | }, | |
463 | }, | |
464 | .slaves = omap2430_uart3_slaves, | |
465 | .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), | |
466 | .class = &uart_class, | |
467 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
468 | }; | |
469 | ||
2004290f PW |
470 | /* I2C common */ |
471 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
472 | .rev_offs = 0x00, | |
473 | .sysc_offs = 0x20, | |
474 | .syss_offs = 0x10, | |
475 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
476 | .sysc_fields = &omap_hwmod_sysc_type1, | |
477 | }; | |
478 | ||
479 | static struct omap_hwmod_class i2c_class = { | |
480 | .name = "i2c", | |
481 | .sysc = &i2c_sysc, | |
482 | }; | |
483 | ||
2004290f PW |
484 | /* I2C1 */ |
485 | ||
486 | static struct omap_i2c_dev_attr i2c1_dev_attr = { | |
487 | .fifo_depth = 8, /* bytes */ | |
488 | }; | |
489 | ||
490 | static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { | |
491 | { .irq = INT_24XX_I2C1_IRQ, }, | |
492 | }; | |
493 | ||
494 | static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { | |
495 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, | |
496 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, | |
497 | }; | |
498 | ||
499 | static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { | |
500 | &omap2430_l4_core__i2c1, | |
501 | }; | |
502 | ||
503 | static struct omap_hwmod omap2430_i2c1_hwmod = { | |
504 | .name = "i2c1", | |
505 | .mpu_irqs = i2c1_mpu_irqs, | |
506 | .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), | |
507 | .sdma_reqs = i2c1_sdma_reqs, | |
508 | .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), | |
509 | .main_clk = "i2chs1_fck", | |
510 | .prcm = { | |
511 | .omap2 = { | |
512 | /* | |
513 | * NOTE: The CM_FCLKEN* and CM_ICLKEN* for | |
514 | * I2CHS IP's do not follow the usual pattern. | |
515 | * prcm_reg_id alone cannot be used to program | |
516 | * the iclk and fclk. Needs to be handled using | |
517 | * additonal flags when clk handling is moved | |
518 | * to hwmod framework. | |
519 | */ | |
520 | .module_offs = CORE_MOD, | |
521 | .prcm_reg_id = 1, | |
522 | .module_bit = OMAP2430_EN_I2CHS1_SHIFT, | |
523 | .idlest_reg_id = 1, | |
524 | .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, | |
525 | }, | |
526 | }, | |
527 | .slaves = omap2430_i2c1_slaves, | |
528 | .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves), | |
529 | .class = &i2c_class, | |
530 | .dev_attr = &i2c1_dev_attr, | |
531 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
532 | }; | |
533 | ||
534 | /* I2C2 */ | |
535 | ||
536 | static struct omap_i2c_dev_attr i2c2_dev_attr = { | |
537 | .fifo_depth = 8, /* bytes */ | |
538 | }; | |
539 | ||
540 | static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { | |
541 | { .irq = INT_24XX_I2C2_IRQ, }, | |
542 | }; | |
543 | ||
544 | static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { | |
545 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, | |
546 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, | |
547 | }; | |
548 | ||
549 | static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { | |
550 | &omap2430_l4_core__i2c2, | |
551 | }; | |
552 | ||
553 | static struct omap_hwmod omap2430_i2c2_hwmod = { | |
554 | .name = "i2c2", | |
555 | .mpu_irqs = i2c2_mpu_irqs, | |
556 | .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), | |
557 | .sdma_reqs = i2c2_sdma_reqs, | |
558 | .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), | |
559 | .main_clk = "i2chs2_fck", | |
560 | .prcm = { | |
561 | .omap2 = { | |
562 | .module_offs = CORE_MOD, | |
563 | .prcm_reg_id = 1, | |
564 | .module_bit = OMAP2430_EN_I2CHS2_SHIFT, | |
565 | .idlest_reg_id = 1, | |
566 | .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, | |
567 | }, | |
568 | }, | |
569 | .slaves = omap2430_i2c2_slaves, | |
570 | .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves), | |
571 | .class = &i2c_class, | |
572 | .dev_attr = &i2c2_dev_attr, | |
573 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
574 | }; | |
575 | ||
aeac0e44 VC |
576 | /* l4_wkup -> gpio1 */ |
577 | static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { | |
578 | { | |
579 | .pa_start = 0x4900C000, | |
580 | .pa_end = 0x4900C1ff, | |
581 | .flags = ADDR_TYPE_RT | |
582 | }, | |
583 | }; | |
584 | ||
585 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { | |
586 | .master = &omap2430_l4_wkup_hwmod, | |
587 | .slave = &omap2430_gpio1_hwmod, | |
588 | .clk = "gpios_ick", | |
589 | .addr = omap2430_gpio1_addr_space, | |
590 | .addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space), | |
591 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
592 | }; | |
593 | ||
594 | /* l4_wkup -> gpio2 */ | |
595 | static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { | |
596 | { | |
597 | .pa_start = 0x4900E000, | |
598 | .pa_end = 0x4900E1ff, | |
599 | .flags = ADDR_TYPE_RT | |
600 | }, | |
601 | }; | |
602 | ||
603 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { | |
604 | .master = &omap2430_l4_wkup_hwmod, | |
605 | .slave = &omap2430_gpio2_hwmod, | |
606 | .clk = "gpios_ick", | |
607 | .addr = omap2430_gpio2_addr_space, | |
608 | .addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space), | |
609 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
610 | }; | |
611 | ||
612 | /* l4_wkup -> gpio3 */ | |
613 | static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { | |
614 | { | |
615 | .pa_start = 0x49010000, | |
616 | .pa_end = 0x490101ff, | |
617 | .flags = ADDR_TYPE_RT | |
618 | }, | |
619 | }; | |
620 | ||
621 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { | |
622 | .master = &omap2430_l4_wkup_hwmod, | |
623 | .slave = &omap2430_gpio3_hwmod, | |
624 | .clk = "gpios_ick", | |
625 | .addr = omap2430_gpio3_addr_space, | |
626 | .addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space), | |
627 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
628 | }; | |
629 | ||
630 | /* l4_wkup -> gpio4 */ | |
631 | static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { | |
632 | { | |
633 | .pa_start = 0x49012000, | |
634 | .pa_end = 0x490121ff, | |
635 | .flags = ADDR_TYPE_RT | |
636 | }, | |
637 | }; | |
638 | ||
639 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { | |
640 | .master = &omap2430_l4_wkup_hwmod, | |
641 | .slave = &omap2430_gpio4_hwmod, | |
642 | .clk = "gpios_ick", | |
643 | .addr = omap2430_gpio4_addr_space, | |
644 | .addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space), | |
645 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
646 | }; | |
647 | ||
648 | /* l4_core -> gpio5 */ | |
649 | static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { | |
650 | { | |
651 | .pa_start = 0x480B6000, | |
652 | .pa_end = 0x480B61ff, | |
653 | .flags = ADDR_TYPE_RT | |
654 | }, | |
655 | }; | |
656 | ||
657 | static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { | |
658 | .master = &omap2430_l4_core_hwmod, | |
659 | .slave = &omap2430_gpio5_hwmod, | |
660 | .clk = "gpio5_ick", | |
661 | .addr = omap2430_gpio5_addr_space, | |
662 | .addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space), | |
663 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
664 | }; | |
665 | ||
666 | /* gpio dev_attr */ | |
667 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
668 | .bank_width = 32, | |
669 | .dbck_flag = false, | |
670 | }; | |
671 | ||
672 | static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = { | |
673 | .rev_offs = 0x0000, | |
674 | .sysc_offs = 0x0010, | |
675 | .syss_offs = 0x0014, | |
676 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
677 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
678 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
679 | .sysc_fields = &omap_hwmod_sysc_type1, | |
680 | }; | |
681 | ||
682 | /* | |
683 | * 'gpio' class | |
684 | * general purpose io module | |
685 | */ | |
686 | static struct omap_hwmod_class omap243x_gpio_hwmod_class = { | |
687 | .name = "gpio", | |
688 | .sysc = &omap243x_gpio_sysc, | |
689 | .rev = 0, | |
690 | }; | |
691 | ||
692 | /* gpio1 */ | |
693 | static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = { | |
694 | { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ | |
695 | }; | |
696 | ||
697 | static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { | |
698 | &omap2430_l4_wkup__gpio1, | |
699 | }; | |
700 | ||
701 | static struct omap_hwmod omap2430_gpio1_hwmod = { | |
702 | .name = "gpio1", | |
703 | .mpu_irqs = omap243x_gpio1_irqs, | |
704 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs), | |
705 | .main_clk = "gpios_fck", | |
706 | .prcm = { | |
707 | .omap2 = { | |
708 | .prcm_reg_id = 1, | |
709 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
710 | .module_offs = WKUP_MOD, | |
711 | .idlest_reg_id = 1, | |
712 | .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
713 | }, | |
714 | }, | |
715 | .slaves = omap2430_gpio1_slaves, | |
716 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), | |
717 | .class = &omap243x_gpio_hwmod_class, | |
718 | .dev_attr = &gpio_dev_attr, | |
719 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
720 | }; | |
721 | ||
722 | /* gpio2 */ | |
723 | static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = { | |
724 | { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ | |
725 | }; | |
726 | ||
727 | static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { | |
728 | &omap2430_l4_wkup__gpio2, | |
729 | }; | |
730 | ||
731 | static struct omap_hwmod omap2430_gpio2_hwmod = { | |
732 | .name = "gpio2", | |
733 | .mpu_irqs = omap243x_gpio2_irqs, | |
734 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs), | |
735 | .main_clk = "gpios_fck", | |
736 | .prcm = { | |
737 | .omap2 = { | |
738 | .prcm_reg_id = 1, | |
739 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
740 | .module_offs = WKUP_MOD, | |
741 | .idlest_reg_id = 1, | |
742 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
743 | }, | |
744 | }, | |
745 | .slaves = omap2430_gpio2_slaves, | |
746 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), | |
747 | .class = &omap243x_gpio_hwmod_class, | |
748 | .dev_attr = &gpio_dev_attr, | |
749 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
750 | }; | |
751 | ||
752 | /* gpio3 */ | |
753 | static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = { | |
754 | { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ | |
755 | }; | |
756 | ||
757 | static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { | |
758 | &omap2430_l4_wkup__gpio3, | |
759 | }; | |
760 | ||
761 | static struct omap_hwmod omap2430_gpio3_hwmod = { | |
762 | .name = "gpio3", | |
763 | .mpu_irqs = omap243x_gpio3_irqs, | |
764 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs), | |
765 | .main_clk = "gpios_fck", | |
766 | .prcm = { | |
767 | .omap2 = { | |
768 | .prcm_reg_id = 1, | |
769 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
770 | .module_offs = WKUP_MOD, | |
771 | .idlest_reg_id = 1, | |
772 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
773 | }, | |
774 | }, | |
775 | .slaves = omap2430_gpio3_slaves, | |
776 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), | |
777 | .class = &omap243x_gpio_hwmod_class, | |
778 | .dev_attr = &gpio_dev_attr, | |
779 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
780 | }; | |
781 | ||
782 | /* gpio4 */ | |
783 | static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = { | |
784 | { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ | |
785 | }; | |
786 | ||
787 | static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { | |
788 | &omap2430_l4_wkup__gpio4, | |
789 | }; | |
790 | ||
791 | static struct omap_hwmod omap2430_gpio4_hwmod = { | |
792 | .name = "gpio4", | |
793 | .mpu_irqs = omap243x_gpio4_irqs, | |
794 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs), | |
795 | .main_clk = "gpios_fck", | |
796 | .prcm = { | |
797 | .omap2 = { | |
798 | .prcm_reg_id = 1, | |
799 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
800 | .module_offs = WKUP_MOD, | |
801 | .idlest_reg_id = 1, | |
802 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
803 | }, | |
804 | }, | |
805 | .slaves = omap2430_gpio4_slaves, | |
806 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), | |
807 | .class = &omap243x_gpio_hwmod_class, | |
808 | .dev_attr = &gpio_dev_attr, | |
809 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
810 | }; | |
811 | ||
812 | /* gpio5 */ | |
813 | static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { | |
814 | { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ | |
815 | }; | |
816 | ||
817 | static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { | |
818 | &omap2430_l4_core__gpio5, | |
819 | }; | |
820 | ||
821 | static struct omap_hwmod omap2430_gpio5_hwmod = { | |
822 | .name = "gpio5", | |
823 | .mpu_irqs = omap243x_gpio5_irqs, | |
824 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs), | |
825 | .main_clk = "gpio5_fck", | |
826 | .prcm = { | |
827 | .omap2 = { | |
828 | .prcm_reg_id = 2, | |
829 | .module_bit = OMAP2430_EN_GPIO5_SHIFT, | |
830 | .module_offs = CORE_MOD, | |
831 | .idlest_reg_id = 2, | |
832 | .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, | |
833 | }, | |
834 | }, | |
835 | .slaves = omap2430_gpio5_slaves, | |
836 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), | |
837 | .class = &omap243x_gpio_hwmod_class, | |
838 | .dev_attr = &gpio_dev_attr, | |
839 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
840 | }; | |
841 | ||
82cbd1ae MK |
842 | /* dma_system */ |
843 | static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = { | |
844 | .rev_offs = 0x0000, | |
845 | .sysc_offs = 0x002c, | |
846 | .syss_offs = 0x0028, | |
847 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | | |
848 | SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | | |
849 | SYSC_HAS_AUTOIDLE), | |
850 | .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
851 | .sysc_fields = &omap_hwmod_sysc_type1, | |
852 | }; | |
853 | ||
854 | static struct omap_hwmod_class omap2430_dma_hwmod_class = { | |
855 | .name = "dma", | |
856 | .sysc = &omap2430_dma_sysc, | |
857 | }; | |
858 | ||
859 | /* dma attributes */ | |
860 | static struct omap_dma_dev_attr dma_dev_attr = { | |
861 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
862 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
863 | .lch_count = 32, | |
864 | }; | |
865 | ||
866 | static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = { | |
867 | { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ | |
868 | { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ | |
869 | { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ | |
870 | { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ | |
871 | }; | |
872 | ||
873 | static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = { | |
874 | { | |
875 | .pa_start = 0x48056000, | |
876 | .pa_end = 0x4a0560ff, | |
877 | .flags = ADDR_TYPE_RT | |
878 | }, | |
879 | }; | |
880 | ||
881 | /* dma_system -> L3 */ | |
882 | static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { | |
883 | .master = &omap2430_dma_system_hwmod, | |
884 | .slave = &omap2430_l3_main_hwmod, | |
885 | .clk = "core_l3_ck", | |
886 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
887 | }; | |
888 | ||
889 | /* dma_system master ports */ | |
890 | static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = { | |
891 | &omap2430_dma_system__l3, | |
892 | }; | |
893 | ||
894 | /* l4_core -> dma_system */ | |
895 | static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { | |
896 | .master = &omap2430_l4_core_hwmod, | |
897 | .slave = &omap2430_dma_system_hwmod, | |
898 | .clk = "sdma_ick", | |
899 | .addr = omap2430_dma_system_addrs, | |
900 | .addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs), | |
901 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
902 | }; | |
903 | ||
904 | /* dma_system slave ports */ | |
905 | static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = { | |
906 | &omap2430_l4_core__dma_system, | |
907 | }; | |
908 | ||
909 | static struct omap_hwmod omap2430_dma_system_hwmod = { | |
910 | .name = "dma", | |
911 | .class = &omap2430_dma_hwmod_class, | |
912 | .mpu_irqs = omap2430_dma_system_irqs, | |
913 | .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs), | |
914 | .main_clk = "core_l3_ck", | |
915 | .slaves = omap2430_dma_system_slaves, | |
916 | .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves), | |
917 | .masters = omap2430_dma_system_masters, | |
918 | .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters), | |
919 | .dev_attr = &dma_dev_attr, | |
920 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
921 | .flags = HWMOD_NO_IDLEST, | |
922 | }; | |
923 | ||
02bfc030 | 924 | static __initdata struct omap_hwmod *omap2430_hwmods[] = { |
4a7cf90a | 925 | &omap2430_l3_main_hwmod, |
02bfc030 PW |
926 | &omap2430_l4_core_hwmod, |
927 | &omap2430_l4_wkup_hwmod, | |
928 | &omap2430_mpu_hwmod, | |
08072acf | 929 | &omap2430_iva_hwmod, |
165e2161 | 930 | &omap2430_wd_timer2_hwmod, |
046465b7 KH |
931 | &omap2430_uart1_hwmod, |
932 | &omap2430_uart2_hwmod, | |
933 | &omap2430_uart3_hwmod, | |
2004290f PW |
934 | &omap2430_i2c1_hwmod, |
935 | &omap2430_i2c2_hwmod, | |
aeac0e44 VC |
936 | |
937 | /* gpio class */ | |
938 | &omap2430_gpio1_hwmod, | |
939 | &omap2430_gpio2_hwmod, | |
940 | &omap2430_gpio3_hwmod, | |
941 | &omap2430_gpio4_hwmod, | |
942 | &omap2430_gpio5_hwmod, | |
82cbd1ae MK |
943 | |
944 | /* dma_system class*/ | |
945 | &omap2430_dma_system_hwmod, | |
02bfc030 PW |
946 | NULL, |
947 | }; | |
948 | ||
7359154e PW |
949 | int __init omap2430_hwmod_init(void) |
950 | { | |
951 | return omap_hwmod_init(omap2430_hwmods); | |
952 | } |