Commit | Line | Data |
---|---|---|
02bfc030 | 1 | /* |
7359154e | 2 | * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips |
02bfc030 | 3 | * |
78183f3f | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
0a78c5c5 | 5 | * Copyright (C) 2012 Texas Instruments, Inc. |
02bfc030 PW |
6 | * Paul Walmsley |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * XXX handle crossbar/shared link difference for L3? | |
7359154e | 13 | * XXX these should be marked initdata for multi-OMAP kernels |
02bfc030 | 14 | */ |
ce491cf8 | 15 | #include <plat/omap_hwmod.h> |
02bfc030 | 16 | #include <mach/irqs.h> |
ce491cf8 TL |
17 | #include <plat/cpu.h> |
18 | #include <plat/dma.h> | |
046465b7 | 19 | #include <plat/serial.h> |
2004290f | 20 | #include <plat/i2c.h> |
aeac0e44 | 21 | #include <plat/gpio.h> |
37801b3d | 22 | #include <plat/mcbsp.h> |
7f904c78 | 23 | #include <plat/mcspi.h> |
b6b58229 | 24 | #include <plat/dmtimer.h> |
6ab8946f | 25 | #include <plat/mmc.h> |
de56dbb6 | 26 | #include <plat/l3_2xxx.h> |
02bfc030 | 27 | |
43b40992 PW |
28 | #include "omap_hwmod_common_data.h" |
29 | ||
02bfc030 | 30 | #include "prm-regbits-24xx.h" |
165e2161 | 31 | #include "cm-regbits-24xx.h" |
ff2516fb | 32 | #include "wd_timer.h" |
02bfc030 | 33 | |
7359154e PW |
34 | /* |
35 | * OMAP2430 hardware module integration data | |
36 | * | |
844a3b63 | 37 | * All of the data in this section should be autogeneratable from the |
7359154e PW |
38 | * TI hardware database or other technical documentation. Data that |
39 | * is driver-specific or driver-kernel integration-specific belongs | |
40 | * elsewhere. | |
41 | */ | |
42 | ||
844a3b63 PW |
43 | /* |
44 | * IP blocks | |
45 | */ | |
de56dbb6 | 46 | |
02bfc030 | 47 | /* L3 */ |
4a7cf90a | 48 | static struct omap_hwmod omap2430_l3_main_hwmod = { |
fa98347e | 49 | .name = "l3_main", |
43b40992 | 50 | .class = &l3_hwmod_class, |
2eb1875d | 51 | .flags = HWMOD_NO_IDLEST, |
02bfc030 PW |
52 | }; |
53 | ||
02bfc030 PW |
54 | /* L4 CORE */ |
55 | static struct omap_hwmod omap2430_l4_core_hwmod = { | |
fa98347e | 56 | .name = "l4_core", |
43b40992 | 57 | .class = &l4_hwmod_class, |
2eb1875d | 58 | .flags = HWMOD_NO_IDLEST, |
02bfc030 PW |
59 | }; |
60 | ||
02bfc030 PW |
61 | /* L4 WKUP */ |
62 | static struct omap_hwmod omap2430_l4_wkup_hwmod = { | |
fa98347e | 63 | .name = "l4_wkup", |
43b40992 | 64 | .class = &l4_hwmod_class, |
2eb1875d | 65 | .flags = HWMOD_NO_IDLEST, |
02bfc030 PW |
66 | }; |
67 | ||
02bfc030 PW |
68 | /* MPU */ |
69 | static struct omap_hwmod omap2430_mpu_hwmod = { | |
5c2c0296 | 70 | .name = "mpu", |
43b40992 | 71 | .class = &mpu_hwmod_class, |
50ebdac2 | 72 | .main_clk = "mpu_ck", |
02bfc030 PW |
73 | }; |
74 | ||
844a3b63 | 75 | /* IVA2 (IVA2) */ |
08072acf PW |
76 | static struct omap_hwmod omap2430_iva_hwmod = { |
77 | .name = "iva", | |
78 | .class = &iva_hwmod_class, | |
08072acf PW |
79 | }; |
80 | ||
c345c8b0 TKD |
81 | /* always-on timers dev attribute */ |
82 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
844a3b63 | 83 | .timer_capability = OMAP_TIMER_ALWON, |
c345c8b0 TKD |
84 | }; |
85 | ||
86 | /* pwm timers dev attribute */ | |
87 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
844a3b63 | 88 | .timer_capability = OMAP_TIMER_HAS_PWM, |
c345c8b0 TKD |
89 | }; |
90 | ||
b6b58229 | 91 | /* timer1 */ |
b6b58229 TG |
92 | static struct omap_hwmod omap2430_timer1_hwmod = { |
93 | .name = "timer1", | |
0d619a89 | 94 | .mpu_irqs = omap2_timer1_mpu_irqs, |
b6b58229 TG |
95 | .main_clk = "gpt1_fck", |
96 | .prcm = { | |
97 | .omap2 = { | |
98 | .prcm_reg_id = 1, | |
99 | .module_bit = OMAP24XX_EN_GPT1_SHIFT, | |
100 | .module_offs = WKUP_MOD, | |
101 | .idlest_reg_id = 1, | |
102 | .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, | |
103 | }, | |
104 | }, | |
c345c8b0 | 105 | .dev_attr = &capability_alwon_dev_attr, |
273b9465 | 106 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
107 | }; |
108 | ||
109 | /* timer2 */ | |
b6b58229 TG |
110 | static struct omap_hwmod omap2430_timer2_hwmod = { |
111 | .name = "timer2", | |
0d619a89 | 112 | .mpu_irqs = omap2_timer2_mpu_irqs, |
b6b58229 TG |
113 | .main_clk = "gpt2_fck", |
114 | .prcm = { | |
115 | .omap2 = { | |
116 | .prcm_reg_id = 1, | |
117 | .module_bit = OMAP24XX_EN_GPT2_SHIFT, | |
118 | .module_offs = CORE_MOD, | |
119 | .idlest_reg_id = 1, | |
120 | .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, | |
121 | }, | |
122 | }, | |
c345c8b0 | 123 | .dev_attr = &capability_alwon_dev_attr, |
273b9465 | 124 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
125 | }; |
126 | ||
127 | /* timer3 */ | |
b6b58229 TG |
128 | static struct omap_hwmod omap2430_timer3_hwmod = { |
129 | .name = "timer3", | |
0d619a89 | 130 | .mpu_irqs = omap2_timer3_mpu_irqs, |
b6b58229 TG |
131 | .main_clk = "gpt3_fck", |
132 | .prcm = { | |
133 | .omap2 = { | |
134 | .prcm_reg_id = 1, | |
135 | .module_bit = OMAP24XX_EN_GPT3_SHIFT, | |
136 | .module_offs = CORE_MOD, | |
137 | .idlest_reg_id = 1, | |
138 | .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, | |
139 | }, | |
140 | }, | |
c345c8b0 | 141 | .dev_attr = &capability_alwon_dev_attr, |
273b9465 | 142 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
143 | }; |
144 | ||
145 | /* timer4 */ | |
b6b58229 TG |
146 | static struct omap_hwmod omap2430_timer4_hwmod = { |
147 | .name = "timer4", | |
0d619a89 | 148 | .mpu_irqs = omap2_timer4_mpu_irqs, |
b6b58229 TG |
149 | .main_clk = "gpt4_fck", |
150 | .prcm = { | |
151 | .omap2 = { | |
152 | .prcm_reg_id = 1, | |
153 | .module_bit = OMAP24XX_EN_GPT4_SHIFT, | |
154 | .module_offs = CORE_MOD, | |
155 | .idlest_reg_id = 1, | |
156 | .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, | |
157 | }, | |
158 | }, | |
c345c8b0 | 159 | .dev_attr = &capability_alwon_dev_attr, |
273b9465 | 160 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
161 | }; |
162 | ||
163 | /* timer5 */ | |
b6b58229 TG |
164 | static struct omap_hwmod omap2430_timer5_hwmod = { |
165 | .name = "timer5", | |
0d619a89 | 166 | .mpu_irqs = omap2_timer5_mpu_irqs, |
b6b58229 TG |
167 | .main_clk = "gpt5_fck", |
168 | .prcm = { | |
169 | .omap2 = { | |
170 | .prcm_reg_id = 1, | |
171 | .module_bit = OMAP24XX_EN_GPT5_SHIFT, | |
172 | .module_offs = CORE_MOD, | |
173 | .idlest_reg_id = 1, | |
174 | .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, | |
175 | }, | |
176 | }, | |
c345c8b0 | 177 | .dev_attr = &capability_alwon_dev_attr, |
273b9465 | 178 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
179 | }; |
180 | ||
181 | /* timer6 */ | |
b6b58229 TG |
182 | static struct omap_hwmod omap2430_timer6_hwmod = { |
183 | .name = "timer6", | |
0d619a89 | 184 | .mpu_irqs = omap2_timer6_mpu_irqs, |
b6b58229 TG |
185 | .main_clk = "gpt6_fck", |
186 | .prcm = { | |
187 | .omap2 = { | |
188 | .prcm_reg_id = 1, | |
189 | .module_bit = OMAP24XX_EN_GPT6_SHIFT, | |
190 | .module_offs = CORE_MOD, | |
191 | .idlest_reg_id = 1, | |
192 | .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, | |
193 | }, | |
194 | }, | |
c345c8b0 | 195 | .dev_attr = &capability_alwon_dev_attr, |
273b9465 | 196 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
197 | }; |
198 | ||
199 | /* timer7 */ | |
b6b58229 TG |
200 | static struct omap_hwmod omap2430_timer7_hwmod = { |
201 | .name = "timer7", | |
0d619a89 | 202 | .mpu_irqs = omap2_timer7_mpu_irqs, |
b6b58229 TG |
203 | .main_clk = "gpt7_fck", |
204 | .prcm = { | |
205 | .omap2 = { | |
206 | .prcm_reg_id = 1, | |
207 | .module_bit = OMAP24XX_EN_GPT7_SHIFT, | |
208 | .module_offs = CORE_MOD, | |
209 | .idlest_reg_id = 1, | |
210 | .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, | |
211 | }, | |
212 | }, | |
c345c8b0 | 213 | .dev_attr = &capability_alwon_dev_attr, |
273b9465 | 214 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
215 | }; |
216 | ||
217 | /* timer8 */ | |
b6b58229 TG |
218 | static struct omap_hwmod omap2430_timer8_hwmod = { |
219 | .name = "timer8", | |
0d619a89 | 220 | .mpu_irqs = omap2_timer8_mpu_irqs, |
b6b58229 TG |
221 | .main_clk = "gpt8_fck", |
222 | .prcm = { | |
223 | .omap2 = { | |
224 | .prcm_reg_id = 1, | |
225 | .module_bit = OMAP24XX_EN_GPT8_SHIFT, | |
226 | .module_offs = CORE_MOD, | |
227 | .idlest_reg_id = 1, | |
228 | .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, | |
229 | }, | |
230 | }, | |
c345c8b0 | 231 | .dev_attr = &capability_alwon_dev_attr, |
273b9465 | 232 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
233 | }; |
234 | ||
235 | /* timer9 */ | |
b6b58229 TG |
236 | static struct omap_hwmod omap2430_timer9_hwmod = { |
237 | .name = "timer9", | |
0d619a89 | 238 | .mpu_irqs = omap2_timer9_mpu_irqs, |
b6b58229 TG |
239 | .main_clk = "gpt9_fck", |
240 | .prcm = { | |
241 | .omap2 = { | |
242 | .prcm_reg_id = 1, | |
243 | .module_bit = OMAP24XX_EN_GPT9_SHIFT, | |
244 | .module_offs = CORE_MOD, | |
245 | .idlest_reg_id = 1, | |
246 | .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, | |
247 | }, | |
248 | }, | |
c345c8b0 | 249 | .dev_attr = &capability_pwm_dev_attr, |
273b9465 | 250 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
251 | }; |
252 | ||
253 | /* timer10 */ | |
b6b58229 TG |
254 | static struct omap_hwmod omap2430_timer10_hwmod = { |
255 | .name = "timer10", | |
0d619a89 | 256 | .mpu_irqs = omap2_timer10_mpu_irqs, |
b6b58229 TG |
257 | .main_clk = "gpt10_fck", |
258 | .prcm = { | |
259 | .omap2 = { | |
260 | .prcm_reg_id = 1, | |
261 | .module_bit = OMAP24XX_EN_GPT10_SHIFT, | |
262 | .module_offs = CORE_MOD, | |
263 | .idlest_reg_id = 1, | |
264 | .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, | |
265 | }, | |
266 | }, | |
c345c8b0 | 267 | .dev_attr = &capability_pwm_dev_attr, |
273b9465 | 268 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
269 | }; |
270 | ||
271 | /* timer11 */ | |
b6b58229 TG |
272 | static struct omap_hwmod omap2430_timer11_hwmod = { |
273 | .name = "timer11", | |
0d619a89 | 274 | .mpu_irqs = omap2_timer11_mpu_irqs, |
b6b58229 TG |
275 | .main_clk = "gpt11_fck", |
276 | .prcm = { | |
277 | .omap2 = { | |
278 | .prcm_reg_id = 1, | |
279 | .module_bit = OMAP24XX_EN_GPT11_SHIFT, | |
280 | .module_offs = CORE_MOD, | |
281 | .idlest_reg_id = 1, | |
282 | .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, | |
283 | }, | |
284 | }, | |
c345c8b0 | 285 | .dev_attr = &capability_pwm_dev_attr, |
273b9465 | 286 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
287 | }; |
288 | ||
289 | /* timer12 */ | |
b6b58229 TG |
290 | static struct omap_hwmod omap2430_timer12_hwmod = { |
291 | .name = "timer12", | |
0d619a89 | 292 | .mpu_irqs = omap2xxx_timer12_mpu_irqs, |
b6b58229 TG |
293 | .main_clk = "gpt12_fck", |
294 | .prcm = { | |
295 | .omap2 = { | |
296 | .prcm_reg_id = 1, | |
297 | .module_bit = OMAP24XX_EN_GPT12_SHIFT, | |
298 | .module_offs = CORE_MOD, | |
299 | .idlest_reg_id = 1, | |
300 | .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, | |
301 | }, | |
302 | }, | |
c345c8b0 | 303 | .dev_attr = &capability_pwm_dev_attr, |
273b9465 | 304 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
305 | }; |
306 | ||
165e2161 VC |
307 | static struct omap_hwmod omap2430_wd_timer2_hwmod = { |
308 | .name = "wd_timer2", | |
273b9465 | 309 | .class = &omap2xxx_wd_timer_hwmod_class, |
165e2161 VC |
310 | .main_clk = "mpu_wdt_fck", |
311 | .prcm = { | |
312 | .omap2 = { | |
313 | .prcm_reg_id = 1, | |
314 | .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
315 | .module_offs = WKUP_MOD, | |
316 | .idlest_reg_id = 1, | |
317 | .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, | |
318 | }, | |
319 | }, | |
165e2161 VC |
320 | }; |
321 | ||
046465b7 | 322 | /* UART1 */ |
046465b7 KH |
323 | static struct omap_hwmod omap2430_uart1_hwmod = { |
324 | .name = "uart1", | |
0d619a89 | 325 | .mpu_irqs = omap2_uart1_mpu_irqs, |
d826ebfa | 326 | .sdma_reqs = omap2_uart1_sdma_reqs, |
046465b7 KH |
327 | .main_clk = "uart1_fck", |
328 | .prcm = { | |
329 | .omap2 = { | |
330 | .module_offs = CORE_MOD, | |
331 | .prcm_reg_id = 1, | |
332 | .module_bit = OMAP24XX_EN_UART1_SHIFT, | |
333 | .idlest_reg_id = 1, | |
334 | .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, | |
335 | }, | |
336 | }, | |
273b9465 | 337 | .class = &omap2_uart_class, |
046465b7 KH |
338 | }; |
339 | ||
340 | /* UART2 */ | |
046465b7 KH |
341 | static struct omap_hwmod omap2430_uart2_hwmod = { |
342 | .name = "uart2", | |
0d619a89 | 343 | .mpu_irqs = omap2_uart2_mpu_irqs, |
d826ebfa | 344 | .sdma_reqs = omap2_uart2_sdma_reqs, |
046465b7 KH |
345 | .main_clk = "uart2_fck", |
346 | .prcm = { | |
347 | .omap2 = { | |
348 | .module_offs = CORE_MOD, | |
349 | .prcm_reg_id = 1, | |
350 | .module_bit = OMAP24XX_EN_UART2_SHIFT, | |
351 | .idlest_reg_id = 1, | |
352 | .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, | |
353 | }, | |
354 | }, | |
273b9465 | 355 | .class = &omap2_uart_class, |
046465b7 KH |
356 | }; |
357 | ||
358 | /* UART3 */ | |
046465b7 KH |
359 | static struct omap_hwmod omap2430_uart3_hwmod = { |
360 | .name = "uart3", | |
0d619a89 | 361 | .mpu_irqs = omap2_uart3_mpu_irqs, |
d826ebfa | 362 | .sdma_reqs = omap2_uart3_sdma_reqs, |
046465b7 KH |
363 | .main_clk = "uart3_fck", |
364 | .prcm = { | |
365 | .omap2 = { | |
366 | .module_offs = CORE_MOD, | |
367 | .prcm_reg_id = 2, | |
368 | .module_bit = OMAP24XX_EN_UART3_SHIFT, | |
369 | .idlest_reg_id = 2, | |
370 | .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, | |
371 | }, | |
372 | }, | |
273b9465 | 373 | .class = &omap2_uart_class, |
046465b7 KH |
374 | }; |
375 | ||
de56dbb6 | 376 | /* dss */ |
de56dbb6 | 377 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { |
1258ea59 TV |
378 | /* |
379 | * The DSS HW needs all DSS clocks enabled during reset. The dss_core | |
380 | * driver does not use these clocks. | |
381 | */ | |
de56dbb6 SG |
382 | { .role = "tv_clk", .clk = "dss_54m_fck" }, |
383 | { .role = "sys_clk", .clk = "dss2_fck" }, | |
384 | }; | |
385 | ||
386 | static struct omap_hwmod omap2430_dss_core_hwmod = { | |
387 | .name = "dss_core", | |
273b9465 | 388 | .class = &omap2_dss_hwmod_class, |
de56dbb6 | 389 | .main_clk = "dss1_fck", /* instead of dss_fck */ |
d826ebfa | 390 | .sdma_reqs = omap2xxx_dss_sdma_chs, |
de56dbb6 SG |
391 | .prcm = { |
392 | .omap2 = { | |
393 | .prcm_reg_id = 1, | |
394 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
395 | .module_offs = CORE_MOD, | |
396 | .idlest_reg_id = 1, | |
397 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, | |
398 | }, | |
399 | }, | |
400 | .opt_clks = dss_opt_clks, | |
401 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
1258ea59 | 402 | .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
de56dbb6 SG |
403 | }; |
404 | ||
de56dbb6 SG |
405 | static struct omap_hwmod omap2430_dss_dispc_hwmod = { |
406 | .name = "dss_dispc", | |
273b9465 | 407 | .class = &omap2_dispc_hwmod_class, |
0d619a89 | 408 | .mpu_irqs = omap2_dispc_irqs, |
de56dbb6 SG |
409 | .main_clk = "dss1_fck", |
410 | .prcm = { | |
411 | .omap2 = { | |
412 | .prcm_reg_id = 1, | |
413 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
414 | .module_offs = CORE_MOD, | |
415 | .idlest_reg_id = 1, | |
416 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, | |
417 | }, | |
418 | }, | |
de56dbb6 | 419 | .flags = HWMOD_NO_IDLEST, |
b923d40d | 420 | .dev_attr = &omap2_3_dss_dispc_dev_attr |
de56dbb6 SG |
421 | }; |
422 | ||
b8ac10d8 TV |
423 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
424 | { .role = "ick", .clk = "dss_ick" }, | |
425 | }; | |
426 | ||
de56dbb6 SG |
427 | static struct omap_hwmod omap2430_dss_rfbi_hwmod = { |
428 | .name = "dss_rfbi", | |
273b9465 | 429 | .class = &omap2_rfbi_hwmod_class, |
de56dbb6 SG |
430 | .main_clk = "dss1_fck", |
431 | .prcm = { | |
432 | .omap2 = { | |
433 | .prcm_reg_id = 1, | |
434 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
435 | .module_offs = CORE_MOD, | |
436 | }, | |
437 | }, | |
b8ac10d8 TV |
438 | .opt_clks = dss_rfbi_opt_clks, |
439 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
de56dbb6 SG |
440 | .flags = HWMOD_NO_IDLEST, |
441 | }; | |
442 | ||
de56dbb6 SG |
443 | static struct omap_hwmod omap2430_dss_venc_hwmod = { |
444 | .name = "dss_venc", | |
273b9465 | 445 | .class = &omap2_venc_hwmod_class, |
b8ac10d8 | 446 | .main_clk = "dss_54m_fck", |
de56dbb6 SG |
447 | .prcm = { |
448 | .omap2 = { | |
449 | .prcm_reg_id = 1, | |
450 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
451 | .module_offs = CORE_MOD, | |
452 | }, | |
453 | }, | |
de56dbb6 SG |
454 | .flags = HWMOD_NO_IDLEST, |
455 | }; | |
456 | ||
2004290f PW |
457 | /* I2C common */ |
458 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
459 | .rev_offs = 0x00, | |
460 | .sysc_offs = 0x20, | |
461 | .syss_offs = 0x10, | |
2d403fe0 PW |
462 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
463 | SYSS_HAS_RESET_STATUS), | |
2004290f PW |
464 | .sysc_fields = &omap_hwmod_sysc_type1, |
465 | }; | |
466 | ||
467 | static struct omap_hwmod_class i2c_class = { | |
468 | .name = "i2c", | |
469 | .sysc = &i2c_sysc, | |
db791a75 | 470 | .rev = OMAP_I2C_IP_VERSION_1, |
6d3c55fd | 471 | .reset = &omap_i2c_reset, |
2004290f PW |
472 | }; |
473 | ||
50ebb777 | 474 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
2004290f | 475 | .fifo_depth = 8, /* bytes */ |
4d4441a6 AG |
476 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | |
477 | OMAP_I2C_FLAG_BUS_SHIFT_2 | | |
478 | OMAP_I2C_FLAG_FORCE_19200_INT_CLK, | |
2004290f PW |
479 | }; |
480 | ||
50ebb777 | 481 | /* I2C1 */ |
2004290f PW |
482 | static struct omap_hwmod omap2430_i2c1_hwmod = { |
483 | .name = "i2c1", | |
3e600522 | 484 | .flags = HWMOD_16BIT_REG, |
0d619a89 | 485 | .mpu_irqs = omap2_i2c1_mpu_irqs, |
d826ebfa | 486 | .sdma_reqs = omap2_i2c1_sdma_reqs, |
2004290f PW |
487 | .main_clk = "i2chs1_fck", |
488 | .prcm = { | |
489 | .omap2 = { | |
490 | /* | |
491 | * NOTE: The CM_FCLKEN* and CM_ICLKEN* for | |
492 | * I2CHS IP's do not follow the usual pattern. | |
493 | * prcm_reg_id alone cannot be used to program | |
494 | * the iclk and fclk. Needs to be handled using | |
25985edc | 495 | * additional flags when clk handling is moved |
2004290f PW |
496 | * to hwmod framework. |
497 | */ | |
498 | .module_offs = CORE_MOD, | |
499 | .prcm_reg_id = 1, | |
500 | .module_bit = OMAP2430_EN_I2CHS1_SHIFT, | |
501 | .idlest_reg_id = 1, | |
502 | .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, | |
503 | }, | |
504 | }, | |
2004290f | 505 | .class = &i2c_class, |
50ebb777 | 506 | .dev_attr = &i2c_dev_attr, |
2004290f PW |
507 | }; |
508 | ||
509 | /* I2C2 */ | |
2004290f PW |
510 | static struct omap_hwmod omap2430_i2c2_hwmod = { |
511 | .name = "i2c2", | |
3e600522 | 512 | .flags = HWMOD_16BIT_REG, |
0d619a89 | 513 | .mpu_irqs = omap2_i2c2_mpu_irqs, |
d826ebfa | 514 | .sdma_reqs = omap2_i2c2_sdma_reqs, |
2004290f PW |
515 | .main_clk = "i2chs2_fck", |
516 | .prcm = { | |
517 | .omap2 = { | |
518 | .module_offs = CORE_MOD, | |
519 | .prcm_reg_id = 1, | |
520 | .module_bit = OMAP2430_EN_I2CHS2_SHIFT, | |
521 | .idlest_reg_id = 1, | |
522 | .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, | |
523 | }, | |
524 | }, | |
2004290f | 525 | .class = &i2c_class, |
50ebb777 | 526 | .dev_attr = &i2c_dev_attr, |
2004290f PW |
527 | }; |
528 | ||
aeac0e44 VC |
529 | /* gpio dev_attr */ |
530 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
531 | .bank_width = 32, | |
532 | .dbck_flag = false, | |
533 | }; | |
534 | ||
aeac0e44 | 535 | /* gpio1 */ |
aeac0e44 VC |
536 | static struct omap_hwmod omap2430_gpio1_hwmod = { |
537 | .name = "gpio1", | |
f95440ca | 538 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 539 | .mpu_irqs = omap2_gpio1_irqs, |
aeac0e44 VC |
540 | .main_clk = "gpios_fck", |
541 | .prcm = { | |
542 | .omap2 = { | |
543 | .prcm_reg_id = 1, | |
544 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
545 | .module_offs = WKUP_MOD, | |
546 | .idlest_reg_id = 1, | |
547 | .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
548 | }, | |
549 | }, | |
273b9465 | 550 | .class = &omap2xxx_gpio_hwmod_class, |
aeac0e44 | 551 | .dev_attr = &gpio_dev_attr, |
aeac0e44 VC |
552 | }; |
553 | ||
554 | /* gpio2 */ | |
aeac0e44 VC |
555 | static struct omap_hwmod omap2430_gpio2_hwmod = { |
556 | .name = "gpio2", | |
f95440ca | 557 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 558 | .mpu_irqs = omap2_gpio2_irqs, |
aeac0e44 VC |
559 | .main_clk = "gpios_fck", |
560 | .prcm = { | |
561 | .omap2 = { | |
562 | .prcm_reg_id = 1, | |
563 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
564 | .module_offs = WKUP_MOD, | |
565 | .idlest_reg_id = 1, | |
566 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
567 | }, | |
568 | }, | |
273b9465 | 569 | .class = &omap2xxx_gpio_hwmod_class, |
aeac0e44 | 570 | .dev_attr = &gpio_dev_attr, |
aeac0e44 VC |
571 | }; |
572 | ||
573 | /* gpio3 */ | |
aeac0e44 VC |
574 | static struct omap_hwmod omap2430_gpio3_hwmod = { |
575 | .name = "gpio3", | |
f95440ca | 576 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 577 | .mpu_irqs = omap2_gpio3_irqs, |
aeac0e44 VC |
578 | .main_clk = "gpios_fck", |
579 | .prcm = { | |
580 | .omap2 = { | |
581 | .prcm_reg_id = 1, | |
582 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
583 | .module_offs = WKUP_MOD, | |
584 | .idlest_reg_id = 1, | |
585 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
586 | }, | |
587 | }, | |
273b9465 | 588 | .class = &omap2xxx_gpio_hwmod_class, |
aeac0e44 | 589 | .dev_attr = &gpio_dev_attr, |
aeac0e44 VC |
590 | }; |
591 | ||
592 | /* gpio4 */ | |
aeac0e44 VC |
593 | static struct omap_hwmod omap2430_gpio4_hwmod = { |
594 | .name = "gpio4", | |
f95440ca | 595 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 596 | .mpu_irqs = omap2_gpio4_irqs, |
aeac0e44 VC |
597 | .main_clk = "gpios_fck", |
598 | .prcm = { | |
599 | .omap2 = { | |
600 | .prcm_reg_id = 1, | |
601 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
602 | .module_offs = WKUP_MOD, | |
603 | .idlest_reg_id = 1, | |
604 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
605 | }, | |
606 | }, | |
273b9465 | 607 | .class = &omap2xxx_gpio_hwmod_class, |
aeac0e44 | 608 | .dev_attr = &gpio_dev_attr, |
aeac0e44 VC |
609 | }; |
610 | ||
611 | /* gpio5 */ | |
612 | static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { | |
613 | { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ | |
212738a4 | 614 | { .irq = -1 } |
aeac0e44 VC |
615 | }; |
616 | ||
aeac0e44 VC |
617 | static struct omap_hwmod omap2430_gpio5_hwmod = { |
618 | .name = "gpio5", | |
f95440ca | 619 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
aeac0e44 | 620 | .mpu_irqs = omap243x_gpio5_irqs, |
aeac0e44 VC |
621 | .main_clk = "gpio5_fck", |
622 | .prcm = { | |
623 | .omap2 = { | |
624 | .prcm_reg_id = 2, | |
625 | .module_bit = OMAP2430_EN_GPIO5_SHIFT, | |
626 | .module_offs = CORE_MOD, | |
627 | .idlest_reg_id = 2, | |
628 | .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, | |
629 | }, | |
630 | }, | |
273b9465 | 631 | .class = &omap2xxx_gpio_hwmod_class, |
aeac0e44 | 632 | .dev_attr = &gpio_dev_attr, |
aeac0e44 VC |
633 | }; |
634 | ||
82cbd1ae MK |
635 | /* dma attributes */ |
636 | static struct omap_dma_dev_attr dma_dev_attr = { | |
637 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
638 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
639 | .lch_count = 32, | |
640 | }; | |
641 | ||
82cbd1ae MK |
642 | static struct omap_hwmod omap2430_dma_system_hwmod = { |
643 | .name = "dma", | |
273b9465 | 644 | .class = &omap2xxx_dma_hwmod_class, |
0d619a89 | 645 | .mpu_irqs = omap2_dma_system_irqs, |
82cbd1ae | 646 | .main_clk = "core_l3_ck", |
82cbd1ae | 647 | .dev_attr = &dma_dev_attr, |
82cbd1ae MK |
648 | .flags = HWMOD_NO_IDLEST, |
649 | }; | |
650 | ||
fca1ab55 | 651 | /* mailbox */ |
fca1ab55 ORL |
652 | static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { |
653 | { .irq = 26 }, | |
212738a4 | 654 | { .irq = -1 } |
fca1ab55 ORL |
655 | }; |
656 | ||
fca1ab55 ORL |
657 | static struct omap_hwmod omap2430_mailbox_hwmod = { |
658 | .name = "mailbox", | |
273b9465 | 659 | .class = &omap2xxx_mailbox_hwmod_class, |
fca1ab55 | 660 | .mpu_irqs = omap2430_mailbox_irqs, |
fca1ab55 ORL |
661 | .main_clk = "mailboxes_ick", |
662 | .prcm = { | |
663 | .omap2 = { | |
664 | .prcm_reg_id = 1, | |
665 | .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | |
666 | .module_offs = CORE_MOD, | |
667 | .idlest_reg_id = 1, | |
668 | .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, | |
669 | }, | |
670 | }, | |
fca1ab55 ORL |
671 | }; |
672 | ||
7f904c78 | 673 | /* mcspi1 */ |
7f904c78 C |
674 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { |
675 | .num_chipselect = 4, | |
676 | }; | |
677 | ||
678 | static struct omap_hwmod omap2430_mcspi1_hwmod = { | |
bec93811 | 679 | .name = "mcspi1", |
0d619a89 | 680 | .mpu_irqs = omap2_mcspi1_mpu_irqs, |
d826ebfa | 681 | .sdma_reqs = omap2_mcspi1_sdma_reqs, |
7f904c78 C |
682 | .main_clk = "mcspi1_fck", |
683 | .prcm = { | |
684 | .omap2 = { | |
685 | .module_offs = CORE_MOD, | |
686 | .prcm_reg_id = 1, | |
687 | .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, | |
688 | .idlest_reg_id = 1, | |
689 | .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, | |
690 | }, | |
691 | }, | |
273b9465 PW |
692 | .class = &omap2xxx_mcspi_class, |
693 | .dev_attr = &omap_mcspi1_dev_attr, | |
7f904c78 C |
694 | }; |
695 | ||
696 | /* mcspi2 */ | |
7f904c78 C |
697 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { |
698 | .num_chipselect = 2, | |
699 | }; | |
700 | ||
701 | static struct omap_hwmod omap2430_mcspi2_hwmod = { | |
bec93811 | 702 | .name = "mcspi2", |
0d619a89 | 703 | .mpu_irqs = omap2_mcspi2_mpu_irqs, |
d826ebfa | 704 | .sdma_reqs = omap2_mcspi2_sdma_reqs, |
7f904c78 C |
705 | .main_clk = "mcspi2_fck", |
706 | .prcm = { | |
707 | .omap2 = { | |
708 | .module_offs = CORE_MOD, | |
709 | .prcm_reg_id = 1, | |
710 | .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, | |
711 | .idlest_reg_id = 1, | |
712 | .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, | |
713 | }, | |
714 | }, | |
273b9465 PW |
715 | .class = &omap2xxx_mcspi_class, |
716 | .dev_attr = &omap_mcspi2_dev_attr, | |
7f904c78 C |
717 | }; |
718 | ||
719 | /* mcspi3 */ | |
720 | static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { | |
721 | { .irq = 91 }, | |
212738a4 | 722 | { .irq = -1 } |
7f904c78 C |
723 | }; |
724 | ||
725 | static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { | |
726 | { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */ | |
727 | { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */ | |
728 | { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */ | |
729 | { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */ | |
bc614958 | 730 | { .dma_req = -1 } |
7f904c78 C |
731 | }; |
732 | ||
7f904c78 C |
733 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { |
734 | .num_chipselect = 2, | |
735 | }; | |
736 | ||
737 | static struct omap_hwmod omap2430_mcspi3_hwmod = { | |
bec93811 | 738 | .name = "mcspi3", |
7f904c78 | 739 | .mpu_irqs = omap2430_mcspi3_mpu_irqs, |
7f904c78 | 740 | .sdma_reqs = omap2430_mcspi3_sdma_reqs, |
7f904c78 C |
741 | .main_clk = "mcspi3_fck", |
742 | .prcm = { | |
743 | .omap2 = { | |
744 | .module_offs = CORE_MOD, | |
745 | .prcm_reg_id = 2, | |
746 | .module_bit = OMAP2430_EN_MCSPI3_SHIFT, | |
747 | .idlest_reg_id = 2, | |
748 | .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, | |
749 | }, | |
750 | }, | |
273b9465 PW |
751 | .class = &omap2xxx_mcspi_class, |
752 | .dev_attr = &omap_mcspi3_dev_attr, | |
7f904c78 C |
753 | }; |
754 | ||
844a3b63 | 755 | /* usbhsotg */ |
44d02acf HH |
756 | static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { |
757 | .rev_offs = 0x0400, | |
758 | .sysc_offs = 0x0404, | |
759 | .syss_offs = 0x0408, | |
760 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| | |
761 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
762 | SYSC_HAS_AUTOIDLE), | |
763 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
764 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
765 | .sysc_fields = &omap_hwmod_sysc_type1, | |
766 | }; | |
767 | ||
768 | static struct omap_hwmod_class usbotg_class = { | |
769 | .name = "usbotg", | |
770 | .sysc = &omap2430_usbhsotg_sysc, | |
771 | }; | |
772 | ||
773 | /* usb_otg_hs */ | |
774 | static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { | |
775 | ||
776 | { .name = "mc", .irq = 92 }, | |
777 | { .name = "dma", .irq = 93 }, | |
212738a4 | 778 | { .irq = -1 } |
44d02acf HH |
779 | }; |
780 | ||
781 | static struct omap_hwmod omap2430_usbhsotg_hwmod = { | |
782 | .name = "usb_otg_hs", | |
783 | .mpu_irqs = omap2430_usbhsotg_mpu_irqs, | |
44d02acf HH |
784 | .main_clk = "usbhs_ick", |
785 | .prcm = { | |
786 | .omap2 = { | |
787 | .prcm_reg_id = 1, | |
788 | .module_bit = OMAP2430_EN_USBHS_MASK, | |
789 | .module_offs = CORE_MOD, | |
790 | .idlest_reg_id = 1, | |
791 | .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, | |
792 | }, | |
793 | }, | |
44d02acf HH |
794 | .class = &usbotg_class, |
795 | /* | |
796 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially | |
797 | * broken when autoidle is enabled | |
798 | * workaround is to disable the autoidle bit at module level. | |
799 | */ | |
800 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | |
801 | | HWMOD_SWSUP_MSTANDBY, | |
44d02acf HH |
802 | }; |
803 | ||
37801b3d C |
804 | /* |
805 | * 'mcbsp' class | |
806 | * multi channel buffered serial port controller | |
807 | */ | |
808 | ||
809 | static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = { | |
810 | .rev_offs = 0x007C, | |
811 | .sysc_offs = 0x008C, | |
812 | .sysc_flags = (SYSC_HAS_SOFTRESET), | |
813 | .sysc_fields = &omap_hwmod_sysc_type1, | |
814 | }; | |
815 | ||
816 | static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { | |
817 | .name = "mcbsp", | |
818 | .sysc = &omap2430_mcbsp_sysc, | |
819 | .rev = MCBSP_CONFIG_TYPE2, | |
820 | }; | |
04aa67de | 821 | |
37801b3d C |
822 | /* mcbsp1 */ |
823 | static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { | |
824 | { .name = "tx", .irq = 59 }, | |
825 | { .name = "rx", .irq = 60 }, | |
826 | { .name = "ovr", .irq = 61 }, | |
827 | { .name = "common", .irq = 64 }, | |
212738a4 | 828 | { .irq = -1 } |
37801b3d C |
829 | }; |
830 | ||
37801b3d C |
831 | static struct omap_hwmod omap2430_mcbsp1_hwmod = { |
832 | .name = "mcbsp1", | |
833 | .class = &omap2430_mcbsp_hwmod_class, | |
834 | .mpu_irqs = omap2430_mcbsp1_irqs, | |
d826ebfa | 835 | .sdma_reqs = omap2_mcbsp1_sdma_reqs, |
37801b3d C |
836 | .main_clk = "mcbsp1_fck", |
837 | .prcm = { | |
838 | .omap2 = { | |
839 | .prcm_reg_id = 1, | |
840 | .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, | |
841 | .module_offs = CORE_MOD, | |
842 | .idlest_reg_id = 1, | |
843 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, | |
844 | }, | |
845 | }, | |
37801b3d C |
846 | }; |
847 | ||
848 | /* mcbsp2 */ | |
849 | static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { | |
850 | { .name = "tx", .irq = 62 }, | |
851 | { .name = "rx", .irq = 63 }, | |
852 | { .name = "common", .irq = 16 }, | |
212738a4 | 853 | { .irq = -1 } |
37801b3d C |
854 | }; |
855 | ||
37801b3d C |
856 | static struct omap_hwmod omap2430_mcbsp2_hwmod = { |
857 | .name = "mcbsp2", | |
858 | .class = &omap2430_mcbsp_hwmod_class, | |
859 | .mpu_irqs = omap2430_mcbsp2_irqs, | |
d826ebfa | 860 | .sdma_reqs = omap2_mcbsp2_sdma_reqs, |
37801b3d C |
861 | .main_clk = "mcbsp2_fck", |
862 | .prcm = { | |
863 | .omap2 = { | |
864 | .prcm_reg_id = 1, | |
865 | .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, | |
866 | .module_offs = CORE_MOD, | |
867 | .idlest_reg_id = 1, | |
868 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, | |
869 | }, | |
870 | }, | |
37801b3d C |
871 | }; |
872 | ||
873 | /* mcbsp3 */ | |
874 | static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { | |
875 | { .name = "tx", .irq = 89 }, | |
876 | { .name = "rx", .irq = 90 }, | |
877 | { .name = "common", .irq = 17 }, | |
212738a4 | 878 | { .irq = -1 } |
37801b3d C |
879 | }; |
880 | ||
37801b3d C |
881 | static struct omap_hwmod omap2430_mcbsp3_hwmod = { |
882 | .name = "mcbsp3", | |
883 | .class = &omap2430_mcbsp_hwmod_class, | |
884 | .mpu_irqs = omap2430_mcbsp3_irqs, | |
d826ebfa | 885 | .sdma_reqs = omap2_mcbsp3_sdma_reqs, |
37801b3d C |
886 | .main_clk = "mcbsp3_fck", |
887 | .prcm = { | |
888 | .omap2 = { | |
889 | .prcm_reg_id = 1, | |
890 | .module_bit = OMAP2430_EN_MCBSP3_SHIFT, | |
891 | .module_offs = CORE_MOD, | |
892 | .idlest_reg_id = 2, | |
893 | .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, | |
894 | }, | |
895 | }, | |
37801b3d C |
896 | }; |
897 | ||
898 | /* mcbsp4 */ | |
899 | static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = { | |
900 | { .name = "tx", .irq = 54 }, | |
901 | { .name = "rx", .irq = 55 }, | |
902 | { .name = "common", .irq = 18 }, | |
212738a4 | 903 | { .irq = -1 } |
37801b3d C |
904 | }; |
905 | ||
906 | static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { | |
907 | { .name = "rx", .dma_req = 20 }, | |
908 | { .name = "tx", .dma_req = 19 }, | |
bc614958 | 909 | { .dma_req = -1 } |
37801b3d C |
910 | }; |
911 | ||
37801b3d C |
912 | static struct omap_hwmod omap2430_mcbsp4_hwmod = { |
913 | .name = "mcbsp4", | |
914 | .class = &omap2430_mcbsp_hwmod_class, | |
915 | .mpu_irqs = omap2430_mcbsp4_irqs, | |
37801b3d | 916 | .sdma_reqs = omap2430_mcbsp4_sdma_chs, |
37801b3d C |
917 | .main_clk = "mcbsp4_fck", |
918 | .prcm = { | |
919 | .omap2 = { | |
920 | .prcm_reg_id = 1, | |
921 | .module_bit = OMAP2430_EN_MCBSP4_SHIFT, | |
922 | .module_offs = CORE_MOD, | |
923 | .idlest_reg_id = 2, | |
924 | .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, | |
925 | }, | |
926 | }, | |
37801b3d C |
927 | }; |
928 | ||
929 | /* mcbsp5 */ | |
930 | static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = { | |
931 | { .name = "tx", .irq = 81 }, | |
932 | { .name = "rx", .irq = 82 }, | |
933 | { .name = "common", .irq = 19 }, | |
212738a4 | 934 | { .irq = -1 } |
37801b3d C |
935 | }; |
936 | ||
937 | static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { | |
938 | { .name = "rx", .dma_req = 22 }, | |
939 | { .name = "tx", .dma_req = 21 }, | |
bc614958 | 940 | { .dma_req = -1 } |
37801b3d C |
941 | }; |
942 | ||
37801b3d C |
943 | static struct omap_hwmod omap2430_mcbsp5_hwmod = { |
944 | .name = "mcbsp5", | |
945 | .class = &omap2430_mcbsp_hwmod_class, | |
946 | .mpu_irqs = omap2430_mcbsp5_irqs, | |
37801b3d | 947 | .sdma_reqs = omap2430_mcbsp5_sdma_chs, |
37801b3d C |
948 | .main_clk = "mcbsp5_fck", |
949 | .prcm = { | |
950 | .omap2 = { | |
951 | .prcm_reg_id = 1, | |
952 | .module_bit = OMAP2430_EN_MCBSP5_SHIFT, | |
953 | .module_offs = CORE_MOD, | |
954 | .idlest_reg_id = 2, | |
955 | .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, | |
956 | }, | |
957 | }, | |
37801b3d | 958 | }; |
04aa67de | 959 | |
bce06f37 | 960 | /* MMC/SD/SDIO common */ |
bce06f37 PW |
961 | static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { |
962 | .rev_offs = 0x1fc, | |
963 | .sysc_offs = 0x10, | |
964 | .syss_offs = 0x14, | |
965 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
966 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
967 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
968 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
969 | .sysc_fields = &omap_hwmod_sysc_type1, | |
970 | }; | |
971 | ||
972 | static struct omap_hwmod_class omap2430_mmc_class = { | |
973 | .name = "mmc", | |
974 | .sysc = &omap2430_mmc_sysc, | |
975 | }; | |
976 | ||
977 | /* MMC/SD/SDIO1 */ | |
bce06f37 PW |
978 | static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { |
979 | { .irq = 83 }, | |
212738a4 | 980 | { .irq = -1 } |
bce06f37 PW |
981 | }; |
982 | ||
983 | static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = { | |
984 | { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */ | |
985 | { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */ | |
bc614958 | 986 | { .dma_req = -1 } |
bce06f37 PW |
987 | }; |
988 | ||
989 | static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { | |
990 | { .role = "dbck", .clk = "mmchsdb1_fck" }, | |
991 | }; | |
992 | ||
6ab8946f KK |
993 | static struct omap_mmc_dev_attr mmc1_dev_attr = { |
994 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
995 | }; | |
996 | ||
bce06f37 PW |
997 | static struct omap_hwmod omap2430_mmc1_hwmod = { |
998 | .name = "mmc1", | |
999 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
1000 | .mpu_irqs = omap2430_mmc1_mpu_irqs, | |
bce06f37 | 1001 | .sdma_reqs = omap2430_mmc1_sdma_reqs, |
bce06f37 PW |
1002 | .opt_clks = omap2430_mmc1_opt_clks, |
1003 | .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), | |
1004 | .main_clk = "mmchs1_fck", | |
1005 | .prcm = { | |
1006 | .omap2 = { | |
1007 | .module_offs = CORE_MOD, | |
1008 | .prcm_reg_id = 2, | |
1009 | .module_bit = OMAP2430_EN_MMCHS1_SHIFT, | |
1010 | .idlest_reg_id = 2, | |
1011 | .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT, | |
1012 | }, | |
1013 | }, | |
6ab8946f | 1014 | .dev_attr = &mmc1_dev_attr, |
bce06f37 | 1015 | .class = &omap2430_mmc_class, |
bce06f37 PW |
1016 | }; |
1017 | ||
1018 | /* MMC/SD/SDIO2 */ | |
bce06f37 PW |
1019 | static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { |
1020 | { .irq = 86 }, | |
212738a4 | 1021 | { .irq = -1 } |
bce06f37 PW |
1022 | }; |
1023 | ||
1024 | static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = { | |
1025 | { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */ | |
1026 | { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */ | |
bc614958 | 1027 | { .dma_req = -1 } |
bce06f37 PW |
1028 | }; |
1029 | ||
1030 | static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { | |
1031 | { .role = "dbck", .clk = "mmchsdb2_fck" }, | |
1032 | }; | |
1033 | ||
bce06f37 PW |
1034 | static struct omap_hwmod omap2430_mmc2_hwmod = { |
1035 | .name = "mmc2", | |
1036 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
1037 | .mpu_irqs = omap2430_mmc2_mpu_irqs, | |
bce06f37 | 1038 | .sdma_reqs = omap2430_mmc2_sdma_reqs, |
bce06f37 PW |
1039 | .opt_clks = omap2430_mmc2_opt_clks, |
1040 | .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), | |
1041 | .main_clk = "mmchs2_fck", | |
1042 | .prcm = { | |
1043 | .omap2 = { | |
1044 | .module_offs = CORE_MOD, | |
1045 | .prcm_reg_id = 2, | |
1046 | .module_bit = OMAP2430_EN_MMCHS2_SHIFT, | |
1047 | .idlest_reg_id = 2, | |
1048 | .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, | |
1049 | }, | |
1050 | }, | |
bce06f37 | 1051 | .class = &omap2430_mmc_class, |
bce06f37 | 1052 | }; |
04aa67de | 1053 | |
844a3b63 PW |
1054 | /* |
1055 | * interfaces | |
1056 | */ | |
1057 | ||
1058 | /* L3 -> L4_CORE interface */ | |
1059 | static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { | |
1060 | .master = &omap2430_l3_main_hwmod, | |
1061 | .slave = &omap2430_l4_core_hwmod, | |
1062 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1063 | }; | |
1064 | ||
1065 | /* MPU -> L3 interface */ | |
1066 | static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = { | |
1067 | .master = &omap2430_mpu_hwmod, | |
1068 | .slave = &omap2430_l3_main_hwmod, | |
1069 | .user = OCP_USER_MPU, | |
1070 | }; | |
1071 | ||
1072 | /* DSS -> l3 */ | |
1073 | static struct omap_hwmod_ocp_if omap2430_dss__l3 = { | |
1074 | .master = &omap2430_dss_core_hwmod, | |
1075 | .slave = &omap2430_l3_main_hwmod, | |
1076 | .fw = { | |
1077 | .omap2 = { | |
1078 | .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, | |
1079 | .flags = OMAP_FIREWALL_L3, | |
1080 | } | |
1081 | }, | |
1082 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1083 | }; | |
1084 | ||
1085 | /* l3_core -> usbhsotg interface */ | |
1086 | static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { | |
1087 | .master = &omap2430_usbhsotg_hwmod, | |
1088 | .slave = &omap2430_l3_main_hwmod, | |
1089 | .clk = "core_l3_ck", | |
1090 | .user = OCP_USER_MPU, | |
1091 | }; | |
1092 | ||
1093 | /* L4 CORE -> I2C1 interface */ | |
1094 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { | |
1095 | .master = &omap2430_l4_core_hwmod, | |
1096 | .slave = &omap2430_i2c1_hwmod, | |
1097 | .clk = "i2c1_ick", | |
1098 | .addr = omap2_i2c1_addr_space, | |
1099 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1100 | }; | |
1101 | ||
1102 | /* L4 CORE -> I2C2 interface */ | |
1103 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { | |
1104 | .master = &omap2430_l4_core_hwmod, | |
1105 | .slave = &omap2430_i2c2_hwmod, | |
1106 | .clk = "i2c2_ick", | |
1107 | .addr = omap2_i2c2_addr_space, | |
1108 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1109 | }; | |
1110 | ||
1111 | /* L4_CORE -> L4_WKUP interface */ | |
1112 | static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { | |
1113 | .master = &omap2430_l4_core_hwmod, | |
1114 | .slave = &omap2430_l4_wkup_hwmod, | |
1115 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1116 | }; | |
1117 | ||
1118 | /* L4 CORE -> UART1 interface */ | |
1119 | static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { | |
1120 | .master = &omap2430_l4_core_hwmod, | |
1121 | .slave = &omap2430_uart1_hwmod, | |
1122 | .clk = "uart1_ick", | |
1123 | .addr = omap2xxx_uart1_addr_space, | |
1124 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1125 | }; | |
1126 | ||
1127 | /* L4 CORE -> UART2 interface */ | |
1128 | static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { | |
1129 | .master = &omap2430_l4_core_hwmod, | |
1130 | .slave = &omap2430_uart2_hwmod, | |
1131 | .clk = "uart2_ick", | |
1132 | .addr = omap2xxx_uart2_addr_space, | |
1133 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1134 | }; | |
1135 | ||
1136 | /* L4 PER -> UART3 interface */ | |
1137 | static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { | |
1138 | .master = &omap2430_l4_core_hwmod, | |
1139 | .slave = &omap2430_uart3_hwmod, | |
1140 | .clk = "uart3_ick", | |
1141 | .addr = omap2xxx_uart3_addr_space, | |
1142 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1143 | }; | |
1144 | ||
1145 | static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { | |
1146 | { | |
1147 | .pa_start = OMAP243X_HS_BASE, | |
1148 | .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, | |
1149 | .flags = ADDR_TYPE_RT | |
1150 | }, | |
1151 | { } | |
1152 | }; | |
1153 | ||
1154 | /* l4_core ->usbhsotg interface */ | |
1155 | static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { | |
1156 | .master = &omap2430_l4_core_hwmod, | |
1157 | .slave = &omap2430_usbhsotg_hwmod, | |
1158 | .clk = "usb_l4_ick", | |
1159 | .addr = omap2430_usbhsotg_addrs, | |
1160 | .user = OCP_USER_MPU, | |
1161 | }; | |
1162 | ||
1163 | /* L4 CORE -> MMC1 interface */ | |
1164 | static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { | |
1165 | .master = &omap2430_l4_core_hwmod, | |
1166 | .slave = &omap2430_mmc1_hwmod, | |
1167 | .clk = "mmchs1_ick", | |
1168 | .addr = omap2430_mmc1_addr_space, | |
1169 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1170 | }; | |
1171 | ||
1172 | /* L4 CORE -> MMC2 interface */ | |
1173 | static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { | |
1174 | .master = &omap2430_l4_core_hwmod, | |
1175 | .slave = &omap2430_mmc2_hwmod, | |
1176 | .clk = "mmchs2_ick", | |
1177 | .addr = omap2430_mmc2_addr_space, | |
1178 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1179 | }; | |
1180 | ||
1181 | /* l4 core -> mcspi1 interface */ | |
1182 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = { | |
1183 | .master = &omap2430_l4_core_hwmod, | |
1184 | .slave = &omap2430_mcspi1_hwmod, | |
1185 | .clk = "mcspi1_ick", | |
1186 | .addr = omap2_mcspi1_addr_space, | |
1187 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1188 | }; | |
1189 | ||
1190 | /* l4 core -> mcspi2 interface */ | |
1191 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = { | |
1192 | .master = &omap2430_l4_core_hwmod, | |
1193 | .slave = &omap2430_mcspi2_hwmod, | |
1194 | .clk = "mcspi2_ick", | |
1195 | .addr = omap2_mcspi2_addr_space, | |
1196 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1197 | }; | |
1198 | ||
1199 | /* l4 core -> mcspi3 interface */ | |
1200 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { | |
1201 | .master = &omap2430_l4_core_hwmod, | |
1202 | .slave = &omap2430_mcspi3_hwmod, | |
1203 | .clk = "mcspi3_ick", | |
1204 | .addr = omap2430_mcspi3_addr_space, | |
1205 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1206 | }; | |
1207 | ||
1208 | /* IVA2 <- L3 interface */ | |
1209 | static struct omap_hwmod_ocp_if omap2430_l3__iva = { | |
1210 | .master = &omap2430_l3_main_hwmod, | |
1211 | .slave = &omap2430_iva_hwmod, | |
1212 | .clk = "dsp_fck", | |
1213 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1214 | }; | |
1215 | ||
1216 | static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { | |
1217 | { | |
1218 | .pa_start = 0x49018000, | |
1219 | .pa_end = 0x49018000 + SZ_1K - 1, | |
1220 | .flags = ADDR_TYPE_RT | |
1221 | }, | |
1222 | { } | |
1223 | }; | |
1224 | ||
1225 | /* l4_wkup -> timer1 */ | |
1226 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { | |
1227 | .master = &omap2430_l4_wkup_hwmod, | |
1228 | .slave = &omap2430_timer1_hwmod, | |
1229 | .clk = "gpt1_ick", | |
1230 | .addr = omap2430_timer1_addrs, | |
1231 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1232 | }; | |
1233 | ||
1234 | /* l4_core -> timer2 */ | |
1235 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = { | |
1236 | .master = &omap2430_l4_core_hwmod, | |
1237 | .slave = &omap2430_timer2_hwmod, | |
1238 | .clk = "gpt2_ick", | |
1239 | .addr = omap2xxx_timer2_addrs, | |
1240 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1241 | }; | |
1242 | ||
1243 | /* l4_core -> timer3 */ | |
1244 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = { | |
1245 | .master = &omap2430_l4_core_hwmod, | |
1246 | .slave = &omap2430_timer3_hwmod, | |
1247 | .clk = "gpt3_ick", | |
1248 | .addr = omap2xxx_timer3_addrs, | |
1249 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1250 | }; | |
1251 | ||
1252 | /* l4_core -> timer4 */ | |
1253 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = { | |
1254 | .master = &omap2430_l4_core_hwmod, | |
1255 | .slave = &omap2430_timer4_hwmod, | |
1256 | .clk = "gpt4_ick", | |
1257 | .addr = omap2xxx_timer4_addrs, | |
1258 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1259 | }; | |
1260 | ||
1261 | /* l4_core -> timer5 */ | |
1262 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = { | |
1263 | .master = &omap2430_l4_core_hwmod, | |
1264 | .slave = &omap2430_timer5_hwmod, | |
1265 | .clk = "gpt5_ick", | |
1266 | .addr = omap2xxx_timer5_addrs, | |
1267 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1268 | }; | |
1269 | ||
1270 | /* l4_core -> timer6 */ | |
1271 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = { | |
1272 | .master = &omap2430_l4_core_hwmod, | |
1273 | .slave = &omap2430_timer6_hwmod, | |
1274 | .clk = "gpt6_ick", | |
1275 | .addr = omap2xxx_timer6_addrs, | |
1276 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1277 | }; | |
1278 | ||
1279 | /* l4_core -> timer7 */ | |
1280 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = { | |
1281 | .master = &omap2430_l4_core_hwmod, | |
1282 | .slave = &omap2430_timer7_hwmod, | |
1283 | .clk = "gpt7_ick", | |
1284 | .addr = omap2xxx_timer7_addrs, | |
1285 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1286 | }; | |
1287 | ||
1288 | /* l4_core -> timer8 */ | |
1289 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = { | |
1290 | .master = &omap2430_l4_core_hwmod, | |
1291 | .slave = &omap2430_timer8_hwmod, | |
1292 | .clk = "gpt8_ick", | |
1293 | .addr = omap2xxx_timer8_addrs, | |
1294 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1295 | }; | |
1296 | ||
1297 | /* l4_core -> timer9 */ | |
1298 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = { | |
1299 | .master = &omap2430_l4_core_hwmod, | |
1300 | .slave = &omap2430_timer9_hwmod, | |
1301 | .clk = "gpt9_ick", | |
1302 | .addr = omap2xxx_timer9_addrs, | |
1303 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1304 | }; | |
1305 | ||
1306 | /* l4_core -> timer10 */ | |
1307 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = { | |
1308 | .master = &omap2430_l4_core_hwmod, | |
1309 | .slave = &omap2430_timer10_hwmod, | |
1310 | .clk = "gpt10_ick", | |
1311 | .addr = omap2_timer10_addrs, | |
1312 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1313 | }; | |
1314 | ||
1315 | /* l4_core -> timer11 */ | |
1316 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = { | |
1317 | .master = &omap2430_l4_core_hwmod, | |
1318 | .slave = &omap2430_timer11_hwmod, | |
1319 | .clk = "gpt11_ick", | |
1320 | .addr = omap2_timer11_addrs, | |
1321 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1322 | }; | |
1323 | ||
1324 | /* l4_core -> timer12 */ | |
1325 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = { | |
1326 | .master = &omap2430_l4_core_hwmod, | |
1327 | .slave = &omap2430_timer12_hwmod, | |
1328 | .clk = "gpt12_ick", | |
1329 | .addr = omap2xxx_timer12_addrs, | |
1330 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1331 | }; | |
1332 | ||
1333 | /* l4_wkup -> wd_timer2 */ | |
1334 | static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { | |
1335 | { | |
1336 | .pa_start = 0x49016000, | |
1337 | .pa_end = 0x4901607f, | |
1338 | .flags = ADDR_TYPE_RT | |
1339 | }, | |
1340 | { } | |
1341 | }; | |
1342 | ||
1343 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { | |
1344 | .master = &omap2430_l4_wkup_hwmod, | |
1345 | .slave = &omap2430_wd_timer2_hwmod, | |
1346 | .clk = "mpu_wdt_ick", | |
1347 | .addr = omap2430_wd_timer2_addrs, | |
1348 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1349 | }; | |
1350 | ||
1351 | /* l4_core -> dss */ | |
1352 | static struct omap_hwmod_ocp_if omap2430_l4_core__dss = { | |
1353 | .master = &omap2430_l4_core_hwmod, | |
1354 | .slave = &omap2430_dss_core_hwmod, | |
1355 | .clk = "dss_ick", | |
1356 | .addr = omap2_dss_addrs, | |
1357 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1358 | }; | |
1359 | ||
1360 | /* l4_core -> dss_dispc */ | |
1361 | static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = { | |
1362 | .master = &omap2430_l4_core_hwmod, | |
1363 | .slave = &omap2430_dss_dispc_hwmod, | |
1364 | .clk = "dss_ick", | |
1365 | .addr = omap2_dss_dispc_addrs, | |
1366 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1367 | }; | |
1368 | ||
1369 | /* l4_core -> dss_rfbi */ | |
1370 | static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = { | |
1371 | .master = &omap2430_l4_core_hwmod, | |
1372 | .slave = &omap2430_dss_rfbi_hwmod, | |
1373 | .clk = "dss_ick", | |
1374 | .addr = omap2_dss_rfbi_addrs, | |
1375 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1376 | }; | |
1377 | ||
1378 | /* l4_core -> dss_venc */ | |
1379 | static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { | |
1380 | .master = &omap2430_l4_core_hwmod, | |
1381 | .slave = &omap2430_dss_venc_hwmod, | |
1382 | .clk = "dss_ick", | |
1383 | .addr = omap2_dss_venc_addrs, | |
1384 | .flags = OCPIF_SWSUP_IDLE, | |
1385 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1386 | }; | |
1387 | ||
1388 | /* l4_wkup -> gpio1 */ | |
1389 | static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { | |
1390 | { | |
1391 | .pa_start = 0x4900C000, | |
1392 | .pa_end = 0x4900C1ff, | |
1393 | .flags = ADDR_TYPE_RT | |
1394 | }, | |
1395 | { } | |
1396 | }; | |
1397 | ||
1398 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { | |
1399 | .master = &omap2430_l4_wkup_hwmod, | |
1400 | .slave = &omap2430_gpio1_hwmod, | |
1401 | .clk = "gpios_ick", | |
1402 | .addr = omap2430_gpio1_addr_space, | |
1403 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1404 | }; | |
1405 | ||
1406 | /* l4_wkup -> gpio2 */ | |
1407 | static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { | |
1408 | { | |
1409 | .pa_start = 0x4900E000, | |
1410 | .pa_end = 0x4900E1ff, | |
1411 | .flags = ADDR_TYPE_RT | |
1412 | }, | |
1413 | { } | |
1414 | }; | |
1415 | ||
1416 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { | |
1417 | .master = &omap2430_l4_wkup_hwmod, | |
1418 | .slave = &omap2430_gpio2_hwmod, | |
1419 | .clk = "gpios_ick", | |
1420 | .addr = omap2430_gpio2_addr_space, | |
1421 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1422 | }; | |
1423 | ||
1424 | /* l4_wkup -> gpio3 */ | |
1425 | static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { | |
1426 | { | |
1427 | .pa_start = 0x49010000, | |
1428 | .pa_end = 0x490101ff, | |
1429 | .flags = ADDR_TYPE_RT | |
1430 | }, | |
1431 | { } | |
1432 | }; | |
1433 | ||
1434 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { | |
1435 | .master = &omap2430_l4_wkup_hwmod, | |
1436 | .slave = &omap2430_gpio3_hwmod, | |
1437 | .clk = "gpios_ick", | |
1438 | .addr = omap2430_gpio3_addr_space, | |
1439 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1440 | }; | |
1441 | ||
1442 | /* l4_wkup -> gpio4 */ | |
1443 | static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { | |
1444 | { | |
1445 | .pa_start = 0x49012000, | |
1446 | .pa_end = 0x490121ff, | |
1447 | .flags = ADDR_TYPE_RT | |
1448 | }, | |
1449 | { } | |
1450 | }; | |
1451 | ||
1452 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { | |
1453 | .master = &omap2430_l4_wkup_hwmod, | |
1454 | .slave = &omap2430_gpio4_hwmod, | |
1455 | .clk = "gpios_ick", | |
1456 | .addr = omap2430_gpio4_addr_space, | |
1457 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1458 | }; | |
1459 | ||
1460 | /* l4_core -> gpio5 */ | |
1461 | static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { | |
1462 | { | |
1463 | .pa_start = 0x480B6000, | |
1464 | .pa_end = 0x480B61ff, | |
1465 | .flags = ADDR_TYPE_RT | |
1466 | }, | |
1467 | { } | |
1468 | }; | |
1469 | ||
1470 | static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { | |
1471 | .master = &omap2430_l4_core_hwmod, | |
1472 | .slave = &omap2430_gpio5_hwmod, | |
1473 | .clk = "gpio5_ick", | |
1474 | .addr = omap2430_gpio5_addr_space, | |
1475 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1476 | }; | |
1477 | ||
1478 | /* dma_system -> L3 */ | |
1479 | static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { | |
1480 | .master = &omap2430_dma_system_hwmod, | |
1481 | .slave = &omap2430_l3_main_hwmod, | |
1482 | .clk = "core_l3_ck", | |
1483 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1484 | }; | |
1485 | ||
1486 | /* l4_core -> dma_system */ | |
1487 | static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { | |
1488 | .master = &omap2430_l4_core_hwmod, | |
1489 | .slave = &omap2430_dma_system_hwmod, | |
1490 | .clk = "sdma_ick", | |
1491 | .addr = omap2_dma_system_addrs, | |
1492 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1493 | }; | |
1494 | ||
1495 | /* l4_core -> mailbox */ | |
1496 | static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { | |
1497 | .master = &omap2430_l4_core_hwmod, | |
1498 | .slave = &omap2430_mailbox_hwmod, | |
1499 | .addr = omap2_mailbox_addrs, | |
1500 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1501 | }; | |
1502 | ||
1503 | /* l4_core -> mcbsp1 */ | |
1504 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { | |
1505 | .master = &omap2430_l4_core_hwmod, | |
1506 | .slave = &omap2430_mcbsp1_hwmod, | |
1507 | .clk = "mcbsp1_ick", | |
1508 | .addr = omap2_mcbsp1_addrs, | |
1509 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1510 | }; | |
1511 | ||
1512 | /* l4_core -> mcbsp2 */ | |
1513 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { | |
1514 | .master = &omap2430_l4_core_hwmod, | |
1515 | .slave = &omap2430_mcbsp2_hwmod, | |
1516 | .clk = "mcbsp2_ick", | |
1517 | .addr = omap2xxx_mcbsp2_addrs, | |
1518 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1519 | }; | |
1520 | ||
1521 | static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { | |
1522 | { | |
1523 | .name = "mpu", | |
1524 | .pa_start = 0x4808C000, | |
1525 | .pa_end = 0x4808C0ff, | |
1526 | .flags = ADDR_TYPE_RT | |
1527 | }, | |
1528 | { } | |
1529 | }; | |
1530 | ||
1531 | /* l4_core -> mcbsp3 */ | |
1532 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { | |
1533 | .master = &omap2430_l4_core_hwmod, | |
1534 | .slave = &omap2430_mcbsp3_hwmod, | |
1535 | .clk = "mcbsp3_ick", | |
1536 | .addr = omap2430_mcbsp3_addrs, | |
1537 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1538 | }; | |
1539 | ||
1540 | static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { | |
1541 | { | |
1542 | .name = "mpu", | |
1543 | .pa_start = 0x4808E000, | |
1544 | .pa_end = 0x4808E0ff, | |
1545 | .flags = ADDR_TYPE_RT | |
1546 | }, | |
1547 | { } | |
1548 | }; | |
1549 | ||
1550 | /* l4_core -> mcbsp4 */ | |
1551 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { | |
1552 | .master = &omap2430_l4_core_hwmod, | |
1553 | .slave = &omap2430_mcbsp4_hwmod, | |
1554 | .clk = "mcbsp4_ick", | |
1555 | .addr = omap2430_mcbsp4_addrs, | |
1556 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1557 | }; | |
1558 | ||
1559 | static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { | |
1560 | { | |
1561 | .name = "mpu", | |
1562 | .pa_start = 0x48096000, | |
1563 | .pa_end = 0x480960ff, | |
1564 | .flags = ADDR_TYPE_RT | |
1565 | }, | |
1566 | { } | |
1567 | }; | |
1568 | ||
1569 | /* l4_core -> mcbsp5 */ | |
1570 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { | |
1571 | .master = &omap2430_l4_core_hwmod, | |
1572 | .slave = &omap2430_mcbsp5_hwmod, | |
1573 | .clk = "mcbsp5_ick", | |
1574 | .addr = omap2430_mcbsp5_addrs, | |
1575 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1576 | }; | |
1577 | ||
0a78c5c5 PW |
1578 | static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { |
1579 | &omap2430_l3_main__l4_core, | |
1580 | &omap2430_mpu__l3_main, | |
1581 | &omap2430_dss__l3, | |
1582 | &omap2430_usbhsotg__l3, | |
1583 | &omap2430_l4_core__i2c1, | |
1584 | &omap2430_l4_core__i2c2, | |
1585 | &omap2430_l4_core__l4_wkup, | |
1586 | &omap2_l4_core__uart1, | |
1587 | &omap2_l4_core__uart2, | |
1588 | &omap2_l4_core__uart3, | |
1589 | &omap2430_l4_core__usbhsotg, | |
1590 | &omap2430_l4_core__mmc1, | |
1591 | &omap2430_l4_core__mmc2, | |
1592 | &omap2430_l4_core__mcspi1, | |
1593 | &omap2430_l4_core__mcspi2, | |
1594 | &omap2430_l4_core__mcspi3, | |
1595 | &omap2430_l3__iva, | |
1596 | &omap2430_l4_wkup__timer1, | |
1597 | &omap2430_l4_core__timer2, | |
1598 | &omap2430_l4_core__timer3, | |
1599 | &omap2430_l4_core__timer4, | |
1600 | &omap2430_l4_core__timer5, | |
1601 | &omap2430_l4_core__timer6, | |
1602 | &omap2430_l4_core__timer7, | |
1603 | &omap2430_l4_core__timer8, | |
1604 | &omap2430_l4_core__timer9, | |
1605 | &omap2430_l4_core__timer10, | |
1606 | &omap2430_l4_core__timer11, | |
1607 | &omap2430_l4_core__timer12, | |
1608 | &omap2430_l4_wkup__wd_timer2, | |
1609 | &omap2430_l4_core__dss, | |
1610 | &omap2430_l4_core__dss_dispc, | |
1611 | &omap2430_l4_core__dss_rfbi, | |
1612 | &omap2430_l4_core__dss_venc, | |
1613 | &omap2430_l4_wkup__gpio1, | |
1614 | &omap2430_l4_wkup__gpio2, | |
1615 | &omap2430_l4_wkup__gpio3, | |
1616 | &omap2430_l4_wkup__gpio4, | |
1617 | &omap2430_l4_core__gpio5, | |
1618 | &omap2430_dma_system__l3, | |
1619 | &omap2430_l4_core__dma_system, | |
1620 | &omap2430_l4_core__mailbox, | |
1621 | &omap2430_l4_core__mcbsp1, | |
1622 | &omap2430_l4_core__mcbsp2, | |
1623 | &omap2430_l4_core__mcbsp3, | |
1624 | &omap2430_l4_core__mcbsp4, | |
1625 | &omap2430_l4_core__mcbsp5, | |
02bfc030 PW |
1626 | NULL, |
1627 | }; | |
1628 | ||
7359154e PW |
1629 | int __init omap2430_hwmod_init(void) |
1630 | { | |
0a78c5c5 | 1631 | return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs); |
7359154e | 1632 | } |