Commit | Line | Data |
---|---|---|
02bfc030 | 1 | /* |
7359154e | 2 | * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips |
02bfc030 | 3 | * |
78183f3f | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
0a78c5c5 | 5 | * Copyright (C) 2012 Texas Instruments, Inc. |
02bfc030 PW |
6 | * Paul Walmsley |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * XXX handle crossbar/shared link difference for L3? | |
7359154e | 13 | * XXX these should be marked initdata for multi-OMAP kernels |
02bfc030 | 14 | */ |
ce491cf8 | 15 | #include <plat/omap_hwmod.h> |
ce491cf8 TL |
16 | #include <plat/cpu.h> |
17 | #include <plat/dma.h> | |
046465b7 | 18 | #include <plat/serial.h> |
2004290f | 19 | #include <plat/i2c.h> |
37801b3d | 20 | #include <plat/mcbsp.h> |
7f904c78 | 21 | #include <plat/mcspi.h> |
b6b58229 | 22 | #include <plat/dmtimer.h> |
6ab8946f | 23 | #include <plat/mmc.h> |
de56dbb6 | 24 | #include <plat/l3_2xxx.h> |
02bfc030 | 25 | |
7d7e1eba TL |
26 | #include <plat/hardware.h> |
27 | ||
43b40992 PW |
28 | #include "omap_hwmod_common_data.h" |
29 | ||
02bfc030 | 30 | #include "prm-regbits-24xx.h" |
165e2161 | 31 | #include "cm-regbits-24xx.h" |
ff2516fb | 32 | #include "wd_timer.h" |
02bfc030 | 33 | |
7359154e PW |
34 | /* |
35 | * OMAP2430 hardware module integration data | |
36 | * | |
844a3b63 | 37 | * All of the data in this section should be autogeneratable from the |
7359154e PW |
38 | * TI hardware database or other technical documentation. Data that |
39 | * is driver-specific or driver-kernel integration-specific belongs | |
40 | * elsewhere. | |
41 | */ | |
42 | ||
844a3b63 PW |
43 | /* |
44 | * IP blocks | |
45 | */ | |
de56dbb6 | 46 | |
844a3b63 | 47 | /* IVA2 (IVA2) */ |
3af35fbc PW |
48 | static struct omap_hwmod_rst_info omap2430_iva_resets[] = { |
49 | { .name = "logic", .rst_shift = 0 }, | |
50 | { .name = "mmu", .rst_shift = 1 }, | |
51 | }; | |
52 | ||
08072acf PW |
53 | static struct omap_hwmod omap2430_iva_hwmod = { |
54 | .name = "iva", | |
55 | .class = &iva_hwmod_class, | |
3af35fbc PW |
56 | .clkdm_name = "dsp_clkdm", |
57 | .rst_lines = omap2430_iva_resets, | |
58 | .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets), | |
59 | .main_clk = "dsp_fck", | |
08072acf PW |
60 | }; |
61 | ||
2004290f PW |
62 | /* I2C common */ |
63 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
64 | .rev_offs = 0x00, | |
65 | .sysc_offs = 0x20, | |
66 | .syss_offs = 0x10, | |
2d403fe0 PW |
67 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
68 | SYSS_HAS_RESET_STATUS), | |
2004290f PW |
69 | .sysc_fields = &omap_hwmod_sysc_type1, |
70 | }; | |
71 | ||
72 | static struct omap_hwmod_class i2c_class = { | |
73 | .name = "i2c", | |
74 | .sysc = &i2c_sysc, | |
db791a75 | 75 | .rev = OMAP_I2C_IP_VERSION_1, |
6d3c55fd | 76 | .reset = &omap_i2c_reset, |
2004290f PW |
77 | }; |
78 | ||
50ebb777 | 79 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
2004290f | 80 | .fifo_depth = 8, /* bytes */ |
4d4441a6 AG |
81 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | |
82 | OMAP_I2C_FLAG_BUS_SHIFT_2 | | |
83 | OMAP_I2C_FLAG_FORCE_19200_INT_CLK, | |
2004290f PW |
84 | }; |
85 | ||
50ebb777 | 86 | /* I2C1 */ |
2004290f PW |
87 | static struct omap_hwmod omap2430_i2c1_hwmod = { |
88 | .name = "i2c1", | |
3e600522 | 89 | .flags = HWMOD_16BIT_REG, |
0d619a89 | 90 | .mpu_irqs = omap2_i2c1_mpu_irqs, |
d826ebfa | 91 | .sdma_reqs = omap2_i2c1_sdma_reqs, |
2004290f PW |
92 | .main_clk = "i2chs1_fck", |
93 | .prcm = { | |
94 | .omap2 = { | |
95 | /* | |
96 | * NOTE: The CM_FCLKEN* and CM_ICLKEN* for | |
97 | * I2CHS IP's do not follow the usual pattern. | |
98 | * prcm_reg_id alone cannot be used to program | |
99 | * the iclk and fclk. Needs to be handled using | |
25985edc | 100 | * additional flags when clk handling is moved |
2004290f PW |
101 | * to hwmod framework. |
102 | */ | |
103 | .module_offs = CORE_MOD, | |
104 | .prcm_reg_id = 1, | |
105 | .module_bit = OMAP2430_EN_I2CHS1_SHIFT, | |
106 | .idlest_reg_id = 1, | |
107 | .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, | |
108 | }, | |
109 | }, | |
2004290f | 110 | .class = &i2c_class, |
50ebb777 | 111 | .dev_attr = &i2c_dev_attr, |
2004290f PW |
112 | }; |
113 | ||
114 | /* I2C2 */ | |
2004290f PW |
115 | static struct omap_hwmod omap2430_i2c2_hwmod = { |
116 | .name = "i2c2", | |
3e600522 | 117 | .flags = HWMOD_16BIT_REG, |
0d619a89 | 118 | .mpu_irqs = omap2_i2c2_mpu_irqs, |
d826ebfa | 119 | .sdma_reqs = omap2_i2c2_sdma_reqs, |
2004290f PW |
120 | .main_clk = "i2chs2_fck", |
121 | .prcm = { | |
122 | .omap2 = { | |
123 | .module_offs = CORE_MOD, | |
124 | .prcm_reg_id = 1, | |
125 | .module_bit = OMAP2430_EN_I2CHS2_SHIFT, | |
126 | .idlest_reg_id = 1, | |
127 | .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, | |
128 | }, | |
129 | }, | |
2004290f | 130 | .class = &i2c_class, |
50ebb777 | 131 | .dev_attr = &i2c_dev_attr, |
2004290f PW |
132 | }; |
133 | ||
aeac0e44 VC |
134 | /* gpio5 */ |
135 | static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { | |
7d7e1eba TL |
136 | { .irq = 33 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK5 */ |
137 | { .irq = -1 }, | |
aeac0e44 VC |
138 | }; |
139 | ||
aeac0e44 VC |
140 | static struct omap_hwmod omap2430_gpio5_hwmod = { |
141 | .name = "gpio5", | |
f95440ca | 142 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
aeac0e44 | 143 | .mpu_irqs = omap243x_gpio5_irqs, |
aeac0e44 VC |
144 | .main_clk = "gpio5_fck", |
145 | .prcm = { | |
146 | .omap2 = { | |
147 | .prcm_reg_id = 2, | |
148 | .module_bit = OMAP2430_EN_GPIO5_SHIFT, | |
149 | .module_offs = CORE_MOD, | |
150 | .idlest_reg_id = 2, | |
151 | .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, | |
152 | }, | |
153 | }, | |
273b9465 | 154 | .class = &omap2xxx_gpio_hwmod_class, |
cb48427e | 155 | .dev_attr = &omap2xxx_gpio_dev_attr, |
aeac0e44 VC |
156 | }; |
157 | ||
82cbd1ae MK |
158 | /* dma attributes */ |
159 | static struct omap_dma_dev_attr dma_dev_attr = { | |
160 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
161 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
162 | .lch_count = 32, | |
163 | }; | |
164 | ||
82cbd1ae MK |
165 | static struct omap_hwmod omap2430_dma_system_hwmod = { |
166 | .name = "dma", | |
273b9465 | 167 | .class = &omap2xxx_dma_hwmod_class, |
0d619a89 | 168 | .mpu_irqs = omap2_dma_system_irqs, |
82cbd1ae | 169 | .main_clk = "core_l3_ck", |
82cbd1ae | 170 | .dev_attr = &dma_dev_attr, |
82cbd1ae MK |
171 | .flags = HWMOD_NO_IDLEST, |
172 | }; | |
173 | ||
fca1ab55 | 174 | /* mailbox */ |
fca1ab55 | 175 | static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { |
7d7e1eba TL |
176 | { .irq = 26 + OMAP_INTC_START, }, |
177 | { .irq = -1 }, | |
fca1ab55 ORL |
178 | }; |
179 | ||
fca1ab55 ORL |
180 | static struct omap_hwmod omap2430_mailbox_hwmod = { |
181 | .name = "mailbox", | |
273b9465 | 182 | .class = &omap2xxx_mailbox_hwmod_class, |
fca1ab55 | 183 | .mpu_irqs = omap2430_mailbox_irqs, |
fca1ab55 ORL |
184 | .main_clk = "mailboxes_ick", |
185 | .prcm = { | |
186 | .omap2 = { | |
187 | .prcm_reg_id = 1, | |
188 | .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | |
189 | .module_offs = CORE_MOD, | |
190 | .idlest_reg_id = 1, | |
191 | .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, | |
192 | }, | |
193 | }, | |
fca1ab55 ORL |
194 | }; |
195 | ||
7f904c78 C |
196 | /* mcspi3 */ |
197 | static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { | |
7d7e1eba TL |
198 | { .irq = 91 + OMAP_INTC_START, }, |
199 | { .irq = -1 }, | |
7f904c78 C |
200 | }; |
201 | ||
202 | static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { | |
203 | { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */ | |
204 | { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */ | |
205 | { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */ | |
206 | { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */ | |
bc614958 | 207 | { .dma_req = -1 } |
7f904c78 C |
208 | }; |
209 | ||
7f904c78 C |
210 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { |
211 | .num_chipselect = 2, | |
212 | }; | |
213 | ||
214 | static struct omap_hwmod omap2430_mcspi3_hwmod = { | |
bec93811 | 215 | .name = "mcspi3", |
7f904c78 | 216 | .mpu_irqs = omap2430_mcspi3_mpu_irqs, |
7f904c78 | 217 | .sdma_reqs = omap2430_mcspi3_sdma_reqs, |
7f904c78 C |
218 | .main_clk = "mcspi3_fck", |
219 | .prcm = { | |
220 | .omap2 = { | |
221 | .module_offs = CORE_MOD, | |
222 | .prcm_reg_id = 2, | |
223 | .module_bit = OMAP2430_EN_MCSPI3_SHIFT, | |
224 | .idlest_reg_id = 2, | |
225 | .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, | |
226 | }, | |
227 | }, | |
273b9465 PW |
228 | .class = &omap2xxx_mcspi_class, |
229 | .dev_attr = &omap_mcspi3_dev_attr, | |
7f904c78 C |
230 | }; |
231 | ||
844a3b63 | 232 | /* usbhsotg */ |
44d02acf HH |
233 | static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { |
234 | .rev_offs = 0x0400, | |
235 | .sysc_offs = 0x0404, | |
236 | .syss_offs = 0x0408, | |
237 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| | |
238 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
239 | SYSC_HAS_AUTOIDLE), | |
240 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
241 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
242 | .sysc_fields = &omap_hwmod_sysc_type1, | |
243 | }; | |
244 | ||
245 | static struct omap_hwmod_class usbotg_class = { | |
246 | .name = "usbotg", | |
247 | .sysc = &omap2430_usbhsotg_sysc, | |
248 | }; | |
249 | ||
250 | /* usb_otg_hs */ | |
251 | static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { | |
252 | ||
7d7e1eba TL |
253 | { .name = "mc", .irq = 92 + OMAP_INTC_START, }, |
254 | { .name = "dma", .irq = 93 + OMAP_INTC_START, }, | |
255 | { .irq = -1 }, | |
44d02acf HH |
256 | }; |
257 | ||
258 | static struct omap_hwmod omap2430_usbhsotg_hwmod = { | |
259 | .name = "usb_otg_hs", | |
260 | .mpu_irqs = omap2430_usbhsotg_mpu_irqs, | |
44d02acf HH |
261 | .main_clk = "usbhs_ick", |
262 | .prcm = { | |
263 | .omap2 = { | |
264 | .prcm_reg_id = 1, | |
265 | .module_bit = OMAP2430_EN_USBHS_MASK, | |
266 | .module_offs = CORE_MOD, | |
267 | .idlest_reg_id = 1, | |
268 | .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, | |
269 | }, | |
270 | }, | |
44d02acf HH |
271 | .class = &usbotg_class, |
272 | /* | |
273 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially | |
274 | * broken when autoidle is enabled | |
275 | * workaround is to disable the autoidle bit at module level. | |
276 | */ | |
277 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | |
278 | | HWMOD_SWSUP_MSTANDBY, | |
44d02acf HH |
279 | }; |
280 | ||
37801b3d C |
281 | /* |
282 | * 'mcbsp' class | |
283 | * multi channel buffered serial port controller | |
284 | */ | |
285 | ||
286 | static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = { | |
287 | .rev_offs = 0x007C, | |
288 | .sysc_offs = 0x008C, | |
289 | .sysc_flags = (SYSC_HAS_SOFTRESET), | |
290 | .sysc_fields = &omap_hwmod_sysc_type1, | |
291 | }; | |
292 | ||
293 | static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { | |
294 | .name = "mcbsp", | |
295 | .sysc = &omap2430_mcbsp_sysc, | |
296 | .rev = MCBSP_CONFIG_TYPE2, | |
297 | }; | |
04aa67de | 298 | |
db382a86 PU |
299 | static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { |
300 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | |
301 | { .role = "prcm_fck", .clk = "func_96m_ck" }, | |
302 | }; | |
303 | ||
37801b3d C |
304 | /* mcbsp1 */ |
305 | static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { | |
7d7e1eba TL |
306 | { .name = "tx", .irq = 59 + OMAP_INTC_START, }, |
307 | { .name = "rx", .irq = 60 + OMAP_INTC_START, }, | |
308 | { .name = "ovr", .irq = 61 + OMAP_INTC_START, }, | |
309 | { .name = "common", .irq = 64 + OMAP_INTC_START, }, | |
310 | { .irq = -1 }, | |
37801b3d C |
311 | }; |
312 | ||
37801b3d C |
313 | static struct omap_hwmod omap2430_mcbsp1_hwmod = { |
314 | .name = "mcbsp1", | |
315 | .class = &omap2430_mcbsp_hwmod_class, | |
316 | .mpu_irqs = omap2430_mcbsp1_irqs, | |
d826ebfa | 317 | .sdma_reqs = omap2_mcbsp1_sdma_reqs, |
37801b3d C |
318 | .main_clk = "mcbsp1_fck", |
319 | .prcm = { | |
320 | .omap2 = { | |
321 | .prcm_reg_id = 1, | |
322 | .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, | |
323 | .module_offs = CORE_MOD, | |
324 | .idlest_reg_id = 1, | |
325 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, | |
326 | }, | |
327 | }, | |
db382a86 PU |
328 | .opt_clks = mcbsp_opt_clks, |
329 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | |
37801b3d C |
330 | }; |
331 | ||
332 | /* mcbsp2 */ | |
333 | static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { | |
7d7e1eba TL |
334 | { .name = "tx", .irq = 62 + OMAP_INTC_START, }, |
335 | { .name = "rx", .irq = 63 + OMAP_INTC_START, }, | |
336 | { .name = "common", .irq = 16 + OMAP_INTC_START, }, | |
337 | { .irq = -1 }, | |
37801b3d C |
338 | }; |
339 | ||
37801b3d C |
340 | static struct omap_hwmod omap2430_mcbsp2_hwmod = { |
341 | .name = "mcbsp2", | |
342 | .class = &omap2430_mcbsp_hwmod_class, | |
343 | .mpu_irqs = omap2430_mcbsp2_irqs, | |
d826ebfa | 344 | .sdma_reqs = omap2_mcbsp2_sdma_reqs, |
37801b3d C |
345 | .main_clk = "mcbsp2_fck", |
346 | .prcm = { | |
347 | .omap2 = { | |
348 | .prcm_reg_id = 1, | |
349 | .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, | |
350 | .module_offs = CORE_MOD, | |
351 | .idlest_reg_id = 1, | |
352 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, | |
353 | }, | |
354 | }, | |
db382a86 PU |
355 | .opt_clks = mcbsp_opt_clks, |
356 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | |
37801b3d C |
357 | }; |
358 | ||
359 | /* mcbsp3 */ | |
360 | static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { | |
7d7e1eba TL |
361 | { .name = "tx", .irq = 89 + OMAP_INTC_START, }, |
362 | { .name = "rx", .irq = 90 + OMAP_INTC_START, }, | |
363 | { .name = "common", .irq = 17 + OMAP_INTC_START, }, | |
364 | { .irq = -1 }, | |
37801b3d C |
365 | }; |
366 | ||
37801b3d C |
367 | static struct omap_hwmod omap2430_mcbsp3_hwmod = { |
368 | .name = "mcbsp3", | |
369 | .class = &omap2430_mcbsp_hwmod_class, | |
370 | .mpu_irqs = omap2430_mcbsp3_irqs, | |
d826ebfa | 371 | .sdma_reqs = omap2_mcbsp3_sdma_reqs, |
37801b3d C |
372 | .main_clk = "mcbsp3_fck", |
373 | .prcm = { | |
374 | .omap2 = { | |
375 | .prcm_reg_id = 1, | |
376 | .module_bit = OMAP2430_EN_MCBSP3_SHIFT, | |
377 | .module_offs = CORE_MOD, | |
378 | .idlest_reg_id = 2, | |
379 | .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, | |
380 | }, | |
381 | }, | |
db382a86 PU |
382 | .opt_clks = mcbsp_opt_clks, |
383 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | |
37801b3d C |
384 | }; |
385 | ||
386 | /* mcbsp4 */ | |
387 | static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = { | |
7d7e1eba TL |
388 | { .name = "tx", .irq = 54 + OMAP_INTC_START, }, |
389 | { .name = "rx", .irq = 55 + OMAP_INTC_START, }, | |
390 | { .name = "common", .irq = 18 + OMAP_INTC_START, }, | |
391 | { .irq = -1 }, | |
37801b3d C |
392 | }; |
393 | ||
394 | static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { | |
395 | { .name = "rx", .dma_req = 20 }, | |
396 | { .name = "tx", .dma_req = 19 }, | |
bc614958 | 397 | { .dma_req = -1 } |
37801b3d C |
398 | }; |
399 | ||
37801b3d C |
400 | static struct omap_hwmod omap2430_mcbsp4_hwmod = { |
401 | .name = "mcbsp4", | |
402 | .class = &omap2430_mcbsp_hwmod_class, | |
403 | .mpu_irqs = omap2430_mcbsp4_irqs, | |
37801b3d | 404 | .sdma_reqs = omap2430_mcbsp4_sdma_chs, |
37801b3d C |
405 | .main_clk = "mcbsp4_fck", |
406 | .prcm = { | |
407 | .omap2 = { | |
408 | .prcm_reg_id = 1, | |
409 | .module_bit = OMAP2430_EN_MCBSP4_SHIFT, | |
410 | .module_offs = CORE_MOD, | |
411 | .idlest_reg_id = 2, | |
412 | .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, | |
413 | }, | |
414 | }, | |
db382a86 PU |
415 | .opt_clks = mcbsp_opt_clks, |
416 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | |
37801b3d C |
417 | }; |
418 | ||
419 | /* mcbsp5 */ | |
420 | static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = { | |
7d7e1eba TL |
421 | { .name = "tx", .irq = 81 + OMAP_INTC_START, }, |
422 | { .name = "rx", .irq = 82 + OMAP_INTC_START, }, | |
423 | { .name = "common", .irq = 19 + OMAP_INTC_START, }, | |
424 | { .irq = -1 }, | |
37801b3d C |
425 | }; |
426 | ||
427 | static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { | |
428 | { .name = "rx", .dma_req = 22 }, | |
429 | { .name = "tx", .dma_req = 21 }, | |
bc614958 | 430 | { .dma_req = -1 } |
37801b3d C |
431 | }; |
432 | ||
37801b3d C |
433 | static struct omap_hwmod omap2430_mcbsp5_hwmod = { |
434 | .name = "mcbsp5", | |
435 | .class = &omap2430_mcbsp_hwmod_class, | |
436 | .mpu_irqs = omap2430_mcbsp5_irqs, | |
37801b3d | 437 | .sdma_reqs = omap2430_mcbsp5_sdma_chs, |
37801b3d C |
438 | .main_clk = "mcbsp5_fck", |
439 | .prcm = { | |
440 | .omap2 = { | |
441 | .prcm_reg_id = 1, | |
442 | .module_bit = OMAP2430_EN_MCBSP5_SHIFT, | |
443 | .module_offs = CORE_MOD, | |
444 | .idlest_reg_id = 2, | |
445 | .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, | |
446 | }, | |
447 | }, | |
db382a86 PU |
448 | .opt_clks = mcbsp_opt_clks, |
449 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | |
37801b3d | 450 | }; |
04aa67de | 451 | |
bce06f37 | 452 | /* MMC/SD/SDIO common */ |
bce06f37 PW |
453 | static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { |
454 | .rev_offs = 0x1fc, | |
455 | .sysc_offs = 0x10, | |
456 | .syss_offs = 0x14, | |
457 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
458 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
459 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
460 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
461 | .sysc_fields = &omap_hwmod_sysc_type1, | |
462 | }; | |
463 | ||
464 | static struct omap_hwmod_class omap2430_mmc_class = { | |
465 | .name = "mmc", | |
466 | .sysc = &omap2430_mmc_sysc, | |
467 | }; | |
468 | ||
469 | /* MMC/SD/SDIO1 */ | |
bce06f37 | 470 | static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { |
7d7e1eba TL |
471 | { .irq = 83 + OMAP_INTC_START, }, |
472 | { .irq = -1 }, | |
bce06f37 PW |
473 | }; |
474 | ||
475 | static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = { | |
476 | { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */ | |
477 | { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */ | |
bc614958 | 478 | { .dma_req = -1 } |
bce06f37 PW |
479 | }; |
480 | ||
481 | static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { | |
482 | { .role = "dbck", .clk = "mmchsdb1_fck" }, | |
483 | }; | |
484 | ||
6ab8946f KK |
485 | static struct omap_mmc_dev_attr mmc1_dev_attr = { |
486 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
487 | }; | |
488 | ||
bce06f37 PW |
489 | static struct omap_hwmod omap2430_mmc1_hwmod = { |
490 | .name = "mmc1", | |
491 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
492 | .mpu_irqs = omap2430_mmc1_mpu_irqs, | |
bce06f37 | 493 | .sdma_reqs = omap2430_mmc1_sdma_reqs, |
bce06f37 PW |
494 | .opt_clks = omap2430_mmc1_opt_clks, |
495 | .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), | |
496 | .main_clk = "mmchs1_fck", | |
497 | .prcm = { | |
498 | .omap2 = { | |
499 | .module_offs = CORE_MOD, | |
500 | .prcm_reg_id = 2, | |
501 | .module_bit = OMAP2430_EN_MMCHS1_SHIFT, | |
502 | .idlest_reg_id = 2, | |
503 | .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT, | |
504 | }, | |
505 | }, | |
6ab8946f | 506 | .dev_attr = &mmc1_dev_attr, |
bce06f37 | 507 | .class = &omap2430_mmc_class, |
bce06f37 PW |
508 | }; |
509 | ||
510 | /* MMC/SD/SDIO2 */ | |
bce06f37 | 511 | static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { |
7d7e1eba TL |
512 | { .irq = 86 + OMAP_INTC_START, }, |
513 | { .irq = -1 }, | |
bce06f37 PW |
514 | }; |
515 | ||
516 | static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = { | |
517 | { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */ | |
518 | { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */ | |
bc614958 | 519 | { .dma_req = -1 } |
bce06f37 PW |
520 | }; |
521 | ||
522 | static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { | |
523 | { .role = "dbck", .clk = "mmchsdb2_fck" }, | |
524 | }; | |
525 | ||
bce06f37 PW |
526 | static struct omap_hwmod omap2430_mmc2_hwmod = { |
527 | .name = "mmc2", | |
528 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
529 | .mpu_irqs = omap2430_mmc2_mpu_irqs, | |
bce06f37 | 530 | .sdma_reqs = omap2430_mmc2_sdma_reqs, |
bce06f37 PW |
531 | .opt_clks = omap2430_mmc2_opt_clks, |
532 | .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), | |
533 | .main_clk = "mmchs2_fck", | |
534 | .prcm = { | |
535 | .omap2 = { | |
536 | .module_offs = CORE_MOD, | |
537 | .prcm_reg_id = 2, | |
538 | .module_bit = OMAP2430_EN_MMCHS2_SHIFT, | |
539 | .idlest_reg_id = 2, | |
540 | .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, | |
541 | }, | |
542 | }, | |
bce06f37 | 543 | .class = &omap2430_mmc_class, |
bce06f37 | 544 | }; |
04aa67de | 545 | |
f32bd778 PW |
546 | /* HDQ1W/1-wire */ |
547 | static struct omap_hwmod omap2430_hdq1w_hwmod = { | |
548 | .name = "hdq1w", | |
549 | .mpu_irqs = omap2_hdq1w_mpu_irqs, | |
550 | .main_clk = "hdq_fck", | |
551 | .prcm = { | |
552 | .omap2 = { | |
553 | .module_offs = CORE_MOD, | |
554 | .prcm_reg_id = 1, | |
555 | .module_bit = OMAP24XX_EN_HDQ_SHIFT, | |
556 | .idlest_reg_id = 1, | |
557 | .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT, | |
558 | }, | |
559 | }, | |
560 | .class = &omap2_hdq1w_class, | |
561 | }; | |
562 | ||
844a3b63 PW |
563 | /* |
564 | * interfaces | |
565 | */ | |
566 | ||
567 | /* L3 -> L4_CORE interface */ | |
844a3b63 PW |
568 | /* l3_core -> usbhsotg interface */ |
569 | static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { | |
570 | .master = &omap2430_usbhsotg_hwmod, | |
cb48427e | 571 | .slave = &omap2xxx_l3_main_hwmod, |
844a3b63 PW |
572 | .clk = "core_l3_ck", |
573 | .user = OCP_USER_MPU, | |
574 | }; | |
575 | ||
576 | /* L4 CORE -> I2C1 interface */ | |
577 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { | |
cb48427e | 578 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
579 | .slave = &omap2430_i2c1_hwmod, |
580 | .clk = "i2c1_ick", | |
581 | .addr = omap2_i2c1_addr_space, | |
582 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
583 | }; | |
584 | ||
585 | /* L4 CORE -> I2C2 interface */ | |
586 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { | |
cb48427e | 587 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
588 | .slave = &omap2430_i2c2_hwmod, |
589 | .clk = "i2c2_ick", | |
590 | .addr = omap2_i2c2_addr_space, | |
591 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
592 | }; | |
593 | ||
844a3b63 PW |
594 | static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { |
595 | { | |
596 | .pa_start = OMAP243X_HS_BASE, | |
597 | .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, | |
598 | .flags = ADDR_TYPE_RT | |
599 | }, | |
600 | { } | |
601 | }; | |
602 | ||
603 | /* l4_core ->usbhsotg interface */ | |
604 | static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { | |
cb48427e | 605 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
606 | .slave = &omap2430_usbhsotg_hwmod, |
607 | .clk = "usb_l4_ick", | |
608 | .addr = omap2430_usbhsotg_addrs, | |
609 | .user = OCP_USER_MPU, | |
610 | }; | |
611 | ||
612 | /* L4 CORE -> MMC1 interface */ | |
613 | static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { | |
cb48427e | 614 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
615 | .slave = &omap2430_mmc1_hwmod, |
616 | .clk = "mmchs1_ick", | |
617 | .addr = omap2430_mmc1_addr_space, | |
618 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
619 | }; | |
620 | ||
621 | /* L4 CORE -> MMC2 interface */ | |
622 | static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { | |
cb48427e | 623 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
624 | .slave = &omap2430_mmc2_hwmod, |
625 | .clk = "mmchs2_ick", | |
626 | .addr = omap2430_mmc2_addr_space, | |
627 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
628 | }; | |
629 | ||
844a3b63 PW |
630 | /* l4 core -> mcspi3 interface */ |
631 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { | |
cb48427e | 632 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
633 | .slave = &omap2430_mcspi3_hwmod, |
634 | .clk = "mcspi3_ick", | |
635 | .addr = omap2430_mcspi3_addr_space, | |
636 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
637 | }; | |
638 | ||
639 | /* IVA2 <- L3 interface */ | |
640 | static struct omap_hwmod_ocp_if omap2430_l3__iva = { | |
cb48427e | 641 | .master = &omap2xxx_l3_main_hwmod, |
844a3b63 | 642 | .slave = &omap2430_iva_hwmod, |
3af35fbc | 643 | .clk = "core_l3_ck", |
844a3b63 PW |
644 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
645 | }; | |
646 | ||
647 | static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { | |
648 | { | |
649 | .pa_start = 0x49018000, | |
650 | .pa_end = 0x49018000 + SZ_1K - 1, | |
651 | .flags = ADDR_TYPE_RT | |
652 | }, | |
653 | { } | |
654 | }; | |
655 | ||
656 | /* l4_wkup -> timer1 */ | |
657 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { | |
cb48427e PW |
658 | .master = &omap2xxx_l4_wkup_hwmod, |
659 | .slave = &omap2xxx_timer1_hwmod, | |
844a3b63 PW |
660 | .clk = "gpt1_ick", |
661 | .addr = omap2430_timer1_addrs, | |
662 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
663 | }; | |
664 | ||
844a3b63 PW |
665 | /* l4_wkup -> wd_timer2 */ |
666 | static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { | |
667 | { | |
668 | .pa_start = 0x49016000, | |
669 | .pa_end = 0x4901607f, | |
670 | .flags = ADDR_TYPE_RT | |
671 | }, | |
672 | { } | |
673 | }; | |
674 | ||
675 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { | |
cb48427e PW |
676 | .master = &omap2xxx_l4_wkup_hwmod, |
677 | .slave = &omap2xxx_wd_timer2_hwmod, | |
844a3b63 PW |
678 | .clk = "mpu_wdt_ick", |
679 | .addr = omap2430_wd_timer2_addrs, | |
680 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
681 | }; | |
682 | ||
844a3b63 PW |
683 | /* l4_wkup -> gpio1 */ |
684 | static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { | |
685 | { | |
686 | .pa_start = 0x4900C000, | |
687 | .pa_end = 0x4900C1ff, | |
688 | .flags = ADDR_TYPE_RT | |
689 | }, | |
690 | { } | |
691 | }; | |
692 | ||
693 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { | |
cb48427e PW |
694 | .master = &omap2xxx_l4_wkup_hwmod, |
695 | .slave = &omap2xxx_gpio1_hwmod, | |
844a3b63 PW |
696 | .clk = "gpios_ick", |
697 | .addr = omap2430_gpio1_addr_space, | |
698 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
699 | }; | |
700 | ||
701 | /* l4_wkup -> gpio2 */ | |
702 | static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { | |
703 | { | |
704 | .pa_start = 0x4900E000, | |
705 | .pa_end = 0x4900E1ff, | |
706 | .flags = ADDR_TYPE_RT | |
707 | }, | |
708 | { } | |
709 | }; | |
710 | ||
711 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { | |
cb48427e PW |
712 | .master = &omap2xxx_l4_wkup_hwmod, |
713 | .slave = &omap2xxx_gpio2_hwmod, | |
844a3b63 PW |
714 | .clk = "gpios_ick", |
715 | .addr = omap2430_gpio2_addr_space, | |
716 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
717 | }; | |
718 | ||
719 | /* l4_wkup -> gpio3 */ | |
720 | static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { | |
721 | { | |
722 | .pa_start = 0x49010000, | |
723 | .pa_end = 0x490101ff, | |
724 | .flags = ADDR_TYPE_RT | |
725 | }, | |
726 | { } | |
727 | }; | |
728 | ||
729 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { | |
cb48427e PW |
730 | .master = &omap2xxx_l4_wkup_hwmod, |
731 | .slave = &omap2xxx_gpio3_hwmod, | |
844a3b63 PW |
732 | .clk = "gpios_ick", |
733 | .addr = omap2430_gpio3_addr_space, | |
734 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
735 | }; | |
736 | ||
737 | /* l4_wkup -> gpio4 */ | |
738 | static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { | |
739 | { | |
740 | .pa_start = 0x49012000, | |
741 | .pa_end = 0x490121ff, | |
742 | .flags = ADDR_TYPE_RT | |
743 | }, | |
744 | { } | |
745 | }; | |
746 | ||
747 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { | |
cb48427e PW |
748 | .master = &omap2xxx_l4_wkup_hwmod, |
749 | .slave = &omap2xxx_gpio4_hwmod, | |
844a3b63 PW |
750 | .clk = "gpios_ick", |
751 | .addr = omap2430_gpio4_addr_space, | |
752 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
753 | }; | |
754 | ||
755 | /* l4_core -> gpio5 */ | |
756 | static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { | |
757 | { | |
758 | .pa_start = 0x480B6000, | |
759 | .pa_end = 0x480B61ff, | |
760 | .flags = ADDR_TYPE_RT | |
761 | }, | |
762 | { } | |
763 | }; | |
764 | ||
765 | static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { | |
cb48427e | 766 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
767 | .slave = &omap2430_gpio5_hwmod, |
768 | .clk = "gpio5_ick", | |
769 | .addr = omap2430_gpio5_addr_space, | |
770 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
771 | }; | |
772 | ||
773 | /* dma_system -> L3 */ | |
774 | static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { | |
775 | .master = &omap2430_dma_system_hwmod, | |
cb48427e | 776 | .slave = &omap2xxx_l3_main_hwmod, |
844a3b63 PW |
777 | .clk = "core_l3_ck", |
778 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
779 | }; | |
780 | ||
781 | /* l4_core -> dma_system */ | |
782 | static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { | |
cb48427e | 783 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
784 | .slave = &omap2430_dma_system_hwmod, |
785 | .clk = "sdma_ick", | |
786 | .addr = omap2_dma_system_addrs, | |
787 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
788 | }; | |
789 | ||
790 | /* l4_core -> mailbox */ | |
791 | static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { | |
cb48427e | 792 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
793 | .slave = &omap2430_mailbox_hwmod, |
794 | .addr = omap2_mailbox_addrs, | |
795 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
796 | }; | |
797 | ||
798 | /* l4_core -> mcbsp1 */ | |
799 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { | |
cb48427e | 800 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
801 | .slave = &omap2430_mcbsp1_hwmod, |
802 | .clk = "mcbsp1_ick", | |
803 | .addr = omap2_mcbsp1_addrs, | |
804 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
805 | }; | |
806 | ||
807 | /* l4_core -> mcbsp2 */ | |
808 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { | |
cb48427e | 809 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
810 | .slave = &omap2430_mcbsp2_hwmod, |
811 | .clk = "mcbsp2_ick", | |
812 | .addr = omap2xxx_mcbsp2_addrs, | |
813 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
814 | }; | |
815 | ||
816 | static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { | |
817 | { | |
818 | .name = "mpu", | |
819 | .pa_start = 0x4808C000, | |
820 | .pa_end = 0x4808C0ff, | |
821 | .flags = ADDR_TYPE_RT | |
822 | }, | |
823 | { } | |
824 | }; | |
825 | ||
826 | /* l4_core -> mcbsp3 */ | |
827 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { | |
cb48427e | 828 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
829 | .slave = &omap2430_mcbsp3_hwmod, |
830 | .clk = "mcbsp3_ick", | |
831 | .addr = omap2430_mcbsp3_addrs, | |
832 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
833 | }; | |
834 | ||
835 | static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { | |
836 | { | |
837 | .name = "mpu", | |
838 | .pa_start = 0x4808E000, | |
839 | .pa_end = 0x4808E0ff, | |
840 | .flags = ADDR_TYPE_RT | |
841 | }, | |
842 | { } | |
843 | }; | |
844 | ||
845 | /* l4_core -> mcbsp4 */ | |
846 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { | |
cb48427e | 847 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
848 | .slave = &omap2430_mcbsp4_hwmod, |
849 | .clk = "mcbsp4_ick", | |
850 | .addr = omap2430_mcbsp4_addrs, | |
851 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
852 | }; | |
853 | ||
854 | static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { | |
855 | { | |
856 | .name = "mpu", | |
857 | .pa_start = 0x48096000, | |
858 | .pa_end = 0x480960ff, | |
859 | .flags = ADDR_TYPE_RT | |
860 | }, | |
861 | { } | |
862 | }; | |
863 | ||
864 | /* l4_core -> mcbsp5 */ | |
865 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { | |
cb48427e | 866 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
867 | .slave = &omap2430_mcbsp5_hwmod, |
868 | .clk = "mcbsp5_ick", | |
869 | .addr = omap2430_mcbsp5_addrs, | |
870 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
871 | }; | |
872 | ||
f32bd778 PW |
873 | /* l4_core -> hdq1w */ |
874 | static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = { | |
875 | .master = &omap2xxx_l4_core_hwmod, | |
876 | .slave = &omap2430_hdq1w_hwmod, | |
877 | .clk = "hdq_ick", | |
878 | .addr = omap2_hdq1w_addr_space, | |
879 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
880 | .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, | |
881 | }; | |
882 | ||
c8d82ff6 VH |
883 | /* l4_wkup -> 32ksync_counter */ |
884 | static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = { | |
885 | { | |
886 | .pa_start = 0x49020000, | |
887 | .pa_end = 0x4902001f, | |
888 | .flags = ADDR_TYPE_RT | |
889 | }, | |
890 | { } | |
891 | }; | |
892 | ||
893 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = { | |
894 | .master = &omap2xxx_l4_wkup_hwmod, | |
895 | .slave = &omap2xxx_counter_32k_hwmod, | |
896 | .clk = "sync_32k_ick", | |
897 | .addr = omap2430_counter_32k_addrs, | |
898 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
899 | }; | |
900 | ||
0a78c5c5 | 901 | static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { |
6a29755f PW |
902 | &omap2xxx_l3_main__l4_core, |
903 | &omap2xxx_mpu__l3_main, | |
904 | &omap2xxx_dss__l3, | |
0a78c5c5 PW |
905 | &omap2430_usbhsotg__l3, |
906 | &omap2430_l4_core__i2c1, | |
907 | &omap2430_l4_core__i2c2, | |
6a29755f | 908 | &omap2xxx_l4_core__l4_wkup, |
0a78c5c5 PW |
909 | &omap2_l4_core__uart1, |
910 | &omap2_l4_core__uart2, | |
911 | &omap2_l4_core__uart3, | |
912 | &omap2430_l4_core__usbhsotg, | |
913 | &omap2430_l4_core__mmc1, | |
914 | &omap2430_l4_core__mmc2, | |
6a29755f PW |
915 | &omap2xxx_l4_core__mcspi1, |
916 | &omap2xxx_l4_core__mcspi2, | |
0a78c5c5 PW |
917 | &omap2430_l4_core__mcspi3, |
918 | &omap2430_l3__iva, | |
919 | &omap2430_l4_wkup__timer1, | |
6a29755f PW |
920 | &omap2xxx_l4_core__timer2, |
921 | &omap2xxx_l4_core__timer3, | |
922 | &omap2xxx_l4_core__timer4, | |
923 | &omap2xxx_l4_core__timer5, | |
924 | &omap2xxx_l4_core__timer6, | |
925 | &omap2xxx_l4_core__timer7, | |
926 | &omap2xxx_l4_core__timer8, | |
927 | &omap2xxx_l4_core__timer9, | |
928 | &omap2xxx_l4_core__timer10, | |
929 | &omap2xxx_l4_core__timer11, | |
930 | &omap2xxx_l4_core__timer12, | |
0a78c5c5 | 931 | &omap2430_l4_wkup__wd_timer2, |
6a29755f PW |
932 | &omap2xxx_l4_core__dss, |
933 | &omap2xxx_l4_core__dss_dispc, | |
934 | &omap2xxx_l4_core__dss_rfbi, | |
935 | &omap2xxx_l4_core__dss_venc, | |
0a78c5c5 PW |
936 | &omap2430_l4_wkup__gpio1, |
937 | &omap2430_l4_wkup__gpio2, | |
938 | &omap2430_l4_wkup__gpio3, | |
939 | &omap2430_l4_wkup__gpio4, | |
940 | &omap2430_l4_core__gpio5, | |
941 | &omap2430_dma_system__l3, | |
942 | &omap2430_l4_core__dma_system, | |
943 | &omap2430_l4_core__mailbox, | |
944 | &omap2430_l4_core__mcbsp1, | |
945 | &omap2430_l4_core__mcbsp2, | |
946 | &omap2430_l4_core__mcbsp3, | |
947 | &omap2430_l4_core__mcbsp4, | |
948 | &omap2430_l4_core__mcbsp5, | |
f32bd778 | 949 | &omap2430_l4_core__hdq1w, |
c8d82ff6 | 950 | &omap2430_l4_wkup__counter_32k, |
02bfc030 PW |
951 | NULL, |
952 | }; | |
953 | ||
7359154e PW |
954 | int __init omap2430_hwmod_init(void) |
955 | { | |
9ebfd285 | 956 | omap_hwmod_init(); |
0a78c5c5 | 957 | return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs); |
7359154e | 958 | } |