Commit | Line | Data |
---|---|---|
02bfc030 | 1 | /* |
7359154e | 2 | * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips |
02bfc030 | 3 | * |
78183f3f | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
0a78c5c5 | 5 | * Copyright (C) 2012 Texas Instruments, Inc. |
02bfc030 PW |
6 | * Paul Walmsley |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * XXX handle crossbar/shared link difference for L3? | |
7359154e | 13 | * XXX these should be marked initdata for multi-OMAP kernels |
02bfc030 | 14 | */ |
ce491cf8 | 15 | #include <plat/omap_hwmod.h> |
ce491cf8 | 16 | #include <plat/dma.h> |
046465b7 | 17 | #include <plat/serial.h> |
2004290f | 18 | #include <plat/i2c.h> |
37801b3d | 19 | #include <plat/mcbsp.h> |
7f904c78 | 20 | #include <plat/mcspi.h> |
b6b58229 | 21 | #include <plat/dmtimer.h> |
6ab8946f | 22 | #include <plat/mmc.h> |
de56dbb6 | 23 | #include <plat/l3_2xxx.h> |
02bfc030 | 24 | |
dbc04161 | 25 | #include "soc.h" |
43b40992 | 26 | #include "omap_hwmod_common_data.h" |
02bfc030 | 27 | #include "prm-regbits-24xx.h" |
165e2161 | 28 | #include "cm-regbits-24xx.h" |
ff2516fb | 29 | #include "wd_timer.h" |
02bfc030 | 30 | |
7359154e PW |
31 | /* |
32 | * OMAP2430 hardware module integration data | |
33 | * | |
844a3b63 | 34 | * All of the data in this section should be autogeneratable from the |
7359154e PW |
35 | * TI hardware database or other technical documentation. Data that |
36 | * is driver-specific or driver-kernel integration-specific belongs | |
37 | * elsewhere. | |
38 | */ | |
39 | ||
844a3b63 PW |
40 | /* |
41 | * IP blocks | |
42 | */ | |
de56dbb6 | 43 | |
844a3b63 | 44 | /* IVA2 (IVA2) */ |
3af35fbc PW |
45 | static struct omap_hwmod_rst_info omap2430_iva_resets[] = { |
46 | { .name = "logic", .rst_shift = 0 }, | |
47 | { .name = "mmu", .rst_shift = 1 }, | |
48 | }; | |
49 | ||
08072acf PW |
50 | static struct omap_hwmod omap2430_iva_hwmod = { |
51 | .name = "iva", | |
52 | .class = &iva_hwmod_class, | |
3af35fbc PW |
53 | .clkdm_name = "dsp_clkdm", |
54 | .rst_lines = omap2430_iva_resets, | |
55 | .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets), | |
56 | .main_clk = "dsp_fck", | |
08072acf PW |
57 | }; |
58 | ||
2004290f PW |
59 | /* I2C common */ |
60 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
61 | .rev_offs = 0x00, | |
62 | .sysc_offs = 0x20, | |
63 | .syss_offs = 0x10, | |
2d403fe0 PW |
64 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
65 | SYSS_HAS_RESET_STATUS), | |
2004290f PW |
66 | .sysc_fields = &omap_hwmod_sysc_type1, |
67 | }; | |
68 | ||
69 | static struct omap_hwmod_class i2c_class = { | |
70 | .name = "i2c", | |
71 | .sysc = &i2c_sysc, | |
db791a75 | 72 | .rev = OMAP_I2C_IP_VERSION_1, |
6d3c55fd | 73 | .reset = &omap_i2c_reset, |
2004290f PW |
74 | }; |
75 | ||
50ebb777 | 76 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
2004290f | 77 | .fifo_depth = 8, /* bytes */ |
4d4441a6 AG |
78 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | |
79 | OMAP_I2C_FLAG_BUS_SHIFT_2 | | |
80 | OMAP_I2C_FLAG_FORCE_19200_INT_CLK, | |
2004290f PW |
81 | }; |
82 | ||
50ebb777 | 83 | /* I2C1 */ |
2004290f PW |
84 | static struct omap_hwmod omap2430_i2c1_hwmod = { |
85 | .name = "i2c1", | |
3e600522 | 86 | .flags = HWMOD_16BIT_REG, |
0d619a89 | 87 | .mpu_irqs = omap2_i2c1_mpu_irqs, |
d826ebfa | 88 | .sdma_reqs = omap2_i2c1_sdma_reqs, |
2004290f PW |
89 | .main_clk = "i2chs1_fck", |
90 | .prcm = { | |
91 | .omap2 = { | |
92 | /* | |
93 | * NOTE: The CM_FCLKEN* and CM_ICLKEN* for | |
94 | * I2CHS IP's do not follow the usual pattern. | |
95 | * prcm_reg_id alone cannot be used to program | |
96 | * the iclk and fclk. Needs to be handled using | |
25985edc | 97 | * additional flags when clk handling is moved |
2004290f PW |
98 | * to hwmod framework. |
99 | */ | |
100 | .module_offs = CORE_MOD, | |
101 | .prcm_reg_id = 1, | |
102 | .module_bit = OMAP2430_EN_I2CHS1_SHIFT, | |
103 | .idlest_reg_id = 1, | |
104 | .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, | |
105 | }, | |
106 | }, | |
2004290f | 107 | .class = &i2c_class, |
50ebb777 | 108 | .dev_attr = &i2c_dev_attr, |
2004290f PW |
109 | }; |
110 | ||
111 | /* I2C2 */ | |
2004290f PW |
112 | static struct omap_hwmod omap2430_i2c2_hwmod = { |
113 | .name = "i2c2", | |
3e600522 | 114 | .flags = HWMOD_16BIT_REG, |
0d619a89 | 115 | .mpu_irqs = omap2_i2c2_mpu_irqs, |
d826ebfa | 116 | .sdma_reqs = omap2_i2c2_sdma_reqs, |
2004290f PW |
117 | .main_clk = "i2chs2_fck", |
118 | .prcm = { | |
119 | .omap2 = { | |
120 | .module_offs = CORE_MOD, | |
121 | .prcm_reg_id = 1, | |
122 | .module_bit = OMAP2430_EN_I2CHS2_SHIFT, | |
123 | .idlest_reg_id = 1, | |
124 | .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, | |
125 | }, | |
126 | }, | |
2004290f | 127 | .class = &i2c_class, |
50ebb777 | 128 | .dev_attr = &i2c_dev_attr, |
2004290f PW |
129 | }; |
130 | ||
aeac0e44 VC |
131 | /* gpio5 */ |
132 | static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { | |
7d7e1eba TL |
133 | { .irq = 33 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK5 */ |
134 | { .irq = -1 }, | |
aeac0e44 VC |
135 | }; |
136 | ||
aeac0e44 VC |
137 | static struct omap_hwmod omap2430_gpio5_hwmod = { |
138 | .name = "gpio5", | |
f95440ca | 139 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
aeac0e44 | 140 | .mpu_irqs = omap243x_gpio5_irqs, |
aeac0e44 VC |
141 | .main_clk = "gpio5_fck", |
142 | .prcm = { | |
143 | .omap2 = { | |
144 | .prcm_reg_id = 2, | |
145 | .module_bit = OMAP2430_EN_GPIO5_SHIFT, | |
146 | .module_offs = CORE_MOD, | |
147 | .idlest_reg_id = 2, | |
148 | .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, | |
149 | }, | |
150 | }, | |
273b9465 | 151 | .class = &omap2xxx_gpio_hwmod_class, |
cb48427e | 152 | .dev_attr = &omap2xxx_gpio_dev_attr, |
aeac0e44 VC |
153 | }; |
154 | ||
82cbd1ae MK |
155 | /* dma attributes */ |
156 | static struct omap_dma_dev_attr dma_dev_attr = { | |
157 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
158 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
159 | .lch_count = 32, | |
160 | }; | |
161 | ||
82cbd1ae MK |
162 | static struct omap_hwmod omap2430_dma_system_hwmod = { |
163 | .name = "dma", | |
273b9465 | 164 | .class = &omap2xxx_dma_hwmod_class, |
0d619a89 | 165 | .mpu_irqs = omap2_dma_system_irqs, |
82cbd1ae | 166 | .main_clk = "core_l3_ck", |
82cbd1ae | 167 | .dev_attr = &dma_dev_attr, |
82cbd1ae MK |
168 | .flags = HWMOD_NO_IDLEST, |
169 | }; | |
170 | ||
fca1ab55 | 171 | /* mailbox */ |
fca1ab55 | 172 | static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { |
7d7e1eba TL |
173 | { .irq = 26 + OMAP_INTC_START, }, |
174 | { .irq = -1 }, | |
fca1ab55 ORL |
175 | }; |
176 | ||
fca1ab55 ORL |
177 | static struct omap_hwmod omap2430_mailbox_hwmod = { |
178 | .name = "mailbox", | |
273b9465 | 179 | .class = &omap2xxx_mailbox_hwmod_class, |
fca1ab55 | 180 | .mpu_irqs = omap2430_mailbox_irqs, |
fca1ab55 ORL |
181 | .main_clk = "mailboxes_ick", |
182 | .prcm = { | |
183 | .omap2 = { | |
184 | .prcm_reg_id = 1, | |
185 | .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | |
186 | .module_offs = CORE_MOD, | |
187 | .idlest_reg_id = 1, | |
188 | .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, | |
189 | }, | |
190 | }, | |
fca1ab55 ORL |
191 | }; |
192 | ||
7f904c78 C |
193 | /* mcspi3 */ |
194 | static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { | |
7d7e1eba TL |
195 | { .irq = 91 + OMAP_INTC_START, }, |
196 | { .irq = -1 }, | |
7f904c78 C |
197 | }; |
198 | ||
199 | static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { | |
200 | { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */ | |
201 | { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */ | |
202 | { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */ | |
203 | { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */ | |
bc614958 | 204 | { .dma_req = -1 } |
7f904c78 C |
205 | }; |
206 | ||
7f904c78 C |
207 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { |
208 | .num_chipselect = 2, | |
209 | }; | |
210 | ||
211 | static struct omap_hwmod omap2430_mcspi3_hwmod = { | |
bec93811 | 212 | .name = "mcspi3", |
7f904c78 | 213 | .mpu_irqs = omap2430_mcspi3_mpu_irqs, |
7f904c78 | 214 | .sdma_reqs = omap2430_mcspi3_sdma_reqs, |
7f904c78 C |
215 | .main_clk = "mcspi3_fck", |
216 | .prcm = { | |
217 | .omap2 = { | |
218 | .module_offs = CORE_MOD, | |
219 | .prcm_reg_id = 2, | |
220 | .module_bit = OMAP2430_EN_MCSPI3_SHIFT, | |
221 | .idlest_reg_id = 2, | |
222 | .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, | |
223 | }, | |
224 | }, | |
273b9465 PW |
225 | .class = &omap2xxx_mcspi_class, |
226 | .dev_attr = &omap_mcspi3_dev_attr, | |
7f904c78 C |
227 | }; |
228 | ||
844a3b63 | 229 | /* usbhsotg */ |
44d02acf HH |
230 | static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { |
231 | .rev_offs = 0x0400, | |
232 | .sysc_offs = 0x0404, | |
233 | .syss_offs = 0x0408, | |
234 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| | |
235 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
236 | SYSC_HAS_AUTOIDLE), | |
237 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
238 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
239 | .sysc_fields = &omap_hwmod_sysc_type1, | |
240 | }; | |
241 | ||
242 | static struct omap_hwmod_class usbotg_class = { | |
243 | .name = "usbotg", | |
244 | .sysc = &omap2430_usbhsotg_sysc, | |
245 | }; | |
246 | ||
247 | /* usb_otg_hs */ | |
248 | static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { | |
249 | ||
7d7e1eba TL |
250 | { .name = "mc", .irq = 92 + OMAP_INTC_START, }, |
251 | { .name = "dma", .irq = 93 + OMAP_INTC_START, }, | |
252 | { .irq = -1 }, | |
44d02acf HH |
253 | }; |
254 | ||
255 | static struct omap_hwmod omap2430_usbhsotg_hwmod = { | |
256 | .name = "usb_otg_hs", | |
257 | .mpu_irqs = omap2430_usbhsotg_mpu_irqs, | |
44d02acf HH |
258 | .main_clk = "usbhs_ick", |
259 | .prcm = { | |
260 | .omap2 = { | |
261 | .prcm_reg_id = 1, | |
262 | .module_bit = OMAP2430_EN_USBHS_MASK, | |
263 | .module_offs = CORE_MOD, | |
264 | .idlest_reg_id = 1, | |
265 | .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, | |
266 | }, | |
267 | }, | |
44d02acf HH |
268 | .class = &usbotg_class, |
269 | /* | |
270 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially | |
271 | * broken when autoidle is enabled | |
272 | * workaround is to disable the autoidle bit at module level. | |
273 | */ | |
274 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | |
275 | | HWMOD_SWSUP_MSTANDBY, | |
44d02acf HH |
276 | }; |
277 | ||
37801b3d C |
278 | /* |
279 | * 'mcbsp' class | |
280 | * multi channel buffered serial port controller | |
281 | */ | |
282 | ||
283 | static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = { | |
284 | .rev_offs = 0x007C, | |
285 | .sysc_offs = 0x008C, | |
286 | .sysc_flags = (SYSC_HAS_SOFTRESET), | |
287 | .sysc_fields = &omap_hwmod_sysc_type1, | |
288 | }; | |
289 | ||
290 | static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { | |
291 | .name = "mcbsp", | |
292 | .sysc = &omap2430_mcbsp_sysc, | |
293 | .rev = MCBSP_CONFIG_TYPE2, | |
294 | }; | |
04aa67de | 295 | |
db382a86 PU |
296 | static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { |
297 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | |
298 | { .role = "prcm_fck", .clk = "func_96m_ck" }, | |
299 | }; | |
300 | ||
37801b3d C |
301 | /* mcbsp1 */ |
302 | static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { | |
7d7e1eba TL |
303 | { .name = "tx", .irq = 59 + OMAP_INTC_START, }, |
304 | { .name = "rx", .irq = 60 + OMAP_INTC_START, }, | |
305 | { .name = "ovr", .irq = 61 + OMAP_INTC_START, }, | |
306 | { .name = "common", .irq = 64 + OMAP_INTC_START, }, | |
307 | { .irq = -1 }, | |
37801b3d C |
308 | }; |
309 | ||
37801b3d C |
310 | static struct omap_hwmod omap2430_mcbsp1_hwmod = { |
311 | .name = "mcbsp1", | |
312 | .class = &omap2430_mcbsp_hwmod_class, | |
313 | .mpu_irqs = omap2430_mcbsp1_irqs, | |
d826ebfa | 314 | .sdma_reqs = omap2_mcbsp1_sdma_reqs, |
37801b3d C |
315 | .main_clk = "mcbsp1_fck", |
316 | .prcm = { | |
317 | .omap2 = { | |
318 | .prcm_reg_id = 1, | |
319 | .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, | |
320 | .module_offs = CORE_MOD, | |
321 | .idlest_reg_id = 1, | |
322 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, | |
323 | }, | |
324 | }, | |
db382a86 PU |
325 | .opt_clks = mcbsp_opt_clks, |
326 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | |
37801b3d C |
327 | }; |
328 | ||
329 | /* mcbsp2 */ | |
330 | static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { | |
7d7e1eba TL |
331 | { .name = "tx", .irq = 62 + OMAP_INTC_START, }, |
332 | { .name = "rx", .irq = 63 + OMAP_INTC_START, }, | |
333 | { .name = "common", .irq = 16 + OMAP_INTC_START, }, | |
334 | { .irq = -1 }, | |
37801b3d C |
335 | }; |
336 | ||
37801b3d C |
337 | static struct omap_hwmod omap2430_mcbsp2_hwmod = { |
338 | .name = "mcbsp2", | |
339 | .class = &omap2430_mcbsp_hwmod_class, | |
340 | .mpu_irqs = omap2430_mcbsp2_irqs, | |
d826ebfa | 341 | .sdma_reqs = omap2_mcbsp2_sdma_reqs, |
37801b3d C |
342 | .main_clk = "mcbsp2_fck", |
343 | .prcm = { | |
344 | .omap2 = { | |
345 | .prcm_reg_id = 1, | |
346 | .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, | |
347 | .module_offs = CORE_MOD, | |
348 | .idlest_reg_id = 1, | |
349 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, | |
350 | }, | |
351 | }, | |
db382a86 PU |
352 | .opt_clks = mcbsp_opt_clks, |
353 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | |
37801b3d C |
354 | }; |
355 | ||
356 | /* mcbsp3 */ | |
357 | static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { | |
7d7e1eba TL |
358 | { .name = "tx", .irq = 89 + OMAP_INTC_START, }, |
359 | { .name = "rx", .irq = 90 + OMAP_INTC_START, }, | |
360 | { .name = "common", .irq = 17 + OMAP_INTC_START, }, | |
361 | { .irq = -1 }, | |
37801b3d C |
362 | }; |
363 | ||
37801b3d C |
364 | static struct omap_hwmod omap2430_mcbsp3_hwmod = { |
365 | .name = "mcbsp3", | |
366 | .class = &omap2430_mcbsp_hwmod_class, | |
367 | .mpu_irqs = omap2430_mcbsp3_irqs, | |
d826ebfa | 368 | .sdma_reqs = omap2_mcbsp3_sdma_reqs, |
37801b3d C |
369 | .main_clk = "mcbsp3_fck", |
370 | .prcm = { | |
371 | .omap2 = { | |
372 | .prcm_reg_id = 1, | |
373 | .module_bit = OMAP2430_EN_MCBSP3_SHIFT, | |
374 | .module_offs = CORE_MOD, | |
375 | .idlest_reg_id = 2, | |
376 | .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, | |
377 | }, | |
378 | }, | |
db382a86 PU |
379 | .opt_clks = mcbsp_opt_clks, |
380 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | |
37801b3d C |
381 | }; |
382 | ||
383 | /* mcbsp4 */ | |
384 | static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = { | |
7d7e1eba TL |
385 | { .name = "tx", .irq = 54 + OMAP_INTC_START, }, |
386 | { .name = "rx", .irq = 55 + OMAP_INTC_START, }, | |
387 | { .name = "common", .irq = 18 + OMAP_INTC_START, }, | |
388 | { .irq = -1 }, | |
37801b3d C |
389 | }; |
390 | ||
391 | static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { | |
392 | { .name = "rx", .dma_req = 20 }, | |
393 | { .name = "tx", .dma_req = 19 }, | |
bc614958 | 394 | { .dma_req = -1 } |
37801b3d C |
395 | }; |
396 | ||
37801b3d C |
397 | static struct omap_hwmod omap2430_mcbsp4_hwmod = { |
398 | .name = "mcbsp4", | |
399 | .class = &omap2430_mcbsp_hwmod_class, | |
400 | .mpu_irqs = omap2430_mcbsp4_irqs, | |
37801b3d | 401 | .sdma_reqs = omap2430_mcbsp4_sdma_chs, |
37801b3d C |
402 | .main_clk = "mcbsp4_fck", |
403 | .prcm = { | |
404 | .omap2 = { | |
405 | .prcm_reg_id = 1, | |
406 | .module_bit = OMAP2430_EN_MCBSP4_SHIFT, | |
407 | .module_offs = CORE_MOD, | |
408 | .idlest_reg_id = 2, | |
409 | .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, | |
410 | }, | |
411 | }, | |
db382a86 PU |
412 | .opt_clks = mcbsp_opt_clks, |
413 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | |
37801b3d C |
414 | }; |
415 | ||
416 | /* mcbsp5 */ | |
417 | static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = { | |
7d7e1eba TL |
418 | { .name = "tx", .irq = 81 + OMAP_INTC_START, }, |
419 | { .name = "rx", .irq = 82 + OMAP_INTC_START, }, | |
420 | { .name = "common", .irq = 19 + OMAP_INTC_START, }, | |
421 | { .irq = -1 }, | |
37801b3d C |
422 | }; |
423 | ||
424 | static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { | |
425 | { .name = "rx", .dma_req = 22 }, | |
426 | { .name = "tx", .dma_req = 21 }, | |
bc614958 | 427 | { .dma_req = -1 } |
37801b3d C |
428 | }; |
429 | ||
37801b3d C |
430 | static struct omap_hwmod omap2430_mcbsp5_hwmod = { |
431 | .name = "mcbsp5", | |
432 | .class = &omap2430_mcbsp_hwmod_class, | |
433 | .mpu_irqs = omap2430_mcbsp5_irqs, | |
37801b3d | 434 | .sdma_reqs = omap2430_mcbsp5_sdma_chs, |
37801b3d C |
435 | .main_clk = "mcbsp5_fck", |
436 | .prcm = { | |
437 | .omap2 = { | |
438 | .prcm_reg_id = 1, | |
439 | .module_bit = OMAP2430_EN_MCBSP5_SHIFT, | |
440 | .module_offs = CORE_MOD, | |
441 | .idlest_reg_id = 2, | |
442 | .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, | |
443 | }, | |
444 | }, | |
db382a86 PU |
445 | .opt_clks = mcbsp_opt_clks, |
446 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | |
37801b3d | 447 | }; |
04aa67de | 448 | |
bce06f37 | 449 | /* MMC/SD/SDIO common */ |
bce06f37 PW |
450 | static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { |
451 | .rev_offs = 0x1fc, | |
452 | .sysc_offs = 0x10, | |
453 | .syss_offs = 0x14, | |
454 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
455 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
456 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
457 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
458 | .sysc_fields = &omap_hwmod_sysc_type1, | |
459 | }; | |
460 | ||
461 | static struct omap_hwmod_class omap2430_mmc_class = { | |
462 | .name = "mmc", | |
463 | .sysc = &omap2430_mmc_sysc, | |
464 | }; | |
465 | ||
466 | /* MMC/SD/SDIO1 */ | |
bce06f37 | 467 | static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { |
7d7e1eba TL |
468 | { .irq = 83 + OMAP_INTC_START, }, |
469 | { .irq = -1 }, | |
bce06f37 PW |
470 | }; |
471 | ||
472 | static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = { | |
473 | { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */ | |
474 | { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */ | |
bc614958 | 475 | { .dma_req = -1 } |
bce06f37 PW |
476 | }; |
477 | ||
478 | static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { | |
479 | { .role = "dbck", .clk = "mmchsdb1_fck" }, | |
480 | }; | |
481 | ||
6ab8946f KK |
482 | static struct omap_mmc_dev_attr mmc1_dev_attr = { |
483 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
484 | }; | |
485 | ||
bce06f37 PW |
486 | static struct omap_hwmod omap2430_mmc1_hwmod = { |
487 | .name = "mmc1", | |
488 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
489 | .mpu_irqs = omap2430_mmc1_mpu_irqs, | |
bce06f37 | 490 | .sdma_reqs = omap2430_mmc1_sdma_reqs, |
bce06f37 PW |
491 | .opt_clks = omap2430_mmc1_opt_clks, |
492 | .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), | |
493 | .main_clk = "mmchs1_fck", | |
494 | .prcm = { | |
495 | .omap2 = { | |
496 | .module_offs = CORE_MOD, | |
497 | .prcm_reg_id = 2, | |
498 | .module_bit = OMAP2430_EN_MMCHS1_SHIFT, | |
499 | .idlest_reg_id = 2, | |
500 | .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT, | |
501 | }, | |
502 | }, | |
6ab8946f | 503 | .dev_attr = &mmc1_dev_attr, |
bce06f37 | 504 | .class = &omap2430_mmc_class, |
bce06f37 PW |
505 | }; |
506 | ||
507 | /* MMC/SD/SDIO2 */ | |
bce06f37 | 508 | static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { |
7d7e1eba TL |
509 | { .irq = 86 + OMAP_INTC_START, }, |
510 | { .irq = -1 }, | |
bce06f37 PW |
511 | }; |
512 | ||
513 | static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = { | |
514 | { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */ | |
515 | { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */ | |
bc614958 | 516 | { .dma_req = -1 } |
bce06f37 PW |
517 | }; |
518 | ||
519 | static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { | |
520 | { .role = "dbck", .clk = "mmchsdb2_fck" }, | |
521 | }; | |
522 | ||
bce06f37 PW |
523 | static struct omap_hwmod omap2430_mmc2_hwmod = { |
524 | .name = "mmc2", | |
525 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
526 | .mpu_irqs = omap2430_mmc2_mpu_irqs, | |
bce06f37 | 527 | .sdma_reqs = omap2430_mmc2_sdma_reqs, |
bce06f37 PW |
528 | .opt_clks = omap2430_mmc2_opt_clks, |
529 | .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), | |
530 | .main_clk = "mmchs2_fck", | |
531 | .prcm = { | |
532 | .omap2 = { | |
533 | .module_offs = CORE_MOD, | |
534 | .prcm_reg_id = 2, | |
535 | .module_bit = OMAP2430_EN_MMCHS2_SHIFT, | |
536 | .idlest_reg_id = 2, | |
537 | .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, | |
538 | }, | |
539 | }, | |
bce06f37 | 540 | .class = &omap2430_mmc_class, |
bce06f37 | 541 | }; |
04aa67de | 542 | |
f32bd778 PW |
543 | /* HDQ1W/1-wire */ |
544 | static struct omap_hwmod omap2430_hdq1w_hwmod = { | |
545 | .name = "hdq1w", | |
546 | .mpu_irqs = omap2_hdq1w_mpu_irqs, | |
547 | .main_clk = "hdq_fck", | |
548 | .prcm = { | |
549 | .omap2 = { | |
550 | .module_offs = CORE_MOD, | |
551 | .prcm_reg_id = 1, | |
552 | .module_bit = OMAP24XX_EN_HDQ_SHIFT, | |
553 | .idlest_reg_id = 1, | |
554 | .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT, | |
555 | }, | |
556 | }, | |
557 | .class = &omap2_hdq1w_class, | |
558 | }; | |
559 | ||
844a3b63 PW |
560 | /* |
561 | * interfaces | |
562 | */ | |
563 | ||
564 | /* L3 -> L4_CORE interface */ | |
844a3b63 PW |
565 | /* l3_core -> usbhsotg interface */ |
566 | static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { | |
567 | .master = &omap2430_usbhsotg_hwmod, | |
cb48427e | 568 | .slave = &omap2xxx_l3_main_hwmod, |
844a3b63 PW |
569 | .clk = "core_l3_ck", |
570 | .user = OCP_USER_MPU, | |
571 | }; | |
572 | ||
573 | /* L4 CORE -> I2C1 interface */ | |
574 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { | |
cb48427e | 575 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
576 | .slave = &omap2430_i2c1_hwmod, |
577 | .clk = "i2c1_ick", | |
578 | .addr = omap2_i2c1_addr_space, | |
579 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
580 | }; | |
581 | ||
582 | /* L4 CORE -> I2C2 interface */ | |
583 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { | |
cb48427e | 584 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
585 | .slave = &omap2430_i2c2_hwmod, |
586 | .clk = "i2c2_ick", | |
587 | .addr = omap2_i2c2_addr_space, | |
588 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
589 | }; | |
590 | ||
844a3b63 PW |
591 | static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { |
592 | { | |
593 | .pa_start = OMAP243X_HS_BASE, | |
594 | .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, | |
595 | .flags = ADDR_TYPE_RT | |
596 | }, | |
597 | { } | |
598 | }; | |
599 | ||
600 | /* l4_core ->usbhsotg interface */ | |
601 | static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { | |
cb48427e | 602 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
603 | .slave = &omap2430_usbhsotg_hwmod, |
604 | .clk = "usb_l4_ick", | |
605 | .addr = omap2430_usbhsotg_addrs, | |
606 | .user = OCP_USER_MPU, | |
607 | }; | |
608 | ||
609 | /* L4 CORE -> MMC1 interface */ | |
610 | static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { | |
cb48427e | 611 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
612 | .slave = &omap2430_mmc1_hwmod, |
613 | .clk = "mmchs1_ick", | |
614 | .addr = omap2430_mmc1_addr_space, | |
615 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
616 | }; | |
617 | ||
618 | /* L4 CORE -> MMC2 interface */ | |
619 | static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { | |
cb48427e | 620 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
621 | .slave = &omap2430_mmc2_hwmod, |
622 | .clk = "mmchs2_ick", | |
623 | .addr = omap2430_mmc2_addr_space, | |
624 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
625 | }; | |
626 | ||
844a3b63 PW |
627 | /* l4 core -> mcspi3 interface */ |
628 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { | |
cb48427e | 629 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
630 | .slave = &omap2430_mcspi3_hwmod, |
631 | .clk = "mcspi3_ick", | |
632 | .addr = omap2430_mcspi3_addr_space, | |
633 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
634 | }; | |
635 | ||
636 | /* IVA2 <- L3 interface */ | |
637 | static struct omap_hwmod_ocp_if omap2430_l3__iva = { | |
cb48427e | 638 | .master = &omap2xxx_l3_main_hwmod, |
844a3b63 | 639 | .slave = &omap2430_iva_hwmod, |
3af35fbc | 640 | .clk = "core_l3_ck", |
844a3b63 PW |
641 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
642 | }; | |
643 | ||
644 | static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { | |
645 | { | |
646 | .pa_start = 0x49018000, | |
647 | .pa_end = 0x49018000 + SZ_1K - 1, | |
648 | .flags = ADDR_TYPE_RT | |
649 | }, | |
650 | { } | |
651 | }; | |
652 | ||
653 | /* l4_wkup -> timer1 */ | |
654 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { | |
cb48427e PW |
655 | .master = &omap2xxx_l4_wkup_hwmod, |
656 | .slave = &omap2xxx_timer1_hwmod, | |
844a3b63 PW |
657 | .clk = "gpt1_ick", |
658 | .addr = omap2430_timer1_addrs, | |
659 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
660 | }; | |
661 | ||
844a3b63 PW |
662 | /* l4_wkup -> wd_timer2 */ |
663 | static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { | |
664 | { | |
665 | .pa_start = 0x49016000, | |
666 | .pa_end = 0x4901607f, | |
667 | .flags = ADDR_TYPE_RT | |
668 | }, | |
669 | { } | |
670 | }; | |
671 | ||
672 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { | |
cb48427e PW |
673 | .master = &omap2xxx_l4_wkup_hwmod, |
674 | .slave = &omap2xxx_wd_timer2_hwmod, | |
844a3b63 PW |
675 | .clk = "mpu_wdt_ick", |
676 | .addr = omap2430_wd_timer2_addrs, | |
677 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
678 | }; | |
679 | ||
844a3b63 PW |
680 | /* l4_wkup -> gpio1 */ |
681 | static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { | |
682 | { | |
683 | .pa_start = 0x4900C000, | |
684 | .pa_end = 0x4900C1ff, | |
685 | .flags = ADDR_TYPE_RT | |
686 | }, | |
687 | { } | |
688 | }; | |
689 | ||
690 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { | |
cb48427e PW |
691 | .master = &omap2xxx_l4_wkup_hwmod, |
692 | .slave = &omap2xxx_gpio1_hwmod, | |
844a3b63 PW |
693 | .clk = "gpios_ick", |
694 | .addr = omap2430_gpio1_addr_space, | |
695 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
696 | }; | |
697 | ||
698 | /* l4_wkup -> gpio2 */ | |
699 | static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { | |
700 | { | |
701 | .pa_start = 0x4900E000, | |
702 | .pa_end = 0x4900E1ff, | |
703 | .flags = ADDR_TYPE_RT | |
704 | }, | |
705 | { } | |
706 | }; | |
707 | ||
708 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { | |
cb48427e PW |
709 | .master = &omap2xxx_l4_wkup_hwmod, |
710 | .slave = &omap2xxx_gpio2_hwmod, | |
844a3b63 PW |
711 | .clk = "gpios_ick", |
712 | .addr = omap2430_gpio2_addr_space, | |
713 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
714 | }; | |
715 | ||
716 | /* l4_wkup -> gpio3 */ | |
717 | static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { | |
718 | { | |
719 | .pa_start = 0x49010000, | |
720 | .pa_end = 0x490101ff, | |
721 | .flags = ADDR_TYPE_RT | |
722 | }, | |
723 | { } | |
724 | }; | |
725 | ||
726 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { | |
cb48427e PW |
727 | .master = &omap2xxx_l4_wkup_hwmod, |
728 | .slave = &omap2xxx_gpio3_hwmod, | |
844a3b63 PW |
729 | .clk = "gpios_ick", |
730 | .addr = omap2430_gpio3_addr_space, | |
731 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
732 | }; | |
733 | ||
734 | /* l4_wkup -> gpio4 */ | |
735 | static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { | |
736 | { | |
737 | .pa_start = 0x49012000, | |
738 | .pa_end = 0x490121ff, | |
739 | .flags = ADDR_TYPE_RT | |
740 | }, | |
741 | { } | |
742 | }; | |
743 | ||
744 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { | |
cb48427e PW |
745 | .master = &omap2xxx_l4_wkup_hwmod, |
746 | .slave = &omap2xxx_gpio4_hwmod, | |
844a3b63 PW |
747 | .clk = "gpios_ick", |
748 | .addr = omap2430_gpio4_addr_space, | |
749 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
750 | }; | |
751 | ||
752 | /* l4_core -> gpio5 */ | |
753 | static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { | |
754 | { | |
755 | .pa_start = 0x480B6000, | |
756 | .pa_end = 0x480B61ff, | |
757 | .flags = ADDR_TYPE_RT | |
758 | }, | |
759 | { } | |
760 | }; | |
761 | ||
762 | static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { | |
cb48427e | 763 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
764 | .slave = &omap2430_gpio5_hwmod, |
765 | .clk = "gpio5_ick", | |
766 | .addr = omap2430_gpio5_addr_space, | |
767 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
768 | }; | |
769 | ||
770 | /* dma_system -> L3 */ | |
771 | static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { | |
772 | .master = &omap2430_dma_system_hwmod, | |
cb48427e | 773 | .slave = &omap2xxx_l3_main_hwmod, |
844a3b63 PW |
774 | .clk = "core_l3_ck", |
775 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
776 | }; | |
777 | ||
778 | /* l4_core -> dma_system */ | |
779 | static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { | |
cb48427e | 780 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
781 | .slave = &omap2430_dma_system_hwmod, |
782 | .clk = "sdma_ick", | |
783 | .addr = omap2_dma_system_addrs, | |
784 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
785 | }; | |
786 | ||
787 | /* l4_core -> mailbox */ | |
788 | static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { | |
cb48427e | 789 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
790 | .slave = &omap2430_mailbox_hwmod, |
791 | .addr = omap2_mailbox_addrs, | |
792 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
793 | }; | |
794 | ||
795 | /* l4_core -> mcbsp1 */ | |
796 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { | |
cb48427e | 797 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
798 | .slave = &omap2430_mcbsp1_hwmod, |
799 | .clk = "mcbsp1_ick", | |
800 | .addr = omap2_mcbsp1_addrs, | |
801 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
802 | }; | |
803 | ||
804 | /* l4_core -> mcbsp2 */ | |
805 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { | |
cb48427e | 806 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
807 | .slave = &omap2430_mcbsp2_hwmod, |
808 | .clk = "mcbsp2_ick", | |
809 | .addr = omap2xxx_mcbsp2_addrs, | |
810 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
811 | }; | |
812 | ||
813 | static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { | |
814 | { | |
815 | .name = "mpu", | |
816 | .pa_start = 0x4808C000, | |
817 | .pa_end = 0x4808C0ff, | |
818 | .flags = ADDR_TYPE_RT | |
819 | }, | |
820 | { } | |
821 | }; | |
822 | ||
823 | /* l4_core -> mcbsp3 */ | |
824 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { | |
cb48427e | 825 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
826 | .slave = &omap2430_mcbsp3_hwmod, |
827 | .clk = "mcbsp3_ick", | |
828 | .addr = omap2430_mcbsp3_addrs, | |
829 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
830 | }; | |
831 | ||
832 | static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { | |
833 | { | |
834 | .name = "mpu", | |
835 | .pa_start = 0x4808E000, | |
836 | .pa_end = 0x4808E0ff, | |
837 | .flags = ADDR_TYPE_RT | |
838 | }, | |
839 | { } | |
840 | }; | |
841 | ||
842 | /* l4_core -> mcbsp4 */ | |
843 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { | |
cb48427e | 844 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
845 | .slave = &omap2430_mcbsp4_hwmod, |
846 | .clk = "mcbsp4_ick", | |
847 | .addr = omap2430_mcbsp4_addrs, | |
848 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
849 | }; | |
850 | ||
851 | static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { | |
852 | { | |
853 | .name = "mpu", | |
854 | .pa_start = 0x48096000, | |
855 | .pa_end = 0x480960ff, | |
856 | .flags = ADDR_TYPE_RT | |
857 | }, | |
858 | { } | |
859 | }; | |
860 | ||
861 | /* l4_core -> mcbsp5 */ | |
862 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { | |
cb48427e | 863 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
864 | .slave = &omap2430_mcbsp5_hwmod, |
865 | .clk = "mcbsp5_ick", | |
866 | .addr = omap2430_mcbsp5_addrs, | |
867 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
868 | }; | |
869 | ||
f32bd778 PW |
870 | /* l4_core -> hdq1w */ |
871 | static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = { | |
872 | .master = &omap2xxx_l4_core_hwmod, | |
873 | .slave = &omap2430_hdq1w_hwmod, | |
874 | .clk = "hdq_ick", | |
875 | .addr = omap2_hdq1w_addr_space, | |
876 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
877 | .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, | |
878 | }; | |
879 | ||
c8d82ff6 VH |
880 | /* l4_wkup -> 32ksync_counter */ |
881 | static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = { | |
882 | { | |
883 | .pa_start = 0x49020000, | |
884 | .pa_end = 0x4902001f, | |
885 | .flags = ADDR_TYPE_RT | |
886 | }, | |
887 | { } | |
888 | }; | |
889 | ||
49484a60 AM |
890 | static struct omap_hwmod_addr_space omap2430_gpmc_addrs[] = { |
891 | { | |
892 | .pa_start = 0x6e000000, | |
893 | .pa_end = 0x6e000fff, | |
894 | .flags = ADDR_TYPE_RT | |
895 | }, | |
896 | { } | |
897 | }; | |
898 | ||
c8d82ff6 VH |
899 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = { |
900 | .master = &omap2xxx_l4_wkup_hwmod, | |
901 | .slave = &omap2xxx_counter_32k_hwmod, | |
902 | .clk = "sync_32k_ick", | |
903 | .addr = omap2430_counter_32k_addrs, | |
904 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
905 | }; | |
906 | ||
49484a60 AM |
907 | static struct omap_hwmod_ocp_if omap2430_l3__gpmc = { |
908 | .master = &omap2xxx_l3_main_hwmod, | |
909 | .slave = &omap2xxx_gpmc_hwmod, | |
910 | .clk = "core_l3_ck", | |
911 | .addr = omap2430_gpmc_addrs, | |
912 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
913 | }; | |
914 | ||
0a78c5c5 | 915 | static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { |
6a29755f PW |
916 | &omap2xxx_l3_main__l4_core, |
917 | &omap2xxx_mpu__l3_main, | |
918 | &omap2xxx_dss__l3, | |
0a78c5c5 PW |
919 | &omap2430_usbhsotg__l3, |
920 | &omap2430_l4_core__i2c1, | |
921 | &omap2430_l4_core__i2c2, | |
6a29755f | 922 | &omap2xxx_l4_core__l4_wkup, |
0a78c5c5 PW |
923 | &omap2_l4_core__uart1, |
924 | &omap2_l4_core__uart2, | |
925 | &omap2_l4_core__uart3, | |
926 | &omap2430_l4_core__usbhsotg, | |
927 | &omap2430_l4_core__mmc1, | |
928 | &omap2430_l4_core__mmc2, | |
6a29755f PW |
929 | &omap2xxx_l4_core__mcspi1, |
930 | &omap2xxx_l4_core__mcspi2, | |
0a78c5c5 PW |
931 | &omap2430_l4_core__mcspi3, |
932 | &omap2430_l3__iva, | |
933 | &omap2430_l4_wkup__timer1, | |
6a29755f PW |
934 | &omap2xxx_l4_core__timer2, |
935 | &omap2xxx_l4_core__timer3, | |
936 | &omap2xxx_l4_core__timer4, | |
937 | &omap2xxx_l4_core__timer5, | |
938 | &omap2xxx_l4_core__timer6, | |
939 | &omap2xxx_l4_core__timer7, | |
940 | &omap2xxx_l4_core__timer8, | |
941 | &omap2xxx_l4_core__timer9, | |
942 | &omap2xxx_l4_core__timer10, | |
943 | &omap2xxx_l4_core__timer11, | |
944 | &omap2xxx_l4_core__timer12, | |
0a78c5c5 | 945 | &omap2430_l4_wkup__wd_timer2, |
6a29755f PW |
946 | &omap2xxx_l4_core__dss, |
947 | &omap2xxx_l4_core__dss_dispc, | |
948 | &omap2xxx_l4_core__dss_rfbi, | |
949 | &omap2xxx_l4_core__dss_venc, | |
0a78c5c5 PW |
950 | &omap2430_l4_wkup__gpio1, |
951 | &omap2430_l4_wkup__gpio2, | |
952 | &omap2430_l4_wkup__gpio3, | |
953 | &omap2430_l4_wkup__gpio4, | |
954 | &omap2430_l4_core__gpio5, | |
955 | &omap2430_dma_system__l3, | |
956 | &omap2430_l4_core__dma_system, | |
957 | &omap2430_l4_core__mailbox, | |
958 | &omap2430_l4_core__mcbsp1, | |
959 | &omap2430_l4_core__mcbsp2, | |
960 | &omap2430_l4_core__mcbsp3, | |
961 | &omap2430_l4_core__mcbsp4, | |
962 | &omap2430_l4_core__mcbsp5, | |
f32bd778 | 963 | &omap2430_l4_core__hdq1w, |
c8d82ff6 | 964 | &omap2430_l4_wkup__counter_32k, |
49484a60 | 965 | &omap2430_l3__gpmc, |
02bfc030 PW |
966 | NULL, |
967 | }; | |
968 | ||
7359154e PW |
969 | int __init omap2430_hwmod_init(void) |
970 | { | |
9ebfd285 | 971 | omap_hwmod_init(); |
0a78c5c5 | 972 | return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs); |
7359154e | 973 | } |