[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_2xxx_3xxx_ipblock_data.c

/*
 * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
 *
 * Copyright (C) 2011 Nokia Corporation
 * Copyright (C) 2012 Texas Instruments, Inc.
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <plat/omap_hwmod.h>
#include <plat/serial.h>
#include <plat/dma.h>
#include <plat/common.h>
#include <plat/hdq1w.h>

#include "omap_hwmod_common_data.h"

/* UART */

static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
	.rev_offs	= 0x50,
	.sysc_offs	= 0x54,
	.syss_offs	= 0x58,
	.sysc_flags	= (SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2_uart_class = {
	.name	= "uart",
	.sysc	= &omap2_uart_sysc,
};

/*
 * 'dss' class
 * display sub-system
 */

static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
			   SYSS_HAS_RESET_STATUS),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2_dss_hwmod_class = {
	.name	= "dss",
	.sysc	= &omap2_dss_sysc,
	.reset	= omap_dss_reset,
};

/*
 * 'rfbi' class
 * remote frame buffer interface
 */

static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			   SYSC_HAS_AUTOIDLE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2_rfbi_hwmod_class = {
	.name	= "rfbi",
	.sysc	= &omap2_rfbi_sysc,
};

/*
 * 'venc' class
 * video encoder
 */

struct omap_hwmod_class omap2_venc_hwmod_class = {
	.name = "venc",
};


/* Common DMA request line data */
struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
	{ .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
	{ .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
	{ .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
	{ .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
	{ .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
	{ .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
	{ .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
	{ .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
	{ .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
	{ .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
	{ .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
	{ .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
	{ .name = "rx", .dma_req = 32 },
	{ .name = "tx", .dma_req = 31 },
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
	{ .name = "rx", .dma_req = 34 },
	{ .name = "tx", .dma_req = 33 },
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
	{ .name = "rx", .dma_req = 18 },
	{ .name = "tx", .dma_req = 17 },
	{ .dma_req = -1 }
};

/* Other IP block data */


/*
 * omap_hwmod class data
 */

struct omap_hwmod_class l3_hwmod_class = {
	.name = "l3"
};

struct omap_hwmod_class l4_hwmod_class = {
	.name = "l4"
};

struct omap_hwmod_class mpu_hwmod_class = {
	.name = "mpu"
};

struct omap_hwmod_class iva_hwmod_class = {
	.name = "iva"
};

/* Common MPU IRQ line data */

struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
	{ .irq = 37 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
	{ .irq = 38 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
	{ .irq = 39 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
	{ .irq = 40 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
	{ .irq = 41 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
	{ .irq = 42 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
	{ .irq = 43 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
	{ .irq = 44 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
	{ .irq = 45 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
	{ .irq = 46 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
	{ .irq = 47 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
	{ .irq = 72 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
	{ .irq = 73 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
	{ .irq = 74 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
	{ .irq = 25 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
	{ .irq = 56 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
	{ .irq = 57 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
	{ .irq = 29 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK1 */
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
	{ .irq = 30 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK2 */
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
	{ .irq = 31 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK3 */
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
	{ .irq = 32 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK4 */
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
	{ .name = "0", .irq = 12 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ0 */
	{ .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */
	{ .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */
	{ .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
	{ .irq = 65 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
	{ .irq = 66 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
	.rev_offs	= 0x0,
	.sysc_offs	= 0x14,
	.syss_offs	= 0x18,
	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
			   SYSS_HAS_RESET_STATUS),
	.sysc_fields    = &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2_hdq1w_class = {
	.name	= "hdq1w",
	.sysc	= &omap2_hdq1w_sysc,
	.reset	= &omap_hdq1w_reset,
};

struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = {
	{ .irq = 58 + OMAP_INTC_START, },
	{ .irq = -1 },
};
Commit	Line	Data
0d619a89 PW	1	/*
	2	* omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
	3	*
	4	* Copyright (C) 2011 Nokia Corporation
03d830e8	5	* Copyright (C) 2012 Texas Instruments, Inc.
0d619a89 PW	6	* Paul Walmsley
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12	#include <plat/omap_hwmod.h>
	13	#include <plat/serial.h>
d826ebfa	14	#include <plat/dma.h>
13662dc5	15	#include <plat/common.h>
03d830e8	16	#include <plat/hdq1w.h>
0d619a89	17
0d619a89 PW	18	#include "omap_hwmod_common_data.h"
0d619a89 PW	19
273b9465 PW	20	/* UART */
	21
	22	static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
	23	.rev_offs = 0x50,
	24	.sysc_offs = 0x54,
	25	.syss_offs = 0x58,
	26	.sysc_flags = (SYSC_HAS_SIDLEMODE \|
	27	SYSC_HAS_ENAWAKEUP \| SYSC_HAS_SOFTRESET \|
	28	SYSC_HAS_AUTOIDLE \| SYSS_HAS_RESET_STATUS),
	29	.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
	30	.sysc_fields = &omap_hwmod_sysc_type1,
	31	};
	32
	33	struct omap_hwmod_class omap2_uart_class = {
	34	.name = "uart",
	35	.sysc = &omap2_uart_sysc,
	36	};
	37
	38	/*
	39	* 'dss' class
	40	* display sub-system
	41	*/
	42
	43	static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
	44	.rev_offs = 0x0000,
	45	.sysc_offs = 0x0010,
	46	.syss_offs = 0x0014,
3ce32676 TV	47	.sysc_flags = (SYSC_HAS_SOFTRESET \| SYSC_HAS_AUTOIDLE \|
3ce32676 TV	48	SYSS_HAS_RESET_STATUS),
273b9465 PW	49	.sysc_fields = &omap_hwmod_sysc_type1,
	50	};
	51
	52	struct omap_hwmod_class omap2_dss_hwmod_class = {
	53	.name = "dss",
	54	.sysc = &omap2_dss_sysc,
13662dc5	55	.reset = omap_dss_reset,
273b9465 PW	56	};
273b9465 PW	57
273b9465 PW	58	/*
	59	* 'rfbi' class
	60	* remote frame buffer interface
	61	*/
	62
	63	static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
	64	.rev_offs = 0x0000,
	65	.sysc_offs = 0x0010,
	66	.syss_offs = 0x0014,
	67	.sysc_flags = (SYSC_HAS_SIDLEMODE \| SYSC_HAS_SOFTRESET \|
	68	SYSC_HAS_AUTOIDLE),
	69	.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
	70	.sysc_fields = &omap_hwmod_sysc_type1,
	71	};
	72
	73	struct omap_hwmod_class omap2_rfbi_hwmod_class = {
	74	.name = "rfbi",
	75	.sysc = &omap2_rfbi_sysc,
	76	};
	77
	78	/*
	79	* 'venc' class
	80	* video encoder
	81	*/
	82
	83	struct omap_hwmod_class omap2_venc_hwmod_class = {
	84	.name = "venc",
	85	};
	86
	87
	88	/* Common DMA request line data */
	89	struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
	90	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
	91	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
	92	{ .dma_req = -1 }
	93	};
	94
	95	struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
	96	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
	97	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
	98	{ .dma_req = -1 }
	99	};
	100
	101	struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
	102	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
	103	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
	104	{ .dma_req = -1 }
	105	};
	106
	107	struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
	108	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
	109	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
	110	{ .dma_req = -1 }
	111	};
	112
	113	struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
	114	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
	115	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
	116	{ .dma_req = -1 }
	117	};
	118
	119	struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
	120	{ .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
	121	{ .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
122	{ .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
123	{ .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
124	{ .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
125	{ .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
126	{ .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
127	{ .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
128	{ .dma_req = -1 }
129	};
130
131	struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
132	{ .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
133	{ .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
134	{ .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
135	{ .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
136	{ .dma_req = -1 }
137	};
138
139	struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
140	{ .name = "rx", .dma_req = 32 },
141	{ .name = "tx", .dma_req = 31 },
142	{ .dma_req = -1 }
143	};
144
145	struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
146	{ .name = "rx", .dma_req = 34 },
147	{ .name = "tx", .dma_req = 33 },
148	{ .dma_req = -1 }
149	};
150
151	struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
152	{ .name = "rx", .dma_req = 18 },
153	{ .name = "tx", .dma_req = 17 },
154	{ .dma_req = -1 }
155	};
156
157	/* Other IP block data */
158
d826ebfa PW	159
	160	/*
	161	* omap_hwmod class data
	162	*/
	163
	164	struct omap_hwmod_class l3_hwmod_class = {
	165	.name = "l3"
	166	};
	167
	168	struct omap_hwmod_class l4_hwmod_class = {
	169	.name = "l4"
	170	};
	171
	172	struct omap_hwmod_class mpu_hwmod_class = {
	173	.name = "mpu"
	174	};
	175
	176	struct omap_hwmod_class iva_hwmod_class = {
	177	.name = "iva"
	178	};
	179
	180	/* Common MPU IRQ line data */
	181
0d619a89	182	struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
7d7e1eba TL	183	{ .irq = 37 + OMAP_INTC_START, },
7d7e1eba TL	184	{ .irq = -1 },
0d619a89 PW	185	};
	186
	187	struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
7d7e1eba TL	188	{ .irq = 38 + OMAP_INTC_START, },
7d7e1eba TL	189	{ .irq = -1 },
0d619a89 PW	190	};
	191
	192	struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
7d7e1eba TL	193	{ .irq = 39 + OMAP_INTC_START, },
7d7e1eba TL	194	{ .irq = -1 },
0d619a89 PW	195	};
	196
	197	struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
7d7e1eba TL	198	{ .irq = 40 + OMAP_INTC_START, },
7d7e1eba TL	199	{ .irq = -1 },
0d619a89 PW	200	};
	201
	202	struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
7d7e1eba TL	203	{ .irq = 41 + OMAP_INTC_START, },
7d7e1eba TL	204	{ .irq = -1 },
0d619a89 PW	205	};
	206
	207	struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
7d7e1eba TL	208	{ .irq = 42 + OMAP_INTC_START, },
7d7e1eba TL	209	{ .irq = -1 },
0d619a89 PW	210	};
	211
	212	struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
7d7e1eba TL	213	{ .irq = 43 + OMAP_INTC_START, },
7d7e1eba TL	214	{ .irq = -1 },
0d619a89 PW	215	};
	216
	217	struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
7d7e1eba TL	218	{ .irq = 44 + OMAP_INTC_START, },
7d7e1eba TL	219	{ .irq = -1 },
0d619a89 PW	220	};
	221
	222	struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
7d7e1eba TL	223	{ .irq = 45 + OMAP_INTC_START, },
7d7e1eba TL	224	{ .irq = -1 },
0d619a89 PW	225	};
	226
	227	struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
7d7e1eba TL	228	{ .irq = 46 + OMAP_INTC_START, },
7d7e1eba TL	229	{ .irq = -1 },
0d619a89 PW	230	};
	231
	232	struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
7d7e1eba TL	233	{ .irq = 47 + OMAP_INTC_START, },
7d7e1eba TL	234	{ .irq = -1 },
0d619a89 PW	235	};
	236
	237	struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
7d7e1eba TL	238	{ .irq = 72 + OMAP_INTC_START, },
7d7e1eba TL	239	{ .irq = -1 },
0d619a89 PW	240	};
	241
	242	struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
7d7e1eba TL	243	{ .irq = 73 + OMAP_INTC_START, },
7d7e1eba TL	244	{ .irq = -1 },
0d619a89 PW	245	};
	246
	247	struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
7d7e1eba TL	248	{ .irq = 74 + OMAP_INTC_START, },
7d7e1eba TL	249	{ .irq = -1 },
0d619a89 PW	250	};
	251
	252	struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
7d7e1eba TL	253	{ .irq = 25 + OMAP_INTC_START, },
7d7e1eba TL	254	{ .irq = -1 },
0d619a89 PW	255	};
	256
	257	struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
7d7e1eba TL	258	{ .irq = 56 + OMAP_INTC_START, },
7d7e1eba TL	259	{ .irq = -1 },
0d619a89 PW	260	};
	261
	262	struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
7d7e1eba TL	263	{ .irq = 57 + OMAP_INTC_START, },
7d7e1eba TL	264	{ .irq = -1 },
0d619a89 PW	265	};
	266
	267	struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
7d7e1eba TL	268	{ .irq = 29 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK1 */
7d7e1eba TL	269	{ .irq = -1 },
0d619a89 PW	270	};
	271
	272	struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
7d7e1eba TL	273	{ .irq = 30 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK2 */
7d7e1eba TL	274	{ .irq = -1 },
0d619a89 PW	275	};
	276
	277	struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
7d7e1eba TL	278	{ .irq = 31 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK3 */
7d7e1eba TL	279	{ .irq = -1 },
0d619a89 PW	280	};
	281
	282	struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
7d7e1eba TL	283	{ .irq = 32 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK4 */
7d7e1eba TL	284	{ .irq = -1 },
0d619a89 PW	285	};
	286
	287	struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
7d7e1eba TL	288	{ .name = "0", .irq = 12 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ0 */
	289	{ .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */
	290	{ .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */
	291	{ .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */
	292	{ .irq = -1 },
0d619a89 PW	293	};
	294
	295	struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
7d7e1eba TL	296	{ .irq = 65 + OMAP_INTC_START, },
7d7e1eba TL	297	{ .irq = -1 },
0d619a89 PW	298	};
	299
	300	struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
7d7e1eba TL	301	{ .irq = 66 + OMAP_INTC_START, },
7d7e1eba TL	302	{ .irq = -1 },
0d619a89 PW	303	};
0d619a89 PW	304
03d830e8 PW	305	struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
	306	.rev_offs = 0x0,
	307	.sysc_offs = 0x14,
	308	.syss_offs = 0x18,
	309	.sysc_flags = (SYSC_HAS_SOFTRESET \| SYSC_HAS_AUTOIDLE \|
	310	SYSS_HAS_RESET_STATUS),
	311	.sysc_fields = &omap_hwmod_sysc_type1,
	312	};
	313
	314	struct omap_hwmod_class omap2_hdq1w_class = {
	315	.name = "hdq1w",
	316	.sysc = &omap2_hdq1w_sysc,
	317	.reset = &omap_hdq1w_reset,
	318	};
	319
	320	struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = {
7d7e1eba TL	321	{ .irq = 58 + OMAP_INTC_START, },
7d7e1eba TL	322	{ .irq = -1 },
03d830e8 PW	323	};
03d830e8 PW	324