[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_2xxx_3xxx_ipblock_data.c

/*
 * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
 *
 * Copyright (C) 2011 Nokia Corporation
 * Copyright (C) 2012 Texas Instruments, Inc.
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/dmaengine.h>
#include <linux/omap-dma.h>

#include "omap_hwmod.h"
#include "hdq1w.h"

#include "omap_hwmod_common_data.h"

/* UART */

static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
	.rev_offs	= 0x50,
	.sysc_offs	= 0x54,
	.syss_offs	= 0x58,
	.sysc_flags	= (SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2_uart_class = {
	.name	= "uart",
	.sysc	= &omap2_uart_sysc,
};

/*
 * 'venc' class
 * video encoder
 */

struct omap_hwmod_class omap2_venc_hwmod_class = {
	.name = "venc",
};


/* Common DMA request line data */
struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
	{ .name = "rx", .dma_req = 50, },
	{ .name = "tx", .dma_req = 49, },
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
	{ .name = "rx", .dma_req = 52, },
	{ .name = "tx", .dma_req = 51, },
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
	{ .name = "rx", .dma_req = 54, },
	{ .name = "tx", .dma_req = 53, },
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 27 },
	{ .name = "rx", .dma_req = 28 },
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 29 },
	{ .name = "rx", .dma_req = 30 },
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
	{ .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
	{ .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
	{ .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
	{ .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
	{ .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
	{ .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
	{ .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
	{ .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
	{ .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
	{ .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
	{ .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
	{ .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
	{ .name = "rx", .dma_req = 32 },
	{ .name = "tx", .dma_req = 31 },
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
	{ .name = "rx", .dma_req = 34 },
	{ .name = "tx", .dma_req = 33 },
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
	{ .name = "rx", .dma_req = 18 },
	{ .name = "tx", .dma_req = 17 },
	{ .dma_req = -1 }
};

/* Other IP block data */


/*
 * omap_hwmod class data
 */

struct omap_hwmod_class l3_hwmod_class = {
	.name = "l3"
};

struct omap_hwmod_class l4_hwmod_class = {
	.name = "l4"
};

struct omap_hwmod_class mpu_hwmod_class = {
	.name = "mpu"
};

struct omap_hwmod_class iva_hwmod_class = {
	.name = "iva"
};

/* Common MPU IRQ line data */

struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
	{ .irq = 37 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
	{ .irq = 38 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
	{ .irq = 39 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
	{ .irq = 40 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
	{ .irq = 41 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
	{ .irq = 42 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
	{ .irq = 43 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
	{ .irq = 44 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
	{ .irq = 45 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
	{ .irq = 46 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
	{ .irq = 47 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
	{ .irq = 72 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
	{ .irq = 73 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
	{ .irq = 74 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
	{ .irq = 25 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
	{ .irq = 56 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
	{ .irq = 57 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
	{ .irq = 29 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK1 */
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
	{ .irq = 30 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK2 */
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
	{ .irq = 31 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK3 */
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
	{ .irq = 32 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK4 */
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
	{ .name = "0", .irq = 12 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ0 */
	{ .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */
	{ .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */
	{ .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
	{ .irq = 65 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
	{ .irq = 66 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
	.rev_offs	= 0x0,
	.sysc_offs	= 0x14,
	.syss_offs	= 0x18,
	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
			   SYSS_HAS_RESET_STATUS),
	.sysc_fields    = &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2_hdq1w_class = {
	.name	= "hdq1w",
	.sysc	= &omap2_hdq1w_sysc,
	.reset	= &omap_hdq1w_reset,
};

struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = {
	{ .irq = 58 + OMAP_INTC_START, },
	{ .irq = -1 },
};
Commit	Line	Data
0d619a89 PW	1	/*
	2	* omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
	3	*
	4	* Copyright (C) 2011 Nokia Corporation
03d830e8	5	* Copyright (C) 2012 Texas Instruments, Inc.
0d619a89 PW	6	* Paul Walmsley
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
2a296c8f	12
45c3eb7d TL	13	#include <linux/dmaengine.h>
45c3eb7d TL	14	#include <linux/omap-dma.h>
2a296c8f	15
2a296c8f	16	#include "omap_hwmod.h"
a0b30ca5	17	#include "hdq1w.h"
0d619a89	18
0d619a89 PW	19	#include "omap_hwmod_common_data.h"
0d619a89 PW	20
273b9465 PW	21	/* UART */
	22
	23	static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
	24	.rev_offs = 0x50,
	25	.sysc_offs = 0x54,
	26	.syss_offs = 0x58,
	27	.sysc_flags = (SYSC_HAS_SIDLEMODE \|
	28	SYSC_HAS_ENAWAKEUP \| SYSC_HAS_SOFTRESET \|
	29	SYSC_HAS_AUTOIDLE \| SYSS_HAS_RESET_STATUS),
	30	.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
	31	.sysc_fields = &omap_hwmod_sysc_type1,
	32	};
	33
	34	struct omap_hwmod_class omap2_uart_class = {
	35	.name = "uart",
	36	.sysc = &omap2_uart_sysc,
	37	};
	38
273b9465 PW	39	/*
	40	* 'venc' class
	41	* video encoder
	42	*/
	43
	44	struct omap_hwmod_class omap2_venc_hwmod_class = {
	45	.name = "venc",
	46	};
	47
	48
	49	/* Common DMA request line data */
	50	struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
0fd8824f JN	51	{ .name = "rx", .dma_req = 50, },
0fd8824f JN	52	{ .name = "tx", .dma_req = 49, },
273b9465 PW	53	{ .dma_req = -1 }
	54	};
	55
	56	struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
0fd8824f JN	57	{ .name = "rx", .dma_req = 52, },
0fd8824f JN	58	{ .name = "tx", .dma_req = 51, },
273b9465 PW	59	{ .dma_req = -1 }
	60	};
	61
	62	struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
0fd8824f JN	63	{ .name = "rx", .dma_req = 54, },
0fd8824f JN	64	{ .name = "tx", .dma_req = 53, },
273b9465 PW	65	{ .dma_req = -1 }
	66	};
	67
	68	struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
0fd8824f JN	69	{ .name = "tx", .dma_req = 27 },
0fd8824f JN	70	{ .name = "rx", .dma_req = 28 },
273b9465 PW	71	{ .dma_req = -1 }
	72	};
	73
	74	struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
0fd8824f JN	75	{ .name = "tx", .dma_req = 29 },
0fd8824f JN	76	{ .name = "rx", .dma_req = 30 },
273b9465 PW	77	{ .dma_req = -1 }
	78	};
	79
	80	struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
	81	{ .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
	82	{ .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
	83	{ .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
	84	{ .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
	85	{ .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
	86	{ .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
	87	{ .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
	88	{ .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
	89	{ .dma_req = -1 }
	90	};
	91
	92	struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
	93	{ .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
	94	{ .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
	95	{ .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
	96	{ .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
	97	{ .dma_req = -1 }
	98	};
	99
	100	struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
	101	{ .name = "rx", .dma_req = 32 },
	102	{ .name = "tx", .dma_req = 31 },
	103	{ .dma_req = -1 }
	104	};
	105
	106	struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
	107	{ .name = "rx", .dma_req = 34 },
	108	{ .name = "tx", .dma_req = 33 },
	109	{ .dma_req = -1 }
	110	};
	111
	112	struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
	113	{ .name = "rx", .dma_req = 18 },
	114	{ .name = "tx", .dma_req = 17 },
	115	{ .dma_req = -1 }
	116	};
	117
	118	/* Other IP block data */
	119
d826ebfa PW	120
	121	/*
	122	* omap_hwmod class data
	123	*/
	124
	125	struct omap_hwmod_class l3_hwmod_class = {
	126	.name = "l3"
	127	};
	128
	129	struct omap_hwmod_class l4_hwmod_class = {
	130	.name = "l4"
	131	};
	132
	133	struct omap_hwmod_class mpu_hwmod_class = {
	134	.name = "mpu"
	135	};
	136
	137	struct omap_hwmod_class iva_hwmod_class = {
	138	.name = "iva"
	139	};
	140
	141	/* Common MPU IRQ line data */
	142
0d619a89	143	struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
7d7e1eba TL	144	{ .irq = 37 + OMAP_INTC_START, },
7d7e1eba TL	145	{ .irq = -1 },
0d619a89 PW	146	};
	147
	148	struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
7d7e1eba TL	149	{ .irq = 38 + OMAP_INTC_START, },
7d7e1eba TL	150	{ .irq = -1 },
0d619a89 PW	151	};
	152
	153	struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
7d7e1eba TL	154	{ .irq = 39 + OMAP_INTC_START, },
7d7e1eba TL	155	{ .irq = -1 },
0d619a89 PW	156	};
	157
	158	struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
7d7e1eba TL	159	{ .irq = 40 + OMAP_INTC_START, },
7d7e1eba TL	160	{ .irq = -1 },
0d619a89 PW	161	};
	162
	163	struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
7d7e1eba TL	164	{ .irq = 41 + OMAP_INTC_START, },
7d7e1eba TL	165	{ .irq = -1 },
0d619a89 PW	166	};
	167
	168	struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
7d7e1eba TL	169	{ .irq = 42 + OMAP_INTC_START, },
7d7e1eba TL	170	{ .irq = -1 },
0d619a89 PW	171	};
	172
	173	struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
7d7e1eba TL	174	{ .irq = 43 + OMAP_INTC_START, },
7d7e1eba TL	175	{ .irq = -1 },
0d619a89 PW	176	};
	177
	178	struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
7d7e1eba TL	179	{ .irq = 44 + OMAP_INTC_START, },
7d7e1eba TL	180	{ .irq = -1 },
0d619a89 PW	181	};
	182
	183	struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
7d7e1eba TL	184	{ .irq = 45 + OMAP_INTC_START, },
7d7e1eba TL	185	{ .irq = -1 },
0d619a89 PW	186	};
	187
	188	struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
7d7e1eba TL	189	{ .irq = 46 + OMAP_INTC_START, },
7d7e1eba TL	190	{ .irq = -1 },
0d619a89 PW	191	};
	192
	193	struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
7d7e1eba TL	194	{ .irq = 47 + OMAP_INTC_START, },
7d7e1eba TL	195	{ .irq = -1 },
0d619a89 PW	196	};
	197
	198	struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
7d7e1eba TL	199	{ .irq = 72 + OMAP_INTC_START, },
7d7e1eba TL	200	{ .irq = -1 },
0d619a89 PW	201	};
	202
	203	struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
7d7e1eba TL	204	{ .irq = 73 + OMAP_INTC_START, },
7d7e1eba TL	205	{ .irq = -1 },
0d619a89 PW	206	};
	207
	208	struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
7d7e1eba TL	209	{ .irq = 74 + OMAP_INTC_START, },
7d7e1eba TL	210	{ .irq = -1 },
0d619a89 PW	211	};
	212
	213	struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
7d7e1eba TL	214	{ .irq = 25 + OMAP_INTC_START, },
7d7e1eba TL	215	{ .irq = -1 },
0d619a89 PW	216	};
	217
	218	struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
7d7e1eba TL	219	{ .irq = 56 + OMAP_INTC_START, },
7d7e1eba TL	220	{ .irq = -1 },
0d619a89 PW	221	};
	222
	223	struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
7d7e1eba TL	224	{ .irq = 57 + OMAP_INTC_START, },
7d7e1eba TL	225	{ .irq = -1 },
0d619a89 PW	226	};
	227
	228	struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
7d7e1eba TL	229	{ .irq = 29 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK1 */
7d7e1eba TL	230	{ .irq = -1 },
0d619a89 PW	231	};
	232
	233	struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
7d7e1eba TL	234	{ .irq = 30 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK2 */
7d7e1eba TL	235	{ .irq = -1 },
0d619a89 PW	236	};
	237
	238	struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
7d7e1eba TL	239	{ .irq = 31 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK3 */
7d7e1eba TL	240	{ .irq = -1 },
0d619a89 PW	241	};
	242
	243	struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
7d7e1eba TL	244	{ .irq = 32 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK4 */
7d7e1eba TL	245	{ .irq = -1 },
0d619a89 PW	246	};
	247
	248	struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
7d7e1eba TL	249	{ .name = "0", .irq = 12 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ0 */
	250	{ .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */
	251	{ .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */
	252	{ .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */
	253	{ .irq = -1 },
0d619a89 PW	254	};
	255
	256	struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
7d7e1eba TL	257	{ .irq = 65 + OMAP_INTC_START, },
7d7e1eba TL	258	{ .irq = -1 },
0d619a89 PW	259	};
	260
	261	struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
7d7e1eba TL	262	{ .irq = 66 + OMAP_INTC_START, },
7d7e1eba TL	263	{ .irq = -1 },
0d619a89 PW	264	};
0d619a89 PW	265
03d830e8 PW	266	struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
	267	.rev_offs = 0x0,
	268	.sysc_offs = 0x14,
	269	.syss_offs = 0x18,
	270	.sysc_flags = (SYSC_HAS_SOFTRESET \| SYSC_HAS_AUTOIDLE \|
	271	SYSS_HAS_RESET_STATUS),
	272	.sysc_fields = &omap_hwmod_sysc_type1,
	273	};
	274
	275	struct omap_hwmod_class omap2_hdq1w_class = {
	276	.name = "hdq1w",
	277	.sysc = &omap2_hdq1w_sysc,
	278	.reset = &omap_hdq1w_reset,
	279	};
	280
	281	struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = {
7d7e1eba TL	282	{ .irq = 58 + OMAP_INTC_START, },
7d7e1eba TL	283	{ .irq = -1 },
03d830e8 PW	284	};
03d830e8 PW	285