[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_2xxx_3xxx_ipblock_data.c

/*
 * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
 *
 * Copyright (C) 2011 Nokia Corporation
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <plat/omap_hwmod.h>
#include <plat/serial.h>
#include <plat/dma.h>

#include <mach/irqs.h>

#include "omap_hwmod_common_data.h"

/* UART */

static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
	.rev_offs	= 0x50,
	.sysc_offs	= 0x54,
	.syss_offs	= 0x58,
	.sysc_flags	= (SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2_uart_class = {
	.name	= "uart",
	.sysc	= &omap2_uart_sysc,
};

/*
 * 'dss' class
 * display sub-system
 */

static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2_dss_hwmod_class = {
	.name	= "dss",
	.sysc	= &omap2_dss_sysc,
};

/*
 * 'dispc' class
 * display controller
 */

static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2_dispc_hwmod_class = {
	.name	= "dispc",
	.sysc	= &omap2_dispc_sysc,
};

/*
 * 'rfbi' class
 * remote frame buffer interface
 */

static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			   SYSC_HAS_AUTOIDLE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2_rfbi_hwmod_class = {
	.name	= "rfbi",
	.sysc	= &omap2_rfbi_sysc,
};

/*
 * 'venc' class
 * video encoder
 */

struct omap_hwmod_class omap2_venc_hwmod_class = {
	.name = "venc",
};


/* Common DMA request line data */
struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
	{ .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
	{ .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
	{ .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
	{ .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
	{ .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
	{ .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
	{ .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
	{ .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
	{ .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
	{ .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
	{ .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
	{ .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
	{ .name = "rx", .dma_req = 32 },
	{ .name = "tx", .dma_req = 31 },
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
	{ .name = "rx", .dma_req = 34 },
	{ .name = "tx", .dma_req = 33 },
	{ .dma_req = -1 }
};

struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
	{ .name = "rx", .dma_req = 18 },
	{ .name = "tx", .dma_req = 17 },
	{ .dma_req = -1 }
};

/* Other IP block data */


/*
 * omap_hwmod class data
 */

struct omap_hwmod_class l3_hwmod_class = {
	.name = "l3"
};

struct omap_hwmod_class l4_hwmod_class = {
	.name = "l4"
};

struct omap_hwmod_class mpu_hwmod_class = {
	.name = "mpu"
};

struct omap_hwmod_class iva_hwmod_class = {
	.name = "iva"
};

/* Common MPU IRQ line data */

struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
	{ .irq = 37, },
	{ .irq = -1 }
};

struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
	{ .irq = 38, },
	{ .irq = -1 }
};

struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
	{ .irq = 39, },
	{ .irq = -1 }
};

struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
	{ .irq = 40, },
	{ .irq = -1 }
};

struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
	{ .irq = 41, },
	{ .irq = -1 }
};

struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
	{ .irq = 42, },
	{ .irq = -1 }
};

struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
	{ .irq = 43, },
	{ .irq = -1 }
};

struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
	{ .irq = 44, },
	{ .irq = -1 }
};

struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
	{ .irq = 45, },
	{ .irq = -1 }
};

struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
	{ .irq = 46, },
	{ .irq = -1 }
};

struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
	{ .irq = 47, },
	{ .irq = -1 }
};

struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
	{ .irq = INT_24XX_UART1_IRQ, },
	{ .irq = -1 }
};

struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
	{ .irq = INT_24XX_UART2_IRQ, },
	{ .irq = -1 }
};

struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
	{ .irq = INT_24XX_UART3_IRQ, },
	{ .irq = -1 }
};

struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
	{ .irq = 25 },
	{ .irq = -1 }
};

struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
	{ .irq = INT_24XX_I2C1_IRQ, },
	{ .irq = -1 }
};

struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
	{ .irq = INT_24XX_I2C2_IRQ, },
	{ .irq = -1 }
};

struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
	{ .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
	{ .irq = -1 }
};

struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
	{ .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
	{ .irq = -1 }
};

struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
	{ .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
	{ .irq = -1 }
};

struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
	{ .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
	{ .irq = -1 }
};

struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
	{ .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
	{ .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
	{ .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
	{ .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
	{ .irq = -1 }
};

struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
	{ .irq = 65 },
	{ .irq = -1 }
};

struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
	{ .irq = 66 },
	{ .irq = -1 }
};
Commit	Line	Data
0d619a89 PW	1	/*
	2	* omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
	3	*
	4	* Copyright (C) 2011 Nokia Corporation
	5	* Paul Walmsley
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	#include <plat/omap_hwmod.h>
	12	#include <plat/serial.h>
d826ebfa	13	#include <plat/dma.h>
0d619a89 PW	14
	15	#include <mach/irqs.h>
	16
	17	#include "omap_hwmod_common_data.h"
	18
273b9465 PW	19	/* UART */
	20
	21	static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
	22	.rev_offs = 0x50,
	23	.sysc_offs = 0x54,
	24	.syss_offs = 0x58,
	25	.sysc_flags = (SYSC_HAS_SIDLEMODE \|
	26	SYSC_HAS_ENAWAKEUP \| SYSC_HAS_SOFTRESET \|
	27	SYSC_HAS_AUTOIDLE \| SYSS_HAS_RESET_STATUS),
	28	.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
	29	.sysc_fields = &omap_hwmod_sysc_type1,
	30	};
	31
	32	struct omap_hwmod_class omap2_uart_class = {
	33	.name = "uart",
	34	.sysc = &omap2_uart_sysc,
	35	};
	36
	37	/*
	38	* 'dss' class
	39	* display sub-system
	40	*/
	41
	42	static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
	43	.rev_offs = 0x0000,
	44	.sysc_offs = 0x0010,
	45	.syss_offs = 0x0014,
	46	.sysc_flags = (SYSC_HAS_SOFTRESET \| SYSC_HAS_AUTOIDLE),
	47	.sysc_fields = &omap_hwmod_sysc_type1,
	48	};
	49
	50	struct omap_hwmod_class omap2_dss_hwmod_class = {
	51	.name = "dss",
	52	.sysc = &omap2_dss_sysc,
	53	};
	54
	55	/*
	56	* 'dispc' class
	57	* display controller
	58	*/
	59
	60	static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
	61	.rev_offs = 0x0000,
	62	.sysc_offs = 0x0010,
	63	.syss_offs = 0x0014,
	64	.sysc_flags = (SYSC_HAS_SIDLEMODE \| SYSC_HAS_MIDLEMODE \|
	65	SYSC_HAS_SOFTRESET \| SYSC_HAS_AUTOIDLE),
	66	.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART \|
	67	MSTANDBY_FORCE \| MSTANDBY_NO \| MSTANDBY_SMART),
	68	.sysc_fields = &omap_hwmod_sysc_type1,
	69	};
	70
	71	struct omap_hwmod_class omap2_dispc_hwmod_class = {
	72	.name = "dispc",
	73	.sysc = &omap2_dispc_sysc,
	74	};
	75
	76	/*
	77	* 'rfbi' class
	78	* remote frame buffer interface
	79	*/
	80
	81	static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
	82	.rev_offs = 0x0000,
83	.sysc_offs = 0x0010,
84	.syss_offs = 0x0014,
85	.sysc_flags = (SYSC_HAS_SIDLEMODE \| SYSC_HAS_SOFTRESET \|
86	SYSC_HAS_AUTOIDLE),
87	.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
88	.sysc_fields = &omap_hwmod_sysc_type1,
89	};
90
91	struct omap_hwmod_class omap2_rfbi_hwmod_class = {
92	.name = "rfbi",
93	.sysc = &omap2_rfbi_sysc,
94	};
95
96	/*
97	* 'venc' class
98	* video encoder
99	*/
100
101	struct omap_hwmod_class omap2_venc_hwmod_class = {
102	.name = "venc",
103	};
104
105
106	/* Common DMA request line data */
107	struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
108	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
109	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
110	{ .dma_req = -1 }
111	};
112
113	struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
114	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
115	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
116	{ .dma_req = -1 }
117	};
118
119	struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
120	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
121	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
122	{ .dma_req = -1 }
123	};
124
125	struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
126	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
127	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
128	{ .dma_req = -1 }
129	};
130
131	struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
132	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
133	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
134	{ .dma_req = -1 }
135	};
136
137	struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
138	{ .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
139	{ .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
140	{ .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
141	{ .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
142	{ .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
143	{ .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
144	{ .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
145	{ .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
146	{ .dma_req = -1 }
147	};
148
149	struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
150	{ .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
151	{ .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
152	{ .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
153	{ .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
154	{ .dma_req = -1 }
155	};
156
157	struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
158	{ .name = "rx", .dma_req = 32 },
159	{ .name = "tx", .dma_req = 31 },
160	{ .dma_req = -1 }
161	};
162
163	struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
164	{ .name = "rx", .dma_req = 34 },
165	{ .name = "tx", .dma_req = 33 },
166	{ .dma_req = -1 }
167	};
168
169	struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
170	{ .name = "rx", .dma_req = 18 },
171	{ .name = "tx", .dma_req = 17 },
172	{ .dma_req = -1 }
173	};
174
175	/* Other IP block data */
176
d826ebfa PW	177
	178	/*
	179	* omap_hwmod class data
	180	*/
	181
	182	struct omap_hwmod_class l3_hwmod_class = {
	183	.name = "l3"
	184	};
	185
	186	struct omap_hwmod_class l4_hwmod_class = {
	187	.name = "l4"
	188	};
	189
	190	struct omap_hwmod_class mpu_hwmod_class = {
	191	.name = "mpu"
	192	};
	193
	194	struct omap_hwmod_class iva_hwmod_class = {
	195	.name = "iva"
	196	};
	197
	198	/* Common MPU IRQ line data */
	199
0d619a89 PW	200	struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
	201	{ .irq = 37, },
	202	{ .irq = -1 }
	203	};
	204
	205	struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
	206	{ .irq = 38, },
	207	{ .irq = -1 }
	208	};
	209
	210	struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
	211	{ .irq = 39, },
	212	{ .irq = -1 }
	213	};
	214
	215	struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
	216	{ .irq = 40, },
	217	{ .irq = -1 }
	218	};
	219
	220	struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
	221	{ .irq = 41, },
	222	{ .irq = -1 }
	223	};
	224
	225	struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
	226	{ .irq = 42, },
	227	{ .irq = -1 }
	228	};
	229
	230	struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
	231	{ .irq = 43, },
	232	{ .irq = -1 }
	233	};
	234
	235	struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
	236	{ .irq = 44, },
	237	{ .irq = -1 }
	238	};
	239
	240	struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
	241	{ .irq = 45, },
	242	{ .irq = -1 }
	243	};
	244
	245	struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
	246	{ .irq = 46, },
	247	{ .irq = -1 }
	248	};
	249
	250	struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
	251	{ .irq = 47, },
	252	{ .irq = -1 }
	253	};
	254
	255	struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
	256	{ .irq = INT_24XX_UART1_IRQ, },
	257	{ .irq = -1 }
	258	};
	259
	260	struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
	261	{ .irq = INT_24XX_UART2_IRQ, },
	262	{ .irq = -1 }
	263	};
264
265	struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
266	{ .irq = INT_24XX_UART3_IRQ, },
267	{ .irq = -1 }
268	};
269
270	struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
271	{ .irq = 25 },
272	{ .irq = -1 }
273	};
274
275	struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
276	{ .irq = INT_24XX_I2C1_IRQ, },
277	{ .irq = -1 }
278	};
279
280	struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
281	{ .irq = INT_24XX_I2C2_IRQ, },
282	{ .irq = -1 }
283	};
284
285	struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
286	{ .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
287	{ .irq = -1 }
288	};
289
290	struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
291	{ .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
292	{ .irq = -1 }
293	};
294
295	struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
296	{ .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
297	{ .irq = -1 }
298	};
299
300	struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
301	{ .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
302	{ .irq = -1 }
303	};
304
305	struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
306	{ .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
307	{ .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
308	{ .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
309	{ .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
310	{ .irq = -1 }
311	};
312
313	struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
314	{ .irq = 65 },
315	{ .irq = -1 }
316	};
317
318	struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
319	{ .irq = 66 },
320	{ .irq = -1 }
321	};
322