[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_2xxx_interconnect_data.c

/*
 * omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
 *
 * Copyright (C) 2009-2011 Nokia Corporation
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * XXX handle crossbar/shared link difference for L3?
 * XXX these should be marked initdata for multi-OMAP kernels
 */
#include <asm/sizes.h>

#include "omap_hwmod.h"
#include "l3_2xxx.h"
#include "l4_2xxx.h"
#include "serial.h"

#include "omap_hwmod_common_data.h"

static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
	{
		.pa_start	= OMAP2_UART1_BASE,
		.pa_end		= OMAP2_UART1_BASE + SZ_8K - 1,
		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
	},
	{ }
};

static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
	{
		.pa_start	= OMAP2_UART2_BASE,
		.pa_end		= OMAP2_UART2_BASE + SZ_1K - 1,
		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
	},
	{ }
};

static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
	{
		.pa_start	= OMAP2_UART3_BASE,
		.pa_end		= OMAP2_UART3_BASE + SZ_1K - 1,
		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
	},
	{ }
};

static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
	{
		.pa_start	= 0x4802a000,
		.pa_end		= 0x4802a000 + SZ_1K - 1,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
	{
		.pa_start	= 0x48078000,
		.pa_end		= 0x48078000 + SZ_1K - 1,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
	{
		.pa_start	= 0x4807a000,
		.pa_end		= 0x4807a000 + SZ_1K - 1,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
	{
		.pa_start	= 0x4807c000,
		.pa_end		= 0x4807c000 + SZ_1K - 1,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
	{
		.pa_start	= 0x4807e000,
		.pa_end		= 0x4807e000 + SZ_1K - 1,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
	{
		.pa_start	= 0x48080000,
		.pa_end		= 0x48080000 + SZ_1K - 1,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
	{
		.pa_start	= 0x48082000,
		.pa_end		= 0x48082000 + SZ_1K - 1,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
	{
		.pa_start	= 0x48084000,
		.pa_end		= 0x48084000 + SZ_1K - 1,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
	{
		.name		= "mpu",
		.pa_start	= 0x48076000,
		.pa_end		= 0x480760ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_addr_space omap2_rng_addr_space[] = {
	{
		.pa_start	= 0x480a0000,
		.pa_end		= 0x480a004f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_addr_space omap2xxx_sham_addrs[] = {
	{
		.pa_start	= 0x480a4000,
		.pa_end		= 0x480a4000 + 0x64 - 1,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_addr_space omap2xxx_aes_addrs[] = {
	{
		.pa_start	= 0x480a6000,
		.pa_end		= 0x480a6000 + 0x50 - 1,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/*
 * Common interconnect data
 */

/* L3 -> L4_CORE interface */
struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = {
	.master	= &omap2xxx_l3_main_hwmod,
	.slave	= &omap2xxx_l4_core_hwmod,
	.user	= OCP_USER_MPU | OCP_USER_SDMA,
};

/* MPU -> L3 interface */
struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = {
	.master = &omap2xxx_mpu_hwmod,
	.slave	= &omap2xxx_l3_main_hwmod,
	.user	= OCP_USER_MPU,
};

/* DSS -> l3 */
struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
	.master		= &omap2xxx_dss_core_hwmod,
	.slave		= &omap2xxx_l3_main_hwmod,
	.fw = {
		.omap2 = {
			.l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
			.flags	= OMAP_FIREWALL_L3,
		}
	},
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* L4_CORE -> L4_WKUP interface */
struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = {
	.master	= &omap2xxx_l4_core_hwmod,
	.slave	= &omap2xxx_l4_wkup_hwmod,
	.user	= OCP_USER_MPU | OCP_USER_SDMA,
};

/* L4 CORE -> UART1 interface */
struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_uart1_hwmod,
	.clk		= "uart1_ick",
	.addr		= omap2xxx_uart1_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* L4 CORE -> UART2 interface */
struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_uart2_hwmod,
	.clk		= "uart2_ick",
	.addr		= omap2xxx_uart2_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* L4 PER -> UART3 interface */
struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_uart3_hwmod,
	.clk		= "uart3_ick",
	.addr		= omap2xxx_uart3_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4 core -> mcspi1 interface */
struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_mcspi1_hwmod,
	.clk		= "mcspi1_ick",
	.addr		= omap2_mcspi1_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4 core -> mcspi2 interface */
struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_mcspi2_hwmod,
	.clk		= "mcspi2_ick",
	.addr		= omap2_mcspi2_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> timer2 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_timer2_hwmod,
	.clk		= "gpt2_ick",
	.addr		= omap2xxx_timer2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> timer3 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_timer3_hwmod,
	.clk		= "gpt3_ick",
	.addr		= omap2xxx_timer3_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> timer4 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_timer4_hwmod,
	.clk		= "gpt4_ick",
	.addr		= omap2xxx_timer4_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> timer5 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_timer5_hwmod,
	.clk		= "gpt5_ick",
	.addr		= omap2xxx_timer5_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> timer6 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_timer6_hwmod,
	.clk		= "gpt6_ick",
	.addr		= omap2xxx_timer6_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> timer7 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_timer7_hwmod,
	.clk		= "gpt7_ick",
	.addr		= omap2xxx_timer7_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> timer8 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_timer8_hwmod,
	.clk		= "gpt8_ick",
	.addr		= omap2xxx_timer8_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> timer9 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_timer9_hwmod,
	.clk		= "gpt9_ick",
	.addr		= omap2xxx_timer9_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> timer10 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_timer10_hwmod,
	.clk		= "gpt10_ick",
	.addr		= omap2_timer10_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> timer11 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_timer11_hwmod,
	.clk		= "gpt11_ick",
	.addr		= omap2_timer11_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> timer12 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_timer12_hwmod,
	.clk		= "gpt12_ick",
	.addr		= omap2xxx_timer12_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> dss */
struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_dss_core_hwmod,
	.clk		= "dss_ick",
	.addr		= omap2_dss_addrs,
	.fw = {
		.omap2 = {
			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
			.flags	= OMAP_FIREWALL_L4,
		}
	},
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> dss_dispc */
struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_dss_dispc_hwmod,
	.clk		= "dss_ick",
	.addr		= omap2_dss_dispc_addrs,
	.fw = {
		.omap2 = {
			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
			.flags	= OMAP_FIREWALL_L4,
		}
	},
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> dss_rfbi */
struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_dss_rfbi_hwmod,
	.clk		= "dss_ick",
	.addr		= omap2_dss_rfbi_addrs,
	.fw = {
		.omap2 = {
			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
			.flags	= OMAP_FIREWALL_L4,
		}
	},
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> dss_venc */
struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_dss_venc_hwmod,
	.clk		= "dss_ick",
	.addr		= omap2_dss_venc_addrs,
	.fw = {
		.omap2 = {
			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
			.flags	= OMAP_FIREWALL_L4,
		}
	},
	.flags		= OCPIF_SWSUP_IDLE,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> rng */
struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_rng_hwmod,
	.clk		= "rng_ick",
	.addr		= omap2_rng_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4 core -> sham interface */
struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_sham_hwmod,
	.clk		= "sha_ick",
	.addr		= omap2xxx_sham_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4 core -> aes interface */
struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_aes_hwmod,
	.clk		= "aes_ick",
	.addr		= omap2xxx_aes_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};
Commit	Line	Data
ded11383 PW	1	/*
	2	* omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
	3	*
	4	* Copyright (C) 2009-2011 Nokia Corporation
	5	* Paul Walmsley
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* XXX handle crossbar/shared link difference for L3?
	12	* XXX these should be marked initdata for multi-OMAP kernels
	13	*/
	14	#include <asm/sizes.h>
	15
2a296c8f	16	#include "omap_hwmod.h"
1e0f51a9	17	#include "l3_2xxx.h"
70606b1c	18	#include "l4_2xxx.h"
3d82cbbb	19	#include "serial.h"
ded11383 PW	20
	21	#include "omap_hwmod_common_data.h"
	22
6a29755f	23	static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
ded11383 PW	24	{
	25	.pa_start = OMAP2_UART1_BASE,
	26	.pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
	27	.flags = ADDR_MAP_ON_INIT \| ADDR_TYPE_RT,
	28	},
	29	{ }
	30	};
	31
6a29755f	32	static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
ded11383 PW	33	{
	34	.pa_start = OMAP2_UART2_BASE,
	35	.pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
	36	.flags = ADDR_MAP_ON_INIT \| ADDR_TYPE_RT,
	37	},
	38	{ }
	39	};
	40
6a29755f	41	static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
ded11383 PW	42	{
	43	.pa_start = OMAP2_UART3_BASE,
	44	.pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
	45	.flags = ADDR_MAP_ON_INIT \| ADDR_TYPE_RT,
	46	},
	47	{ }
	48	};
	49
6a29755f	50	static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
ded11383 PW	51	{
	52	.pa_start = 0x4802a000,
	53	.pa_end = 0x4802a000 + SZ_1K - 1,
	54	.flags = ADDR_TYPE_RT
	55	},
	56	{ }
	57	};
	58
6a29755f	59	static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
ded11383 PW	60	{
	61	.pa_start = 0x48078000,
	62	.pa_end = 0x48078000 + SZ_1K - 1,
	63	.flags = ADDR_TYPE_RT
	64	},
	65	{ }
	66	};
	67
6a29755f	68	static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
ded11383 PW	69	{
	70	.pa_start = 0x4807a000,
	71	.pa_end = 0x4807a000 + SZ_1K - 1,
	72	.flags = ADDR_TYPE_RT
	73	},
	74	{ }
	75	};
	76
6a29755f	77	static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
ded11383 PW	78	{
	79	.pa_start = 0x4807c000,
	80	.pa_end = 0x4807c000 + SZ_1K - 1,
	81	.flags = ADDR_TYPE_RT
	82	},
	83	{ }
	84	};
	85
6a29755f	86	static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
ded11383 PW	87	{
	88	.pa_start = 0x4807e000,
	89	.pa_end = 0x4807e000 + SZ_1K - 1,
	90	.flags = ADDR_TYPE_RT
	91	},
	92	{ }
	93	};
	94
6a29755f	95	static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
ded11383 PW	96	{
	97	.pa_start = 0x48080000,
	98	.pa_end = 0x48080000 + SZ_1K - 1,
	99	.flags = ADDR_TYPE_RT
	100	},
	101	{ }
	102	};
	103
6a29755f	104	static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
ded11383 PW	105	{
	106	.pa_start = 0x48082000,
	107	.pa_end = 0x48082000 + SZ_1K - 1,
	108	.flags = ADDR_TYPE_RT
	109	},
	110	{ }
	111	};
	112
6a29755f	113	static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
ded11383 PW	114	{
	115	.pa_start = 0x48084000,
	116	.pa_end = 0x48084000 + SZ_1K - 1,
	117	.flags = ADDR_TYPE_RT
	118	},
	119	{ }
	120	};
	121
	122	struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
	123	{
	124	.name = "mpu",
	125	.pa_start = 0x48076000,
	126	.pa_end = 0x480760ff,
	127	.flags = ADDR_TYPE_RT
	128	},
	129	{ }
	130	};
	131
e9b0a2fb PW	132	static struct omap_hwmod_addr_space omap2_rng_addr_space[] = {
	133	{
	134	.pa_start = 0x480a0000,
	135	.pa_end = 0x480a004f,
	136	.flags = ADDR_TYPE_RT
	137	},
	138	{ }
	139	};
	140
e569e994 MG	141	static struct omap_hwmod_addr_space omap2xxx_sham_addrs[] = {
	142	{
	143	.pa_start = 0x480a4000,
	144	.pa_end = 0x480a4000 + 0x64 - 1,
	145	.flags = ADDR_TYPE_RT
	146	},
	147	{ }
	148	};
	149
660ffd6b MG	150	static struct omap_hwmod_addr_space omap2xxx_aes_addrs[] = {
	151	{
	152	.pa_start = 0x480a6000,
	153	.pa_end = 0x480a6000 + 0x50 - 1,
	154	.flags = ADDR_TYPE_RT
	155	},
	156	{ }
	157	};
	158
6a29755f PW	159	/*
	160	* Common interconnect data
	161	*/
	162
	163	/* L3 -> L4_CORE interface */
	164	struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = {
	165	.master = &omap2xxx_l3_main_hwmod,
	166	.slave = &omap2xxx_l4_core_hwmod,
	167	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	168	};
	169
	170	/* MPU -> L3 interface */
	171	struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = {
	172	.master = &omap2xxx_mpu_hwmod,
	173	.slave = &omap2xxx_l3_main_hwmod,
	174	.user = OCP_USER_MPU,
	175	};
	176
	177	/* DSS -> l3 */
	178	struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
	179	.master = &omap2xxx_dss_core_hwmod,
	180	.slave = &omap2xxx_l3_main_hwmod,
	181	.fw = {
	182	.omap2 = {
	183	.l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
	184	.flags = OMAP_FIREWALL_L3,
	185	}
	186	},
	187	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	188	};
	189
	190	/* L4_CORE -> L4_WKUP interface */
	191	struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = {
	192	.master = &omap2xxx_l4_core_hwmod,
	193	.slave = &omap2xxx_l4_wkup_hwmod,
	194	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	195	};
	196
	197	/* L4 CORE -> UART1 interface */
	198	struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
	199	.master = &omap2xxx_l4_core_hwmod,
	200	.slave = &omap2xxx_uart1_hwmod,
	201	.clk = "uart1_ick",
	202	.addr = omap2xxx_uart1_addr_space,
	203	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	204	};
	205
	206	/* L4 CORE -> UART2 interface */
	207	struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
	208	.master = &omap2xxx_l4_core_hwmod,
	209	.slave = &omap2xxx_uart2_hwmod,
	210	.clk = "uart2_ick",
	211	.addr = omap2xxx_uart2_addr_space,
	212	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	213	};
	214
	215	/* L4 PER -> UART3 interface */
	216	struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
	217	.master = &omap2xxx_l4_core_hwmod,
	218	.slave = &omap2xxx_uart3_hwmod,
	219	.clk = "uart3_ick",
	220	.addr = omap2xxx_uart3_addr_space,
	221	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	222	};
223
224	/* l4 core -> mcspi1 interface */
225	struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
226	.master = &omap2xxx_l4_core_hwmod,
227	.slave = &omap2xxx_mcspi1_hwmod,
228	.clk = "mcspi1_ick",
229	.addr = omap2_mcspi1_addr_space,
230	.user = OCP_USER_MPU \| OCP_USER_SDMA,
231	};
232
233	/* l4 core -> mcspi2 interface */
234	struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
235	.master = &omap2xxx_l4_core_hwmod,
236	.slave = &omap2xxx_mcspi2_hwmod,
237	.clk = "mcspi2_ick",
238	.addr = omap2_mcspi2_addr_space,
239	.user = OCP_USER_MPU \| OCP_USER_SDMA,
240	};
241
242	/* l4_core -> timer2 */
243	struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
244	.master = &omap2xxx_l4_core_hwmod,
245	.slave = &omap2xxx_timer2_hwmod,
246	.clk = "gpt2_ick",
247	.addr = omap2xxx_timer2_addrs,
248	.user = OCP_USER_MPU \| OCP_USER_SDMA,
249	};
250
251	/* l4_core -> timer3 */
252	struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
253	.master = &omap2xxx_l4_core_hwmod,
254	.slave = &omap2xxx_timer3_hwmod,
255	.clk = "gpt3_ick",
256	.addr = omap2xxx_timer3_addrs,
257	.user = OCP_USER_MPU \| OCP_USER_SDMA,
258	};
259
260	/* l4_core -> timer4 */
261	struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
262	.master = &omap2xxx_l4_core_hwmod,
263	.slave = &omap2xxx_timer4_hwmod,
264	.clk = "gpt4_ick",
265	.addr = omap2xxx_timer4_addrs,
266	.user = OCP_USER_MPU \| OCP_USER_SDMA,
267	};
268
269	/* l4_core -> timer5 */
270	struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
271	.master = &omap2xxx_l4_core_hwmod,
272	.slave = &omap2xxx_timer5_hwmod,
273	.clk = "gpt5_ick",
274	.addr = omap2xxx_timer5_addrs,
275	.user = OCP_USER_MPU \| OCP_USER_SDMA,
276	};
277
278	/* l4_core -> timer6 */
279	struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
280	.master = &omap2xxx_l4_core_hwmod,
281	.slave = &omap2xxx_timer6_hwmod,
282	.clk = "gpt6_ick",
283	.addr = omap2xxx_timer6_addrs,
284	.user = OCP_USER_MPU \| OCP_USER_SDMA,
285	};
286
287	/* l4_core -> timer7 */
288	struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
289	.master = &omap2xxx_l4_core_hwmod,
290	.slave = &omap2xxx_timer7_hwmod,
291	.clk = "gpt7_ick",
292	.addr = omap2xxx_timer7_addrs,
293	.user = OCP_USER_MPU \| OCP_USER_SDMA,
294	};
295
296	/* l4_core -> timer8 */
297	struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
298	.master = &omap2xxx_l4_core_hwmod,
299	.slave = &omap2xxx_timer8_hwmod,
300	.clk = "gpt8_ick",
301	.addr = omap2xxx_timer8_addrs,
302	.user = OCP_USER_MPU \| OCP_USER_SDMA,
303	};
304
305	/* l4_core -> timer9 */
306	struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
307	.master = &omap2xxx_l4_core_hwmod,
308	.slave = &omap2xxx_timer9_hwmod,
309	.clk = "gpt9_ick",
310	.addr = omap2xxx_timer9_addrs,
311	.user = OCP_USER_MPU \| OCP_USER_SDMA,
312	};
313
314	/* l4_core -> timer10 */
315	struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
316	.master = &omap2xxx_l4_core_hwmod,
317	.slave = &omap2xxx_timer10_hwmod,
318	.clk = "gpt10_ick",
319	.addr = omap2_timer10_addrs,
320	.user = OCP_USER_MPU \| OCP_USER_SDMA,
321	};
322
323	/* l4_core -> timer11 */
324	struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
325	.master = &omap2xxx_l4_core_hwmod,
326	.slave = &omap2xxx_timer11_hwmod,
327	.clk = "gpt11_ick",
328	.addr = omap2_timer11_addrs,
329	.user = OCP_USER_MPU \| OCP_USER_SDMA,
330	};
331
332	/* l4_core -> timer12 */
333	struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
334	.master = &omap2xxx_l4_core_hwmod,
335	.slave = &omap2xxx_timer12_hwmod,
336	.clk = "gpt12_ick",
337	.addr = omap2xxx_timer12_addrs,
338	.user = OCP_USER_MPU \| OCP_USER_SDMA,
339	};
340
341	/* l4_core -> dss */
342	struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
343	.master = &omap2xxx_l4_core_hwmod,
344	.slave = &omap2xxx_dss_core_hwmod,
345	.clk = "dss_ick",
346	.addr = omap2_dss_addrs,
347	.fw = {
348	.omap2 = {
349	.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
350	.flags = OMAP_FIREWALL_L4,
351	}
352	},
353	.user = OCP_USER_MPU \| OCP_USER_SDMA,
354	};
355
356	/* l4_core -> dss_dispc */
357	struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
358	.master = &omap2xxx_l4_core_hwmod,
359	.slave = &omap2xxx_dss_dispc_hwmod,
360	.clk = "dss_ick",
361	.addr = omap2_dss_dispc_addrs,
362	.fw = {
363	.omap2 = {
364	.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
365	.flags = OMAP_FIREWALL_L4,
366	}
367	},
368	.user = OCP_USER_MPU \| OCP_USER_SDMA,
369	};
370
371	/* l4_core -> dss_rfbi */
372	struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
373	.master = &omap2xxx_l4_core_hwmod,
374	.slave = &omap2xxx_dss_rfbi_hwmod,
375	.clk = "dss_ick",
376	.addr = omap2_dss_rfbi_addrs,
377	.fw = {
378	.omap2 = {
379	.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
380	.flags = OMAP_FIREWALL_L4,
381	}
382	},
383	.user = OCP_USER_MPU \| OCP_USER_SDMA,
384	};
385
386	/* l4_core -> dss_venc */
387	struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
388	.master = &omap2xxx_l4_core_hwmod,
389	.slave = &omap2xxx_dss_venc_hwmod,
390	.clk = "dss_ick",
391	.addr = omap2_dss_venc_addrs,
392	.fw = {
393	.omap2 = {
394	.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
395	.flags = OMAP_FIREWALL_L4,
396	}
397	},
398	.flags = OCPIF_SWSUP_IDLE,
399	.user = OCP_USER_MPU \| OCP_USER_SDMA,
400	};
ded11383	401
e9b0a2fb PW	402	/* l4_core -> rng */
	403	struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
	404	.master = &omap2xxx_l4_core_hwmod,
	405	.slave = &omap2xxx_rng_hwmod,
	406	.clk = "rng_ick",
	407	.addr = omap2_rng_addr_space,
	408	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	409	};
e569e994 MG	410
	411	/* l4 core -> sham interface */
	412	struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
	413	.master = &omap2xxx_l4_core_hwmod,
	414	.slave = &omap2xxx_sham_hwmod,
	415	.clk = "sha_ick",
	416	.addr = omap2xxx_sham_addrs,
fa7807b4	417	.user = OCP_USER_MPU \| OCP_USER_SDMA,
e569e994	418	};
660ffd6b MG	419
	420	/* l4 core -> aes interface */
	421	struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = {
	422	.master = &omap2xxx_l4_core_hwmod,
	423	.slave = &omap2xxx_aes_hwmod,
	424	.clk = "aes_ick",
	425	.addr = omap2xxx_aes_addrs,
	426	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	427	};