[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_2xxx_interconnect_data.c

/*
 * omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
 *
 * Copyright (C) 2009-2011 Nokia Corporation
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * XXX handle crossbar/shared link difference for L3?
 * XXX these should be marked initdata for multi-OMAP kernels
 */
#include <asm/sizes.h>

#include <plat/serial.h>

#include "omap_hwmod.h"
#include "l3_2xxx.h"
#include "l4_2xxx.h"

#include "omap_hwmod_common_data.h"

static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
	{
		.pa_start	= OMAP2_UART1_BASE,
		.pa_end		= OMAP2_UART1_BASE + SZ_8K - 1,
		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
	},
	{ }
};

static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
	{
		.pa_start	= OMAP2_UART2_BASE,
		.pa_end		= OMAP2_UART2_BASE + SZ_1K - 1,
		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
	},
	{ }
};

static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
	{
		.pa_start	= OMAP2_UART3_BASE,
		.pa_end		= OMAP2_UART3_BASE + SZ_1K - 1,
		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
	},
	{ }
};

static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
	{
		.pa_start	= 0x4802a000,
		.pa_end		= 0x4802a000 + SZ_1K - 1,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
	{
		.pa_start	= 0x48078000,
		.pa_end		= 0x48078000 + SZ_1K - 1,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
	{
		.pa_start	= 0x4807a000,
		.pa_end		= 0x4807a000 + SZ_1K - 1,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
	{
		.pa_start	= 0x4807c000,
		.pa_end		= 0x4807c000 + SZ_1K - 1,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
	{
		.pa_start	= 0x4807e000,
		.pa_end		= 0x4807e000 + SZ_1K - 1,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
	{
		.pa_start	= 0x48080000,
		.pa_end		= 0x48080000 + SZ_1K - 1,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
	{
		.pa_start	= 0x48082000,
		.pa_end		= 0x48082000 + SZ_1K - 1,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
	{
		.pa_start	= 0x48084000,
		.pa_end		= 0x48084000 + SZ_1K - 1,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
	{
		.name		= "mpu",
		.pa_start	= 0x48076000,
		.pa_end		= 0x480760ff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_addr_space omap2_rng_addr_space[] = {
	{
		.pa_start	= 0x480a0000,
		.pa_end		= 0x480a004f,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

/*
 * Common interconnect data
 */

/* L3 -> L4_CORE interface */
struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = {
	.master	= &omap2xxx_l3_main_hwmod,
	.slave	= &omap2xxx_l4_core_hwmod,
	.user	= OCP_USER_MPU | OCP_USER_SDMA,
};

/* MPU -> L3 interface */
struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = {
	.master = &omap2xxx_mpu_hwmod,
	.slave	= &omap2xxx_l3_main_hwmod,
	.user	= OCP_USER_MPU,
};

/* DSS -> l3 */
struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
	.master		= &omap2xxx_dss_core_hwmod,
	.slave		= &omap2xxx_l3_main_hwmod,
	.fw = {
		.omap2 = {
			.l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
			.flags	= OMAP_FIREWALL_L3,
		}
	},
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* L4_CORE -> L4_WKUP interface */
struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = {
	.master	= &omap2xxx_l4_core_hwmod,
	.slave	= &omap2xxx_l4_wkup_hwmod,
	.user	= OCP_USER_MPU | OCP_USER_SDMA,
};

/* L4 CORE -> UART1 interface */
struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_uart1_hwmod,
	.clk		= "uart1_ick",
	.addr		= omap2xxx_uart1_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* L4 CORE -> UART2 interface */
struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_uart2_hwmod,
	.clk		= "uart2_ick",
	.addr		= omap2xxx_uart2_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* L4 PER -> UART3 interface */
struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_uart3_hwmod,
	.clk		= "uart3_ick",
	.addr		= omap2xxx_uart3_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4 core -> mcspi1 interface */
struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_mcspi1_hwmod,
	.clk		= "mcspi1_ick",
	.addr		= omap2_mcspi1_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4 core -> mcspi2 interface */
struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_mcspi2_hwmod,
	.clk		= "mcspi2_ick",
	.addr		= omap2_mcspi2_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> timer2 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_timer2_hwmod,
	.clk		= "gpt2_ick",
	.addr		= omap2xxx_timer2_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> timer3 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_timer3_hwmod,
	.clk		= "gpt3_ick",
	.addr		= omap2xxx_timer3_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> timer4 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_timer4_hwmod,
	.clk		= "gpt4_ick",
	.addr		= omap2xxx_timer4_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> timer5 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_timer5_hwmod,
	.clk		= "gpt5_ick",
	.addr		= omap2xxx_timer5_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> timer6 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_timer6_hwmod,
	.clk		= "gpt6_ick",
	.addr		= omap2xxx_timer6_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> timer7 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_timer7_hwmod,
	.clk		= "gpt7_ick",
	.addr		= omap2xxx_timer7_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> timer8 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_timer8_hwmod,
	.clk		= "gpt8_ick",
	.addr		= omap2xxx_timer8_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> timer9 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_timer9_hwmod,
	.clk		= "gpt9_ick",
	.addr		= omap2xxx_timer9_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> timer10 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_timer10_hwmod,
	.clk		= "gpt10_ick",
	.addr		= omap2_timer10_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> timer11 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_timer11_hwmod,
	.clk		= "gpt11_ick",
	.addr		= omap2_timer11_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> timer12 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_timer12_hwmod,
	.clk		= "gpt12_ick",
	.addr		= omap2xxx_timer12_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> dss */
struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_dss_core_hwmod,
	.clk		= "dss_ick",
	.addr		= omap2_dss_addrs,
	.fw = {
		.omap2 = {
			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
			.flags	= OMAP_FIREWALL_L4,
		}
	},
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> dss_dispc */
struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_dss_dispc_hwmod,
	.clk		= "dss_ick",
	.addr		= omap2_dss_dispc_addrs,
	.fw = {
		.omap2 = {
			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
			.flags	= OMAP_FIREWALL_L4,
		}
	},
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> dss_rfbi */
struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_dss_rfbi_hwmod,
	.clk		= "dss_ick",
	.addr		= omap2_dss_rfbi_addrs,
	.fw = {
		.omap2 = {
			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
			.flags	= OMAP_FIREWALL_L4,
		}
	},
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> dss_venc */
struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_dss_venc_hwmod,
	.clk		= "dss_ick",
	.addr		= omap2_dss_venc_addrs,
	.fw = {
		.omap2 = {
			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
			.flags	= OMAP_FIREWALL_L4,
		}
	},
	.flags		= OCPIF_SWSUP_IDLE,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> rng */
struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2xxx_rng_hwmod,
	.clk		= "rng_ick",
	.addr		= omap2_rng_addr_space,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};
Commit	Line	Data
ded11383 PW	1	/*
	2	* omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
	3	*
	4	* Copyright (C) 2009-2011 Nokia Corporation
	5	* Paul Walmsley
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* XXX handle crossbar/shared link difference for L3?
	12	* XXX these should be marked initdata for multi-OMAP kernels
	13	*/
	14	#include <asm/sizes.h>
	15
ded11383	16	#include <plat/serial.h>
2a296c8f TL	17
2a296c8f TL	18	#include "omap_hwmod.h"
1e0f51a9	19	#include "l3_2xxx.h"
70606b1c	20	#include "l4_2xxx.h"
ded11383 PW	21
	22	#include "omap_hwmod_common_data.h"
	23
6a29755f	24	static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
ded11383 PW	25	{
	26	.pa_start = OMAP2_UART1_BASE,
	27	.pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
	28	.flags = ADDR_MAP_ON_INIT \| ADDR_TYPE_RT,
	29	},
	30	{ }
	31	};
	32
6a29755f	33	static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
ded11383 PW	34	{
	35	.pa_start = OMAP2_UART2_BASE,
	36	.pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
	37	.flags = ADDR_MAP_ON_INIT \| ADDR_TYPE_RT,
	38	},
	39	{ }
	40	};
	41
6a29755f	42	static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
ded11383 PW	43	{
	44	.pa_start = OMAP2_UART3_BASE,
	45	.pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
	46	.flags = ADDR_MAP_ON_INIT \| ADDR_TYPE_RT,
	47	},
	48	{ }
	49	};
	50
6a29755f	51	static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
ded11383 PW	52	{
	53	.pa_start = 0x4802a000,
	54	.pa_end = 0x4802a000 + SZ_1K - 1,
	55	.flags = ADDR_TYPE_RT
	56	},
	57	{ }
	58	};
	59
6a29755f	60	static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
ded11383 PW	61	{
	62	.pa_start = 0x48078000,
	63	.pa_end = 0x48078000 + SZ_1K - 1,
	64	.flags = ADDR_TYPE_RT
	65	},
	66	{ }
	67	};
	68
6a29755f	69	static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
ded11383 PW	70	{
	71	.pa_start = 0x4807a000,
	72	.pa_end = 0x4807a000 + SZ_1K - 1,
	73	.flags = ADDR_TYPE_RT
	74	},
	75	{ }
	76	};
	77
6a29755f	78	static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
ded11383 PW	79	{
	80	.pa_start = 0x4807c000,
	81	.pa_end = 0x4807c000 + SZ_1K - 1,
	82	.flags = ADDR_TYPE_RT
	83	},
	84	{ }
	85	};
	86
6a29755f	87	static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
ded11383 PW	88	{
	89	.pa_start = 0x4807e000,
	90	.pa_end = 0x4807e000 + SZ_1K - 1,
	91	.flags = ADDR_TYPE_RT
	92	},
	93	{ }
	94	};
	95
6a29755f	96	static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
ded11383 PW	97	{
	98	.pa_start = 0x48080000,
	99	.pa_end = 0x48080000 + SZ_1K - 1,
	100	.flags = ADDR_TYPE_RT
	101	},
	102	{ }
	103	};
	104
6a29755f	105	static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
ded11383 PW	106	{
	107	.pa_start = 0x48082000,
	108	.pa_end = 0x48082000 + SZ_1K - 1,
	109	.flags = ADDR_TYPE_RT
	110	},
	111	{ }
	112	};
	113
6a29755f	114	static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
ded11383 PW	115	{
	116	.pa_start = 0x48084000,
	117	.pa_end = 0x48084000 + SZ_1K - 1,
	118	.flags = ADDR_TYPE_RT
	119	},
	120	{ }
	121	};
	122
	123	struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
	124	{
	125	.name = "mpu",
	126	.pa_start = 0x48076000,
	127	.pa_end = 0x480760ff,
	128	.flags = ADDR_TYPE_RT
	129	},
	130	{ }
	131	};
	132
e9b0a2fb PW	133	static struct omap_hwmod_addr_space omap2_rng_addr_space[] = {
	134	{
	135	.pa_start = 0x480a0000,
	136	.pa_end = 0x480a004f,
	137	.flags = ADDR_TYPE_RT
	138	},
	139	{ }
	140	};
	141
6a29755f PW	142	/*
	143	* Common interconnect data
	144	*/
	145
	146	/* L3 -> L4_CORE interface */
	147	struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = {
	148	.master = &omap2xxx_l3_main_hwmod,
	149	.slave = &omap2xxx_l4_core_hwmod,
	150	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	151	};
	152
	153	/* MPU -> L3 interface */
	154	struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = {
	155	.master = &omap2xxx_mpu_hwmod,
	156	.slave = &omap2xxx_l3_main_hwmod,
	157	.user = OCP_USER_MPU,
	158	};
	159
	160	/* DSS -> l3 */
	161	struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
	162	.master = &omap2xxx_dss_core_hwmod,
	163	.slave = &omap2xxx_l3_main_hwmod,
	164	.fw = {
	165	.omap2 = {
	166	.l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
	167	.flags = OMAP_FIREWALL_L3,
	168	}
	169	},
	170	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	171	};
	172
	173	/* L4_CORE -> L4_WKUP interface */
	174	struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = {
	175	.master = &omap2xxx_l4_core_hwmod,
	176	.slave = &omap2xxx_l4_wkup_hwmod,
	177	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	178	};
	179
	180	/* L4 CORE -> UART1 interface */
	181	struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
	182	.master = &omap2xxx_l4_core_hwmod,
	183	.slave = &omap2xxx_uart1_hwmod,
	184	.clk = "uart1_ick",
	185	.addr = omap2xxx_uart1_addr_space,
	186	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	187	};
	188
	189	/* L4 CORE -> UART2 interface */
	190	struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
	191	.master = &omap2xxx_l4_core_hwmod,
	192	.slave = &omap2xxx_uart2_hwmod,
	193	.clk = "uart2_ick",
	194	.addr = omap2xxx_uart2_addr_space,
	195	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	196	};
	197
	198	/* L4 PER -> UART3 interface */
	199	struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
	200	.master = &omap2xxx_l4_core_hwmod,
	201	.slave = &omap2xxx_uart3_hwmod,
	202	.clk = "uart3_ick",
	203	.addr = omap2xxx_uart3_addr_space,
	204	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	205	};
206
207	/* l4 core -> mcspi1 interface */
208	struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
209	.master = &omap2xxx_l4_core_hwmod,
210	.slave = &omap2xxx_mcspi1_hwmod,
211	.clk = "mcspi1_ick",
212	.addr = omap2_mcspi1_addr_space,
213	.user = OCP_USER_MPU \| OCP_USER_SDMA,
214	};
215
216	/* l4 core -> mcspi2 interface */
217	struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
218	.master = &omap2xxx_l4_core_hwmod,
219	.slave = &omap2xxx_mcspi2_hwmod,
220	.clk = "mcspi2_ick",
221	.addr = omap2_mcspi2_addr_space,
222	.user = OCP_USER_MPU \| OCP_USER_SDMA,
223	};
224
225	/* l4_core -> timer2 */
226	struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
227	.master = &omap2xxx_l4_core_hwmod,
228	.slave = &omap2xxx_timer2_hwmod,
229	.clk = "gpt2_ick",
230	.addr = omap2xxx_timer2_addrs,
231	.user = OCP_USER_MPU \| OCP_USER_SDMA,
232	};
233
234	/* l4_core -> timer3 */
235	struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
236	.master = &omap2xxx_l4_core_hwmod,
237	.slave = &omap2xxx_timer3_hwmod,
238	.clk = "gpt3_ick",
239	.addr = omap2xxx_timer3_addrs,
240	.user = OCP_USER_MPU \| OCP_USER_SDMA,
241	};
242
243	/* l4_core -> timer4 */
244	struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
245	.master = &omap2xxx_l4_core_hwmod,
246	.slave = &omap2xxx_timer4_hwmod,
247	.clk = "gpt4_ick",
248	.addr = omap2xxx_timer4_addrs,
249	.user = OCP_USER_MPU \| OCP_USER_SDMA,
250	};
251
252	/* l4_core -> timer5 */
253	struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
254	.master = &omap2xxx_l4_core_hwmod,
255	.slave = &omap2xxx_timer5_hwmod,
256	.clk = "gpt5_ick",
257	.addr = omap2xxx_timer5_addrs,
258	.user = OCP_USER_MPU \| OCP_USER_SDMA,
259	};
260
261	/* l4_core -> timer6 */
262	struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
263	.master = &omap2xxx_l4_core_hwmod,
264	.slave = &omap2xxx_timer6_hwmod,
265	.clk = "gpt6_ick",
266	.addr = omap2xxx_timer6_addrs,
267	.user = OCP_USER_MPU \| OCP_USER_SDMA,
268	};
269
270	/* l4_core -> timer7 */
271	struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
272	.master = &omap2xxx_l4_core_hwmod,
273	.slave = &omap2xxx_timer7_hwmod,
274	.clk = "gpt7_ick",
275	.addr = omap2xxx_timer7_addrs,
276	.user = OCP_USER_MPU \| OCP_USER_SDMA,
277	};
278
279	/* l4_core -> timer8 */
280	struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
281	.master = &omap2xxx_l4_core_hwmod,
282	.slave = &omap2xxx_timer8_hwmod,
283	.clk = "gpt8_ick",
284	.addr = omap2xxx_timer8_addrs,
285	.user = OCP_USER_MPU \| OCP_USER_SDMA,
286	};
287
288	/* l4_core -> timer9 */
289	struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
290	.master = &omap2xxx_l4_core_hwmod,
291	.slave = &omap2xxx_timer9_hwmod,
292	.clk = "gpt9_ick",
293	.addr = omap2xxx_timer9_addrs,
294	.user = OCP_USER_MPU \| OCP_USER_SDMA,
295	};
296
297	/* l4_core -> timer10 */
298	struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
299	.master = &omap2xxx_l4_core_hwmod,
300	.slave = &omap2xxx_timer10_hwmod,
301	.clk = "gpt10_ick",
302	.addr = omap2_timer10_addrs,
303	.user = OCP_USER_MPU \| OCP_USER_SDMA,
304	};
305
306	/* l4_core -> timer11 */
307	struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
308	.master = &omap2xxx_l4_core_hwmod,
309	.slave = &omap2xxx_timer11_hwmod,
310	.clk = "gpt11_ick",
311	.addr = omap2_timer11_addrs,
312	.user = OCP_USER_MPU \| OCP_USER_SDMA,
313	};
314
315	/* l4_core -> timer12 */
316	struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
317	.master = &omap2xxx_l4_core_hwmod,
318	.slave = &omap2xxx_timer12_hwmod,
319	.clk = "gpt12_ick",
320	.addr = omap2xxx_timer12_addrs,
321	.user = OCP_USER_MPU \| OCP_USER_SDMA,
322	};
323
324	/* l4_core -> dss */
325	struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
326	.master = &omap2xxx_l4_core_hwmod,
327	.slave = &omap2xxx_dss_core_hwmod,
328	.clk = "dss_ick",
329	.addr = omap2_dss_addrs,
330	.fw = {
331	.omap2 = {
332	.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
333	.flags = OMAP_FIREWALL_L4,
334	}
335	},
336	.user = OCP_USER_MPU \| OCP_USER_SDMA,
337	};
338
339	/* l4_core -> dss_dispc */
340	struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
341	.master = &omap2xxx_l4_core_hwmod,
342	.slave = &omap2xxx_dss_dispc_hwmod,
343	.clk = "dss_ick",
344	.addr = omap2_dss_dispc_addrs,
345	.fw = {
346	.omap2 = {
347	.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
348	.flags = OMAP_FIREWALL_L4,
349	}
350	},
351	.user = OCP_USER_MPU \| OCP_USER_SDMA,
352	};
353
354	/* l4_core -> dss_rfbi */
355	struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
356	.master = &omap2xxx_l4_core_hwmod,
357	.slave = &omap2xxx_dss_rfbi_hwmod,
358	.clk = "dss_ick",
359	.addr = omap2_dss_rfbi_addrs,
360	.fw = {
361	.omap2 = {
362	.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
363	.flags = OMAP_FIREWALL_L4,
364	}
365	},
366	.user = OCP_USER_MPU \| OCP_USER_SDMA,
367	};
368
369	/* l4_core -> dss_venc */
370	struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
371	.master = &omap2xxx_l4_core_hwmod,
372	.slave = &omap2xxx_dss_venc_hwmod,
373	.clk = "dss_ick",
374	.addr = omap2_dss_venc_addrs,
375	.fw = {
376	.omap2 = {
377	.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
378	.flags = OMAP_FIREWALL_L4,
379	}
380	},
381	.flags = OCPIF_SWSUP_IDLE,
382	.user = OCP_USER_MPU \| OCP_USER_SDMA,
383	};
ded11383	384
e9b0a2fb PW	385	/* l4_core -> rng */
	386	struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
	387	.master = &omap2xxx_l4_core_hwmod,
	388	.slave = &omap2xxx_rng_hwmod,
	389	.clk = "rng_ick",
	390	.addr = omap2_rng_addr_space,
	391	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	392	};