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0d619a89 PW |
1 | /* |
2 | * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx | |
3 | * | |
4 | * Copyright (C) 2011 Nokia Corporation | |
5 | * Paul Walmsley | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <plat/omap_hwmod.h> | |
12 | #include <plat/serial.h> | |
cb48427e | 13 | #include <plat/gpio.h> |
d826ebfa | 14 | #include <plat/dma.h> |
273b9465 PW |
15 | #include <plat/dmtimer.h> |
16 | #include <plat/mcspi.h> | |
0d619a89 PW |
17 | |
18 | #include <mach/irqs.h> | |
19 | ||
20 | #include "omap_hwmod_common_data.h" | |
cb48427e PW |
21 | #include "cm-regbits-24xx.h" |
22 | #include "prm-regbits-24xx.h" | |
273b9465 | 23 | #include "wd_timer.h" |
0d619a89 PW |
24 | |
25 | struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = { | |
26 | { .irq = 48, }, | |
27 | { .irq = -1 } | |
28 | }; | |
d826ebfa PW |
29 | |
30 | struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = { | |
31 | { .name = "dispc", .dma_req = 5 }, | |
32 | { .dma_req = -1 } | |
33 | }; | |
1ac6d46e TV |
34 | |
35 | /* | |
36 | * 'dispc' class | |
37 | * display controller | |
38 | */ | |
39 | ||
40 | static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = { | |
41 | .rev_offs = 0x0000, | |
42 | .sysc_offs = 0x0010, | |
43 | .syss_offs = 0x0014, | |
44 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | | |
45 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
46 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
47 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
48 | .sysc_fields = &omap_hwmod_sysc_type1, | |
49 | }; | |
50 | ||
51 | struct omap_hwmod_class omap2_dispc_hwmod_class = { | |
52 | .name = "dispc", | |
53 | .sysc = &omap2_dispc_sysc, | |
54 | }; | |
55 | ||
273b9465 PW |
56 | /* OMAP2xxx Timer Common */ |
57 | static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = { | |
58 | .rev_offs = 0x0000, | |
59 | .sysc_offs = 0x0010, | |
60 | .syss_offs = 0x0014, | |
61 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
62 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
63 | SYSC_HAS_AUTOIDLE), | |
64 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
65 | .sysc_fields = &omap_hwmod_sysc_type1, | |
66 | }; | |
67 | ||
68 | struct omap_hwmod_class omap2xxx_timer_hwmod_class = { | |
69 | .name = "timer", | |
70 | .sysc = &omap2xxx_timer_sysc, | |
71 | .rev = OMAP_TIMER_IP_VERSION_1, | |
72 | }; | |
73 | ||
74 | /* | |
75 | * 'wd_timer' class | |
76 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
77 | * overflow condition | |
78 | */ | |
79 | ||
80 | static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = { | |
81 | .rev_offs = 0x0000, | |
82 | .sysc_offs = 0x0010, | |
83 | .syss_offs = 0x0014, | |
84 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | | |
85 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
86 | .sysc_fields = &omap_hwmod_sysc_type1, | |
87 | }; | |
88 | ||
89 | struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = { | |
90 | .name = "wd_timer", | |
91 | .sysc = &omap2xxx_wd_timer_sysc, | |
414e4128 KH |
92 | .pre_shutdown = &omap2_wd_timer_disable, |
93 | .reset = &omap2_wd_timer_reset, | |
273b9465 PW |
94 | }; |
95 | ||
96 | /* | |
97 | * 'gpio' class | |
98 | * general purpose io module | |
99 | */ | |
100 | static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = { | |
101 | .rev_offs = 0x0000, | |
102 | .sysc_offs = 0x0010, | |
103 | .syss_offs = 0x0014, | |
104 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
105 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
106 | SYSS_HAS_RESET_STATUS), | |
107 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
108 | .sysc_fields = &omap_hwmod_sysc_type1, | |
109 | }; | |
110 | ||
111 | struct omap_hwmod_class omap2xxx_gpio_hwmod_class = { | |
112 | .name = "gpio", | |
113 | .sysc = &omap2xxx_gpio_sysc, | |
114 | .rev = 0, | |
115 | }; | |
116 | ||
117 | /* system dma */ | |
118 | static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = { | |
119 | .rev_offs = 0x0000, | |
120 | .sysc_offs = 0x002c, | |
121 | .syss_offs = 0x0028, | |
122 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | | |
123 | SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | | |
124 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
125 | .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
126 | .sysc_fields = &omap_hwmod_sysc_type1, | |
127 | }; | |
128 | ||
129 | struct omap_hwmod_class omap2xxx_dma_hwmod_class = { | |
130 | .name = "dma", | |
131 | .sysc = &omap2xxx_dma_sysc, | |
132 | }; | |
133 | ||
134 | /* | |
135 | * 'mailbox' class | |
136 | * mailbox module allowing communication between the on-chip processors | |
137 | * using a queued mailbox-interrupt mechanism. | |
138 | */ | |
139 | ||
140 | static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = { | |
141 | .rev_offs = 0x000, | |
142 | .sysc_offs = 0x010, | |
143 | .syss_offs = 0x014, | |
144 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
145 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
146 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
147 | .sysc_fields = &omap_hwmod_sysc_type1, | |
148 | }; | |
149 | ||
150 | struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = { | |
151 | .name = "mailbox", | |
152 | .sysc = &omap2xxx_mailbox_sysc, | |
153 | }; | |
154 | ||
155 | /* | |
156 | * 'mcspi' class | |
157 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
158 | * bus | |
159 | */ | |
160 | ||
161 | static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = { | |
162 | .rev_offs = 0x0000, | |
163 | .sysc_offs = 0x0010, | |
164 | .syss_offs = 0x0014, | |
165 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
166 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
167 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
168 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
169 | .sysc_fields = &omap_hwmod_sysc_type1, | |
170 | }; | |
171 | ||
172 | struct omap_hwmod_class omap2xxx_mcspi_class = { | |
173 | .name = "mcspi", | |
174 | .sysc = &omap2xxx_mcspi_sysc, | |
175 | .rev = OMAP2_MCSPI_REV, | |
176 | }; | |
cb48427e PW |
177 | |
178 | /* | |
179 | * IP blocks | |
180 | */ | |
181 | ||
182 | /* L3 */ | |
183 | struct omap_hwmod omap2xxx_l3_main_hwmod = { | |
184 | .name = "l3_main", | |
185 | .class = &l3_hwmod_class, | |
186 | .flags = HWMOD_NO_IDLEST, | |
187 | }; | |
188 | ||
189 | /* L4 CORE */ | |
190 | struct omap_hwmod omap2xxx_l4_core_hwmod = { | |
191 | .name = "l4_core", | |
192 | .class = &l4_hwmod_class, | |
193 | .flags = HWMOD_NO_IDLEST, | |
194 | }; | |
195 | ||
196 | /* L4 WKUP */ | |
197 | struct omap_hwmod omap2xxx_l4_wkup_hwmod = { | |
198 | .name = "l4_wkup", | |
199 | .class = &l4_hwmod_class, | |
200 | .flags = HWMOD_NO_IDLEST, | |
201 | }; | |
202 | ||
203 | /* MPU */ | |
204 | struct omap_hwmod omap2xxx_mpu_hwmod = { | |
205 | .name = "mpu", | |
206 | .class = &mpu_hwmod_class, | |
207 | .main_clk = "mpu_ck", | |
208 | }; | |
209 | ||
210 | /* IVA2 */ | |
211 | struct omap_hwmod omap2xxx_iva_hwmod = { | |
212 | .name = "iva", | |
213 | .class = &iva_hwmod_class, | |
214 | }; | |
215 | ||
216 | /* always-on timers dev attribute */ | |
217 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
218 | .timer_capability = OMAP_TIMER_ALWON, | |
219 | }; | |
220 | ||
221 | /* pwm timers dev attribute */ | |
222 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
223 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
224 | }; | |
225 | ||
226 | /* timer1 */ | |
227 | ||
228 | struct omap_hwmod omap2xxx_timer1_hwmod = { | |
229 | .name = "timer1", | |
230 | .mpu_irqs = omap2_timer1_mpu_irqs, | |
231 | .main_clk = "gpt1_fck", | |
232 | .prcm = { | |
233 | .omap2 = { | |
234 | .prcm_reg_id = 1, | |
235 | .module_bit = OMAP24XX_EN_GPT1_SHIFT, | |
236 | .module_offs = WKUP_MOD, | |
237 | .idlest_reg_id = 1, | |
238 | .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, | |
239 | }, | |
240 | }, | |
241 | .dev_attr = &capability_alwon_dev_attr, | |
242 | .class = &omap2xxx_timer_hwmod_class, | |
243 | }; | |
244 | ||
245 | /* timer2 */ | |
246 | ||
247 | struct omap_hwmod omap2xxx_timer2_hwmod = { | |
248 | .name = "timer2", | |
249 | .mpu_irqs = omap2_timer2_mpu_irqs, | |
250 | .main_clk = "gpt2_fck", | |
251 | .prcm = { | |
252 | .omap2 = { | |
253 | .prcm_reg_id = 1, | |
254 | .module_bit = OMAP24XX_EN_GPT2_SHIFT, | |
255 | .module_offs = CORE_MOD, | |
256 | .idlest_reg_id = 1, | |
257 | .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, | |
258 | }, | |
259 | }, | |
260 | .dev_attr = &capability_alwon_dev_attr, | |
261 | .class = &omap2xxx_timer_hwmod_class, | |
262 | }; | |
263 | ||
264 | /* timer3 */ | |
265 | ||
266 | struct omap_hwmod omap2xxx_timer3_hwmod = { | |
267 | .name = "timer3", | |
268 | .mpu_irqs = omap2_timer3_mpu_irqs, | |
269 | .main_clk = "gpt3_fck", | |
270 | .prcm = { | |
271 | .omap2 = { | |
272 | .prcm_reg_id = 1, | |
273 | .module_bit = OMAP24XX_EN_GPT3_SHIFT, | |
274 | .module_offs = CORE_MOD, | |
275 | .idlest_reg_id = 1, | |
276 | .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, | |
277 | }, | |
278 | }, | |
279 | .dev_attr = &capability_alwon_dev_attr, | |
280 | .class = &omap2xxx_timer_hwmod_class, | |
281 | }; | |
282 | ||
283 | /* timer4 */ | |
284 | ||
285 | struct omap_hwmod omap2xxx_timer4_hwmod = { | |
286 | .name = "timer4", | |
287 | .mpu_irqs = omap2_timer4_mpu_irqs, | |
288 | .main_clk = "gpt4_fck", | |
289 | .prcm = { | |
290 | .omap2 = { | |
291 | .prcm_reg_id = 1, | |
292 | .module_bit = OMAP24XX_EN_GPT4_SHIFT, | |
293 | .module_offs = CORE_MOD, | |
294 | .idlest_reg_id = 1, | |
295 | .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, | |
296 | }, | |
297 | }, | |
298 | .dev_attr = &capability_alwon_dev_attr, | |
299 | .class = &omap2xxx_timer_hwmod_class, | |
300 | }; | |
301 | ||
302 | /* timer5 */ | |
303 | ||
304 | struct omap_hwmod omap2xxx_timer5_hwmod = { | |
305 | .name = "timer5", | |
306 | .mpu_irqs = omap2_timer5_mpu_irqs, | |
307 | .main_clk = "gpt5_fck", | |
308 | .prcm = { | |
309 | .omap2 = { | |
310 | .prcm_reg_id = 1, | |
311 | .module_bit = OMAP24XX_EN_GPT5_SHIFT, | |
312 | .module_offs = CORE_MOD, | |
313 | .idlest_reg_id = 1, | |
314 | .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, | |
315 | }, | |
316 | }, | |
317 | .dev_attr = &capability_alwon_dev_attr, | |
318 | .class = &omap2xxx_timer_hwmod_class, | |
319 | }; | |
320 | ||
321 | /* timer6 */ | |
322 | ||
323 | struct omap_hwmod omap2xxx_timer6_hwmod = { | |
324 | .name = "timer6", | |
325 | .mpu_irqs = omap2_timer6_mpu_irqs, | |
326 | .main_clk = "gpt6_fck", | |
327 | .prcm = { | |
328 | .omap2 = { | |
329 | .prcm_reg_id = 1, | |
330 | .module_bit = OMAP24XX_EN_GPT6_SHIFT, | |
331 | .module_offs = CORE_MOD, | |
332 | .idlest_reg_id = 1, | |
333 | .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, | |
334 | }, | |
335 | }, | |
336 | .dev_attr = &capability_alwon_dev_attr, | |
337 | .class = &omap2xxx_timer_hwmod_class, | |
338 | }; | |
339 | ||
340 | /* timer7 */ | |
341 | ||
342 | struct omap_hwmod omap2xxx_timer7_hwmod = { | |
343 | .name = "timer7", | |
344 | .mpu_irqs = omap2_timer7_mpu_irqs, | |
345 | .main_clk = "gpt7_fck", | |
346 | .prcm = { | |
347 | .omap2 = { | |
348 | .prcm_reg_id = 1, | |
349 | .module_bit = OMAP24XX_EN_GPT7_SHIFT, | |
350 | .module_offs = CORE_MOD, | |
351 | .idlest_reg_id = 1, | |
352 | .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, | |
353 | }, | |
354 | }, | |
355 | .dev_attr = &capability_alwon_dev_attr, | |
356 | .class = &omap2xxx_timer_hwmod_class, | |
357 | }; | |
358 | ||
359 | /* timer8 */ | |
360 | ||
361 | struct omap_hwmod omap2xxx_timer8_hwmod = { | |
362 | .name = "timer8", | |
363 | .mpu_irqs = omap2_timer8_mpu_irqs, | |
364 | .main_clk = "gpt8_fck", | |
365 | .prcm = { | |
366 | .omap2 = { | |
367 | .prcm_reg_id = 1, | |
368 | .module_bit = OMAP24XX_EN_GPT8_SHIFT, | |
369 | .module_offs = CORE_MOD, | |
370 | .idlest_reg_id = 1, | |
371 | .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, | |
372 | }, | |
373 | }, | |
374 | .dev_attr = &capability_alwon_dev_attr, | |
375 | .class = &omap2xxx_timer_hwmod_class, | |
376 | }; | |
377 | ||
378 | /* timer9 */ | |
379 | ||
380 | struct omap_hwmod omap2xxx_timer9_hwmod = { | |
381 | .name = "timer9", | |
382 | .mpu_irqs = omap2_timer9_mpu_irqs, | |
383 | .main_clk = "gpt9_fck", | |
384 | .prcm = { | |
385 | .omap2 = { | |
386 | .prcm_reg_id = 1, | |
387 | .module_bit = OMAP24XX_EN_GPT9_SHIFT, | |
388 | .module_offs = CORE_MOD, | |
389 | .idlest_reg_id = 1, | |
390 | .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, | |
391 | }, | |
392 | }, | |
393 | .dev_attr = &capability_pwm_dev_attr, | |
394 | .class = &omap2xxx_timer_hwmod_class, | |
395 | }; | |
396 | ||
397 | /* timer10 */ | |
398 | ||
399 | struct omap_hwmod omap2xxx_timer10_hwmod = { | |
400 | .name = "timer10", | |
401 | .mpu_irqs = omap2_timer10_mpu_irqs, | |
402 | .main_clk = "gpt10_fck", | |
403 | .prcm = { | |
404 | .omap2 = { | |
405 | .prcm_reg_id = 1, | |
406 | .module_bit = OMAP24XX_EN_GPT10_SHIFT, | |
407 | .module_offs = CORE_MOD, | |
408 | .idlest_reg_id = 1, | |
409 | .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, | |
410 | }, | |
411 | }, | |
412 | .dev_attr = &capability_pwm_dev_attr, | |
413 | .class = &omap2xxx_timer_hwmod_class, | |
414 | }; | |
415 | ||
416 | /* timer11 */ | |
417 | ||
418 | struct omap_hwmod omap2xxx_timer11_hwmod = { | |
419 | .name = "timer11", | |
420 | .mpu_irqs = omap2_timer11_mpu_irqs, | |
421 | .main_clk = "gpt11_fck", | |
422 | .prcm = { | |
423 | .omap2 = { | |
424 | .prcm_reg_id = 1, | |
425 | .module_bit = OMAP24XX_EN_GPT11_SHIFT, | |
426 | .module_offs = CORE_MOD, | |
427 | .idlest_reg_id = 1, | |
428 | .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, | |
429 | }, | |
430 | }, | |
431 | .dev_attr = &capability_pwm_dev_attr, | |
432 | .class = &omap2xxx_timer_hwmod_class, | |
433 | }; | |
434 | ||
435 | /* timer12 */ | |
436 | ||
437 | struct omap_hwmod omap2xxx_timer12_hwmod = { | |
438 | .name = "timer12", | |
439 | .mpu_irqs = omap2xxx_timer12_mpu_irqs, | |
440 | .main_clk = "gpt12_fck", | |
441 | .prcm = { | |
442 | .omap2 = { | |
443 | .prcm_reg_id = 1, | |
444 | .module_bit = OMAP24XX_EN_GPT12_SHIFT, | |
445 | .module_offs = CORE_MOD, | |
446 | .idlest_reg_id = 1, | |
447 | .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, | |
448 | }, | |
449 | }, | |
450 | .dev_attr = &capability_pwm_dev_attr, | |
451 | .class = &omap2xxx_timer_hwmod_class, | |
452 | }; | |
453 | ||
454 | /* wd_timer2 */ | |
455 | struct omap_hwmod omap2xxx_wd_timer2_hwmod = { | |
456 | .name = "wd_timer2", | |
457 | .class = &omap2xxx_wd_timer_hwmod_class, | |
458 | .main_clk = "mpu_wdt_fck", | |
459 | .prcm = { | |
460 | .omap2 = { | |
461 | .prcm_reg_id = 1, | |
462 | .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
463 | .module_offs = WKUP_MOD, | |
464 | .idlest_reg_id = 1, | |
465 | .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, | |
466 | }, | |
467 | }, | |
468 | }; | |
469 | ||
470 | /* UART1 */ | |
471 | ||
472 | struct omap_hwmod omap2xxx_uart1_hwmod = { | |
473 | .name = "uart1", | |
474 | .mpu_irqs = omap2_uart1_mpu_irqs, | |
475 | .sdma_reqs = omap2_uart1_sdma_reqs, | |
476 | .main_clk = "uart1_fck", | |
477 | .prcm = { | |
478 | .omap2 = { | |
479 | .module_offs = CORE_MOD, | |
480 | .prcm_reg_id = 1, | |
481 | .module_bit = OMAP24XX_EN_UART1_SHIFT, | |
482 | .idlest_reg_id = 1, | |
483 | .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, | |
484 | }, | |
485 | }, | |
486 | .class = &omap2_uart_class, | |
487 | }; | |
488 | ||
489 | /* UART2 */ | |
490 | ||
491 | struct omap_hwmod omap2xxx_uart2_hwmod = { | |
492 | .name = "uart2", | |
493 | .mpu_irqs = omap2_uart2_mpu_irqs, | |
494 | .sdma_reqs = omap2_uart2_sdma_reqs, | |
495 | .main_clk = "uart2_fck", | |
496 | .prcm = { | |
497 | .omap2 = { | |
498 | .module_offs = CORE_MOD, | |
499 | .prcm_reg_id = 1, | |
500 | .module_bit = OMAP24XX_EN_UART2_SHIFT, | |
501 | .idlest_reg_id = 1, | |
502 | .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, | |
503 | }, | |
504 | }, | |
505 | .class = &omap2_uart_class, | |
506 | }; | |
507 | ||
508 | /* UART3 */ | |
509 | ||
510 | struct omap_hwmod omap2xxx_uart3_hwmod = { | |
511 | .name = "uart3", | |
512 | .mpu_irqs = omap2_uart3_mpu_irqs, | |
513 | .sdma_reqs = omap2_uart3_sdma_reqs, | |
514 | .main_clk = "uart3_fck", | |
515 | .prcm = { | |
516 | .omap2 = { | |
517 | .module_offs = CORE_MOD, | |
518 | .prcm_reg_id = 2, | |
519 | .module_bit = OMAP24XX_EN_UART3_SHIFT, | |
520 | .idlest_reg_id = 2, | |
521 | .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, | |
522 | }, | |
523 | }, | |
524 | .class = &omap2_uart_class, | |
525 | }; | |
526 | ||
527 | /* dss */ | |
528 | ||
529 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |
530 | /* | |
531 | * The DSS HW needs all DSS clocks enabled during reset. The dss_core | |
532 | * driver does not use these clocks. | |
533 | */ | |
534 | { .role = "tv_clk", .clk = "dss_54m_fck" }, | |
535 | { .role = "sys_clk", .clk = "dss2_fck" }, | |
536 | }; | |
537 | ||
538 | struct omap_hwmod omap2xxx_dss_core_hwmod = { | |
539 | .name = "dss_core", | |
540 | .class = &omap2_dss_hwmod_class, | |
541 | .main_clk = "dss1_fck", /* instead of dss_fck */ | |
542 | .sdma_reqs = omap2xxx_dss_sdma_chs, | |
543 | .prcm = { | |
544 | .omap2 = { | |
545 | .prcm_reg_id = 1, | |
546 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
547 | .module_offs = CORE_MOD, | |
548 | .idlest_reg_id = 1, | |
549 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, | |
550 | }, | |
551 | }, | |
552 | .opt_clks = dss_opt_clks, | |
553 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
554 | .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
555 | }; | |
556 | ||
557 | struct omap_hwmod omap2xxx_dss_dispc_hwmod = { | |
558 | .name = "dss_dispc", | |
559 | .class = &omap2_dispc_hwmod_class, | |
560 | .mpu_irqs = omap2_dispc_irqs, | |
561 | .main_clk = "dss1_fck", | |
562 | .prcm = { | |
563 | .omap2 = { | |
564 | .prcm_reg_id = 1, | |
565 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
566 | .module_offs = CORE_MOD, | |
567 | .idlest_reg_id = 1, | |
568 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, | |
569 | }, | |
570 | }, | |
571 | .flags = HWMOD_NO_IDLEST, | |
572 | .dev_attr = &omap2_3_dss_dispc_dev_attr | |
573 | }; | |
574 | ||
575 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { | |
576 | { .role = "ick", .clk = "dss_ick" }, | |
577 | }; | |
578 | ||
579 | struct omap_hwmod omap2xxx_dss_rfbi_hwmod = { | |
580 | .name = "dss_rfbi", | |
581 | .class = &omap2_rfbi_hwmod_class, | |
582 | .main_clk = "dss1_fck", | |
583 | .prcm = { | |
584 | .omap2 = { | |
585 | .prcm_reg_id = 1, | |
586 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
587 | .module_offs = CORE_MOD, | |
588 | }, | |
589 | }, | |
590 | .opt_clks = dss_rfbi_opt_clks, | |
591 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
592 | .flags = HWMOD_NO_IDLEST, | |
593 | }; | |
594 | ||
595 | struct omap_hwmod omap2xxx_dss_venc_hwmod = { | |
596 | .name = "dss_venc", | |
597 | .class = &omap2_venc_hwmod_class, | |
598 | .main_clk = "dss_54m_fck", | |
599 | .prcm = { | |
600 | .omap2 = { | |
601 | .prcm_reg_id = 1, | |
602 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
603 | .module_offs = CORE_MOD, | |
604 | }, | |
605 | }, | |
606 | .flags = HWMOD_NO_IDLEST, | |
607 | }; | |
608 | ||
609 | /* gpio dev_attr */ | |
610 | struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = { | |
611 | .bank_width = 32, | |
612 | .dbck_flag = false, | |
613 | }; | |
614 | ||
615 | /* gpio1 */ | |
616 | struct omap_hwmod omap2xxx_gpio1_hwmod = { | |
617 | .name = "gpio1", | |
618 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
619 | .mpu_irqs = omap2_gpio1_irqs, | |
620 | .main_clk = "gpios_fck", | |
621 | .prcm = { | |
622 | .omap2 = { | |
623 | .prcm_reg_id = 1, | |
624 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
625 | .module_offs = WKUP_MOD, | |
626 | .idlest_reg_id = 1, | |
627 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
628 | }, | |
629 | }, | |
630 | .class = &omap2xxx_gpio_hwmod_class, | |
631 | .dev_attr = &omap2xxx_gpio_dev_attr, | |
632 | }; | |
633 | ||
634 | /* gpio2 */ | |
635 | struct omap_hwmod omap2xxx_gpio2_hwmod = { | |
636 | .name = "gpio2", | |
637 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
638 | .mpu_irqs = omap2_gpio2_irqs, | |
639 | .main_clk = "gpios_fck", | |
640 | .prcm = { | |
641 | .omap2 = { | |
642 | .prcm_reg_id = 1, | |
643 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
644 | .module_offs = WKUP_MOD, | |
645 | .idlest_reg_id = 1, | |
646 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
647 | }, | |
648 | }, | |
649 | .class = &omap2xxx_gpio_hwmod_class, | |
650 | .dev_attr = &omap2xxx_gpio_dev_attr, | |
651 | }; | |
652 | ||
653 | /* gpio3 */ | |
654 | struct omap_hwmod omap2xxx_gpio3_hwmod = { | |
655 | .name = "gpio3", | |
656 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
657 | .mpu_irqs = omap2_gpio3_irqs, | |
658 | .main_clk = "gpios_fck", | |
659 | .prcm = { | |
660 | .omap2 = { | |
661 | .prcm_reg_id = 1, | |
662 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
663 | .module_offs = WKUP_MOD, | |
664 | .idlest_reg_id = 1, | |
665 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
666 | }, | |
667 | }, | |
668 | .class = &omap2xxx_gpio_hwmod_class, | |
669 | .dev_attr = &omap2xxx_gpio_dev_attr, | |
670 | }; | |
671 | ||
672 | /* gpio4 */ | |
673 | struct omap_hwmod omap2xxx_gpio4_hwmod = { | |
674 | .name = "gpio4", | |
675 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
676 | .mpu_irqs = omap2_gpio4_irqs, | |
677 | .main_clk = "gpios_fck", | |
678 | .prcm = { | |
679 | .omap2 = { | |
680 | .prcm_reg_id = 1, | |
681 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
682 | .module_offs = WKUP_MOD, | |
683 | .idlest_reg_id = 1, | |
684 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
685 | }, | |
686 | }, | |
687 | .class = &omap2xxx_gpio_hwmod_class, | |
688 | .dev_attr = &omap2xxx_gpio_dev_attr, | |
689 | }; | |
690 | ||
691 | /* mcspi1 */ | |
692 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { | |
693 | .num_chipselect = 4, | |
694 | }; | |
695 | ||
696 | struct omap_hwmod omap2xxx_mcspi1_hwmod = { | |
697 | .name = "mcspi1", | |
698 | .mpu_irqs = omap2_mcspi1_mpu_irqs, | |
699 | .sdma_reqs = omap2_mcspi1_sdma_reqs, | |
700 | .main_clk = "mcspi1_fck", | |
701 | .prcm = { | |
702 | .omap2 = { | |
703 | .module_offs = CORE_MOD, | |
704 | .prcm_reg_id = 1, | |
705 | .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, | |
706 | .idlest_reg_id = 1, | |
707 | .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, | |
708 | }, | |
709 | }, | |
710 | .class = &omap2xxx_mcspi_class, | |
711 | .dev_attr = &omap_mcspi1_dev_attr, | |
712 | }; | |
713 | ||
714 | /* mcspi2 */ | |
715 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { | |
716 | .num_chipselect = 2, | |
717 | }; | |
718 | ||
719 | struct omap_hwmod omap2xxx_mcspi2_hwmod = { | |
720 | .name = "mcspi2", | |
721 | .mpu_irqs = omap2_mcspi2_mpu_irqs, | |
722 | .sdma_reqs = omap2_mcspi2_sdma_reqs, | |
723 | .main_clk = "mcspi2_fck", | |
724 | .prcm = { | |
725 | .omap2 = { | |
726 | .module_offs = CORE_MOD, | |
727 | .prcm_reg_id = 1, | |
728 | .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, | |
729 | .idlest_reg_id = 1, | |
730 | .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, | |
731 | }, | |
732 | }, | |
733 | .class = &omap2xxx_mcspi_class, | |
734 | .dev_attr = &omap_mcspi2_dev_attr, | |
735 | }; | |
c8d82ff6 VH |
736 | |
737 | ||
738 | static struct omap_hwmod_class omap2xxx_counter_hwmod_class = { | |
739 | .name = "counter", | |
740 | }; | |
741 | ||
742 | struct omap_hwmod omap2xxx_counter_32k_hwmod = { | |
743 | .name = "counter_32k", | |
744 | .main_clk = "func_32k_ck", | |
745 | .prcm = { | |
746 | .omap2 = { | |
747 | .module_offs = WKUP_MOD, | |
748 | .prcm_reg_id = 1, | |
749 | .module_bit = OMAP24XX_ST_32KSYNC_SHIFT, | |
750 | .idlest_reg_id = 1, | |
751 | .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT, | |
752 | }, | |
753 | }, | |
754 | .class = &omap2xxx_counter_hwmod_class, | |
755 | }; |