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26649467 AM |
1 | /* |
2 | * | |
3 | * Copyright (C) 2013 Texas Instruments Incorporated | |
4 | * | |
5 | * Interconnects common for AM335x and AM43x | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation version 2. | |
10 | * | |
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
12 | * kind, whether express or implied; without even the implied warranty | |
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/sizes.h> | |
18 | #include "omap_hwmod.h" | |
19 | #include "omap_hwmod_33xx_43xx_common_data.h" | |
20 | ||
21 | /* mpu -> l3 main */ | |
22 | struct omap_hwmod_ocp_if am33xx_mpu__l3_main = { | |
23 | .master = &am33xx_mpu_hwmod, | |
24 | .slave = &am33xx_l3_main_hwmod, | |
25 | .clk = "dpll_mpu_m2_ck", | |
26 | .user = OCP_USER_MPU, | |
27 | }; | |
28 | ||
29 | /* l3 main -> l3 s */ | |
30 | struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = { | |
31 | .master = &am33xx_l3_main_hwmod, | |
32 | .slave = &am33xx_l3_s_hwmod, | |
33 | .clk = "l3s_gclk", | |
34 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
35 | }; | |
36 | ||
37 | /* l3 s -> l4 per/ls */ | |
38 | struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = { | |
39 | .master = &am33xx_l3_s_hwmod, | |
40 | .slave = &am33xx_l4_ls_hwmod, | |
41 | .clk = "l3s_gclk", | |
42 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
43 | }; | |
44 | ||
45 | /* l3 s -> l4 wkup */ | |
46 | struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = { | |
47 | .master = &am33xx_l3_s_hwmod, | |
48 | .slave = &am33xx_l4_wkup_hwmod, | |
49 | .clk = "l3s_gclk", | |
50 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
51 | }; | |
52 | ||
53 | /* l3 main -> l3 instr */ | |
54 | struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = { | |
55 | .master = &am33xx_l3_main_hwmod, | |
56 | .slave = &am33xx_l3_instr_hwmod, | |
57 | .clk = "l3s_gclk", | |
58 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
59 | }; | |
60 | ||
61 | /* mpu -> prcm */ | |
62 | struct omap_hwmod_ocp_if am33xx_mpu__prcm = { | |
63 | .master = &am33xx_mpu_hwmod, | |
64 | .slave = &am33xx_prcm_hwmod, | |
65 | .clk = "dpll_mpu_m2_ck", | |
66 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
67 | }; | |
68 | ||
69 | /* l3 s -> l3 main*/ | |
70 | struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = { | |
71 | .master = &am33xx_l3_s_hwmod, | |
72 | .slave = &am33xx_l3_main_hwmod, | |
73 | .clk = "l3s_gclk", | |
74 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
75 | }; | |
76 | ||
77 | /* pru-icss -> l3 main */ | |
78 | struct omap_hwmod_ocp_if am33xx_pruss__l3_main = { | |
79 | .master = &am33xx_pruss_hwmod, | |
80 | .slave = &am33xx_l3_main_hwmod, | |
81 | .clk = "l3_gclk", | |
82 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
83 | }; | |
84 | ||
85 | /* gfx -> l3 main */ | |
86 | struct omap_hwmod_ocp_if am33xx_gfx__l3_main = { | |
87 | .master = &am33xx_gfx_hwmod, | |
88 | .slave = &am33xx_l3_main_hwmod, | |
89 | .clk = "dpll_core_m4_ck", | |
90 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
91 | }; | |
92 | ||
93 | /* l3 main -> gfx */ | |
94 | struct omap_hwmod_ocp_if am33xx_l3_main__gfx = { | |
95 | .master = &am33xx_l3_main_hwmod, | |
96 | .slave = &am33xx_gfx_hwmod, | |
97 | .clk = "dpll_core_m4_ck", | |
98 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
99 | }; | |
100 | ||
101 | /* l4 wkup -> rtc */ | |
102 | struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = { | |
103 | .master = &am33xx_l4_wkup_hwmod, | |
104 | .slave = &am33xx_rtc_hwmod, | |
105 | .clk = "clkdiv32k_ick", | |
106 | .user = OCP_USER_MPU, | |
107 | }; | |
108 | ||
109 | /* l4 per/ls -> DCAN0 */ | |
110 | struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = { | |
111 | .master = &am33xx_l4_ls_hwmod, | |
112 | .slave = &am33xx_dcan0_hwmod, | |
113 | .clk = "l4ls_gclk", | |
114 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
115 | }; | |
116 | ||
117 | /* l4 per/ls -> DCAN1 */ | |
118 | struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = { | |
119 | .master = &am33xx_l4_ls_hwmod, | |
120 | .slave = &am33xx_dcan1_hwmod, | |
121 | .clk = "l4ls_gclk", | |
122 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
123 | }; | |
124 | ||
125 | /* l4 per/ls -> GPIO2 */ | |
126 | struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = { | |
127 | .master = &am33xx_l4_ls_hwmod, | |
128 | .slave = &am33xx_gpio1_hwmod, | |
129 | .clk = "l4ls_gclk", | |
130 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
131 | }; | |
132 | ||
133 | /* l4 per/ls -> gpio3 */ | |
134 | struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = { | |
135 | .master = &am33xx_l4_ls_hwmod, | |
136 | .slave = &am33xx_gpio2_hwmod, | |
137 | .clk = "l4ls_gclk", | |
138 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
139 | }; | |
140 | ||
141 | /* l4 per/ls -> gpio4 */ | |
142 | struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = { | |
143 | .master = &am33xx_l4_ls_hwmod, | |
144 | .slave = &am33xx_gpio3_hwmod, | |
145 | .clk = "l4ls_gclk", | |
146 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
147 | }; | |
148 | ||
149 | struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = { | |
150 | .master = &am33xx_cpgmac0_hwmod, | |
151 | .slave = &am33xx_mdio_hwmod, | |
152 | .user = OCP_USER_MPU, | |
153 | }; | |
154 | ||
26649467 AM |
155 | struct omap_hwmod_ocp_if am33xx_l4_ls__elm = { |
156 | .master = &am33xx_l4_ls_hwmod, | |
157 | .slave = &am33xx_elm_hwmod, | |
158 | .clk = "l4ls_gclk", | |
26649467 AM |
159 | .user = OCP_USER_MPU, |
160 | }; | |
161 | ||
162 | static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = { | |
163 | { | |
164 | .pa_start = 0x48300000, | |
165 | .pa_end = 0x48300000 + SZ_16 - 1, | |
166 | .flags = ADDR_TYPE_RT | |
167 | }, | |
168 | { } | |
169 | }; | |
170 | ||
171 | struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = { | |
172 | .master = &am33xx_l4_ls_hwmod, | |
173 | .slave = &am33xx_epwmss0_hwmod, | |
174 | .clk = "l4ls_gclk", | |
175 | .addr = am33xx_epwmss0_addr_space, | |
176 | .user = OCP_USER_MPU, | |
177 | }; | |
178 | ||
179 | struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = { | |
180 | .master = &am33xx_epwmss0_hwmod, | |
181 | .slave = &am33xx_ecap0_hwmod, | |
182 | .clk = "l4ls_gclk", | |
183 | .user = OCP_USER_MPU, | |
184 | }; | |
185 | ||
186 | struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = { | |
187 | .master = &am33xx_epwmss0_hwmod, | |
188 | .slave = &am33xx_eqep0_hwmod, | |
189 | .clk = "l4ls_gclk", | |
190 | .user = OCP_USER_MPU, | |
191 | }; | |
192 | ||
193 | struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = { | |
194 | .master = &am33xx_epwmss0_hwmod, | |
195 | .slave = &am33xx_ehrpwm0_hwmod, | |
196 | .clk = "l4ls_gclk", | |
197 | .user = OCP_USER_MPU, | |
198 | }; | |
199 | ||
200 | ||
201 | static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = { | |
202 | { | |
203 | .pa_start = 0x48302000, | |
204 | .pa_end = 0x48302000 + SZ_16 - 1, | |
205 | .flags = ADDR_TYPE_RT | |
206 | }, | |
207 | { } | |
208 | }; | |
209 | ||
210 | struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = { | |
211 | .master = &am33xx_l4_ls_hwmod, | |
212 | .slave = &am33xx_epwmss1_hwmod, | |
213 | .clk = "l4ls_gclk", | |
214 | .addr = am33xx_epwmss1_addr_space, | |
215 | .user = OCP_USER_MPU, | |
216 | }; | |
217 | ||
218 | struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = { | |
219 | .master = &am33xx_epwmss1_hwmod, | |
220 | .slave = &am33xx_ecap1_hwmod, | |
221 | .clk = "l4ls_gclk", | |
222 | .user = OCP_USER_MPU, | |
223 | }; | |
224 | ||
225 | struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = { | |
226 | .master = &am33xx_epwmss1_hwmod, | |
227 | .slave = &am33xx_eqep1_hwmod, | |
228 | .clk = "l4ls_gclk", | |
229 | .user = OCP_USER_MPU, | |
230 | }; | |
231 | ||
232 | struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = { | |
233 | .master = &am33xx_epwmss1_hwmod, | |
234 | .slave = &am33xx_ehrpwm1_hwmod, | |
235 | .clk = "l4ls_gclk", | |
236 | .user = OCP_USER_MPU, | |
237 | }; | |
238 | ||
239 | static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = { | |
240 | { | |
241 | .pa_start = 0x48304000, | |
242 | .pa_end = 0x48304000 + SZ_16 - 1, | |
243 | .flags = ADDR_TYPE_RT | |
244 | }, | |
245 | { } | |
246 | }; | |
247 | ||
248 | struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = { | |
249 | .master = &am33xx_l4_ls_hwmod, | |
250 | .slave = &am33xx_epwmss2_hwmod, | |
251 | .clk = "l4ls_gclk", | |
252 | .addr = am33xx_epwmss2_addr_space, | |
253 | .user = OCP_USER_MPU, | |
254 | }; | |
255 | ||
256 | struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = { | |
257 | .master = &am33xx_epwmss2_hwmod, | |
258 | .slave = &am33xx_ecap2_hwmod, | |
259 | .clk = "l4ls_gclk", | |
260 | .user = OCP_USER_MPU, | |
261 | }; | |
262 | ||
263 | struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = { | |
264 | .master = &am33xx_epwmss2_hwmod, | |
265 | .slave = &am33xx_eqep2_hwmod, | |
266 | .clk = "l4ls_gclk", | |
267 | .user = OCP_USER_MPU, | |
268 | }; | |
269 | ||
270 | struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = { | |
271 | .master = &am33xx_epwmss2_hwmod, | |
272 | .slave = &am33xx_ehrpwm2_hwmod, | |
273 | .clk = "l4ls_gclk", | |
274 | .user = OCP_USER_MPU, | |
275 | }; | |
276 | ||
277 | /* l3s cfg -> gpmc */ | |
26649467 AM |
278 | struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { |
279 | .master = &am33xx_l3_s_hwmod, | |
280 | .slave = &am33xx_gpmc_hwmod, | |
281 | .clk = "l3s_gclk", | |
26649467 AM |
282 | .user = OCP_USER_MPU, |
283 | }; | |
284 | ||
285 | /* i2c2 */ | |
286 | struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = { | |
287 | .master = &am33xx_l4_ls_hwmod, | |
288 | .slave = &am33xx_i2c2_hwmod, | |
289 | .clk = "l4ls_gclk", | |
290 | .user = OCP_USER_MPU, | |
291 | }; | |
292 | ||
293 | struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = { | |
294 | .master = &am33xx_l4_ls_hwmod, | |
295 | .slave = &am33xx_i2c3_hwmod, | |
296 | .clk = "l4ls_gclk", | |
297 | .user = OCP_USER_MPU, | |
298 | }; | |
299 | ||
26649467 AM |
300 | /* l4 ls -> mailbox */ |
301 | struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = { | |
302 | .master = &am33xx_l4_ls_hwmod, | |
303 | .slave = &am33xx_mailbox_hwmod, | |
304 | .clk = "l4ls_gclk", | |
26649467 AM |
305 | .user = OCP_USER_MPU, |
306 | }; | |
307 | ||
308 | /* l4 ls -> spinlock */ | |
309 | struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = { | |
310 | .master = &am33xx_l4_ls_hwmod, | |
311 | .slave = &am33xx_spinlock_hwmod, | |
312 | .clk = "l4ls_gclk", | |
313 | .user = OCP_USER_MPU, | |
314 | }; | |
315 | ||
316 | /* l4 ls -> mcasp0 */ | |
317 | static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = { | |
318 | { | |
319 | .pa_start = 0x48038000, | |
320 | .pa_end = 0x48038000 + SZ_8K - 1, | |
321 | .flags = ADDR_TYPE_RT | |
322 | }, | |
323 | { } | |
324 | }; | |
325 | ||
326 | struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = { | |
327 | .master = &am33xx_l4_ls_hwmod, | |
328 | .slave = &am33xx_mcasp0_hwmod, | |
329 | .clk = "l4ls_gclk", | |
330 | .addr = am33xx_mcasp0_addr_space, | |
331 | .user = OCP_USER_MPU, | |
332 | }; | |
333 | ||
334 | /* l4 ls -> mcasp1 */ | |
335 | static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = { | |
336 | { | |
337 | .pa_start = 0x4803C000, | |
338 | .pa_end = 0x4803C000 + SZ_8K - 1, | |
339 | .flags = ADDR_TYPE_RT | |
340 | }, | |
341 | { } | |
342 | }; | |
343 | ||
344 | struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = { | |
345 | .master = &am33xx_l4_ls_hwmod, | |
346 | .slave = &am33xx_mcasp1_hwmod, | |
347 | .clk = "l4ls_gclk", | |
348 | .addr = am33xx_mcasp1_addr_space, | |
349 | .user = OCP_USER_MPU, | |
350 | }; | |
351 | ||
352 | /* l4 ls -> mmc0 */ | |
353 | static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = { | |
354 | { | |
355 | .pa_start = 0x48060100, | |
356 | .pa_end = 0x48060100 + SZ_4K - 1, | |
357 | .flags = ADDR_TYPE_RT, | |
358 | }, | |
359 | { } | |
360 | }; | |
361 | ||
362 | struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = { | |
363 | .master = &am33xx_l4_ls_hwmod, | |
364 | .slave = &am33xx_mmc0_hwmod, | |
365 | .clk = "l4ls_gclk", | |
366 | .addr = am33xx_mmc0_addr_space, | |
367 | .user = OCP_USER_MPU, | |
368 | }; | |
369 | ||
370 | /* l4 ls -> mmc1 */ | |
371 | static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = { | |
372 | { | |
373 | .pa_start = 0x481d8100, | |
374 | .pa_end = 0x481d8100 + SZ_4K - 1, | |
375 | .flags = ADDR_TYPE_RT, | |
376 | }, | |
377 | { } | |
378 | }; | |
379 | ||
380 | struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = { | |
381 | .master = &am33xx_l4_ls_hwmod, | |
382 | .slave = &am33xx_mmc1_hwmod, | |
383 | .clk = "l4ls_gclk", | |
384 | .addr = am33xx_mmc1_addr_space, | |
385 | .user = OCP_USER_MPU, | |
386 | }; | |
387 | ||
388 | /* l3 s -> mmc2 */ | |
389 | static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = { | |
390 | { | |
391 | .pa_start = 0x47810100, | |
392 | .pa_end = 0x47810100 + SZ_64K - 1, | |
393 | .flags = ADDR_TYPE_RT, | |
394 | }, | |
395 | { } | |
396 | }; | |
397 | ||
398 | struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = { | |
399 | .master = &am33xx_l3_s_hwmod, | |
400 | .slave = &am33xx_mmc2_hwmod, | |
401 | .clk = "l3s_gclk", | |
402 | .addr = am33xx_mmc2_addr_space, | |
403 | .user = OCP_USER_MPU, | |
404 | }; | |
405 | ||
406 | /* l4 ls -> mcspi0 */ | |
407 | struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = { | |
408 | .master = &am33xx_l4_ls_hwmod, | |
409 | .slave = &am33xx_spi0_hwmod, | |
410 | .clk = "l4ls_gclk", | |
411 | .user = OCP_USER_MPU, | |
412 | }; | |
413 | ||
414 | /* l4 ls -> mcspi1 */ | |
415 | struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = { | |
416 | .master = &am33xx_l4_ls_hwmod, | |
417 | .slave = &am33xx_spi1_hwmod, | |
418 | .clk = "l4ls_gclk", | |
419 | .user = OCP_USER_MPU, | |
420 | }; | |
421 | ||
422 | /* l4 per -> timer2 */ | |
423 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { | |
424 | .master = &am33xx_l4_ls_hwmod, | |
425 | .slave = &am33xx_timer2_hwmod, | |
426 | .clk = "l4ls_gclk", | |
427 | .user = OCP_USER_MPU, | |
428 | }; | |
429 | ||
430 | /* l4 per -> timer3 */ | |
431 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = { | |
432 | .master = &am33xx_l4_ls_hwmod, | |
433 | .slave = &am33xx_timer3_hwmod, | |
434 | .clk = "l4ls_gclk", | |
435 | .user = OCP_USER_MPU, | |
436 | }; | |
437 | ||
438 | /* l4 per -> timer4 */ | |
439 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = { | |
440 | .master = &am33xx_l4_ls_hwmod, | |
441 | .slave = &am33xx_timer4_hwmod, | |
442 | .clk = "l4ls_gclk", | |
443 | .user = OCP_USER_MPU, | |
444 | }; | |
445 | ||
446 | /* l4 per -> timer5 */ | |
447 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = { | |
448 | .master = &am33xx_l4_ls_hwmod, | |
449 | .slave = &am33xx_timer5_hwmod, | |
450 | .clk = "l4ls_gclk", | |
451 | .user = OCP_USER_MPU, | |
452 | }; | |
453 | ||
454 | /* l4 per -> timer6 */ | |
455 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = { | |
456 | .master = &am33xx_l4_ls_hwmod, | |
457 | .slave = &am33xx_timer6_hwmod, | |
458 | .clk = "l4ls_gclk", | |
459 | .user = OCP_USER_MPU, | |
460 | }; | |
461 | ||
462 | /* l4 per -> timer7 */ | |
463 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = { | |
464 | .master = &am33xx_l4_ls_hwmod, | |
465 | .slave = &am33xx_timer7_hwmod, | |
466 | .clk = "l4ls_gclk", | |
467 | .user = OCP_USER_MPU, | |
468 | }; | |
469 | ||
470 | /* l3 main -> tpcc */ | |
471 | struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = { | |
472 | .master = &am33xx_l3_main_hwmod, | |
473 | .slave = &am33xx_tpcc_hwmod, | |
474 | .clk = "l3_gclk", | |
475 | .user = OCP_USER_MPU, | |
476 | }; | |
477 | ||
478 | /* l3 main -> tpcc0 */ | |
479 | static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = { | |
480 | { | |
481 | .pa_start = 0x49800000, | |
482 | .pa_end = 0x49800000 + SZ_8K - 1, | |
483 | .flags = ADDR_TYPE_RT, | |
484 | }, | |
485 | { } | |
486 | }; | |
487 | ||
488 | struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = { | |
489 | .master = &am33xx_l3_main_hwmod, | |
490 | .slave = &am33xx_tptc0_hwmod, | |
491 | .clk = "l3_gclk", | |
492 | .addr = am33xx_tptc0_addr_space, | |
493 | .user = OCP_USER_MPU, | |
494 | }; | |
495 | ||
496 | /* l3 main -> tpcc1 */ | |
497 | static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = { | |
498 | { | |
499 | .pa_start = 0x49900000, | |
500 | .pa_end = 0x49900000 + SZ_8K - 1, | |
501 | .flags = ADDR_TYPE_RT, | |
502 | }, | |
503 | { } | |
504 | }; | |
505 | ||
506 | struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = { | |
507 | .master = &am33xx_l3_main_hwmod, | |
508 | .slave = &am33xx_tptc1_hwmod, | |
509 | .clk = "l3_gclk", | |
510 | .addr = am33xx_tptc1_addr_space, | |
511 | .user = OCP_USER_MPU, | |
512 | }; | |
513 | ||
514 | /* l3 main -> tpcc2 */ | |
515 | static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = { | |
516 | { | |
517 | .pa_start = 0x49a00000, | |
518 | .pa_end = 0x49a00000 + SZ_8K - 1, | |
519 | .flags = ADDR_TYPE_RT, | |
520 | }, | |
521 | { } | |
522 | }; | |
523 | ||
524 | struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = { | |
525 | .master = &am33xx_l3_main_hwmod, | |
526 | .slave = &am33xx_tptc2_hwmod, | |
527 | .clk = "l3_gclk", | |
528 | .addr = am33xx_tptc2_addr_space, | |
529 | .user = OCP_USER_MPU, | |
530 | }; | |
531 | ||
532 | /* l4 ls -> uart2 */ | |
533 | struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = { | |
534 | .master = &am33xx_l4_ls_hwmod, | |
535 | .slave = &am33xx_uart2_hwmod, | |
536 | .clk = "l4ls_gclk", | |
537 | .user = OCP_USER_MPU, | |
538 | }; | |
539 | ||
540 | /* l4 ls -> uart3 */ | |
541 | struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = { | |
542 | .master = &am33xx_l4_ls_hwmod, | |
543 | .slave = &am33xx_uart3_hwmod, | |
544 | .clk = "l4ls_gclk", | |
545 | .user = OCP_USER_MPU, | |
546 | }; | |
547 | ||
548 | /* l4 ls -> uart4 */ | |
549 | struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = { | |
550 | .master = &am33xx_l4_ls_hwmod, | |
551 | .slave = &am33xx_uart4_hwmod, | |
552 | .clk = "l4ls_gclk", | |
553 | .user = OCP_USER_MPU, | |
554 | }; | |
555 | ||
556 | /* l4 ls -> uart5 */ | |
557 | struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = { | |
558 | .master = &am33xx_l4_ls_hwmod, | |
559 | .slave = &am33xx_uart5_hwmod, | |
560 | .clk = "l4ls_gclk", | |
561 | .user = OCP_USER_MPU, | |
562 | }; | |
563 | ||
564 | /* l4 ls -> uart6 */ | |
565 | struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = { | |
566 | .master = &am33xx_l4_ls_hwmod, | |
567 | .slave = &am33xx_uart6_hwmod, | |
568 | .clk = "l4ls_gclk", | |
569 | .user = OCP_USER_MPU, | |
570 | }; | |
571 | ||
572 | /* l3 main -> ocmc */ | |
573 | struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = { | |
574 | .master = &am33xx_l3_main_hwmod, | |
575 | .slave = &am33xx_ocmcram_hwmod, | |
576 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
577 | }; | |
578 | ||
579 | /* l3 main -> sha0 HIB2 */ | |
580 | static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = { | |
581 | { | |
582 | .pa_start = 0x53100000, | |
583 | .pa_end = 0x53100000 + SZ_512 - 1, | |
584 | .flags = ADDR_TYPE_RT | |
585 | }, | |
586 | { } | |
587 | }; | |
588 | ||
589 | struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = { | |
590 | .master = &am33xx_l3_main_hwmod, | |
591 | .slave = &am33xx_sha0_hwmod, | |
592 | .clk = "sha0_fck", | |
593 | .addr = am33xx_sha0_addrs, | |
594 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
595 | }; | |
596 | ||
597 | /* l3 main -> AES0 HIB2 */ | |
598 | static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = { | |
599 | { | |
600 | .pa_start = 0x53500000, | |
601 | .pa_end = 0x53500000 + SZ_1M - 1, | |
602 | .flags = ADDR_TYPE_RT | |
603 | }, | |
604 | { } | |
605 | }; | |
606 | ||
607 | struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = { | |
608 | .master = &am33xx_l3_main_hwmod, | |
609 | .slave = &am33xx_aes0_hwmod, | |
610 | .clk = "aes0_fck", | |
611 | .addr = am33xx_aes0_addrs, | |
612 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
613 | }; |