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26649467 AM |
1 | /* |
2 | * | |
3 | * Copyright (C) 2013 Texas Instruments Incorporated | |
4 | * | |
5 | * Interconnects common for AM335x and AM43x | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation version 2. | |
10 | * | |
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
12 | * kind, whether express or implied; without even the implied warranty | |
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/sizes.h> | |
18 | #include "omap_hwmod.h" | |
19 | #include "omap_hwmod_33xx_43xx_common_data.h" | |
20 | ||
21 | /* mpu -> l3 main */ | |
22 | struct omap_hwmod_ocp_if am33xx_mpu__l3_main = { | |
23 | .master = &am33xx_mpu_hwmod, | |
24 | .slave = &am33xx_l3_main_hwmod, | |
25 | .clk = "dpll_mpu_m2_ck", | |
26 | .user = OCP_USER_MPU, | |
27 | }; | |
28 | ||
29 | /* l3 main -> l3 s */ | |
30 | struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = { | |
31 | .master = &am33xx_l3_main_hwmod, | |
32 | .slave = &am33xx_l3_s_hwmod, | |
33 | .clk = "l3s_gclk", | |
34 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
35 | }; | |
36 | ||
37 | /* l3 s -> l4 per/ls */ | |
38 | struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = { | |
39 | .master = &am33xx_l3_s_hwmod, | |
40 | .slave = &am33xx_l4_ls_hwmod, | |
41 | .clk = "l3s_gclk", | |
42 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
43 | }; | |
44 | ||
45 | /* l3 s -> l4 wkup */ | |
46 | struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = { | |
47 | .master = &am33xx_l3_s_hwmod, | |
48 | .slave = &am33xx_l4_wkup_hwmod, | |
49 | .clk = "l3s_gclk", | |
50 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
51 | }; | |
52 | ||
53 | /* l3 main -> l3 instr */ | |
54 | struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = { | |
55 | .master = &am33xx_l3_main_hwmod, | |
56 | .slave = &am33xx_l3_instr_hwmod, | |
57 | .clk = "l3s_gclk", | |
58 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
59 | }; | |
60 | ||
61 | /* mpu -> prcm */ | |
62 | struct omap_hwmod_ocp_if am33xx_mpu__prcm = { | |
63 | .master = &am33xx_mpu_hwmod, | |
64 | .slave = &am33xx_prcm_hwmod, | |
65 | .clk = "dpll_mpu_m2_ck", | |
66 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
67 | }; | |
68 | ||
69 | /* l3 s -> l3 main*/ | |
70 | struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = { | |
71 | .master = &am33xx_l3_s_hwmod, | |
72 | .slave = &am33xx_l3_main_hwmod, | |
73 | .clk = "l3s_gclk", | |
74 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
75 | }; | |
76 | ||
77 | /* pru-icss -> l3 main */ | |
78 | struct omap_hwmod_ocp_if am33xx_pruss__l3_main = { | |
79 | .master = &am33xx_pruss_hwmod, | |
80 | .slave = &am33xx_l3_main_hwmod, | |
81 | .clk = "l3_gclk", | |
82 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
83 | }; | |
84 | ||
85 | /* gfx -> l3 main */ | |
86 | struct omap_hwmod_ocp_if am33xx_gfx__l3_main = { | |
87 | .master = &am33xx_gfx_hwmod, | |
88 | .slave = &am33xx_l3_main_hwmod, | |
89 | .clk = "dpll_core_m4_ck", | |
90 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
91 | }; | |
92 | ||
93 | /* l3 main -> gfx */ | |
94 | struct omap_hwmod_ocp_if am33xx_l3_main__gfx = { | |
95 | .master = &am33xx_l3_main_hwmod, | |
96 | .slave = &am33xx_gfx_hwmod, | |
97 | .clk = "dpll_core_m4_ck", | |
98 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
99 | }; | |
100 | ||
101 | /* l4 wkup -> rtc */ | |
102 | struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = { | |
103 | .master = &am33xx_l4_wkup_hwmod, | |
104 | .slave = &am33xx_rtc_hwmod, | |
105 | .clk = "clkdiv32k_ick", | |
106 | .user = OCP_USER_MPU, | |
107 | }; | |
108 | ||
109 | /* l4 per/ls -> DCAN0 */ | |
110 | struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = { | |
111 | .master = &am33xx_l4_ls_hwmod, | |
112 | .slave = &am33xx_dcan0_hwmod, | |
113 | .clk = "l4ls_gclk", | |
114 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
115 | }; | |
116 | ||
117 | /* l4 per/ls -> DCAN1 */ | |
118 | struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = { | |
119 | .master = &am33xx_l4_ls_hwmod, | |
120 | .slave = &am33xx_dcan1_hwmod, | |
121 | .clk = "l4ls_gclk", | |
122 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
123 | }; | |
124 | ||
125 | /* l4 per/ls -> GPIO2 */ | |
126 | struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = { | |
127 | .master = &am33xx_l4_ls_hwmod, | |
128 | .slave = &am33xx_gpio1_hwmod, | |
129 | .clk = "l4ls_gclk", | |
130 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
131 | }; | |
132 | ||
133 | /* l4 per/ls -> gpio3 */ | |
134 | struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = { | |
135 | .master = &am33xx_l4_ls_hwmod, | |
136 | .slave = &am33xx_gpio2_hwmod, | |
137 | .clk = "l4ls_gclk", | |
138 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
139 | }; | |
140 | ||
141 | /* l4 per/ls -> gpio4 */ | |
142 | struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = { | |
143 | .master = &am33xx_l4_ls_hwmod, | |
144 | .slave = &am33xx_gpio3_hwmod, | |
145 | .clk = "l4ls_gclk", | |
146 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
147 | }; | |
148 | ||
149 | struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = { | |
150 | .master = &am33xx_cpgmac0_hwmod, | |
151 | .slave = &am33xx_mdio_hwmod, | |
152 | .user = OCP_USER_MPU, | |
153 | }; | |
154 | ||
155 | static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = { | |
156 | { | |
157 | .pa_start = 0x48080000, | |
158 | .pa_end = 0x48080000 + SZ_8K - 1, | |
159 | .flags = ADDR_TYPE_RT | |
160 | }, | |
161 | { } | |
162 | }; | |
163 | ||
164 | struct omap_hwmod_ocp_if am33xx_l4_ls__elm = { | |
165 | .master = &am33xx_l4_ls_hwmod, | |
166 | .slave = &am33xx_elm_hwmod, | |
167 | .clk = "l4ls_gclk", | |
168 | .addr = am33xx_elm_addr_space, | |
169 | .user = OCP_USER_MPU, | |
170 | }; | |
171 | ||
172 | static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = { | |
173 | { | |
174 | .pa_start = 0x48300000, | |
175 | .pa_end = 0x48300000 + SZ_16 - 1, | |
176 | .flags = ADDR_TYPE_RT | |
177 | }, | |
178 | { } | |
179 | }; | |
180 | ||
181 | struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = { | |
182 | .master = &am33xx_l4_ls_hwmod, | |
183 | .slave = &am33xx_epwmss0_hwmod, | |
184 | .clk = "l4ls_gclk", | |
185 | .addr = am33xx_epwmss0_addr_space, | |
186 | .user = OCP_USER_MPU, | |
187 | }; | |
188 | ||
189 | struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = { | |
190 | .master = &am33xx_epwmss0_hwmod, | |
191 | .slave = &am33xx_ecap0_hwmod, | |
192 | .clk = "l4ls_gclk", | |
193 | .user = OCP_USER_MPU, | |
194 | }; | |
195 | ||
196 | struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = { | |
197 | .master = &am33xx_epwmss0_hwmod, | |
198 | .slave = &am33xx_eqep0_hwmod, | |
199 | .clk = "l4ls_gclk", | |
200 | .user = OCP_USER_MPU, | |
201 | }; | |
202 | ||
203 | struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = { | |
204 | .master = &am33xx_epwmss0_hwmod, | |
205 | .slave = &am33xx_ehrpwm0_hwmod, | |
206 | .clk = "l4ls_gclk", | |
207 | .user = OCP_USER_MPU, | |
208 | }; | |
209 | ||
210 | ||
211 | static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = { | |
212 | { | |
213 | .pa_start = 0x48302000, | |
214 | .pa_end = 0x48302000 + SZ_16 - 1, | |
215 | .flags = ADDR_TYPE_RT | |
216 | }, | |
217 | { } | |
218 | }; | |
219 | ||
220 | struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = { | |
221 | .master = &am33xx_l4_ls_hwmod, | |
222 | .slave = &am33xx_epwmss1_hwmod, | |
223 | .clk = "l4ls_gclk", | |
224 | .addr = am33xx_epwmss1_addr_space, | |
225 | .user = OCP_USER_MPU, | |
226 | }; | |
227 | ||
228 | struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = { | |
229 | .master = &am33xx_epwmss1_hwmod, | |
230 | .slave = &am33xx_ecap1_hwmod, | |
231 | .clk = "l4ls_gclk", | |
232 | .user = OCP_USER_MPU, | |
233 | }; | |
234 | ||
235 | struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = { | |
236 | .master = &am33xx_epwmss1_hwmod, | |
237 | .slave = &am33xx_eqep1_hwmod, | |
238 | .clk = "l4ls_gclk", | |
239 | .user = OCP_USER_MPU, | |
240 | }; | |
241 | ||
242 | struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = { | |
243 | .master = &am33xx_epwmss1_hwmod, | |
244 | .slave = &am33xx_ehrpwm1_hwmod, | |
245 | .clk = "l4ls_gclk", | |
246 | .user = OCP_USER_MPU, | |
247 | }; | |
248 | ||
249 | static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = { | |
250 | { | |
251 | .pa_start = 0x48304000, | |
252 | .pa_end = 0x48304000 + SZ_16 - 1, | |
253 | .flags = ADDR_TYPE_RT | |
254 | }, | |
255 | { } | |
256 | }; | |
257 | ||
258 | struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = { | |
259 | .master = &am33xx_l4_ls_hwmod, | |
260 | .slave = &am33xx_epwmss2_hwmod, | |
261 | .clk = "l4ls_gclk", | |
262 | .addr = am33xx_epwmss2_addr_space, | |
263 | .user = OCP_USER_MPU, | |
264 | }; | |
265 | ||
266 | struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = { | |
267 | .master = &am33xx_epwmss2_hwmod, | |
268 | .slave = &am33xx_ecap2_hwmod, | |
269 | .clk = "l4ls_gclk", | |
270 | .user = OCP_USER_MPU, | |
271 | }; | |
272 | ||
273 | struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = { | |
274 | .master = &am33xx_epwmss2_hwmod, | |
275 | .slave = &am33xx_eqep2_hwmod, | |
276 | .clk = "l4ls_gclk", | |
277 | .user = OCP_USER_MPU, | |
278 | }; | |
279 | ||
280 | struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = { | |
281 | .master = &am33xx_epwmss2_hwmod, | |
282 | .slave = &am33xx_ehrpwm2_hwmod, | |
283 | .clk = "l4ls_gclk", | |
284 | .user = OCP_USER_MPU, | |
285 | }; | |
286 | ||
287 | /* l3s cfg -> gpmc */ | |
288 | static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = { | |
289 | { | |
290 | .pa_start = 0x50000000, | |
291 | .pa_end = 0x50000000 + SZ_8K - 1, | |
292 | .flags = ADDR_TYPE_RT, | |
293 | }, | |
294 | { } | |
295 | }; | |
296 | ||
297 | struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { | |
298 | .master = &am33xx_l3_s_hwmod, | |
299 | .slave = &am33xx_gpmc_hwmod, | |
300 | .clk = "l3s_gclk", | |
301 | .addr = am33xx_gpmc_addr_space, | |
302 | .user = OCP_USER_MPU, | |
303 | }; | |
304 | ||
305 | /* i2c2 */ | |
306 | struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = { | |
307 | .master = &am33xx_l4_ls_hwmod, | |
308 | .slave = &am33xx_i2c2_hwmod, | |
309 | .clk = "l4ls_gclk", | |
310 | .user = OCP_USER_MPU, | |
311 | }; | |
312 | ||
313 | struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = { | |
314 | .master = &am33xx_l4_ls_hwmod, | |
315 | .slave = &am33xx_i2c3_hwmod, | |
316 | .clk = "l4ls_gclk", | |
317 | .user = OCP_USER_MPU, | |
318 | }; | |
319 | ||
26649467 AM |
320 | /* l4 ls -> mailbox */ |
321 | struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = { | |
322 | .master = &am33xx_l4_ls_hwmod, | |
323 | .slave = &am33xx_mailbox_hwmod, | |
324 | .clk = "l4ls_gclk", | |
26649467 AM |
325 | .user = OCP_USER_MPU, |
326 | }; | |
327 | ||
328 | /* l4 ls -> spinlock */ | |
329 | struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = { | |
330 | .master = &am33xx_l4_ls_hwmod, | |
331 | .slave = &am33xx_spinlock_hwmod, | |
332 | .clk = "l4ls_gclk", | |
333 | .user = OCP_USER_MPU, | |
334 | }; | |
335 | ||
336 | /* l4 ls -> mcasp0 */ | |
337 | static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = { | |
338 | { | |
339 | .pa_start = 0x48038000, | |
340 | .pa_end = 0x48038000 + SZ_8K - 1, | |
341 | .flags = ADDR_TYPE_RT | |
342 | }, | |
343 | { } | |
344 | }; | |
345 | ||
346 | struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = { | |
347 | .master = &am33xx_l4_ls_hwmod, | |
348 | .slave = &am33xx_mcasp0_hwmod, | |
349 | .clk = "l4ls_gclk", | |
350 | .addr = am33xx_mcasp0_addr_space, | |
351 | .user = OCP_USER_MPU, | |
352 | }; | |
353 | ||
354 | /* l4 ls -> mcasp1 */ | |
355 | static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = { | |
356 | { | |
357 | .pa_start = 0x4803C000, | |
358 | .pa_end = 0x4803C000 + SZ_8K - 1, | |
359 | .flags = ADDR_TYPE_RT | |
360 | }, | |
361 | { } | |
362 | }; | |
363 | ||
364 | struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = { | |
365 | .master = &am33xx_l4_ls_hwmod, | |
366 | .slave = &am33xx_mcasp1_hwmod, | |
367 | .clk = "l4ls_gclk", | |
368 | .addr = am33xx_mcasp1_addr_space, | |
369 | .user = OCP_USER_MPU, | |
370 | }; | |
371 | ||
372 | /* l4 ls -> mmc0 */ | |
373 | static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = { | |
374 | { | |
375 | .pa_start = 0x48060100, | |
376 | .pa_end = 0x48060100 + SZ_4K - 1, | |
377 | .flags = ADDR_TYPE_RT, | |
378 | }, | |
379 | { } | |
380 | }; | |
381 | ||
382 | struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = { | |
383 | .master = &am33xx_l4_ls_hwmod, | |
384 | .slave = &am33xx_mmc0_hwmod, | |
385 | .clk = "l4ls_gclk", | |
386 | .addr = am33xx_mmc0_addr_space, | |
387 | .user = OCP_USER_MPU, | |
388 | }; | |
389 | ||
390 | /* l4 ls -> mmc1 */ | |
391 | static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = { | |
392 | { | |
393 | .pa_start = 0x481d8100, | |
394 | .pa_end = 0x481d8100 + SZ_4K - 1, | |
395 | .flags = ADDR_TYPE_RT, | |
396 | }, | |
397 | { } | |
398 | }; | |
399 | ||
400 | struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = { | |
401 | .master = &am33xx_l4_ls_hwmod, | |
402 | .slave = &am33xx_mmc1_hwmod, | |
403 | .clk = "l4ls_gclk", | |
404 | .addr = am33xx_mmc1_addr_space, | |
405 | .user = OCP_USER_MPU, | |
406 | }; | |
407 | ||
408 | /* l3 s -> mmc2 */ | |
409 | static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = { | |
410 | { | |
411 | .pa_start = 0x47810100, | |
412 | .pa_end = 0x47810100 + SZ_64K - 1, | |
413 | .flags = ADDR_TYPE_RT, | |
414 | }, | |
415 | { } | |
416 | }; | |
417 | ||
418 | struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = { | |
419 | .master = &am33xx_l3_s_hwmod, | |
420 | .slave = &am33xx_mmc2_hwmod, | |
421 | .clk = "l3s_gclk", | |
422 | .addr = am33xx_mmc2_addr_space, | |
423 | .user = OCP_USER_MPU, | |
424 | }; | |
425 | ||
426 | /* l4 ls -> mcspi0 */ | |
427 | struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = { | |
428 | .master = &am33xx_l4_ls_hwmod, | |
429 | .slave = &am33xx_spi0_hwmod, | |
430 | .clk = "l4ls_gclk", | |
431 | .user = OCP_USER_MPU, | |
432 | }; | |
433 | ||
434 | /* l4 ls -> mcspi1 */ | |
435 | struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = { | |
436 | .master = &am33xx_l4_ls_hwmod, | |
437 | .slave = &am33xx_spi1_hwmod, | |
438 | .clk = "l4ls_gclk", | |
439 | .user = OCP_USER_MPU, | |
440 | }; | |
441 | ||
442 | /* l4 per -> timer2 */ | |
443 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { | |
444 | .master = &am33xx_l4_ls_hwmod, | |
445 | .slave = &am33xx_timer2_hwmod, | |
446 | .clk = "l4ls_gclk", | |
447 | .user = OCP_USER_MPU, | |
448 | }; | |
449 | ||
450 | /* l4 per -> timer3 */ | |
451 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = { | |
452 | .master = &am33xx_l4_ls_hwmod, | |
453 | .slave = &am33xx_timer3_hwmod, | |
454 | .clk = "l4ls_gclk", | |
455 | .user = OCP_USER_MPU, | |
456 | }; | |
457 | ||
458 | /* l4 per -> timer4 */ | |
459 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = { | |
460 | .master = &am33xx_l4_ls_hwmod, | |
461 | .slave = &am33xx_timer4_hwmod, | |
462 | .clk = "l4ls_gclk", | |
463 | .user = OCP_USER_MPU, | |
464 | }; | |
465 | ||
466 | /* l4 per -> timer5 */ | |
467 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = { | |
468 | .master = &am33xx_l4_ls_hwmod, | |
469 | .slave = &am33xx_timer5_hwmod, | |
470 | .clk = "l4ls_gclk", | |
471 | .user = OCP_USER_MPU, | |
472 | }; | |
473 | ||
474 | /* l4 per -> timer6 */ | |
475 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = { | |
476 | .master = &am33xx_l4_ls_hwmod, | |
477 | .slave = &am33xx_timer6_hwmod, | |
478 | .clk = "l4ls_gclk", | |
479 | .user = OCP_USER_MPU, | |
480 | }; | |
481 | ||
482 | /* l4 per -> timer7 */ | |
483 | struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = { | |
484 | .master = &am33xx_l4_ls_hwmod, | |
485 | .slave = &am33xx_timer7_hwmod, | |
486 | .clk = "l4ls_gclk", | |
487 | .user = OCP_USER_MPU, | |
488 | }; | |
489 | ||
490 | /* l3 main -> tpcc */ | |
491 | struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = { | |
492 | .master = &am33xx_l3_main_hwmod, | |
493 | .slave = &am33xx_tpcc_hwmod, | |
494 | .clk = "l3_gclk", | |
495 | .user = OCP_USER_MPU, | |
496 | }; | |
497 | ||
498 | /* l3 main -> tpcc0 */ | |
499 | static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = { | |
500 | { | |
501 | .pa_start = 0x49800000, | |
502 | .pa_end = 0x49800000 + SZ_8K - 1, | |
503 | .flags = ADDR_TYPE_RT, | |
504 | }, | |
505 | { } | |
506 | }; | |
507 | ||
508 | struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = { | |
509 | .master = &am33xx_l3_main_hwmod, | |
510 | .slave = &am33xx_tptc0_hwmod, | |
511 | .clk = "l3_gclk", | |
512 | .addr = am33xx_tptc0_addr_space, | |
513 | .user = OCP_USER_MPU, | |
514 | }; | |
515 | ||
516 | /* l3 main -> tpcc1 */ | |
517 | static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = { | |
518 | { | |
519 | .pa_start = 0x49900000, | |
520 | .pa_end = 0x49900000 + SZ_8K - 1, | |
521 | .flags = ADDR_TYPE_RT, | |
522 | }, | |
523 | { } | |
524 | }; | |
525 | ||
526 | struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = { | |
527 | .master = &am33xx_l3_main_hwmod, | |
528 | .slave = &am33xx_tptc1_hwmod, | |
529 | .clk = "l3_gclk", | |
530 | .addr = am33xx_tptc1_addr_space, | |
531 | .user = OCP_USER_MPU, | |
532 | }; | |
533 | ||
534 | /* l3 main -> tpcc2 */ | |
535 | static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = { | |
536 | { | |
537 | .pa_start = 0x49a00000, | |
538 | .pa_end = 0x49a00000 + SZ_8K - 1, | |
539 | .flags = ADDR_TYPE_RT, | |
540 | }, | |
541 | { } | |
542 | }; | |
543 | ||
544 | struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = { | |
545 | .master = &am33xx_l3_main_hwmod, | |
546 | .slave = &am33xx_tptc2_hwmod, | |
547 | .clk = "l3_gclk", | |
548 | .addr = am33xx_tptc2_addr_space, | |
549 | .user = OCP_USER_MPU, | |
550 | }; | |
551 | ||
552 | /* l4 ls -> uart2 */ | |
553 | struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = { | |
554 | .master = &am33xx_l4_ls_hwmod, | |
555 | .slave = &am33xx_uart2_hwmod, | |
556 | .clk = "l4ls_gclk", | |
557 | .user = OCP_USER_MPU, | |
558 | }; | |
559 | ||
560 | /* l4 ls -> uart3 */ | |
561 | struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = { | |
562 | .master = &am33xx_l4_ls_hwmod, | |
563 | .slave = &am33xx_uart3_hwmod, | |
564 | .clk = "l4ls_gclk", | |
565 | .user = OCP_USER_MPU, | |
566 | }; | |
567 | ||
568 | /* l4 ls -> uart4 */ | |
569 | struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = { | |
570 | .master = &am33xx_l4_ls_hwmod, | |
571 | .slave = &am33xx_uart4_hwmod, | |
572 | .clk = "l4ls_gclk", | |
573 | .user = OCP_USER_MPU, | |
574 | }; | |
575 | ||
576 | /* l4 ls -> uart5 */ | |
577 | struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = { | |
578 | .master = &am33xx_l4_ls_hwmod, | |
579 | .slave = &am33xx_uart5_hwmod, | |
580 | .clk = "l4ls_gclk", | |
581 | .user = OCP_USER_MPU, | |
582 | }; | |
583 | ||
584 | /* l4 ls -> uart6 */ | |
585 | struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = { | |
586 | .master = &am33xx_l4_ls_hwmod, | |
587 | .slave = &am33xx_uart6_hwmod, | |
588 | .clk = "l4ls_gclk", | |
589 | .user = OCP_USER_MPU, | |
590 | }; | |
591 | ||
592 | /* l3 main -> ocmc */ | |
593 | struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = { | |
594 | .master = &am33xx_l3_main_hwmod, | |
595 | .slave = &am33xx_ocmcram_hwmod, | |
596 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
597 | }; | |
598 | ||
599 | /* l3 main -> sha0 HIB2 */ | |
600 | static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = { | |
601 | { | |
602 | .pa_start = 0x53100000, | |
603 | .pa_end = 0x53100000 + SZ_512 - 1, | |
604 | .flags = ADDR_TYPE_RT | |
605 | }, | |
606 | { } | |
607 | }; | |
608 | ||
609 | struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = { | |
610 | .master = &am33xx_l3_main_hwmod, | |
611 | .slave = &am33xx_sha0_hwmod, | |
612 | .clk = "sha0_fck", | |
613 | .addr = am33xx_sha0_addrs, | |
614 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
615 | }; | |
616 | ||
617 | /* l3 main -> AES0 HIB2 */ | |
618 | static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = { | |
619 | { | |
620 | .pa_start = 0x53500000, | |
621 | .pa_end = 0x53500000 + SZ_1M - 1, | |
622 | .flags = ADDR_TYPE_RT | |
623 | }, | |
624 | { } | |
625 | }; | |
626 | ||
627 | struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = { | |
628 | .master = &am33xx_l3_main_hwmod, | |
629 | .slave = &am33xx_aes0_hwmod, | |
630 | .clk = "aes0_fck", | |
631 | .addr = am33xx_aes0_addrs, | |
632 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
633 | }; |