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Merge branch 'sched-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_33xx_data.c
CommitLineData
a2cfc509
VH		 1/*
2 * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
3 *
4 * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
3a8761c0
TL		 17#include <linux/i2c-omap.h>
18
2a296c8f 19#include "omap_hwmod.h"
11964f53 20#include <linux/platform_data/gpio-omap.h>
aa817b2e 21#include <linux/platform_data/spi-omap2-mcspi.h>
a2cfc509
VH		 22
23#include "omap_hwmod_common_data.h"
24
25#include "control.h"
26#include "cm33xx.h"
27#include "prm33xx.h"
28#include "prm-regbits-33xx.h"
3a8761c0 29#include "i2c.h"
68f39e74 30#include "mmc.h"
05cf03b6 31#include "wd_timer.h"
a2cfc509 32
a2cfc509
VH		 33/*
34 * IP blocks
35 */
36
37/*
38 * 'emif_fw' class
39 * instance(s): emif_fw
40 */
41static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
42 .name = "emif_fw",
43};
44
45/* emif_fw */
46static struct omap_hwmod am33xx_emif_fw_hwmod = {
47 .name = "emif_fw",
48 .class = &am33xx_emif_fw_hwmod_class,
49 .clkdm_name = "l4fw_clkdm",
50 .main_clk = "l4fw_gclk",
51 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
52 .prcm = {
53 .omap4 = {
54 .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
55 .modulemode = MODULEMODE_SWCTRL,
56 },
57 },
58};
59
60/*
61 * 'emif' class
62 * instance(s): emif
63 */
64static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
65 .rev_offs = 0x0000,
66};
67
68static struct omap_hwmod_class am33xx_emif_hwmod_class = {
69 .name = "emif",
70 .sysc = &am33xx_emif_sysc,
71};
72
73static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
74 { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
75 { .irq = -1 },
76};
77
78/* emif */
79static struct omap_hwmod am33xx_emif_hwmod = {
80 .name = "emif",
81 .class = &am33xx_emif_hwmod_class,
82 .clkdm_name = "l3_clkdm",
83 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
84 .mpu_irqs = am33xx_emif_irqs,
85 .main_clk = "dpll_ddr_m2_div2_ck",
86 .prcm = {
87 .omap4 = {
88 .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
89 .modulemode = MODULEMODE_SWCTRL,
90 },
91 },
92};
93
94/*
95 * 'l3' class
96 * instance(s): l3_main, l3_s, l3_instr
97 */
98static struct omap_hwmod_class am33xx_l3_hwmod_class = {
99 .name = "l3",
100};
101
102/* l3_main (l3_fast) */
103static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
104 { .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
105 { .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
106 { .irq = -1 },
107};
108
109static struct omap_hwmod am33xx_l3_main_hwmod = {
110 .name = "l3_main",
111 .class = &am33xx_l3_hwmod_class,
112 .clkdm_name = "l3_clkdm",
113 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
114 .mpu_irqs = am33xx_l3_main_irqs,
115 .main_clk = "l3_gclk",
116 .prcm = {
117 .omap4 = {
118 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
119 .modulemode = MODULEMODE_SWCTRL,
120 },
121 },
122};
123
124/* l3_s */
125static struct omap_hwmod am33xx_l3_s_hwmod = {
126 .name = "l3_s",
127 .class = &am33xx_l3_hwmod_class,
128 .clkdm_name = "l3s_clkdm",
129};
130
131/* l3_instr */
132static struct omap_hwmod am33xx_l3_instr_hwmod = {
133 .name = "l3_instr",
134 .class = &am33xx_l3_hwmod_class,
135 .clkdm_name = "l3_clkdm",
136 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
137 .main_clk = "l3_gclk",
138 .prcm = {
139 .omap4 = {
140 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
141 .modulemode = MODULEMODE_SWCTRL,
142 },
143 },
144};
145
146/*
147 * 'l4' class
148 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
149 */
150static struct omap_hwmod_class am33xx_l4_hwmod_class = {
151 .name = "l4",
152};
153
154/* l4_ls */
155static struct omap_hwmod am33xx_l4_ls_hwmod = {
156 .name = "l4_ls",
157 .class = &am33xx_l4_hwmod_class,
158 .clkdm_name = "l4ls_clkdm",
159 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
160 .main_clk = "l4ls_gclk",
161 .prcm = {
162 .omap4 = {
163 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
164 .modulemode = MODULEMODE_SWCTRL,
165 },
166 },
167};
168
169/* l4_hs */
170static struct omap_hwmod am33xx_l4_hs_hwmod = {
171 .name = "l4_hs",
172 .class = &am33xx_l4_hwmod_class,
173 .clkdm_name = "l4hs_clkdm",
174 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
175 .main_clk = "l4hs_gclk",
176 .prcm = {
177 .omap4 = {
178 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
179 .modulemode = MODULEMODE_SWCTRL,
180 },
181 },
182};
183
184
185/* l4_wkup */
186static struct omap_hwmod am33xx_l4_wkup_hwmod = {
187 .name = "l4_wkup",
188 .class = &am33xx_l4_hwmod_class,
189 .clkdm_name = "l4_wkup_clkdm",
190 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
191 .prcm = {
192 .omap4 = {
193 .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
194 .modulemode = MODULEMODE_SWCTRL,
195 },
196 },
197};
198
199/* l4_fw */
200static struct omap_hwmod am33xx_l4_fw_hwmod = {
201 .name = "l4_fw",
202 .class = &am33xx_l4_hwmod_class,
203 .clkdm_name = "l4fw_clkdm",
204 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
205 .prcm = {
206 .omap4 = {
207 .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
208 .modulemode = MODULEMODE_SWCTRL,
209 },
210 },
211};
212
213/*
214 * 'mpu' class
215 */
216static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
217 .name = "mpu",
218};
219
220/* mpu */
221static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
222 { .name = "emuint", .irq = 0 + OMAP_INTC_START, },
223 { .name = "commtx", .irq = 1 + OMAP_INTC_START, },
224 { .name = "commrx", .irq = 2 + OMAP_INTC_START, },
225 { .name = "bench", .irq = 3 + OMAP_INTC_START, },
226 { .irq = -1 },
227};
228
229static struct omap_hwmod am33xx_mpu_hwmod = {
230 .name = "mpu",
231 .class = &am33xx_mpu_hwmod_class,
232 .clkdm_name = "mpu_clkdm",
233 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
234 .mpu_irqs = am33xx_mpu_irqs,
235 .main_clk = "dpll_mpu_m2_ck",
236 .prcm = {
237 .omap4 = {
238 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
239 .modulemode = MODULEMODE_SWCTRL,
240 },
241 },
242};
243
244/*
245 * 'wakeup m3' class
246 * Wakeup controller sub-system under wakeup domain
247 */
248static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
249 .name = "wkup_m3",
250};
251
252static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
253 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
254};
255
256static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
257 { .name = "txev", .irq = 78 + OMAP_INTC_START, },
258 { .irq = -1 },
259};
260
261/* wkup_m3 */
262static struct omap_hwmod am33xx_wkup_m3_hwmod = {
263 .name = "wkup_m3",
264 .class = &am33xx_wkup_m3_hwmod_class,
265 .clkdm_name = "l4_wkup_aon_clkdm",
092bda62
HG		 266 /* Keep hardreset asserted */
267 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
a2cfc509
VH		 268 .mpu_irqs = am33xx_wkup_m3_irqs,
269 .main_clk = "dpll_core_m4_div2_ck",
270 .prcm = {
271 .omap4 = {
272 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
273 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
3077fe69 274 .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
a2cfc509
VH		 275 .modulemode = MODULEMODE_SWCTRL,
276 },
277 },
278 .rst_lines = am33xx_wkup_m3_resets,
279 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
280};
281
282/*
283 * 'pru-icss' class
284 * Programmable Real-Time Unit and Industrial Communication Subsystem
285 */
286static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
287 .name = "pruss",
288};
289
290static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
291 { .name = "pruss", .rst_shift = 1 },
292};
293
294static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
295 { .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
296 { .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
297 { .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
298 { .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
299 { .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
300 { .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
301 { .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
302 { .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
303 { .irq = -1 },
304};
305
306/* pru-icss */
307/* Pseudo hwmod for reset control purpose only */
308static struct omap_hwmod am33xx_pruss_hwmod = {
309 .name = "pruss",
310 .class = &am33xx_pruss_hwmod_class,
311 .clkdm_name = "pruss_ocp_clkdm",
312 .mpu_irqs = am33xx_pruss_irqs,
313 .main_clk = "pruss_ocp_gclk",
314 .prcm = {
315 .omap4 = {
316 .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
317 .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
318 .modulemode = MODULEMODE_SWCTRL,
319 },
320 },
321 .rst_lines = am33xx_pruss_resets,
322 .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
323};
324
325/* gfx */
326/* Pseudo hwmod for reset control purpose only */
327static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
328 .name = "gfx",
329};
330
331static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
332 { .name = "gfx", .rst_shift = 0 },
333};
334
335static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
336 { .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
337 { .irq = -1 },
338};
339
340static struct omap_hwmod am33xx_gfx_hwmod = {
341 .name = "gfx",
342 .class = &am33xx_gfx_hwmod_class,
343 .clkdm_name = "gfx_l3_clkdm",
344 .mpu_irqs = am33xx_gfx_irqs,
345 .main_clk = "gfx_fck_div_ck",
346 .prcm = {
347 .omap4 = {
348 .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
349 .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
350 .modulemode = MODULEMODE_SWCTRL,
351 },
352 },
353 .rst_lines = am33xx_gfx_resets,
354 .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
355};
356
357/*
358 * 'prcm' class
359 * power and reset manager (whole prcm infrastructure)
360 */
361static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
362 .name = "prcm",
363};
364
365/* prcm */
366static struct omap_hwmod am33xx_prcm_hwmod = {
367 .name = "prcm",
368 .class = &am33xx_prcm_hwmod_class,
369 .clkdm_name = "l4_wkup_clkdm",
370};
371
372/*
373 * 'adc/tsc' class
374 * TouchScreen Controller (Anolog-To-Digital Converter)
375 */
376static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
377 .rev_offs = 0x00,
378 .sysc_offs = 0x10,
379 .sysc_flags = SYSC_HAS_SIDLEMODE,
380 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
381 SIDLE_SMART_WKUP),
382 .sysc_fields = &omap_hwmod_sysc_type2,
383};
384
385static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
386 .name = "adc_tsc",
387 .sysc = &am33xx_adc_tsc_sysc,
388};
389
390static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
391 { .irq = 16 + OMAP_INTC_START, },
392 { .irq = -1 },
393};
394
395static struct omap_hwmod am33xx_adc_tsc_hwmod = {
396 .name = "adc_tsc",
397 .class = &am33xx_adc_tsc_hwmod_class,
398 .clkdm_name = "l4_wkup_clkdm",
399 .mpu_irqs = am33xx_adc_tsc_irqs,
400 .main_clk = "adc_tsc_fck",
401 .prcm = {
402 .omap4 = {
403 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
404 .modulemode = MODULEMODE_SWCTRL,
405 },
406 },
407};
408
409/*
410 * Modules omap_hwmod structures
411 *
412 * The following IPs are excluded for the moment because:
413 * - They do not need an explicit SW control using omap_hwmod API.
414 * - They still need to be validated with the driver
415 * properly adapted to omap_hwmod / omap_device
416 *
417 * - cEFUSE (doesn't fall under any ocp_if)
418 * - clkdiv32k
419 * - debugss
a2cfc509 420 * - ocp watch point
a2cfc509
VH		 421 */
422#if 0
423/*
424 * 'cefuse' class
425 */
426static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
427 .name = "cefuse",
428};
429
430static struct omap_hwmod am33xx_cefuse_hwmod = {
431 .name = "cefuse",
432 .class = &am33xx_cefuse_hwmod_class,
433 .clkdm_name = "l4_cefuse_clkdm",
434 .main_clk = "cefuse_fck",
435 .prcm = {
436 .omap4 = {
437 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
438 .modulemode = MODULEMODE_SWCTRL,
439 },
440 },
441};
442
443/*
444 * 'clkdiv32k' class
445 */
446static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
447 .name = "clkdiv32k",
448};
449
450static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
451 .name = "clkdiv32k",
452 .class = &am33xx_clkdiv32k_hwmod_class,
453 .clkdm_name = "clk_24mhz_clkdm",
454 .main_clk = "clkdiv32k_ick",
455 .prcm = {
456 .omap4 = {
457 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
458 .modulemode = MODULEMODE_SWCTRL,
459 },
460 },
461};
462
463/*
464 * 'debugss' class
465 * debug sub system
466 */
467static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
468 .name = "debugss",
469};
470
471static struct omap_hwmod am33xx_debugss_hwmod = {
472 .name = "debugss",
473 .class = &am33xx_debugss_hwmod_class,
474 .clkdm_name = "l3_aon_clkdm",
475 .main_clk = "debugss_ick",
476 .prcm = {
477 .omap4 = {
478 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
479 .modulemode = MODULEMODE_SWCTRL,
480 },
481 },
482};
483
a2cfc509
VH		 484/* ocpwp */
485static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
486 .name = "ocpwp",
487};
488
489static struct omap_hwmod am33xx_ocpwp_hwmod = {
490 .name = "ocpwp",
491 .class = &am33xx_ocpwp_hwmod_class,
492 .clkdm_name = "l4ls_clkdm",
493 .main_clk = "l4ls_gclk",
494 .prcm = {
495 .omap4 = {
496 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
497 .modulemode = MODULEMODE_SWCTRL,
498 },
499 },
500};
1cb804b9 501#endif
a2cfc509
VH		 502
503/*
1cb804b9 504 * 'aes0' class
a2cfc509 505 */
1cb804b9
MG		 506static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
507 .rev_offs = 0x80,
508 .sysc_offs = 0x84,
509 .syss_offs = 0x88,
510 .sysc_flags = SYSS_HAS_RESET_STATUS,
511};
512
513static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
514 .name = "aes0",
515 .sysc = &am33xx_aes0_sysc,
a2cfc509
VH		 516};
517
518static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
1cb804b9 519 { .irq = 103 + OMAP_INTC_START, },
a2cfc509
VH		 520 { .irq = -1 },
521};
522
1cb804b9
MG		 523static struct omap_hwmod_dma_info am33xx_aes0_edma_reqs[] = {
524 { .name = "tx", .dma_req = 6, },
525 { .name = "rx", .dma_req = 5, },
526 { .dma_req = -1 }
527};
528
a2cfc509 529static struct omap_hwmod am33xx_aes0_hwmod = {
1cb804b9
MG		 530 .name = "aes",
531 .class = &am33xx_aes0_hwmod_class,
a2cfc509
VH		 532 .clkdm_name = "l3_clkdm",
533 .mpu_irqs = am33xx_aes0_irqs,
1cb804b9
MG		 534 .sdma_reqs = am33xx_aes0_edma_reqs,
535 .main_clk = "aes0_fck",
a2cfc509
VH		 536 .prcm = {
537 .omap4 = {
538 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
539 .modulemode = MODULEMODE_SWCTRL,
540 },
541 },
542};
543
aec94bf5
MG		 544/* sha0 HIB2 (the 'P' (public) device) */
545static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
546 .rev_offs = 0x100,
547 .sysc_offs = 0x110,
548 .syss_offs = 0x114,
549 .sysc_flags = SYSS_HAS_RESET_STATUS,
550};
a2cfc509 551
a2cfc509
VH		 552static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
553 .name = "sha0",
aec94bf5 554 .sysc = &am33xx_sha0_sysc,
a2cfc509
VH		 555};
556
557static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
aec94bf5 558 { .irq = 109 + OMAP_INTC_START, },
a2cfc509
VH		 559 { .irq = -1 },
560};
561
aec94bf5
MG		 562static struct omap_hwmod_dma_info am33xx_sha0_edma_reqs[] = {
563 { .name = "rx", .dma_req = 36, },
564 { .dma_req = -1 }
565};
566
a2cfc509 567static struct omap_hwmod am33xx_sha0_hwmod = {
aec94bf5 568 .name = "sham",
a2cfc509
VH		 569 .class = &am33xx_sha0_hwmod_class,
570 .clkdm_name = "l3_clkdm",
571 .mpu_irqs = am33xx_sha0_irqs,
aec94bf5 572 .sdma_reqs = am33xx_sha0_edma_reqs,
a2cfc509
VH		 573 .main_clk = "l3_gclk",
574 .prcm = {
575 .omap4 = {
576 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
577 .modulemode = MODULEMODE_SWCTRL,
578 },
579 },
580};
581
ca903b6f
VB		 582/* ocmcram */
583static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
584 .name = "ocmcram",
585};
586
587static struct omap_hwmod am33xx_ocmcram_hwmod = {
588 .name = "ocmcram",
589 .class = &am33xx_ocmcram_hwmod_class,
590 .clkdm_name = "l3_clkdm",
591 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
592 .main_clk = "l3_gclk",
593 .prcm = {
594 .omap4 = {
595 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
596 .modulemode = MODULEMODE_SWCTRL,
597 },
598 },
599};
600
a2cfc509
VH		 601/* 'smartreflex' class */
602static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
603 .name = "smartreflex",
604};
605
606/* smartreflex0 */
607static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
608 { .irq = 120 + OMAP_INTC_START, },
609 { .irq = -1 },
610};
611
612static struct omap_hwmod am33xx_smartreflex0_hwmod = {
613 .name = "smartreflex0",
614 .class = &am33xx_smartreflex_hwmod_class,
615 .clkdm_name = "l4_wkup_clkdm",
616 .mpu_irqs = am33xx_smartreflex0_irqs,
617 .main_clk = "smartreflex0_fck",
618 .prcm = {
619 .omap4 = {
620 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
621 .modulemode = MODULEMODE_SWCTRL,
622 },
623 },
624};
625
626/* smartreflex1 */
627static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
628 { .irq = 121 + OMAP_INTC_START, },
629 { .irq = -1 },
630};
631
632static struct omap_hwmod am33xx_smartreflex1_hwmod = {
633 .name = "smartreflex1",
634 .class = &am33xx_smartreflex_hwmod_class,
635 .clkdm_name = "l4_wkup_clkdm",
636 .mpu_irqs = am33xx_smartreflex1_irqs,
637 .main_clk = "smartreflex1_fck",
638 .prcm = {
639 .omap4 = {
640 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
641 .modulemode = MODULEMODE_SWCTRL,
642 },
643 },
644};
645
646/*
647 * 'control' module class
648 */
649static struct omap_hwmod_class am33xx_control_hwmod_class = {
650 .name = "control",
651};
652
653static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
654 { .irq = 8 + OMAP_INTC_START, },
655 { .irq = -1 },
656};
657
658static struct omap_hwmod am33xx_control_hwmod = {
659 .name = "control",
660 .class = &am33xx_control_hwmod_class,
661 .clkdm_name = "l4_wkup_clkdm",
662 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
663 .mpu_irqs = am33xx_control_irqs,
664 .main_clk = "dpll_core_m4_div2_ck",
665 .prcm = {
666 .omap4 = {
667 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
668 .modulemode = MODULEMODE_SWCTRL,
669 },
670 },
671};
672
673/*
674 * 'cpgmac' class
675 * cpsw/cpgmac sub system
676 */
677static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
678 .rev_offs = 0x0,
679 .sysc_offs = 0x8,
680 .syss_offs = 0x4,
681 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
682 SYSS_HAS_RESET_STATUS),
683 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
684 MSTANDBY_NO),
685 .sysc_fields = &omap_hwmod_sysc_type3,
686};
687
688static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
689 .name = "cpgmac0",
690 .sysc = &am33xx_cpgmac_sysc,
691};
692
693static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
694 { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
695 { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
696 { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
697 { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
698 { .irq = -1 },
699};
700
701static struct omap_hwmod am33xx_cpgmac0_hwmod = {
702 .name = "cpgmac0",
703 .class = &am33xx_cpgmac0_hwmod_class,
704 .clkdm_name = "cpsw_125mhz_clkdm",
70384a6a 705 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
a2cfc509
VH		 706 .mpu_irqs = am33xx_cpgmac0_irqs,
707 .main_clk = "cpsw_125mhz_gclk",
708 .prcm = {
709 .omap4 = {
710 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
711 .modulemode = MODULEMODE_SWCTRL,
712 },
713 },
714};
715
70384a6a
M		 716/*
717 * mdio class
718 */
719static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
720 .name = "davinci_mdio",
721};
722
723static struct omap_hwmod am33xx_mdio_hwmod = {
724 .name = "davinci_mdio",
725 .class = &am33xx_mdio_hwmod_class,
726 .clkdm_name = "cpsw_125mhz_clkdm",
727 .main_clk = "cpsw_125mhz_gclk",
728};
729
a2cfc509
VH		 730/*
731 * dcan class
732 */
733static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
734 .name = "d_can",
735};
736
737/* dcan0 */
738static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
739 { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
740 { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
741 { .irq = -1 },
742};
743
744static struct omap_hwmod am33xx_dcan0_hwmod = {
745 .name = "d_can0",
746 .class = &am33xx_dcan_hwmod_class,
747 .clkdm_name = "l4ls_clkdm",
748 .mpu_irqs = am33xx_dcan0_irqs,
749 .main_clk = "dcan0_fck",
750 .prcm = {
751 .omap4 = {
752 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
753 .modulemode = MODULEMODE_SWCTRL,
754 },
755 },
756};
757
758/* dcan1 */
759static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
760 { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
761 { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
762 { .irq = -1 },
763};
764static struct omap_hwmod am33xx_dcan1_hwmod = {
765 .name = "d_can1",
766 .class = &am33xx_dcan_hwmod_class,
767 .clkdm_name = "l4ls_clkdm",
768 .mpu_irqs = am33xx_dcan1_irqs,
769 .main_clk = "dcan1_fck",
770 .prcm = {
771 .omap4 = {
772 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
773 .modulemode = MODULEMODE_SWCTRL,
774 },
775 },
776};
777
778/* elm */
779static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
780 .rev_offs = 0x0000,
781 .sysc_offs = 0x0010,
782 .syss_offs = 0x0014,
783 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
784 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
785 SYSS_HAS_RESET_STATUS),
786 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
787 .sysc_fields = &omap_hwmod_sysc_type1,
788};
789
790static struct omap_hwmod_class am33xx_elm_hwmod_class = {
791 .name = "elm",
792 .sysc = &am33xx_elm_sysc,
793};
794
795static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
796 { .irq = 4 + OMAP_INTC_START, },
797 { .irq = -1 },
798};
799
800static struct omap_hwmod am33xx_elm_hwmod = {
801 .name = "elm",
802 .class = &am33xx_elm_hwmod_class,
803 .clkdm_name = "l4ls_clkdm",
804 .mpu_irqs = am33xx_elm_irqs,
805 .main_clk = "l4ls_gclk",
806 .prcm = {
807 .omap4 = {
808 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
809 .modulemode = MODULEMODE_SWCTRL,
810 },
811 },
812};
813
9652d19a 814/* pwmss */
a2cfc509
VH		 815static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
816 .rev_offs = 0x0,
817 .sysc_offs = 0x4,
818 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
819 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
820 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
821 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
822 .sysc_fields = &omap_hwmod_sysc_type2,
823};
824
825static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
826 .name = "epwmss",
827 .sysc = &am33xx_epwmss_sysc,
828};
829
9652d19a
PA		 830static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
831 .name = "ecap",
a2cfc509
VH		 832};
833
9652d19a
PA		 834static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
835 .name = "eqep",
a2cfc509
VH		 836};
837
9652d19a
PA		 838static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
839 .name = "ehrpwm",
a2cfc509
VH		 840};
841
9652d19a
PA		 842/* epwmss0 */
843static struct omap_hwmod am33xx_epwmss0_hwmod = {
844 .name = "epwmss0",
a2cfc509
VH		 845 .class = &am33xx_epwmss_hwmod_class,
846 .clkdm_name = "l4ls_clkdm",
a2cfc509
VH		 847 .main_clk = "l4ls_gclk",
848 .prcm = {
849 .omap4 = {
9652d19a 850 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
a2cfc509
VH		 851 .modulemode = MODULEMODE_SWCTRL,
852 },
853 },
854};
855
9652d19a
PA		 856/* ecap0 */
857static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
858 { .irq = 31 + OMAP_INTC_START, },
a2cfc509
VH		 859 { .irq = -1 },
860};
861
9652d19a
PA		 862static struct omap_hwmod am33xx_ecap0_hwmod = {
863 .name = "ecap0",
864 .class = &am33xx_ecap_hwmod_class,
a2cfc509 865 .clkdm_name = "l4ls_clkdm",
9652d19a 866 .mpu_irqs = am33xx_ecap0_irqs,
a2cfc509 867 .main_clk = "l4ls_gclk",
a2cfc509
VH		 868};
869
bee76659
PA		 870/* eqep0 */
871static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
872 { .irq = 79 + OMAP_INTC_START, },
873 { .irq = -1 },
874};
875
876static struct omap_hwmod am33xx_eqep0_hwmod = {
877 .name = "eqep0",
9652d19a 878 .class = &am33xx_eqep_hwmod_class,
bee76659
PA		 879 .clkdm_name = "l4ls_clkdm",
880 .mpu_irqs = am33xx_eqep0_irqs,
881 .main_clk = "l4ls_gclk",
bee76659
PA		 882};
883
9652d19a
PA		 884/* ehrpwm0 */
885static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
886 { .name = "int", .irq = 86 + OMAP_INTC_START, },
887 { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
bee76659
PA		 888 { .irq = -1 },
889};
890
9652d19a
PA		 891static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
892 .name = "ehrpwm0",
893 .class = &am33xx_ehrpwm_hwmod_class,
894 .clkdm_name = "l4ls_clkdm",
895 .mpu_irqs = am33xx_ehrpwm0_irqs,
896 .main_clk = "l4ls_gclk",
897};
898
899/* epwmss1 */
900static struct omap_hwmod am33xx_epwmss1_hwmod = {
901 .name = "epwmss1",
bee76659
PA		 902 .class = &am33xx_epwmss_hwmod_class,
903 .clkdm_name = "l4ls_clkdm",
bee76659
PA		 904 .main_clk = "l4ls_gclk",
905 .prcm = {
906 .omap4 = {
907 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
908 .modulemode = MODULEMODE_SWCTRL,
909 },
910 },
911};
912
9652d19a
PA		 913/* ecap1 */
914static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
915 { .irq = 47 + OMAP_INTC_START, },
bee76659
PA		 916 { .irq = -1 },
917};
918
9652d19a
PA		 919static struct omap_hwmod am33xx_ecap1_hwmod = {
920 .name = "ecap1",
921 .class = &am33xx_ecap_hwmod_class,
bee76659 922 .clkdm_name = "l4ls_clkdm",
9652d19a 923 .mpu_irqs = am33xx_ecap1_irqs,
bee76659 924 .main_clk = "l4ls_gclk",
bee76659
PA		 925};
926
9652d19a
PA		 927/* eqep1 */
928static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
929 { .irq = 88 + OMAP_INTC_START, },
a2cfc509
VH		 930 { .irq = -1 },
931};
932
9652d19a
PA		 933static struct omap_hwmod am33xx_eqep1_hwmod = {
934 .name = "eqep1",
935 .class = &am33xx_eqep_hwmod_class,
a2cfc509 936 .clkdm_name = "l4ls_clkdm",
9652d19a 937 .mpu_irqs = am33xx_eqep1_irqs,
a2cfc509 938 .main_clk = "l4ls_gclk",
a2cfc509
VH		 939};
940
9652d19a
PA		 941/* ehrpwm1 */
942static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
943 { .name = "int", .irq = 87 + OMAP_INTC_START, },
944 { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
a2cfc509
VH		 945 { .irq = -1 },
946};
947
9652d19a
PA		 948static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
949 .name = "ehrpwm1",
950 .class = &am33xx_ehrpwm_hwmod_class,
951 .clkdm_name = "l4ls_clkdm",
952 .mpu_irqs = am33xx_ehrpwm1_irqs,
953 .main_clk = "l4ls_gclk",
954};
955
956/* epwmss2 */
957static struct omap_hwmod am33xx_epwmss2_hwmod = {
958 .name = "epwmss2",
a2cfc509
VH		 959 .class = &am33xx_epwmss_hwmod_class,
960 .clkdm_name = "l4ls_clkdm",
a2cfc509
VH		 961 .main_clk = "l4ls_gclk",
962 .prcm = {
963 .omap4 = {
9652d19a 964 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
a2cfc509
VH		 965 .modulemode = MODULEMODE_SWCTRL,
966 },
967 },
968};
969
970/* ecap2 */
971static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
972 { .irq = 61 + OMAP_INTC_START, },
973 { .irq = -1 },
974};
975
976static struct omap_hwmod am33xx_ecap2_hwmod = {
977 .name = "ecap2",
9652d19a
PA		 978 .class = &am33xx_ecap_hwmod_class,
979 .clkdm_name = "l4ls_clkdm",
a2cfc509 980 .mpu_irqs = am33xx_ecap2_irqs,
9652d19a
PA		 981 .main_clk = "l4ls_gclk",
982};
983
984/* eqep2 */
985static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
986 { .irq = 89 + OMAP_INTC_START, },
987 { .irq = -1 },
988};
989
990static struct omap_hwmod am33xx_eqep2_hwmod = {
991 .name = "eqep2",
992 .class = &am33xx_eqep_hwmod_class,
a2cfc509 993 .clkdm_name = "l4ls_clkdm",
9652d19a
PA		 994 .mpu_irqs = am33xx_eqep2_irqs,
995 .main_clk = "l4ls_gclk",
996};
997
998/* ehrpwm2 */
999static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
1000 { .name = "int", .irq = 39 + OMAP_INTC_START, },
1001 { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
1002 { .irq = -1 },
1003};
1004
1005static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
1006 .name = "ehrpwm2",
1007 .class = &am33xx_ehrpwm_hwmod_class,
1008 .clkdm_name = "l4ls_clkdm",
1009 .mpu_irqs = am33xx_ehrpwm2_irqs,
a2cfc509 1010 .main_clk = "l4ls_gclk",
a2cfc509
VH		 1011};
1012
1013/*
1014 * 'gpio' class: for gpio 0,1,2,3
1015 */
1016static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
1017 .rev_offs = 0x0000,
1018 .sysc_offs = 0x0010,
1019 .syss_offs = 0x0114,
1020 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1021 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1022 SYSS_HAS_RESET_STATUS),
1023 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1024 SIDLE_SMART_WKUP),
1025 .sysc_fields = &omap_hwmod_sysc_type1,
1026};
1027
1028static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
1029 .name = "gpio",
1030 .sysc = &am33xx_gpio_sysc,
1031 .rev = 2,
1032};
1033
1034static struct omap_gpio_dev_attr gpio_dev_attr = {
1035 .bank_width = 32,
1036 .dbck_flag = true,
1037};
1038
1039/* gpio0 */
1040static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
1041 { .role = "dbclk", .clk = "gpio0_dbclk" },
1042};
1043
1044static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
1045 { .irq = 96 + OMAP_INTC_START, },
1046 { .irq = -1 },
1047};
1048
1049static struct omap_hwmod am33xx_gpio0_hwmod = {
1050 .name = "gpio1",
1051 .class = &am33xx_gpio_hwmod_class,
1052 .clkdm_name = "l4_wkup_clkdm",
1053 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1054 .mpu_irqs = am33xx_gpio0_irqs,
1055 .main_clk = "dpll_core_m4_div2_ck",
1056 .prcm = {
1057 .omap4 = {
1058 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
1059 .modulemode = MODULEMODE_SWCTRL,
1060 },
1061 },
1062 .opt_clks = gpio0_opt_clks,
1063 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
1064 .dev_attr = &gpio_dev_attr,
1065};
1066
1067/* gpio1 */
1068static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
1069 { .irq = 98 + OMAP_INTC_START, },
1070 { .irq = -1 },
1071};
1072
1073static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1074 { .role = "dbclk", .clk = "gpio1_dbclk" },
1075};
1076
1077static struct omap_hwmod am33xx_gpio1_hwmod = {
1078 .name = "gpio2",
1079 .class = &am33xx_gpio_hwmod_class,
1080 .clkdm_name = "l4ls_clkdm",
1081 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1082 .mpu_irqs = am33xx_gpio1_irqs,
1083 .main_clk = "l4ls_gclk",
1084 .prcm = {
1085 .omap4 = {
1086 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
1087 .modulemode = MODULEMODE_SWCTRL,
1088 },
1089 },
1090 .opt_clks = gpio1_opt_clks,
1091 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1092 .dev_attr = &gpio_dev_attr,
1093};
1094
1095/* gpio2 */
1096static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
1097 { .irq = 32 + OMAP_INTC_START, },
1098 { .irq = -1 },
1099};
1100
1101static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1102 { .role = "dbclk", .clk = "gpio2_dbclk" },
1103};
1104
1105static struct omap_hwmod am33xx_gpio2_hwmod = {
1106 .name = "gpio3",
1107 .class = &am33xx_gpio_hwmod_class,
1108 .clkdm_name = "l4ls_clkdm",
1109 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1110 .mpu_irqs = am33xx_gpio2_irqs,
1111 .main_clk = "l4ls_gclk",
1112 .prcm = {
1113 .omap4 = {
1114 .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
1115 .modulemode = MODULEMODE_SWCTRL,
1116 },
1117 },
1118 .opt_clks = gpio2_opt_clks,
1119 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1120 .dev_attr = &gpio_dev_attr,
1121};
1122
1123/* gpio3 */
1124static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
1125 { .irq = 62 + OMAP_INTC_START, },
1126 { .irq = -1 },
1127};
1128
1129static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1130 { .role = "dbclk", .clk = "gpio3_dbclk" },
1131};
1132
1133static struct omap_hwmod am33xx_gpio3_hwmod = {
1134 .name = "gpio4",
1135 .class = &am33xx_gpio_hwmod_class,
1136 .clkdm_name = "l4ls_clkdm",
1137 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1138 .mpu_irqs = am33xx_gpio3_irqs,
1139 .main_clk = "l4ls_gclk",
1140 .prcm = {
1141 .omap4 = {
1142 .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
1143 .modulemode = MODULEMODE_SWCTRL,
1144 },
1145 },
1146 .opt_clks = gpio3_opt_clks,
1147 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1148 .dev_attr = &gpio_dev_attr,
1149};
1150
1151/* gpmc */
1152static struct omap_hwmod_class_sysconfig gpmc_sysc = {
1153 .rev_offs = 0x0,
1154 .sysc_offs = 0x10,
1155 .syss_offs = 0x14,
1156 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1157 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1158 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1159 .sysc_fields = &omap_hwmod_sysc_type1,
1160};
1161
1162static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
1163 .name = "gpmc",
1164 .sysc = &gpmc_sysc,
1165};
1166
1167static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
1168 { .irq = 100 + OMAP_INTC_START, },
1169 { .irq = -1 },
1170};
1171
1172static struct omap_hwmod am33xx_gpmc_hwmod = {
1173 .name = "gpmc",
1174 .class = &am33xx_gpmc_hwmod_class,
1175 .clkdm_name = "l3s_clkdm",
1176 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1177 .mpu_irqs = am33xx_gpmc_irqs,
1178 .main_clk = "l3s_gclk",
1179 .prcm = {
1180 .omap4 = {
1181 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
1182 .modulemode = MODULEMODE_SWCTRL,
1183 },
1184 },
1185};
1186
1187/* 'i2c' class */
1188static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
1189 .sysc_offs = 0x0010,
1190 .syss_offs = 0x0090,
1191 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1192 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1193 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1194 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1195 SIDLE_SMART_WKUP),
1196 .sysc_fields = &omap_hwmod_sysc_type1,
1197};
1198
1199static struct omap_hwmod_class i2c_class = {
1200 .name = "i2c",
1201 .sysc = &am33xx_i2c_sysc,
1202 .rev = OMAP_I2C_IP_VERSION_2,
1203 .reset = &omap_i2c_reset,
1204};
1205
1206static struct omap_i2c_dev_attr i2c_dev_attr = {
972deb4f 1207 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
a2cfc509
VH		 1208};
1209
1210/* i2c1 */
1211static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1212 { .irq = 70 + OMAP_INTC_START, },
1213 { .irq = -1 },
1214};
1215
1216static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
1217 { .name = "tx", .dma_req = 0, },
1218 { .name = "rx", .dma_req = 0, },
1219 { .dma_req = -1 }
1220};
1221
1222static struct omap_hwmod am33xx_i2c1_hwmod = {
1223 .name = "i2c1",
1224 .class = &i2c_class,
1225 .clkdm_name = "l4_wkup_clkdm",
1226 .mpu_irqs = i2c1_mpu_irqs,
1227 .sdma_reqs = i2c1_edma_reqs,
1228 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1229 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1230 .prcm = {
1231 .omap4 = {
1232 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
1233 .modulemode = MODULEMODE_SWCTRL,
1234 },
1235 },
1236 .dev_attr = &i2c_dev_attr,
1237};
1238
1239/* i2c1 */
1240static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1241 { .irq = 71 + OMAP_INTC_START, },
1242 { .irq = -1 },
1243};
1244
1245static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
1246 { .name = "tx", .dma_req = 0, },
1247 { .name = "rx", .dma_req = 0, },
1248 { .dma_req = -1 }
1249};
1250
1251static struct omap_hwmod am33xx_i2c2_hwmod = {
1252 .name = "i2c2",
1253 .class = &i2c_class,
1254 .clkdm_name = "l4ls_clkdm",
1255 .mpu_irqs = i2c2_mpu_irqs,
1256 .sdma_reqs = i2c2_edma_reqs,
1257 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1258 .main_clk = "dpll_per_m2_div4_ck",
1259 .prcm = {
1260 .omap4 = {
1261 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
1262 .modulemode = MODULEMODE_SWCTRL,
1263 },
1264 },
1265 .dev_attr = &i2c_dev_attr,
1266};
1267
1268/* i2c3 */
1269static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
1270 { .name = "tx", .dma_req = 0, },
1271 { .name = "rx", .dma_req = 0, },
1272 { .dma_req = -1 }
1273};
1274
1275static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1276 { .irq = 30 + OMAP_INTC_START, },
1277 { .irq = -1 },
1278};
1279
1280static struct omap_hwmod am33xx_i2c3_hwmod = {
1281 .name = "i2c3",
1282 .class = &i2c_class,
1283 .clkdm_name = "l4ls_clkdm",
1284 .mpu_irqs = i2c3_mpu_irqs,
1285 .sdma_reqs = i2c3_edma_reqs,
1286 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1287 .main_clk = "dpll_per_m2_div4_ck",
1288 .prcm = {
1289 .omap4 = {
1290 .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
1291 .modulemode = MODULEMODE_SWCTRL,
1292 },
1293 },
1294 .dev_attr = &i2c_dev_attr,
1295};
1296
1297
1298/* lcdc */
1299static struct omap_hwmod_class_sysconfig lcdc_sysc = {
1300 .rev_offs = 0x0,
1301 .sysc_offs = 0x54,
1302 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
1303 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1304 .sysc_fields = &omap_hwmod_sysc_type2,
1305};
1306
1307static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1308 .name = "lcdc",
1309 .sysc = &lcdc_sysc,
1310};
1311
1312static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1313 { .irq = 36 + OMAP_INTC_START, },
1314 { .irq = -1 },
1315};
1316
1317static struct omap_hwmod am33xx_lcdc_hwmod = {
1318 .name = "lcdc",
1319 .class = &am33xx_lcdc_hwmod_class,
1320 .clkdm_name = "lcdc_clkdm",
1321 .mpu_irqs = am33xx_lcdc_irqs,
1322 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1323 .main_clk = "lcd_gclk",
1324 .prcm = {
1325 .omap4 = {
1326 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1327 .modulemode = MODULEMODE_SWCTRL,
1328 },
1329 },
1330};
1331
1332/*
1333 * 'mailbox' class
1334 * mailbox module allowing communication between the on-chip processors using a
1335 * queued mailbox-interrupt mechanism.
1336 */
1337static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1338 .rev_offs = 0x0000,
1339 .sysc_offs = 0x0010,
1340 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1341 SYSC_HAS_SOFTRESET),
1342 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1343 .sysc_fields = &omap_hwmod_sysc_type2,
1344};
1345
1346static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1347 .name = "mailbox",
1348 .sysc = &am33xx_mailbox_sysc,
1349};
1350
1351static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1352 { .irq = 77 + OMAP_INTC_START, },
1353 { .irq = -1 },
1354};
1355
1356static struct omap_hwmod am33xx_mailbox_hwmod = {
1357 .name = "mailbox",
1358 .class = &am33xx_mailbox_hwmod_class,
1359 .clkdm_name = "l4ls_clkdm",
1360 .mpu_irqs = am33xx_mailbox_irqs,
1361 .main_clk = "l4ls_gclk",
1362 .prcm = {
1363 .omap4 = {
1364 .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1365 .modulemode = MODULEMODE_SWCTRL,
1366 },
1367 },
1368};
1369
1370/*
1371 * 'mcasp' class
1372 */
1373static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
1374 .rev_offs = 0x0,
1375 .sysc_offs = 0x4,
1376 .sysc_flags = SYSC_HAS_SIDLEMODE,
1377 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1378 .sysc_fields = &omap_hwmod_sysc_type3,
1379};
1380
1381static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1382 .name = "mcasp",
1383 .sysc = &am33xx_mcasp_sysc,
1384};
1385
1386/* mcasp0 */
1387static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1388 { .name = "ax", .irq = 80 + OMAP_INTC_START, },
1389 { .name = "ar", .irq = 81 + OMAP_INTC_START, },
1390 { .irq = -1 },
1391};
1392
1393static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
1394 { .name = "tx", .dma_req = 8, },
1395 { .name = "rx", .dma_req = 9, },
1396 { .dma_req = -1 }
1397};
1398
1399static struct omap_hwmod am33xx_mcasp0_hwmod = {
1400 .name = "mcasp0",
1401 .class = &am33xx_mcasp_hwmod_class,
1402 .clkdm_name = "l3s_clkdm",
1403 .mpu_irqs = am33xx_mcasp0_irqs,
1404 .sdma_reqs = am33xx_mcasp0_edma_reqs,
1405 .main_clk = "mcasp0_fck",
1406 .prcm = {
1407 .omap4 = {
1408 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1409 .modulemode = MODULEMODE_SWCTRL,
1410 },
1411 },
1412};
1413
1414/* mcasp1 */
1415static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
1416 { .name = "ax", .irq = 82 + OMAP_INTC_START, },
1417 { .name = "ar", .irq = 83 + OMAP_INTC_START, },
1418 { .irq = -1 },
1419};
1420
1421static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
1422 { .name = "tx", .dma_req = 10, },
1423 { .name = "rx", .dma_req = 11, },
1424 { .dma_req = -1 }
1425};
1426
1427static struct omap_hwmod am33xx_mcasp1_hwmod = {
1428 .name = "mcasp1",
1429 .class = &am33xx_mcasp_hwmod_class,
1430 .clkdm_name = "l3s_clkdm",
1431 .mpu_irqs = am33xx_mcasp1_irqs,
1432 .sdma_reqs = am33xx_mcasp1_edma_reqs,
1433 .main_clk = "mcasp1_fck",
1434 .prcm = {
1435 .omap4 = {
1436 .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
1437 .modulemode = MODULEMODE_SWCTRL,
1438 },
1439 },
1440};
1441
1442/* 'mmc' class */
1443static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1444 .rev_offs = 0x1fc,
1445 .sysc_offs = 0x10,
1446 .syss_offs = 0x14,
1447 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1448 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1449 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1450 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1451 .sysc_fields = &omap_hwmod_sysc_type1,
1452};
1453
1454static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1455 .name = "mmc",
1456 .sysc = &am33xx_mmc_sysc,
1457};
1458
1459/* mmc0 */
1460static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1461 { .irq = 64 + OMAP_INTC_START, },
1462 { .irq = -1 },
1463};
1464
1465static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1466 { .name = "tx", .dma_req = 24, },
1467 { .name = "rx", .dma_req = 25, },
1468 { .dma_req = -1 }
1469};
1470
1471static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1472 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1473};
1474
1475static struct omap_hwmod am33xx_mmc0_hwmod = {
1476 .name = "mmc1",
1477 .class = &am33xx_mmc_hwmod_class,
1478 .clkdm_name = "l4ls_clkdm",
1479 .mpu_irqs = am33xx_mmc0_irqs,
1480 .sdma_reqs = am33xx_mmc0_edma_reqs,
1481 .main_clk = "mmc_clk",
1482 .prcm = {
1483 .omap4 = {
1484 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1485 .modulemode = MODULEMODE_SWCTRL,
1486 },
1487 },
1488 .dev_attr = &am33xx_mmc0_dev_attr,
1489};
1490
1491/* mmc1 */
1492static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1493 { .irq = 28 + OMAP_INTC_START, },
1494 { .irq = -1 },
1495};
1496
1497static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1498 { .name = "tx", .dma_req = 2, },
1499 { .name = "rx", .dma_req = 3, },
1500 { .dma_req = -1 }
1501};
1502
1503static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1504 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1505};
1506
1507static struct omap_hwmod am33xx_mmc1_hwmod = {
1508 .name = "mmc2",
1509 .class = &am33xx_mmc_hwmod_class,
1510 .clkdm_name = "l4ls_clkdm",
1511 .mpu_irqs = am33xx_mmc1_irqs,
1512 .sdma_reqs = am33xx_mmc1_edma_reqs,
1513 .main_clk = "mmc_clk",
1514 .prcm = {
1515 .omap4 = {
1516 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1517 .modulemode = MODULEMODE_SWCTRL,
1518 },
1519 },
1520 .dev_attr = &am33xx_mmc1_dev_attr,
1521};
1522
1523/* mmc2 */
1524static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1525 { .irq = 29 + OMAP_INTC_START, },
1526 { .irq = -1 },
1527};
1528
1529static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1530 { .name = "tx", .dma_req = 64, },
1531 { .name = "rx", .dma_req = 65, },
1532 { .dma_req = -1 }
1533};
1534
1535static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1536 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1537};
1538static struct omap_hwmod am33xx_mmc2_hwmod = {
1539 .name = "mmc3",
1540 .class = &am33xx_mmc_hwmod_class,
1541 .clkdm_name = "l3s_clkdm",
1542 .mpu_irqs = am33xx_mmc2_irqs,
1543 .sdma_reqs = am33xx_mmc2_edma_reqs,
1544 .main_clk = "mmc_clk",
1545 .prcm = {
1546 .omap4 = {
1547 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1548 .modulemode = MODULEMODE_SWCTRL,
1549 },
1550 },
1551 .dev_attr = &am33xx_mmc2_dev_attr,
1552};
1553
1554/*
1555 * 'rtc' class
1556 * rtc subsystem
1557 */
1558static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
1559 .rev_offs = 0x0074,
1560 .sysc_offs = 0x0078,
1561 .sysc_flags = SYSC_HAS_SIDLEMODE,
1562 .idlemodes = (SIDLE_FORCE | SIDLE_NO |
1563 SIDLE_SMART | SIDLE_SMART_WKUP),
1564 .sysc_fields = &omap_hwmod_sysc_type3,
1565};
1566
1567static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1568 .name = "rtc",
1569 .sysc = &am33xx_rtc_sysc,
1570};
1571
1572static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1573 { .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
1574 { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
1575 { .irq = -1 },
1576};
1577
1578static struct omap_hwmod am33xx_rtc_hwmod = {
1579 .name = "rtc",
1580 .class = &am33xx_rtc_hwmod_class,
1581 .clkdm_name = "l4_rtc_clkdm",
1582 .mpu_irqs = am33xx_rtc_irqs,
1583 .main_clk = "clk_32768_ck",
1584 .prcm = {
1585 .omap4 = {
1586 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1587 .modulemode = MODULEMODE_SWCTRL,
1588 },
1589 },
1590};
1591
1592/* 'spi' class */
1593static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1594 .rev_offs = 0x0000,
1595 .sysc_offs = 0x0110,
1596 .syss_offs = 0x0114,
1597 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1598 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1599 SYSS_HAS_RESET_STATUS),
1600 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1601 .sysc_fields = &omap_hwmod_sysc_type1,
1602};
1603
1604static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1605 .name = "mcspi",
1606 .sysc = &am33xx_mcspi_sysc,
1607 .rev = OMAP4_MCSPI_REV,
1608};
1609
1610/* spi0 */
1611static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1612 { .irq = 65 + OMAP_INTC_START, },
1613 { .irq = -1 },
1614};
1615
1616static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
1617 { .name = "rx0", .dma_req = 17 },
1618 { .name = "tx0", .dma_req = 16 },
1619 { .name = "rx1", .dma_req = 19 },
1620 { .name = "tx1", .dma_req = 18 },
1621 { .dma_req = -1 }
1622};
1623
1624static struct omap2_mcspi_dev_attr mcspi_attrib = {
1625 .num_chipselect = 2,
1626};
1627static struct omap_hwmod am33xx_spi0_hwmod = {
1628 .name = "spi0",
1629 .class = &am33xx_spi_hwmod_class,
1630 .clkdm_name = "l4ls_clkdm",
1631 .mpu_irqs = am33xx_spi0_irqs,
1632 .sdma_reqs = am33xx_mcspi0_edma_reqs,
1633 .main_clk = "dpll_per_m2_div4_ck",
1634 .prcm = {
1635 .omap4 = {
1636 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1637 .modulemode = MODULEMODE_SWCTRL,
1638 },
1639 },
1640 .dev_attr = &mcspi_attrib,
1641};
1642
1643/* spi1 */
1644static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1645 { .irq = 125 + OMAP_INTC_START, },
1646 { .irq = -1 },
1647};
1648
1649static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
1650 { .name = "rx0", .dma_req = 43 },
1651 { .name = "tx0", .dma_req = 42 },
1652 { .name = "rx1", .dma_req = 45 },
1653 { .name = "tx1", .dma_req = 44 },
1654 { .dma_req = -1 }
1655};
1656
1657static struct omap_hwmod am33xx_spi1_hwmod = {
1658 .name = "spi1",
1659 .class = &am33xx_spi_hwmod_class,
1660 .clkdm_name = "l4ls_clkdm",
1661 .mpu_irqs = am33xx_spi1_irqs,
1662 .sdma_reqs = am33xx_mcspi1_edma_reqs,
1663 .main_clk = "dpll_per_m2_div4_ck",
1664 .prcm = {
1665 .omap4 = {
1666 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1667 .modulemode = MODULEMODE_SWCTRL,
1668 },
1669 },
1670 .dev_attr = &mcspi_attrib,
1671};
1672
1673/*
1674 * 'spinlock' class
1675 * spinlock provides hardware assistance for synchronizing the
1676 * processes running on multiple processors
1677 */
1678static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1679 .name = "spinlock",
1680};
1681
1682static struct omap_hwmod am33xx_spinlock_hwmod = {
1683 .name = "spinlock",
1684 .class = &am33xx_spinlock_hwmod_class,
1685 .clkdm_name = "l4ls_clkdm",
1686 .main_clk = "l4ls_gclk",
1687 .prcm = {
1688 .omap4 = {
1689 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1690 .modulemode = MODULEMODE_SWCTRL,
1691 },
1692 },
1693};
1694
1695/* 'timer 2-7' class */
1696static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1697 .rev_offs = 0x0000,
1698 .sysc_offs = 0x0010,
1699 .syss_offs = 0x0014,
1700 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1701 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1702 SIDLE_SMART_WKUP),
1703 .sysc_fields = &omap_hwmod_sysc_type2,
1704};
1705
1706static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1707 .name = "timer",
1708 .sysc = &am33xx_timer_sysc,
1709};
1710
1711/* timer1 1ms */
1712static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1713 .rev_offs = 0x0000,
1714 .sysc_offs = 0x0010,
1715 .syss_offs = 0x0014,
1716 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1717 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1718 SYSS_HAS_RESET_STATUS),
1719 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1720 .sysc_fields = &omap_hwmod_sysc_type1,
1721};
1722
1723static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1724 .name = "timer",
1725 .sysc = &am33xx_timer1ms_sysc,
1726};
1727
1728static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
1729 { .irq = 67 + OMAP_INTC_START, },
1730 { .irq = -1 },
1731};
1732
1733static struct omap_hwmod am33xx_timer1_hwmod = {
1734 .name = "timer1",
1735 .class = &am33xx_timer1ms_hwmod_class,
1736 .clkdm_name = "l4_wkup_clkdm",
1737 .mpu_irqs = am33xx_timer1_irqs,
1738 .main_clk = "timer1_fck",
1739 .prcm = {
1740 .omap4 = {
1741 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1742 .modulemode = MODULEMODE_SWCTRL,
1743 },
1744 },
1745};
1746
1747static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
1748 { .irq = 68 + OMAP_INTC_START, },
1749 { .irq = -1 },
1750};
1751
1752static struct omap_hwmod am33xx_timer2_hwmod = {
1753 .name = "timer2",
1754 .class = &am33xx_timer_hwmod_class,
1755 .clkdm_name = "l4ls_clkdm",
1756 .mpu_irqs = am33xx_timer2_irqs,
1757 .main_clk = "timer2_fck",
1758 .prcm = {
1759 .omap4 = {
1760 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1761 .modulemode = MODULEMODE_SWCTRL,
1762 },
1763 },
1764};
1765
1766static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
1767 { .irq = 69 + OMAP_INTC_START, },
1768 { .irq = -1 },
1769};
1770
1771static struct omap_hwmod am33xx_timer3_hwmod = {
1772 .name = "timer3",
1773 .class = &am33xx_timer_hwmod_class,
1774 .clkdm_name = "l4ls_clkdm",
1775 .mpu_irqs = am33xx_timer3_irqs,
1776 .main_clk = "timer3_fck",
1777 .prcm = {
1778 .omap4 = {
1779 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1780 .modulemode = MODULEMODE_SWCTRL,
1781 },
1782 },
1783};
1784
1785static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
1786 { .irq = 92 + OMAP_INTC_START, },
1787 { .irq = -1 },
1788};
1789
1790static struct omap_hwmod am33xx_timer4_hwmod = {
1791 .name = "timer4",
1792 .class = &am33xx_timer_hwmod_class,
1793 .clkdm_name = "l4ls_clkdm",
1794 .mpu_irqs = am33xx_timer4_irqs,
1795 .main_clk = "timer4_fck",
1796 .prcm = {
1797 .omap4 = {
1798 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1799 .modulemode = MODULEMODE_SWCTRL,
1800 },
1801 },
1802};
1803
1804static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
1805 { .irq = 93 + OMAP_INTC_START, },
1806 { .irq = -1 },
1807};
1808
1809static struct omap_hwmod am33xx_timer5_hwmod = {
1810 .name = "timer5",
1811 .class = &am33xx_timer_hwmod_class,
1812 .clkdm_name = "l4ls_clkdm",
1813 .mpu_irqs = am33xx_timer5_irqs,
1814 .main_clk = "timer5_fck",
1815 .prcm = {
1816 .omap4 = {
1817 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1818 .modulemode = MODULEMODE_SWCTRL,
1819 },
1820 },
1821};
1822
1823static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
1824 { .irq = 94 + OMAP_INTC_START, },
1825 { .irq = -1 },
1826};
1827
1828static struct omap_hwmod am33xx_timer6_hwmod = {
1829 .name = "timer6",
1830 .class = &am33xx_timer_hwmod_class,
1831 .clkdm_name = "l4ls_clkdm",
1832 .mpu_irqs = am33xx_timer6_irqs,
1833 .main_clk = "timer6_fck",
1834 .prcm = {
1835 .omap4 = {
1836 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
1837 .modulemode = MODULEMODE_SWCTRL,
1838 },
1839 },
1840};
1841
1842static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
1843 { .irq = 95 + OMAP_INTC_START, },
1844 { .irq = -1 },
1845};
1846
1847static struct omap_hwmod am33xx_timer7_hwmod = {
1848 .name = "timer7",
1849 .class = &am33xx_timer_hwmod_class,
1850 .clkdm_name = "l4ls_clkdm",
1851 .mpu_irqs = am33xx_timer7_irqs,
1852 .main_clk = "timer7_fck",
1853 .prcm = {
1854 .omap4 = {
1855 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
1856 .modulemode = MODULEMODE_SWCTRL,
1857 },
1858 },
1859};
1860
1861/* tpcc */
1862static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1863 .name = "tpcc",
1864};
1865
1866static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
1867 { .name = "edma0", .irq = 12 + OMAP_INTC_START, },
1868 { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
1869 { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, },
1870 { .irq = -1 },
1871};
1872
1873static struct omap_hwmod am33xx_tpcc_hwmod = {
1874 .name = "tpcc",
1875 .class = &am33xx_tpcc_hwmod_class,
1876 .clkdm_name = "l3_clkdm",
1877 .mpu_irqs = am33xx_tpcc_irqs,
1878 .main_clk = "l3_gclk",
1879 .prcm = {
1880 .omap4 = {
1881 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
1882 .modulemode = MODULEMODE_SWCTRL,
1883 },
1884 },
1885};
1886
1887static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1888 .rev_offs = 0x0,
1889 .sysc_offs = 0x10,
1890 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1891 SYSC_HAS_MIDLEMODE),
1892 .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1893 .sysc_fields = &omap_hwmod_sysc_type2,
1894};
1895
1896/* 'tptc' class */
1897static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1898 .name = "tptc",
1899 .sysc = &am33xx_tptc_sysc,
1900};
1901
1902/* tptc0 */
1903static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
1904 { .irq = 112 + OMAP_INTC_START, },
1905 { .irq = -1 },
1906};
1907
1908static struct omap_hwmod am33xx_tptc0_hwmod = {
1909 .name = "tptc0",
1910 .class = &am33xx_tptc_hwmod_class,
1911 .clkdm_name = "l3_clkdm",
1912 .mpu_irqs = am33xx_tptc0_irqs,
0bfbbded 1913 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
a2cfc509
VH		 1914 .main_clk = "l3_gclk",
1915 .prcm = {
1916 .omap4 = {
1917 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
1918 .modulemode = MODULEMODE_SWCTRL,
1919 },
1920 },
1921};
1922
1923/* tptc1 */
1924static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
1925 { .irq = 113 + OMAP_INTC_START, },
1926 { .irq = -1 },
1927};
1928
1929static struct omap_hwmod am33xx_tptc1_hwmod = {
1930 .name = "tptc1",
1931 .class = &am33xx_tptc_hwmod_class,
1932 .clkdm_name = "l3_clkdm",
1933 .mpu_irqs = am33xx_tptc1_irqs,
1934 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1935 .main_clk = "l3_gclk",
1936 .prcm = {
1937 .omap4 = {
1938 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
1939 .modulemode = MODULEMODE_SWCTRL,
1940 },
1941 },
1942};
1943
1944/* tptc2 */
1945static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
1946 { .irq = 114 + OMAP_INTC_START, },
1947 { .irq = -1 },
1948};
1949
1950static struct omap_hwmod am33xx_tptc2_hwmod = {
1951 .name = "tptc2",
1952 .class = &am33xx_tptc_hwmod_class,
1953 .clkdm_name = "l3_clkdm",
1954 .mpu_irqs = am33xx_tptc2_irqs,
1955 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1956 .main_clk = "l3_gclk",
1957 .prcm = {
1958 .omap4 = {
1959 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
1960 .modulemode = MODULEMODE_SWCTRL,
1961 },
1962 },
1963};
1964
1965/* 'uart' class */
1966static struct omap_hwmod_class_sysconfig uart_sysc = {
1967 .rev_offs = 0x50,
1968 .sysc_offs = 0x54,
1969 .syss_offs = 0x58,
1970 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1971 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1972 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1973 SIDLE_SMART_WKUP),
1974 .sysc_fields = &omap_hwmod_sysc_type1,
1975};
1976
1977static struct omap_hwmod_class uart_class = {
1978 .name = "uart",
1979 .sysc = &uart_sysc,
1980};
1981
1982/* uart1 */
1983static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
1984 { .name = "tx", .dma_req = 26, },
1985 { .name = "rx", .dma_req = 27, },
1986 { .dma_req = -1 }
1987};
1988
1989static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
1990 { .irq = 72 + OMAP_INTC_START, },
1991 { .irq = -1 },
1992};
1993
1994static struct omap_hwmod am33xx_uart1_hwmod = {
1995 .name = "uart1",
1996 .class = &uart_class,
1997 .clkdm_name = "l4_wkup_clkdm",
1998 .mpu_irqs = am33xx_uart1_irqs,
1999 .sdma_reqs = uart1_edma_reqs,
2000 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
2001 .prcm = {
2002 .omap4 = {
2003 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
2004 .modulemode = MODULEMODE_SWCTRL,
2005 },
2006 },
2007};
2008
2009static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
2010 { .irq = 73 + OMAP_INTC_START, },
2011 { .irq = -1 },
2012};
2013
2014static struct omap_hwmod am33xx_uart2_hwmod = {
2015 .name = "uart2",
2016 .class = &uart_class,
2017 .clkdm_name = "l4ls_clkdm",
2018 .mpu_irqs = am33xx_uart2_irqs,
2019 .sdma_reqs = uart1_edma_reqs,
2020 .main_clk = "dpll_per_m2_div4_ck",
2021 .prcm = {
2022 .omap4 = {
2023 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
2024 .modulemode = MODULEMODE_SWCTRL,
2025 },
2026 },
2027};
2028
2029/* uart3 */
2030static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
2031 { .name = "tx", .dma_req = 30, },
2032 { .name = "rx", .dma_req = 31, },
2033 { .dma_req = -1 }
2034};
2035
2036static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2037 { .irq = 74 + OMAP_INTC_START, },
2038 { .irq = -1 },
2039};
2040
2041static struct omap_hwmod am33xx_uart3_hwmod = {
2042 .name = "uart3",
2043 .class = &uart_class,
2044 .clkdm_name = "l4ls_clkdm",
2045 .mpu_irqs = am33xx_uart3_irqs,
2046 .sdma_reqs = uart3_edma_reqs,
2047 .main_clk = "dpll_per_m2_div4_ck",
2048 .prcm = {
2049 .omap4 = {
2050 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
2051 .modulemode = MODULEMODE_SWCTRL,
2052 },
2053 },
2054};
2055
2056static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2057 { .irq = 44 + OMAP_INTC_START, },
2058 { .irq = -1 },
2059};
2060
2061static struct omap_hwmod am33xx_uart4_hwmod = {
2062 .name = "uart4",
2063 .class = &uart_class,
2064 .clkdm_name = "l4ls_clkdm",
2065 .mpu_irqs = am33xx_uart4_irqs,
2066 .sdma_reqs = uart1_edma_reqs,
2067 .main_clk = "dpll_per_m2_div4_ck",
2068 .prcm = {
2069 .omap4 = {
2070 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
2071 .modulemode = MODULEMODE_SWCTRL,
2072 },
2073 },
2074};
2075
2076static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2077 { .irq = 45 + OMAP_INTC_START, },
2078 { .irq = -1 },
2079};
2080
2081static struct omap_hwmod am33xx_uart5_hwmod = {
2082 .name = "uart5",
2083 .class = &uart_class,
2084 .clkdm_name = "l4ls_clkdm",
2085 .mpu_irqs = am33xx_uart5_irqs,
2086 .sdma_reqs = uart1_edma_reqs,
2087 .main_clk = "dpll_per_m2_div4_ck",
2088 .prcm = {
2089 .omap4 = {
2090 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2091 .modulemode = MODULEMODE_SWCTRL,
2092 },
2093 },
2094};
2095
2096static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2097 { .irq = 46 + OMAP_INTC_START, },
2098 { .irq = -1 },
2099};
2100
2101static struct omap_hwmod am33xx_uart6_hwmod = {
2102 .name = "uart6",
2103 .class = &uart_class,
2104 .clkdm_name = "l4ls_clkdm",
2105 .mpu_irqs = am33xx_uart6_irqs,
2106 .sdma_reqs = uart1_edma_reqs,
2107 .main_clk = "dpll_per_m2_div4_ck",
2108 .prcm = {
2109 .omap4 = {
2110 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2111 .modulemode = MODULEMODE_SWCTRL,
2112 },
2113 },
2114};
2115
2116/* 'wd_timer' class */
05cf03b6
VH		 2117static struct omap_hwmod_class_sysconfig wdt_sysc = {
2118 .rev_offs = 0x0,
2119 .sysc_offs = 0x10,
2120 .syss_offs = 0x14,
2121 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2122 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2123 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2124 SIDLE_SMART_WKUP),
2125 .sysc_fields = &omap_hwmod_sysc_type1,
2126};
2127
a2cfc509
VH		 2128static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2129 .name = "wd_timer",
05cf03b6
VH		 2130 .sysc = &wdt_sysc,
2131 .pre_shutdown = &omap2_wd_timer_disable,
a2cfc509
VH		 2132};
2133
2134/*
2135 * XXX: device.c file uses hardcoded name for watchdog timer
2136 * driver "wd_timer2, so we are also using same name as of now...
2137 */
2138static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2139 .name = "wd_timer2",
2140 .class = &am33xx_wd_timer_hwmod_class,
2141 .clkdm_name = "l4_wkup_clkdm",
05cf03b6 2142 .flags = HWMOD_SWSUP_SIDLE,
a2cfc509
VH		 2143 .main_clk = "wdt1_fck",
2144 .prcm = {
2145 .omap4 = {
2146 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2147 .modulemode = MODULEMODE_SWCTRL,
2148 },
2149 },
2150};
2151
2152/*
2153 * 'usb_otg' class
2154 * high-speed on-the-go universal serial bus (usb_otg) controller
2155 */
2156static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2157 .rev_offs = 0x0,
2158 .sysc_offs = 0x10,
2159 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
2160 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2161 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2162 .sysc_fields = &omap_hwmod_sysc_type2,
2163};
2164
2165static struct omap_hwmod_class am33xx_usbotg_class = {
2166 .name = "usbotg",
2167 .sysc = &am33xx_usbhsotg_sysc,
2168};
2169
2170static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2171 { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
2172 { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
2173 { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
6adba67e 2174 { .irq = -1, },
a2cfc509
VH		 2175};
2176
2177static struct omap_hwmod am33xx_usbss_hwmod = {
2178 .name = "usb_otg_hs",
2179 .class = &am33xx_usbotg_class,
2180 .clkdm_name = "l3s_clkdm",
2181 .mpu_irqs = am33xx_usbss_mpu_irqs,
2182 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2183 .main_clk = "usbotg_fck",
2184 .prcm = {
2185 .omap4 = {
2186 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2187 .modulemode = MODULEMODE_SWCTRL,
2188 },
2189 },
2190};
2191
2192
2193/*
2194 * Interfaces
2195 */
2196
2197/* l4 fw -> emif fw */
2198static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
2199 .master = &am33xx_l4_fw_hwmod,
2200 .slave = &am33xx_emif_fw_hwmod,
2201 .clk = "l4fw_gclk",
2202 .user = OCP_USER_MPU,
2203};
2204
2205static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
2206 {
2207 .pa_start = 0x4c000000,
2208 .pa_end = 0x4c000fff,
2209 .flags = ADDR_TYPE_RT
2210 },
2211 { }
2212};
2213/* l3 main -> emif */
2214static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
2215 .master = &am33xx_l3_main_hwmod,
2216 .slave = &am33xx_emif_hwmod,
2217 .clk = "dpll_core_m4_ck",
2218 .addr = am33xx_emif_addrs,
2219 .user = OCP_USER_MPU | OCP_USER_SDMA,
2220};
2221
2222/* mpu -> l3 main */
2223static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
2224 .master = &am33xx_mpu_hwmod,
2225 .slave = &am33xx_l3_main_hwmod,
2226 .clk = "dpll_mpu_m2_ck",
2227 .user = OCP_USER_MPU,
2228};
2229
2230/* l3 main -> l4 hs */
2231static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
2232 .master = &am33xx_l3_main_hwmod,
2233 .slave = &am33xx_l4_hs_hwmod,
2234 .clk = "l3s_gclk",
2235 .user = OCP_USER_MPU | OCP_USER_SDMA,
2236};
2237
2238/* l3 main -> l3 s */
2239static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
2240 .master = &am33xx_l3_main_hwmod,
2241 .slave = &am33xx_l3_s_hwmod,
2242 .clk = "l3s_gclk",
2243 .user = OCP_USER_MPU | OCP_USER_SDMA,
2244};
2245
2246/* l3 s -> l4 per/ls */
2247static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
2248 .master = &am33xx_l3_s_hwmod,
2249 .slave = &am33xx_l4_ls_hwmod,
2250 .clk = "l3s_gclk",
2251 .user = OCP_USER_MPU | OCP_USER_SDMA,
2252};
2253
2254/* l3 s -> l4 wkup */
2255static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
2256 .master = &am33xx_l3_s_hwmod,
2257 .slave = &am33xx_l4_wkup_hwmod,
2258 .clk = "l3s_gclk",
2259 .user = OCP_USER_MPU | OCP_USER_SDMA,
2260};
2261
2262/* l3 s -> l4 fw */
2263static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
2264 .master = &am33xx_l3_s_hwmod,
2265 .slave = &am33xx_l4_fw_hwmod,
2266 .clk = "l3s_gclk",
2267 .user = OCP_USER_MPU | OCP_USER_SDMA,
2268};
2269
2270/* l3 main -> l3 instr */
2271static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
2272 .master = &am33xx_l3_main_hwmod,
2273 .slave = &am33xx_l3_instr_hwmod,
2274 .clk = "l3s_gclk",
2275 .user = OCP_USER_MPU | OCP_USER_SDMA,
2276};
2277
2278/* mpu -> prcm */
2279static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
2280 .master = &am33xx_mpu_hwmod,
2281 .slave = &am33xx_prcm_hwmod,
2282 .clk = "dpll_mpu_m2_ck",
2283 .user = OCP_USER_MPU | OCP_USER_SDMA,
2284};
2285
2286/* l3 s -> l3 main*/
2287static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
2288 .master = &am33xx_l3_s_hwmod,
2289 .slave = &am33xx_l3_main_hwmod,
2290 .clk = "l3s_gclk",
2291 .user = OCP_USER_MPU | OCP_USER_SDMA,
2292};
2293
2294/* pru-icss -> l3 main */
2295static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
2296 .master = &am33xx_pruss_hwmod,
2297 .slave = &am33xx_l3_main_hwmod,
2298 .clk = "l3_gclk",
2299 .user = OCP_USER_MPU | OCP_USER_SDMA,
2300};
2301
2302/* wkup m3 -> l4 wkup */
2303static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
2304 .master = &am33xx_wkup_m3_hwmod,
2305 .slave = &am33xx_l4_wkup_hwmod,
2306 .clk = "dpll_core_m4_div2_ck",
2307 .user = OCP_USER_MPU | OCP_USER_SDMA,
2308};
2309
2310/* gfx -> l3 main */
2311static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
2312 .master = &am33xx_gfx_hwmod,
2313 .slave = &am33xx_l3_main_hwmod,
2314 .clk = "dpll_core_m4_ck",
2315 .user = OCP_USER_MPU | OCP_USER_SDMA,
2316};
2317
2318/* l4 wkup -> wkup m3 */
2319static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
2320 {
2321 .name = "umem",
2322 .pa_start = 0x44d00000,
2323 .pa_end = 0x44d00000 + SZ_16K - 1,
2324 .flags = ADDR_TYPE_RT
2325 },
2326 {
2327 .name = "dmem",
2328 .pa_start = 0x44d80000,
2329 .pa_end = 0x44d80000 + SZ_8K - 1,
2330 .flags = ADDR_TYPE_RT
2331 },
2332 { }
2333};
2334
2335static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
2336 .master = &am33xx_l4_wkup_hwmod,
2337 .slave = &am33xx_wkup_m3_hwmod,
2338 .clk = "dpll_core_m4_div2_ck",
2339 .addr = am33xx_wkup_m3_addrs,
2340 .user = OCP_USER_MPU | OCP_USER_SDMA,
2341};
2342
2343/* l4 hs -> pru-icss */
2344static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
2345 {
2346 .pa_start = 0x4a300000,
2347 .pa_end = 0x4a300000 + SZ_512K - 1,
2348 .flags = ADDR_TYPE_RT
2349 },
2350 { }
2351};
2352
2353static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
2354 .master = &am33xx_l4_hs_hwmod,
2355 .slave = &am33xx_pruss_hwmod,
2356 .clk = "dpll_core_m4_ck",
2357 .addr = am33xx_pruss_addrs,
2358 .user = OCP_USER_MPU | OCP_USER_SDMA,
2359};
2360
2361/* l3 main -> gfx */
2362static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
2363 {
2364 .pa_start = 0x56000000,
2365 .pa_end = 0x56000000 + SZ_16M - 1,
2366 .flags = ADDR_TYPE_RT
2367 },
2368 { }
2369};
2370
2371static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
2372 .master = &am33xx_l3_main_hwmod,
2373 .slave = &am33xx_gfx_hwmod,
2374 .clk = "dpll_core_m4_ck",
2375 .addr = am33xx_gfx_addrs,
2376 .user = OCP_USER_MPU | OCP_USER_SDMA,
2377};
2378
2379/* l4 wkup -> smartreflex0 */
2380static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
2381 {
2382 .pa_start = 0x44e37000,
2383 .pa_end = 0x44e37000 + SZ_4K - 1,
2384 .flags = ADDR_TYPE_RT
2385 },
2386 { }
2387};
2388
2389static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
2390 .master = &am33xx_l4_wkup_hwmod,
2391 .slave = &am33xx_smartreflex0_hwmod,
2392 .clk = "dpll_core_m4_div2_ck",
2393 .addr = am33xx_smartreflex0_addrs,
2394 .user = OCP_USER_MPU,
2395};
2396
2397/* l4 wkup -> smartreflex1 */
2398static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
2399 {
2400 .pa_start = 0x44e39000,
2401 .pa_end = 0x44e39000 + SZ_4K - 1,
2402 .flags = ADDR_TYPE_RT
2403 },
2404 { }
2405};
2406
2407static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
2408 .master = &am33xx_l4_wkup_hwmod,
2409 .slave = &am33xx_smartreflex1_hwmod,
2410 .clk = "dpll_core_m4_div2_ck",
2411 .addr = am33xx_smartreflex1_addrs,
2412 .user = OCP_USER_MPU,
2413};
2414
2415/* l4 wkup -> control */
2416static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
2417 {
2418 .pa_start = 0x44e10000,
2419 .pa_end = 0x44e10000 + SZ_8K - 1,
2420 .flags = ADDR_TYPE_RT
2421 },
2422 { }
2423};
2424
2425static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
2426 .master = &am33xx_l4_wkup_hwmod,
2427 .slave = &am33xx_control_hwmod,
2428 .clk = "dpll_core_m4_div2_ck",
2429 .addr = am33xx_control_addrs,
2430 .user = OCP_USER_MPU,
2431};
2432
2433/* l4 wkup -> rtc */
2434static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
2435 {
2436 .pa_start = 0x44e3e000,
2437 .pa_end = 0x44e3e000 + SZ_4K - 1,
2438 .flags = ADDR_TYPE_RT
2439 },
2440 { }
2441};
2442
2443static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
2444 .master = &am33xx_l4_wkup_hwmod,
2445 .slave = &am33xx_rtc_hwmod,
2446 .clk = "clkdiv32k_ick",
2447 .addr = am33xx_rtc_addrs,
2448 .user = OCP_USER_MPU,
2449};
2450
2451/* l4 per/ls -> DCAN0 */
2452static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
2453 {
2454 .pa_start = 0x481CC000,
2455 .pa_end = 0x481CC000 + SZ_4K - 1,
2456 .flags = ADDR_TYPE_RT
2457 },
2458 { }
2459};
2460
2461static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
2462 .master = &am33xx_l4_ls_hwmod,
2463 .slave = &am33xx_dcan0_hwmod,
2464 .clk = "l4ls_gclk",
2465 .addr = am33xx_dcan0_addrs,
2466 .user = OCP_USER_MPU | OCP_USER_SDMA,
2467};
2468
2469/* l4 per/ls -> DCAN1 */
2470static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
2471 {
2472 .pa_start = 0x481D0000,
2473 .pa_end = 0x481D0000 + SZ_4K - 1,
2474 .flags = ADDR_TYPE_RT
2475 },
2476 { }
2477};
2478
2479static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
2480 .master = &am33xx_l4_ls_hwmod,
2481 .slave = &am33xx_dcan1_hwmod,
2482 .clk = "l4ls_gclk",
2483 .addr = am33xx_dcan1_addrs,
2484 .user = OCP_USER_MPU | OCP_USER_SDMA,
2485};
2486
2487/* l4 per/ls -> GPIO2 */
2488static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
2489 {
2490 .pa_start = 0x4804C000,
2491 .pa_end = 0x4804C000 + SZ_4K - 1,
2492 .flags = ADDR_TYPE_RT,
2493 },
2494 { }
2495};
2496
2497static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
2498 .master = &am33xx_l4_ls_hwmod,
2499 .slave = &am33xx_gpio1_hwmod,
2500 .clk = "l4ls_gclk",
2501 .addr = am33xx_gpio1_addrs,
2502 .user = OCP_USER_MPU | OCP_USER_SDMA,
2503};
2504
2505/* l4 per/ls -> gpio3 */
2506static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
2507 {
2508 .pa_start = 0x481AC000,
2509 .pa_end = 0x481AC000 + SZ_4K - 1,
2510 .flags = ADDR_TYPE_RT,
2511 },
2512 { }
2513};
2514
2515static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
2516 .master = &am33xx_l4_ls_hwmod,
2517 .slave = &am33xx_gpio2_hwmod,
2518 .clk = "l4ls_gclk",
2519 .addr = am33xx_gpio2_addrs,
2520 .user = OCP_USER_MPU | OCP_USER_SDMA,
2521};
2522
2523/* l4 per/ls -> gpio4 */
2524static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
2525 {
2526 .pa_start = 0x481AE000,
2527 .pa_end = 0x481AE000 + SZ_4K - 1,
2528 .flags = ADDR_TYPE_RT,
2529 },
2530 { }
2531};
2532
2533static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
2534 .master = &am33xx_l4_ls_hwmod,
2535 .slave = &am33xx_gpio3_hwmod,
2536 .clk = "l4ls_gclk",
2537 .addr = am33xx_gpio3_addrs,
2538 .user = OCP_USER_MPU | OCP_USER_SDMA,
2539};
2540
2541/* L4 WKUP -> I2C1 */
2542static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
2543 {
2544 .pa_start = 0x44E0B000,
2545 .pa_end = 0x44E0B000 + SZ_4K - 1,
2546 .flags = ADDR_TYPE_RT,
2547 },
2548 { }
2549};
2550
2551static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
2552 .master = &am33xx_l4_wkup_hwmod,
2553 .slave = &am33xx_i2c1_hwmod,
2554 .clk = "dpll_core_m4_div2_ck",
2555 .addr = am33xx_i2c1_addr_space,
2556 .user = OCP_USER_MPU,
2557};
2558
2559/* L4 WKUP -> GPIO1 */
2560static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
2561 {
2562 .pa_start = 0x44E07000,
2563 .pa_end = 0x44E07000 + SZ_4K - 1,
2564 .flags = ADDR_TYPE_RT,
2565 },
2566 { }
2567};
2568
2569static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
2570 .master = &am33xx_l4_wkup_hwmod,
2571 .slave = &am33xx_gpio0_hwmod,
2572 .clk = "dpll_core_m4_div2_ck",
2573 .addr = am33xx_gpio0_addrs,
2574 .user = OCP_USER_MPU | OCP_USER_SDMA,
2575};
2576
2577/* L4 WKUP -> ADC_TSC */
2578static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
2579 {
2580 .pa_start = 0x44E0D000,
2581 .pa_end = 0x44E0D000 + SZ_8K - 1,
2582 .flags = ADDR_TYPE_RT
2583 },
2584 { }
2585};
2586
2587static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
2588 .master = &am33xx_l4_wkup_hwmod,
2589 .slave = &am33xx_adc_tsc_hwmod,
2590 .clk = "dpll_core_m4_div2_ck",
2591 .addr = am33xx_adc_tsc_addrs,
2592 .user = OCP_USER_MPU,
2593};
2594
2595static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
2596 /* cpsw ss */
2597 {
2598 .pa_start = 0x4a100000,
2599 .pa_end = 0x4a100000 + SZ_2K - 1,
a2cfc509
VH		 2600 },
2601 /* cpsw wr */
2602 {
2603 .pa_start = 0x4a101200,
2604 .pa_end = 0x4a101200 + SZ_256 - 1,
2605 .flags = ADDR_TYPE_RT,
2606 },
2607 { }
2608};
2609
2610static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
2611 .master = &am33xx_l4_hs_hwmod,
2612 .slave = &am33xx_cpgmac0_hwmod,
2613 .clk = "cpsw_125mhz_gclk",
2614 .addr = am33xx_cpgmac0_addr_space,
2615 .user = OCP_USER_MPU,
2616};
2617
9816aa80 2618static struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
70384a6a
M		 2619 {
2620 .pa_start = 0x4A101000,
2621 .pa_end = 0x4A101000 + SZ_256 - 1,
2622 },
2623 { }
2624};
2625
9816aa80 2626static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
70384a6a
M		 2627 .master = &am33xx_cpgmac0_hwmod,
2628 .slave = &am33xx_mdio_hwmod,
2629 .addr = am33xx_mdio_addr_space,
2630 .user = OCP_USER_MPU,
2631};
2632
a2cfc509
VH		 2633static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
2634 {
2635 .pa_start = 0x48080000,
2636 .pa_end = 0x48080000 + SZ_8K - 1,
2637 .flags = ADDR_TYPE_RT
2638 },
2639 { }
2640};
2641
2642static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
2643 .master = &am33xx_l4_ls_hwmod,
2644 .slave = &am33xx_elm_hwmod,
2645 .clk = "l4ls_gclk",
2646 .addr = am33xx_elm_addr_space,
2647 .user = OCP_USER_MPU,
2648};
2649
9652d19a 2650static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
a2cfc509
VH		 2651 {
2652 .pa_start = 0x48300000,
2653 .pa_end = 0x48300000 + SZ_16 - 1,
2654 .flags = ADDR_TYPE_RT
2655 },
a2cfc509
VH		 2656 { }
2657};
2658
9652d19a 2659static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
a2cfc509 2660 .master = &am33xx_l4_ls_hwmod,
9652d19a 2661 .slave = &am33xx_epwmss0_hwmod,
a2cfc509 2662 .clk = "l4ls_gclk",
9652d19a 2663 .addr = am33xx_epwmss0_addr_space,
a2cfc509
VH		 2664 .user = OCP_USER_MPU,
2665};
2666
9652d19a 2667static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
a2cfc509 2668 {
9652d19a
PA		 2669 .pa_start = 0x48300100,
2670 .pa_end = 0x48300100 + SZ_128 - 1,
a2cfc509
VH		 2671 },
2672 { }
2673};
2674
9652d19a
PA		 2675static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
2676 .master = &am33xx_epwmss0_hwmod,
2677 .slave = &am33xx_ecap0_hwmod,
a2cfc509 2678 .clk = "l4ls_gclk",
9652d19a 2679 .addr = am33xx_ecap0_addr_space,
a2cfc509
VH		 2680 .user = OCP_USER_MPU,
2681};
2682
9652d19a 2683static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
a2cfc509 2684 {
9652d19a
PA		 2685 .pa_start = 0x48300180,
2686 .pa_end = 0x48300180 + SZ_128 - 1,
a2cfc509 2687 },
9652d19a
PA		 2688 { }
2689};
2690
2691static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
2692 .master = &am33xx_epwmss0_hwmod,
2693 .slave = &am33xx_eqep0_hwmod,
2694 .clk = "l4ls_gclk",
2695 .addr = am33xx_eqep0_addr_space,
2696 .user = OCP_USER_MPU,
2697};
2698
2699static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
a2cfc509 2700 {
9652d19a
PA		 2701 .pa_start = 0x48300200,
2702 .pa_end = 0x48300200 + SZ_128 - 1,
a2cfc509
VH		 2703 },
2704 { }
2705};
2706
9652d19a
PA		 2707static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
2708 .master = &am33xx_epwmss0_hwmod,
2709 .slave = &am33xx_ehrpwm0_hwmod,
a2cfc509 2710 .clk = "l4ls_gclk",
9652d19a 2711 .addr = am33xx_ehrpwm0_addr_space,
a2cfc509
VH		 2712 .user = OCP_USER_MPU,
2713};
2714
9652d19a
PA		 2715
2716static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
bee76659 2717 {
9652d19a
PA		 2718 .pa_start = 0x48302000,
2719 .pa_end = 0x48302000 + SZ_16 - 1,
bee76659
PA		 2720 .flags = ADDR_TYPE_RT
2721 },
bee76659
PA		 2722 { }
2723};
2724
9652d19a 2725static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
bee76659 2726 .master = &am33xx_l4_ls_hwmod,
9652d19a 2727 .slave = &am33xx_epwmss1_hwmod,
bee76659 2728 .clk = "l4ls_gclk",
9652d19a 2729 .addr = am33xx_epwmss1_addr_space,
bee76659
PA		 2730 .user = OCP_USER_MPU,
2731};
2732
9652d19a 2733static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
bee76659 2734 {
9652d19a
PA		 2735 .pa_start = 0x48302100,
2736 .pa_end = 0x48302100 + SZ_128 - 1,
bee76659 2737 },
9652d19a
PA		 2738 { }
2739};
2740
2741static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
2742 .master = &am33xx_epwmss1_hwmod,
2743 .slave = &am33xx_ecap1_hwmod,
2744 .clk = "l4ls_gclk",
2745 .addr = am33xx_ecap1_addr_space,
2746 .user = OCP_USER_MPU,
2747};
2748
2749static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
bee76659
PA		 2750 {
2751 .pa_start = 0x48302180,
2752 .pa_end = 0x48302180 + SZ_128 - 1,
2753 },
2754 { }
2755};
2756
9652d19a
PA		 2757static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
2758 .master = &am33xx_epwmss1_hwmod,
bee76659
PA		 2759 .slave = &am33xx_eqep1_hwmod,
2760 .clk = "l4ls_gclk",
2761 .addr = am33xx_eqep1_addr_space,
2762 .user = OCP_USER_MPU,
2763};
2764
9652d19a 2765static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
bee76659 2766 {
9652d19a
PA		 2767 .pa_start = 0x48302200,
2768 .pa_end = 0x48302200 + SZ_128 - 1,
bee76659
PA		 2769 },
2770 { }
2771};
2772
9652d19a
PA		 2773static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
2774 .master = &am33xx_epwmss1_hwmod,
2775 .slave = &am33xx_ehrpwm1_hwmod,
bee76659 2776 .clk = "l4ls_gclk",
9652d19a 2777 .addr = am33xx_ehrpwm1_addr_space,
bee76659
PA		 2778 .user = OCP_USER_MPU,
2779};
2780
9652d19a 2781static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
a2cfc509 2782 {
9652d19a
PA		 2783 .pa_start = 0x48304000,
2784 .pa_end = 0x48304000 + SZ_16 - 1,
a2cfc509
VH		 2785 .flags = ADDR_TYPE_RT
2786 },
a2cfc509
VH		 2787 { }
2788};
2789
9652d19a 2790static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
a2cfc509 2791 .master = &am33xx_l4_ls_hwmod,
9652d19a 2792 .slave = &am33xx_epwmss2_hwmod,
a2cfc509 2793 .clk = "l4ls_gclk",
9652d19a 2794 .addr = am33xx_epwmss2_addr_space,
a2cfc509
VH		 2795 .user = OCP_USER_MPU,
2796};
2797
9652d19a 2798static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
a2cfc509 2799 {
9652d19a
PA		 2800 .pa_start = 0x48304100,
2801 .pa_end = 0x48304100 + SZ_128 - 1,
a2cfc509
VH		 2802 },
2803 { }
2804};
2805
9652d19a
PA		 2806static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
2807 .master = &am33xx_epwmss2_hwmod,
2808 .slave = &am33xx_ecap2_hwmod,
a2cfc509 2809 .clk = "l4ls_gclk",
9652d19a 2810 .addr = am33xx_ecap2_addr_space,
a2cfc509
VH		 2811 .user = OCP_USER_MPU,
2812};
2813
9652d19a 2814static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
a2cfc509 2815 {
9652d19a
PA		 2816 .pa_start = 0x48304180,
2817 .pa_end = 0x48304180 + SZ_128 - 1,
a2cfc509 2818 },
9652d19a
PA		 2819 { }
2820};
2821
2822static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
2823 .master = &am33xx_epwmss2_hwmod,
2824 .slave = &am33xx_eqep2_hwmod,
2825 .clk = "l4ls_gclk",
2826 .addr = am33xx_eqep2_addr_space,
2827 .user = OCP_USER_MPU,
2828};
2829
2830static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
a2cfc509 2831 {
9652d19a
PA		 2832 .pa_start = 0x48304200,
2833 .pa_end = 0x48304200 + SZ_128 - 1,
a2cfc509
VH		 2834 },
2835 { }
2836};
2837
9652d19a
PA		 2838static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
2839 .master = &am33xx_epwmss2_hwmod,
2840 .slave = &am33xx_ehrpwm2_hwmod,
a2cfc509 2841 .clk = "l4ls_gclk",
9652d19a 2842 .addr = am33xx_ehrpwm2_addr_space,
a2cfc509
VH		 2843 .user = OCP_USER_MPU,
2844};
2845
2846/* l3s cfg -> gpmc */
2847static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
2848 {
2849 .pa_start = 0x50000000,
2850 .pa_end = 0x50000000 + SZ_8K - 1,
2851 .flags = ADDR_TYPE_RT,
2852 },
2853 { }
2854};
2855
2856static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
2857 .master = &am33xx_l3_s_hwmod,
2858 .slave = &am33xx_gpmc_hwmod,
2859 .clk = "l3s_gclk",
2860 .addr = am33xx_gpmc_addr_space,
2861 .user = OCP_USER_MPU,
2862};
2863
2864/* i2c2 */
2865static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
2866 {
2867 .pa_start = 0x4802A000,
2868 .pa_end = 0x4802A000 + SZ_4K - 1,
2869 .flags = ADDR_TYPE_RT,
2870 },
2871 { }
2872};
2873
2874static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
2875 .master = &am33xx_l4_ls_hwmod,
2876 .slave = &am33xx_i2c2_hwmod,
2877 .clk = "l4ls_gclk",
2878 .addr = am33xx_i2c2_addr_space,
2879 .user = OCP_USER_MPU,
2880};
2881
2882static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
2883 {
2884 .pa_start = 0x4819C000,
2885 .pa_end = 0x4819C000 + SZ_4K - 1,
2886 .flags = ADDR_TYPE_RT
2887 },
2888 { }
2889};
2890
2891static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
2892 .master = &am33xx_l4_ls_hwmod,
2893 .slave = &am33xx_i2c3_hwmod,
2894 .clk = "l4ls_gclk",
2895 .addr = am33xx_i2c3_addr_space,
2896 .user = OCP_USER_MPU,
2897};
2898
2899static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
2900 {
2901 .pa_start = 0x4830E000,
2902 .pa_end = 0x4830E000 + SZ_8K - 1,
2903 .flags = ADDR_TYPE_RT,
2904 },
2905 { }
2906};
2907
2908static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
2909 .master = &am33xx_l3_main_hwmod,
2910 .slave = &am33xx_lcdc_hwmod,
2911 .clk = "dpll_core_m4_ck",
2912 .addr = am33xx_lcdc_addr_space,
2913 .user = OCP_USER_MPU,
2914};
2915
2916static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
2917 {
2918 .pa_start = 0x480C8000,
2919 .pa_end = 0x480C8000 + (SZ_4K - 1),
2920 .flags = ADDR_TYPE_RT
2921 },
2922 { }
2923};
2924
2925/* l4 ls -> mailbox */
2926static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
2927 .master = &am33xx_l4_ls_hwmod,
2928 .slave = &am33xx_mailbox_hwmod,
2929 .clk = "l4ls_gclk",
2930 .addr = am33xx_mailbox_addrs,
2931 .user = OCP_USER_MPU,
2932};
2933
2934/* l4 ls -> spinlock */
2935static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
2936 {
2937 .pa_start = 0x480Ca000,
2938 .pa_end = 0x480Ca000 + SZ_4K - 1,
2939 .flags = ADDR_TYPE_RT
2940 },
2941 { }
2942};
2943
2944static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
2945 .master = &am33xx_l4_ls_hwmod,
2946 .slave = &am33xx_spinlock_hwmod,
2947 .clk = "l4ls_gclk",
2948 .addr = am33xx_spinlock_addrs,
2949 .user = OCP_USER_MPU,
2950};
2951
2952/* l4 ls -> mcasp0 */
2953static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
2954 {
2955 .pa_start = 0x48038000,
2956 .pa_end = 0x48038000 + SZ_8K - 1,
2957 .flags = ADDR_TYPE_RT
2958 },
2959 { }
2960};
2961
2962static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
2963 .master = &am33xx_l4_ls_hwmod,
2964 .slave = &am33xx_mcasp0_hwmod,
2965 .clk = "l4ls_gclk",
2966 .addr = am33xx_mcasp0_addr_space,
2967 .user = OCP_USER_MPU,
2968};
2969
2970/* l3 s -> mcasp0 data */
2971static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
2972 {
2973 .pa_start = 0x46000000,
2974 .pa_end = 0x46000000 + SZ_4M - 1,
2975 .flags = ADDR_TYPE_RT
2976 },
2977 { }
2978};
2979
2980static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
2981 .master = &am33xx_l3_s_hwmod,
2982 .slave = &am33xx_mcasp0_hwmod,
2983 .clk = "l3s_gclk",
2984 .addr = am33xx_mcasp0_data_addr_space,
2985 .user = OCP_USER_SDMA,
2986};
2987
2988/* l4 ls -> mcasp1 */
2989static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
2990 {
2991 .pa_start = 0x4803C000,
2992 .pa_end = 0x4803C000 + SZ_8K - 1,
2993 .flags = ADDR_TYPE_RT
2994 },
2995 { }
2996};
2997
2998static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
2999 .master = &am33xx_l4_ls_hwmod,
3000 .slave = &am33xx_mcasp1_hwmod,
3001 .clk = "l4ls_gclk",
3002 .addr = am33xx_mcasp1_addr_space,
3003 .user = OCP_USER_MPU,
3004};
3005
3006/* l3 s -> mcasp1 data */
3007static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
3008 {
3009 .pa_start = 0x46400000,
3010 .pa_end = 0x46400000 + SZ_4M - 1,
3011 .flags = ADDR_TYPE_RT
3012 },
3013 { }
3014};
3015
3016static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
3017 .master = &am33xx_l3_s_hwmod,
3018 .slave = &am33xx_mcasp1_hwmod,
3019 .clk = "l3s_gclk",
3020 .addr = am33xx_mcasp1_data_addr_space,
3021 .user = OCP_USER_SDMA,
3022};
3023
3024/* l4 ls -> mmc0 */
3025static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
3026 {
3027 .pa_start = 0x48060100,
3028 .pa_end = 0x48060100 + SZ_4K - 1,
3029 .flags = ADDR_TYPE_RT,
3030 },
3031 { }
3032};
3033
3034static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
3035 .master = &am33xx_l4_ls_hwmod,
3036 .slave = &am33xx_mmc0_hwmod,
3037 .clk = "l4ls_gclk",
3038 .addr = am33xx_mmc0_addr_space,
3039 .user = OCP_USER_MPU,
3040};
3041
3042/* l4 ls -> mmc1 */
3043static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
3044 {
3045 .pa_start = 0x481d8100,
3046 .pa_end = 0x481d8100 + SZ_4K - 1,
3047 .flags = ADDR_TYPE_RT,
3048 },
3049 { }
3050};
3051
3052static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
3053 .master = &am33xx_l4_ls_hwmod,
3054 .slave = &am33xx_mmc1_hwmod,
3055 .clk = "l4ls_gclk",
3056 .addr = am33xx_mmc1_addr_space,
3057 .user = OCP_USER_MPU,
3058};
3059
3060/* l3 s -> mmc2 */
3061static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
3062 {
3063 .pa_start = 0x47810100,
3064 .pa_end = 0x47810100 + SZ_64K - 1,
3065 .flags = ADDR_TYPE_RT,
3066 },
3067 { }
3068};
3069
3070static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
3071 .master = &am33xx_l3_s_hwmod,
3072 .slave = &am33xx_mmc2_hwmod,
3073 .clk = "l3s_gclk",
3074 .addr = am33xx_mmc2_addr_space,
3075 .user = OCP_USER_MPU,
3076};
3077
3078/* l4 ls -> mcspi0 */
3079static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
3080 {
3081 .pa_start = 0x48030000,
3082 .pa_end = 0x48030000 + SZ_1K - 1,
3083 .flags = ADDR_TYPE_RT,
3084 },
3085 { }
3086};
3087
3088static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
3089 .master = &am33xx_l4_ls_hwmod,
3090 .slave = &am33xx_spi0_hwmod,
3091 .clk = "l4ls_gclk",
3092 .addr = am33xx_mcspi0_addr_space,
3093 .user = OCP_USER_MPU,
3094};
3095
3096/* l4 ls -> mcspi1 */
3097static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
3098 {
3099 .pa_start = 0x481A0000,
3100 .pa_end = 0x481A0000 + SZ_1K - 1,
3101 .flags = ADDR_TYPE_RT,
3102 },
3103 { }
3104};
3105
3106static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
3107 .master = &am33xx_l4_ls_hwmod,
3108 .slave = &am33xx_spi1_hwmod,
3109 .clk = "l4ls_gclk",
3110 .addr = am33xx_mcspi1_addr_space,
3111 .user = OCP_USER_MPU,
3112};
3113
3114/* l4 wkup -> timer1 */
3115static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
3116 {
3117 .pa_start = 0x44E31000,
3118 .pa_end = 0x44E31000 + SZ_1K - 1,
3119 .flags = ADDR_TYPE_RT
3120 },
3121 { }
3122};
3123
3124static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
3125 .master = &am33xx_l4_wkup_hwmod,
3126 .slave = &am33xx_timer1_hwmod,
3127 .clk = "dpll_core_m4_div2_ck",
3128 .addr = am33xx_timer1_addr_space,
3129 .user = OCP_USER_MPU,
3130};
3131
3132/* l4 per -> timer2 */
3133static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
3134 {
3135 .pa_start = 0x48040000,
3136 .pa_end = 0x48040000 + SZ_1K - 1,
3137 .flags = ADDR_TYPE_RT
3138 },
3139 { }
3140};
3141
3142static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
3143 .master = &am33xx_l4_ls_hwmod,
3144 .slave = &am33xx_timer2_hwmod,
3145 .clk = "l4ls_gclk",
3146 .addr = am33xx_timer2_addr_space,
3147 .user = OCP_USER_MPU,
3148};
3149
3150/* l4 per -> timer3 */
3151static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
3152 {
3153 .pa_start = 0x48042000,
3154 .pa_end = 0x48042000 + SZ_1K - 1,
3155 .flags = ADDR_TYPE_RT
3156 },
3157 { }
3158};
3159
3160static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
3161 .master = &am33xx_l4_ls_hwmod,
3162 .slave = &am33xx_timer3_hwmod,
3163 .clk = "l4ls_gclk",
3164 .addr = am33xx_timer3_addr_space,
3165 .user = OCP_USER_MPU,
3166};
3167
3168/* l4 per -> timer4 */
3169static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
3170 {
3171 .pa_start = 0x48044000,
3172 .pa_end = 0x48044000 + SZ_1K - 1,
3173 .flags = ADDR_TYPE_RT
3174 },
3175 { }
3176};
3177
3178static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
3179 .master = &am33xx_l4_ls_hwmod,
3180 .slave = &am33xx_timer4_hwmod,
3181 .clk = "l4ls_gclk",
3182 .addr = am33xx_timer4_addr_space,
3183 .user = OCP_USER_MPU,
3184};
3185
3186/* l4 per -> timer5 */
3187static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
3188 {
3189 .pa_start = 0x48046000,
3190 .pa_end = 0x48046000 + SZ_1K - 1,
3191 .flags = ADDR_TYPE_RT
3192 },
3193 { }
3194};
3195
3196static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
3197 .master = &am33xx_l4_ls_hwmod,
3198 .slave = &am33xx_timer5_hwmod,
3199 .clk = "l4ls_gclk",
3200 .addr = am33xx_timer5_addr_space,
3201 .user = OCP_USER_MPU,
3202};
3203
3204/* l4 per -> timer6 */
3205static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
3206 {
3207 .pa_start = 0x48048000,
3208 .pa_end = 0x48048000 + SZ_1K - 1,
3209 .flags = ADDR_TYPE_RT
3210 },
3211 { }
3212};
3213
3214static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
3215 .master = &am33xx_l4_ls_hwmod,
3216 .slave = &am33xx_timer6_hwmod,
3217 .clk = "l4ls_gclk",
3218 .addr = am33xx_timer6_addr_space,
3219 .user = OCP_USER_MPU,
3220};
3221
3222/* l4 per -> timer7 */
3223static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
3224 {
3225 .pa_start = 0x4804A000,
3226 .pa_end = 0x4804A000 + SZ_1K - 1,
3227 .flags = ADDR_TYPE_RT
3228 },
3229 { }
3230};
3231
3232static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
3233 .master = &am33xx_l4_ls_hwmod,
3234 .slave = &am33xx_timer7_hwmod,
3235 .clk = "l4ls_gclk",
3236 .addr = am33xx_timer7_addr_space,
3237 .user = OCP_USER_MPU,
3238};
3239
3240/* l3 main -> tpcc */
3241static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
3242 {
3243 .pa_start = 0x49000000,
3244 .pa_end = 0x49000000 + SZ_32K - 1,
3245 .flags = ADDR_TYPE_RT
3246 },
3247 { }
3248};
3249
3250static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
3251 .master = &am33xx_l3_main_hwmod,
3252 .slave = &am33xx_tpcc_hwmod,
3253 .clk = "l3_gclk",
3254 .addr = am33xx_tpcc_addr_space,
3255 .user = OCP_USER_MPU,
3256};
3257
3258/* l3 main -> tpcc0 */
3259static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
3260 {
3261 .pa_start = 0x49800000,
3262 .pa_end = 0x49800000 + SZ_8K - 1,
3263 .flags = ADDR_TYPE_RT,
3264 },
3265 { }
3266};
3267
3268static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
3269 .master = &am33xx_l3_main_hwmod,
3270 .slave = &am33xx_tptc0_hwmod,
3271 .clk = "l3_gclk",
3272 .addr = am33xx_tptc0_addr_space,
3273 .user = OCP_USER_MPU,
3274};
3275
3276/* l3 main -> tpcc1 */
3277static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
3278 {
3279 .pa_start = 0x49900000,
3280 .pa_end = 0x49900000 + SZ_8K - 1,
3281 .flags = ADDR_TYPE_RT,
3282 },
3283 { }
3284};
3285
3286static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
3287 .master = &am33xx_l3_main_hwmod,
3288 .slave = &am33xx_tptc1_hwmod,
3289 .clk = "l3_gclk",
3290 .addr = am33xx_tptc1_addr_space,
3291 .user = OCP_USER_MPU,
3292};
3293
3294/* l3 main -> tpcc2 */
3295static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
3296 {
3297 .pa_start = 0x49a00000,
3298 .pa_end = 0x49a00000 + SZ_8K - 1,
3299 .flags = ADDR_TYPE_RT,
3300 },
3301 { }
3302};
3303
3304static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
3305 .master = &am33xx_l3_main_hwmod,
3306 .slave = &am33xx_tptc2_hwmod,
3307 .clk = "l3_gclk",
3308 .addr = am33xx_tptc2_addr_space,
3309 .user = OCP_USER_MPU,
3310};
3311
3312/* l4 wkup -> uart1 */
3313static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
3314 {
3315 .pa_start = 0x44E09000,
3316 .pa_end = 0x44E09000 + SZ_8K - 1,
3317 .flags = ADDR_TYPE_RT,
3318 },
3319 { }
3320};
3321
3322static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
3323 .master = &am33xx_l4_wkup_hwmod,
3324 .slave = &am33xx_uart1_hwmod,
3325 .clk = "dpll_core_m4_div2_ck",
3326 .addr = am33xx_uart1_addr_space,
3327 .user = OCP_USER_MPU,
3328};
3329
3330/* l4 ls -> uart2 */
3331static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
3332 {
3333 .pa_start = 0x48022000,
3334 .pa_end = 0x48022000 + SZ_8K - 1,
3335 .flags = ADDR_TYPE_RT,
3336 },
3337 { }
3338};
3339
3340static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
3341 .master = &am33xx_l4_ls_hwmod,
3342 .slave = &am33xx_uart2_hwmod,
3343 .clk = "l4ls_gclk",
3344 .addr = am33xx_uart2_addr_space,
3345 .user = OCP_USER_MPU,
3346};
3347
3348/* l4 ls -> uart3 */
3349static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
3350 {
3351 .pa_start = 0x48024000,
3352 .pa_end = 0x48024000 + SZ_8K - 1,
3353 .flags = ADDR_TYPE_RT,
3354 },
3355 { }
3356};
3357
3358static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
3359 .master = &am33xx_l4_ls_hwmod,
3360 .slave = &am33xx_uart3_hwmod,
3361 .clk = "l4ls_gclk",
3362 .addr = am33xx_uart3_addr_space,
3363 .user = OCP_USER_MPU,
3364};
3365
3366/* l4 ls -> uart4 */
3367static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
3368 {
3369 .pa_start = 0x481A6000,
3370 .pa_end = 0x481A6000 + SZ_8K - 1,
3371 .flags = ADDR_TYPE_RT,
3372 },
3373 { }
3374};
3375
3376static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
3377 .master = &am33xx_l4_ls_hwmod,
3378 .slave = &am33xx_uart4_hwmod,
3379 .clk = "l4ls_gclk",
3380 .addr = am33xx_uart4_addr_space,
3381 .user = OCP_USER_MPU,
3382};
3383
3384/* l4 ls -> uart5 */
3385static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
3386 {
3387 .pa_start = 0x481A8000,
3388 .pa_end = 0x481A8000 + SZ_8K - 1,
3389 .flags = ADDR_TYPE_RT,
3390 },
3391 { }
3392};
3393
3394static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
3395 .master = &am33xx_l4_ls_hwmod,
3396 .slave = &am33xx_uart5_hwmod,
3397 .clk = "l4ls_gclk",
3398 .addr = am33xx_uart5_addr_space,
3399 .user = OCP_USER_MPU,
3400};
3401
3402/* l4 ls -> uart6 */
3403static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
3404 {
3405 .pa_start = 0x481aa000,
3406 .pa_end = 0x481aa000 + SZ_8K - 1,
3407 .flags = ADDR_TYPE_RT,
3408 },
3409 { }
3410};
3411
3412static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
3413 .master = &am33xx_l4_ls_hwmod,
3414 .slave = &am33xx_uart6_hwmod,
3415 .clk = "l4ls_gclk",
3416 .addr = am33xx_uart6_addr_space,
3417 .user = OCP_USER_MPU,
3418};
3419
3420/* l4 wkup -> wd_timer1 */
3421static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
3422 {
3423 .pa_start = 0x44e35000,
3424 .pa_end = 0x44e35000 + SZ_4K - 1,
3425 .flags = ADDR_TYPE_RT
3426 },
3427 { }
3428};
3429
3430static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
3431 .master = &am33xx_l4_wkup_hwmod,
3432 .slave = &am33xx_wd_timer1_hwmod,
3433 .clk = "dpll_core_m4_div2_ck",
3434 .addr = am33xx_wd_timer1_addrs,
3435 .user = OCP_USER_MPU,
3436};
3437
3438/* usbss */
3439/* l3 s -> USBSS interface */
3440static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
3441 {
3442 .name = "usbss",
3443 .pa_start = 0x47400000,
3444 .pa_end = 0x47400000 + SZ_4K - 1,
3445 .flags = ADDR_TYPE_RT
3446 },
3447 {
3448 .name = "musb0",
3449 .pa_start = 0x47401000,
3450 .pa_end = 0x47401000 + SZ_2K - 1,
3451 .flags = ADDR_TYPE_RT
3452 },
3453 {
3454 .name = "musb1",
3455 .pa_start = 0x47401800,
3456 .pa_end = 0x47401800 + SZ_2K - 1,
3457 .flags = ADDR_TYPE_RT
3458 },
3459 { }
3460};
3461
3462static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
3463 .master = &am33xx_l3_s_hwmod,
3464 .slave = &am33xx_usbss_hwmod,
3465 .clk = "l3s_gclk",
3466 .addr = am33xx_usbss_addr_space,
3467 .user = OCP_USER_MPU,
3468 .flags = OCPIF_SWSUP_IDLE,
3469};
3470
ca903b6f
VB		 3471/* l3 main -> ocmc */
3472static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
3473 .master = &am33xx_l3_main_hwmod,
3474 .slave = &am33xx_ocmcram_hwmod,
3475 .user = OCP_USER_MPU | OCP_USER_SDMA,
3476};
3477
aec94bf5
MG		 3478/* l3 main -> sha0 HIB2 */
3479static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = {
3480 {
3481 .pa_start = 0x53100000,
3482 .pa_end = 0x53100000 + SZ_512 - 1,
3483 .flags = ADDR_TYPE_RT
3484 },
3485 { }
3486};
3487
3488static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
3489 .master = &am33xx_l3_main_hwmod,
3490 .slave = &am33xx_sha0_hwmod,
3491 .clk = "sha0_fck",
3492 .addr = am33xx_sha0_addrs,
3493 .user = OCP_USER_MPU | OCP_USER_SDMA,
3494};
3495
1cb804b9
MG		 3496/* l3 main -> AES0 HIB2 */
3497static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = {
3498 {
3499 .pa_start = 0x53500000,
3500 .pa_end = 0x53500000 + SZ_1M - 1,
3501 .flags = ADDR_TYPE_RT
3502 },
3503 { }
3504};
3505
3506static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
3507 .master = &am33xx_l3_main_hwmod,
3508 .slave = &am33xx_aes0_hwmod,
3509 .clk = "aes0_fck",
3510 .addr = am33xx_aes0_addrs,
3511 .user = OCP_USER_MPU | OCP_USER_SDMA,
3512};
3513
a2cfc509
VH		 3514static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3515 &am33xx_l4_fw__emif_fw,
3516 &am33xx_l3_main__emif,
3517 &am33xx_mpu__l3_main,
3518 &am33xx_mpu__prcm,
3519 &am33xx_l3_s__l4_ls,
3520 &am33xx_l3_s__l4_wkup,
3521 &am33xx_l3_s__l4_fw,
3522 &am33xx_l3_main__l4_hs,
3523 &am33xx_l3_main__l3_s,
3524 &am33xx_l3_main__l3_instr,
3525 &am33xx_l3_main__gfx,
3526 &am33xx_l3_s__l3_main,
3527 &am33xx_pruss__l3_main,
3528 &am33xx_wkup_m3__l4_wkup,
3529 &am33xx_gfx__l3_main,
3530 &am33xx_l4_wkup__wkup_m3,
3531 &am33xx_l4_wkup__control,
3532 &am33xx_l4_wkup__smartreflex0,
3533 &am33xx_l4_wkup__smartreflex1,
3534 &am33xx_l4_wkup__uart1,
3535 &am33xx_l4_wkup__timer1,
3536 &am33xx_l4_wkup__rtc,
3537 &am33xx_l4_wkup__i2c1,
3538 &am33xx_l4_wkup__gpio0,
3539 &am33xx_l4_wkup__adc_tsc,
3540 &am33xx_l4_wkup__wd_timer1,
3541 &am33xx_l4_hs__pruss,
3542 &am33xx_l4_per__dcan0,
3543 &am33xx_l4_per__dcan1,
3544 &am33xx_l4_per__gpio1,
3545 &am33xx_l4_per__gpio2,
3546 &am33xx_l4_per__gpio3,
3547 &am33xx_l4_per__i2c2,
3548 &am33xx_l4_per__i2c3,
3549 &am33xx_l4_per__mailbox,
3550 &am33xx_l4_ls__mcasp0,
3551 &am33xx_l3_s__mcasp0_data,
3552 &am33xx_l4_ls__mcasp1,
3553 &am33xx_l3_s__mcasp1_data,
3554 &am33xx_l4_ls__mmc0,
3555 &am33xx_l4_ls__mmc1,
3556 &am33xx_l3_s__mmc2,
3557 &am33xx_l4_ls__timer2,
3558 &am33xx_l4_ls__timer3,
3559 &am33xx_l4_ls__timer4,
3560 &am33xx_l4_ls__timer5,
3561 &am33xx_l4_ls__timer6,
3562 &am33xx_l4_ls__timer7,
3563 &am33xx_l3_main__tpcc,
3564 &am33xx_l4_ls__uart2,
3565 &am33xx_l4_ls__uart3,
3566 &am33xx_l4_ls__uart4,
3567 &am33xx_l4_ls__uart5,
3568 &am33xx_l4_ls__uart6,
3569 &am33xx_l4_ls__spinlock,
3570 &am33xx_l4_ls__elm,
9652d19a
PA		 3571 &am33xx_l4_ls__epwmss0,
3572 &am33xx_epwmss0__ecap0,
3573 &am33xx_epwmss0__eqep0,
3574 &am33xx_epwmss0__ehrpwm0,
3575 &am33xx_l4_ls__epwmss1,
3576 &am33xx_epwmss1__ecap1,
3577 &am33xx_epwmss1__eqep1,
3578 &am33xx_epwmss1__ehrpwm1,
3579 &am33xx_l4_ls__epwmss2,
3580 &am33xx_epwmss2__ecap2,
3581 &am33xx_epwmss2__eqep2,
3582 &am33xx_epwmss2__ehrpwm2,
a2cfc509
VH		 3583 &am33xx_l3_s__gpmc,
3584 &am33xx_l3_main__lcdc,
3585 &am33xx_l4_ls__mcspi0,
3586 &am33xx_l4_ls__mcspi1,
3587 &am33xx_l3_main__tptc0,
3588 &am33xx_l3_main__tptc1,
3589 &am33xx_l3_main__tptc2,
ca903b6f 3590 &am33xx_l3_main__ocmc,
a2cfc509
VH		 3591 &am33xx_l3_s__usbss,
3592 &am33xx_l4_hs__cpgmac0,
70384a6a 3593 &am33xx_cpgmac0__mdio,
aec94bf5 3594 &am33xx_l3_main__sha0,
1cb804b9 3595 &am33xx_l3_main__aes0,
a2cfc509
VH		 3596 NULL,
3597};
3598
3599int __init am33xx_hwmod_init(void)
3600{
3601 omap_hwmod_init();
3602 return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
3603}
Linux kernel - Deliverables
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