[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_33xx_data.c

/*
 * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
 *
 * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
 *
 * This file is automatically generated from the AM33XX hardware databases.
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

#include <linux/i2c-omap.h>

#include "omap_hwmod.h"
#include <linux/platform_data/gpio-omap.h>
#include <linux/platform_data/spi-omap2-mcspi.h>

#include "omap_hwmod_common_data.h"

#include "control.h"
#include "cm33xx.h"
#include "prm33xx.h"
#include "prm-regbits-33xx.h"
#include "i2c.h"
#include "mmc.h"
#include "wd_timer.h"
#include "omap_hwmod_33xx_43xx_common_data.h"

/*
 * IP blocks
 */

/*
 * 'emif' class
 * instance(s): emif
 */
static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
	.rev_offs	= 0x0000,
};

static struct omap_hwmod_class am33xx_emif_hwmod_class = {
	.name		= "emif",
	.sysc		= &am33xx_emif_sysc,
};

/* emif */
static struct omap_hwmod am33xx_emif_hwmod = {
	.name		= "emif",
	.class		= &am33xx_emif_hwmod_class,
	.clkdm_name	= "l3_clkdm",
	.flags		= HWMOD_INIT_NO_IDLE,
	.main_clk	= "dpll_ddr_m2_div2_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/* l4_hs */
static struct omap_hwmod am33xx_l4_hs_hwmod = {
	.name		= "l4_hs",
	.class		= &am33xx_l4_hwmod_class,
	.clkdm_name	= "l4hs_clkdm",
	.flags		= HWMOD_INIT_NO_IDLE,
	.main_clk	= "l4hs_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
	{ .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
};

/* wkup_m3  */
static struct omap_hwmod am33xx_wkup_m3_hwmod = {
	.name		= "wkup_m3",
	.class		= &am33xx_wkup_m3_hwmod_class,
	.clkdm_name	= "l4_wkup_aon_clkdm",
	/* Keep hardreset asserted */
	.flags		= HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
	.main_clk	= "dpll_core_m4_div2_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
			.rstctrl_offs	= AM33XX_RM_WKUP_RSTCTRL_OFFSET,
			.rstst_offs	= AM33XX_RM_WKUP_RSTST_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
	.rst_lines	= am33xx_wkup_m3_resets,
	.rst_lines_cnt	= ARRAY_SIZE(am33xx_wkup_m3_resets),
};

/*
 * 'adc/tsc' class
 * TouchScreen Controller (Anolog-To-Digital Converter)
 */
static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
	.rev_offs	= 0x00,
	.sysc_offs	= 0x10,
	.sysc_flags	= SYSC_HAS_SIDLEMODE,
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
	.name		= "adc_tsc",
	.sysc		= &am33xx_adc_tsc_sysc,
};

static struct omap_hwmod am33xx_adc_tsc_hwmod = {
	.name		= "adc_tsc",
	.class		= &am33xx_adc_tsc_hwmod_class,
	.clkdm_name	= "l4_wkup_clkdm",
	.main_clk	= "adc_tsc_fck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/*
 * Modules omap_hwmod structures
 *
 * The following IPs are excluded for the moment because:
 * - They do not need an explicit SW control using omap_hwmod API.
 * - They still need to be validated with the driver
 *   properly adapted to omap_hwmod / omap_device
 *
 *    - cEFUSE (doesn't fall under any ocp_if)
 *    - clkdiv32k
 *    - ocp watch point
 */
#if 0
/*
 * 'cefuse' class
 */
static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
	.name		= "cefuse",
};

static struct omap_hwmod am33xx_cefuse_hwmod = {
	.name		= "cefuse",
	.class		= &am33xx_cefuse_hwmod_class,
	.clkdm_name	= "l4_cefuse_clkdm",
	.main_clk	= "cefuse_fck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'clkdiv32k' class
 */
static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
	.name		= "clkdiv32k",
};

static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
	.name		= "clkdiv32k",
	.class		= &am33xx_clkdiv32k_hwmod_class,
	.clkdm_name	= "clk_24mhz_clkdm",
	.main_clk	= "clkdiv32k_ick",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/* ocpwp */
static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
	.name		= "ocpwp",
};

static struct omap_hwmod am33xx_ocpwp_hwmod = {
	.name		= "ocpwp",
	.class		= &am33xx_ocpwp_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.main_clk	= "l4ls_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};
#endif

/*
 * 'debugss' class
 * debug sub system
 */
static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
	{ .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
	{ .role = "dbg_clka", .clk = "dbg_clka_ck" },
};

static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
	.name		= "debugss",
};

static struct omap_hwmod am33xx_debugss_hwmod = {
	.name		= "debugss",
	.class		= &am33xx_debugss_hwmod_class,
	.clkdm_name	= "l3_aon_clkdm",
	.main_clk	= "trace_clk_div_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
	.opt_clks	= debugss_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(debugss_opt_clks),
};

static struct omap_hwmod am33xx_control_hwmod = {
	.name		= "control",
	.class		= &am33xx_control_hwmod_class,
	.clkdm_name	= "l4_wkup_clkdm",
	.flags		= HWMOD_INIT_NO_IDLE,
	.main_clk	= "dpll_core_m4_div2_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/* gpio0 */
static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
	{ .role = "dbclk", .clk = "gpio0_dbclk" },
};

static struct omap_hwmod am33xx_gpio0_hwmod = {
	.name		= "gpio1",
	.class		= &am33xx_gpio_hwmod_class,
	.clkdm_name	= "l4_wkup_clkdm",
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.main_clk	= "dpll_core_m4_div2_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
	.opt_clks	= gpio0_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio0_opt_clks),
	.dev_attr	= &gpio_dev_attr,
};

/* lcdc */
static struct omap_hwmod_class_sysconfig lcdc_sysc = {
	.rev_offs	= 0x0,
	.sysc_offs	= 0x54,
	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
	.name		= "lcdc",
	.sysc		= &lcdc_sysc,
};

static struct omap_hwmod am33xx_lcdc_hwmod = {
	.name		= "lcdc",
	.class		= &am33xx_lcdc_hwmod_class,
	.clkdm_name	= "lcdc_clkdm",
	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
	.main_clk	= "lcd_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

/*
 * 'usb_otg' class
 * high-speed on-the-go universal serial bus (usb_otg) controller
 */
static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
	.rev_offs	= 0x0,
	.sysc_offs	= 0x10,
	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			  MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class am33xx_usbotg_class = {
	.name		= "usbotg",
	.sysc		= &am33xx_usbhsotg_sysc,
};

static struct omap_hwmod am33xx_usbss_hwmod = {
	.name		= "usb_otg_hs",
	.class		= &am33xx_usbotg_class,
	.clkdm_name	= "l3s_clkdm",
	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
	.main_clk	= "usbotg_fck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};


/*
 * Interfaces
 */

static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
	{
		.pa_start	= 0x4c000000,
		.pa_end		= 0x4c000fff,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};
/* l3 main -> emif */
static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
	.master		= &am33xx_l3_main_hwmod,
	.slave		= &am33xx_emif_hwmod,
	.clk		= "dpll_core_m4_ck",
	.addr		= am33xx_emif_addrs,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3 main -> l4 hs */
static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
	.master		= &am33xx_l3_main_hwmod,
	.slave		= &am33xx_l4_hs_hwmod,
	.clk		= "l3s_gclk",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* wkup m3 -> l4 wkup */
static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
	.master		= &am33xx_wkup_m3_hwmod,
	.slave		= &am33xx_l4_wkup_hwmod,
	.clk		= "dpll_core_m4_div2_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4 wkup -> wkup m3 */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am33xx_wkup_m3_hwmod,
	.clk		= "dpll_core_m4_div2_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4 hs -> pru-icss */
static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
	.master		= &am33xx_l4_hs_hwmod,
	.slave		= &am33xx_pruss_hwmod,
	.clk		= "dpll_core_m4_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3_main -> debugss */
static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = {
	{
		.pa_start	= 0x4b000000,
		.pa_end		= 0x4b000000 + SZ_16M - 1,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
	.master		= &am33xx_l3_main_hwmod,
	.slave		= &am33xx_debugss_hwmod,
	.clk		= "dpll_core_m4_ck",
	.addr		= am33xx_debugss_addrs,
	.user		= OCP_USER_MPU,
};

/* l4 wkup -> smartreflex0 */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am33xx_smartreflex0_hwmod,
	.clk		= "dpll_core_m4_div2_ck",
	.user		= OCP_USER_MPU,
};

/* l4 wkup -> smartreflex1 */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am33xx_smartreflex1_hwmod,
	.clk		= "dpll_core_m4_div2_ck",
	.user		= OCP_USER_MPU,
};

/* l4 wkup -> control */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am33xx_control_hwmod,
	.clk		= "dpll_core_m4_div2_ck",
	.user		= OCP_USER_MPU,
};

/* L4 WKUP -> I2C1 */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am33xx_i2c1_hwmod,
	.clk		= "dpll_core_m4_div2_ck",
	.user		= OCP_USER_MPU,
};

/* L4 WKUP -> GPIO1 */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am33xx_gpio0_hwmod,
	.clk		= "dpll_core_m4_div2_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* L4 WKUP -> ADC_TSC */
static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
	{
		.pa_start	= 0x44E0D000,
		.pa_end		= 0x44E0D000 + SZ_8K - 1,
		.flags		= ADDR_TYPE_RT
	},
	{ }
};

static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am33xx_adc_tsc_hwmod,
	.clk		= "dpll_core_m4_div2_ck",
	.addr		= am33xx_adc_tsc_addrs,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
	.master		= &am33xx_l4_hs_hwmod,
	.slave		= &am33xx_cpgmac0_hwmod,
	.clk		= "cpsw_125mhz_gclk",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
	{
		.pa_start	= 0x4830E000,
		.pa_end		= 0x4830E000 + SZ_8K - 1,
		.flags		= ADDR_TYPE_RT,
	},
	{ }
};

static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
	.master		= &am33xx_l3_main_hwmod,
	.slave		= &am33xx_lcdc_hwmod,
	.clk		= "dpll_core_m4_ck",
	.addr		= am33xx_lcdc_addr_space,
	.user		= OCP_USER_MPU,
};

/* l4 wkup -> timer1 */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am33xx_timer1_hwmod,
	.clk		= "dpll_core_m4_div2_ck",
	.user		= OCP_USER_MPU,
};

/* l4 wkup -> uart1 */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am33xx_uart1_hwmod,
	.clk		= "dpll_core_m4_div2_ck",
	.user		= OCP_USER_MPU,
};

/* l4 wkup -> wd_timer1 */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am33xx_wd_timer1_hwmod,
	.clk		= "dpll_core_m4_div2_ck",
	.user		= OCP_USER_MPU,
};

/* usbss */
/* l3 s -> USBSS interface */
static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
	.master		= &am33xx_l3_s_hwmod,
	.slave		= &am33xx_usbss_hwmod,
	.clk		= "l3s_gclk",
	.user		= OCP_USER_MPU,
	.flags		= OCPIF_SWSUP_IDLE,
};

/* rng */
static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
	.rev_offs	= 0x1fe0,
	.sysc_offs	= 0x1fe4,
	.sysc_flags	= SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
	.idlemodes	= SIDLE_FORCE | SIDLE_NO,
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class am33xx_rng_hwmod_class = {
	.name		= "rng",
	.sysc		= &am33xx_rng_sysc,
};

static struct omap_hwmod am33xx_rng_hwmod = {
	.name		= "rng",
	.class		= &am33xx_rng_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.flags		= HWMOD_SWSUP_SIDLE,
	.main_clk	= "rng_fck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM33XX_CM_PER_RNG_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod_ocp_if am33xx_l4_per__rng = {
	.master		= &am33xx_l4_ls_hwmod,
	.slave		= &am33xx_rng_hwmod,
	.clk		= "rng_fck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
	&am33xx_l3_main__emif,
	&am33xx_mpu__l3_main,
	&am33xx_mpu__prcm,
	&am33xx_l3_s__l4_ls,
	&am33xx_l3_s__l4_wkup,
	&am33xx_l3_main__l4_hs,
	&am33xx_l3_main__l3_s,
	&am33xx_l3_main__l3_instr,
	&am33xx_l3_main__gfx,
	&am33xx_l3_s__l3_main,
	&am33xx_pruss__l3_main,
	&am33xx_wkup_m3__l4_wkup,
	&am33xx_gfx__l3_main,
	&am33xx_l3_main__debugss,
	&am33xx_l4_wkup__wkup_m3,
	&am33xx_l4_wkup__control,
	&am33xx_l4_wkup__smartreflex0,
	&am33xx_l4_wkup__smartreflex1,
	&am33xx_l4_wkup__uart1,
	&am33xx_l4_wkup__timer1,
	&am33xx_l4_wkup__rtc,
	&am33xx_l4_wkup__i2c1,
	&am33xx_l4_wkup__gpio0,
	&am33xx_l4_wkup__adc_tsc,
	&am33xx_l4_wkup__wd_timer1,
	&am33xx_l4_hs__pruss,
	&am33xx_l4_per__dcan0,
	&am33xx_l4_per__dcan1,
	&am33xx_l4_per__gpio1,
	&am33xx_l4_per__gpio2,
	&am33xx_l4_per__gpio3,
	&am33xx_l4_per__i2c2,
	&am33xx_l4_per__i2c3,
	&am33xx_l4_per__mailbox,
	&am33xx_l4_ls__mcasp0,
	&am33xx_l4_ls__mcasp1,
	&am33xx_l4_ls__mmc0,
	&am33xx_l4_ls__mmc1,
	&am33xx_l3_s__mmc2,
	&am33xx_l4_ls__timer2,
	&am33xx_l4_ls__timer3,
	&am33xx_l4_ls__timer4,
	&am33xx_l4_ls__timer5,
	&am33xx_l4_ls__timer6,
	&am33xx_l4_ls__timer7,
	&am33xx_l3_main__tpcc,
	&am33xx_l4_ls__uart2,
	&am33xx_l4_ls__uart3,
	&am33xx_l4_ls__uart4,
	&am33xx_l4_ls__uart5,
	&am33xx_l4_ls__uart6,
	&am33xx_l4_ls__spinlock,
	&am33xx_l4_ls__elm,
	&am33xx_l4_ls__epwmss0,
	&am33xx_epwmss0__ecap0,
	&am33xx_epwmss0__eqep0,
	&am33xx_epwmss0__ehrpwm0,
	&am33xx_l4_ls__epwmss1,
	&am33xx_epwmss1__ecap1,
	&am33xx_epwmss1__eqep1,
	&am33xx_epwmss1__ehrpwm1,
	&am33xx_l4_ls__epwmss2,
	&am33xx_epwmss2__ecap2,
	&am33xx_epwmss2__eqep2,
	&am33xx_epwmss2__ehrpwm2,
	&am33xx_l3_s__gpmc,
	&am33xx_l3_main__lcdc,
	&am33xx_l4_ls__mcspi0,
	&am33xx_l4_ls__mcspi1,
	&am33xx_l3_main__tptc0,
	&am33xx_l3_main__tptc1,
	&am33xx_l3_main__tptc2,
	&am33xx_l3_main__ocmc,
	&am33xx_l3_s__usbss,
	&am33xx_l4_hs__cpgmac0,
	&am33xx_cpgmac0__mdio,
	&am33xx_l3_main__sha0,
	&am33xx_l3_main__aes0,
	&am33xx_l4_per__rng,
	NULL,
};

int __init am33xx_hwmod_init(void)
{
	omap_hwmod_am33xx_reg();
	omap_hwmod_init();
	return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
}
Commit	Line	Data
a2cfc509 VH	1	/*
	2	* omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
	3	*
	4	* Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
	5	*
	6	* This file is automatically generated from the AM33XX hardware databases.
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation version 2.
	10	*
	11	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	12	* kind, whether express or implied; without even the implied warranty
	13	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*/
	16
3a8761c0 TL	17	#include <linux/i2c-omap.h>
3a8761c0 TL	18
2a296c8f	19	#include "omap_hwmod.h"
11964f53	20	#include <linux/platform_data/gpio-omap.h>
aa817b2e	21	#include <linux/platform_data/spi-omap2-mcspi.h>
a2cfc509 VH	22
	23	#include "omap_hwmod_common_data.h"
	24
	25	#include "control.h"
	26	#include "cm33xx.h"
	27	#include "prm33xx.h"
	28	#include "prm-regbits-33xx.h"
3a8761c0	29	#include "i2c.h"
68f39e74	30	#include "mmc.h"
05cf03b6	31	#include "wd_timer.h"
26649467	32	#include "omap_hwmod_33xx_43xx_common_data.h"
a2cfc509	33
a2cfc509 VH	34	/*
	35	* IP blocks
	36	*/
	37
a2cfc509 VH	38	/*
	39	* 'emif' class
	40	* instance(s): emif
	41	*/
	42	static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
	43	.rev_offs = 0x0000,
	44	};
	45
	46	static struct omap_hwmod_class am33xx_emif_hwmod_class = {
	47	.name = "emif",
	48	.sysc = &am33xx_emif_sysc,
	49	};
	50
a2cfc509 VH	51	/* emif */
	52	static struct omap_hwmod am33xx_emif_hwmod = {
	53	.name = "emif",
	54	.class = &am33xx_emif_hwmod_class,
	55	.clkdm_name = "l3_clkdm",
b2eb0002	56	.flags = HWMOD_INIT_NO_IDLE,
a2cfc509 VH	57	.main_clk = "dpll_ddr_m2_div2_ck",
	58	.prcm = {
	59	.omap4 = {
	60	.clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
	61	.modulemode = MODULEMODE_SWCTRL,
	62	},
	63	},
	64	};
	65
a2cfc509 VH	66	/* l4_hs */
	67	static struct omap_hwmod am33xx_l4_hs_hwmod = {
	68	.name = "l4_hs",
	69	.class = &am33xx_l4_hwmod_class,
	70	.clkdm_name = "l4hs_clkdm",
b2eb0002	71	.flags = HWMOD_INIT_NO_IDLE,
a2cfc509 VH	72	.main_clk = "l4hs_gclk",
	73	.prcm = {
	74	.omap4 = {
	75	.clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
	76	.modulemode = MODULEMODE_SWCTRL,
	77	},
	78	},
	79	};
	80
a2cfc509 VH	81	static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
	82	{ .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
	83	};
	84
a2cfc509 VH	85	/* wkup_m3 */
	86	static struct omap_hwmod am33xx_wkup_m3_hwmod = {
	87	.name = "wkup_m3",
	88	.class = &am33xx_wkup_m3_hwmod_class,
	89	.clkdm_name = "l4_wkup_aon_clkdm",
092bda62 HG	90	/* Keep hardreset asserted */
092bda62 HG	91	.flags = HWMOD_INIT_NO_RESET \| HWMOD_NO_IDLEST,
a2cfc509 VH	92	.main_clk = "dpll_core_m4_div2_ck",
	93	.prcm = {
	94	.omap4 = {
	95	.clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
	96	.rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
3077fe69	97	.rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
a2cfc509 VH	98	.modulemode = MODULEMODE_SWCTRL,
	99	},
	100	},
	101	.rst_lines = am33xx_wkup_m3_resets,
	102	.rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
	103	};
	104
a2cfc509 VH	105	/*
	106	* 'adc/tsc' class
	107	* TouchScreen Controller (Anolog-To-Digital Converter)
	108	*/
	109	static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
	110	.rev_offs = 0x00,
	111	.sysc_offs = 0x10,
	112	.sysc_flags = SYSC_HAS_SIDLEMODE,
	113	.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART \|
	114	SIDLE_SMART_WKUP),
	115	.sysc_fields = &omap_hwmod_sysc_type2,
	116	};
	117
	118	static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
	119	.name = "adc_tsc",
	120	.sysc = &am33xx_adc_tsc_sysc,
	121	};
	122
a2cfc509 VH	123	static struct omap_hwmod am33xx_adc_tsc_hwmod = {
	124	.name = "adc_tsc",
	125	.class = &am33xx_adc_tsc_hwmod_class,
	126	.clkdm_name = "l4_wkup_clkdm",
a2cfc509 VH	127	.main_clk = "adc_tsc_fck",
	128	.prcm = {
	129	.omap4 = {
	130	.clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
	131	.modulemode = MODULEMODE_SWCTRL,
	132	},
	133	},
	134	};
	135
	136	/*
	137	* Modules omap_hwmod structures
	138	*
	139	* The following IPs are excluded for the moment because:
	140	* - They do not need an explicit SW control using omap_hwmod API.
	141	* - They still need to be validated with the driver
	142	* properly adapted to omap_hwmod / omap_device
	143	*
	144	* - cEFUSE (doesn't fall under any ocp_if)
	145	* - clkdiv32k
a2cfc509	146	* - ocp watch point
a2cfc509 VH	147	*/
	148	#if 0
	149	/*
	150	* 'cefuse' class
	151	*/
	152	static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
	153	.name = "cefuse",
	154	};
	155
	156	static struct omap_hwmod am33xx_cefuse_hwmod = {
	157	.name = "cefuse",
	158	.class = &am33xx_cefuse_hwmod_class,
	159	.clkdm_name = "l4_cefuse_clkdm",
	160	.main_clk = "cefuse_fck",
	161	.prcm = {
	162	.omap4 = {
	163	.clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
	164	.modulemode = MODULEMODE_SWCTRL,
	165	},
	166	},
	167	};
	168
	169	/*
	170	* 'clkdiv32k' class
	171	*/
	172	static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
	173	.name = "clkdiv32k",
	174	};
	175
	176	static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
	177	.name = "clkdiv32k",
	178	.class = &am33xx_clkdiv32k_hwmod_class,
	179	.clkdm_name = "clk_24mhz_clkdm",
	180	.main_clk = "clkdiv32k_ick",
	181	.prcm = {
	182	.omap4 = {
	183	.clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
	184	.modulemode = MODULEMODE_SWCTRL,
	185	},
	186	},
	187	};
	188
a2cfc509 VH	189	/* ocpwp */
	190	static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
	191	.name = "ocpwp",
	192	};
	193
	194	static struct omap_hwmod am33xx_ocpwp_hwmod = {
	195	.name = "ocpwp",
	196	.class = &am33xx_ocpwp_hwmod_class,
	197	.clkdm_name = "l4ls_clkdm",
	198	.main_clk = "l4ls_gclk",
	199	.prcm = {
	200	.omap4 = {
	201	.clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
	202	.modulemode = MODULEMODE_SWCTRL,
	203	},
	204	},
	205	};
1cb804b9	206	#endif
a2cfc509	207
1721c702 VH	208	/*
	209	* 'debugss' class
	210	* debug sub system
	211	*/
	212	static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
	213	{ .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
	214	{ .role = "dbg_clka", .clk = "dbg_clka_ck" },
	215	};
	216
	217	static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
	218	.name = "debugss",
	219	};
	220
	221	static struct omap_hwmod am33xx_debugss_hwmod = {
	222	.name = "debugss",
	223	.class = &am33xx_debugss_hwmod_class,
	224	.clkdm_name = "l3_aon_clkdm",
	225	.main_clk = "trace_clk_div_ck",
	226	.prcm = {
	227	.omap4 = {
	228	.clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
	229	.modulemode = MODULEMODE_SWCTRL,
	230	},
	231	},
	232	.opt_clks = debugss_opt_clks,
	233	.opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks),
	234	};
	235
a2cfc509 VH	236	static struct omap_hwmod am33xx_control_hwmod = {
	237	.name = "control",
	238	.class = &am33xx_control_hwmod_class,
	239	.clkdm_name = "l4_wkup_clkdm",
b2eb0002	240	.flags = HWMOD_INIT_NO_IDLE,
a2cfc509 VH	241	.main_clk = "dpll_core_m4_div2_ck",
	242	.prcm = {
	243	.omap4 = {
	244	.clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
	245	.modulemode = MODULEMODE_SWCTRL,
	246	},
	247	},
	248	};
	249
26649467 AM	250	/* gpio0 */
	251	static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
	252	{ .role = "dbclk", .clk = "gpio0_dbclk" },
a2cfc509 VH	253	};
a2cfc509 VH	254
26649467 AM	255	static struct omap_hwmod am33xx_gpio0_hwmod = {
	256	.name = "gpio1",
	257	.class = &am33xx_gpio_hwmod_class,
	258	.clkdm_name = "l4_wkup_clkdm",
	259	.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	260	.main_clk = "dpll_core_m4_div2_ck",
a2cfc509 VH	261	.prcm = {
a2cfc509 VH	262	.omap4 = {
26649467	263	.clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
a2cfc509 VH	264	.modulemode = MODULEMODE_SWCTRL,
	265	},
	266	},
26649467 AM	267	.opt_clks = gpio0_opt_clks,
	268	.opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
	269	.dev_attr = &gpio_dev_attr,
a2cfc509 VH	270	};
a2cfc509 VH	271
26649467 AM	272	/* lcdc */
	273	static struct omap_hwmod_class_sysconfig lcdc_sysc = {
	274	.rev_offs = 0x0,
	275	.sysc_offs = 0x54,
	276	.sysc_flags = (SYSC_HAS_SIDLEMODE \| SYSC_HAS_MIDLEMODE),
a2cfc509	277	.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
26649467	278	.sysc_fields = &omap_hwmod_sysc_type2,
a2cfc509 VH	279	};
a2cfc509 VH	280
26649467 AM	281	static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
	282	.name = "lcdc",
	283	.sysc = &lcdc_sysc,
a2cfc509 VH	284	};
a2cfc509 VH	285
26649467 AM	286	static struct omap_hwmod am33xx_lcdc_hwmod = {
	287	.name = "lcdc",
	288	.class = &am33xx_lcdc_hwmod_class,
	289	.clkdm_name = "lcdc_clkdm",
	290	.flags = HWMOD_SWSUP_SIDLE \| HWMOD_SWSUP_MSTANDBY,
	291	.main_clk = "lcd_gclk",
a2cfc509 VH	292	.prcm = {
a2cfc509 VH	293	.omap4 = {
26649467	294	.clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
a2cfc509 VH	295	.modulemode = MODULEMODE_SWCTRL,
	296	},
	297	},
	298	};
	299
26649467 AM	300	/*
	301	* 'usb_otg' class
	302	* high-speed on-the-go universal serial bus (usb_otg) controller
	303	*/
	304	static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
a2cfc509	305	.rev_offs = 0x0,
26649467	306	.sysc_offs = 0x10,
a2cfc509 VH	307	.sysc_flags = (SYSC_HAS_SIDLEMODE \| SYSC_HAS_MIDLEMODE),
a2cfc509 VH	308	.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART \|
26649467	309	MSTANDBY_FORCE \| MSTANDBY_NO \| MSTANDBY_SMART),
a2cfc509 VH	310	.sysc_fields = &omap_hwmod_sysc_type2,
	311	};
	312
26649467 AM	313	static struct omap_hwmod_class am33xx_usbotg_class = {
	314	.name = "usbotg",
	315	.sysc = &am33xx_usbhsotg_sysc,
a2cfc509 VH	316	};
a2cfc509 VH	317
26649467 AM	318	static struct omap_hwmod am33xx_usbss_hwmod = {
	319	.name = "usb_otg_hs",
	320	.class = &am33xx_usbotg_class,
	321	.clkdm_name = "l3s_clkdm",
	322	.flags = HWMOD_SWSUP_SIDLE \| HWMOD_SWSUP_MSTANDBY,
	323	.main_clk = "usbotg_fck",
a2cfc509 VH	324	.prcm = {
a2cfc509 VH	325	.omap4 = {
26649467	326	.clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
a2cfc509 VH	327	.modulemode = MODULEMODE_SWCTRL,
	328	},
	329	},
	330	};
	331
bee76659	332
26649467 AM	333	/*
	334	* Interfaces
	335	*/
a2cfc509	336
26649467	337	static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
a2cfc509	338	{
26649467 AM	339	.pa_start = 0x4c000000,
	340	.pa_end = 0x4c000fff,
	341	.flags = ADDR_TYPE_RT
a2cfc509 VH	342	},
	343	{ }
	344	};
26649467 AM	345	/* l3 main -> emif */
	346	static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
	347	.master = &am33xx_l3_main_hwmod,
	348	.slave = &am33xx_emif_hwmod,
	349	.clk = "dpll_core_m4_ck",
	350	.addr = am33xx_emif_addrs,
	351	.user = OCP_USER_MPU \| OCP_USER_SDMA,
a2cfc509 VH	352	};
a2cfc509 VH	353
26649467 AM	354	/* l3 main -> l4 hs */
	355	static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
	356	.master = &am33xx_l3_main_hwmod,
	357	.slave = &am33xx_l4_hs_hwmod,
	358	.clk = "l3s_gclk",
	359	.user = OCP_USER_MPU \| OCP_USER_SDMA,
a2cfc509 VH	360	};
a2cfc509 VH	361
26649467 AM	362	/* wkup m3 -> l4 wkup */
	363	static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
	364	.master = &am33xx_wkup_m3_hwmod,
	365	.slave = &am33xx_l4_wkup_hwmod,
	366	.clk = "dpll_core_m4_div2_ck",
	367	.user = OCP_USER_MPU \| OCP_USER_SDMA,
a2cfc509 VH	368	};
a2cfc509 VH	369
26649467 AM	370	/* l4 wkup -> wkup m3 */
	371	static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
	372	.master = &am33xx_l4_wkup_hwmod,
	373	.slave = &am33xx_wkup_m3_hwmod,
	374	.clk = "dpll_core_m4_div2_ck",
	375	.user = OCP_USER_MPU \| OCP_USER_SDMA,
a2cfc509 VH	376	};
a2cfc509 VH	377
26649467 AM	378	/* l4 hs -> pru-icss */
	379	static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
	380	.master = &am33xx_l4_hs_hwmod,
	381	.slave = &am33xx_pruss_hwmod,
a2cfc509	382	.clk = "dpll_core_m4_ck",
26649467	383	.user = OCP_USER_MPU \| OCP_USER_SDMA,
a2cfc509 VH	384	};
a2cfc509 VH	385
26649467 AM	386	/* l3_main -> debugss */
26649467 AM	387	static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = {
a2cfc509	388	{
26649467 AM	389	.pa_start = 0x4b000000,
26649467 AM	390	.pa_end = 0x4b000000 + SZ_16M - 1,
a2cfc509 VH	391	.flags = ADDR_TYPE_RT
	392	},
	393	{ }
	394	};
	395
26649467 AM	396	static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
	397	.master = &am33xx_l3_main_hwmod,
	398	.slave = &am33xx_debugss_hwmod,
	399	.clk = "dpll_core_m4_ck",
	400	.addr = am33xx_debugss_addrs,
a2cfc509 VH	401	.user = OCP_USER_MPU,
	402	};
	403
26649467 AM	404	/* l4 wkup -> smartreflex0 */
	405	static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
	406	.master = &am33xx_l4_wkup_hwmod,
	407	.slave = &am33xx_smartreflex0_hwmod,
	408	.clk = "dpll_core_m4_div2_ck",
a2cfc509 VH	409	.user = OCP_USER_MPU,
	410	};
	411
26649467 AM	412	/* l4 wkup -> smartreflex1 */
	413	static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
	414	.master = &am33xx_l4_wkup_hwmod,
	415	.slave = &am33xx_smartreflex1_hwmod,
	416	.clk = "dpll_core_m4_div2_ck",
a2cfc509 VH	417	.user = OCP_USER_MPU,
	418	};
	419
26649467 AM	420	/* l4 wkup -> control */
	421	static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
	422	.master = &am33xx_l4_wkup_hwmod,
	423	.slave = &am33xx_control_hwmod,
	424	.clk = "dpll_core_m4_div2_ck",
a2cfc509 VH	425	.user = OCP_USER_MPU,
	426	};
	427
26649467 AM	428	/* L4 WKUP -> I2C1 */
	429	static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
	430	.master = &am33xx_l4_wkup_hwmod,
	431	.slave = &am33xx_i2c1_hwmod,
	432	.clk = "dpll_core_m4_div2_ck",
a2cfc509 VH	433	.user = OCP_USER_MPU,
	434	};
	435
26649467 AM	436	/* L4 WKUP -> GPIO1 */
	437	static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
	438	.master = &am33xx_l4_wkup_hwmod,
	439	.slave = &am33xx_gpio0_hwmod,
	440	.clk = "dpll_core_m4_div2_ck",
	441	.user = OCP_USER_MPU \| OCP_USER_SDMA,
a2cfc509 VH	442	};
a2cfc509 VH	443
26649467 AM	444	/* L4 WKUP -> ADC_TSC */
26649467 AM	445	static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
a2cfc509	446	{
26649467 AM	447	.pa_start = 0x44E0D000,
	448	.pa_end = 0x44E0D000 + SZ_8K - 1,
	449	.flags = ADDR_TYPE_RT
a2cfc509 VH	450	},
	451	{ }
	452	};
	453
26649467	454	static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
a2cfc509	455	.master = &am33xx_l4_wkup_hwmod,
26649467	456	.slave = &am33xx_adc_tsc_hwmod,
a2cfc509	457	.clk = "dpll_core_m4_div2_ck",
26649467	458	.addr = am33xx_adc_tsc_addrs,
a2cfc509 VH	459	.user = OCP_USER_MPU,
	460	};
	461
26649467 AM	462	static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
	463	.master = &am33xx_l4_hs_hwmod,
	464	.slave = &am33xx_cpgmac0_hwmod,
	465	.clk = "cpsw_125mhz_gclk",
a2cfc509 VH	466	.user = OCP_USER_MPU,
	467	};
	468
26649467	469	static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
a2cfc509	470	{
26649467 AM	471	.pa_start = 0x4830E000,
26649467 AM	472	.pa_end = 0x4830E000 + SZ_8K - 1,
a2cfc509 VH	473	.flags = ADDR_TYPE_RT,
	474	},
	475	{ }
	476	};
	477
26649467	478	static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
a2cfc509	479	.master = &am33xx_l3_main_hwmod,
26649467 AM	480	.slave = &am33xx_lcdc_hwmod,
	481	.clk = "dpll_core_m4_ck",
	482	.addr = am33xx_lcdc_addr_space,
a2cfc509 VH	483	.user = OCP_USER_MPU,
	484	};
	485
26649467 AM	486	/* l4 wkup -> timer1 */
	487	static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
	488	.master = &am33xx_l4_wkup_hwmod,
	489	.slave = &am33xx_timer1_hwmod,
	490	.clk = "dpll_core_m4_div2_ck",
a2cfc509 VH	491	.user = OCP_USER_MPU,
	492	};
	493
	494	/* l4 wkup -> uart1 */
a2cfc509 VH	495	static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
	496	.master = &am33xx_l4_wkup_hwmod,
	497	.slave = &am33xx_uart1_hwmod,
	498	.clk = "dpll_core_m4_div2_ck",
a2cfc509 VH	499	.user = OCP_USER_MPU,
	500	};
	501
a2cfc509	502	/* l4 wkup -> wd_timer1 */
a2cfc509 VH	503	static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
	504	.master = &am33xx_l4_wkup_hwmod,
	505	.slave = &am33xx_wd_timer1_hwmod,
	506	.clk = "dpll_core_m4_div2_ck",
a2cfc509 VH	507	.user = OCP_USER_MPU,
	508	};
	509
	510	/* usbss */
	511	/* l3 s -> USBSS interface */
a2cfc509 VH	512	static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
	513	.master = &am33xx_l3_s_hwmod,
	514	.slave = &am33xx_usbss_hwmod,
	515	.clk = "l3s_gclk",
a2cfc509 VH	516	.user = OCP_USER_MPU,
	517	.flags = OCPIF_SWSUP_IDLE,
	518	};
	519
ace1e3ec LV	520	/* rng */
	521	static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
	522	.rev_offs = 0x1fe0,
	523	.sysc_offs = 0x1fe4,
	524	.sysc_flags = SYSC_HAS_AUTOIDLE \| SYSC_HAS_SIDLEMODE,
	525	.idlemodes = SIDLE_FORCE \| SIDLE_NO,
	526	.sysc_fields = &omap_hwmod_sysc_type1,
	527	};
	528
	529	static struct omap_hwmod_class am33xx_rng_hwmod_class = {
	530	.name = "rng",
	531	.sysc = &am33xx_rng_sysc,
	532	};
	533
	534	static struct omap_hwmod am33xx_rng_hwmod = {
	535	.name = "rng",
	536	.class = &am33xx_rng_hwmod_class,
	537	.clkdm_name = "l4ls_clkdm",
	538	.flags = HWMOD_SWSUP_SIDLE,
	539	.main_clk = "rng_fck",
	540	.prcm = {
	541	.omap4 = {
	542	.clkctrl_offs = AM33XX_CM_PER_RNG_CLKCTRL_OFFSET,
	543	.modulemode = MODULEMODE_SWCTRL,
	544	},
	545	},
	546	};
	547
	548	static struct omap_hwmod_ocp_if am33xx_l4_per__rng = {
	549	.master = &am33xx_l4_ls_hwmod,
	550	.slave = &am33xx_rng_hwmod,
	551	.clk = "rng_fck",
	552	.user = OCP_USER_MPU,
	553	};
	554
a2cfc509	555	static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
a2cfc509 VH	556	&am33xx_l3_main__emif,
	557	&am33xx_mpu__l3_main,
	558	&am33xx_mpu__prcm,
	559	&am33xx_l3_s__l4_ls,
	560	&am33xx_l3_s__l4_wkup,
a2cfc509 VH	561	&am33xx_l3_main__l4_hs,
	562	&am33xx_l3_main__l3_s,
	563	&am33xx_l3_main__l3_instr,
	564	&am33xx_l3_main__gfx,
	565	&am33xx_l3_s__l3_main,
	566	&am33xx_pruss__l3_main,
	567	&am33xx_wkup_m3__l4_wkup,
	568	&am33xx_gfx__l3_main,
1721c702	569	&am33xx_l3_main__debugss,
a2cfc509 VH	570	&am33xx_l4_wkup__wkup_m3,
	571	&am33xx_l4_wkup__control,
	572	&am33xx_l4_wkup__smartreflex0,
	573	&am33xx_l4_wkup__smartreflex1,
	574	&am33xx_l4_wkup__uart1,
	575	&am33xx_l4_wkup__timer1,
	576	&am33xx_l4_wkup__rtc,
	577	&am33xx_l4_wkup__i2c1,
	578	&am33xx_l4_wkup__gpio0,
	579	&am33xx_l4_wkup__adc_tsc,
	580	&am33xx_l4_wkup__wd_timer1,
	581	&am33xx_l4_hs__pruss,
	582	&am33xx_l4_per__dcan0,
	583	&am33xx_l4_per__dcan1,
	584	&am33xx_l4_per__gpio1,
	585	&am33xx_l4_per__gpio2,
	586	&am33xx_l4_per__gpio3,
	587	&am33xx_l4_per__i2c2,
	588	&am33xx_l4_per__i2c3,
	589	&am33xx_l4_per__mailbox,
	590	&am33xx_l4_ls__mcasp0,
a2cfc509	591	&am33xx_l4_ls__mcasp1,
a2cfc509 VH	592	&am33xx_l4_ls__mmc0,
	593	&am33xx_l4_ls__mmc1,
	594	&am33xx_l3_s__mmc2,
	595	&am33xx_l4_ls__timer2,
	596	&am33xx_l4_ls__timer3,
	597	&am33xx_l4_ls__timer4,
	598	&am33xx_l4_ls__timer5,
	599	&am33xx_l4_ls__timer6,
	600	&am33xx_l4_ls__timer7,
	601	&am33xx_l3_main__tpcc,
	602	&am33xx_l4_ls__uart2,
	603	&am33xx_l4_ls__uart3,
	604	&am33xx_l4_ls__uart4,
	605	&am33xx_l4_ls__uart5,
	606	&am33xx_l4_ls__uart6,
	607	&am33xx_l4_ls__spinlock,
	608	&am33xx_l4_ls__elm,
9652d19a PA	609	&am33xx_l4_ls__epwmss0,
	610	&am33xx_epwmss0__ecap0,
	611	&am33xx_epwmss0__eqep0,
	612	&am33xx_epwmss0__ehrpwm0,
	613	&am33xx_l4_ls__epwmss1,
	614	&am33xx_epwmss1__ecap1,
	615	&am33xx_epwmss1__eqep1,
	616	&am33xx_epwmss1__ehrpwm1,
	617	&am33xx_l4_ls__epwmss2,
	618	&am33xx_epwmss2__ecap2,
	619	&am33xx_epwmss2__eqep2,
	620	&am33xx_epwmss2__ehrpwm2,
a2cfc509 VH	621	&am33xx_l3_s__gpmc,
	622	&am33xx_l3_main__lcdc,
	623	&am33xx_l4_ls__mcspi0,
	624	&am33xx_l4_ls__mcspi1,
	625	&am33xx_l3_main__tptc0,
	626	&am33xx_l3_main__tptc1,
	627	&am33xx_l3_main__tptc2,
ca903b6f	628	&am33xx_l3_main__ocmc,
a2cfc509 VH	629	&am33xx_l3_s__usbss,
a2cfc509 VH	630	&am33xx_l4_hs__cpgmac0,
70384a6a	631	&am33xx_cpgmac0__mdio,
aec94bf5	632	&am33xx_l3_main__sha0,
1cb804b9	633	&am33xx_l3_main__aes0,
ace1e3ec	634	&am33xx_l4_per__rng,
a2cfc509 VH	635	NULL,
	636	};
	637
	638	int __init am33xx_hwmod_init(void)
	639	{
1c7e224d	640	omap_hwmod_am33xx_reg();
a2cfc509 VH	641	omap_hwmod_init();
	642	return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
	643	}