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a2cfc509 VH |
1 | /* |
2 | * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips | |
3 | * | |
4 | * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * This file is automatically generated from the AM33XX hardware databases. | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation version 2. | |
10 | * | |
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
12 | * kind, whether express or implied; without even the implied warranty | |
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
3a8761c0 TL |
17 | #include <linux/i2c-omap.h> |
18 | ||
2a296c8f | 19 | #include "omap_hwmod.h" |
11964f53 | 20 | #include <linux/platform_data/gpio-omap.h> |
aa817b2e | 21 | #include <linux/platform_data/spi-omap2-mcspi.h> |
a2cfc509 VH |
22 | |
23 | #include "omap_hwmod_common_data.h" | |
24 | ||
25 | #include "control.h" | |
26 | #include "cm33xx.h" | |
27 | #include "prm33xx.h" | |
28 | #include "prm-regbits-33xx.h" | |
3a8761c0 | 29 | #include "i2c.h" |
68f39e74 | 30 | #include "mmc.h" |
05cf03b6 | 31 | #include "wd_timer.h" |
a2cfc509 | 32 | |
a2cfc509 VH |
33 | /* |
34 | * IP blocks | |
35 | */ | |
36 | ||
a2cfc509 VH |
37 | /* |
38 | * 'emif' class | |
39 | * instance(s): emif | |
40 | */ | |
41 | static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = { | |
42 | .rev_offs = 0x0000, | |
43 | }; | |
44 | ||
45 | static struct omap_hwmod_class am33xx_emif_hwmod_class = { | |
46 | .name = "emif", | |
47 | .sysc = &am33xx_emif_sysc, | |
48 | }; | |
49 | ||
a2cfc509 VH |
50 | /* emif */ |
51 | static struct omap_hwmod am33xx_emif_hwmod = { | |
52 | .name = "emif", | |
53 | .class = &am33xx_emif_hwmod_class, | |
54 | .clkdm_name = "l3_clkdm", | |
55 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
a2cfc509 VH |
56 | .main_clk = "dpll_ddr_m2_div2_ck", |
57 | .prcm = { | |
58 | .omap4 = { | |
59 | .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET, | |
60 | .modulemode = MODULEMODE_SWCTRL, | |
61 | }, | |
62 | }, | |
63 | }; | |
64 | ||
65 | /* | |
66 | * 'l3' class | |
67 | * instance(s): l3_main, l3_s, l3_instr | |
68 | */ | |
69 | static struct omap_hwmod_class am33xx_l3_hwmod_class = { | |
70 | .name = "l3", | |
71 | }; | |
72 | ||
a2cfc509 VH |
73 | static struct omap_hwmod am33xx_l3_main_hwmod = { |
74 | .name = "l3_main", | |
75 | .class = &am33xx_l3_hwmod_class, | |
76 | .clkdm_name = "l3_clkdm", | |
77 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
a2cfc509 VH |
78 | .main_clk = "l3_gclk", |
79 | .prcm = { | |
80 | .omap4 = { | |
81 | .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET, | |
82 | .modulemode = MODULEMODE_SWCTRL, | |
83 | }, | |
84 | }, | |
85 | }; | |
86 | ||
87 | /* l3_s */ | |
88 | static struct omap_hwmod am33xx_l3_s_hwmod = { | |
89 | .name = "l3_s", | |
90 | .class = &am33xx_l3_hwmod_class, | |
91 | .clkdm_name = "l3s_clkdm", | |
92 | }; | |
93 | ||
94 | /* l3_instr */ | |
95 | static struct omap_hwmod am33xx_l3_instr_hwmod = { | |
96 | .name = "l3_instr", | |
97 | .class = &am33xx_l3_hwmod_class, | |
98 | .clkdm_name = "l3_clkdm", | |
99 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
100 | .main_clk = "l3_gclk", | |
101 | .prcm = { | |
102 | .omap4 = { | |
103 | .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET, | |
104 | .modulemode = MODULEMODE_SWCTRL, | |
105 | }, | |
106 | }, | |
107 | }; | |
108 | ||
109 | /* | |
110 | * 'l4' class | |
111 | * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw | |
112 | */ | |
113 | static struct omap_hwmod_class am33xx_l4_hwmod_class = { | |
114 | .name = "l4", | |
115 | }; | |
116 | ||
117 | /* l4_ls */ | |
118 | static struct omap_hwmod am33xx_l4_ls_hwmod = { | |
119 | .name = "l4_ls", | |
120 | .class = &am33xx_l4_hwmod_class, | |
121 | .clkdm_name = "l4ls_clkdm", | |
122 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
123 | .main_clk = "l4ls_gclk", | |
124 | .prcm = { | |
125 | .omap4 = { | |
126 | .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET, | |
127 | .modulemode = MODULEMODE_SWCTRL, | |
128 | }, | |
129 | }, | |
130 | }; | |
131 | ||
132 | /* l4_hs */ | |
133 | static struct omap_hwmod am33xx_l4_hs_hwmod = { | |
134 | .name = "l4_hs", | |
135 | .class = &am33xx_l4_hwmod_class, | |
136 | .clkdm_name = "l4hs_clkdm", | |
137 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
138 | .main_clk = "l4hs_gclk", | |
139 | .prcm = { | |
140 | .omap4 = { | |
141 | .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET, | |
142 | .modulemode = MODULEMODE_SWCTRL, | |
143 | }, | |
144 | }, | |
145 | }; | |
146 | ||
147 | ||
148 | /* l4_wkup */ | |
149 | static struct omap_hwmod am33xx_l4_wkup_hwmod = { | |
150 | .name = "l4_wkup", | |
151 | .class = &am33xx_l4_hwmod_class, | |
152 | .clkdm_name = "l4_wkup_clkdm", | |
153 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
154 | .prcm = { | |
155 | .omap4 = { | |
156 | .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, | |
157 | .modulemode = MODULEMODE_SWCTRL, | |
158 | }, | |
159 | }, | |
160 | }; | |
161 | ||
a2cfc509 VH |
162 | /* |
163 | * 'mpu' class | |
164 | */ | |
165 | static struct omap_hwmod_class am33xx_mpu_hwmod_class = { | |
166 | .name = "mpu", | |
167 | }; | |
168 | ||
a2cfc509 VH |
169 | static struct omap_hwmod am33xx_mpu_hwmod = { |
170 | .name = "mpu", | |
171 | .class = &am33xx_mpu_hwmod_class, | |
172 | .clkdm_name = "mpu_clkdm", | |
173 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
a2cfc509 VH |
174 | .main_clk = "dpll_mpu_m2_ck", |
175 | .prcm = { | |
176 | .omap4 = { | |
177 | .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET, | |
178 | .modulemode = MODULEMODE_SWCTRL, | |
179 | }, | |
180 | }, | |
181 | }; | |
182 | ||
183 | /* | |
184 | * 'wakeup m3' class | |
185 | * Wakeup controller sub-system under wakeup domain | |
186 | */ | |
187 | static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = { | |
188 | .name = "wkup_m3", | |
189 | }; | |
190 | ||
191 | static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = { | |
192 | { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, | |
193 | }; | |
194 | ||
a2cfc509 VH |
195 | /* wkup_m3 */ |
196 | static struct omap_hwmod am33xx_wkup_m3_hwmod = { | |
197 | .name = "wkup_m3", | |
198 | .class = &am33xx_wkup_m3_hwmod_class, | |
199 | .clkdm_name = "l4_wkup_aon_clkdm", | |
092bda62 HG |
200 | /* Keep hardreset asserted */ |
201 | .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST, | |
a2cfc509 VH |
202 | .main_clk = "dpll_core_m4_div2_ck", |
203 | .prcm = { | |
204 | .omap4 = { | |
205 | .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET, | |
206 | .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET, | |
3077fe69 | 207 | .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET, |
a2cfc509 VH |
208 | .modulemode = MODULEMODE_SWCTRL, |
209 | }, | |
210 | }, | |
211 | .rst_lines = am33xx_wkup_m3_resets, | |
212 | .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets), | |
213 | }; | |
214 | ||
215 | /* | |
216 | * 'pru-icss' class | |
217 | * Programmable Real-Time Unit and Industrial Communication Subsystem | |
218 | */ | |
219 | static struct omap_hwmod_class am33xx_pruss_hwmod_class = { | |
220 | .name = "pruss", | |
221 | }; | |
222 | ||
223 | static struct omap_hwmod_rst_info am33xx_pruss_resets[] = { | |
224 | { .name = "pruss", .rst_shift = 1 }, | |
225 | }; | |
226 | ||
a2cfc509 VH |
227 | /* pru-icss */ |
228 | /* Pseudo hwmod for reset control purpose only */ | |
229 | static struct omap_hwmod am33xx_pruss_hwmod = { | |
230 | .name = "pruss", | |
231 | .class = &am33xx_pruss_hwmod_class, | |
232 | .clkdm_name = "pruss_ocp_clkdm", | |
a2cfc509 VH |
233 | .main_clk = "pruss_ocp_gclk", |
234 | .prcm = { | |
235 | .omap4 = { | |
236 | .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET, | |
237 | .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET, | |
238 | .modulemode = MODULEMODE_SWCTRL, | |
239 | }, | |
240 | }, | |
241 | .rst_lines = am33xx_pruss_resets, | |
242 | .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets), | |
243 | }; | |
244 | ||
245 | /* gfx */ | |
246 | /* Pseudo hwmod for reset control purpose only */ | |
247 | static struct omap_hwmod_class am33xx_gfx_hwmod_class = { | |
248 | .name = "gfx", | |
249 | }; | |
250 | ||
251 | static struct omap_hwmod_rst_info am33xx_gfx_resets[] = { | |
27c7004a | 252 | { .name = "gfx", .rst_shift = 0, .st_shift = 0}, |
a2cfc509 VH |
253 | }; |
254 | ||
a2cfc509 VH |
255 | static struct omap_hwmod am33xx_gfx_hwmod = { |
256 | .name = "gfx", | |
257 | .class = &am33xx_gfx_hwmod_class, | |
258 | .clkdm_name = "gfx_l3_clkdm", | |
a2cfc509 VH |
259 | .main_clk = "gfx_fck_div_ck", |
260 | .prcm = { | |
261 | .omap4 = { | |
262 | .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET, | |
263 | .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET, | |
27c7004a | 264 | .rstst_offs = AM33XX_RM_GFX_RSTST_OFFSET, |
a2cfc509 VH |
265 | .modulemode = MODULEMODE_SWCTRL, |
266 | }, | |
267 | }, | |
268 | .rst_lines = am33xx_gfx_resets, | |
269 | .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets), | |
270 | }; | |
271 | ||
272 | /* | |
273 | * 'prcm' class | |
274 | * power and reset manager (whole prcm infrastructure) | |
275 | */ | |
276 | static struct omap_hwmod_class am33xx_prcm_hwmod_class = { | |
277 | .name = "prcm", | |
278 | }; | |
279 | ||
280 | /* prcm */ | |
281 | static struct omap_hwmod am33xx_prcm_hwmod = { | |
282 | .name = "prcm", | |
283 | .class = &am33xx_prcm_hwmod_class, | |
284 | .clkdm_name = "l4_wkup_clkdm", | |
285 | }; | |
286 | ||
287 | /* | |
288 | * 'adc/tsc' class | |
289 | * TouchScreen Controller (Anolog-To-Digital Converter) | |
290 | */ | |
291 | static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = { | |
292 | .rev_offs = 0x00, | |
293 | .sysc_offs = 0x10, | |
294 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
295 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
296 | SIDLE_SMART_WKUP), | |
297 | .sysc_fields = &omap_hwmod_sysc_type2, | |
298 | }; | |
299 | ||
300 | static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = { | |
301 | .name = "adc_tsc", | |
302 | .sysc = &am33xx_adc_tsc_sysc, | |
303 | }; | |
304 | ||
a2cfc509 VH |
305 | static struct omap_hwmod am33xx_adc_tsc_hwmod = { |
306 | .name = "adc_tsc", | |
307 | .class = &am33xx_adc_tsc_hwmod_class, | |
308 | .clkdm_name = "l4_wkup_clkdm", | |
a2cfc509 VH |
309 | .main_clk = "adc_tsc_fck", |
310 | .prcm = { | |
311 | .omap4 = { | |
312 | .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET, | |
313 | .modulemode = MODULEMODE_SWCTRL, | |
314 | }, | |
315 | }, | |
316 | }; | |
317 | ||
318 | /* | |
319 | * Modules omap_hwmod structures | |
320 | * | |
321 | * The following IPs are excluded for the moment because: | |
322 | * - They do not need an explicit SW control using omap_hwmod API. | |
323 | * - They still need to be validated with the driver | |
324 | * properly adapted to omap_hwmod / omap_device | |
325 | * | |
326 | * - cEFUSE (doesn't fall under any ocp_if) | |
327 | * - clkdiv32k | |
328 | * - debugss | |
a2cfc509 | 329 | * - ocp watch point |
a2cfc509 VH |
330 | */ |
331 | #if 0 | |
332 | /* | |
333 | * 'cefuse' class | |
334 | */ | |
335 | static struct omap_hwmod_class am33xx_cefuse_hwmod_class = { | |
336 | .name = "cefuse", | |
337 | }; | |
338 | ||
339 | static struct omap_hwmod am33xx_cefuse_hwmod = { | |
340 | .name = "cefuse", | |
341 | .class = &am33xx_cefuse_hwmod_class, | |
342 | .clkdm_name = "l4_cefuse_clkdm", | |
343 | .main_clk = "cefuse_fck", | |
344 | .prcm = { | |
345 | .omap4 = { | |
346 | .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET, | |
347 | .modulemode = MODULEMODE_SWCTRL, | |
348 | }, | |
349 | }, | |
350 | }; | |
351 | ||
352 | /* | |
353 | * 'clkdiv32k' class | |
354 | */ | |
355 | static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = { | |
356 | .name = "clkdiv32k", | |
357 | }; | |
358 | ||
359 | static struct omap_hwmod am33xx_clkdiv32k_hwmod = { | |
360 | .name = "clkdiv32k", | |
361 | .class = &am33xx_clkdiv32k_hwmod_class, | |
362 | .clkdm_name = "clk_24mhz_clkdm", | |
363 | .main_clk = "clkdiv32k_ick", | |
364 | .prcm = { | |
365 | .omap4 = { | |
366 | .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET, | |
367 | .modulemode = MODULEMODE_SWCTRL, | |
368 | }, | |
369 | }, | |
370 | }; | |
371 | ||
372 | /* | |
373 | * 'debugss' class | |
374 | * debug sub system | |
375 | */ | |
376 | static struct omap_hwmod_class am33xx_debugss_hwmod_class = { | |
377 | .name = "debugss", | |
378 | }; | |
379 | ||
380 | static struct omap_hwmod am33xx_debugss_hwmod = { | |
381 | .name = "debugss", | |
382 | .class = &am33xx_debugss_hwmod_class, | |
383 | .clkdm_name = "l3_aon_clkdm", | |
384 | .main_clk = "debugss_ick", | |
385 | .prcm = { | |
386 | .omap4 = { | |
387 | .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET, | |
388 | .modulemode = MODULEMODE_SWCTRL, | |
389 | }, | |
390 | }, | |
391 | }; | |
392 | ||
a2cfc509 VH |
393 | /* ocpwp */ |
394 | static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = { | |
395 | .name = "ocpwp", | |
396 | }; | |
397 | ||
398 | static struct omap_hwmod am33xx_ocpwp_hwmod = { | |
399 | .name = "ocpwp", | |
400 | .class = &am33xx_ocpwp_hwmod_class, | |
401 | .clkdm_name = "l4ls_clkdm", | |
402 | .main_clk = "l4ls_gclk", | |
403 | .prcm = { | |
404 | .omap4 = { | |
405 | .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET, | |
406 | .modulemode = MODULEMODE_SWCTRL, | |
407 | }, | |
408 | }, | |
409 | }; | |
1cb804b9 | 410 | #endif |
a2cfc509 VH |
411 | |
412 | /* | |
1cb804b9 | 413 | * 'aes0' class |
a2cfc509 | 414 | */ |
1cb804b9 MG |
415 | static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = { |
416 | .rev_offs = 0x80, | |
417 | .sysc_offs = 0x84, | |
418 | .syss_offs = 0x88, | |
419 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
420 | }; | |
421 | ||
422 | static struct omap_hwmod_class am33xx_aes0_hwmod_class = { | |
423 | .name = "aes0", | |
424 | .sysc = &am33xx_aes0_sysc, | |
a2cfc509 VH |
425 | }; |
426 | ||
a2cfc509 | 427 | static struct omap_hwmod am33xx_aes0_hwmod = { |
1cb804b9 MG |
428 | .name = "aes", |
429 | .class = &am33xx_aes0_hwmod_class, | |
a2cfc509 | 430 | .clkdm_name = "l3_clkdm", |
1cb804b9 | 431 | .main_clk = "aes0_fck", |
a2cfc509 VH |
432 | .prcm = { |
433 | .omap4 = { | |
434 | .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET, | |
435 | .modulemode = MODULEMODE_SWCTRL, | |
436 | }, | |
437 | }, | |
438 | }; | |
439 | ||
aec94bf5 MG |
440 | /* sha0 HIB2 (the 'P' (public) device) */ |
441 | static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = { | |
442 | .rev_offs = 0x100, | |
443 | .sysc_offs = 0x110, | |
444 | .syss_offs = 0x114, | |
445 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
446 | }; | |
a2cfc509 | 447 | |
a2cfc509 VH |
448 | static struct omap_hwmod_class am33xx_sha0_hwmod_class = { |
449 | .name = "sha0", | |
aec94bf5 | 450 | .sysc = &am33xx_sha0_sysc, |
a2cfc509 VH |
451 | }; |
452 | ||
a2cfc509 | 453 | static struct omap_hwmod am33xx_sha0_hwmod = { |
aec94bf5 | 454 | .name = "sham", |
a2cfc509 VH |
455 | .class = &am33xx_sha0_hwmod_class, |
456 | .clkdm_name = "l3_clkdm", | |
a2cfc509 VH |
457 | .main_clk = "l3_gclk", |
458 | .prcm = { | |
459 | .omap4 = { | |
460 | .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET, | |
461 | .modulemode = MODULEMODE_SWCTRL, | |
462 | }, | |
463 | }, | |
464 | }; | |
465 | ||
ca903b6f VB |
466 | /* ocmcram */ |
467 | static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = { | |
468 | .name = "ocmcram", | |
469 | }; | |
470 | ||
471 | static struct omap_hwmod am33xx_ocmcram_hwmod = { | |
472 | .name = "ocmcram", | |
473 | .class = &am33xx_ocmcram_hwmod_class, | |
474 | .clkdm_name = "l3_clkdm", | |
475 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
476 | .main_clk = "l3_gclk", | |
477 | .prcm = { | |
478 | .omap4 = { | |
479 | .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET, | |
480 | .modulemode = MODULEMODE_SWCTRL, | |
481 | }, | |
482 | }, | |
483 | }; | |
484 | ||
a2cfc509 VH |
485 | /* 'smartreflex' class */ |
486 | static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { | |
487 | .name = "smartreflex", | |
488 | }; | |
489 | ||
490 | /* smartreflex0 */ | |
a2cfc509 VH |
491 | static struct omap_hwmod am33xx_smartreflex0_hwmod = { |
492 | .name = "smartreflex0", | |
493 | .class = &am33xx_smartreflex_hwmod_class, | |
494 | .clkdm_name = "l4_wkup_clkdm", | |
a2cfc509 VH |
495 | .main_clk = "smartreflex0_fck", |
496 | .prcm = { | |
497 | .omap4 = { | |
498 | .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET, | |
499 | .modulemode = MODULEMODE_SWCTRL, | |
500 | }, | |
501 | }, | |
502 | }; | |
503 | ||
504 | /* smartreflex1 */ | |
a2cfc509 VH |
505 | static struct omap_hwmod am33xx_smartreflex1_hwmod = { |
506 | .name = "smartreflex1", | |
507 | .class = &am33xx_smartreflex_hwmod_class, | |
508 | .clkdm_name = "l4_wkup_clkdm", | |
a2cfc509 VH |
509 | .main_clk = "smartreflex1_fck", |
510 | .prcm = { | |
511 | .omap4 = { | |
512 | .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET, | |
513 | .modulemode = MODULEMODE_SWCTRL, | |
514 | }, | |
515 | }, | |
516 | }; | |
517 | ||
518 | /* | |
519 | * 'control' module class | |
520 | */ | |
521 | static struct omap_hwmod_class am33xx_control_hwmod_class = { | |
522 | .name = "control", | |
523 | }; | |
524 | ||
a2cfc509 VH |
525 | static struct omap_hwmod am33xx_control_hwmod = { |
526 | .name = "control", | |
527 | .class = &am33xx_control_hwmod_class, | |
528 | .clkdm_name = "l4_wkup_clkdm", | |
529 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
a2cfc509 VH |
530 | .main_clk = "dpll_core_m4_div2_ck", |
531 | .prcm = { | |
532 | .omap4 = { | |
533 | .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET, | |
534 | .modulemode = MODULEMODE_SWCTRL, | |
535 | }, | |
536 | }, | |
537 | }; | |
538 | ||
539 | /* | |
540 | * 'cpgmac' class | |
541 | * cpsw/cpgmac sub system | |
542 | */ | |
543 | static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = { | |
544 | .rev_offs = 0x0, | |
545 | .sysc_offs = 0x8, | |
546 | .syss_offs = 0x4, | |
547 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | | |
548 | SYSS_HAS_RESET_STATUS), | |
549 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | | |
550 | MSTANDBY_NO), | |
551 | .sysc_fields = &omap_hwmod_sysc_type3, | |
552 | }; | |
553 | ||
554 | static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = { | |
555 | .name = "cpgmac0", | |
556 | .sysc = &am33xx_cpgmac_sysc, | |
557 | }; | |
558 | ||
a2cfc509 VH |
559 | static struct omap_hwmod am33xx_cpgmac0_hwmod = { |
560 | .name = "cpgmac0", | |
561 | .class = &am33xx_cpgmac0_hwmod_class, | |
562 | .clkdm_name = "cpsw_125mhz_clkdm", | |
70384a6a | 563 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), |
a2cfc509 VH |
564 | .main_clk = "cpsw_125mhz_gclk", |
565 | .prcm = { | |
566 | .omap4 = { | |
567 | .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET, | |
568 | .modulemode = MODULEMODE_SWCTRL, | |
569 | }, | |
570 | }, | |
571 | }; | |
572 | ||
70384a6a M |
573 | /* |
574 | * mdio class | |
575 | */ | |
576 | static struct omap_hwmod_class am33xx_mdio_hwmod_class = { | |
577 | .name = "davinci_mdio", | |
578 | }; | |
579 | ||
580 | static struct omap_hwmod am33xx_mdio_hwmod = { | |
581 | .name = "davinci_mdio", | |
582 | .class = &am33xx_mdio_hwmod_class, | |
583 | .clkdm_name = "cpsw_125mhz_clkdm", | |
584 | .main_clk = "cpsw_125mhz_gclk", | |
585 | }; | |
586 | ||
a2cfc509 VH |
587 | /* |
588 | * dcan class | |
589 | */ | |
590 | static struct omap_hwmod_class am33xx_dcan_hwmod_class = { | |
591 | .name = "d_can", | |
592 | }; | |
593 | ||
594 | /* dcan0 */ | |
a2cfc509 VH |
595 | static struct omap_hwmod am33xx_dcan0_hwmod = { |
596 | .name = "d_can0", | |
597 | .class = &am33xx_dcan_hwmod_class, | |
598 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
599 | .main_clk = "dcan0_fck", |
600 | .prcm = { | |
601 | .omap4 = { | |
602 | .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET, | |
603 | .modulemode = MODULEMODE_SWCTRL, | |
604 | }, | |
605 | }, | |
606 | }; | |
607 | ||
608 | /* dcan1 */ | |
a2cfc509 VH |
609 | static struct omap_hwmod am33xx_dcan1_hwmod = { |
610 | .name = "d_can1", | |
611 | .class = &am33xx_dcan_hwmod_class, | |
612 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
613 | .main_clk = "dcan1_fck", |
614 | .prcm = { | |
615 | .omap4 = { | |
616 | .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET, | |
617 | .modulemode = MODULEMODE_SWCTRL, | |
618 | }, | |
619 | }, | |
620 | }; | |
621 | ||
622 | /* elm */ | |
623 | static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = { | |
624 | .rev_offs = 0x0000, | |
625 | .sysc_offs = 0x0010, | |
626 | .syss_offs = 0x0014, | |
627 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
628 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
629 | SYSS_HAS_RESET_STATUS), | |
630 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
631 | .sysc_fields = &omap_hwmod_sysc_type1, | |
632 | }; | |
633 | ||
634 | static struct omap_hwmod_class am33xx_elm_hwmod_class = { | |
635 | .name = "elm", | |
636 | .sysc = &am33xx_elm_sysc, | |
637 | }; | |
638 | ||
a2cfc509 VH |
639 | static struct omap_hwmod am33xx_elm_hwmod = { |
640 | .name = "elm", | |
641 | .class = &am33xx_elm_hwmod_class, | |
642 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
643 | .main_clk = "l4ls_gclk", |
644 | .prcm = { | |
645 | .omap4 = { | |
646 | .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET, | |
647 | .modulemode = MODULEMODE_SWCTRL, | |
648 | }, | |
649 | }, | |
650 | }; | |
651 | ||
9652d19a | 652 | /* pwmss */ |
a2cfc509 VH |
653 | static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = { |
654 | .rev_offs = 0x0, | |
655 | .sysc_offs = 0x4, | |
656 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), | |
657 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
658 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
659 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
660 | .sysc_fields = &omap_hwmod_sysc_type2, | |
661 | }; | |
662 | ||
663 | static struct omap_hwmod_class am33xx_epwmss_hwmod_class = { | |
664 | .name = "epwmss", | |
665 | .sysc = &am33xx_epwmss_sysc, | |
666 | }; | |
667 | ||
9652d19a PA |
668 | static struct omap_hwmod_class am33xx_ecap_hwmod_class = { |
669 | .name = "ecap", | |
a2cfc509 VH |
670 | }; |
671 | ||
9652d19a PA |
672 | static struct omap_hwmod_class am33xx_eqep_hwmod_class = { |
673 | .name = "eqep", | |
a2cfc509 VH |
674 | }; |
675 | ||
9652d19a PA |
676 | static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = { |
677 | .name = "ehrpwm", | |
a2cfc509 VH |
678 | }; |
679 | ||
9652d19a PA |
680 | /* epwmss0 */ |
681 | static struct omap_hwmod am33xx_epwmss0_hwmod = { | |
682 | .name = "epwmss0", | |
a2cfc509 VH |
683 | .class = &am33xx_epwmss_hwmod_class, |
684 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
685 | .main_clk = "l4ls_gclk", |
686 | .prcm = { | |
687 | .omap4 = { | |
9652d19a | 688 | .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET, |
a2cfc509 VH |
689 | .modulemode = MODULEMODE_SWCTRL, |
690 | }, | |
691 | }, | |
692 | }; | |
693 | ||
9652d19a | 694 | /* ecap0 */ |
9652d19a PA |
695 | static struct omap_hwmod am33xx_ecap0_hwmod = { |
696 | .name = "ecap0", | |
697 | .class = &am33xx_ecap_hwmod_class, | |
a2cfc509 | 698 | .clkdm_name = "l4ls_clkdm", |
a2cfc509 | 699 | .main_clk = "l4ls_gclk", |
a2cfc509 VH |
700 | }; |
701 | ||
bee76659 | 702 | /* eqep0 */ |
bee76659 PA |
703 | static struct omap_hwmod am33xx_eqep0_hwmod = { |
704 | .name = "eqep0", | |
9652d19a | 705 | .class = &am33xx_eqep_hwmod_class, |
bee76659 | 706 | .clkdm_name = "l4ls_clkdm", |
bee76659 | 707 | .main_clk = "l4ls_gclk", |
bee76659 PA |
708 | }; |
709 | ||
9652d19a | 710 | /* ehrpwm0 */ |
9652d19a PA |
711 | static struct omap_hwmod am33xx_ehrpwm0_hwmod = { |
712 | .name = "ehrpwm0", | |
713 | .class = &am33xx_ehrpwm_hwmod_class, | |
714 | .clkdm_name = "l4ls_clkdm", | |
9652d19a PA |
715 | .main_clk = "l4ls_gclk", |
716 | }; | |
717 | ||
718 | /* epwmss1 */ | |
719 | static struct omap_hwmod am33xx_epwmss1_hwmod = { | |
720 | .name = "epwmss1", | |
bee76659 PA |
721 | .class = &am33xx_epwmss_hwmod_class, |
722 | .clkdm_name = "l4ls_clkdm", | |
bee76659 PA |
723 | .main_clk = "l4ls_gclk", |
724 | .prcm = { | |
725 | .omap4 = { | |
726 | .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET, | |
727 | .modulemode = MODULEMODE_SWCTRL, | |
728 | }, | |
729 | }, | |
730 | }; | |
731 | ||
9652d19a | 732 | /* ecap1 */ |
9652d19a PA |
733 | static struct omap_hwmod am33xx_ecap1_hwmod = { |
734 | .name = "ecap1", | |
735 | .class = &am33xx_ecap_hwmod_class, | |
bee76659 | 736 | .clkdm_name = "l4ls_clkdm", |
bee76659 | 737 | .main_clk = "l4ls_gclk", |
bee76659 PA |
738 | }; |
739 | ||
9652d19a | 740 | /* eqep1 */ |
9652d19a PA |
741 | static struct omap_hwmod am33xx_eqep1_hwmod = { |
742 | .name = "eqep1", | |
743 | .class = &am33xx_eqep_hwmod_class, | |
a2cfc509 | 744 | .clkdm_name = "l4ls_clkdm", |
a2cfc509 | 745 | .main_clk = "l4ls_gclk", |
a2cfc509 VH |
746 | }; |
747 | ||
9652d19a | 748 | /* ehrpwm1 */ |
9652d19a PA |
749 | static struct omap_hwmod am33xx_ehrpwm1_hwmod = { |
750 | .name = "ehrpwm1", | |
751 | .class = &am33xx_ehrpwm_hwmod_class, | |
752 | .clkdm_name = "l4ls_clkdm", | |
9652d19a PA |
753 | .main_clk = "l4ls_gclk", |
754 | }; | |
755 | ||
756 | /* epwmss2 */ | |
757 | static struct omap_hwmod am33xx_epwmss2_hwmod = { | |
758 | .name = "epwmss2", | |
a2cfc509 VH |
759 | .class = &am33xx_epwmss_hwmod_class, |
760 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
761 | .main_clk = "l4ls_gclk", |
762 | .prcm = { | |
763 | .omap4 = { | |
9652d19a | 764 | .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET, |
a2cfc509 VH |
765 | .modulemode = MODULEMODE_SWCTRL, |
766 | }, | |
767 | }, | |
768 | }; | |
769 | ||
770 | /* ecap2 */ | |
a2cfc509 VH |
771 | static struct omap_hwmod am33xx_ecap2_hwmod = { |
772 | .name = "ecap2", | |
9652d19a PA |
773 | .class = &am33xx_ecap_hwmod_class, |
774 | .clkdm_name = "l4ls_clkdm", | |
9652d19a PA |
775 | .main_clk = "l4ls_gclk", |
776 | }; | |
777 | ||
778 | /* eqep2 */ | |
9652d19a PA |
779 | static struct omap_hwmod am33xx_eqep2_hwmod = { |
780 | .name = "eqep2", | |
781 | .class = &am33xx_eqep_hwmod_class, | |
a2cfc509 | 782 | .clkdm_name = "l4ls_clkdm", |
9652d19a PA |
783 | .main_clk = "l4ls_gclk", |
784 | }; | |
785 | ||
786 | /* ehrpwm2 */ | |
9652d19a PA |
787 | static struct omap_hwmod am33xx_ehrpwm2_hwmod = { |
788 | .name = "ehrpwm2", | |
789 | .class = &am33xx_ehrpwm_hwmod_class, | |
790 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 | 791 | .main_clk = "l4ls_gclk", |
a2cfc509 VH |
792 | }; |
793 | ||
794 | /* | |
795 | * 'gpio' class: for gpio 0,1,2,3 | |
796 | */ | |
797 | static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = { | |
798 | .rev_offs = 0x0000, | |
799 | .sysc_offs = 0x0010, | |
800 | .syss_offs = 0x0114, | |
801 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
802 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
803 | SYSS_HAS_RESET_STATUS), | |
804 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
805 | SIDLE_SMART_WKUP), | |
806 | .sysc_fields = &omap_hwmod_sysc_type1, | |
807 | }; | |
808 | ||
809 | static struct omap_hwmod_class am33xx_gpio_hwmod_class = { | |
810 | .name = "gpio", | |
811 | .sysc = &am33xx_gpio_sysc, | |
812 | .rev = 2, | |
813 | }; | |
814 | ||
815 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
816 | .bank_width = 32, | |
817 | .dbck_flag = true, | |
818 | }; | |
819 | ||
820 | /* gpio0 */ | |
821 | static struct omap_hwmod_opt_clk gpio0_opt_clks[] = { | |
822 | { .role = "dbclk", .clk = "gpio0_dbclk" }, | |
823 | }; | |
824 | ||
a2cfc509 VH |
825 | static struct omap_hwmod am33xx_gpio0_hwmod = { |
826 | .name = "gpio1", | |
827 | .class = &am33xx_gpio_hwmod_class, | |
828 | .clkdm_name = "l4_wkup_clkdm", | |
829 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
a2cfc509 VH |
830 | .main_clk = "dpll_core_m4_div2_ck", |
831 | .prcm = { | |
832 | .omap4 = { | |
833 | .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET, | |
834 | .modulemode = MODULEMODE_SWCTRL, | |
835 | }, | |
836 | }, | |
837 | .opt_clks = gpio0_opt_clks, | |
838 | .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks), | |
839 | .dev_attr = &gpio_dev_attr, | |
840 | }; | |
841 | ||
842 | /* gpio1 */ | |
a2cfc509 VH |
843 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
844 | { .role = "dbclk", .clk = "gpio1_dbclk" }, | |
845 | }; | |
846 | ||
847 | static struct omap_hwmod am33xx_gpio1_hwmod = { | |
848 | .name = "gpio2", | |
849 | .class = &am33xx_gpio_hwmod_class, | |
850 | .clkdm_name = "l4ls_clkdm", | |
851 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
a2cfc509 VH |
852 | .main_clk = "l4ls_gclk", |
853 | .prcm = { | |
854 | .omap4 = { | |
855 | .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET, | |
856 | .modulemode = MODULEMODE_SWCTRL, | |
857 | }, | |
858 | }, | |
859 | .opt_clks = gpio1_opt_clks, | |
860 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
861 | .dev_attr = &gpio_dev_attr, | |
862 | }; | |
863 | ||
864 | /* gpio2 */ | |
a2cfc509 VH |
865 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
866 | { .role = "dbclk", .clk = "gpio2_dbclk" }, | |
867 | }; | |
868 | ||
869 | static struct omap_hwmod am33xx_gpio2_hwmod = { | |
870 | .name = "gpio3", | |
871 | .class = &am33xx_gpio_hwmod_class, | |
872 | .clkdm_name = "l4ls_clkdm", | |
873 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
a2cfc509 VH |
874 | .main_clk = "l4ls_gclk", |
875 | .prcm = { | |
876 | .omap4 = { | |
877 | .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET, | |
878 | .modulemode = MODULEMODE_SWCTRL, | |
879 | }, | |
880 | }, | |
881 | .opt_clks = gpio2_opt_clks, | |
882 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
883 | .dev_attr = &gpio_dev_attr, | |
884 | }; | |
885 | ||
886 | /* gpio3 */ | |
a2cfc509 VH |
887 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
888 | { .role = "dbclk", .clk = "gpio3_dbclk" }, | |
889 | }; | |
890 | ||
891 | static struct omap_hwmod am33xx_gpio3_hwmod = { | |
892 | .name = "gpio4", | |
893 | .class = &am33xx_gpio_hwmod_class, | |
894 | .clkdm_name = "l4ls_clkdm", | |
895 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
a2cfc509 VH |
896 | .main_clk = "l4ls_gclk", |
897 | .prcm = { | |
898 | .omap4 = { | |
899 | .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET, | |
900 | .modulemode = MODULEMODE_SWCTRL, | |
901 | }, | |
902 | }, | |
903 | .opt_clks = gpio3_opt_clks, | |
904 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
905 | .dev_attr = &gpio_dev_attr, | |
906 | }; | |
907 | ||
908 | /* gpmc */ | |
909 | static struct omap_hwmod_class_sysconfig gpmc_sysc = { | |
910 | .rev_offs = 0x0, | |
911 | .sysc_offs = 0x10, | |
912 | .syss_offs = 0x14, | |
913 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
914 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
915 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
916 | .sysc_fields = &omap_hwmod_sysc_type1, | |
917 | }; | |
918 | ||
919 | static struct omap_hwmod_class am33xx_gpmc_hwmod_class = { | |
920 | .name = "gpmc", | |
921 | .sysc = &gpmc_sysc, | |
922 | }; | |
923 | ||
a2cfc509 VH |
924 | static struct omap_hwmod am33xx_gpmc_hwmod = { |
925 | .name = "gpmc", | |
926 | .class = &am33xx_gpmc_hwmod_class, | |
927 | .clkdm_name = "l3s_clkdm", | |
928 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
a2cfc509 VH |
929 | .main_clk = "l3s_gclk", |
930 | .prcm = { | |
931 | .omap4 = { | |
932 | .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET, | |
933 | .modulemode = MODULEMODE_SWCTRL, | |
934 | }, | |
935 | }, | |
936 | }; | |
937 | ||
938 | /* 'i2c' class */ | |
939 | static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = { | |
940 | .sysc_offs = 0x0010, | |
941 | .syss_offs = 0x0090, | |
942 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
943 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
944 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
945 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
946 | SIDLE_SMART_WKUP), | |
947 | .sysc_fields = &omap_hwmod_sysc_type1, | |
948 | }; | |
949 | ||
950 | static struct omap_hwmod_class i2c_class = { | |
951 | .name = "i2c", | |
952 | .sysc = &am33xx_i2c_sysc, | |
953 | .rev = OMAP_I2C_IP_VERSION_2, | |
954 | .reset = &omap_i2c_reset, | |
955 | }; | |
956 | ||
957 | static struct omap_i2c_dev_attr i2c_dev_attr = { | |
972deb4f | 958 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, |
a2cfc509 VH |
959 | }; |
960 | ||
961 | /* i2c1 */ | |
a2cfc509 VH |
962 | static struct omap_hwmod am33xx_i2c1_hwmod = { |
963 | .name = "i2c1", | |
964 | .class = &i2c_class, | |
965 | .clkdm_name = "l4_wkup_clkdm", | |
a2cfc509 VH |
966 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
967 | .main_clk = "dpll_per_m2_div4_wkupdm_ck", | |
968 | .prcm = { | |
969 | .omap4 = { | |
970 | .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET, | |
971 | .modulemode = MODULEMODE_SWCTRL, | |
972 | }, | |
973 | }, | |
974 | .dev_attr = &i2c_dev_attr, | |
975 | }; | |
976 | ||
977 | /* i2c1 */ | |
a2cfc509 VH |
978 | static struct omap_hwmod am33xx_i2c2_hwmod = { |
979 | .name = "i2c2", | |
980 | .class = &i2c_class, | |
981 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
982 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
983 | .main_clk = "dpll_per_m2_div4_ck", | |
984 | .prcm = { | |
985 | .omap4 = { | |
986 | .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET, | |
987 | .modulemode = MODULEMODE_SWCTRL, | |
988 | }, | |
989 | }, | |
990 | .dev_attr = &i2c_dev_attr, | |
991 | }; | |
992 | ||
993 | /* i2c3 */ | |
a2cfc509 VH |
994 | static struct omap_hwmod am33xx_i2c3_hwmod = { |
995 | .name = "i2c3", | |
996 | .class = &i2c_class, | |
997 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
998 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
999 | .main_clk = "dpll_per_m2_div4_ck", | |
1000 | .prcm = { | |
1001 | .omap4 = { | |
1002 | .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET, | |
1003 | .modulemode = MODULEMODE_SWCTRL, | |
1004 | }, | |
1005 | }, | |
1006 | .dev_attr = &i2c_dev_attr, | |
1007 | }; | |
1008 | ||
1009 | ||
1010 | /* lcdc */ | |
1011 | static struct omap_hwmod_class_sysconfig lcdc_sysc = { | |
1012 | .rev_offs = 0x0, | |
1013 | .sysc_offs = 0x54, | |
1014 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), | |
1015 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1016 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1017 | }; | |
1018 | ||
1019 | static struct omap_hwmod_class am33xx_lcdc_hwmod_class = { | |
1020 | .name = "lcdc", | |
1021 | .sysc = &lcdc_sysc, | |
1022 | }; | |
1023 | ||
a2cfc509 VH |
1024 | static struct omap_hwmod am33xx_lcdc_hwmod = { |
1025 | .name = "lcdc", | |
1026 | .class = &am33xx_lcdc_hwmod_class, | |
1027 | .clkdm_name = "lcdc_clkdm", | |
a2cfc509 VH |
1028 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
1029 | .main_clk = "lcd_gclk", | |
1030 | .prcm = { | |
1031 | .omap4 = { | |
1032 | .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET, | |
1033 | .modulemode = MODULEMODE_SWCTRL, | |
1034 | }, | |
1035 | }, | |
1036 | }; | |
1037 | ||
1038 | /* | |
1039 | * 'mailbox' class | |
1040 | * mailbox module allowing communication between the on-chip processors using a | |
1041 | * queued mailbox-interrupt mechanism. | |
1042 | */ | |
1043 | static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = { | |
1044 | .rev_offs = 0x0000, | |
1045 | .sysc_offs = 0x0010, | |
1046 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1047 | SYSC_HAS_SOFTRESET), | |
1048 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1049 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1050 | }; | |
1051 | ||
1052 | static struct omap_hwmod_class am33xx_mailbox_hwmod_class = { | |
1053 | .name = "mailbox", | |
1054 | .sysc = &am33xx_mailbox_sysc, | |
1055 | }; | |
1056 | ||
a2cfc509 VH |
1057 | static struct omap_hwmod am33xx_mailbox_hwmod = { |
1058 | .name = "mailbox", | |
1059 | .class = &am33xx_mailbox_hwmod_class, | |
1060 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
1061 | .main_clk = "l4ls_gclk", |
1062 | .prcm = { | |
1063 | .omap4 = { | |
1064 | .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET, | |
1065 | .modulemode = MODULEMODE_SWCTRL, | |
1066 | }, | |
1067 | }, | |
1068 | }; | |
1069 | ||
1070 | /* | |
1071 | * 'mcasp' class | |
1072 | */ | |
1073 | static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = { | |
1074 | .rev_offs = 0x0, | |
1075 | .sysc_offs = 0x4, | |
1076 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
1077 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1078 | .sysc_fields = &omap_hwmod_sysc_type3, | |
1079 | }; | |
1080 | ||
1081 | static struct omap_hwmod_class am33xx_mcasp_hwmod_class = { | |
1082 | .name = "mcasp", | |
1083 | .sysc = &am33xx_mcasp_sysc, | |
1084 | }; | |
1085 | ||
1086 | /* mcasp0 */ | |
a2cfc509 VH |
1087 | static struct omap_hwmod am33xx_mcasp0_hwmod = { |
1088 | .name = "mcasp0", | |
1089 | .class = &am33xx_mcasp_hwmod_class, | |
1090 | .clkdm_name = "l3s_clkdm", | |
a2cfc509 VH |
1091 | .main_clk = "mcasp0_fck", |
1092 | .prcm = { | |
1093 | .omap4 = { | |
1094 | .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET, | |
1095 | .modulemode = MODULEMODE_SWCTRL, | |
1096 | }, | |
1097 | }, | |
1098 | }; | |
1099 | ||
1100 | /* mcasp1 */ | |
a2cfc509 VH |
1101 | static struct omap_hwmod am33xx_mcasp1_hwmod = { |
1102 | .name = "mcasp1", | |
1103 | .class = &am33xx_mcasp_hwmod_class, | |
1104 | .clkdm_name = "l3s_clkdm", | |
a2cfc509 VH |
1105 | .main_clk = "mcasp1_fck", |
1106 | .prcm = { | |
1107 | .omap4 = { | |
1108 | .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET, | |
1109 | .modulemode = MODULEMODE_SWCTRL, | |
1110 | }, | |
1111 | }, | |
1112 | }; | |
1113 | ||
1114 | /* 'mmc' class */ | |
1115 | static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = { | |
1116 | .rev_offs = 0x1fc, | |
1117 | .sysc_offs = 0x10, | |
1118 | .syss_offs = 0x14, | |
1119 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1120 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1121 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1122 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1123 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1124 | }; | |
1125 | ||
1126 | static struct omap_hwmod_class am33xx_mmc_hwmod_class = { | |
1127 | .name = "mmc", | |
1128 | .sysc = &am33xx_mmc_sysc, | |
1129 | }; | |
1130 | ||
1131 | /* mmc0 */ | |
a2cfc509 VH |
1132 | static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = { |
1133 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
1134 | }; | |
1135 | ||
1136 | static struct omap_hwmod am33xx_mmc0_hwmod = { | |
1137 | .name = "mmc1", | |
1138 | .class = &am33xx_mmc_hwmod_class, | |
1139 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
1140 | .main_clk = "mmc_clk", |
1141 | .prcm = { | |
1142 | .omap4 = { | |
1143 | .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET, | |
1144 | .modulemode = MODULEMODE_SWCTRL, | |
1145 | }, | |
1146 | }, | |
1147 | .dev_attr = &am33xx_mmc0_dev_attr, | |
1148 | }; | |
1149 | ||
1150 | /* mmc1 */ | |
a2cfc509 VH |
1151 | static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = { |
1152 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
1153 | }; | |
1154 | ||
1155 | static struct omap_hwmod am33xx_mmc1_hwmod = { | |
1156 | .name = "mmc2", | |
1157 | .class = &am33xx_mmc_hwmod_class, | |
1158 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
1159 | .main_clk = "mmc_clk", |
1160 | .prcm = { | |
1161 | .omap4 = { | |
1162 | .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET, | |
1163 | .modulemode = MODULEMODE_SWCTRL, | |
1164 | }, | |
1165 | }, | |
1166 | .dev_attr = &am33xx_mmc1_dev_attr, | |
1167 | }; | |
1168 | ||
1169 | /* mmc2 */ | |
a2cfc509 VH |
1170 | static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = { |
1171 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
1172 | }; | |
1173 | static struct omap_hwmod am33xx_mmc2_hwmod = { | |
1174 | .name = "mmc3", | |
1175 | .class = &am33xx_mmc_hwmod_class, | |
1176 | .clkdm_name = "l3s_clkdm", | |
a2cfc509 VH |
1177 | .main_clk = "mmc_clk", |
1178 | .prcm = { | |
1179 | .omap4 = { | |
1180 | .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET, | |
1181 | .modulemode = MODULEMODE_SWCTRL, | |
1182 | }, | |
1183 | }, | |
1184 | .dev_attr = &am33xx_mmc2_dev_attr, | |
1185 | }; | |
1186 | ||
1187 | /* | |
1188 | * 'rtc' class | |
1189 | * rtc subsystem | |
1190 | */ | |
1191 | static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = { | |
1192 | .rev_offs = 0x0074, | |
1193 | .sysc_offs = 0x0078, | |
1194 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
1195 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | | |
1196 | SIDLE_SMART | SIDLE_SMART_WKUP), | |
1197 | .sysc_fields = &omap_hwmod_sysc_type3, | |
1198 | }; | |
1199 | ||
1200 | static struct omap_hwmod_class am33xx_rtc_hwmod_class = { | |
1201 | .name = "rtc", | |
1202 | .sysc = &am33xx_rtc_sysc, | |
1203 | }; | |
1204 | ||
a2cfc509 VH |
1205 | static struct omap_hwmod am33xx_rtc_hwmod = { |
1206 | .name = "rtc", | |
1207 | .class = &am33xx_rtc_hwmod_class, | |
1208 | .clkdm_name = "l4_rtc_clkdm", | |
a2cfc509 VH |
1209 | .main_clk = "clk_32768_ck", |
1210 | .prcm = { | |
1211 | .omap4 = { | |
1212 | .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET, | |
1213 | .modulemode = MODULEMODE_SWCTRL, | |
1214 | }, | |
1215 | }, | |
1216 | }; | |
1217 | ||
1218 | /* 'spi' class */ | |
1219 | static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = { | |
1220 | .rev_offs = 0x0000, | |
1221 | .sysc_offs = 0x0110, | |
1222 | .syss_offs = 0x0114, | |
1223 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1224 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
1225 | SYSS_HAS_RESET_STATUS), | |
1226 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1227 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1228 | }; | |
1229 | ||
1230 | static struct omap_hwmod_class am33xx_spi_hwmod_class = { | |
1231 | .name = "mcspi", | |
1232 | .sysc = &am33xx_mcspi_sysc, | |
1233 | .rev = OMAP4_MCSPI_REV, | |
1234 | }; | |
1235 | ||
1236 | /* spi0 */ | |
a2cfc509 VH |
1237 | static struct omap2_mcspi_dev_attr mcspi_attrib = { |
1238 | .num_chipselect = 2, | |
1239 | }; | |
1240 | static struct omap_hwmod am33xx_spi0_hwmod = { | |
1241 | .name = "spi0", | |
1242 | .class = &am33xx_spi_hwmod_class, | |
1243 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
1244 | .main_clk = "dpll_per_m2_div4_ck", |
1245 | .prcm = { | |
1246 | .omap4 = { | |
1247 | .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET, | |
1248 | .modulemode = MODULEMODE_SWCTRL, | |
1249 | }, | |
1250 | }, | |
1251 | .dev_attr = &mcspi_attrib, | |
1252 | }; | |
1253 | ||
1254 | /* spi1 */ | |
a2cfc509 VH |
1255 | static struct omap_hwmod am33xx_spi1_hwmod = { |
1256 | .name = "spi1", | |
1257 | .class = &am33xx_spi_hwmod_class, | |
1258 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
1259 | .main_clk = "dpll_per_m2_div4_ck", |
1260 | .prcm = { | |
1261 | .omap4 = { | |
1262 | .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET, | |
1263 | .modulemode = MODULEMODE_SWCTRL, | |
1264 | }, | |
1265 | }, | |
1266 | .dev_attr = &mcspi_attrib, | |
1267 | }; | |
1268 | ||
1269 | /* | |
1270 | * 'spinlock' class | |
1271 | * spinlock provides hardware assistance for synchronizing the | |
1272 | * processes running on multiple processors | |
1273 | */ | |
1274 | static struct omap_hwmod_class am33xx_spinlock_hwmod_class = { | |
1275 | .name = "spinlock", | |
1276 | }; | |
1277 | ||
1278 | static struct omap_hwmod am33xx_spinlock_hwmod = { | |
1279 | .name = "spinlock", | |
1280 | .class = &am33xx_spinlock_hwmod_class, | |
1281 | .clkdm_name = "l4ls_clkdm", | |
1282 | .main_clk = "l4ls_gclk", | |
1283 | .prcm = { | |
1284 | .omap4 = { | |
1285 | .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET, | |
1286 | .modulemode = MODULEMODE_SWCTRL, | |
1287 | }, | |
1288 | }, | |
1289 | }; | |
1290 | ||
1291 | /* 'timer 2-7' class */ | |
1292 | static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = { | |
1293 | .rev_offs = 0x0000, | |
1294 | .sysc_offs = 0x0010, | |
1295 | .syss_offs = 0x0014, | |
1296 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1297 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1298 | SIDLE_SMART_WKUP), | |
1299 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1300 | }; | |
1301 | ||
1302 | static struct omap_hwmod_class am33xx_timer_hwmod_class = { | |
1303 | .name = "timer", | |
1304 | .sysc = &am33xx_timer_sysc, | |
1305 | }; | |
1306 | ||
1307 | /* timer1 1ms */ | |
1308 | static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = { | |
1309 | .rev_offs = 0x0000, | |
1310 | .sysc_offs = 0x0010, | |
1311 | .syss_offs = 0x0014, | |
1312 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1313 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
1314 | SYSS_HAS_RESET_STATUS), | |
1315 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1316 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1317 | }; | |
1318 | ||
1319 | static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = { | |
1320 | .name = "timer", | |
1321 | .sysc = &am33xx_timer1ms_sysc, | |
1322 | }; | |
1323 | ||
a2cfc509 VH |
1324 | static struct omap_hwmod am33xx_timer1_hwmod = { |
1325 | .name = "timer1", | |
1326 | .class = &am33xx_timer1ms_hwmod_class, | |
1327 | .clkdm_name = "l4_wkup_clkdm", | |
a2cfc509 VH |
1328 | .main_clk = "timer1_fck", |
1329 | .prcm = { | |
1330 | .omap4 = { | |
1331 | .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET, | |
1332 | .modulemode = MODULEMODE_SWCTRL, | |
1333 | }, | |
1334 | }, | |
1335 | }; | |
1336 | ||
a2cfc509 VH |
1337 | static struct omap_hwmod am33xx_timer2_hwmod = { |
1338 | .name = "timer2", | |
1339 | .class = &am33xx_timer_hwmod_class, | |
1340 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
1341 | .main_clk = "timer2_fck", |
1342 | .prcm = { | |
1343 | .omap4 = { | |
1344 | .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET, | |
1345 | .modulemode = MODULEMODE_SWCTRL, | |
1346 | }, | |
1347 | }, | |
1348 | }; | |
1349 | ||
a2cfc509 VH |
1350 | static struct omap_hwmod am33xx_timer3_hwmod = { |
1351 | .name = "timer3", | |
1352 | .class = &am33xx_timer_hwmod_class, | |
1353 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
1354 | .main_clk = "timer3_fck", |
1355 | .prcm = { | |
1356 | .omap4 = { | |
1357 | .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET, | |
1358 | .modulemode = MODULEMODE_SWCTRL, | |
1359 | }, | |
1360 | }, | |
1361 | }; | |
1362 | ||
a2cfc509 VH |
1363 | static struct omap_hwmod am33xx_timer4_hwmod = { |
1364 | .name = "timer4", | |
1365 | .class = &am33xx_timer_hwmod_class, | |
1366 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
1367 | .main_clk = "timer4_fck", |
1368 | .prcm = { | |
1369 | .omap4 = { | |
1370 | .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET, | |
1371 | .modulemode = MODULEMODE_SWCTRL, | |
1372 | }, | |
1373 | }, | |
1374 | }; | |
1375 | ||
a2cfc509 VH |
1376 | static struct omap_hwmod am33xx_timer5_hwmod = { |
1377 | .name = "timer5", | |
1378 | .class = &am33xx_timer_hwmod_class, | |
1379 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
1380 | .main_clk = "timer5_fck", |
1381 | .prcm = { | |
1382 | .omap4 = { | |
1383 | .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET, | |
1384 | .modulemode = MODULEMODE_SWCTRL, | |
1385 | }, | |
1386 | }, | |
1387 | }; | |
1388 | ||
a2cfc509 VH |
1389 | static struct omap_hwmod am33xx_timer6_hwmod = { |
1390 | .name = "timer6", | |
1391 | .class = &am33xx_timer_hwmod_class, | |
1392 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
1393 | .main_clk = "timer6_fck", |
1394 | .prcm = { | |
1395 | .omap4 = { | |
1396 | .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET, | |
1397 | .modulemode = MODULEMODE_SWCTRL, | |
1398 | }, | |
1399 | }, | |
1400 | }; | |
1401 | ||
a2cfc509 VH |
1402 | static struct omap_hwmod am33xx_timer7_hwmod = { |
1403 | .name = "timer7", | |
1404 | .class = &am33xx_timer_hwmod_class, | |
1405 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
1406 | .main_clk = "timer7_fck", |
1407 | .prcm = { | |
1408 | .omap4 = { | |
1409 | .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET, | |
1410 | .modulemode = MODULEMODE_SWCTRL, | |
1411 | }, | |
1412 | }, | |
1413 | }; | |
1414 | ||
1415 | /* tpcc */ | |
1416 | static struct omap_hwmod_class am33xx_tpcc_hwmod_class = { | |
1417 | .name = "tpcc", | |
1418 | }; | |
1419 | ||
a2cfc509 VH |
1420 | static struct omap_hwmod am33xx_tpcc_hwmod = { |
1421 | .name = "tpcc", | |
1422 | .class = &am33xx_tpcc_hwmod_class, | |
1423 | .clkdm_name = "l3_clkdm", | |
a2cfc509 VH |
1424 | .main_clk = "l3_gclk", |
1425 | .prcm = { | |
1426 | .omap4 = { | |
1427 | .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET, | |
1428 | .modulemode = MODULEMODE_SWCTRL, | |
1429 | }, | |
1430 | }, | |
1431 | }; | |
1432 | ||
1433 | static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = { | |
1434 | .rev_offs = 0x0, | |
1435 | .sysc_offs = 0x10, | |
1436 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1437 | SYSC_HAS_MIDLEMODE), | |
1438 | .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE), | |
1439 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1440 | }; | |
1441 | ||
1442 | /* 'tptc' class */ | |
1443 | static struct omap_hwmod_class am33xx_tptc_hwmod_class = { | |
1444 | .name = "tptc", | |
1445 | .sysc = &am33xx_tptc_sysc, | |
1446 | }; | |
1447 | ||
1448 | /* tptc0 */ | |
a2cfc509 VH |
1449 | static struct omap_hwmod am33xx_tptc0_hwmod = { |
1450 | .name = "tptc0", | |
1451 | .class = &am33xx_tptc_hwmod_class, | |
1452 | .clkdm_name = "l3_clkdm", | |
0bfbbded | 1453 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
a2cfc509 VH |
1454 | .main_clk = "l3_gclk", |
1455 | .prcm = { | |
1456 | .omap4 = { | |
1457 | .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET, | |
1458 | .modulemode = MODULEMODE_SWCTRL, | |
1459 | }, | |
1460 | }, | |
1461 | }; | |
1462 | ||
1463 | /* tptc1 */ | |
a2cfc509 VH |
1464 | static struct omap_hwmod am33xx_tptc1_hwmod = { |
1465 | .name = "tptc1", | |
1466 | .class = &am33xx_tptc_hwmod_class, | |
1467 | .clkdm_name = "l3_clkdm", | |
a2cfc509 VH |
1468 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), |
1469 | .main_clk = "l3_gclk", | |
1470 | .prcm = { | |
1471 | .omap4 = { | |
1472 | .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET, | |
1473 | .modulemode = MODULEMODE_SWCTRL, | |
1474 | }, | |
1475 | }, | |
1476 | }; | |
1477 | ||
1478 | /* tptc2 */ | |
a2cfc509 VH |
1479 | static struct omap_hwmod am33xx_tptc2_hwmod = { |
1480 | .name = "tptc2", | |
1481 | .class = &am33xx_tptc_hwmod_class, | |
1482 | .clkdm_name = "l3_clkdm", | |
a2cfc509 VH |
1483 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), |
1484 | .main_clk = "l3_gclk", | |
1485 | .prcm = { | |
1486 | .omap4 = { | |
1487 | .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET, | |
1488 | .modulemode = MODULEMODE_SWCTRL, | |
1489 | }, | |
1490 | }, | |
1491 | }; | |
1492 | ||
1493 | /* 'uart' class */ | |
1494 | static struct omap_hwmod_class_sysconfig uart_sysc = { | |
1495 | .rev_offs = 0x50, | |
1496 | .sysc_offs = 0x54, | |
1497 | .syss_offs = 0x58, | |
1498 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
1499 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1500 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1501 | SIDLE_SMART_WKUP), | |
1502 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1503 | }; | |
1504 | ||
1505 | static struct omap_hwmod_class uart_class = { | |
1506 | .name = "uart", | |
1507 | .sysc = &uart_sysc, | |
1508 | }; | |
1509 | ||
1510 | /* uart1 */ | |
a2cfc509 VH |
1511 | static struct omap_hwmod am33xx_uart1_hwmod = { |
1512 | .name = "uart1", | |
1513 | .class = &uart_class, | |
1514 | .clkdm_name = "l4_wkup_clkdm", | |
66dde54e | 1515 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
a2cfc509 VH |
1516 | .main_clk = "dpll_per_m2_div4_wkupdm_ck", |
1517 | .prcm = { | |
1518 | .omap4 = { | |
1519 | .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET, | |
1520 | .modulemode = MODULEMODE_SWCTRL, | |
1521 | }, | |
1522 | }, | |
1523 | }; | |
1524 | ||
a2cfc509 VH |
1525 | static struct omap_hwmod am33xx_uart2_hwmod = { |
1526 | .name = "uart2", | |
1527 | .class = &uart_class, | |
1528 | .clkdm_name = "l4ls_clkdm", | |
66dde54e | 1529 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
a2cfc509 VH |
1530 | .main_clk = "dpll_per_m2_div4_ck", |
1531 | .prcm = { | |
1532 | .omap4 = { | |
1533 | .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET, | |
1534 | .modulemode = MODULEMODE_SWCTRL, | |
1535 | }, | |
1536 | }, | |
1537 | }; | |
1538 | ||
1539 | /* uart3 */ | |
a2cfc509 VH |
1540 | static struct omap_hwmod am33xx_uart3_hwmod = { |
1541 | .name = "uart3", | |
1542 | .class = &uart_class, | |
1543 | .clkdm_name = "l4ls_clkdm", | |
66dde54e | 1544 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
a2cfc509 VH |
1545 | .main_clk = "dpll_per_m2_div4_ck", |
1546 | .prcm = { | |
1547 | .omap4 = { | |
1548 | .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET, | |
1549 | .modulemode = MODULEMODE_SWCTRL, | |
1550 | }, | |
1551 | }, | |
1552 | }; | |
1553 | ||
a2cfc509 VH |
1554 | static struct omap_hwmod am33xx_uart4_hwmod = { |
1555 | .name = "uart4", | |
1556 | .class = &uart_class, | |
1557 | .clkdm_name = "l4ls_clkdm", | |
66dde54e | 1558 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
a2cfc509 VH |
1559 | .main_clk = "dpll_per_m2_div4_ck", |
1560 | .prcm = { | |
1561 | .omap4 = { | |
1562 | .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET, | |
1563 | .modulemode = MODULEMODE_SWCTRL, | |
1564 | }, | |
1565 | }, | |
1566 | }; | |
1567 | ||
a2cfc509 VH |
1568 | static struct omap_hwmod am33xx_uart5_hwmod = { |
1569 | .name = "uart5", | |
1570 | .class = &uart_class, | |
1571 | .clkdm_name = "l4ls_clkdm", | |
66dde54e | 1572 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
a2cfc509 VH |
1573 | .main_clk = "dpll_per_m2_div4_ck", |
1574 | .prcm = { | |
1575 | .omap4 = { | |
1576 | .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET, | |
1577 | .modulemode = MODULEMODE_SWCTRL, | |
1578 | }, | |
1579 | }, | |
1580 | }; | |
1581 | ||
a2cfc509 VH |
1582 | static struct omap_hwmod am33xx_uart6_hwmod = { |
1583 | .name = "uart6", | |
1584 | .class = &uart_class, | |
1585 | .clkdm_name = "l4ls_clkdm", | |
66dde54e | 1586 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
a2cfc509 VH |
1587 | .main_clk = "dpll_per_m2_div4_ck", |
1588 | .prcm = { | |
1589 | .omap4 = { | |
1590 | .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET, | |
1591 | .modulemode = MODULEMODE_SWCTRL, | |
1592 | }, | |
1593 | }, | |
1594 | }; | |
1595 | ||
1596 | /* 'wd_timer' class */ | |
05cf03b6 VH |
1597 | static struct omap_hwmod_class_sysconfig wdt_sysc = { |
1598 | .rev_offs = 0x0, | |
1599 | .sysc_offs = 0x10, | |
1600 | .syss_offs = 0x14, | |
1601 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
1602 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1603 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1604 | SIDLE_SMART_WKUP), | |
1605 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1606 | }; | |
1607 | ||
a2cfc509 VH |
1608 | static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = { |
1609 | .name = "wd_timer", | |
05cf03b6 VH |
1610 | .sysc = &wdt_sysc, |
1611 | .pre_shutdown = &omap2_wd_timer_disable, | |
a2cfc509 VH |
1612 | }; |
1613 | ||
1614 | /* | |
1615 | * XXX: device.c file uses hardcoded name for watchdog timer | |
1616 | * driver "wd_timer2, so we are also using same name as of now... | |
1617 | */ | |
1618 | static struct omap_hwmod am33xx_wd_timer1_hwmod = { | |
1619 | .name = "wd_timer2", | |
1620 | .class = &am33xx_wd_timer_hwmod_class, | |
1621 | .clkdm_name = "l4_wkup_clkdm", | |
05cf03b6 | 1622 | .flags = HWMOD_SWSUP_SIDLE, |
a2cfc509 VH |
1623 | .main_clk = "wdt1_fck", |
1624 | .prcm = { | |
1625 | .omap4 = { | |
1626 | .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET, | |
1627 | .modulemode = MODULEMODE_SWCTRL, | |
1628 | }, | |
1629 | }, | |
1630 | }; | |
1631 | ||
1632 | /* | |
1633 | * 'usb_otg' class | |
1634 | * high-speed on-the-go universal serial bus (usb_otg) controller | |
1635 | */ | |
1636 | static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = { | |
1637 | .rev_offs = 0x0, | |
1638 | .sysc_offs = 0x10, | |
1639 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), | |
1640 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1641 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1642 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1643 | }; | |
1644 | ||
1645 | static struct omap_hwmod_class am33xx_usbotg_class = { | |
1646 | .name = "usbotg", | |
1647 | .sysc = &am33xx_usbhsotg_sysc, | |
1648 | }; | |
1649 | ||
a2cfc509 VH |
1650 | static struct omap_hwmod am33xx_usbss_hwmod = { |
1651 | .name = "usb_otg_hs", | |
1652 | .class = &am33xx_usbotg_class, | |
1653 | .clkdm_name = "l3s_clkdm", | |
a2cfc509 VH |
1654 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
1655 | .main_clk = "usbotg_fck", | |
1656 | .prcm = { | |
1657 | .omap4 = { | |
1658 | .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET, | |
1659 | .modulemode = MODULEMODE_SWCTRL, | |
1660 | }, | |
1661 | }, | |
1662 | }; | |
1663 | ||
1664 | ||
1665 | /* | |
1666 | * Interfaces | |
1667 | */ | |
1668 | ||
a2cfc509 VH |
1669 | static struct omap_hwmod_addr_space am33xx_emif_addrs[] = { |
1670 | { | |
1671 | .pa_start = 0x4c000000, | |
1672 | .pa_end = 0x4c000fff, | |
1673 | .flags = ADDR_TYPE_RT | |
1674 | }, | |
1675 | { } | |
1676 | }; | |
1677 | /* l3 main -> emif */ | |
1678 | static struct omap_hwmod_ocp_if am33xx_l3_main__emif = { | |
1679 | .master = &am33xx_l3_main_hwmod, | |
1680 | .slave = &am33xx_emif_hwmod, | |
1681 | .clk = "dpll_core_m4_ck", | |
1682 | .addr = am33xx_emif_addrs, | |
1683 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1684 | }; | |
1685 | ||
1686 | /* mpu -> l3 main */ | |
1687 | static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = { | |
1688 | .master = &am33xx_mpu_hwmod, | |
1689 | .slave = &am33xx_l3_main_hwmod, | |
1690 | .clk = "dpll_mpu_m2_ck", | |
1691 | .user = OCP_USER_MPU, | |
1692 | }; | |
1693 | ||
1694 | /* l3 main -> l4 hs */ | |
1695 | static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = { | |
1696 | .master = &am33xx_l3_main_hwmod, | |
1697 | .slave = &am33xx_l4_hs_hwmod, | |
1698 | .clk = "l3s_gclk", | |
1699 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1700 | }; | |
1701 | ||
1702 | /* l3 main -> l3 s */ | |
1703 | static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = { | |
1704 | .master = &am33xx_l3_main_hwmod, | |
1705 | .slave = &am33xx_l3_s_hwmod, | |
1706 | .clk = "l3s_gclk", | |
1707 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1708 | }; | |
1709 | ||
1710 | /* l3 s -> l4 per/ls */ | |
1711 | static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = { | |
1712 | .master = &am33xx_l3_s_hwmod, | |
1713 | .slave = &am33xx_l4_ls_hwmod, | |
1714 | .clk = "l3s_gclk", | |
1715 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1716 | }; | |
1717 | ||
1718 | /* l3 s -> l4 wkup */ | |
1719 | static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = { | |
1720 | .master = &am33xx_l3_s_hwmod, | |
1721 | .slave = &am33xx_l4_wkup_hwmod, | |
1722 | .clk = "l3s_gclk", | |
1723 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1724 | }; | |
1725 | ||
a2cfc509 VH |
1726 | /* l3 main -> l3 instr */ |
1727 | static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = { | |
1728 | .master = &am33xx_l3_main_hwmod, | |
1729 | .slave = &am33xx_l3_instr_hwmod, | |
1730 | .clk = "l3s_gclk", | |
1731 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1732 | }; | |
1733 | ||
1734 | /* mpu -> prcm */ | |
1735 | static struct omap_hwmod_ocp_if am33xx_mpu__prcm = { | |
1736 | .master = &am33xx_mpu_hwmod, | |
1737 | .slave = &am33xx_prcm_hwmod, | |
1738 | .clk = "dpll_mpu_m2_ck", | |
1739 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1740 | }; | |
1741 | ||
1742 | /* l3 s -> l3 main*/ | |
1743 | static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = { | |
1744 | .master = &am33xx_l3_s_hwmod, | |
1745 | .slave = &am33xx_l3_main_hwmod, | |
1746 | .clk = "l3s_gclk", | |
1747 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1748 | }; | |
1749 | ||
1750 | /* pru-icss -> l3 main */ | |
1751 | static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = { | |
1752 | .master = &am33xx_pruss_hwmod, | |
1753 | .slave = &am33xx_l3_main_hwmod, | |
1754 | .clk = "l3_gclk", | |
1755 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1756 | }; | |
1757 | ||
1758 | /* wkup m3 -> l4 wkup */ | |
1759 | static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = { | |
1760 | .master = &am33xx_wkup_m3_hwmod, | |
1761 | .slave = &am33xx_l4_wkup_hwmod, | |
1762 | .clk = "dpll_core_m4_div2_ck", | |
1763 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1764 | }; | |
1765 | ||
1766 | /* gfx -> l3 main */ | |
1767 | static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = { | |
1768 | .master = &am33xx_gfx_hwmod, | |
1769 | .slave = &am33xx_l3_main_hwmod, | |
1770 | .clk = "dpll_core_m4_ck", | |
1771 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1772 | }; | |
1773 | ||
1774 | /* l4 wkup -> wkup m3 */ | |
a2cfc509 VH |
1775 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = { |
1776 | .master = &am33xx_l4_wkup_hwmod, | |
1777 | .slave = &am33xx_wkup_m3_hwmod, | |
1778 | .clk = "dpll_core_m4_div2_ck", | |
a2cfc509 VH |
1779 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1780 | }; | |
1781 | ||
1782 | /* l4 hs -> pru-icss */ | |
a2cfc509 VH |
1783 | static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = { |
1784 | .master = &am33xx_l4_hs_hwmod, | |
1785 | .slave = &am33xx_pruss_hwmod, | |
1786 | .clk = "dpll_core_m4_ck", | |
a2cfc509 VH |
1787 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1788 | }; | |
1789 | ||
1790 | /* l3 main -> gfx */ | |
a2cfc509 VH |
1791 | static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = { |
1792 | .master = &am33xx_l3_main_hwmod, | |
1793 | .slave = &am33xx_gfx_hwmod, | |
1794 | .clk = "dpll_core_m4_ck", | |
a2cfc509 VH |
1795 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1796 | }; | |
1797 | ||
1798 | /* l4 wkup -> smartreflex0 */ | |
a2cfc509 VH |
1799 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = { |
1800 | .master = &am33xx_l4_wkup_hwmod, | |
1801 | .slave = &am33xx_smartreflex0_hwmod, | |
1802 | .clk = "dpll_core_m4_div2_ck", | |
a2cfc509 VH |
1803 | .user = OCP_USER_MPU, |
1804 | }; | |
1805 | ||
1806 | /* l4 wkup -> smartreflex1 */ | |
a2cfc509 VH |
1807 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = { |
1808 | .master = &am33xx_l4_wkup_hwmod, | |
1809 | .slave = &am33xx_smartreflex1_hwmod, | |
1810 | .clk = "dpll_core_m4_div2_ck", | |
a2cfc509 VH |
1811 | .user = OCP_USER_MPU, |
1812 | }; | |
1813 | ||
1814 | /* l4 wkup -> control */ | |
a2cfc509 VH |
1815 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = { |
1816 | .master = &am33xx_l4_wkup_hwmod, | |
1817 | .slave = &am33xx_control_hwmod, | |
1818 | .clk = "dpll_core_m4_div2_ck", | |
a2cfc509 VH |
1819 | .user = OCP_USER_MPU, |
1820 | }; | |
1821 | ||
1822 | /* l4 wkup -> rtc */ | |
a2cfc509 VH |
1823 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = { |
1824 | .master = &am33xx_l4_wkup_hwmod, | |
1825 | .slave = &am33xx_rtc_hwmod, | |
1826 | .clk = "clkdiv32k_ick", | |
a2cfc509 VH |
1827 | .user = OCP_USER_MPU, |
1828 | }; | |
1829 | ||
1830 | /* l4 per/ls -> DCAN0 */ | |
a2cfc509 VH |
1831 | static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = { |
1832 | .master = &am33xx_l4_ls_hwmod, | |
1833 | .slave = &am33xx_dcan0_hwmod, | |
1834 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
1835 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1836 | }; | |
1837 | ||
1838 | /* l4 per/ls -> DCAN1 */ | |
a2cfc509 VH |
1839 | static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = { |
1840 | .master = &am33xx_l4_ls_hwmod, | |
1841 | .slave = &am33xx_dcan1_hwmod, | |
1842 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
1843 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1844 | }; | |
1845 | ||
1846 | /* l4 per/ls -> GPIO2 */ | |
a2cfc509 VH |
1847 | static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = { |
1848 | .master = &am33xx_l4_ls_hwmod, | |
1849 | .slave = &am33xx_gpio1_hwmod, | |
1850 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
1851 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1852 | }; | |
1853 | ||
1854 | /* l4 per/ls -> gpio3 */ | |
a2cfc509 VH |
1855 | static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = { |
1856 | .master = &am33xx_l4_ls_hwmod, | |
1857 | .slave = &am33xx_gpio2_hwmod, | |
1858 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
1859 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1860 | }; | |
1861 | ||
1862 | /* l4 per/ls -> gpio4 */ | |
a2cfc509 VH |
1863 | static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = { |
1864 | .master = &am33xx_l4_ls_hwmod, | |
1865 | .slave = &am33xx_gpio3_hwmod, | |
1866 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
1867 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1868 | }; | |
1869 | ||
1870 | /* L4 WKUP -> I2C1 */ | |
a2cfc509 VH |
1871 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = { |
1872 | .master = &am33xx_l4_wkup_hwmod, | |
1873 | .slave = &am33xx_i2c1_hwmod, | |
1874 | .clk = "dpll_core_m4_div2_ck", | |
a2cfc509 VH |
1875 | .user = OCP_USER_MPU, |
1876 | }; | |
1877 | ||
1878 | /* L4 WKUP -> GPIO1 */ | |
a2cfc509 VH |
1879 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = { |
1880 | .master = &am33xx_l4_wkup_hwmod, | |
1881 | .slave = &am33xx_gpio0_hwmod, | |
1882 | .clk = "dpll_core_m4_div2_ck", | |
a2cfc509 VH |
1883 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1884 | }; | |
1885 | ||
1886 | /* L4 WKUP -> ADC_TSC */ | |
1887 | static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = { | |
1888 | { | |
1889 | .pa_start = 0x44E0D000, | |
1890 | .pa_end = 0x44E0D000 + SZ_8K - 1, | |
1891 | .flags = ADDR_TYPE_RT | |
1892 | }, | |
1893 | { } | |
1894 | }; | |
1895 | ||
1896 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = { | |
1897 | .master = &am33xx_l4_wkup_hwmod, | |
1898 | .slave = &am33xx_adc_tsc_hwmod, | |
1899 | .clk = "dpll_core_m4_div2_ck", | |
1900 | .addr = am33xx_adc_tsc_addrs, | |
1901 | .user = OCP_USER_MPU, | |
1902 | }; | |
1903 | ||
a2cfc509 VH |
1904 | static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = { |
1905 | .master = &am33xx_l4_hs_hwmod, | |
1906 | .slave = &am33xx_cpgmac0_hwmod, | |
1907 | .clk = "cpsw_125mhz_gclk", | |
a2cfc509 VH |
1908 | .user = OCP_USER_MPU, |
1909 | }; | |
1910 | ||
9816aa80 | 1911 | static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = { |
70384a6a M |
1912 | .master = &am33xx_cpgmac0_hwmod, |
1913 | .slave = &am33xx_mdio_hwmod, | |
70384a6a M |
1914 | .user = OCP_USER_MPU, |
1915 | }; | |
1916 | ||
a2cfc509 VH |
1917 | static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = { |
1918 | { | |
1919 | .pa_start = 0x48080000, | |
1920 | .pa_end = 0x48080000 + SZ_8K - 1, | |
1921 | .flags = ADDR_TYPE_RT | |
1922 | }, | |
1923 | { } | |
1924 | }; | |
1925 | ||
1926 | static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = { | |
1927 | .master = &am33xx_l4_ls_hwmod, | |
1928 | .slave = &am33xx_elm_hwmod, | |
1929 | .clk = "l4ls_gclk", | |
1930 | .addr = am33xx_elm_addr_space, | |
1931 | .user = OCP_USER_MPU, | |
1932 | }; | |
1933 | ||
9652d19a | 1934 | static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = { |
a2cfc509 VH |
1935 | { |
1936 | .pa_start = 0x48300000, | |
1937 | .pa_end = 0x48300000 + SZ_16 - 1, | |
1938 | .flags = ADDR_TYPE_RT | |
1939 | }, | |
a2cfc509 VH |
1940 | { } |
1941 | }; | |
1942 | ||
9652d19a | 1943 | static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = { |
a2cfc509 | 1944 | .master = &am33xx_l4_ls_hwmod, |
9652d19a | 1945 | .slave = &am33xx_epwmss0_hwmod, |
a2cfc509 | 1946 | .clk = "l4ls_gclk", |
9652d19a | 1947 | .addr = am33xx_epwmss0_addr_space, |
a2cfc509 VH |
1948 | .user = OCP_USER_MPU, |
1949 | }; | |
1950 | ||
9652d19a PA |
1951 | static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = { |
1952 | .master = &am33xx_epwmss0_hwmod, | |
1953 | .slave = &am33xx_ecap0_hwmod, | |
a2cfc509 | 1954 | .clk = "l4ls_gclk", |
a2cfc509 VH |
1955 | .user = OCP_USER_MPU, |
1956 | }; | |
1957 | ||
9652d19a PA |
1958 | static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = { |
1959 | .master = &am33xx_epwmss0_hwmod, | |
1960 | .slave = &am33xx_eqep0_hwmod, | |
1961 | .clk = "l4ls_gclk", | |
9652d19a PA |
1962 | .user = OCP_USER_MPU, |
1963 | }; | |
1964 | ||
9652d19a PA |
1965 | static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = { |
1966 | .master = &am33xx_epwmss0_hwmod, | |
1967 | .slave = &am33xx_ehrpwm0_hwmod, | |
a2cfc509 | 1968 | .clk = "l4ls_gclk", |
a2cfc509 VH |
1969 | .user = OCP_USER_MPU, |
1970 | }; | |
1971 | ||
9652d19a PA |
1972 | |
1973 | static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = { | |
bee76659 | 1974 | { |
9652d19a PA |
1975 | .pa_start = 0x48302000, |
1976 | .pa_end = 0x48302000 + SZ_16 - 1, | |
bee76659 PA |
1977 | .flags = ADDR_TYPE_RT |
1978 | }, | |
bee76659 PA |
1979 | { } |
1980 | }; | |
1981 | ||
9652d19a | 1982 | static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = { |
bee76659 | 1983 | .master = &am33xx_l4_ls_hwmod, |
9652d19a | 1984 | .slave = &am33xx_epwmss1_hwmod, |
bee76659 | 1985 | .clk = "l4ls_gclk", |
9652d19a | 1986 | .addr = am33xx_epwmss1_addr_space, |
bee76659 PA |
1987 | .user = OCP_USER_MPU, |
1988 | }; | |
1989 | ||
9652d19a PA |
1990 | static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = { |
1991 | .master = &am33xx_epwmss1_hwmod, | |
1992 | .slave = &am33xx_ecap1_hwmod, | |
1993 | .clk = "l4ls_gclk", | |
9652d19a PA |
1994 | .user = OCP_USER_MPU, |
1995 | }; | |
1996 | ||
9652d19a PA |
1997 | static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = { |
1998 | .master = &am33xx_epwmss1_hwmod, | |
bee76659 PA |
1999 | .slave = &am33xx_eqep1_hwmod, |
2000 | .clk = "l4ls_gclk", | |
bee76659 PA |
2001 | .user = OCP_USER_MPU, |
2002 | }; | |
2003 | ||
9652d19a PA |
2004 | static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = { |
2005 | .master = &am33xx_epwmss1_hwmod, | |
2006 | .slave = &am33xx_ehrpwm1_hwmod, | |
bee76659 | 2007 | .clk = "l4ls_gclk", |
bee76659 PA |
2008 | .user = OCP_USER_MPU, |
2009 | }; | |
2010 | ||
9652d19a | 2011 | static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = { |
a2cfc509 | 2012 | { |
9652d19a PA |
2013 | .pa_start = 0x48304000, |
2014 | .pa_end = 0x48304000 + SZ_16 - 1, | |
a2cfc509 VH |
2015 | .flags = ADDR_TYPE_RT |
2016 | }, | |
a2cfc509 VH |
2017 | { } |
2018 | }; | |
2019 | ||
9652d19a | 2020 | static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = { |
a2cfc509 | 2021 | .master = &am33xx_l4_ls_hwmod, |
9652d19a | 2022 | .slave = &am33xx_epwmss2_hwmod, |
a2cfc509 | 2023 | .clk = "l4ls_gclk", |
9652d19a | 2024 | .addr = am33xx_epwmss2_addr_space, |
a2cfc509 VH |
2025 | .user = OCP_USER_MPU, |
2026 | }; | |
2027 | ||
9652d19a PA |
2028 | static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = { |
2029 | .master = &am33xx_epwmss2_hwmod, | |
2030 | .slave = &am33xx_ecap2_hwmod, | |
a2cfc509 | 2031 | .clk = "l4ls_gclk", |
a2cfc509 VH |
2032 | .user = OCP_USER_MPU, |
2033 | }; | |
2034 | ||
9652d19a PA |
2035 | static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = { |
2036 | .master = &am33xx_epwmss2_hwmod, | |
2037 | .slave = &am33xx_eqep2_hwmod, | |
2038 | .clk = "l4ls_gclk", | |
9652d19a PA |
2039 | .user = OCP_USER_MPU, |
2040 | }; | |
2041 | ||
9652d19a PA |
2042 | static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = { |
2043 | .master = &am33xx_epwmss2_hwmod, | |
2044 | .slave = &am33xx_ehrpwm2_hwmod, | |
a2cfc509 | 2045 | .clk = "l4ls_gclk", |
a2cfc509 VH |
2046 | .user = OCP_USER_MPU, |
2047 | }; | |
2048 | ||
2049 | /* l3s cfg -> gpmc */ | |
2050 | static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = { | |
2051 | { | |
2052 | .pa_start = 0x50000000, | |
2053 | .pa_end = 0x50000000 + SZ_8K - 1, | |
2054 | .flags = ADDR_TYPE_RT, | |
2055 | }, | |
2056 | { } | |
2057 | }; | |
2058 | ||
2059 | static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { | |
2060 | .master = &am33xx_l3_s_hwmod, | |
2061 | .slave = &am33xx_gpmc_hwmod, | |
2062 | .clk = "l3s_gclk", | |
2063 | .addr = am33xx_gpmc_addr_space, | |
2064 | .user = OCP_USER_MPU, | |
2065 | }; | |
2066 | ||
2067 | /* i2c2 */ | |
a2cfc509 VH |
2068 | static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = { |
2069 | .master = &am33xx_l4_ls_hwmod, | |
2070 | .slave = &am33xx_i2c2_hwmod, | |
2071 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2072 | .user = OCP_USER_MPU, |
2073 | }; | |
2074 | ||
a2cfc509 VH |
2075 | static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = { |
2076 | .master = &am33xx_l4_ls_hwmod, | |
2077 | .slave = &am33xx_i2c3_hwmod, | |
2078 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2079 | .user = OCP_USER_MPU, |
2080 | }; | |
2081 | ||
2082 | static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = { | |
2083 | { | |
2084 | .pa_start = 0x4830E000, | |
2085 | .pa_end = 0x4830E000 + SZ_8K - 1, | |
2086 | .flags = ADDR_TYPE_RT, | |
2087 | }, | |
2088 | { } | |
2089 | }; | |
2090 | ||
2091 | static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = { | |
2092 | .master = &am33xx_l3_main_hwmod, | |
2093 | .slave = &am33xx_lcdc_hwmod, | |
2094 | .clk = "dpll_core_m4_ck", | |
2095 | .addr = am33xx_lcdc_addr_space, | |
2096 | .user = OCP_USER_MPU, | |
2097 | }; | |
2098 | ||
2099 | static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = { | |
2100 | { | |
2101 | .pa_start = 0x480C8000, | |
2102 | .pa_end = 0x480C8000 + (SZ_4K - 1), | |
2103 | .flags = ADDR_TYPE_RT | |
2104 | }, | |
2105 | { } | |
2106 | }; | |
2107 | ||
2108 | /* l4 ls -> mailbox */ | |
2109 | static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = { | |
2110 | .master = &am33xx_l4_ls_hwmod, | |
2111 | .slave = &am33xx_mailbox_hwmod, | |
2112 | .clk = "l4ls_gclk", | |
2113 | .addr = am33xx_mailbox_addrs, | |
2114 | .user = OCP_USER_MPU, | |
2115 | }; | |
2116 | ||
2117 | /* l4 ls -> spinlock */ | |
a2cfc509 VH |
2118 | static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = { |
2119 | .master = &am33xx_l4_ls_hwmod, | |
2120 | .slave = &am33xx_spinlock_hwmod, | |
2121 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2122 | .user = OCP_USER_MPU, |
2123 | }; | |
2124 | ||
2125 | /* l4 ls -> mcasp0 */ | |
2126 | static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = { | |
2127 | { | |
2128 | .pa_start = 0x48038000, | |
2129 | .pa_end = 0x48038000 + SZ_8K - 1, | |
2130 | .flags = ADDR_TYPE_RT | |
2131 | }, | |
2132 | { } | |
2133 | }; | |
2134 | ||
2135 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = { | |
2136 | .master = &am33xx_l4_ls_hwmod, | |
2137 | .slave = &am33xx_mcasp0_hwmod, | |
2138 | .clk = "l4ls_gclk", | |
2139 | .addr = am33xx_mcasp0_addr_space, | |
2140 | .user = OCP_USER_MPU, | |
2141 | }; | |
2142 | ||
a2cfc509 VH |
2143 | /* l4 ls -> mcasp1 */ |
2144 | static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = { | |
2145 | { | |
2146 | .pa_start = 0x4803C000, | |
2147 | .pa_end = 0x4803C000 + SZ_8K - 1, | |
2148 | .flags = ADDR_TYPE_RT | |
2149 | }, | |
2150 | { } | |
2151 | }; | |
2152 | ||
2153 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = { | |
2154 | .master = &am33xx_l4_ls_hwmod, | |
2155 | .slave = &am33xx_mcasp1_hwmod, | |
2156 | .clk = "l4ls_gclk", | |
2157 | .addr = am33xx_mcasp1_addr_space, | |
2158 | .user = OCP_USER_MPU, | |
2159 | }; | |
2160 | ||
a2cfc509 VH |
2161 | /* l4 ls -> mmc0 */ |
2162 | static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = { | |
2163 | { | |
2164 | .pa_start = 0x48060100, | |
2165 | .pa_end = 0x48060100 + SZ_4K - 1, | |
2166 | .flags = ADDR_TYPE_RT, | |
2167 | }, | |
2168 | { } | |
2169 | }; | |
2170 | ||
2171 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = { | |
2172 | .master = &am33xx_l4_ls_hwmod, | |
2173 | .slave = &am33xx_mmc0_hwmod, | |
2174 | .clk = "l4ls_gclk", | |
2175 | .addr = am33xx_mmc0_addr_space, | |
2176 | .user = OCP_USER_MPU, | |
2177 | }; | |
2178 | ||
2179 | /* l4 ls -> mmc1 */ | |
2180 | static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = { | |
2181 | { | |
2182 | .pa_start = 0x481d8100, | |
2183 | .pa_end = 0x481d8100 + SZ_4K - 1, | |
2184 | .flags = ADDR_TYPE_RT, | |
2185 | }, | |
2186 | { } | |
2187 | }; | |
2188 | ||
2189 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = { | |
2190 | .master = &am33xx_l4_ls_hwmod, | |
2191 | .slave = &am33xx_mmc1_hwmod, | |
2192 | .clk = "l4ls_gclk", | |
2193 | .addr = am33xx_mmc1_addr_space, | |
2194 | .user = OCP_USER_MPU, | |
2195 | }; | |
2196 | ||
2197 | /* l3 s -> mmc2 */ | |
2198 | static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = { | |
2199 | { | |
2200 | .pa_start = 0x47810100, | |
2201 | .pa_end = 0x47810100 + SZ_64K - 1, | |
2202 | .flags = ADDR_TYPE_RT, | |
2203 | }, | |
2204 | { } | |
2205 | }; | |
2206 | ||
2207 | static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = { | |
2208 | .master = &am33xx_l3_s_hwmod, | |
2209 | .slave = &am33xx_mmc2_hwmod, | |
2210 | .clk = "l3s_gclk", | |
2211 | .addr = am33xx_mmc2_addr_space, | |
2212 | .user = OCP_USER_MPU, | |
2213 | }; | |
2214 | ||
2215 | /* l4 ls -> mcspi0 */ | |
a2cfc509 VH |
2216 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = { |
2217 | .master = &am33xx_l4_ls_hwmod, | |
2218 | .slave = &am33xx_spi0_hwmod, | |
2219 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2220 | .user = OCP_USER_MPU, |
2221 | }; | |
2222 | ||
2223 | /* l4 ls -> mcspi1 */ | |
a2cfc509 VH |
2224 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = { |
2225 | .master = &am33xx_l4_ls_hwmod, | |
2226 | .slave = &am33xx_spi1_hwmod, | |
2227 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2228 | .user = OCP_USER_MPU, |
2229 | }; | |
2230 | ||
2231 | /* l4 wkup -> timer1 */ | |
a2cfc509 VH |
2232 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = { |
2233 | .master = &am33xx_l4_wkup_hwmod, | |
2234 | .slave = &am33xx_timer1_hwmod, | |
2235 | .clk = "dpll_core_m4_div2_ck", | |
a2cfc509 VH |
2236 | .user = OCP_USER_MPU, |
2237 | }; | |
2238 | ||
2239 | /* l4 per -> timer2 */ | |
a2cfc509 VH |
2240 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { |
2241 | .master = &am33xx_l4_ls_hwmod, | |
2242 | .slave = &am33xx_timer2_hwmod, | |
2243 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2244 | .user = OCP_USER_MPU, |
2245 | }; | |
2246 | ||
2247 | /* l4 per -> timer3 */ | |
a2cfc509 VH |
2248 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = { |
2249 | .master = &am33xx_l4_ls_hwmod, | |
2250 | .slave = &am33xx_timer3_hwmod, | |
2251 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2252 | .user = OCP_USER_MPU, |
2253 | }; | |
2254 | ||
2255 | /* l4 per -> timer4 */ | |
a2cfc509 VH |
2256 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = { |
2257 | .master = &am33xx_l4_ls_hwmod, | |
2258 | .slave = &am33xx_timer4_hwmod, | |
2259 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2260 | .user = OCP_USER_MPU, |
2261 | }; | |
2262 | ||
2263 | /* l4 per -> timer5 */ | |
a2cfc509 VH |
2264 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = { |
2265 | .master = &am33xx_l4_ls_hwmod, | |
2266 | .slave = &am33xx_timer5_hwmod, | |
2267 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2268 | .user = OCP_USER_MPU, |
2269 | }; | |
2270 | ||
2271 | /* l4 per -> timer6 */ | |
a2cfc509 VH |
2272 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = { |
2273 | .master = &am33xx_l4_ls_hwmod, | |
2274 | .slave = &am33xx_timer6_hwmod, | |
2275 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2276 | .user = OCP_USER_MPU, |
2277 | }; | |
2278 | ||
2279 | /* l4 per -> timer7 */ | |
a2cfc509 VH |
2280 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = { |
2281 | .master = &am33xx_l4_ls_hwmod, | |
2282 | .slave = &am33xx_timer7_hwmod, | |
2283 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2284 | .user = OCP_USER_MPU, |
2285 | }; | |
2286 | ||
2287 | /* l3 main -> tpcc */ | |
a2cfc509 VH |
2288 | static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = { |
2289 | .master = &am33xx_l3_main_hwmod, | |
2290 | .slave = &am33xx_tpcc_hwmod, | |
2291 | .clk = "l3_gclk", | |
a2cfc509 VH |
2292 | .user = OCP_USER_MPU, |
2293 | }; | |
2294 | ||
2295 | /* l3 main -> tpcc0 */ | |
2296 | static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = { | |
2297 | { | |
2298 | .pa_start = 0x49800000, | |
2299 | .pa_end = 0x49800000 + SZ_8K - 1, | |
2300 | .flags = ADDR_TYPE_RT, | |
2301 | }, | |
2302 | { } | |
2303 | }; | |
2304 | ||
2305 | static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = { | |
2306 | .master = &am33xx_l3_main_hwmod, | |
2307 | .slave = &am33xx_tptc0_hwmod, | |
2308 | .clk = "l3_gclk", | |
2309 | .addr = am33xx_tptc0_addr_space, | |
2310 | .user = OCP_USER_MPU, | |
2311 | }; | |
2312 | ||
2313 | /* l3 main -> tpcc1 */ | |
2314 | static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = { | |
2315 | { | |
2316 | .pa_start = 0x49900000, | |
2317 | .pa_end = 0x49900000 + SZ_8K - 1, | |
2318 | .flags = ADDR_TYPE_RT, | |
2319 | }, | |
2320 | { } | |
2321 | }; | |
2322 | ||
2323 | static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = { | |
2324 | .master = &am33xx_l3_main_hwmod, | |
2325 | .slave = &am33xx_tptc1_hwmod, | |
2326 | .clk = "l3_gclk", | |
2327 | .addr = am33xx_tptc1_addr_space, | |
2328 | .user = OCP_USER_MPU, | |
2329 | }; | |
2330 | ||
2331 | /* l3 main -> tpcc2 */ | |
2332 | static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = { | |
2333 | { | |
2334 | .pa_start = 0x49a00000, | |
2335 | .pa_end = 0x49a00000 + SZ_8K - 1, | |
2336 | .flags = ADDR_TYPE_RT, | |
2337 | }, | |
2338 | { } | |
2339 | }; | |
2340 | ||
2341 | static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = { | |
2342 | .master = &am33xx_l3_main_hwmod, | |
2343 | .slave = &am33xx_tptc2_hwmod, | |
2344 | .clk = "l3_gclk", | |
2345 | .addr = am33xx_tptc2_addr_space, | |
2346 | .user = OCP_USER_MPU, | |
2347 | }; | |
2348 | ||
2349 | /* l4 wkup -> uart1 */ | |
a2cfc509 VH |
2350 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = { |
2351 | .master = &am33xx_l4_wkup_hwmod, | |
2352 | .slave = &am33xx_uart1_hwmod, | |
2353 | .clk = "dpll_core_m4_div2_ck", | |
a2cfc509 VH |
2354 | .user = OCP_USER_MPU, |
2355 | }; | |
2356 | ||
2357 | /* l4 ls -> uart2 */ | |
a2cfc509 VH |
2358 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = { |
2359 | .master = &am33xx_l4_ls_hwmod, | |
2360 | .slave = &am33xx_uart2_hwmod, | |
2361 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2362 | .user = OCP_USER_MPU, |
2363 | }; | |
2364 | ||
2365 | /* l4 ls -> uart3 */ | |
a2cfc509 VH |
2366 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = { |
2367 | .master = &am33xx_l4_ls_hwmod, | |
2368 | .slave = &am33xx_uart3_hwmod, | |
2369 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2370 | .user = OCP_USER_MPU, |
2371 | }; | |
2372 | ||
2373 | /* l4 ls -> uart4 */ | |
a2cfc509 VH |
2374 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = { |
2375 | .master = &am33xx_l4_ls_hwmod, | |
2376 | .slave = &am33xx_uart4_hwmod, | |
2377 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2378 | .user = OCP_USER_MPU, |
2379 | }; | |
2380 | ||
2381 | /* l4 ls -> uart5 */ | |
a2cfc509 VH |
2382 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = { |
2383 | .master = &am33xx_l4_ls_hwmod, | |
2384 | .slave = &am33xx_uart5_hwmod, | |
2385 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2386 | .user = OCP_USER_MPU, |
2387 | }; | |
2388 | ||
2389 | /* l4 ls -> uart6 */ | |
a2cfc509 VH |
2390 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = { |
2391 | .master = &am33xx_l4_ls_hwmod, | |
2392 | .slave = &am33xx_uart6_hwmod, | |
2393 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2394 | .user = OCP_USER_MPU, |
2395 | }; | |
2396 | ||
2397 | /* l4 wkup -> wd_timer1 */ | |
a2cfc509 VH |
2398 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = { |
2399 | .master = &am33xx_l4_wkup_hwmod, | |
2400 | .slave = &am33xx_wd_timer1_hwmod, | |
2401 | .clk = "dpll_core_m4_div2_ck", | |
a2cfc509 VH |
2402 | .user = OCP_USER_MPU, |
2403 | }; | |
2404 | ||
2405 | /* usbss */ | |
2406 | /* l3 s -> USBSS interface */ | |
a2cfc509 VH |
2407 | static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = { |
2408 | .master = &am33xx_l3_s_hwmod, | |
2409 | .slave = &am33xx_usbss_hwmod, | |
2410 | .clk = "l3s_gclk", | |
a2cfc509 VH |
2411 | .user = OCP_USER_MPU, |
2412 | .flags = OCPIF_SWSUP_IDLE, | |
2413 | }; | |
2414 | ||
ca903b6f VB |
2415 | /* l3 main -> ocmc */ |
2416 | static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = { | |
2417 | .master = &am33xx_l3_main_hwmod, | |
2418 | .slave = &am33xx_ocmcram_hwmod, | |
2419 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2420 | }; | |
2421 | ||
aec94bf5 MG |
2422 | /* l3 main -> sha0 HIB2 */ |
2423 | static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = { | |
2424 | { | |
2425 | .pa_start = 0x53100000, | |
2426 | .pa_end = 0x53100000 + SZ_512 - 1, | |
2427 | .flags = ADDR_TYPE_RT | |
2428 | }, | |
2429 | { } | |
2430 | }; | |
2431 | ||
2432 | static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = { | |
2433 | .master = &am33xx_l3_main_hwmod, | |
2434 | .slave = &am33xx_sha0_hwmod, | |
2435 | .clk = "sha0_fck", | |
2436 | .addr = am33xx_sha0_addrs, | |
2437 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2438 | }; | |
2439 | ||
1cb804b9 MG |
2440 | /* l3 main -> AES0 HIB2 */ |
2441 | static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = { | |
2442 | { | |
2443 | .pa_start = 0x53500000, | |
2444 | .pa_end = 0x53500000 + SZ_1M - 1, | |
2445 | .flags = ADDR_TYPE_RT | |
2446 | }, | |
2447 | { } | |
2448 | }; | |
2449 | ||
2450 | static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = { | |
2451 | .master = &am33xx_l3_main_hwmod, | |
2452 | .slave = &am33xx_aes0_hwmod, | |
2453 | .clk = "aes0_fck", | |
2454 | .addr = am33xx_aes0_addrs, | |
2455 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2456 | }; | |
2457 | ||
a2cfc509 | 2458 | static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { |
a2cfc509 VH |
2459 | &am33xx_l3_main__emif, |
2460 | &am33xx_mpu__l3_main, | |
2461 | &am33xx_mpu__prcm, | |
2462 | &am33xx_l3_s__l4_ls, | |
2463 | &am33xx_l3_s__l4_wkup, | |
a2cfc509 VH |
2464 | &am33xx_l3_main__l4_hs, |
2465 | &am33xx_l3_main__l3_s, | |
2466 | &am33xx_l3_main__l3_instr, | |
2467 | &am33xx_l3_main__gfx, | |
2468 | &am33xx_l3_s__l3_main, | |
2469 | &am33xx_pruss__l3_main, | |
2470 | &am33xx_wkup_m3__l4_wkup, | |
2471 | &am33xx_gfx__l3_main, | |
2472 | &am33xx_l4_wkup__wkup_m3, | |
2473 | &am33xx_l4_wkup__control, | |
2474 | &am33xx_l4_wkup__smartreflex0, | |
2475 | &am33xx_l4_wkup__smartreflex1, | |
2476 | &am33xx_l4_wkup__uart1, | |
2477 | &am33xx_l4_wkup__timer1, | |
2478 | &am33xx_l4_wkup__rtc, | |
2479 | &am33xx_l4_wkup__i2c1, | |
2480 | &am33xx_l4_wkup__gpio0, | |
2481 | &am33xx_l4_wkup__adc_tsc, | |
2482 | &am33xx_l4_wkup__wd_timer1, | |
2483 | &am33xx_l4_hs__pruss, | |
2484 | &am33xx_l4_per__dcan0, | |
2485 | &am33xx_l4_per__dcan1, | |
2486 | &am33xx_l4_per__gpio1, | |
2487 | &am33xx_l4_per__gpio2, | |
2488 | &am33xx_l4_per__gpio3, | |
2489 | &am33xx_l4_per__i2c2, | |
2490 | &am33xx_l4_per__i2c3, | |
2491 | &am33xx_l4_per__mailbox, | |
2492 | &am33xx_l4_ls__mcasp0, | |
a2cfc509 | 2493 | &am33xx_l4_ls__mcasp1, |
a2cfc509 VH |
2494 | &am33xx_l4_ls__mmc0, |
2495 | &am33xx_l4_ls__mmc1, | |
2496 | &am33xx_l3_s__mmc2, | |
2497 | &am33xx_l4_ls__timer2, | |
2498 | &am33xx_l4_ls__timer3, | |
2499 | &am33xx_l4_ls__timer4, | |
2500 | &am33xx_l4_ls__timer5, | |
2501 | &am33xx_l4_ls__timer6, | |
2502 | &am33xx_l4_ls__timer7, | |
2503 | &am33xx_l3_main__tpcc, | |
2504 | &am33xx_l4_ls__uart2, | |
2505 | &am33xx_l4_ls__uart3, | |
2506 | &am33xx_l4_ls__uart4, | |
2507 | &am33xx_l4_ls__uart5, | |
2508 | &am33xx_l4_ls__uart6, | |
2509 | &am33xx_l4_ls__spinlock, | |
2510 | &am33xx_l4_ls__elm, | |
9652d19a PA |
2511 | &am33xx_l4_ls__epwmss0, |
2512 | &am33xx_epwmss0__ecap0, | |
2513 | &am33xx_epwmss0__eqep0, | |
2514 | &am33xx_epwmss0__ehrpwm0, | |
2515 | &am33xx_l4_ls__epwmss1, | |
2516 | &am33xx_epwmss1__ecap1, | |
2517 | &am33xx_epwmss1__eqep1, | |
2518 | &am33xx_epwmss1__ehrpwm1, | |
2519 | &am33xx_l4_ls__epwmss2, | |
2520 | &am33xx_epwmss2__ecap2, | |
2521 | &am33xx_epwmss2__eqep2, | |
2522 | &am33xx_epwmss2__ehrpwm2, | |
a2cfc509 VH |
2523 | &am33xx_l3_s__gpmc, |
2524 | &am33xx_l3_main__lcdc, | |
2525 | &am33xx_l4_ls__mcspi0, | |
2526 | &am33xx_l4_ls__mcspi1, | |
2527 | &am33xx_l3_main__tptc0, | |
2528 | &am33xx_l3_main__tptc1, | |
2529 | &am33xx_l3_main__tptc2, | |
ca903b6f | 2530 | &am33xx_l3_main__ocmc, |
a2cfc509 VH |
2531 | &am33xx_l3_s__usbss, |
2532 | &am33xx_l4_hs__cpgmac0, | |
70384a6a | 2533 | &am33xx_cpgmac0__mdio, |
aec94bf5 | 2534 | &am33xx_l3_main__sha0, |
1cb804b9 | 2535 | &am33xx_l3_main__aes0, |
a2cfc509 VH |
2536 | NULL, |
2537 | }; | |
2538 | ||
2539 | int __init am33xx_hwmod_init(void) | |
2540 | { | |
2541 | omap_hwmod_init(); | |
2542 | return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs); | |
2543 | } |