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[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_33xx_data.c
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a2cfc509
VH		 1/*
2 * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
3 *
4 * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <plat/omap_hwmod.h>
18#include <plat/cpu.h>
11964f53 19#include <linux/platform_data/gpio-omap.h>
aa817b2e 20#include <linux/platform_data/spi-omap2-mcspi.h>
a2cfc509
VH		 21#include <plat/dma.h>
22#include <plat/mmc.h>
a2cfc509
VH		 23#include <plat/i2c.h>
24
25#include "omap_hwmod_common_data.h"
26
27#include "control.h"
28#include "cm33xx.h"
29#include "prm33xx.h"
30#include "prm-regbits-33xx.h"
31
a2cfc509
VH		 32/*
33 * IP blocks
34 */
35
36/*
37 * 'emif_fw' class
38 * instance(s): emif_fw
39 */
40static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
41 .name = "emif_fw",
42};
43
44/* emif_fw */
45static struct omap_hwmod am33xx_emif_fw_hwmod = {
46 .name = "emif_fw",
47 .class = &am33xx_emif_fw_hwmod_class,
48 .clkdm_name = "l4fw_clkdm",
49 .main_clk = "l4fw_gclk",
50 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
51 .prcm = {
52 .omap4 = {
53 .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
54 .modulemode = MODULEMODE_SWCTRL,
55 },
56 },
57};
58
59/*
60 * 'emif' class
61 * instance(s): emif
62 */
63static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
64 .rev_offs = 0x0000,
65};
66
67static struct omap_hwmod_class am33xx_emif_hwmod_class = {
68 .name = "emif",
69 .sysc = &am33xx_emif_sysc,
70};
71
72static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
73 { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
74 { .irq = -1 },
75};
76
77/* emif */
78static struct omap_hwmod am33xx_emif_hwmod = {
79 .name = "emif",
80 .class = &am33xx_emif_hwmod_class,
81 .clkdm_name = "l3_clkdm",
82 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
83 .mpu_irqs = am33xx_emif_irqs,
84 .main_clk = "dpll_ddr_m2_div2_ck",
85 .prcm = {
86 .omap4 = {
87 .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
88 .modulemode = MODULEMODE_SWCTRL,
89 },
90 },
91};
92
93/*
94 * 'l3' class
95 * instance(s): l3_main, l3_s, l3_instr
96 */
97static struct omap_hwmod_class am33xx_l3_hwmod_class = {
98 .name = "l3",
99};
100
101/* l3_main (l3_fast) */
102static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
103 { .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
104 { .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
105 { .irq = -1 },
106};
107
108static struct omap_hwmod am33xx_l3_main_hwmod = {
109 .name = "l3_main",
110 .class = &am33xx_l3_hwmod_class,
111 .clkdm_name = "l3_clkdm",
112 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
113 .mpu_irqs = am33xx_l3_main_irqs,
114 .main_clk = "l3_gclk",
115 .prcm = {
116 .omap4 = {
117 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
118 .modulemode = MODULEMODE_SWCTRL,
119 },
120 },
121};
122
123/* l3_s */
124static struct omap_hwmod am33xx_l3_s_hwmod = {
125 .name = "l3_s",
126 .class = &am33xx_l3_hwmod_class,
127 .clkdm_name = "l3s_clkdm",
128};
129
130/* l3_instr */
131static struct omap_hwmod am33xx_l3_instr_hwmod = {
132 .name = "l3_instr",
133 .class = &am33xx_l3_hwmod_class,
134 .clkdm_name = "l3_clkdm",
135 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
136 .main_clk = "l3_gclk",
137 .prcm = {
138 .omap4 = {
139 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
140 .modulemode = MODULEMODE_SWCTRL,
141 },
142 },
143};
144
145/*
146 * 'l4' class
147 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
148 */
149static struct omap_hwmod_class am33xx_l4_hwmod_class = {
150 .name = "l4",
151};
152
153/* l4_ls */
154static struct omap_hwmod am33xx_l4_ls_hwmod = {
155 .name = "l4_ls",
156 .class = &am33xx_l4_hwmod_class,
157 .clkdm_name = "l4ls_clkdm",
158 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
159 .main_clk = "l4ls_gclk",
160 .prcm = {
161 .omap4 = {
162 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
163 .modulemode = MODULEMODE_SWCTRL,
164 },
165 },
166};
167
168/* l4_hs */
169static struct omap_hwmod am33xx_l4_hs_hwmod = {
170 .name = "l4_hs",
171 .class = &am33xx_l4_hwmod_class,
172 .clkdm_name = "l4hs_clkdm",
173 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
174 .main_clk = "l4hs_gclk",
175 .prcm = {
176 .omap4 = {
177 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
178 .modulemode = MODULEMODE_SWCTRL,
179 },
180 },
181};
182
183
184/* l4_wkup */
185static struct omap_hwmod am33xx_l4_wkup_hwmod = {
186 .name = "l4_wkup",
187 .class = &am33xx_l4_hwmod_class,
188 .clkdm_name = "l4_wkup_clkdm",
189 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
190 .prcm = {
191 .omap4 = {
192 .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
193 .modulemode = MODULEMODE_SWCTRL,
194 },
195 },
196};
197
198/* l4_fw */
199static struct omap_hwmod am33xx_l4_fw_hwmod = {
200 .name = "l4_fw",
201 .class = &am33xx_l4_hwmod_class,
202 .clkdm_name = "l4fw_clkdm",
203 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
204 .prcm = {
205 .omap4 = {
206 .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
207 .modulemode = MODULEMODE_SWCTRL,
208 },
209 },
210};
211
212/*
213 * 'mpu' class
214 */
215static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
216 .name = "mpu",
217};
218
219/* mpu */
220static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
221 { .name = "emuint", .irq = 0 + OMAP_INTC_START, },
222 { .name = "commtx", .irq = 1 + OMAP_INTC_START, },
223 { .name = "commrx", .irq = 2 + OMAP_INTC_START, },
224 { .name = "bench", .irq = 3 + OMAP_INTC_START, },
225 { .irq = -1 },
226};
227
228static struct omap_hwmod am33xx_mpu_hwmod = {
229 .name = "mpu",
230 .class = &am33xx_mpu_hwmod_class,
231 .clkdm_name = "mpu_clkdm",
232 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
233 .mpu_irqs = am33xx_mpu_irqs,
234 .main_clk = "dpll_mpu_m2_ck",
235 .prcm = {
236 .omap4 = {
237 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
238 .modulemode = MODULEMODE_SWCTRL,
239 },
240 },
241};
242
243/*
244 * 'wakeup m3' class
245 * Wakeup controller sub-system under wakeup domain
246 */
247static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
248 .name = "wkup_m3",
249};
250
251static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
252 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
253};
254
255static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
256 { .name = "txev", .irq = 78 + OMAP_INTC_START, },
257 { .irq = -1 },
258};
259
260/* wkup_m3 */
261static struct omap_hwmod am33xx_wkup_m3_hwmod = {
262 .name = "wkup_m3",
263 .class = &am33xx_wkup_m3_hwmod_class,
264 .clkdm_name = "l4_wkup_aon_clkdm",
265 .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */
266 .mpu_irqs = am33xx_wkup_m3_irqs,
267 .main_clk = "dpll_core_m4_div2_ck",
268 .prcm = {
269 .omap4 = {
270 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
271 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
272 .modulemode = MODULEMODE_SWCTRL,
273 },
274 },
275 .rst_lines = am33xx_wkup_m3_resets,
276 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
277};
278
279/*
280 * 'pru-icss' class
281 * Programmable Real-Time Unit and Industrial Communication Subsystem
282 */
283static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
284 .name = "pruss",
285};
286
287static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
288 { .name = "pruss", .rst_shift = 1 },
289};
290
291static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
292 { .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
293 { .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
294 { .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
295 { .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
296 { .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
297 { .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
298 { .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
299 { .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
300 { .irq = -1 },
301};
302
303/* pru-icss */
304/* Pseudo hwmod for reset control purpose only */
305static struct omap_hwmod am33xx_pruss_hwmod = {
306 .name = "pruss",
307 .class = &am33xx_pruss_hwmod_class,
308 .clkdm_name = "pruss_ocp_clkdm",
309 .mpu_irqs = am33xx_pruss_irqs,
310 .main_clk = "pruss_ocp_gclk",
311 .prcm = {
312 .omap4 = {
313 .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
314 .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
315 .modulemode = MODULEMODE_SWCTRL,
316 },
317 },
318 .rst_lines = am33xx_pruss_resets,
319 .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
320};
321
322/* gfx */
323/* Pseudo hwmod for reset control purpose only */
324static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
325 .name = "gfx",
326};
327
328static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
329 { .name = "gfx", .rst_shift = 0 },
330};
331
332static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
333 { .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
334 { .irq = -1 },
335};
336
337static struct omap_hwmod am33xx_gfx_hwmod = {
338 .name = "gfx",
339 .class = &am33xx_gfx_hwmod_class,
340 .clkdm_name = "gfx_l3_clkdm",
341 .mpu_irqs = am33xx_gfx_irqs,
342 .main_clk = "gfx_fck_div_ck",
343 .prcm = {
344 .omap4 = {
345 .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
346 .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
347 .modulemode = MODULEMODE_SWCTRL,
348 },
349 },
350 .rst_lines = am33xx_gfx_resets,
351 .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
352};
353
354/*
355 * 'prcm' class
356 * power and reset manager (whole prcm infrastructure)
357 */
358static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
359 .name = "prcm",
360};
361
362/* prcm */
363static struct omap_hwmod am33xx_prcm_hwmod = {
364 .name = "prcm",
365 .class = &am33xx_prcm_hwmod_class,
366 .clkdm_name = "l4_wkup_clkdm",
367};
368
369/*
370 * 'adc/tsc' class
371 * TouchScreen Controller (Anolog-To-Digital Converter)
372 */
373static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
374 .rev_offs = 0x00,
375 .sysc_offs = 0x10,
376 .sysc_flags = SYSC_HAS_SIDLEMODE,
377 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
378 SIDLE_SMART_WKUP),
379 .sysc_fields = &omap_hwmod_sysc_type2,
380};
381
382static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
383 .name = "adc_tsc",
384 .sysc = &am33xx_adc_tsc_sysc,
385};
386
387static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
388 { .irq = 16 + OMAP_INTC_START, },
389 { .irq = -1 },
390};
391
392static struct omap_hwmod am33xx_adc_tsc_hwmod = {
393 .name = "adc_tsc",
394 .class = &am33xx_adc_tsc_hwmod_class,
395 .clkdm_name = "l4_wkup_clkdm",
396 .mpu_irqs = am33xx_adc_tsc_irqs,
397 .main_clk = "adc_tsc_fck",
398 .prcm = {
399 .omap4 = {
400 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
401 .modulemode = MODULEMODE_SWCTRL,
402 },
403 },
404};
405
406/*
407 * Modules omap_hwmod structures
408 *
409 * The following IPs are excluded for the moment because:
410 * - They do not need an explicit SW control using omap_hwmod API.
411 * - They still need to be validated with the driver
412 * properly adapted to omap_hwmod / omap_device
413 *
414 * - cEFUSE (doesn't fall under any ocp_if)
415 * - clkdiv32k
416 * - debugss
417 * - ocmc ram
418 * - ocp watch point
419 * - aes0
420 * - sha0
421 */
422#if 0
423/*
424 * 'cefuse' class
425 */
426static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
427 .name = "cefuse",
428};
429
430static struct omap_hwmod am33xx_cefuse_hwmod = {
431 .name = "cefuse",
432 .class = &am33xx_cefuse_hwmod_class,
433 .clkdm_name = "l4_cefuse_clkdm",
434 .main_clk = "cefuse_fck",
435 .prcm = {
436 .omap4 = {
437 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
438 .modulemode = MODULEMODE_SWCTRL,
439 },
440 },
441};
442
443/*
444 * 'clkdiv32k' class
445 */
446static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
447 .name = "clkdiv32k",
448};
449
450static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
451 .name = "clkdiv32k",
452 .class = &am33xx_clkdiv32k_hwmod_class,
453 .clkdm_name = "clk_24mhz_clkdm",
454 .main_clk = "clkdiv32k_ick",
455 .prcm = {
456 .omap4 = {
457 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
458 .modulemode = MODULEMODE_SWCTRL,
459 },
460 },
461};
462
463/*
464 * 'debugss' class
465 * debug sub system
466 */
467static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
468 .name = "debugss",
469};
470
471static struct omap_hwmod am33xx_debugss_hwmod = {
472 .name = "debugss",
473 .class = &am33xx_debugss_hwmod_class,
474 .clkdm_name = "l3_aon_clkdm",
475 .main_clk = "debugss_ick",
476 .prcm = {
477 .omap4 = {
478 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
479 .modulemode = MODULEMODE_SWCTRL,
480 },
481 },
482};
483
484/* ocmcram */
485static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
486 .name = "ocmcram",
487};
488
489static struct omap_hwmod am33xx_ocmcram_hwmod = {
490 .name = "ocmcram",
491 .class = &am33xx_ocmcram_hwmod_class,
492 .clkdm_name = "l3_clkdm",
493 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
494 .main_clk = "l3_gclk",
495 .prcm = {
496 .omap4 = {
497 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
498 .modulemode = MODULEMODE_SWCTRL,
499 },
500 },
501};
502
503/* ocpwp */
504static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
505 .name = "ocpwp",
506};
507
508static struct omap_hwmod am33xx_ocpwp_hwmod = {
509 .name = "ocpwp",
510 .class = &am33xx_ocpwp_hwmod_class,
511 .clkdm_name = "l4ls_clkdm",
512 .main_clk = "l4ls_gclk",
513 .prcm = {
514 .omap4 = {
515 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
516 .modulemode = MODULEMODE_SWCTRL,
517 },
518 },
519};
520
521/*
522 * 'aes' class
523 */
524static struct omap_hwmod_class am33xx_aes_hwmod_class = {
525 .name = "aes",
526};
527
528static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
529 { .irq = 102 + OMAP_INTC_START, },
530 { .irq = -1 },
531};
532
533static struct omap_hwmod am33xx_aes0_hwmod = {
534 .name = "aes0",
535 .class = &am33xx_aes_hwmod_class,
536 .clkdm_name = "l3_clkdm",
537 .mpu_irqs = am33xx_aes0_irqs,
538 .main_clk = "l3_gclk",
539 .prcm = {
540 .omap4 = {
541 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
542 .modulemode = MODULEMODE_SWCTRL,
543 },
544 },
545};
546
547/* sha0 */
548static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
549 .name = "sha0",
550};
551
552static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
553 { .irq = 108 + OMAP_INTC_START, },
554 { .irq = -1 },
555};
556
557static struct omap_hwmod am33xx_sha0_hwmod = {
558 .name = "sha0",
559 .class = &am33xx_sha0_hwmod_class,
560 .clkdm_name = "l3_clkdm",
561 .mpu_irqs = am33xx_sha0_irqs,
562 .main_clk = "l3_gclk",
563 .prcm = {
564 .omap4 = {
565 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
566 .modulemode = MODULEMODE_SWCTRL,
567 },
568 },
569};
570
571#endif
572
573/* 'smartreflex' class */
574static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
575 .name = "smartreflex",
576};
577
578/* smartreflex0 */
579static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
580 { .irq = 120 + OMAP_INTC_START, },
581 { .irq = -1 },
582};
583
584static struct omap_hwmod am33xx_smartreflex0_hwmod = {
585 .name = "smartreflex0",
586 .class = &am33xx_smartreflex_hwmod_class,
587 .clkdm_name = "l4_wkup_clkdm",
588 .mpu_irqs = am33xx_smartreflex0_irqs,
589 .main_clk = "smartreflex0_fck",
590 .prcm = {
591 .omap4 = {
592 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
593 .modulemode = MODULEMODE_SWCTRL,
594 },
595 },
596};
597
598/* smartreflex1 */
599static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
600 { .irq = 121 + OMAP_INTC_START, },
601 { .irq = -1 },
602};
603
604static struct omap_hwmod am33xx_smartreflex1_hwmod = {
605 .name = "smartreflex1",
606 .class = &am33xx_smartreflex_hwmod_class,
607 .clkdm_name = "l4_wkup_clkdm",
608 .mpu_irqs = am33xx_smartreflex1_irqs,
609 .main_clk = "smartreflex1_fck",
610 .prcm = {
611 .omap4 = {
612 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
613 .modulemode = MODULEMODE_SWCTRL,
614 },
615 },
616};
617
618/*
619 * 'control' module class
620 */
621static struct omap_hwmod_class am33xx_control_hwmod_class = {
622 .name = "control",
623};
624
625static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
626 { .irq = 8 + OMAP_INTC_START, },
627 { .irq = -1 },
628};
629
630static struct omap_hwmod am33xx_control_hwmod = {
631 .name = "control",
632 .class = &am33xx_control_hwmod_class,
633 .clkdm_name = "l4_wkup_clkdm",
634 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
635 .mpu_irqs = am33xx_control_irqs,
636 .main_clk = "dpll_core_m4_div2_ck",
637 .prcm = {
638 .omap4 = {
639 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
640 .modulemode = MODULEMODE_SWCTRL,
641 },
642 },
643};
644
645/*
646 * 'cpgmac' class
647 * cpsw/cpgmac sub system
648 */
649static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
650 .rev_offs = 0x0,
651 .sysc_offs = 0x8,
652 .syss_offs = 0x4,
653 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
654 SYSS_HAS_RESET_STATUS),
655 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
656 MSTANDBY_NO),
657 .sysc_fields = &omap_hwmod_sysc_type3,
658};
659
660static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
661 .name = "cpgmac0",
662 .sysc = &am33xx_cpgmac_sysc,
663};
664
665static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
666 { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
667 { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
668 { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
669 { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
670 { .irq = -1 },
671};
672
673static struct omap_hwmod am33xx_cpgmac0_hwmod = {
674 .name = "cpgmac0",
675 .class = &am33xx_cpgmac0_hwmod_class,
676 .clkdm_name = "cpsw_125mhz_clkdm",
677 .mpu_irqs = am33xx_cpgmac0_irqs,
678 .main_clk = "cpsw_125mhz_gclk",
679 .prcm = {
680 .omap4 = {
681 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
682 .modulemode = MODULEMODE_SWCTRL,
683 },
684 },
685};
686
687/*
688 * dcan class
689 */
690static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
691 .name = "d_can",
692};
693
694/* dcan0 */
695static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
696 { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
697 { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
698 { .irq = -1 },
699};
700
701static struct omap_hwmod am33xx_dcan0_hwmod = {
702 .name = "d_can0",
703 .class = &am33xx_dcan_hwmod_class,
704 .clkdm_name = "l4ls_clkdm",
705 .mpu_irqs = am33xx_dcan0_irqs,
706 .main_clk = "dcan0_fck",
707 .prcm = {
708 .omap4 = {
709 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
710 .modulemode = MODULEMODE_SWCTRL,
711 },
712 },
713};
714
715/* dcan1 */
716static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
717 { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
718 { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
719 { .irq = -1 },
720};
721static struct omap_hwmod am33xx_dcan1_hwmod = {
722 .name = "d_can1",
723 .class = &am33xx_dcan_hwmod_class,
724 .clkdm_name = "l4ls_clkdm",
725 .mpu_irqs = am33xx_dcan1_irqs,
726 .main_clk = "dcan1_fck",
727 .prcm = {
728 .omap4 = {
729 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
730 .modulemode = MODULEMODE_SWCTRL,
731 },
732 },
733};
734
735/* elm */
736static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
737 .rev_offs = 0x0000,
738 .sysc_offs = 0x0010,
739 .syss_offs = 0x0014,
740 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
741 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
742 SYSS_HAS_RESET_STATUS),
743 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
744 .sysc_fields = &omap_hwmod_sysc_type1,
745};
746
747static struct omap_hwmod_class am33xx_elm_hwmod_class = {
748 .name = "elm",
749 .sysc = &am33xx_elm_sysc,
750};
751
752static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
753 { .irq = 4 + OMAP_INTC_START, },
754 { .irq = -1 },
755};
756
757static struct omap_hwmod am33xx_elm_hwmod = {
758 .name = "elm",
759 .class = &am33xx_elm_hwmod_class,
760 .clkdm_name = "l4ls_clkdm",
761 .mpu_irqs = am33xx_elm_irqs,
762 .main_clk = "l4ls_gclk",
763 .prcm = {
764 .omap4 = {
765 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
766 .modulemode = MODULEMODE_SWCTRL,
767 },
768 },
769};
770
771/*
772 * 'epwmss' class: ecap0,1,2, ehrpwm0,1,2
773 */
774static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
775 .rev_offs = 0x0,
776 .sysc_offs = 0x4,
777 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
778 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
779 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
780 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
781 .sysc_fields = &omap_hwmod_sysc_type2,
782};
783
784static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
785 .name = "epwmss",
786 .sysc = &am33xx_epwmss_sysc,
787};
788
789/* ehrpwm0 */
790static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
791 { .name = "int", .irq = 86 + OMAP_INTC_START, },
792 { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
793 { .irq = -1 },
794};
795
796static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
797 .name = "ehrpwm0",
798 .class = &am33xx_epwmss_hwmod_class,
799 .clkdm_name = "l4ls_clkdm",
800 .mpu_irqs = am33xx_ehrpwm0_irqs,
801 .main_clk = "l4ls_gclk",
802 .prcm = {
803 .omap4 = {
804 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
805 .modulemode = MODULEMODE_SWCTRL,
806 },
807 },
808};
809
810/* ehrpwm1 */
811static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
812 { .name = "int", .irq = 87 + OMAP_INTC_START, },
813 { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
814 { .irq = -1 },
815};
816
817static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
818 .name = "ehrpwm1",
819 .class = &am33xx_epwmss_hwmod_class,
820 .clkdm_name = "l4ls_clkdm",
821 .mpu_irqs = am33xx_ehrpwm1_irqs,
822 .main_clk = "l4ls_gclk",
823 .prcm = {
824 .omap4 = {
825 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
826 .modulemode = MODULEMODE_SWCTRL,
827 },
828 },
829};
830
831/* ehrpwm2 */
832static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
833 { .name = "int", .irq = 39 + OMAP_INTC_START, },
834 { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
835 { .irq = -1 },
836};
837
838static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
839 .name = "ehrpwm2",
840 .class = &am33xx_epwmss_hwmod_class,
841 .clkdm_name = "l4ls_clkdm",
842 .mpu_irqs = am33xx_ehrpwm2_irqs,
843 .main_clk = "l4ls_gclk",
844 .prcm = {
845 .omap4 = {
846 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
847 .modulemode = MODULEMODE_SWCTRL,
848 },
849 },
850};
851
852/* ecap0 */
853static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
854 { .irq = 31 + OMAP_INTC_START, },
855 { .irq = -1 },
856};
857
858static struct omap_hwmod am33xx_ecap0_hwmod = {
859 .name = "ecap0",
860 .class = &am33xx_epwmss_hwmod_class,
861 .clkdm_name = "l4ls_clkdm",
862 .mpu_irqs = am33xx_ecap0_irqs,
863 .main_clk = "l4ls_gclk",
864 .prcm = {
865 .omap4 = {
866 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
867 .modulemode = MODULEMODE_SWCTRL,
868 },
869 },
870};
871
872/* ecap1 */
873static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
874 { .irq = 47 + OMAP_INTC_START, },
875 { .irq = -1 },
876};
877
878static struct omap_hwmod am33xx_ecap1_hwmod = {
879 .name = "ecap1",
880 .class = &am33xx_epwmss_hwmod_class,
881 .clkdm_name = "l4ls_clkdm",
882 .mpu_irqs = am33xx_ecap1_irqs,
883 .main_clk = "l4ls_gclk",
884 .prcm = {
885 .omap4 = {
886 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
887 .modulemode = MODULEMODE_SWCTRL,
888 },
889 },
890};
891
892/* ecap2 */
893static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
894 { .irq = 61 + OMAP_INTC_START, },
895 { .irq = -1 },
896};
897
898static struct omap_hwmod am33xx_ecap2_hwmod = {
899 .name = "ecap2",
900 .mpu_irqs = am33xx_ecap2_irqs,
901 .class = &am33xx_epwmss_hwmod_class,
902 .clkdm_name = "l4ls_clkdm",
903 .main_clk = "l4ls_gclk",
904 .prcm = {
905 .omap4 = {
906 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
907 .modulemode = MODULEMODE_SWCTRL,
908 },
909 },
910};
911
912/*
913 * 'gpio' class: for gpio 0,1,2,3
914 */
915static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
916 .rev_offs = 0x0000,
917 .sysc_offs = 0x0010,
918 .syss_offs = 0x0114,
919 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
920 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
921 SYSS_HAS_RESET_STATUS),
922 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
923 SIDLE_SMART_WKUP),
924 .sysc_fields = &omap_hwmod_sysc_type1,
925};
926
927static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
928 .name = "gpio",
929 .sysc = &am33xx_gpio_sysc,
930 .rev = 2,
931};
932
933static struct omap_gpio_dev_attr gpio_dev_attr = {
934 .bank_width = 32,
935 .dbck_flag = true,
936};
937
938/* gpio0 */
939static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
940 { .role = "dbclk", .clk = "gpio0_dbclk" },
941};
942
943static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
944 { .irq = 96 + OMAP_INTC_START, },
945 { .irq = -1 },
946};
947
948static struct omap_hwmod am33xx_gpio0_hwmod = {
949 .name = "gpio1",
950 .class = &am33xx_gpio_hwmod_class,
951 .clkdm_name = "l4_wkup_clkdm",
952 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
953 .mpu_irqs = am33xx_gpio0_irqs,
954 .main_clk = "dpll_core_m4_div2_ck",
955 .prcm = {
956 .omap4 = {
957 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
958 .modulemode = MODULEMODE_SWCTRL,
959 },
960 },
961 .opt_clks = gpio0_opt_clks,
962 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
963 .dev_attr = &gpio_dev_attr,
964};
965
966/* gpio1 */
967static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
968 { .irq = 98 + OMAP_INTC_START, },
969 { .irq = -1 },
970};
971
972static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
973 { .role = "dbclk", .clk = "gpio1_dbclk" },
974};
975
976static struct omap_hwmod am33xx_gpio1_hwmod = {
977 .name = "gpio2",
978 .class = &am33xx_gpio_hwmod_class,
979 .clkdm_name = "l4ls_clkdm",
980 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
981 .mpu_irqs = am33xx_gpio1_irqs,
982 .main_clk = "l4ls_gclk",
983 .prcm = {
984 .omap4 = {
985 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
986 .modulemode = MODULEMODE_SWCTRL,
987 },
988 },
989 .opt_clks = gpio1_opt_clks,
990 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
991 .dev_attr = &gpio_dev_attr,
992};
993
994/* gpio2 */
995static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
996 { .irq = 32 + OMAP_INTC_START, },
997 { .irq = -1 },
998};
999
1000static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1001 { .role = "dbclk", .clk = "gpio2_dbclk" },
1002};
1003
1004static struct omap_hwmod am33xx_gpio2_hwmod = {
1005 .name = "gpio3",
1006 .class = &am33xx_gpio_hwmod_class,
1007 .clkdm_name = "l4ls_clkdm",
1008 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1009 .mpu_irqs = am33xx_gpio2_irqs,
1010 .main_clk = "l4ls_gclk",
1011 .prcm = {
1012 .omap4 = {
1013 .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
1014 .modulemode = MODULEMODE_SWCTRL,
1015 },
1016 },
1017 .opt_clks = gpio2_opt_clks,
1018 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1019 .dev_attr = &gpio_dev_attr,
1020};
1021
1022/* gpio3 */
1023static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
1024 { .irq = 62 + OMAP_INTC_START, },
1025 { .irq = -1 },
1026};
1027
1028static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1029 { .role = "dbclk", .clk = "gpio3_dbclk" },
1030};
1031
1032static struct omap_hwmod am33xx_gpio3_hwmod = {
1033 .name = "gpio4",
1034 .class = &am33xx_gpio_hwmod_class,
1035 .clkdm_name = "l4ls_clkdm",
1036 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1037 .mpu_irqs = am33xx_gpio3_irqs,
1038 .main_clk = "l4ls_gclk",
1039 .prcm = {
1040 .omap4 = {
1041 .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
1042 .modulemode = MODULEMODE_SWCTRL,
1043 },
1044 },
1045 .opt_clks = gpio3_opt_clks,
1046 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1047 .dev_attr = &gpio_dev_attr,
1048};
1049
1050/* gpmc */
1051static struct omap_hwmod_class_sysconfig gpmc_sysc = {
1052 .rev_offs = 0x0,
1053 .sysc_offs = 0x10,
1054 .syss_offs = 0x14,
1055 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1056 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1057 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1058 .sysc_fields = &omap_hwmod_sysc_type1,
1059};
1060
1061static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
1062 .name = "gpmc",
1063 .sysc = &gpmc_sysc,
1064};
1065
1066static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
1067 { .irq = 100 + OMAP_INTC_START, },
1068 { .irq = -1 },
1069};
1070
1071static struct omap_hwmod am33xx_gpmc_hwmod = {
1072 .name = "gpmc",
1073 .class = &am33xx_gpmc_hwmod_class,
1074 .clkdm_name = "l3s_clkdm",
1075 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1076 .mpu_irqs = am33xx_gpmc_irqs,
1077 .main_clk = "l3s_gclk",
1078 .prcm = {
1079 .omap4 = {
1080 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
1081 .modulemode = MODULEMODE_SWCTRL,
1082 },
1083 },
1084};
1085
1086/* 'i2c' class */
1087static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
1088 .sysc_offs = 0x0010,
1089 .syss_offs = 0x0090,
1090 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1091 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1092 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1093 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1094 SIDLE_SMART_WKUP),
1095 .sysc_fields = &omap_hwmod_sysc_type1,
1096};
1097
1098static struct omap_hwmod_class i2c_class = {
1099 .name = "i2c",
1100 .sysc = &am33xx_i2c_sysc,
1101 .rev = OMAP_I2C_IP_VERSION_2,
1102 .reset = &omap_i2c_reset,
1103};
1104
1105static struct omap_i2c_dev_attr i2c_dev_attr = {
1106 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1107 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1108};
1109
1110/* i2c1 */
1111static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1112 { .irq = 70 + OMAP_INTC_START, },
1113 { .irq = -1 },
1114};
1115
1116static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
1117 { .name = "tx", .dma_req = 0, },
1118 { .name = "rx", .dma_req = 0, },
1119 { .dma_req = -1 }
1120};
1121
1122static struct omap_hwmod am33xx_i2c1_hwmod = {
1123 .name = "i2c1",
1124 .class = &i2c_class,
1125 .clkdm_name = "l4_wkup_clkdm",
1126 .mpu_irqs = i2c1_mpu_irqs,
1127 .sdma_reqs = i2c1_edma_reqs,
1128 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1129 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1130 .prcm = {
1131 .omap4 = {
1132 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
1133 .modulemode = MODULEMODE_SWCTRL,
1134 },
1135 },
1136 .dev_attr = &i2c_dev_attr,
1137};
1138
1139/* i2c1 */
1140static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1141 { .irq = 71 + OMAP_INTC_START, },
1142 { .irq = -1 },
1143};
1144
1145static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
1146 { .name = "tx", .dma_req = 0, },
1147 { .name = "rx", .dma_req = 0, },
1148 { .dma_req = -1 }
1149};
1150
1151static struct omap_hwmod am33xx_i2c2_hwmod = {
1152 .name = "i2c2",
1153 .class = &i2c_class,
1154 .clkdm_name = "l4ls_clkdm",
1155 .mpu_irqs = i2c2_mpu_irqs,
1156 .sdma_reqs = i2c2_edma_reqs,
1157 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1158 .main_clk = "dpll_per_m2_div4_ck",
1159 .prcm = {
1160 .omap4 = {
1161 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
1162 .modulemode = MODULEMODE_SWCTRL,
1163 },
1164 },
1165 .dev_attr = &i2c_dev_attr,
1166};
1167
1168/* i2c3 */
1169static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
1170 { .name = "tx", .dma_req = 0, },
1171 { .name = "rx", .dma_req = 0, },
1172 { .dma_req = -1 }
1173};
1174
1175static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1176 { .irq = 30 + OMAP_INTC_START, },
1177 { .irq = -1 },
1178};
1179
1180static struct omap_hwmod am33xx_i2c3_hwmod = {
1181 .name = "i2c3",
1182 .class = &i2c_class,
1183 .clkdm_name = "l4ls_clkdm",
1184 .mpu_irqs = i2c3_mpu_irqs,
1185 .sdma_reqs = i2c3_edma_reqs,
1186 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1187 .main_clk = "dpll_per_m2_div4_ck",
1188 .prcm = {
1189 .omap4 = {
1190 .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
1191 .modulemode = MODULEMODE_SWCTRL,
1192 },
1193 },
1194 .dev_attr = &i2c_dev_attr,
1195};
1196
1197
1198/* lcdc */
1199static struct omap_hwmod_class_sysconfig lcdc_sysc = {
1200 .rev_offs = 0x0,
1201 .sysc_offs = 0x54,
1202 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
1203 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1204 .sysc_fields = &omap_hwmod_sysc_type2,
1205};
1206
1207static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1208 .name = "lcdc",
1209 .sysc = &lcdc_sysc,
1210};
1211
1212static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1213 { .irq = 36 + OMAP_INTC_START, },
1214 { .irq = -1 },
1215};
1216
1217static struct omap_hwmod am33xx_lcdc_hwmod = {
1218 .name = "lcdc",
1219 .class = &am33xx_lcdc_hwmod_class,
1220 .clkdm_name = "lcdc_clkdm",
1221 .mpu_irqs = am33xx_lcdc_irqs,
1222 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1223 .main_clk = "lcd_gclk",
1224 .prcm = {
1225 .omap4 = {
1226 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1227 .modulemode = MODULEMODE_SWCTRL,
1228 },
1229 },
1230};
1231
1232/*
1233 * 'mailbox' class
1234 * mailbox module allowing communication between the on-chip processors using a
1235 * queued mailbox-interrupt mechanism.
1236 */
1237static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1238 .rev_offs = 0x0000,
1239 .sysc_offs = 0x0010,
1240 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1241 SYSC_HAS_SOFTRESET),
1242 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1243 .sysc_fields = &omap_hwmod_sysc_type2,
1244};
1245
1246static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1247 .name = "mailbox",
1248 .sysc = &am33xx_mailbox_sysc,
1249};
1250
1251static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1252 { .irq = 77 + OMAP_INTC_START, },
1253 { .irq = -1 },
1254};
1255
1256static struct omap_hwmod am33xx_mailbox_hwmod = {
1257 .name = "mailbox",
1258 .class = &am33xx_mailbox_hwmod_class,
1259 .clkdm_name = "l4ls_clkdm",
1260 .mpu_irqs = am33xx_mailbox_irqs,
1261 .main_clk = "l4ls_gclk",
1262 .prcm = {
1263 .omap4 = {
1264 .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1265 .modulemode = MODULEMODE_SWCTRL,
1266 },
1267 },
1268};
1269
1270/*
1271 * 'mcasp' class
1272 */
1273static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
1274 .rev_offs = 0x0,
1275 .sysc_offs = 0x4,
1276 .sysc_flags = SYSC_HAS_SIDLEMODE,
1277 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1278 .sysc_fields = &omap_hwmod_sysc_type3,
1279};
1280
1281static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1282 .name = "mcasp",
1283 .sysc = &am33xx_mcasp_sysc,
1284};
1285
1286/* mcasp0 */
1287static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1288 { .name = "ax", .irq = 80 + OMAP_INTC_START, },
1289 { .name = "ar", .irq = 81 + OMAP_INTC_START, },
1290 { .irq = -1 },
1291};
1292
1293static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
1294 { .name = "tx", .dma_req = 8, },
1295 { .name = "rx", .dma_req = 9, },
1296 { .dma_req = -1 }
1297};
1298
1299static struct omap_hwmod am33xx_mcasp0_hwmod = {
1300 .name = "mcasp0",
1301 .class = &am33xx_mcasp_hwmod_class,
1302 .clkdm_name = "l3s_clkdm",
1303 .mpu_irqs = am33xx_mcasp0_irqs,
1304 .sdma_reqs = am33xx_mcasp0_edma_reqs,
1305 .main_clk = "mcasp0_fck",
1306 .prcm = {
1307 .omap4 = {
1308 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1309 .modulemode = MODULEMODE_SWCTRL,
1310 },
1311 },
1312};
1313
1314/* mcasp1 */
1315static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
1316 { .name = "ax", .irq = 82 + OMAP_INTC_START, },
1317 { .name = "ar", .irq = 83 + OMAP_INTC_START, },
1318 { .irq = -1 },
1319};
1320
1321static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
1322 { .name = "tx", .dma_req = 10, },
1323 { .name = "rx", .dma_req = 11, },
1324 { .dma_req = -1 }
1325};
1326
1327static struct omap_hwmod am33xx_mcasp1_hwmod = {
1328 .name = "mcasp1",
1329 .class = &am33xx_mcasp_hwmod_class,
1330 .clkdm_name = "l3s_clkdm",
1331 .mpu_irqs = am33xx_mcasp1_irqs,
1332 .sdma_reqs = am33xx_mcasp1_edma_reqs,
1333 .main_clk = "mcasp1_fck",
1334 .prcm = {
1335 .omap4 = {
1336 .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
1337 .modulemode = MODULEMODE_SWCTRL,
1338 },
1339 },
1340};
1341
1342/* 'mmc' class */
1343static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1344 .rev_offs = 0x1fc,
1345 .sysc_offs = 0x10,
1346 .syss_offs = 0x14,
1347 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1348 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1349 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1350 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1351 .sysc_fields = &omap_hwmod_sysc_type1,
1352};
1353
1354static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1355 .name = "mmc",
1356 .sysc = &am33xx_mmc_sysc,
1357};
1358
1359/* mmc0 */
1360static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1361 { .irq = 64 + OMAP_INTC_START, },
1362 { .irq = -1 },
1363};
1364
1365static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1366 { .name = "tx", .dma_req = 24, },
1367 { .name = "rx", .dma_req = 25, },
1368 { .dma_req = -1 }
1369};
1370
1371static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1372 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1373};
1374
1375static struct omap_hwmod am33xx_mmc0_hwmod = {
1376 .name = "mmc1",
1377 .class = &am33xx_mmc_hwmod_class,
1378 .clkdm_name = "l4ls_clkdm",
1379 .mpu_irqs = am33xx_mmc0_irqs,
1380 .sdma_reqs = am33xx_mmc0_edma_reqs,
1381 .main_clk = "mmc_clk",
1382 .prcm = {
1383 .omap4 = {
1384 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1385 .modulemode = MODULEMODE_SWCTRL,
1386 },
1387 },
1388 .dev_attr = &am33xx_mmc0_dev_attr,
1389};
1390
1391/* mmc1 */
1392static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1393 { .irq = 28 + OMAP_INTC_START, },
1394 { .irq = -1 },
1395};
1396
1397static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1398 { .name = "tx", .dma_req = 2, },
1399 { .name = "rx", .dma_req = 3, },
1400 { .dma_req = -1 }
1401};
1402
1403static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1404 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1405};
1406
1407static struct omap_hwmod am33xx_mmc1_hwmod = {
1408 .name = "mmc2",
1409 .class = &am33xx_mmc_hwmod_class,
1410 .clkdm_name = "l4ls_clkdm",
1411 .mpu_irqs = am33xx_mmc1_irqs,
1412 .sdma_reqs = am33xx_mmc1_edma_reqs,
1413 .main_clk = "mmc_clk",
1414 .prcm = {
1415 .omap4 = {
1416 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1417 .modulemode = MODULEMODE_SWCTRL,
1418 },
1419 },
1420 .dev_attr = &am33xx_mmc1_dev_attr,
1421};
1422
1423/* mmc2 */
1424static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1425 { .irq = 29 + OMAP_INTC_START, },
1426 { .irq = -1 },
1427};
1428
1429static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1430 { .name = "tx", .dma_req = 64, },
1431 { .name = "rx", .dma_req = 65, },
1432 { .dma_req = -1 }
1433};
1434
1435static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1436 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1437};
1438static struct omap_hwmod am33xx_mmc2_hwmod = {
1439 .name = "mmc3",
1440 .class = &am33xx_mmc_hwmod_class,
1441 .clkdm_name = "l3s_clkdm",
1442 .mpu_irqs = am33xx_mmc2_irqs,
1443 .sdma_reqs = am33xx_mmc2_edma_reqs,
1444 .main_clk = "mmc_clk",
1445 .prcm = {
1446 .omap4 = {
1447 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1448 .modulemode = MODULEMODE_SWCTRL,
1449 },
1450 },
1451 .dev_attr = &am33xx_mmc2_dev_attr,
1452};
1453
1454/*
1455 * 'rtc' class
1456 * rtc subsystem
1457 */
1458static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
1459 .rev_offs = 0x0074,
1460 .sysc_offs = 0x0078,
1461 .sysc_flags = SYSC_HAS_SIDLEMODE,
1462 .idlemodes = (SIDLE_FORCE | SIDLE_NO |
1463 SIDLE_SMART | SIDLE_SMART_WKUP),
1464 .sysc_fields = &omap_hwmod_sysc_type3,
1465};
1466
1467static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1468 .name = "rtc",
1469 .sysc = &am33xx_rtc_sysc,
1470};
1471
1472static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1473 { .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
1474 { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
1475 { .irq = -1 },
1476};
1477
1478static struct omap_hwmod am33xx_rtc_hwmod = {
1479 .name = "rtc",
1480 .class = &am33xx_rtc_hwmod_class,
1481 .clkdm_name = "l4_rtc_clkdm",
1482 .mpu_irqs = am33xx_rtc_irqs,
1483 .main_clk = "clk_32768_ck",
1484 .prcm = {
1485 .omap4 = {
1486 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1487 .modulemode = MODULEMODE_SWCTRL,
1488 },
1489 },
1490};
1491
1492/* 'spi' class */
1493static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1494 .rev_offs = 0x0000,
1495 .sysc_offs = 0x0110,
1496 .syss_offs = 0x0114,
1497 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1498 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1499 SYSS_HAS_RESET_STATUS),
1500 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1501 .sysc_fields = &omap_hwmod_sysc_type1,
1502};
1503
1504static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1505 .name = "mcspi",
1506 .sysc = &am33xx_mcspi_sysc,
1507 .rev = OMAP4_MCSPI_REV,
1508};
1509
1510/* spi0 */
1511static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1512 { .irq = 65 + OMAP_INTC_START, },
1513 { .irq = -1 },
1514};
1515
1516static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
1517 { .name = "rx0", .dma_req = 17 },
1518 { .name = "tx0", .dma_req = 16 },
1519 { .name = "rx1", .dma_req = 19 },
1520 { .name = "tx1", .dma_req = 18 },
1521 { .dma_req = -1 }
1522};
1523
1524static struct omap2_mcspi_dev_attr mcspi_attrib = {
1525 .num_chipselect = 2,
1526};
1527static struct omap_hwmod am33xx_spi0_hwmod = {
1528 .name = "spi0",
1529 .class = &am33xx_spi_hwmod_class,
1530 .clkdm_name = "l4ls_clkdm",
1531 .mpu_irqs = am33xx_spi0_irqs,
1532 .sdma_reqs = am33xx_mcspi0_edma_reqs,
1533 .main_clk = "dpll_per_m2_div4_ck",
1534 .prcm = {
1535 .omap4 = {
1536 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1537 .modulemode = MODULEMODE_SWCTRL,
1538 },
1539 },
1540 .dev_attr = &mcspi_attrib,
1541};
1542
1543/* spi1 */
1544static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1545 { .irq = 125 + OMAP_INTC_START, },
1546 { .irq = -1 },
1547};
1548
1549static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
1550 { .name = "rx0", .dma_req = 43 },
1551 { .name = "tx0", .dma_req = 42 },
1552 { .name = "rx1", .dma_req = 45 },
1553 { .name = "tx1", .dma_req = 44 },
1554 { .dma_req = -1 }
1555};
1556
1557static struct omap_hwmod am33xx_spi1_hwmod = {
1558 .name = "spi1",
1559 .class = &am33xx_spi_hwmod_class,
1560 .clkdm_name = "l4ls_clkdm",
1561 .mpu_irqs = am33xx_spi1_irqs,
1562 .sdma_reqs = am33xx_mcspi1_edma_reqs,
1563 .main_clk = "dpll_per_m2_div4_ck",
1564 .prcm = {
1565 .omap4 = {
1566 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1567 .modulemode = MODULEMODE_SWCTRL,
1568 },
1569 },
1570 .dev_attr = &mcspi_attrib,
1571};
1572
1573/*
1574 * 'spinlock' class
1575 * spinlock provides hardware assistance for synchronizing the
1576 * processes running on multiple processors
1577 */
1578static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1579 .name = "spinlock",
1580};
1581
1582static struct omap_hwmod am33xx_spinlock_hwmod = {
1583 .name = "spinlock",
1584 .class = &am33xx_spinlock_hwmod_class,
1585 .clkdm_name = "l4ls_clkdm",
1586 .main_clk = "l4ls_gclk",
1587 .prcm = {
1588 .omap4 = {
1589 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1590 .modulemode = MODULEMODE_SWCTRL,
1591 },
1592 },
1593};
1594
1595/* 'timer 2-7' class */
1596static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1597 .rev_offs = 0x0000,
1598 .sysc_offs = 0x0010,
1599 .syss_offs = 0x0014,
1600 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1601 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1602 SIDLE_SMART_WKUP),
1603 .sysc_fields = &omap_hwmod_sysc_type2,
1604};
1605
1606static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1607 .name = "timer",
1608 .sysc = &am33xx_timer_sysc,
1609};
1610
1611/* timer1 1ms */
1612static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1613 .rev_offs = 0x0000,
1614 .sysc_offs = 0x0010,
1615 .syss_offs = 0x0014,
1616 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1617 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1618 SYSS_HAS_RESET_STATUS),
1619 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1620 .sysc_fields = &omap_hwmod_sysc_type1,
1621};
1622
1623static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1624 .name = "timer",
1625 .sysc = &am33xx_timer1ms_sysc,
1626};
1627
1628static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
1629 { .irq = 67 + OMAP_INTC_START, },
1630 { .irq = -1 },
1631};
1632
1633static struct omap_hwmod am33xx_timer1_hwmod = {
1634 .name = "timer1",
1635 .class = &am33xx_timer1ms_hwmod_class,
1636 .clkdm_name = "l4_wkup_clkdm",
1637 .mpu_irqs = am33xx_timer1_irqs,
1638 .main_clk = "timer1_fck",
1639 .prcm = {
1640 .omap4 = {
1641 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1642 .modulemode = MODULEMODE_SWCTRL,
1643 },
1644 },
1645};
1646
1647static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
1648 { .irq = 68 + OMAP_INTC_START, },
1649 { .irq = -1 },
1650};
1651
1652static struct omap_hwmod am33xx_timer2_hwmod = {
1653 .name = "timer2",
1654 .class = &am33xx_timer_hwmod_class,
1655 .clkdm_name = "l4ls_clkdm",
1656 .mpu_irqs = am33xx_timer2_irqs,
1657 .main_clk = "timer2_fck",
1658 .prcm = {
1659 .omap4 = {
1660 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1661 .modulemode = MODULEMODE_SWCTRL,
1662 },
1663 },
1664};
1665
1666static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
1667 { .irq = 69 + OMAP_INTC_START, },
1668 { .irq = -1 },
1669};
1670
1671static struct omap_hwmod am33xx_timer3_hwmod = {
1672 .name = "timer3",
1673 .class = &am33xx_timer_hwmod_class,
1674 .clkdm_name = "l4ls_clkdm",
1675 .mpu_irqs = am33xx_timer3_irqs,
1676 .main_clk = "timer3_fck",
1677 .prcm = {
1678 .omap4 = {
1679 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1680 .modulemode = MODULEMODE_SWCTRL,
1681 },
1682 },
1683};
1684
1685static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
1686 { .irq = 92 + OMAP_INTC_START, },
1687 { .irq = -1 },
1688};
1689
1690static struct omap_hwmod am33xx_timer4_hwmod = {
1691 .name = "timer4",
1692 .class = &am33xx_timer_hwmod_class,
1693 .clkdm_name = "l4ls_clkdm",
1694 .mpu_irqs = am33xx_timer4_irqs,
1695 .main_clk = "timer4_fck",
1696 .prcm = {
1697 .omap4 = {
1698 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1699 .modulemode = MODULEMODE_SWCTRL,
1700 },
1701 },
1702};
1703
1704static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
1705 { .irq = 93 + OMAP_INTC_START, },
1706 { .irq = -1 },
1707};
1708
1709static struct omap_hwmod am33xx_timer5_hwmod = {
1710 .name = "timer5",
1711 .class = &am33xx_timer_hwmod_class,
1712 .clkdm_name = "l4ls_clkdm",
1713 .mpu_irqs = am33xx_timer5_irqs,
1714 .main_clk = "timer5_fck",
1715 .prcm = {
1716 .omap4 = {
1717 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1718 .modulemode = MODULEMODE_SWCTRL,
1719 },
1720 },
1721};
1722
1723static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
1724 { .irq = 94 + OMAP_INTC_START, },
1725 { .irq = -1 },
1726};
1727
1728static struct omap_hwmod am33xx_timer6_hwmod = {
1729 .name = "timer6",
1730 .class = &am33xx_timer_hwmod_class,
1731 .clkdm_name = "l4ls_clkdm",
1732 .mpu_irqs = am33xx_timer6_irqs,
1733 .main_clk = "timer6_fck",
1734 .prcm = {
1735 .omap4 = {
1736 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
1737 .modulemode = MODULEMODE_SWCTRL,
1738 },
1739 },
1740};
1741
1742static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
1743 { .irq = 95 + OMAP_INTC_START, },
1744 { .irq = -1 },
1745};
1746
1747static struct omap_hwmod am33xx_timer7_hwmod = {
1748 .name = "timer7",
1749 .class = &am33xx_timer_hwmod_class,
1750 .clkdm_name = "l4ls_clkdm",
1751 .mpu_irqs = am33xx_timer7_irqs,
1752 .main_clk = "timer7_fck",
1753 .prcm = {
1754 .omap4 = {
1755 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
1756 .modulemode = MODULEMODE_SWCTRL,
1757 },
1758 },
1759};
1760
1761/* tpcc */
1762static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1763 .name = "tpcc",
1764};
1765
1766static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
1767 { .name = "edma0", .irq = 12 + OMAP_INTC_START, },
1768 { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
1769 { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, },
1770 { .irq = -1 },
1771};
1772
1773static struct omap_hwmod am33xx_tpcc_hwmod = {
1774 .name = "tpcc",
1775 .class = &am33xx_tpcc_hwmod_class,
1776 .clkdm_name = "l3_clkdm",
1777 .mpu_irqs = am33xx_tpcc_irqs,
1778 .main_clk = "l3_gclk",
1779 .prcm = {
1780 .omap4 = {
1781 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
1782 .modulemode = MODULEMODE_SWCTRL,
1783 },
1784 },
1785};
1786
1787static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1788 .rev_offs = 0x0,
1789 .sysc_offs = 0x10,
1790 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1791 SYSC_HAS_MIDLEMODE),
1792 .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1793 .sysc_fields = &omap_hwmod_sysc_type2,
1794};
1795
1796/* 'tptc' class */
1797static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1798 .name = "tptc",
1799 .sysc = &am33xx_tptc_sysc,
1800};
1801
1802/* tptc0 */
1803static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
1804 { .irq = 112 + OMAP_INTC_START, },
1805 { .irq = -1 },
1806};
1807
1808static struct omap_hwmod am33xx_tptc0_hwmod = {
1809 .name = "tptc0",
1810 .class = &am33xx_tptc_hwmod_class,
1811 .clkdm_name = "l3_clkdm",
1812 .mpu_irqs = am33xx_tptc0_irqs,
1813 .main_clk = "l3_gclk",
1814 .prcm = {
1815 .omap4 = {
1816 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
1817 .modulemode = MODULEMODE_SWCTRL,
1818 },
1819 },
1820};
1821
1822/* tptc1 */
1823static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
1824 { .irq = 113 + OMAP_INTC_START, },
1825 { .irq = -1 },
1826};
1827
1828static struct omap_hwmod am33xx_tptc1_hwmod = {
1829 .name = "tptc1",
1830 .class = &am33xx_tptc_hwmod_class,
1831 .clkdm_name = "l3_clkdm",
1832 .mpu_irqs = am33xx_tptc1_irqs,
1833 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1834 .main_clk = "l3_gclk",
1835 .prcm = {
1836 .omap4 = {
1837 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
1838 .modulemode = MODULEMODE_SWCTRL,
1839 },
1840 },
1841};
1842
1843/* tptc2 */
1844static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
1845 { .irq = 114 + OMAP_INTC_START, },
1846 { .irq = -1 },
1847};
1848
1849static struct omap_hwmod am33xx_tptc2_hwmod = {
1850 .name = "tptc2",
1851 .class = &am33xx_tptc_hwmod_class,
1852 .clkdm_name = "l3_clkdm",
1853 .mpu_irqs = am33xx_tptc2_irqs,
1854 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1855 .main_clk = "l3_gclk",
1856 .prcm = {
1857 .omap4 = {
1858 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
1859 .modulemode = MODULEMODE_SWCTRL,
1860 },
1861 },
1862};
1863
1864/* 'uart' class */
1865static struct omap_hwmod_class_sysconfig uart_sysc = {
1866 .rev_offs = 0x50,
1867 .sysc_offs = 0x54,
1868 .syss_offs = 0x58,
1869 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1870 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1871 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1872 SIDLE_SMART_WKUP),
1873 .sysc_fields = &omap_hwmod_sysc_type1,
1874};
1875
1876static struct omap_hwmod_class uart_class = {
1877 .name = "uart",
1878 .sysc = &uart_sysc,
1879};
1880
1881/* uart1 */
1882static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
1883 { .name = "tx", .dma_req = 26, },
1884 { .name = "rx", .dma_req = 27, },
1885 { .dma_req = -1 }
1886};
1887
1888static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
1889 { .irq = 72 + OMAP_INTC_START, },
1890 { .irq = -1 },
1891};
1892
1893static struct omap_hwmod am33xx_uart1_hwmod = {
1894 .name = "uart1",
1895 .class = &uart_class,
1896 .clkdm_name = "l4_wkup_clkdm",
1897 .mpu_irqs = am33xx_uart1_irqs,
1898 .sdma_reqs = uart1_edma_reqs,
1899 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1900 .prcm = {
1901 .omap4 = {
1902 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
1903 .modulemode = MODULEMODE_SWCTRL,
1904 },
1905 },
1906};
1907
1908static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
1909 { .irq = 73 + OMAP_INTC_START, },
1910 { .irq = -1 },
1911};
1912
1913static struct omap_hwmod am33xx_uart2_hwmod = {
1914 .name = "uart2",
1915 .class = &uart_class,
1916 .clkdm_name = "l4ls_clkdm",
1917 .mpu_irqs = am33xx_uart2_irqs,
1918 .sdma_reqs = uart1_edma_reqs,
1919 .main_clk = "dpll_per_m2_div4_ck",
1920 .prcm = {
1921 .omap4 = {
1922 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
1923 .modulemode = MODULEMODE_SWCTRL,
1924 },
1925 },
1926};
1927
1928/* uart3 */
1929static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
1930 { .name = "tx", .dma_req = 30, },
1931 { .name = "rx", .dma_req = 31, },
1932 { .dma_req = -1 }
1933};
1934
1935static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
1936 { .irq = 74 + OMAP_INTC_START, },
1937 { .irq = -1 },
1938};
1939
1940static struct omap_hwmod am33xx_uart3_hwmod = {
1941 .name = "uart3",
1942 .class = &uart_class,
1943 .clkdm_name = "l4ls_clkdm",
1944 .mpu_irqs = am33xx_uart3_irqs,
1945 .sdma_reqs = uart3_edma_reqs,
1946 .main_clk = "dpll_per_m2_div4_ck",
1947 .prcm = {
1948 .omap4 = {
1949 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
1950 .modulemode = MODULEMODE_SWCTRL,
1951 },
1952 },
1953};
1954
1955static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
1956 { .irq = 44 + OMAP_INTC_START, },
1957 { .irq = -1 },
1958};
1959
1960static struct omap_hwmod am33xx_uart4_hwmod = {
1961 .name = "uart4",
1962 .class = &uart_class,
1963 .clkdm_name = "l4ls_clkdm",
1964 .mpu_irqs = am33xx_uart4_irqs,
1965 .sdma_reqs = uart1_edma_reqs,
1966 .main_clk = "dpll_per_m2_div4_ck",
1967 .prcm = {
1968 .omap4 = {
1969 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
1970 .modulemode = MODULEMODE_SWCTRL,
1971 },
1972 },
1973};
1974
1975static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
1976 { .irq = 45 + OMAP_INTC_START, },
1977 { .irq = -1 },
1978};
1979
1980static struct omap_hwmod am33xx_uart5_hwmod = {
1981 .name = "uart5",
1982 .class = &uart_class,
1983 .clkdm_name = "l4ls_clkdm",
1984 .mpu_irqs = am33xx_uart5_irqs,
1985 .sdma_reqs = uart1_edma_reqs,
1986 .main_clk = "dpll_per_m2_div4_ck",
1987 .prcm = {
1988 .omap4 = {
1989 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
1990 .modulemode = MODULEMODE_SWCTRL,
1991 },
1992 },
1993};
1994
1995static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
1996 { .irq = 46 + OMAP_INTC_START, },
1997 { .irq = -1 },
1998};
1999
2000static struct omap_hwmod am33xx_uart6_hwmod = {
2001 .name = "uart6",
2002 .class = &uart_class,
2003 .clkdm_name = "l4ls_clkdm",
2004 .mpu_irqs = am33xx_uart6_irqs,
2005 .sdma_reqs = uart1_edma_reqs,
2006 .main_clk = "dpll_per_m2_div4_ck",
2007 .prcm = {
2008 .omap4 = {
2009 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2010 .modulemode = MODULEMODE_SWCTRL,
2011 },
2012 },
2013};
2014
2015/* 'wd_timer' class */
2016static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2017 .name = "wd_timer",
2018};
2019
2020/*
2021 * XXX: device.c file uses hardcoded name for watchdog timer
2022 * driver "wd_timer2, so we are also using same name as of now...
2023 */
2024static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2025 .name = "wd_timer2",
2026 .class = &am33xx_wd_timer_hwmod_class,
2027 .clkdm_name = "l4_wkup_clkdm",
2028 .main_clk = "wdt1_fck",
2029 .prcm = {
2030 .omap4 = {
2031 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2032 .modulemode = MODULEMODE_SWCTRL,
2033 },
2034 },
2035};
2036
2037/*
2038 * 'usb_otg' class
2039 * high-speed on-the-go universal serial bus (usb_otg) controller
2040 */
2041static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2042 .rev_offs = 0x0,
2043 .sysc_offs = 0x10,
2044 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
2045 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2046 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2047 .sysc_fields = &omap_hwmod_sysc_type2,
2048};
2049
2050static struct omap_hwmod_class am33xx_usbotg_class = {
2051 .name = "usbotg",
2052 .sysc = &am33xx_usbhsotg_sysc,
2053};
2054
2055static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2056 { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
2057 { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
2058 { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
2059 { .irq = -1 + OMAP_INTC_START, },
2060};
2061
2062static struct omap_hwmod am33xx_usbss_hwmod = {
2063 .name = "usb_otg_hs",
2064 .class = &am33xx_usbotg_class,
2065 .clkdm_name = "l3s_clkdm",
2066 .mpu_irqs = am33xx_usbss_mpu_irqs,
2067 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2068 .main_clk = "usbotg_fck",
2069 .prcm = {
2070 .omap4 = {
2071 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2072 .modulemode = MODULEMODE_SWCTRL,
2073 },
2074 },
2075};
2076
2077
2078/*
2079 * Interfaces
2080 */
2081
2082/* l4 fw -> emif fw */
2083static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
2084 .master = &am33xx_l4_fw_hwmod,
2085 .slave = &am33xx_emif_fw_hwmod,
2086 .clk = "l4fw_gclk",
2087 .user = OCP_USER_MPU,
2088};
2089
2090static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
2091 {
2092 .pa_start = 0x4c000000,
2093 .pa_end = 0x4c000fff,
2094 .flags = ADDR_TYPE_RT
2095 },
2096 { }
2097};
2098/* l3 main -> emif */
2099static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
2100 .master = &am33xx_l3_main_hwmod,
2101 .slave = &am33xx_emif_hwmod,
2102 .clk = "dpll_core_m4_ck",
2103 .addr = am33xx_emif_addrs,
2104 .user = OCP_USER_MPU | OCP_USER_SDMA,
2105};
2106
2107/* mpu -> l3 main */
2108static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
2109 .master = &am33xx_mpu_hwmod,
2110 .slave = &am33xx_l3_main_hwmod,
2111 .clk = "dpll_mpu_m2_ck",
2112 .user = OCP_USER_MPU,
2113};
2114
2115/* l3 main -> l4 hs */
2116static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
2117 .master = &am33xx_l3_main_hwmod,
2118 .slave = &am33xx_l4_hs_hwmod,
2119 .clk = "l3s_gclk",
2120 .user = OCP_USER_MPU | OCP_USER_SDMA,
2121};
2122
2123/* l3 main -> l3 s */
2124static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
2125 .master = &am33xx_l3_main_hwmod,
2126 .slave = &am33xx_l3_s_hwmod,
2127 .clk = "l3s_gclk",
2128 .user = OCP_USER_MPU | OCP_USER_SDMA,
2129};
2130
2131/* l3 s -> l4 per/ls */
2132static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
2133 .master = &am33xx_l3_s_hwmod,
2134 .slave = &am33xx_l4_ls_hwmod,
2135 .clk = "l3s_gclk",
2136 .user = OCP_USER_MPU | OCP_USER_SDMA,
2137};
2138
2139/* l3 s -> l4 wkup */
2140static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
2141 .master = &am33xx_l3_s_hwmod,
2142 .slave = &am33xx_l4_wkup_hwmod,
2143 .clk = "l3s_gclk",
2144 .user = OCP_USER_MPU | OCP_USER_SDMA,
2145};
2146
2147/* l3 s -> l4 fw */
2148static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
2149 .master = &am33xx_l3_s_hwmod,
2150 .slave = &am33xx_l4_fw_hwmod,
2151 .clk = "l3s_gclk",
2152 .user = OCP_USER_MPU | OCP_USER_SDMA,
2153};
2154
2155/* l3 main -> l3 instr */
2156static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
2157 .master = &am33xx_l3_main_hwmod,
2158 .slave = &am33xx_l3_instr_hwmod,
2159 .clk = "l3s_gclk",
2160 .user = OCP_USER_MPU | OCP_USER_SDMA,
2161};
2162
2163/* mpu -> prcm */
2164static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
2165 .master = &am33xx_mpu_hwmod,
2166 .slave = &am33xx_prcm_hwmod,
2167 .clk = "dpll_mpu_m2_ck",
2168 .user = OCP_USER_MPU | OCP_USER_SDMA,
2169};
2170
2171/* l3 s -> l3 main*/
2172static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
2173 .master = &am33xx_l3_s_hwmod,
2174 .slave = &am33xx_l3_main_hwmod,
2175 .clk = "l3s_gclk",
2176 .user = OCP_USER_MPU | OCP_USER_SDMA,
2177};
2178
2179/* pru-icss -> l3 main */
2180static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
2181 .master = &am33xx_pruss_hwmod,
2182 .slave = &am33xx_l3_main_hwmod,
2183 .clk = "l3_gclk",
2184 .user = OCP_USER_MPU | OCP_USER_SDMA,
2185};
2186
2187/* wkup m3 -> l4 wkup */
2188static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
2189 .master = &am33xx_wkup_m3_hwmod,
2190 .slave = &am33xx_l4_wkup_hwmod,
2191 .clk = "dpll_core_m4_div2_ck",
2192 .user = OCP_USER_MPU | OCP_USER_SDMA,
2193};
2194
2195/* gfx -> l3 main */
2196static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
2197 .master = &am33xx_gfx_hwmod,
2198 .slave = &am33xx_l3_main_hwmod,
2199 .clk = "dpll_core_m4_ck",
2200 .user = OCP_USER_MPU | OCP_USER_SDMA,
2201};
2202
2203/* l4 wkup -> wkup m3 */
2204static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
2205 {
2206 .name = "umem",
2207 .pa_start = 0x44d00000,
2208 .pa_end = 0x44d00000 + SZ_16K - 1,
2209 .flags = ADDR_TYPE_RT
2210 },
2211 {
2212 .name = "dmem",
2213 .pa_start = 0x44d80000,
2214 .pa_end = 0x44d80000 + SZ_8K - 1,
2215 .flags = ADDR_TYPE_RT
2216 },
2217 { }
2218};
2219
2220static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
2221 .master = &am33xx_l4_wkup_hwmod,
2222 .slave = &am33xx_wkup_m3_hwmod,
2223 .clk = "dpll_core_m4_div2_ck",
2224 .addr = am33xx_wkup_m3_addrs,
2225 .user = OCP_USER_MPU | OCP_USER_SDMA,
2226};
2227
2228/* l4 hs -> pru-icss */
2229static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
2230 {
2231 .pa_start = 0x4a300000,
2232 .pa_end = 0x4a300000 + SZ_512K - 1,
2233 .flags = ADDR_TYPE_RT
2234 },
2235 { }
2236};
2237
2238static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
2239 .master = &am33xx_l4_hs_hwmod,
2240 .slave = &am33xx_pruss_hwmod,
2241 .clk = "dpll_core_m4_ck",
2242 .addr = am33xx_pruss_addrs,
2243 .user = OCP_USER_MPU | OCP_USER_SDMA,
2244};
2245
2246/* l3 main -> gfx */
2247static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
2248 {
2249 .pa_start = 0x56000000,
2250 .pa_end = 0x56000000 + SZ_16M - 1,
2251 .flags = ADDR_TYPE_RT
2252 },
2253 { }
2254};
2255
2256static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
2257 .master = &am33xx_l3_main_hwmod,
2258 .slave = &am33xx_gfx_hwmod,
2259 .clk = "dpll_core_m4_ck",
2260 .addr = am33xx_gfx_addrs,
2261 .user = OCP_USER_MPU | OCP_USER_SDMA,
2262};
2263
2264/* l4 wkup -> smartreflex0 */
2265static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
2266 {
2267 .pa_start = 0x44e37000,
2268 .pa_end = 0x44e37000 + SZ_4K - 1,
2269 .flags = ADDR_TYPE_RT
2270 },
2271 { }
2272};
2273
2274static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
2275 .master = &am33xx_l4_wkup_hwmod,
2276 .slave = &am33xx_smartreflex0_hwmod,
2277 .clk = "dpll_core_m4_div2_ck",
2278 .addr = am33xx_smartreflex0_addrs,
2279 .user = OCP_USER_MPU,
2280};
2281
2282/* l4 wkup -> smartreflex1 */
2283static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
2284 {
2285 .pa_start = 0x44e39000,
2286 .pa_end = 0x44e39000 + SZ_4K - 1,
2287 .flags = ADDR_TYPE_RT
2288 },
2289 { }
2290};
2291
2292static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
2293 .master = &am33xx_l4_wkup_hwmod,
2294 .slave = &am33xx_smartreflex1_hwmod,
2295 .clk = "dpll_core_m4_div2_ck",
2296 .addr = am33xx_smartreflex1_addrs,
2297 .user = OCP_USER_MPU,
2298};
2299
2300/* l4 wkup -> control */
2301static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
2302 {
2303 .pa_start = 0x44e10000,
2304 .pa_end = 0x44e10000 + SZ_8K - 1,
2305 .flags = ADDR_TYPE_RT
2306 },
2307 { }
2308};
2309
2310static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
2311 .master = &am33xx_l4_wkup_hwmod,
2312 .slave = &am33xx_control_hwmod,
2313 .clk = "dpll_core_m4_div2_ck",
2314 .addr = am33xx_control_addrs,
2315 .user = OCP_USER_MPU,
2316};
2317
2318/* l4 wkup -> rtc */
2319static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
2320 {
2321 .pa_start = 0x44e3e000,
2322 .pa_end = 0x44e3e000 + SZ_4K - 1,
2323 .flags = ADDR_TYPE_RT
2324 },
2325 { }
2326};
2327
2328static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
2329 .master = &am33xx_l4_wkup_hwmod,
2330 .slave = &am33xx_rtc_hwmod,
2331 .clk = "clkdiv32k_ick",
2332 .addr = am33xx_rtc_addrs,
2333 .user = OCP_USER_MPU,
2334};
2335
2336/* l4 per/ls -> DCAN0 */
2337static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
2338 {
2339 .pa_start = 0x481CC000,
2340 .pa_end = 0x481CC000 + SZ_4K - 1,
2341 .flags = ADDR_TYPE_RT
2342 },
2343 { }
2344};
2345
2346static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
2347 .master = &am33xx_l4_ls_hwmod,
2348 .slave = &am33xx_dcan0_hwmod,
2349 .clk = "l4ls_gclk",
2350 .addr = am33xx_dcan0_addrs,
2351 .user = OCP_USER_MPU | OCP_USER_SDMA,
2352};
2353
2354/* l4 per/ls -> DCAN1 */
2355static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
2356 {
2357 .pa_start = 0x481D0000,
2358 .pa_end = 0x481D0000 + SZ_4K - 1,
2359 .flags = ADDR_TYPE_RT
2360 },
2361 { }
2362};
2363
2364static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
2365 .master = &am33xx_l4_ls_hwmod,
2366 .slave = &am33xx_dcan1_hwmod,
2367 .clk = "l4ls_gclk",
2368 .addr = am33xx_dcan1_addrs,
2369 .user = OCP_USER_MPU | OCP_USER_SDMA,
2370};
2371
2372/* l4 per/ls -> GPIO2 */
2373static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
2374 {
2375 .pa_start = 0x4804C000,
2376 .pa_end = 0x4804C000 + SZ_4K - 1,
2377 .flags = ADDR_TYPE_RT,
2378 },
2379 { }
2380};
2381
2382static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
2383 .master = &am33xx_l4_ls_hwmod,
2384 .slave = &am33xx_gpio1_hwmod,
2385 .clk = "l4ls_gclk",
2386 .addr = am33xx_gpio1_addrs,
2387 .user = OCP_USER_MPU | OCP_USER_SDMA,
2388};
2389
2390/* l4 per/ls -> gpio3 */
2391static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
2392 {
2393 .pa_start = 0x481AC000,
2394 .pa_end = 0x481AC000 + SZ_4K - 1,
2395 .flags = ADDR_TYPE_RT,
2396 },
2397 { }
2398};
2399
2400static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
2401 .master = &am33xx_l4_ls_hwmod,
2402 .slave = &am33xx_gpio2_hwmod,
2403 .clk = "l4ls_gclk",
2404 .addr = am33xx_gpio2_addrs,
2405 .user = OCP_USER_MPU | OCP_USER_SDMA,
2406};
2407
2408/* l4 per/ls -> gpio4 */
2409static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
2410 {
2411 .pa_start = 0x481AE000,
2412 .pa_end = 0x481AE000 + SZ_4K - 1,
2413 .flags = ADDR_TYPE_RT,
2414 },
2415 { }
2416};
2417
2418static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
2419 .master = &am33xx_l4_ls_hwmod,
2420 .slave = &am33xx_gpio3_hwmod,
2421 .clk = "l4ls_gclk",
2422 .addr = am33xx_gpio3_addrs,
2423 .user = OCP_USER_MPU | OCP_USER_SDMA,
2424};
2425
2426/* L4 WKUP -> I2C1 */
2427static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
2428 {
2429 .pa_start = 0x44E0B000,
2430 .pa_end = 0x44E0B000 + SZ_4K - 1,
2431 .flags = ADDR_TYPE_RT,
2432 },
2433 { }
2434};
2435
2436static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
2437 .master = &am33xx_l4_wkup_hwmod,
2438 .slave = &am33xx_i2c1_hwmod,
2439 .clk = "dpll_core_m4_div2_ck",
2440 .addr = am33xx_i2c1_addr_space,
2441 .user = OCP_USER_MPU,
2442};
2443
2444/* L4 WKUP -> GPIO1 */
2445static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
2446 {
2447 .pa_start = 0x44E07000,
2448 .pa_end = 0x44E07000 + SZ_4K - 1,
2449 .flags = ADDR_TYPE_RT,
2450 },
2451 { }
2452};
2453
2454static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
2455 .master = &am33xx_l4_wkup_hwmod,
2456 .slave = &am33xx_gpio0_hwmod,
2457 .clk = "dpll_core_m4_div2_ck",
2458 .addr = am33xx_gpio0_addrs,
2459 .user = OCP_USER_MPU | OCP_USER_SDMA,
2460};
2461
2462/* L4 WKUP -> ADC_TSC */
2463static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
2464 {
2465 .pa_start = 0x44E0D000,
2466 .pa_end = 0x44E0D000 + SZ_8K - 1,
2467 .flags = ADDR_TYPE_RT
2468 },
2469 { }
2470};
2471
2472static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
2473 .master = &am33xx_l4_wkup_hwmod,
2474 .slave = &am33xx_adc_tsc_hwmod,
2475 .clk = "dpll_core_m4_div2_ck",
2476 .addr = am33xx_adc_tsc_addrs,
2477 .user = OCP_USER_MPU,
2478};
2479
2480static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
2481 /* cpsw ss */
2482 {
2483 .pa_start = 0x4a100000,
2484 .pa_end = 0x4a100000 + SZ_2K - 1,
2485 .flags = ADDR_TYPE_RT,
2486 },
2487 /* cpsw wr */
2488 {
2489 .pa_start = 0x4a101200,
2490 .pa_end = 0x4a101200 + SZ_256 - 1,
2491 .flags = ADDR_TYPE_RT,
2492 },
2493 { }
2494};
2495
2496static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
2497 .master = &am33xx_l4_hs_hwmod,
2498 .slave = &am33xx_cpgmac0_hwmod,
2499 .clk = "cpsw_125mhz_gclk",
2500 .addr = am33xx_cpgmac0_addr_space,
2501 .user = OCP_USER_MPU,
2502};
2503
2504static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
2505 {
2506 .pa_start = 0x48080000,
2507 .pa_end = 0x48080000 + SZ_8K - 1,
2508 .flags = ADDR_TYPE_RT
2509 },
2510 { }
2511};
2512
2513static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
2514 .master = &am33xx_l4_ls_hwmod,
2515 .slave = &am33xx_elm_hwmod,
2516 .clk = "l4ls_gclk",
2517 .addr = am33xx_elm_addr_space,
2518 .user = OCP_USER_MPU,
2519};
2520
2521/*
2522 * Splitting the resources to handle access of PWMSS config space
2523 * and module specific part independently
2524 */
2525static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
2526 {
2527 .pa_start = 0x48300000,
2528 .pa_end = 0x48300000 + SZ_16 - 1,
2529 .flags = ADDR_TYPE_RT
2530 },
2531 {
2532 .pa_start = 0x48300200,
2533 .pa_end = 0x48300200 + SZ_256 - 1,
2534 .flags = ADDR_TYPE_RT
2535 },
2536 { }
2537};
2538
2539static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = {
2540 .master = &am33xx_l4_ls_hwmod,
2541 .slave = &am33xx_ehrpwm0_hwmod,
2542 .clk = "l4ls_gclk",
2543 .addr = am33xx_ehrpwm0_addr_space,
2544 .user = OCP_USER_MPU,
2545};
2546
2547/*
2548 * Splitting the resources to handle access of PWMSS config space
2549 * and module specific part independently
2550 */
2551static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
2552 {
2553 .pa_start = 0x48302000,
2554 .pa_end = 0x48302000 + SZ_16 - 1,
2555 .flags = ADDR_TYPE_RT
2556 },
2557 {
2558 .pa_start = 0x48302200,
2559 .pa_end = 0x48302200 + SZ_256 - 1,
2560 .flags = ADDR_TYPE_RT
2561 },
2562 { }
2563};
2564
2565static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = {
2566 .master = &am33xx_l4_ls_hwmod,
2567 .slave = &am33xx_ehrpwm1_hwmod,
2568 .clk = "l4ls_gclk",
2569 .addr = am33xx_ehrpwm1_addr_space,
2570 .user = OCP_USER_MPU,
2571};
2572
2573/*
2574 * Splitting the resources to handle access of PWMSS config space
2575 * and module specific part independently
2576 */
2577static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
2578 {
2579 .pa_start = 0x48304000,
2580 .pa_end = 0x48304000 + SZ_16 - 1,
2581 .flags = ADDR_TYPE_RT
2582 },
2583 {
2584 .pa_start = 0x48304200,
2585 .pa_end = 0x48304200 + SZ_256 - 1,
2586 .flags = ADDR_TYPE_RT
2587 },
2588 { }
2589};
2590
2591static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
2592 .master = &am33xx_l4_ls_hwmod,
2593 .slave = &am33xx_ehrpwm2_hwmod,
2594 .clk = "l4ls_gclk",
2595 .addr = am33xx_ehrpwm2_addr_space,
2596 .user = OCP_USER_MPU,
2597};
2598
2599/*
2600 * Splitting the resources to handle access of PWMSS config space
2601 * and module specific part independently
2602 */
2603static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
2604 {
2605 .pa_start = 0x48300000,
2606 .pa_end = 0x48300000 + SZ_16 - 1,
2607 .flags = ADDR_TYPE_RT
2608 },
2609 {
2610 .pa_start = 0x48300100,
2611 .pa_end = 0x48300100 + SZ_256 - 1,
2612 .flags = ADDR_TYPE_RT
2613 },
2614 { }
2615};
2616
2617static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = {
2618 .master = &am33xx_l4_ls_hwmod,
2619 .slave = &am33xx_ecap0_hwmod,
2620 .clk = "l4ls_gclk",
2621 .addr = am33xx_ecap0_addr_space,
2622 .user = OCP_USER_MPU,
2623};
2624
2625/*
2626 * Splitting the resources to handle access of PWMSS config space
2627 * and module specific part independently
2628 */
2629static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
2630 {
2631 .pa_start = 0x48302000,
2632 .pa_end = 0x48302000 + SZ_16 - 1,
2633 .flags = ADDR_TYPE_RT
2634 },
2635 {
2636 .pa_start = 0x48302100,
2637 .pa_end = 0x48302100 + SZ_256 - 1,
2638 .flags = ADDR_TYPE_RT
2639 },
2640 { }
2641};
2642
2643static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = {
2644 .master = &am33xx_l4_ls_hwmod,
2645 .slave = &am33xx_ecap1_hwmod,
2646 .clk = "l4ls_gclk",
2647 .addr = am33xx_ecap1_addr_space,
2648 .user = OCP_USER_MPU,
2649};
2650
2651/*
2652 * Splitting the resources to handle access of PWMSS config space
2653 * and module specific part independently
2654 */
2655static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
2656 {
2657 .pa_start = 0x48304000,
2658 .pa_end = 0x48304000 + SZ_16 - 1,
2659 .flags = ADDR_TYPE_RT
2660 },
2661 {
2662 .pa_start = 0x48304100,
2663 .pa_end = 0x48304100 + SZ_256 - 1,
2664 .flags = ADDR_TYPE_RT
2665 },
2666 { }
2667};
2668
2669static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = {
2670 .master = &am33xx_l4_ls_hwmod,
2671 .slave = &am33xx_ecap2_hwmod,
2672 .clk = "l4ls_gclk",
2673 .addr = am33xx_ecap2_addr_space,
2674 .user = OCP_USER_MPU,
2675};
2676
2677/* l3s cfg -> gpmc */
2678static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
2679 {
2680 .pa_start = 0x50000000,
2681 .pa_end = 0x50000000 + SZ_8K - 1,
2682 .flags = ADDR_TYPE_RT,
2683 },
2684 { }
2685};
2686
2687static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
2688 .master = &am33xx_l3_s_hwmod,
2689 .slave = &am33xx_gpmc_hwmod,
2690 .clk = "l3s_gclk",
2691 .addr = am33xx_gpmc_addr_space,
2692 .user = OCP_USER_MPU,
2693};
2694
2695/* i2c2 */
2696static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
2697 {
2698 .pa_start = 0x4802A000,
2699 .pa_end = 0x4802A000 + SZ_4K - 1,
2700 .flags = ADDR_TYPE_RT,
2701 },
2702 { }
2703};
2704
2705static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
2706 .master = &am33xx_l4_ls_hwmod,
2707 .slave = &am33xx_i2c2_hwmod,
2708 .clk = "l4ls_gclk",
2709 .addr = am33xx_i2c2_addr_space,
2710 .user = OCP_USER_MPU,
2711};
2712
2713static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
2714 {
2715 .pa_start = 0x4819C000,
2716 .pa_end = 0x4819C000 + SZ_4K - 1,
2717 .flags = ADDR_TYPE_RT
2718 },
2719 { }
2720};
2721
2722static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
2723 .master = &am33xx_l4_ls_hwmod,
2724 .slave = &am33xx_i2c3_hwmod,
2725 .clk = "l4ls_gclk",
2726 .addr = am33xx_i2c3_addr_space,
2727 .user = OCP_USER_MPU,
2728};
2729
2730static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
2731 {
2732 .pa_start = 0x4830E000,
2733 .pa_end = 0x4830E000 + SZ_8K - 1,
2734 .flags = ADDR_TYPE_RT,
2735 },
2736 { }
2737};
2738
2739static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
2740 .master = &am33xx_l3_main_hwmod,
2741 .slave = &am33xx_lcdc_hwmod,
2742 .clk = "dpll_core_m4_ck",
2743 .addr = am33xx_lcdc_addr_space,
2744 .user = OCP_USER_MPU,
2745};
2746
2747static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
2748 {
2749 .pa_start = 0x480C8000,
2750 .pa_end = 0x480C8000 + (SZ_4K - 1),
2751 .flags = ADDR_TYPE_RT
2752 },
2753 { }
2754};
2755
2756/* l4 ls -> mailbox */
2757static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
2758 .master = &am33xx_l4_ls_hwmod,
2759 .slave = &am33xx_mailbox_hwmod,
2760 .clk = "l4ls_gclk",
2761 .addr = am33xx_mailbox_addrs,
2762 .user = OCP_USER_MPU,
2763};
2764
2765/* l4 ls -> spinlock */
2766static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
2767 {
2768 .pa_start = 0x480Ca000,
2769 .pa_end = 0x480Ca000 + SZ_4K - 1,
2770 .flags = ADDR_TYPE_RT
2771 },
2772 { }
2773};
2774
2775static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
2776 .master = &am33xx_l4_ls_hwmod,
2777 .slave = &am33xx_spinlock_hwmod,
2778 .clk = "l4ls_gclk",
2779 .addr = am33xx_spinlock_addrs,
2780 .user = OCP_USER_MPU,
2781};
2782
2783/* l4 ls -> mcasp0 */
2784static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
2785 {
2786 .pa_start = 0x48038000,
2787 .pa_end = 0x48038000 + SZ_8K - 1,
2788 .flags = ADDR_TYPE_RT
2789 },
2790 { }
2791};
2792
2793static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
2794 .master = &am33xx_l4_ls_hwmod,
2795 .slave = &am33xx_mcasp0_hwmod,
2796 .clk = "l4ls_gclk",
2797 .addr = am33xx_mcasp0_addr_space,
2798 .user = OCP_USER_MPU,
2799};
2800
2801/* l3 s -> mcasp0 data */
2802static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
2803 {
2804 .pa_start = 0x46000000,
2805 .pa_end = 0x46000000 + SZ_4M - 1,
2806 .flags = ADDR_TYPE_RT
2807 },
2808 { }
2809};
2810
2811static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
2812 .master = &am33xx_l3_s_hwmod,
2813 .slave = &am33xx_mcasp0_hwmod,
2814 .clk = "l3s_gclk",
2815 .addr = am33xx_mcasp0_data_addr_space,
2816 .user = OCP_USER_SDMA,
2817};
2818
2819/* l4 ls -> mcasp1 */
2820static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
2821 {
2822 .pa_start = 0x4803C000,
2823 .pa_end = 0x4803C000 + SZ_8K - 1,
2824 .flags = ADDR_TYPE_RT
2825 },
2826 { }
2827};
2828
2829static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
2830 .master = &am33xx_l4_ls_hwmod,
2831 .slave = &am33xx_mcasp1_hwmod,
2832 .clk = "l4ls_gclk",
2833 .addr = am33xx_mcasp1_addr_space,
2834 .user = OCP_USER_MPU,
2835};
2836
2837/* l3 s -> mcasp1 data */
2838static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
2839 {
2840 .pa_start = 0x46400000,
2841 .pa_end = 0x46400000 + SZ_4M - 1,
2842 .flags = ADDR_TYPE_RT
2843 },
2844 { }
2845};
2846
2847static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
2848 .master = &am33xx_l3_s_hwmod,
2849 .slave = &am33xx_mcasp1_hwmod,
2850 .clk = "l3s_gclk",
2851 .addr = am33xx_mcasp1_data_addr_space,
2852 .user = OCP_USER_SDMA,
2853};
2854
2855/* l4 ls -> mmc0 */
2856static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
2857 {
2858 .pa_start = 0x48060100,
2859 .pa_end = 0x48060100 + SZ_4K - 1,
2860 .flags = ADDR_TYPE_RT,
2861 },
2862 { }
2863};
2864
2865static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
2866 .master = &am33xx_l4_ls_hwmod,
2867 .slave = &am33xx_mmc0_hwmod,
2868 .clk = "l4ls_gclk",
2869 .addr = am33xx_mmc0_addr_space,
2870 .user = OCP_USER_MPU,
2871};
2872
2873/* l4 ls -> mmc1 */
2874static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
2875 {
2876 .pa_start = 0x481d8100,
2877 .pa_end = 0x481d8100 + SZ_4K - 1,
2878 .flags = ADDR_TYPE_RT,
2879 },
2880 { }
2881};
2882
2883static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
2884 .master = &am33xx_l4_ls_hwmod,
2885 .slave = &am33xx_mmc1_hwmod,
2886 .clk = "l4ls_gclk",
2887 .addr = am33xx_mmc1_addr_space,
2888 .user = OCP_USER_MPU,
2889};
2890
2891/* l3 s -> mmc2 */
2892static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
2893 {
2894 .pa_start = 0x47810100,
2895 .pa_end = 0x47810100 + SZ_64K - 1,
2896 .flags = ADDR_TYPE_RT,
2897 },
2898 { }
2899};
2900
2901static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
2902 .master = &am33xx_l3_s_hwmod,
2903 .slave = &am33xx_mmc2_hwmod,
2904 .clk = "l3s_gclk",
2905 .addr = am33xx_mmc2_addr_space,
2906 .user = OCP_USER_MPU,
2907};
2908
2909/* l4 ls -> mcspi0 */
2910static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
2911 {
2912 .pa_start = 0x48030000,
2913 .pa_end = 0x48030000 + SZ_1K - 1,
2914 .flags = ADDR_TYPE_RT,
2915 },
2916 { }
2917};
2918
2919static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
2920 .master = &am33xx_l4_ls_hwmod,
2921 .slave = &am33xx_spi0_hwmod,
2922 .clk = "l4ls_gclk",
2923 .addr = am33xx_mcspi0_addr_space,
2924 .user = OCP_USER_MPU,
2925};
2926
2927/* l4 ls -> mcspi1 */
2928static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
2929 {
2930 .pa_start = 0x481A0000,
2931 .pa_end = 0x481A0000 + SZ_1K - 1,
2932 .flags = ADDR_TYPE_RT,
2933 },
2934 { }
2935};
2936
2937static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
2938 .master = &am33xx_l4_ls_hwmod,
2939 .slave = &am33xx_spi1_hwmod,
2940 .clk = "l4ls_gclk",
2941 .addr = am33xx_mcspi1_addr_space,
2942 .user = OCP_USER_MPU,
2943};
2944
2945/* l4 wkup -> timer1 */
2946static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
2947 {
2948 .pa_start = 0x44E31000,
2949 .pa_end = 0x44E31000 + SZ_1K - 1,
2950 .flags = ADDR_TYPE_RT
2951 },
2952 { }
2953};
2954
2955static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
2956 .master = &am33xx_l4_wkup_hwmod,
2957 .slave = &am33xx_timer1_hwmod,
2958 .clk = "dpll_core_m4_div2_ck",
2959 .addr = am33xx_timer1_addr_space,
2960 .user = OCP_USER_MPU,
2961};
2962
2963/* l4 per -> timer2 */
2964static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
2965 {
2966 .pa_start = 0x48040000,
2967 .pa_end = 0x48040000 + SZ_1K - 1,
2968 .flags = ADDR_TYPE_RT
2969 },
2970 { }
2971};
2972
2973static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
2974 .master = &am33xx_l4_ls_hwmod,
2975 .slave = &am33xx_timer2_hwmod,
2976 .clk = "l4ls_gclk",
2977 .addr = am33xx_timer2_addr_space,
2978 .user = OCP_USER_MPU,
2979};
2980
2981/* l4 per -> timer3 */
2982static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
2983 {
2984 .pa_start = 0x48042000,
2985 .pa_end = 0x48042000 + SZ_1K - 1,
2986 .flags = ADDR_TYPE_RT
2987 },
2988 { }
2989};
2990
2991static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
2992 .master = &am33xx_l4_ls_hwmod,
2993 .slave = &am33xx_timer3_hwmod,
2994 .clk = "l4ls_gclk",
2995 .addr = am33xx_timer3_addr_space,
2996 .user = OCP_USER_MPU,
2997};
2998
2999/* l4 per -> timer4 */
3000static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
3001 {
3002 .pa_start = 0x48044000,
3003 .pa_end = 0x48044000 + SZ_1K - 1,
3004 .flags = ADDR_TYPE_RT
3005 },
3006 { }
3007};
3008
3009static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
3010 .master = &am33xx_l4_ls_hwmod,
3011 .slave = &am33xx_timer4_hwmod,
3012 .clk = "l4ls_gclk",
3013 .addr = am33xx_timer4_addr_space,
3014 .user = OCP_USER_MPU,
3015};
3016
3017/* l4 per -> timer5 */
3018static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
3019 {
3020 .pa_start = 0x48046000,
3021 .pa_end = 0x48046000 + SZ_1K - 1,
3022 .flags = ADDR_TYPE_RT
3023 },
3024 { }
3025};
3026
3027static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
3028 .master = &am33xx_l4_ls_hwmod,
3029 .slave = &am33xx_timer5_hwmod,
3030 .clk = "l4ls_gclk",
3031 .addr = am33xx_timer5_addr_space,
3032 .user = OCP_USER_MPU,
3033};
3034
3035/* l4 per -> timer6 */
3036static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
3037 {
3038 .pa_start = 0x48048000,
3039 .pa_end = 0x48048000 + SZ_1K - 1,
3040 .flags = ADDR_TYPE_RT
3041 },
3042 { }
3043};
3044
3045static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
3046 .master = &am33xx_l4_ls_hwmod,
3047 .slave = &am33xx_timer6_hwmod,
3048 .clk = "l4ls_gclk",
3049 .addr = am33xx_timer6_addr_space,
3050 .user = OCP_USER_MPU,
3051};
3052
3053/* l4 per -> timer7 */
3054static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
3055 {
3056 .pa_start = 0x4804A000,
3057 .pa_end = 0x4804A000 + SZ_1K - 1,
3058 .flags = ADDR_TYPE_RT
3059 },
3060 { }
3061};
3062
3063static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
3064 .master = &am33xx_l4_ls_hwmod,
3065 .slave = &am33xx_timer7_hwmod,
3066 .clk = "l4ls_gclk",
3067 .addr = am33xx_timer7_addr_space,
3068 .user = OCP_USER_MPU,
3069};
3070
3071/* l3 main -> tpcc */
3072static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
3073 {
3074 .pa_start = 0x49000000,
3075 .pa_end = 0x49000000 + SZ_32K - 1,
3076 .flags = ADDR_TYPE_RT
3077 },
3078 { }
3079};
3080
3081static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
3082 .master = &am33xx_l3_main_hwmod,
3083 .slave = &am33xx_tpcc_hwmod,
3084 .clk = "l3_gclk",
3085 .addr = am33xx_tpcc_addr_space,
3086 .user = OCP_USER_MPU,
3087};
3088
3089/* l3 main -> tpcc0 */
3090static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
3091 {
3092 .pa_start = 0x49800000,
3093 .pa_end = 0x49800000 + SZ_8K - 1,
3094 .flags = ADDR_TYPE_RT,
3095 },
3096 { }
3097};
3098
3099static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
3100 .master = &am33xx_l3_main_hwmod,
3101 .slave = &am33xx_tptc0_hwmod,
3102 .clk = "l3_gclk",
3103 .addr = am33xx_tptc0_addr_space,
3104 .user = OCP_USER_MPU,
3105};
3106
3107/* l3 main -> tpcc1 */
3108static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
3109 {
3110 .pa_start = 0x49900000,
3111 .pa_end = 0x49900000 + SZ_8K - 1,
3112 .flags = ADDR_TYPE_RT,
3113 },
3114 { }
3115};
3116
3117static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
3118 .master = &am33xx_l3_main_hwmod,
3119 .slave = &am33xx_tptc1_hwmod,
3120 .clk = "l3_gclk",
3121 .addr = am33xx_tptc1_addr_space,
3122 .user = OCP_USER_MPU,
3123};
3124
3125/* l3 main -> tpcc2 */
3126static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
3127 {
3128 .pa_start = 0x49a00000,
3129 .pa_end = 0x49a00000 + SZ_8K - 1,
3130 .flags = ADDR_TYPE_RT,
3131 },
3132 { }
3133};
3134
3135static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
3136 .master = &am33xx_l3_main_hwmod,
3137 .slave = &am33xx_tptc2_hwmod,
3138 .clk = "l3_gclk",
3139 .addr = am33xx_tptc2_addr_space,
3140 .user = OCP_USER_MPU,
3141};
3142
3143/* l4 wkup -> uart1 */
3144static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
3145 {
3146 .pa_start = 0x44E09000,
3147 .pa_end = 0x44E09000 + SZ_8K - 1,
3148 .flags = ADDR_TYPE_RT,
3149 },
3150 { }
3151};
3152
3153static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
3154 .master = &am33xx_l4_wkup_hwmod,
3155 .slave = &am33xx_uart1_hwmod,
3156 .clk = "dpll_core_m4_div2_ck",
3157 .addr = am33xx_uart1_addr_space,
3158 .user = OCP_USER_MPU,
3159};
3160
3161/* l4 ls -> uart2 */
3162static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
3163 {
3164 .pa_start = 0x48022000,
3165 .pa_end = 0x48022000 + SZ_8K - 1,
3166 .flags = ADDR_TYPE_RT,
3167 },
3168 { }
3169};
3170
3171static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
3172 .master = &am33xx_l4_ls_hwmod,
3173 .slave = &am33xx_uart2_hwmod,
3174 .clk = "l4ls_gclk",
3175 .addr = am33xx_uart2_addr_space,
3176 .user = OCP_USER_MPU,
3177};
3178
3179/* l4 ls -> uart3 */
3180static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
3181 {
3182 .pa_start = 0x48024000,
3183 .pa_end = 0x48024000 + SZ_8K - 1,
3184 .flags = ADDR_TYPE_RT,
3185 },
3186 { }
3187};
3188
3189static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
3190 .master = &am33xx_l4_ls_hwmod,
3191 .slave = &am33xx_uart3_hwmod,
3192 .clk = "l4ls_gclk",
3193 .addr = am33xx_uart3_addr_space,
3194 .user = OCP_USER_MPU,
3195};
3196
3197/* l4 ls -> uart4 */
3198static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
3199 {
3200 .pa_start = 0x481A6000,
3201 .pa_end = 0x481A6000 + SZ_8K - 1,
3202 .flags = ADDR_TYPE_RT,
3203 },
3204 { }
3205};
3206
3207static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
3208 .master = &am33xx_l4_ls_hwmod,
3209 .slave = &am33xx_uart4_hwmod,
3210 .clk = "l4ls_gclk",
3211 .addr = am33xx_uart4_addr_space,
3212 .user = OCP_USER_MPU,
3213};
3214
3215/* l4 ls -> uart5 */
3216static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
3217 {
3218 .pa_start = 0x481A8000,
3219 .pa_end = 0x481A8000 + SZ_8K - 1,
3220 .flags = ADDR_TYPE_RT,
3221 },
3222 { }
3223};
3224
3225static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
3226 .master = &am33xx_l4_ls_hwmod,
3227 .slave = &am33xx_uart5_hwmod,
3228 .clk = "l4ls_gclk",
3229 .addr = am33xx_uart5_addr_space,
3230 .user = OCP_USER_MPU,
3231};
3232
3233/* l4 ls -> uart6 */
3234static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
3235 {
3236 .pa_start = 0x481aa000,
3237 .pa_end = 0x481aa000 + SZ_8K - 1,
3238 .flags = ADDR_TYPE_RT,
3239 },
3240 { }
3241};
3242
3243static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
3244 .master = &am33xx_l4_ls_hwmod,
3245 .slave = &am33xx_uart6_hwmod,
3246 .clk = "l4ls_gclk",
3247 .addr = am33xx_uart6_addr_space,
3248 .user = OCP_USER_MPU,
3249};
3250
3251/* l4 wkup -> wd_timer1 */
3252static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
3253 {
3254 .pa_start = 0x44e35000,
3255 .pa_end = 0x44e35000 + SZ_4K - 1,
3256 .flags = ADDR_TYPE_RT
3257 },
3258 { }
3259};
3260
3261static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
3262 .master = &am33xx_l4_wkup_hwmod,
3263 .slave = &am33xx_wd_timer1_hwmod,
3264 .clk = "dpll_core_m4_div2_ck",
3265 .addr = am33xx_wd_timer1_addrs,
3266 .user = OCP_USER_MPU,
3267};
3268
3269/* usbss */
3270/* l3 s -> USBSS interface */
3271static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
3272 {
3273 .name = "usbss",
3274 .pa_start = 0x47400000,
3275 .pa_end = 0x47400000 + SZ_4K - 1,
3276 .flags = ADDR_TYPE_RT
3277 },
3278 {
3279 .name = "musb0",
3280 .pa_start = 0x47401000,
3281 .pa_end = 0x47401000 + SZ_2K - 1,
3282 .flags = ADDR_TYPE_RT
3283 },
3284 {
3285 .name = "musb1",
3286 .pa_start = 0x47401800,
3287 .pa_end = 0x47401800 + SZ_2K - 1,
3288 .flags = ADDR_TYPE_RT
3289 },
3290 { }
3291};
3292
3293static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
3294 .master = &am33xx_l3_s_hwmod,
3295 .slave = &am33xx_usbss_hwmod,
3296 .clk = "l3s_gclk",
3297 .addr = am33xx_usbss_addr_space,
3298 .user = OCP_USER_MPU,
3299 .flags = OCPIF_SWSUP_IDLE,
3300};
3301
3302static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3303 &am33xx_l4_fw__emif_fw,
3304 &am33xx_l3_main__emif,
3305 &am33xx_mpu__l3_main,
3306 &am33xx_mpu__prcm,
3307 &am33xx_l3_s__l4_ls,
3308 &am33xx_l3_s__l4_wkup,
3309 &am33xx_l3_s__l4_fw,
3310 &am33xx_l3_main__l4_hs,
3311 &am33xx_l3_main__l3_s,
3312 &am33xx_l3_main__l3_instr,
3313 &am33xx_l3_main__gfx,
3314 &am33xx_l3_s__l3_main,
3315 &am33xx_pruss__l3_main,
3316 &am33xx_wkup_m3__l4_wkup,
3317 &am33xx_gfx__l3_main,
3318 &am33xx_l4_wkup__wkup_m3,
3319 &am33xx_l4_wkup__control,
3320 &am33xx_l4_wkup__smartreflex0,
3321 &am33xx_l4_wkup__smartreflex1,
3322 &am33xx_l4_wkup__uart1,
3323 &am33xx_l4_wkup__timer1,
3324 &am33xx_l4_wkup__rtc,
3325 &am33xx_l4_wkup__i2c1,
3326 &am33xx_l4_wkup__gpio0,
3327 &am33xx_l4_wkup__adc_tsc,
3328 &am33xx_l4_wkup__wd_timer1,
3329 &am33xx_l4_hs__pruss,
3330 &am33xx_l4_per__dcan0,
3331 &am33xx_l4_per__dcan1,
3332 &am33xx_l4_per__gpio1,
3333 &am33xx_l4_per__gpio2,
3334 &am33xx_l4_per__gpio3,
3335 &am33xx_l4_per__i2c2,
3336 &am33xx_l4_per__i2c3,
3337 &am33xx_l4_per__mailbox,
3338 &am33xx_l4_ls__mcasp0,
3339 &am33xx_l3_s__mcasp0_data,
3340 &am33xx_l4_ls__mcasp1,
3341 &am33xx_l3_s__mcasp1_data,
3342 &am33xx_l4_ls__mmc0,
3343 &am33xx_l4_ls__mmc1,
3344 &am33xx_l3_s__mmc2,
3345 &am33xx_l4_ls__timer2,
3346 &am33xx_l4_ls__timer3,
3347 &am33xx_l4_ls__timer4,
3348 &am33xx_l4_ls__timer5,
3349 &am33xx_l4_ls__timer6,
3350 &am33xx_l4_ls__timer7,
3351 &am33xx_l3_main__tpcc,
3352 &am33xx_l4_ls__uart2,
3353 &am33xx_l4_ls__uart3,
3354 &am33xx_l4_ls__uart4,
3355 &am33xx_l4_ls__uart5,
3356 &am33xx_l4_ls__uart6,
3357 &am33xx_l4_ls__spinlock,
3358 &am33xx_l4_ls__elm,
3359 &am33xx_l4_ls__ehrpwm0,
3360 &am33xx_l4_ls__ehrpwm1,
3361 &am33xx_l4_ls__ehrpwm2,
3362 &am33xx_l4_ls__ecap0,
3363 &am33xx_l4_ls__ecap1,
3364 &am33xx_l4_ls__ecap2,
3365 &am33xx_l3_s__gpmc,
3366 &am33xx_l3_main__lcdc,
3367 &am33xx_l4_ls__mcspi0,
3368 &am33xx_l4_ls__mcspi1,
3369 &am33xx_l3_main__tptc0,
3370 &am33xx_l3_main__tptc1,
3371 &am33xx_l3_main__tptc2,
3372 &am33xx_l3_s__usbss,
3373 &am33xx_l4_hs__cpgmac0,
3374 NULL,
3375};
3376
3377int __init am33xx_hwmod_init(void)
3378{
3379 omap_hwmod_init();
3380 return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
3381}
Linux kernel - Deliverables
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