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a2cfc509 VH |
1 | /* |
2 | * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips | |
3 | * | |
4 | * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * This file is automatically generated from the AM33XX hardware databases. | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation version 2. | |
10 | * | |
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
12 | * kind, whether express or implied; without even the implied warranty | |
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
3a8761c0 TL |
17 | #include <linux/i2c-omap.h> |
18 | ||
2a296c8f | 19 | #include "omap_hwmod.h" |
11964f53 | 20 | #include <linux/platform_data/gpio-omap.h> |
aa817b2e | 21 | #include <linux/platform_data/spi-omap2-mcspi.h> |
a2cfc509 VH |
22 | |
23 | #include "omap_hwmod_common_data.h" | |
24 | ||
25 | #include "control.h" | |
26 | #include "cm33xx.h" | |
27 | #include "prm33xx.h" | |
28 | #include "prm-regbits-33xx.h" | |
3a8761c0 | 29 | #include "i2c.h" |
68f39e74 | 30 | #include "mmc.h" |
05cf03b6 | 31 | #include "wd_timer.h" |
a2cfc509 | 32 | |
a2cfc509 VH |
33 | /* |
34 | * IP blocks | |
35 | */ | |
36 | ||
a2cfc509 VH |
37 | /* |
38 | * 'emif' class | |
39 | * instance(s): emif | |
40 | */ | |
41 | static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = { | |
42 | .rev_offs = 0x0000, | |
43 | }; | |
44 | ||
45 | static struct omap_hwmod_class am33xx_emif_hwmod_class = { | |
46 | .name = "emif", | |
47 | .sysc = &am33xx_emif_sysc, | |
48 | }; | |
49 | ||
a2cfc509 VH |
50 | /* emif */ |
51 | static struct omap_hwmod am33xx_emif_hwmod = { | |
52 | .name = "emif", | |
53 | .class = &am33xx_emif_hwmod_class, | |
54 | .clkdm_name = "l3_clkdm", | |
55 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
a2cfc509 VH |
56 | .main_clk = "dpll_ddr_m2_div2_ck", |
57 | .prcm = { | |
58 | .omap4 = { | |
59 | .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET, | |
60 | .modulemode = MODULEMODE_SWCTRL, | |
61 | }, | |
62 | }, | |
63 | }; | |
64 | ||
65 | /* | |
66 | * 'l3' class | |
67 | * instance(s): l3_main, l3_s, l3_instr | |
68 | */ | |
69 | static struct omap_hwmod_class am33xx_l3_hwmod_class = { | |
70 | .name = "l3", | |
71 | }; | |
72 | ||
a2cfc509 VH |
73 | static struct omap_hwmod am33xx_l3_main_hwmod = { |
74 | .name = "l3_main", | |
75 | .class = &am33xx_l3_hwmod_class, | |
76 | .clkdm_name = "l3_clkdm", | |
77 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
a2cfc509 VH |
78 | .main_clk = "l3_gclk", |
79 | .prcm = { | |
80 | .omap4 = { | |
81 | .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET, | |
82 | .modulemode = MODULEMODE_SWCTRL, | |
83 | }, | |
84 | }, | |
85 | }; | |
86 | ||
87 | /* l3_s */ | |
88 | static struct omap_hwmod am33xx_l3_s_hwmod = { | |
89 | .name = "l3_s", | |
90 | .class = &am33xx_l3_hwmod_class, | |
91 | .clkdm_name = "l3s_clkdm", | |
92 | }; | |
93 | ||
94 | /* l3_instr */ | |
95 | static struct omap_hwmod am33xx_l3_instr_hwmod = { | |
96 | .name = "l3_instr", | |
97 | .class = &am33xx_l3_hwmod_class, | |
98 | .clkdm_name = "l3_clkdm", | |
99 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
100 | .main_clk = "l3_gclk", | |
101 | .prcm = { | |
102 | .omap4 = { | |
103 | .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET, | |
104 | .modulemode = MODULEMODE_SWCTRL, | |
105 | }, | |
106 | }, | |
107 | }; | |
108 | ||
109 | /* | |
110 | * 'l4' class | |
111 | * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw | |
112 | */ | |
113 | static struct omap_hwmod_class am33xx_l4_hwmod_class = { | |
114 | .name = "l4", | |
115 | }; | |
116 | ||
117 | /* l4_ls */ | |
118 | static struct omap_hwmod am33xx_l4_ls_hwmod = { | |
119 | .name = "l4_ls", | |
120 | .class = &am33xx_l4_hwmod_class, | |
121 | .clkdm_name = "l4ls_clkdm", | |
122 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
123 | .main_clk = "l4ls_gclk", | |
124 | .prcm = { | |
125 | .omap4 = { | |
126 | .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET, | |
127 | .modulemode = MODULEMODE_SWCTRL, | |
128 | }, | |
129 | }, | |
130 | }; | |
131 | ||
132 | /* l4_hs */ | |
133 | static struct omap_hwmod am33xx_l4_hs_hwmod = { | |
134 | .name = "l4_hs", | |
135 | .class = &am33xx_l4_hwmod_class, | |
136 | .clkdm_name = "l4hs_clkdm", | |
137 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
138 | .main_clk = "l4hs_gclk", | |
139 | .prcm = { | |
140 | .omap4 = { | |
141 | .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET, | |
142 | .modulemode = MODULEMODE_SWCTRL, | |
143 | }, | |
144 | }, | |
145 | }; | |
146 | ||
147 | ||
148 | /* l4_wkup */ | |
149 | static struct omap_hwmod am33xx_l4_wkup_hwmod = { | |
150 | .name = "l4_wkup", | |
151 | .class = &am33xx_l4_hwmod_class, | |
152 | .clkdm_name = "l4_wkup_clkdm", | |
153 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
154 | .prcm = { | |
155 | .omap4 = { | |
156 | .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, | |
157 | .modulemode = MODULEMODE_SWCTRL, | |
158 | }, | |
159 | }, | |
160 | }; | |
161 | ||
a2cfc509 VH |
162 | /* |
163 | * 'mpu' class | |
164 | */ | |
165 | static struct omap_hwmod_class am33xx_mpu_hwmod_class = { | |
166 | .name = "mpu", | |
167 | }; | |
168 | ||
a2cfc509 VH |
169 | static struct omap_hwmod am33xx_mpu_hwmod = { |
170 | .name = "mpu", | |
171 | .class = &am33xx_mpu_hwmod_class, | |
172 | .clkdm_name = "mpu_clkdm", | |
173 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
a2cfc509 VH |
174 | .main_clk = "dpll_mpu_m2_ck", |
175 | .prcm = { | |
176 | .omap4 = { | |
177 | .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET, | |
178 | .modulemode = MODULEMODE_SWCTRL, | |
179 | }, | |
180 | }, | |
181 | }; | |
182 | ||
183 | /* | |
184 | * 'wakeup m3' class | |
185 | * Wakeup controller sub-system under wakeup domain | |
186 | */ | |
187 | static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = { | |
188 | .name = "wkup_m3", | |
189 | }; | |
190 | ||
191 | static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = { | |
192 | { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, | |
193 | }; | |
194 | ||
a2cfc509 VH |
195 | /* wkup_m3 */ |
196 | static struct omap_hwmod am33xx_wkup_m3_hwmod = { | |
197 | .name = "wkup_m3", | |
198 | .class = &am33xx_wkup_m3_hwmod_class, | |
199 | .clkdm_name = "l4_wkup_aon_clkdm", | |
092bda62 HG |
200 | /* Keep hardreset asserted */ |
201 | .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST, | |
a2cfc509 VH |
202 | .main_clk = "dpll_core_m4_div2_ck", |
203 | .prcm = { | |
204 | .omap4 = { | |
205 | .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET, | |
206 | .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET, | |
3077fe69 | 207 | .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET, |
a2cfc509 VH |
208 | .modulemode = MODULEMODE_SWCTRL, |
209 | }, | |
210 | }, | |
211 | .rst_lines = am33xx_wkup_m3_resets, | |
212 | .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets), | |
213 | }; | |
214 | ||
215 | /* | |
216 | * 'pru-icss' class | |
217 | * Programmable Real-Time Unit and Industrial Communication Subsystem | |
218 | */ | |
219 | static struct omap_hwmod_class am33xx_pruss_hwmod_class = { | |
220 | .name = "pruss", | |
221 | }; | |
222 | ||
223 | static struct omap_hwmod_rst_info am33xx_pruss_resets[] = { | |
224 | { .name = "pruss", .rst_shift = 1 }, | |
225 | }; | |
226 | ||
a2cfc509 VH |
227 | /* pru-icss */ |
228 | /* Pseudo hwmod for reset control purpose only */ | |
229 | static struct omap_hwmod am33xx_pruss_hwmod = { | |
230 | .name = "pruss", | |
231 | .class = &am33xx_pruss_hwmod_class, | |
232 | .clkdm_name = "pruss_ocp_clkdm", | |
a2cfc509 VH |
233 | .main_clk = "pruss_ocp_gclk", |
234 | .prcm = { | |
235 | .omap4 = { | |
236 | .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET, | |
237 | .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET, | |
238 | .modulemode = MODULEMODE_SWCTRL, | |
239 | }, | |
240 | }, | |
241 | .rst_lines = am33xx_pruss_resets, | |
242 | .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets), | |
243 | }; | |
244 | ||
245 | /* gfx */ | |
246 | /* Pseudo hwmod for reset control purpose only */ | |
247 | static struct omap_hwmod_class am33xx_gfx_hwmod_class = { | |
248 | .name = "gfx", | |
249 | }; | |
250 | ||
251 | static struct omap_hwmod_rst_info am33xx_gfx_resets[] = { | |
27c7004a | 252 | { .name = "gfx", .rst_shift = 0, .st_shift = 0}, |
a2cfc509 VH |
253 | }; |
254 | ||
a2cfc509 VH |
255 | static struct omap_hwmod am33xx_gfx_hwmod = { |
256 | .name = "gfx", | |
257 | .class = &am33xx_gfx_hwmod_class, | |
258 | .clkdm_name = "gfx_l3_clkdm", | |
a2cfc509 VH |
259 | .main_clk = "gfx_fck_div_ck", |
260 | .prcm = { | |
261 | .omap4 = { | |
262 | .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET, | |
263 | .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET, | |
27c7004a | 264 | .rstst_offs = AM33XX_RM_GFX_RSTST_OFFSET, |
a2cfc509 VH |
265 | .modulemode = MODULEMODE_SWCTRL, |
266 | }, | |
267 | }, | |
268 | .rst_lines = am33xx_gfx_resets, | |
269 | .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets), | |
270 | }; | |
271 | ||
272 | /* | |
273 | * 'prcm' class | |
274 | * power and reset manager (whole prcm infrastructure) | |
275 | */ | |
276 | static struct omap_hwmod_class am33xx_prcm_hwmod_class = { | |
277 | .name = "prcm", | |
278 | }; | |
279 | ||
280 | /* prcm */ | |
281 | static struct omap_hwmod am33xx_prcm_hwmod = { | |
282 | .name = "prcm", | |
283 | .class = &am33xx_prcm_hwmod_class, | |
284 | .clkdm_name = "l4_wkup_clkdm", | |
285 | }; | |
286 | ||
287 | /* | |
288 | * 'adc/tsc' class | |
289 | * TouchScreen Controller (Anolog-To-Digital Converter) | |
290 | */ | |
291 | static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = { | |
292 | .rev_offs = 0x00, | |
293 | .sysc_offs = 0x10, | |
294 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
295 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
296 | SIDLE_SMART_WKUP), | |
297 | .sysc_fields = &omap_hwmod_sysc_type2, | |
298 | }; | |
299 | ||
300 | static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = { | |
301 | .name = "adc_tsc", | |
302 | .sysc = &am33xx_adc_tsc_sysc, | |
303 | }; | |
304 | ||
a2cfc509 VH |
305 | static struct omap_hwmod am33xx_adc_tsc_hwmod = { |
306 | .name = "adc_tsc", | |
307 | .class = &am33xx_adc_tsc_hwmod_class, | |
308 | .clkdm_name = "l4_wkup_clkdm", | |
a2cfc509 VH |
309 | .main_clk = "adc_tsc_fck", |
310 | .prcm = { | |
311 | .omap4 = { | |
312 | .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET, | |
313 | .modulemode = MODULEMODE_SWCTRL, | |
314 | }, | |
315 | }, | |
316 | }; | |
317 | ||
318 | /* | |
319 | * Modules omap_hwmod structures | |
320 | * | |
321 | * The following IPs are excluded for the moment because: | |
322 | * - They do not need an explicit SW control using omap_hwmod API. | |
323 | * - They still need to be validated with the driver | |
324 | * properly adapted to omap_hwmod / omap_device | |
325 | * | |
326 | * - cEFUSE (doesn't fall under any ocp_if) | |
327 | * - clkdiv32k | |
a2cfc509 | 328 | * - ocp watch point |
a2cfc509 VH |
329 | */ |
330 | #if 0 | |
331 | /* | |
332 | * 'cefuse' class | |
333 | */ | |
334 | static struct omap_hwmod_class am33xx_cefuse_hwmod_class = { | |
335 | .name = "cefuse", | |
336 | }; | |
337 | ||
338 | static struct omap_hwmod am33xx_cefuse_hwmod = { | |
339 | .name = "cefuse", | |
340 | .class = &am33xx_cefuse_hwmod_class, | |
341 | .clkdm_name = "l4_cefuse_clkdm", | |
342 | .main_clk = "cefuse_fck", | |
343 | .prcm = { | |
344 | .omap4 = { | |
345 | .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET, | |
346 | .modulemode = MODULEMODE_SWCTRL, | |
347 | }, | |
348 | }, | |
349 | }; | |
350 | ||
351 | /* | |
352 | * 'clkdiv32k' class | |
353 | */ | |
354 | static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = { | |
355 | .name = "clkdiv32k", | |
356 | }; | |
357 | ||
358 | static struct omap_hwmod am33xx_clkdiv32k_hwmod = { | |
359 | .name = "clkdiv32k", | |
360 | .class = &am33xx_clkdiv32k_hwmod_class, | |
361 | .clkdm_name = "clk_24mhz_clkdm", | |
362 | .main_clk = "clkdiv32k_ick", | |
363 | .prcm = { | |
364 | .omap4 = { | |
365 | .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET, | |
366 | .modulemode = MODULEMODE_SWCTRL, | |
367 | }, | |
368 | }, | |
369 | }; | |
370 | ||
a2cfc509 VH |
371 | /* ocpwp */ |
372 | static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = { | |
373 | .name = "ocpwp", | |
374 | }; | |
375 | ||
376 | static struct omap_hwmod am33xx_ocpwp_hwmod = { | |
377 | .name = "ocpwp", | |
378 | .class = &am33xx_ocpwp_hwmod_class, | |
379 | .clkdm_name = "l4ls_clkdm", | |
380 | .main_clk = "l4ls_gclk", | |
381 | .prcm = { | |
382 | .omap4 = { | |
383 | .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET, | |
384 | .modulemode = MODULEMODE_SWCTRL, | |
385 | }, | |
386 | }, | |
387 | }; | |
1cb804b9 | 388 | #endif |
a2cfc509 VH |
389 | |
390 | /* | |
1cb804b9 | 391 | * 'aes0' class |
a2cfc509 | 392 | */ |
1cb804b9 MG |
393 | static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = { |
394 | .rev_offs = 0x80, | |
395 | .sysc_offs = 0x84, | |
396 | .syss_offs = 0x88, | |
397 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
398 | }; | |
399 | ||
400 | static struct omap_hwmod_class am33xx_aes0_hwmod_class = { | |
401 | .name = "aes0", | |
402 | .sysc = &am33xx_aes0_sysc, | |
a2cfc509 VH |
403 | }; |
404 | ||
a2cfc509 | 405 | static struct omap_hwmod am33xx_aes0_hwmod = { |
1cb804b9 MG |
406 | .name = "aes", |
407 | .class = &am33xx_aes0_hwmod_class, | |
a2cfc509 | 408 | .clkdm_name = "l3_clkdm", |
1cb804b9 | 409 | .main_clk = "aes0_fck", |
a2cfc509 VH |
410 | .prcm = { |
411 | .omap4 = { | |
412 | .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET, | |
413 | .modulemode = MODULEMODE_SWCTRL, | |
414 | }, | |
415 | }, | |
416 | }; | |
417 | ||
aec94bf5 MG |
418 | /* sha0 HIB2 (the 'P' (public) device) */ |
419 | static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = { | |
420 | .rev_offs = 0x100, | |
421 | .sysc_offs = 0x110, | |
422 | .syss_offs = 0x114, | |
423 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
424 | }; | |
a2cfc509 | 425 | |
a2cfc509 VH |
426 | static struct omap_hwmod_class am33xx_sha0_hwmod_class = { |
427 | .name = "sha0", | |
aec94bf5 | 428 | .sysc = &am33xx_sha0_sysc, |
a2cfc509 VH |
429 | }; |
430 | ||
a2cfc509 | 431 | static struct omap_hwmod am33xx_sha0_hwmod = { |
aec94bf5 | 432 | .name = "sham", |
a2cfc509 VH |
433 | .class = &am33xx_sha0_hwmod_class, |
434 | .clkdm_name = "l3_clkdm", | |
a2cfc509 VH |
435 | .main_clk = "l3_gclk", |
436 | .prcm = { | |
437 | .omap4 = { | |
438 | .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET, | |
439 | .modulemode = MODULEMODE_SWCTRL, | |
440 | }, | |
441 | }, | |
442 | }; | |
443 | ||
ca903b6f VB |
444 | /* ocmcram */ |
445 | static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = { | |
446 | .name = "ocmcram", | |
447 | }; | |
448 | ||
449 | static struct omap_hwmod am33xx_ocmcram_hwmod = { | |
450 | .name = "ocmcram", | |
451 | .class = &am33xx_ocmcram_hwmod_class, | |
452 | .clkdm_name = "l3_clkdm", | |
453 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
454 | .main_clk = "l3_gclk", | |
455 | .prcm = { | |
456 | .omap4 = { | |
457 | .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET, | |
458 | .modulemode = MODULEMODE_SWCTRL, | |
459 | }, | |
460 | }, | |
461 | }; | |
462 | ||
1721c702 VH |
463 | /* |
464 | * 'debugss' class | |
465 | * debug sub system | |
466 | */ | |
467 | static struct omap_hwmod_opt_clk debugss_opt_clks[] = { | |
468 | { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" }, | |
469 | { .role = "dbg_clka", .clk = "dbg_clka_ck" }, | |
470 | }; | |
471 | ||
472 | static struct omap_hwmod_class am33xx_debugss_hwmod_class = { | |
473 | .name = "debugss", | |
474 | }; | |
475 | ||
476 | static struct omap_hwmod am33xx_debugss_hwmod = { | |
477 | .name = "debugss", | |
478 | .class = &am33xx_debugss_hwmod_class, | |
479 | .clkdm_name = "l3_aon_clkdm", | |
480 | .main_clk = "trace_clk_div_ck", | |
481 | .prcm = { | |
482 | .omap4 = { | |
483 | .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET, | |
484 | .modulemode = MODULEMODE_SWCTRL, | |
485 | }, | |
486 | }, | |
487 | .opt_clks = debugss_opt_clks, | |
488 | .opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks), | |
489 | }; | |
490 | ||
a2cfc509 VH |
491 | /* 'smartreflex' class */ |
492 | static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { | |
493 | .name = "smartreflex", | |
494 | }; | |
495 | ||
496 | /* smartreflex0 */ | |
a2cfc509 VH |
497 | static struct omap_hwmod am33xx_smartreflex0_hwmod = { |
498 | .name = "smartreflex0", | |
499 | .class = &am33xx_smartreflex_hwmod_class, | |
500 | .clkdm_name = "l4_wkup_clkdm", | |
a2cfc509 VH |
501 | .main_clk = "smartreflex0_fck", |
502 | .prcm = { | |
503 | .omap4 = { | |
504 | .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET, | |
505 | .modulemode = MODULEMODE_SWCTRL, | |
506 | }, | |
507 | }, | |
508 | }; | |
509 | ||
510 | /* smartreflex1 */ | |
a2cfc509 VH |
511 | static struct omap_hwmod am33xx_smartreflex1_hwmod = { |
512 | .name = "smartreflex1", | |
513 | .class = &am33xx_smartreflex_hwmod_class, | |
514 | .clkdm_name = "l4_wkup_clkdm", | |
a2cfc509 VH |
515 | .main_clk = "smartreflex1_fck", |
516 | .prcm = { | |
517 | .omap4 = { | |
518 | .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET, | |
519 | .modulemode = MODULEMODE_SWCTRL, | |
520 | }, | |
521 | }, | |
522 | }; | |
523 | ||
524 | /* | |
525 | * 'control' module class | |
526 | */ | |
527 | static struct omap_hwmod_class am33xx_control_hwmod_class = { | |
528 | .name = "control", | |
529 | }; | |
530 | ||
a2cfc509 VH |
531 | static struct omap_hwmod am33xx_control_hwmod = { |
532 | .name = "control", | |
533 | .class = &am33xx_control_hwmod_class, | |
534 | .clkdm_name = "l4_wkup_clkdm", | |
535 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
a2cfc509 VH |
536 | .main_clk = "dpll_core_m4_div2_ck", |
537 | .prcm = { | |
538 | .omap4 = { | |
539 | .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET, | |
540 | .modulemode = MODULEMODE_SWCTRL, | |
541 | }, | |
542 | }, | |
543 | }; | |
544 | ||
545 | /* | |
546 | * 'cpgmac' class | |
547 | * cpsw/cpgmac sub system | |
548 | */ | |
549 | static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = { | |
550 | .rev_offs = 0x0, | |
551 | .sysc_offs = 0x8, | |
552 | .syss_offs = 0x4, | |
553 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | | |
554 | SYSS_HAS_RESET_STATUS), | |
555 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | | |
556 | MSTANDBY_NO), | |
557 | .sysc_fields = &omap_hwmod_sysc_type3, | |
558 | }; | |
559 | ||
560 | static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = { | |
561 | .name = "cpgmac0", | |
562 | .sysc = &am33xx_cpgmac_sysc, | |
563 | }; | |
564 | ||
a2cfc509 VH |
565 | static struct omap_hwmod am33xx_cpgmac0_hwmod = { |
566 | .name = "cpgmac0", | |
567 | .class = &am33xx_cpgmac0_hwmod_class, | |
568 | .clkdm_name = "cpsw_125mhz_clkdm", | |
70384a6a | 569 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), |
a2cfc509 | 570 | .main_clk = "cpsw_125mhz_gclk", |
50c2a3a1 | 571 | .mpu_rt_idx = 1, |
a2cfc509 VH |
572 | .prcm = { |
573 | .omap4 = { | |
574 | .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET, | |
575 | .modulemode = MODULEMODE_SWCTRL, | |
576 | }, | |
577 | }, | |
578 | }; | |
579 | ||
70384a6a M |
580 | /* |
581 | * mdio class | |
582 | */ | |
583 | static struct omap_hwmod_class am33xx_mdio_hwmod_class = { | |
584 | .name = "davinci_mdio", | |
585 | }; | |
586 | ||
587 | static struct omap_hwmod am33xx_mdio_hwmod = { | |
588 | .name = "davinci_mdio", | |
589 | .class = &am33xx_mdio_hwmod_class, | |
590 | .clkdm_name = "cpsw_125mhz_clkdm", | |
591 | .main_clk = "cpsw_125mhz_gclk", | |
592 | }; | |
593 | ||
a2cfc509 VH |
594 | /* |
595 | * dcan class | |
596 | */ | |
597 | static struct omap_hwmod_class am33xx_dcan_hwmod_class = { | |
598 | .name = "d_can", | |
599 | }; | |
600 | ||
601 | /* dcan0 */ | |
a2cfc509 VH |
602 | static struct omap_hwmod am33xx_dcan0_hwmod = { |
603 | .name = "d_can0", | |
604 | .class = &am33xx_dcan_hwmod_class, | |
605 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
606 | .main_clk = "dcan0_fck", |
607 | .prcm = { | |
608 | .omap4 = { | |
609 | .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET, | |
610 | .modulemode = MODULEMODE_SWCTRL, | |
611 | }, | |
612 | }, | |
613 | }; | |
614 | ||
615 | /* dcan1 */ | |
a2cfc509 VH |
616 | static struct omap_hwmod am33xx_dcan1_hwmod = { |
617 | .name = "d_can1", | |
618 | .class = &am33xx_dcan_hwmod_class, | |
619 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
620 | .main_clk = "dcan1_fck", |
621 | .prcm = { | |
622 | .omap4 = { | |
623 | .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET, | |
624 | .modulemode = MODULEMODE_SWCTRL, | |
625 | }, | |
626 | }, | |
627 | }; | |
628 | ||
629 | /* elm */ | |
630 | static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = { | |
631 | .rev_offs = 0x0000, | |
632 | .sysc_offs = 0x0010, | |
633 | .syss_offs = 0x0014, | |
634 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
635 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
636 | SYSS_HAS_RESET_STATUS), | |
637 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
638 | .sysc_fields = &omap_hwmod_sysc_type1, | |
639 | }; | |
640 | ||
641 | static struct omap_hwmod_class am33xx_elm_hwmod_class = { | |
642 | .name = "elm", | |
643 | .sysc = &am33xx_elm_sysc, | |
644 | }; | |
645 | ||
a2cfc509 VH |
646 | static struct omap_hwmod am33xx_elm_hwmod = { |
647 | .name = "elm", | |
648 | .class = &am33xx_elm_hwmod_class, | |
649 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
650 | .main_clk = "l4ls_gclk", |
651 | .prcm = { | |
652 | .omap4 = { | |
653 | .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET, | |
654 | .modulemode = MODULEMODE_SWCTRL, | |
655 | }, | |
656 | }, | |
657 | }; | |
658 | ||
9652d19a | 659 | /* pwmss */ |
a2cfc509 VH |
660 | static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = { |
661 | .rev_offs = 0x0, | |
662 | .sysc_offs = 0x4, | |
663 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), | |
664 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
665 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
666 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
667 | .sysc_fields = &omap_hwmod_sysc_type2, | |
668 | }; | |
669 | ||
670 | static struct omap_hwmod_class am33xx_epwmss_hwmod_class = { | |
671 | .name = "epwmss", | |
672 | .sysc = &am33xx_epwmss_sysc, | |
673 | }; | |
674 | ||
9652d19a PA |
675 | static struct omap_hwmod_class am33xx_ecap_hwmod_class = { |
676 | .name = "ecap", | |
a2cfc509 VH |
677 | }; |
678 | ||
9652d19a PA |
679 | static struct omap_hwmod_class am33xx_eqep_hwmod_class = { |
680 | .name = "eqep", | |
a2cfc509 VH |
681 | }; |
682 | ||
9652d19a PA |
683 | static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = { |
684 | .name = "ehrpwm", | |
a2cfc509 VH |
685 | }; |
686 | ||
9652d19a PA |
687 | /* epwmss0 */ |
688 | static struct omap_hwmod am33xx_epwmss0_hwmod = { | |
689 | .name = "epwmss0", | |
a2cfc509 VH |
690 | .class = &am33xx_epwmss_hwmod_class, |
691 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
692 | .main_clk = "l4ls_gclk", |
693 | .prcm = { | |
694 | .omap4 = { | |
9652d19a | 695 | .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET, |
a2cfc509 VH |
696 | .modulemode = MODULEMODE_SWCTRL, |
697 | }, | |
698 | }, | |
699 | }; | |
700 | ||
9652d19a | 701 | /* ecap0 */ |
9652d19a PA |
702 | static struct omap_hwmod am33xx_ecap0_hwmod = { |
703 | .name = "ecap0", | |
704 | .class = &am33xx_ecap_hwmod_class, | |
a2cfc509 | 705 | .clkdm_name = "l4ls_clkdm", |
a2cfc509 | 706 | .main_clk = "l4ls_gclk", |
a2cfc509 VH |
707 | }; |
708 | ||
bee76659 | 709 | /* eqep0 */ |
bee76659 PA |
710 | static struct omap_hwmod am33xx_eqep0_hwmod = { |
711 | .name = "eqep0", | |
9652d19a | 712 | .class = &am33xx_eqep_hwmod_class, |
bee76659 | 713 | .clkdm_name = "l4ls_clkdm", |
bee76659 | 714 | .main_clk = "l4ls_gclk", |
bee76659 PA |
715 | }; |
716 | ||
9652d19a | 717 | /* ehrpwm0 */ |
9652d19a PA |
718 | static struct omap_hwmod am33xx_ehrpwm0_hwmod = { |
719 | .name = "ehrpwm0", | |
720 | .class = &am33xx_ehrpwm_hwmod_class, | |
721 | .clkdm_name = "l4ls_clkdm", | |
9652d19a PA |
722 | .main_clk = "l4ls_gclk", |
723 | }; | |
724 | ||
725 | /* epwmss1 */ | |
726 | static struct omap_hwmod am33xx_epwmss1_hwmod = { | |
727 | .name = "epwmss1", | |
bee76659 PA |
728 | .class = &am33xx_epwmss_hwmod_class, |
729 | .clkdm_name = "l4ls_clkdm", | |
bee76659 PA |
730 | .main_clk = "l4ls_gclk", |
731 | .prcm = { | |
732 | .omap4 = { | |
733 | .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET, | |
734 | .modulemode = MODULEMODE_SWCTRL, | |
735 | }, | |
736 | }, | |
737 | }; | |
738 | ||
9652d19a | 739 | /* ecap1 */ |
9652d19a PA |
740 | static struct omap_hwmod am33xx_ecap1_hwmod = { |
741 | .name = "ecap1", | |
742 | .class = &am33xx_ecap_hwmod_class, | |
bee76659 | 743 | .clkdm_name = "l4ls_clkdm", |
bee76659 | 744 | .main_clk = "l4ls_gclk", |
bee76659 PA |
745 | }; |
746 | ||
9652d19a | 747 | /* eqep1 */ |
9652d19a PA |
748 | static struct omap_hwmod am33xx_eqep1_hwmod = { |
749 | .name = "eqep1", | |
750 | .class = &am33xx_eqep_hwmod_class, | |
a2cfc509 | 751 | .clkdm_name = "l4ls_clkdm", |
a2cfc509 | 752 | .main_clk = "l4ls_gclk", |
a2cfc509 VH |
753 | }; |
754 | ||
9652d19a | 755 | /* ehrpwm1 */ |
9652d19a PA |
756 | static struct omap_hwmod am33xx_ehrpwm1_hwmod = { |
757 | .name = "ehrpwm1", | |
758 | .class = &am33xx_ehrpwm_hwmod_class, | |
759 | .clkdm_name = "l4ls_clkdm", | |
9652d19a PA |
760 | .main_clk = "l4ls_gclk", |
761 | }; | |
762 | ||
763 | /* epwmss2 */ | |
764 | static struct omap_hwmod am33xx_epwmss2_hwmod = { | |
765 | .name = "epwmss2", | |
a2cfc509 VH |
766 | .class = &am33xx_epwmss_hwmod_class, |
767 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
768 | .main_clk = "l4ls_gclk", |
769 | .prcm = { | |
770 | .omap4 = { | |
9652d19a | 771 | .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET, |
a2cfc509 VH |
772 | .modulemode = MODULEMODE_SWCTRL, |
773 | }, | |
774 | }, | |
775 | }; | |
776 | ||
777 | /* ecap2 */ | |
a2cfc509 VH |
778 | static struct omap_hwmod am33xx_ecap2_hwmod = { |
779 | .name = "ecap2", | |
9652d19a PA |
780 | .class = &am33xx_ecap_hwmod_class, |
781 | .clkdm_name = "l4ls_clkdm", | |
9652d19a PA |
782 | .main_clk = "l4ls_gclk", |
783 | }; | |
784 | ||
785 | /* eqep2 */ | |
9652d19a PA |
786 | static struct omap_hwmod am33xx_eqep2_hwmod = { |
787 | .name = "eqep2", | |
788 | .class = &am33xx_eqep_hwmod_class, | |
a2cfc509 | 789 | .clkdm_name = "l4ls_clkdm", |
9652d19a PA |
790 | .main_clk = "l4ls_gclk", |
791 | }; | |
792 | ||
793 | /* ehrpwm2 */ | |
9652d19a PA |
794 | static struct omap_hwmod am33xx_ehrpwm2_hwmod = { |
795 | .name = "ehrpwm2", | |
796 | .class = &am33xx_ehrpwm_hwmod_class, | |
797 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 | 798 | .main_clk = "l4ls_gclk", |
a2cfc509 VH |
799 | }; |
800 | ||
801 | /* | |
802 | * 'gpio' class: for gpio 0,1,2,3 | |
803 | */ | |
804 | static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = { | |
805 | .rev_offs = 0x0000, | |
806 | .sysc_offs = 0x0010, | |
807 | .syss_offs = 0x0114, | |
808 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
809 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
810 | SYSS_HAS_RESET_STATUS), | |
811 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
812 | SIDLE_SMART_WKUP), | |
813 | .sysc_fields = &omap_hwmod_sysc_type1, | |
814 | }; | |
815 | ||
816 | static struct omap_hwmod_class am33xx_gpio_hwmod_class = { | |
817 | .name = "gpio", | |
818 | .sysc = &am33xx_gpio_sysc, | |
819 | .rev = 2, | |
820 | }; | |
821 | ||
822 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
823 | .bank_width = 32, | |
824 | .dbck_flag = true, | |
825 | }; | |
826 | ||
827 | /* gpio0 */ | |
828 | static struct omap_hwmod_opt_clk gpio0_opt_clks[] = { | |
829 | { .role = "dbclk", .clk = "gpio0_dbclk" }, | |
830 | }; | |
831 | ||
a2cfc509 VH |
832 | static struct omap_hwmod am33xx_gpio0_hwmod = { |
833 | .name = "gpio1", | |
834 | .class = &am33xx_gpio_hwmod_class, | |
835 | .clkdm_name = "l4_wkup_clkdm", | |
836 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
a2cfc509 VH |
837 | .main_clk = "dpll_core_m4_div2_ck", |
838 | .prcm = { | |
839 | .omap4 = { | |
840 | .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET, | |
841 | .modulemode = MODULEMODE_SWCTRL, | |
842 | }, | |
843 | }, | |
844 | .opt_clks = gpio0_opt_clks, | |
845 | .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks), | |
846 | .dev_attr = &gpio_dev_attr, | |
847 | }; | |
848 | ||
849 | /* gpio1 */ | |
a2cfc509 VH |
850 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
851 | { .role = "dbclk", .clk = "gpio1_dbclk" }, | |
852 | }; | |
853 | ||
854 | static struct omap_hwmod am33xx_gpio1_hwmod = { | |
855 | .name = "gpio2", | |
856 | .class = &am33xx_gpio_hwmod_class, | |
857 | .clkdm_name = "l4ls_clkdm", | |
858 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
a2cfc509 VH |
859 | .main_clk = "l4ls_gclk", |
860 | .prcm = { | |
861 | .omap4 = { | |
862 | .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET, | |
863 | .modulemode = MODULEMODE_SWCTRL, | |
864 | }, | |
865 | }, | |
866 | .opt_clks = gpio1_opt_clks, | |
867 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
868 | .dev_attr = &gpio_dev_attr, | |
869 | }; | |
870 | ||
871 | /* gpio2 */ | |
a2cfc509 VH |
872 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
873 | { .role = "dbclk", .clk = "gpio2_dbclk" }, | |
874 | }; | |
875 | ||
876 | static struct omap_hwmod am33xx_gpio2_hwmod = { | |
877 | .name = "gpio3", | |
878 | .class = &am33xx_gpio_hwmod_class, | |
879 | .clkdm_name = "l4ls_clkdm", | |
880 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
a2cfc509 VH |
881 | .main_clk = "l4ls_gclk", |
882 | .prcm = { | |
883 | .omap4 = { | |
884 | .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET, | |
885 | .modulemode = MODULEMODE_SWCTRL, | |
886 | }, | |
887 | }, | |
888 | .opt_clks = gpio2_opt_clks, | |
889 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
890 | .dev_attr = &gpio_dev_attr, | |
891 | }; | |
892 | ||
893 | /* gpio3 */ | |
a2cfc509 VH |
894 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
895 | { .role = "dbclk", .clk = "gpio3_dbclk" }, | |
896 | }; | |
897 | ||
898 | static struct omap_hwmod am33xx_gpio3_hwmod = { | |
899 | .name = "gpio4", | |
900 | .class = &am33xx_gpio_hwmod_class, | |
901 | .clkdm_name = "l4ls_clkdm", | |
902 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
a2cfc509 VH |
903 | .main_clk = "l4ls_gclk", |
904 | .prcm = { | |
905 | .omap4 = { | |
906 | .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET, | |
907 | .modulemode = MODULEMODE_SWCTRL, | |
908 | }, | |
909 | }, | |
910 | .opt_clks = gpio3_opt_clks, | |
911 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
912 | .dev_attr = &gpio_dev_attr, | |
913 | }; | |
914 | ||
915 | /* gpmc */ | |
916 | static struct omap_hwmod_class_sysconfig gpmc_sysc = { | |
917 | .rev_offs = 0x0, | |
918 | .sysc_offs = 0x10, | |
919 | .syss_offs = 0x14, | |
920 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
921 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
922 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
923 | .sysc_fields = &omap_hwmod_sysc_type1, | |
924 | }; | |
925 | ||
926 | static struct omap_hwmod_class am33xx_gpmc_hwmod_class = { | |
927 | .name = "gpmc", | |
928 | .sysc = &gpmc_sysc, | |
929 | }; | |
930 | ||
a2cfc509 VH |
931 | static struct omap_hwmod am33xx_gpmc_hwmod = { |
932 | .name = "gpmc", | |
933 | .class = &am33xx_gpmc_hwmod_class, | |
934 | .clkdm_name = "l3s_clkdm", | |
935 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
a2cfc509 VH |
936 | .main_clk = "l3s_gclk", |
937 | .prcm = { | |
938 | .omap4 = { | |
939 | .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET, | |
940 | .modulemode = MODULEMODE_SWCTRL, | |
941 | }, | |
942 | }, | |
943 | }; | |
944 | ||
945 | /* 'i2c' class */ | |
946 | static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = { | |
947 | .sysc_offs = 0x0010, | |
948 | .syss_offs = 0x0090, | |
949 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
950 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
951 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
952 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
953 | SIDLE_SMART_WKUP), | |
954 | .sysc_fields = &omap_hwmod_sysc_type1, | |
955 | }; | |
956 | ||
957 | static struct omap_hwmod_class i2c_class = { | |
958 | .name = "i2c", | |
959 | .sysc = &am33xx_i2c_sysc, | |
960 | .rev = OMAP_I2C_IP_VERSION_2, | |
961 | .reset = &omap_i2c_reset, | |
962 | }; | |
963 | ||
964 | static struct omap_i2c_dev_attr i2c_dev_attr = { | |
972deb4f | 965 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, |
a2cfc509 VH |
966 | }; |
967 | ||
968 | /* i2c1 */ | |
a2cfc509 VH |
969 | static struct omap_hwmod am33xx_i2c1_hwmod = { |
970 | .name = "i2c1", | |
971 | .class = &i2c_class, | |
972 | .clkdm_name = "l4_wkup_clkdm", | |
a2cfc509 VH |
973 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
974 | .main_clk = "dpll_per_m2_div4_wkupdm_ck", | |
975 | .prcm = { | |
976 | .omap4 = { | |
977 | .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET, | |
978 | .modulemode = MODULEMODE_SWCTRL, | |
979 | }, | |
980 | }, | |
981 | .dev_attr = &i2c_dev_attr, | |
982 | }; | |
983 | ||
984 | /* i2c1 */ | |
a2cfc509 VH |
985 | static struct omap_hwmod am33xx_i2c2_hwmod = { |
986 | .name = "i2c2", | |
987 | .class = &i2c_class, | |
988 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
989 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
990 | .main_clk = "dpll_per_m2_div4_ck", | |
991 | .prcm = { | |
992 | .omap4 = { | |
993 | .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET, | |
994 | .modulemode = MODULEMODE_SWCTRL, | |
995 | }, | |
996 | }, | |
997 | .dev_attr = &i2c_dev_attr, | |
998 | }; | |
999 | ||
1000 | /* i2c3 */ | |
a2cfc509 VH |
1001 | static struct omap_hwmod am33xx_i2c3_hwmod = { |
1002 | .name = "i2c3", | |
1003 | .class = &i2c_class, | |
1004 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
1005 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
1006 | .main_clk = "dpll_per_m2_div4_ck", | |
1007 | .prcm = { | |
1008 | .omap4 = { | |
1009 | .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET, | |
1010 | .modulemode = MODULEMODE_SWCTRL, | |
1011 | }, | |
1012 | }, | |
1013 | .dev_attr = &i2c_dev_attr, | |
1014 | }; | |
1015 | ||
1016 | ||
1017 | /* lcdc */ | |
1018 | static struct omap_hwmod_class_sysconfig lcdc_sysc = { | |
1019 | .rev_offs = 0x0, | |
1020 | .sysc_offs = 0x54, | |
1021 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), | |
1022 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1023 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1024 | }; | |
1025 | ||
1026 | static struct omap_hwmod_class am33xx_lcdc_hwmod_class = { | |
1027 | .name = "lcdc", | |
1028 | .sysc = &lcdc_sysc, | |
1029 | }; | |
1030 | ||
a2cfc509 VH |
1031 | static struct omap_hwmod am33xx_lcdc_hwmod = { |
1032 | .name = "lcdc", | |
1033 | .class = &am33xx_lcdc_hwmod_class, | |
1034 | .clkdm_name = "lcdc_clkdm", | |
a2cfc509 VH |
1035 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
1036 | .main_clk = "lcd_gclk", | |
1037 | .prcm = { | |
1038 | .omap4 = { | |
1039 | .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET, | |
1040 | .modulemode = MODULEMODE_SWCTRL, | |
1041 | }, | |
1042 | }, | |
1043 | }; | |
1044 | ||
1045 | /* | |
1046 | * 'mailbox' class | |
1047 | * mailbox module allowing communication between the on-chip processors using a | |
1048 | * queued mailbox-interrupt mechanism. | |
1049 | */ | |
1050 | static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = { | |
1051 | .rev_offs = 0x0000, | |
1052 | .sysc_offs = 0x0010, | |
1053 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1054 | SYSC_HAS_SOFTRESET), | |
1055 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1056 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1057 | }; | |
1058 | ||
1059 | static struct omap_hwmod_class am33xx_mailbox_hwmod_class = { | |
1060 | .name = "mailbox", | |
1061 | .sysc = &am33xx_mailbox_sysc, | |
1062 | }; | |
1063 | ||
a2cfc509 VH |
1064 | static struct omap_hwmod am33xx_mailbox_hwmod = { |
1065 | .name = "mailbox", | |
1066 | .class = &am33xx_mailbox_hwmod_class, | |
1067 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
1068 | .main_clk = "l4ls_gclk", |
1069 | .prcm = { | |
1070 | .omap4 = { | |
1071 | .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET, | |
1072 | .modulemode = MODULEMODE_SWCTRL, | |
1073 | }, | |
1074 | }, | |
1075 | }; | |
1076 | ||
1077 | /* | |
1078 | * 'mcasp' class | |
1079 | */ | |
1080 | static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = { | |
1081 | .rev_offs = 0x0, | |
1082 | .sysc_offs = 0x4, | |
1083 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
1084 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1085 | .sysc_fields = &omap_hwmod_sysc_type3, | |
1086 | }; | |
1087 | ||
1088 | static struct omap_hwmod_class am33xx_mcasp_hwmod_class = { | |
1089 | .name = "mcasp", | |
1090 | .sysc = &am33xx_mcasp_sysc, | |
1091 | }; | |
1092 | ||
1093 | /* mcasp0 */ | |
a2cfc509 VH |
1094 | static struct omap_hwmod am33xx_mcasp0_hwmod = { |
1095 | .name = "mcasp0", | |
1096 | .class = &am33xx_mcasp_hwmod_class, | |
1097 | .clkdm_name = "l3s_clkdm", | |
a2cfc509 VH |
1098 | .main_clk = "mcasp0_fck", |
1099 | .prcm = { | |
1100 | .omap4 = { | |
1101 | .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET, | |
1102 | .modulemode = MODULEMODE_SWCTRL, | |
1103 | }, | |
1104 | }, | |
1105 | }; | |
1106 | ||
1107 | /* mcasp1 */ | |
a2cfc509 VH |
1108 | static struct omap_hwmod am33xx_mcasp1_hwmod = { |
1109 | .name = "mcasp1", | |
1110 | .class = &am33xx_mcasp_hwmod_class, | |
1111 | .clkdm_name = "l3s_clkdm", | |
a2cfc509 VH |
1112 | .main_clk = "mcasp1_fck", |
1113 | .prcm = { | |
1114 | .omap4 = { | |
1115 | .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET, | |
1116 | .modulemode = MODULEMODE_SWCTRL, | |
1117 | }, | |
1118 | }, | |
1119 | }; | |
1120 | ||
1121 | /* 'mmc' class */ | |
1122 | static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = { | |
1123 | .rev_offs = 0x1fc, | |
1124 | .sysc_offs = 0x10, | |
1125 | .syss_offs = 0x14, | |
1126 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1127 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1128 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1129 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1130 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1131 | }; | |
1132 | ||
1133 | static struct omap_hwmod_class am33xx_mmc_hwmod_class = { | |
1134 | .name = "mmc", | |
1135 | .sysc = &am33xx_mmc_sysc, | |
1136 | }; | |
1137 | ||
1138 | /* mmc0 */ | |
a2cfc509 VH |
1139 | static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = { |
1140 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
1141 | }; | |
1142 | ||
1143 | static struct omap_hwmod am33xx_mmc0_hwmod = { | |
1144 | .name = "mmc1", | |
1145 | .class = &am33xx_mmc_hwmod_class, | |
1146 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
1147 | .main_clk = "mmc_clk", |
1148 | .prcm = { | |
1149 | .omap4 = { | |
1150 | .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET, | |
1151 | .modulemode = MODULEMODE_SWCTRL, | |
1152 | }, | |
1153 | }, | |
1154 | .dev_attr = &am33xx_mmc0_dev_attr, | |
1155 | }; | |
1156 | ||
1157 | /* mmc1 */ | |
a2cfc509 VH |
1158 | static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = { |
1159 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
1160 | }; | |
1161 | ||
1162 | static struct omap_hwmod am33xx_mmc1_hwmod = { | |
1163 | .name = "mmc2", | |
1164 | .class = &am33xx_mmc_hwmod_class, | |
1165 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
1166 | .main_clk = "mmc_clk", |
1167 | .prcm = { | |
1168 | .omap4 = { | |
1169 | .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET, | |
1170 | .modulemode = MODULEMODE_SWCTRL, | |
1171 | }, | |
1172 | }, | |
1173 | .dev_attr = &am33xx_mmc1_dev_attr, | |
1174 | }; | |
1175 | ||
1176 | /* mmc2 */ | |
a2cfc509 VH |
1177 | static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = { |
1178 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
1179 | }; | |
1180 | static struct omap_hwmod am33xx_mmc2_hwmod = { | |
1181 | .name = "mmc3", | |
1182 | .class = &am33xx_mmc_hwmod_class, | |
1183 | .clkdm_name = "l3s_clkdm", | |
a2cfc509 VH |
1184 | .main_clk = "mmc_clk", |
1185 | .prcm = { | |
1186 | .omap4 = { | |
1187 | .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET, | |
1188 | .modulemode = MODULEMODE_SWCTRL, | |
1189 | }, | |
1190 | }, | |
1191 | .dev_attr = &am33xx_mmc2_dev_attr, | |
1192 | }; | |
1193 | ||
1194 | /* | |
1195 | * 'rtc' class | |
1196 | * rtc subsystem | |
1197 | */ | |
1198 | static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = { | |
1199 | .rev_offs = 0x0074, | |
1200 | .sysc_offs = 0x0078, | |
1201 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
1202 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | | |
1203 | SIDLE_SMART | SIDLE_SMART_WKUP), | |
1204 | .sysc_fields = &omap_hwmod_sysc_type3, | |
1205 | }; | |
1206 | ||
1207 | static struct omap_hwmod_class am33xx_rtc_hwmod_class = { | |
1208 | .name = "rtc", | |
1209 | .sysc = &am33xx_rtc_sysc, | |
1210 | }; | |
1211 | ||
a2cfc509 VH |
1212 | static struct omap_hwmod am33xx_rtc_hwmod = { |
1213 | .name = "rtc", | |
1214 | .class = &am33xx_rtc_hwmod_class, | |
1215 | .clkdm_name = "l4_rtc_clkdm", | |
a2cfc509 VH |
1216 | .main_clk = "clk_32768_ck", |
1217 | .prcm = { | |
1218 | .omap4 = { | |
1219 | .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET, | |
1220 | .modulemode = MODULEMODE_SWCTRL, | |
1221 | }, | |
1222 | }, | |
1223 | }; | |
1224 | ||
1225 | /* 'spi' class */ | |
1226 | static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = { | |
1227 | .rev_offs = 0x0000, | |
1228 | .sysc_offs = 0x0110, | |
1229 | .syss_offs = 0x0114, | |
1230 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1231 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
1232 | SYSS_HAS_RESET_STATUS), | |
1233 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1234 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1235 | }; | |
1236 | ||
1237 | static struct omap_hwmod_class am33xx_spi_hwmod_class = { | |
1238 | .name = "mcspi", | |
1239 | .sysc = &am33xx_mcspi_sysc, | |
1240 | .rev = OMAP4_MCSPI_REV, | |
1241 | }; | |
1242 | ||
1243 | /* spi0 */ | |
a2cfc509 VH |
1244 | static struct omap2_mcspi_dev_attr mcspi_attrib = { |
1245 | .num_chipselect = 2, | |
1246 | }; | |
1247 | static struct omap_hwmod am33xx_spi0_hwmod = { | |
1248 | .name = "spi0", | |
1249 | .class = &am33xx_spi_hwmod_class, | |
1250 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
1251 | .main_clk = "dpll_per_m2_div4_ck", |
1252 | .prcm = { | |
1253 | .omap4 = { | |
1254 | .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET, | |
1255 | .modulemode = MODULEMODE_SWCTRL, | |
1256 | }, | |
1257 | }, | |
1258 | .dev_attr = &mcspi_attrib, | |
1259 | }; | |
1260 | ||
1261 | /* spi1 */ | |
a2cfc509 VH |
1262 | static struct omap_hwmod am33xx_spi1_hwmod = { |
1263 | .name = "spi1", | |
1264 | .class = &am33xx_spi_hwmod_class, | |
1265 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
1266 | .main_clk = "dpll_per_m2_div4_ck", |
1267 | .prcm = { | |
1268 | .omap4 = { | |
1269 | .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET, | |
1270 | .modulemode = MODULEMODE_SWCTRL, | |
1271 | }, | |
1272 | }, | |
1273 | .dev_attr = &mcspi_attrib, | |
1274 | }; | |
1275 | ||
1276 | /* | |
1277 | * 'spinlock' class | |
1278 | * spinlock provides hardware assistance for synchronizing the | |
1279 | * processes running on multiple processors | |
1280 | */ | |
f0d48990 SA |
1281 | |
1282 | static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = { | |
1283 | .rev_offs = 0x0000, | |
1284 | .sysc_offs = 0x0010, | |
1285 | .syss_offs = 0x0014, | |
1286 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1287 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
1288 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1289 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1290 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1291 | }; | |
1292 | ||
a2cfc509 VH |
1293 | static struct omap_hwmod_class am33xx_spinlock_hwmod_class = { |
1294 | .name = "spinlock", | |
f0d48990 | 1295 | .sysc = &am33xx_spinlock_sysc, |
a2cfc509 VH |
1296 | }; |
1297 | ||
1298 | static struct omap_hwmod am33xx_spinlock_hwmod = { | |
1299 | .name = "spinlock", | |
1300 | .class = &am33xx_spinlock_hwmod_class, | |
1301 | .clkdm_name = "l4ls_clkdm", | |
1302 | .main_clk = "l4ls_gclk", | |
1303 | .prcm = { | |
1304 | .omap4 = { | |
1305 | .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET, | |
1306 | .modulemode = MODULEMODE_SWCTRL, | |
1307 | }, | |
1308 | }, | |
1309 | }; | |
1310 | ||
1311 | /* 'timer 2-7' class */ | |
1312 | static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = { | |
1313 | .rev_offs = 0x0000, | |
1314 | .sysc_offs = 0x0010, | |
1315 | .syss_offs = 0x0014, | |
1316 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1317 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1318 | SIDLE_SMART_WKUP), | |
1319 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1320 | }; | |
1321 | ||
1322 | static struct omap_hwmod_class am33xx_timer_hwmod_class = { | |
1323 | .name = "timer", | |
1324 | .sysc = &am33xx_timer_sysc, | |
1325 | }; | |
1326 | ||
1327 | /* timer1 1ms */ | |
1328 | static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = { | |
1329 | .rev_offs = 0x0000, | |
1330 | .sysc_offs = 0x0010, | |
1331 | .syss_offs = 0x0014, | |
1332 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1333 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
1334 | SYSS_HAS_RESET_STATUS), | |
1335 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1336 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1337 | }; | |
1338 | ||
1339 | static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = { | |
1340 | .name = "timer", | |
1341 | .sysc = &am33xx_timer1ms_sysc, | |
1342 | }; | |
1343 | ||
a2cfc509 VH |
1344 | static struct omap_hwmod am33xx_timer1_hwmod = { |
1345 | .name = "timer1", | |
1346 | .class = &am33xx_timer1ms_hwmod_class, | |
1347 | .clkdm_name = "l4_wkup_clkdm", | |
a2cfc509 VH |
1348 | .main_clk = "timer1_fck", |
1349 | .prcm = { | |
1350 | .omap4 = { | |
1351 | .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET, | |
1352 | .modulemode = MODULEMODE_SWCTRL, | |
1353 | }, | |
1354 | }, | |
1355 | }; | |
1356 | ||
a2cfc509 VH |
1357 | static struct omap_hwmod am33xx_timer2_hwmod = { |
1358 | .name = "timer2", | |
1359 | .class = &am33xx_timer_hwmod_class, | |
1360 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
1361 | .main_clk = "timer2_fck", |
1362 | .prcm = { | |
1363 | .omap4 = { | |
1364 | .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET, | |
1365 | .modulemode = MODULEMODE_SWCTRL, | |
1366 | }, | |
1367 | }, | |
1368 | }; | |
1369 | ||
a2cfc509 VH |
1370 | static struct omap_hwmod am33xx_timer3_hwmod = { |
1371 | .name = "timer3", | |
1372 | .class = &am33xx_timer_hwmod_class, | |
1373 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
1374 | .main_clk = "timer3_fck", |
1375 | .prcm = { | |
1376 | .omap4 = { | |
1377 | .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET, | |
1378 | .modulemode = MODULEMODE_SWCTRL, | |
1379 | }, | |
1380 | }, | |
1381 | }; | |
1382 | ||
a2cfc509 VH |
1383 | static struct omap_hwmod am33xx_timer4_hwmod = { |
1384 | .name = "timer4", | |
1385 | .class = &am33xx_timer_hwmod_class, | |
1386 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
1387 | .main_clk = "timer4_fck", |
1388 | .prcm = { | |
1389 | .omap4 = { | |
1390 | .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET, | |
1391 | .modulemode = MODULEMODE_SWCTRL, | |
1392 | }, | |
1393 | }, | |
1394 | }; | |
1395 | ||
a2cfc509 VH |
1396 | static struct omap_hwmod am33xx_timer5_hwmod = { |
1397 | .name = "timer5", | |
1398 | .class = &am33xx_timer_hwmod_class, | |
1399 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
1400 | .main_clk = "timer5_fck", |
1401 | .prcm = { | |
1402 | .omap4 = { | |
1403 | .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET, | |
1404 | .modulemode = MODULEMODE_SWCTRL, | |
1405 | }, | |
1406 | }, | |
1407 | }; | |
1408 | ||
a2cfc509 VH |
1409 | static struct omap_hwmod am33xx_timer6_hwmod = { |
1410 | .name = "timer6", | |
1411 | .class = &am33xx_timer_hwmod_class, | |
1412 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
1413 | .main_clk = "timer6_fck", |
1414 | .prcm = { | |
1415 | .omap4 = { | |
1416 | .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET, | |
1417 | .modulemode = MODULEMODE_SWCTRL, | |
1418 | }, | |
1419 | }, | |
1420 | }; | |
1421 | ||
a2cfc509 VH |
1422 | static struct omap_hwmod am33xx_timer7_hwmod = { |
1423 | .name = "timer7", | |
1424 | .class = &am33xx_timer_hwmod_class, | |
1425 | .clkdm_name = "l4ls_clkdm", | |
a2cfc509 VH |
1426 | .main_clk = "timer7_fck", |
1427 | .prcm = { | |
1428 | .omap4 = { | |
1429 | .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET, | |
1430 | .modulemode = MODULEMODE_SWCTRL, | |
1431 | }, | |
1432 | }, | |
1433 | }; | |
1434 | ||
1435 | /* tpcc */ | |
1436 | static struct omap_hwmod_class am33xx_tpcc_hwmod_class = { | |
1437 | .name = "tpcc", | |
1438 | }; | |
1439 | ||
a2cfc509 VH |
1440 | static struct omap_hwmod am33xx_tpcc_hwmod = { |
1441 | .name = "tpcc", | |
1442 | .class = &am33xx_tpcc_hwmod_class, | |
1443 | .clkdm_name = "l3_clkdm", | |
a2cfc509 VH |
1444 | .main_clk = "l3_gclk", |
1445 | .prcm = { | |
1446 | .omap4 = { | |
1447 | .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET, | |
1448 | .modulemode = MODULEMODE_SWCTRL, | |
1449 | }, | |
1450 | }, | |
1451 | }; | |
1452 | ||
1453 | static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = { | |
1454 | .rev_offs = 0x0, | |
1455 | .sysc_offs = 0x10, | |
1456 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1457 | SYSC_HAS_MIDLEMODE), | |
1458 | .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE), | |
1459 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1460 | }; | |
1461 | ||
1462 | /* 'tptc' class */ | |
1463 | static struct omap_hwmod_class am33xx_tptc_hwmod_class = { | |
1464 | .name = "tptc", | |
1465 | .sysc = &am33xx_tptc_sysc, | |
1466 | }; | |
1467 | ||
1468 | /* tptc0 */ | |
a2cfc509 VH |
1469 | static struct omap_hwmod am33xx_tptc0_hwmod = { |
1470 | .name = "tptc0", | |
1471 | .class = &am33xx_tptc_hwmod_class, | |
1472 | .clkdm_name = "l3_clkdm", | |
0bfbbded | 1473 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
a2cfc509 VH |
1474 | .main_clk = "l3_gclk", |
1475 | .prcm = { | |
1476 | .omap4 = { | |
1477 | .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET, | |
1478 | .modulemode = MODULEMODE_SWCTRL, | |
1479 | }, | |
1480 | }, | |
1481 | }; | |
1482 | ||
1483 | /* tptc1 */ | |
a2cfc509 VH |
1484 | static struct omap_hwmod am33xx_tptc1_hwmod = { |
1485 | .name = "tptc1", | |
1486 | .class = &am33xx_tptc_hwmod_class, | |
1487 | .clkdm_name = "l3_clkdm", | |
a2cfc509 VH |
1488 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), |
1489 | .main_clk = "l3_gclk", | |
1490 | .prcm = { | |
1491 | .omap4 = { | |
1492 | .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET, | |
1493 | .modulemode = MODULEMODE_SWCTRL, | |
1494 | }, | |
1495 | }, | |
1496 | }; | |
1497 | ||
1498 | /* tptc2 */ | |
a2cfc509 VH |
1499 | static struct omap_hwmod am33xx_tptc2_hwmod = { |
1500 | .name = "tptc2", | |
1501 | .class = &am33xx_tptc_hwmod_class, | |
1502 | .clkdm_name = "l3_clkdm", | |
a2cfc509 VH |
1503 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), |
1504 | .main_clk = "l3_gclk", | |
1505 | .prcm = { | |
1506 | .omap4 = { | |
1507 | .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET, | |
1508 | .modulemode = MODULEMODE_SWCTRL, | |
1509 | }, | |
1510 | }, | |
1511 | }; | |
1512 | ||
1513 | /* 'uart' class */ | |
1514 | static struct omap_hwmod_class_sysconfig uart_sysc = { | |
1515 | .rev_offs = 0x50, | |
1516 | .sysc_offs = 0x54, | |
1517 | .syss_offs = 0x58, | |
1518 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
1519 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1520 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1521 | SIDLE_SMART_WKUP), | |
1522 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1523 | }; | |
1524 | ||
1525 | static struct omap_hwmod_class uart_class = { | |
1526 | .name = "uart", | |
1527 | .sysc = &uart_sysc, | |
1528 | }; | |
1529 | ||
1530 | /* uart1 */ | |
a2cfc509 VH |
1531 | static struct omap_hwmod am33xx_uart1_hwmod = { |
1532 | .name = "uart1", | |
1533 | .class = &uart_class, | |
1534 | .clkdm_name = "l4_wkup_clkdm", | |
7dedd346 | 1535 | .flags = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT, |
a2cfc509 VH |
1536 | .main_clk = "dpll_per_m2_div4_wkupdm_ck", |
1537 | .prcm = { | |
1538 | .omap4 = { | |
1539 | .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET, | |
1540 | .modulemode = MODULEMODE_SWCTRL, | |
1541 | }, | |
1542 | }, | |
1543 | }; | |
1544 | ||
a2cfc509 VH |
1545 | static struct omap_hwmod am33xx_uart2_hwmod = { |
1546 | .name = "uart2", | |
1547 | .class = &uart_class, | |
1548 | .clkdm_name = "l4ls_clkdm", | |
66dde54e | 1549 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
a2cfc509 VH |
1550 | .main_clk = "dpll_per_m2_div4_ck", |
1551 | .prcm = { | |
1552 | .omap4 = { | |
1553 | .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET, | |
1554 | .modulemode = MODULEMODE_SWCTRL, | |
1555 | }, | |
1556 | }, | |
1557 | }; | |
1558 | ||
1559 | /* uart3 */ | |
a2cfc509 VH |
1560 | static struct omap_hwmod am33xx_uart3_hwmod = { |
1561 | .name = "uart3", | |
1562 | .class = &uart_class, | |
1563 | .clkdm_name = "l4ls_clkdm", | |
66dde54e | 1564 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
a2cfc509 VH |
1565 | .main_clk = "dpll_per_m2_div4_ck", |
1566 | .prcm = { | |
1567 | .omap4 = { | |
1568 | .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET, | |
1569 | .modulemode = MODULEMODE_SWCTRL, | |
1570 | }, | |
1571 | }, | |
1572 | }; | |
1573 | ||
a2cfc509 VH |
1574 | static struct omap_hwmod am33xx_uart4_hwmod = { |
1575 | .name = "uart4", | |
1576 | .class = &uart_class, | |
1577 | .clkdm_name = "l4ls_clkdm", | |
66dde54e | 1578 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
a2cfc509 VH |
1579 | .main_clk = "dpll_per_m2_div4_ck", |
1580 | .prcm = { | |
1581 | .omap4 = { | |
1582 | .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET, | |
1583 | .modulemode = MODULEMODE_SWCTRL, | |
1584 | }, | |
1585 | }, | |
1586 | }; | |
1587 | ||
a2cfc509 VH |
1588 | static struct omap_hwmod am33xx_uart5_hwmod = { |
1589 | .name = "uart5", | |
1590 | .class = &uart_class, | |
1591 | .clkdm_name = "l4ls_clkdm", | |
66dde54e | 1592 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
a2cfc509 VH |
1593 | .main_clk = "dpll_per_m2_div4_ck", |
1594 | .prcm = { | |
1595 | .omap4 = { | |
1596 | .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET, | |
1597 | .modulemode = MODULEMODE_SWCTRL, | |
1598 | }, | |
1599 | }, | |
1600 | }; | |
1601 | ||
a2cfc509 VH |
1602 | static struct omap_hwmod am33xx_uart6_hwmod = { |
1603 | .name = "uart6", | |
1604 | .class = &uart_class, | |
1605 | .clkdm_name = "l4ls_clkdm", | |
66dde54e | 1606 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
a2cfc509 VH |
1607 | .main_clk = "dpll_per_m2_div4_ck", |
1608 | .prcm = { | |
1609 | .omap4 = { | |
1610 | .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET, | |
1611 | .modulemode = MODULEMODE_SWCTRL, | |
1612 | }, | |
1613 | }, | |
1614 | }; | |
1615 | ||
1616 | /* 'wd_timer' class */ | |
05cf03b6 VH |
1617 | static struct omap_hwmod_class_sysconfig wdt_sysc = { |
1618 | .rev_offs = 0x0, | |
1619 | .sysc_offs = 0x10, | |
1620 | .syss_offs = 0x14, | |
1621 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
1622 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1623 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1624 | SIDLE_SMART_WKUP), | |
1625 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1626 | }; | |
1627 | ||
a2cfc509 VH |
1628 | static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = { |
1629 | .name = "wd_timer", | |
05cf03b6 VH |
1630 | .sysc = &wdt_sysc, |
1631 | .pre_shutdown = &omap2_wd_timer_disable, | |
a2cfc509 VH |
1632 | }; |
1633 | ||
1634 | /* | |
1635 | * XXX: device.c file uses hardcoded name for watchdog timer | |
1636 | * driver "wd_timer2, so we are also using same name as of now... | |
1637 | */ | |
1638 | static struct omap_hwmod am33xx_wd_timer1_hwmod = { | |
1639 | .name = "wd_timer2", | |
1640 | .class = &am33xx_wd_timer_hwmod_class, | |
1641 | .clkdm_name = "l4_wkup_clkdm", | |
05cf03b6 | 1642 | .flags = HWMOD_SWSUP_SIDLE, |
a2cfc509 VH |
1643 | .main_clk = "wdt1_fck", |
1644 | .prcm = { | |
1645 | .omap4 = { | |
1646 | .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET, | |
1647 | .modulemode = MODULEMODE_SWCTRL, | |
1648 | }, | |
1649 | }, | |
1650 | }; | |
1651 | ||
1652 | /* | |
1653 | * 'usb_otg' class | |
1654 | * high-speed on-the-go universal serial bus (usb_otg) controller | |
1655 | */ | |
1656 | static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = { | |
1657 | .rev_offs = 0x0, | |
1658 | .sysc_offs = 0x10, | |
1659 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), | |
1660 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1661 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1662 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1663 | }; | |
1664 | ||
1665 | static struct omap_hwmod_class am33xx_usbotg_class = { | |
1666 | .name = "usbotg", | |
1667 | .sysc = &am33xx_usbhsotg_sysc, | |
1668 | }; | |
1669 | ||
a2cfc509 VH |
1670 | static struct omap_hwmod am33xx_usbss_hwmod = { |
1671 | .name = "usb_otg_hs", | |
1672 | .class = &am33xx_usbotg_class, | |
1673 | .clkdm_name = "l3s_clkdm", | |
a2cfc509 VH |
1674 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
1675 | .main_clk = "usbotg_fck", | |
1676 | .prcm = { | |
1677 | .omap4 = { | |
1678 | .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET, | |
1679 | .modulemode = MODULEMODE_SWCTRL, | |
1680 | }, | |
1681 | }, | |
1682 | }; | |
1683 | ||
1684 | ||
1685 | /* | |
1686 | * Interfaces | |
1687 | */ | |
1688 | ||
a2cfc509 VH |
1689 | static struct omap_hwmod_addr_space am33xx_emif_addrs[] = { |
1690 | { | |
1691 | .pa_start = 0x4c000000, | |
1692 | .pa_end = 0x4c000fff, | |
1693 | .flags = ADDR_TYPE_RT | |
1694 | }, | |
1695 | { } | |
1696 | }; | |
1697 | /* l3 main -> emif */ | |
1698 | static struct omap_hwmod_ocp_if am33xx_l3_main__emif = { | |
1699 | .master = &am33xx_l3_main_hwmod, | |
1700 | .slave = &am33xx_emif_hwmod, | |
1701 | .clk = "dpll_core_m4_ck", | |
1702 | .addr = am33xx_emif_addrs, | |
1703 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1704 | }; | |
1705 | ||
1706 | /* mpu -> l3 main */ | |
1707 | static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = { | |
1708 | .master = &am33xx_mpu_hwmod, | |
1709 | .slave = &am33xx_l3_main_hwmod, | |
1710 | .clk = "dpll_mpu_m2_ck", | |
1711 | .user = OCP_USER_MPU, | |
1712 | }; | |
1713 | ||
1714 | /* l3 main -> l4 hs */ | |
1715 | static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = { | |
1716 | .master = &am33xx_l3_main_hwmod, | |
1717 | .slave = &am33xx_l4_hs_hwmod, | |
1718 | .clk = "l3s_gclk", | |
1719 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1720 | }; | |
1721 | ||
1722 | /* l3 main -> l3 s */ | |
1723 | static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = { | |
1724 | .master = &am33xx_l3_main_hwmod, | |
1725 | .slave = &am33xx_l3_s_hwmod, | |
1726 | .clk = "l3s_gclk", | |
1727 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1728 | }; | |
1729 | ||
1730 | /* l3 s -> l4 per/ls */ | |
1731 | static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = { | |
1732 | .master = &am33xx_l3_s_hwmod, | |
1733 | .slave = &am33xx_l4_ls_hwmod, | |
1734 | .clk = "l3s_gclk", | |
1735 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1736 | }; | |
1737 | ||
1738 | /* l3 s -> l4 wkup */ | |
1739 | static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = { | |
1740 | .master = &am33xx_l3_s_hwmod, | |
1741 | .slave = &am33xx_l4_wkup_hwmod, | |
1742 | .clk = "l3s_gclk", | |
1743 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1744 | }; | |
1745 | ||
a2cfc509 VH |
1746 | /* l3 main -> l3 instr */ |
1747 | static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = { | |
1748 | .master = &am33xx_l3_main_hwmod, | |
1749 | .slave = &am33xx_l3_instr_hwmod, | |
1750 | .clk = "l3s_gclk", | |
1751 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1752 | }; | |
1753 | ||
1754 | /* mpu -> prcm */ | |
1755 | static struct omap_hwmod_ocp_if am33xx_mpu__prcm = { | |
1756 | .master = &am33xx_mpu_hwmod, | |
1757 | .slave = &am33xx_prcm_hwmod, | |
1758 | .clk = "dpll_mpu_m2_ck", | |
1759 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1760 | }; | |
1761 | ||
1762 | /* l3 s -> l3 main*/ | |
1763 | static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = { | |
1764 | .master = &am33xx_l3_s_hwmod, | |
1765 | .slave = &am33xx_l3_main_hwmod, | |
1766 | .clk = "l3s_gclk", | |
1767 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1768 | }; | |
1769 | ||
1770 | /* pru-icss -> l3 main */ | |
1771 | static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = { | |
1772 | .master = &am33xx_pruss_hwmod, | |
1773 | .slave = &am33xx_l3_main_hwmod, | |
1774 | .clk = "l3_gclk", | |
1775 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1776 | }; | |
1777 | ||
1778 | /* wkup m3 -> l4 wkup */ | |
1779 | static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = { | |
1780 | .master = &am33xx_wkup_m3_hwmod, | |
1781 | .slave = &am33xx_l4_wkup_hwmod, | |
1782 | .clk = "dpll_core_m4_div2_ck", | |
1783 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1784 | }; | |
1785 | ||
1786 | /* gfx -> l3 main */ | |
1787 | static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = { | |
1788 | .master = &am33xx_gfx_hwmod, | |
1789 | .slave = &am33xx_l3_main_hwmod, | |
1790 | .clk = "dpll_core_m4_ck", | |
1791 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1792 | }; | |
1793 | ||
1794 | /* l4 wkup -> wkup m3 */ | |
a2cfc509 VH |
1795 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = { |
1796 | .master = &am33xx_l4_wkup_hwmod, | |
1797 | .slave = &am33xx_wkup_m3_hwmod, | |
1798 | .clk = "dpll_core_m4_div2_ck", | |
a2cfc509 VH |
1799 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1800 | }; | |
1801 | ||
1802 | /* l4 hs -> pru-icss */ | |
a2cfc509 VH |
1803 | static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = { |
1804 | .master = &am33xx_l4_hs_hwmod, | |
1805 | .slave = &am33xx_pruss_hwmod, | |
1806 | .clk = "dpll_core_m4_ck", | |
a2cfc509 VH |
1807 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1808 | }; | |
1809 | ||
1810 | /* l3 main -> gfx */ | |
a2cfc509 VH |
1811 | static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = { |
1812 | .master = &am33xx_l3_main_hwmod, | |
1813 | .slave = &am33xx_gfx_hwmod, | |
1814 | .clk = "dpll_core_m4_ck", | |
a2cfc509 VH |
1815 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1816 | }; | |
1817 | ||
1721c702 VH |
1818 | /* l3_main -> debugss */ |
1819 | static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = { | |
1820 | { | |
1821 | .pa_start = 0x4b000000, | |
1822 | .pa_end = 0x4b000000 + SZ_16M - 1, | |
1823 | .flags = ADDR_TYPE_RT | |
1824 | }, | |
1825 | { } | |
1826 | }; | |
1827 | ||
1828 | static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = { | |
1829 | .master = &am33xx_l3_main_hwmod, | |
1830 | .slave = &am33xx_debugss_hwmod, | |
1831 | .clk = "dpll_core_m4_ck", | |
1832 | .addr = am33xx_debugss_addrs, | |
1833 | .user = OCP_USER_MPU, | |
1834 | }; | |
1835 | ||
a2cfc509 | 1836 | /* l4 wkup -> smartreflex0 */ |
a2cfc509 VH |
1837 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = { |
1838 | .master = &am33xx_l4_wkup_hwmod, | |
1839 | .slave = &am33xx_smartreflex0_hwmod, | |
1840 | .clk = "dpll_core_m4_div2_ck", | |
a2cfc509 VH |
1841 | .user = OCP_USER_MPU, |
1842 | }; | |
1843 | ||
1844 | /* l4 wkup -> smartreflex1 */ | |
a2cfc509 VH |
1845 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = { |
1846 | .master = &am33xx_l4_wkup_hwmod, | |
1847 | .slave = &am33xx_smartreflex1_hwmod, | |
1848 | .clk = "dpll_core_m4_div2_ck", | |
a2cfc509 VH |
1849 | .user = OCP_USER_MPU, |
1850 | }; | |
1851 | ||
1852 | /* l4 wkup -> control */ | |
a2cfc509 VH |
1853 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = { |
1854 | .master = &am33xx_l4_wkup_hwmod, | |
1855 | .slave = &am33xx_control_hwmod, | |
1856 | .clk = "dpll_core_m4_div2_ck", | |
a2cfc509 VH |
1857 | .user = OCP_USER_MPU, |
1858 | }; | |
1859 | ||
1860 | /* l4 wkup -> rtc */ | |
a2cfc509 VH |
1861 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = { |
1862 | .master = &am33xx_l4_wkup_hwmod, | |
1863 | .slave = &am33xx_rtc_hwmod, | |
1864 | .clk = "clkdiv32k_ick", | |
a2cfc509 VH |
1865 | .user = OCP_USER_MPU, |
1866 | }; | |
1867 | ||
1868 | /* l4 per/ls -> DCAN0 */ | |
a2cfc509 VH |
1869 | static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = { |
1870 | .master = &am33xx_l4_ls_hwmod, | |
1871 | .slave = &am33xx_dcan0_hwmod, | |
1872 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
1873 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1874 | }; | |
1875 | ||
1876 | /* l4 per/ls -> DCAN1 */ | |
a2cfc509 VH |
1877 | static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = { |
1878 | .master = &am33xx_l4_ls_hwmod, | |
1879 | .slave = &am33xx_dcan1_hwmod, | |
1880 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
1881 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1882 | }; | |
1883 | ||
1884 | /* l4 per/ls -> GPIO2 */ | |
a2cfc509 VH |
1885 | static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = { |
1886 | .master = &am33xx_l4_ls_hwmod, | |
1887 | .slave = &am33xx_gpio1_hwmod, | |
1888 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
1889 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1890 | }; | |
1891 | ||
1892 | /* l4 per/ls -> gpio3 */ | |
a2cfc509 VH |
1893 | static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = { |
1894 | .master = &am33xx_l4_ls_hwmod, | |
1895 | .slave = &am33xx_gpio2_hwmod, | |
1896 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
1897 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1898 | }; | |
1899 | ||
1900 | /* l4 per/ls -> gpio4 */ | |
a2cfc509 VH |
1901 | static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = { |
1902 | .master = &am33xx_l4_ls_hwmod, | |
1903 | .slave = &am33xx_gpio3_hwmod, | |
1904 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
1905 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1906 | }; | |
1907 | ||
1908 | /* L4 WKUP -> I2C1 */ | |
a2cfc509 VH |
1909 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = { |
1910 | .master = &am33xx_l4_wkup_hwmod, | |
1911 | .slave = &am33xx_i2c1_hwmod, | |
1912 | .clk = "dpll_core_m4_div2_ck", | |
a2cfc509 VH |
1913 | .user = OCP_USER_MPU, |
1914 | }; | |
1915 | ||
1916 | /* L4 WKUP -> GPIO1 */ | |
a2cfc509 VH |
1917 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = { |
1918 | .master = &am33xx_l4_wkup_hwmod, | |
1919 | .slave = &am33xx_gpio0_hwmod, | |
1920 | .clk = "dpll_core_m4_div2_ck", | |
a2cfc509 VH |
1921 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1922 | }; | |
1923 | ||
1924 | /* L4 WKUP -> ADC_TSC */ | |
1925 | static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = { | |
1926 | { | |
1927 | .pa_start = 0x44E0D000, | |
1928 | .pa_end = 0x44E0D000 + SZ_8K - 1, | |
1929 | .flags = ADDR_TYPE_RT | |
1930 | }, | |
1931 | { } | |
1932 | }; | |
1933 | ||
1934 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = { | |
1935 | .master = &am33xx_l4_wkup_hwmod, | |
1936 | .slave = &am33xx_adc_tsc_hwmod, | |
1937 | .clk = "dpll_core_m4_div2_ck", | |
1938 | .addr = am33xx_adc_tsc_addrs, | |
1939 | .user = OCP_USER_MPU, | |
1940 | }; | |
1941 | ||
a2cfc509 VH |
1942 | static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = { |
1943 | .master = &am33xx_l4_hs_hwmod, | |
1944 | .slave = &am33xx_cpgmac0_hwmod, | |
1945 | .clk = "cpsw_125mhz_gclk", | |
a2cfc509 VH |
1946 | .user = OCP_USER_MPU, |
1947 | }; | |
1948 | ||
9816aa80 | 1949 | static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = { |
70384a6a M |
1950 | .master = &am33xx_cpgmac0_hwmod, |
1951 | .slave = &am33xx_mdio_hwmod, | |
70384a6a M |
1952 | .user = OCP_USER_MPU, |
1953 | }; | |
1954 | ||
a2cfc509 VH |
1955 | static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = { |
1956 | { | |
1957 | .pa_start = 0x48080000, | |
1958 | .pa_end = 0x48080000 + SZ_8K - 1, | |
1959 | .flags = ADDR_TYPE_RT | |
1960 | }, | |
1961 | { } | |
1962 | }; | |
1963 | ||
1964 | static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = { | |
1965 | .master = &am33xx_l4_ls_hwmod, | |
1966 | .slave = &am33xx_elm_hwmod, | |
1967 | .clk = "l4ls_gclk", | |
1968 | .addr = am33xx_elm_addr_space, | |
1969 | .user = OCP_USER_MPU, | |
1970 | }; | |
1971 | ||
9652d19a | 1972 | static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = { |
a2cfc509 VH |
1973 | { |
1974 | .pa_start = 0x48300000, | |
1975 | .pa_end = 0x48300000 + SZ_16 - 1, | |
1976 | .flags = ADDR_TYPE_RT | |
1977 | }, | |
a2cfc509 VH |
1978 | { } |
1979 | }; | |
1980 | ||
9652d19a | 1981 | static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = { |
a2cfc509 | 1982 | .master = &am33xx_l4_ls_hwmod, |
9652d19a | 1983 | .slave = &am33xx_epwmss0_hwmod, |
a2cfc509 | 1984 | .clk = "l4ls_gclk", |
9652d19a | 1985 | .addr = am33xx_epwmss0_addr_space, |
a2cfc509 VH |
1986 | .user = OCP_USER_MPU, |
1987 | }; | |
1988 | ||
9652d19a PA |
1989 | static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = { |
1990 | .master = &am33xx_epwmss0_hwmod, | |
1991 | .slave = &am33xx_ecap0_hwmod, | |
a2cfc509 | 1992 | .clk = "l4ls_gclk", |
a2cfc509 VH |
1993 | .user = OCP_USER_MPU, |
1994 | }; | |
1995 | ||
9652d19a PA |
1996 | static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = { |
1997 | .master = &am33xx_epwmss0_hwmod, | |
1998 | .slave = &am33xx_eqep0_hwmod, | |
1999 | .clk = "l4ls_gclk", | |
9652d19a PA |
2000 | .user = OCP_USER_MPU, |
2001 | }; | |
2002 | ||
9652d19a PA |
2003 | static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = { |
2004 | .master = &am33xx_epwmss0_hwmod, | |
2005 | .slave = &am33xx_ehrpwm0_hwmod, | |
a2cfc509 | 2006 | .clk = "l4ls_gclk", |
a2cfc509 VH |
2007 | .user = OCP_USER_MPU, |
2008 | }; | |
2009 | ||
9652d19a PA |
2010 | |
2011 | static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = { | |
bee76659 | 2012 | { |
9652d19a PA |
2013 | .pa_start = 0x48302000, |
2014 | .pa_end = 0x48302000 + SZ_16 - 1, | |
bee76659 PA |
2015 | .flags = ADDR_TYPE_RT |
2016 | }, | |
bee76659 PA |
2017 | { } |
2018 | }; | |
2019 | ||
9652d19a | 2020 | static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = { |
bee76659 | 2021 | .master = &am33xx_l4_ls_hwmod, |
9652d19a | 2022 | .slave = &am33xx_epwmss1_hwmod, |
bee76659 | 2023 | .clk = "l4ls_gclk", |
9652d19a | 2024 | .addr = am33xx_epwmss1_addr_space, |
bee76659 PA |
2025 | .user = OCP_USER_MPU, |
2026 | }; | |
2027 | ||
9652d19a PA |
2028 | static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = { |
2029 | .master = &am33xx_epwmss1_hwmod, | |
2030 | .slave = &am33xx_ecap1_hwmod, | |
2031 | .clk = "l4ls_gclk", | |
9652d19a PA |
2032 | .user = OCP_USER_MPU, |
2033 | }; | |
2034 | ||
9652d19a PA |
2035 | static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = { |
2036 | .master = &am33xx_epwmss1_hwmod, | |
bee76659 PA |
2037 | .slave = &am33xx_eqep1_hwmod, |
2038 | .clk = "l4ls_gclk", | |
bee76659 PA |
2039 | .user = OCP_USER_MPU, |
2040 | }; | |
2041 | ||
9652d19a PA |
2042 | static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = { |
2043 | .master = &am33xx_epwmss1_hwmod, | |
2044 | .slave = &am33xx_ehrpwm1_hwmod, | |
bee76659 | 2045 | .clk = "l4ls_gclk", |
bee76659 PA |
2046 | .user = OCP_USER_MPU, |
2047 | }; | |
2048 | ||
9652d19a | 2049 | static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = { |
a2cfc509 | 2050 | { |
9652d19a PA |
2051 | .pa_start = 0x48304000, |
2052 | .pa_end = 0x48304000 + SZ_16 - 1, | |
a2cfc509 VH |
2053 | .flags = ADDR_TYPE_RT |
2054 | }, | |
a2cfc509 VH |
2055 | { } |
2056 | }; | |
2057 | ||
9652d19a | 2058 | static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = { |
a2cfc509 | 2059 | .master = &am33xx_l4_ls_hwmod, |
9652d19a | 2060 | .slave = &am33xx_epwmss2_hwmod, |
a2cfc509 | 2061 | .clk = "l4ls_gclk", |
9652d19a | 2062 | .addr = am33xx_epwmss2_addr_space, |
a2cfc509 VH |
2063 | .user = OCP_USER_MPU, |
2064 | }; | |
2065 | ||
9652d19a PA |
2066 | static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = { |
2067 | .master = &am33xx_epwmss2_hwmod, | |
2068 | .slave = &am33xx_ecap2_hwmod, | |
a2cfc509 | 2069 | .clk = "l4ls_gclk", |
a2cfc509 VH |
2070 | .user = OCP_USER_MPU, |
2071 | }; | |
2072 | ||
9652d19a PA |
2073 | static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = { |
2074 | .master = &am33xx_epwmss2_hwmod, | |
2075 | .slave = &am33xx_eqep2_hwmod, | |
2076 | .clk = "l4ls_gclk", | |
9652d19a PA |
2077 | .user = OCP_USER_MPU, |
2078 | }; | |
2079 | ||
9652d19a PA |
2080 | static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = { |
2081 | .master = &am33xx_epwmss2_hwmod, | |
2082 | .slave = &am33xx_ehrpwm2_hwmod, | |
a2cfc509 | 2083 | .clk = "l4ls_gclk", |
a2cfc509 VH |
2084 | .user = OCP_USER_MPU, |
2085 | }; | |
2086 | ||
2087 | /* l3s cfg -> gpmc */ | |
2088 | static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = { | |
2089 | { | |
2090 | .pa_start = 0x50000000, | |
2091 | .pa_end = 0x50000000 + SZ_8K - 1, | |
2092 | .flags = ADDR_TYPE_RT, | |
2093 | }, | |
2094 | { } | |
2095 | }; | |
2096 | ||
2097 | static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { | |
2098 | .master = &am33xx_l3_s_hwmod, | |
2099 | .slave = &am33xx_gpmc_hwmod, | |
2100 | .clk = "l3s_gclk", | |
2101 | .addr = am33xx_gpmc_addr_space, | |
2102 | .user = OCP_USER_MPU, | |
2103 | }; | |
2104 | ||
2105 | /* i2c2 */ | |
a2cfc509 VH |
2106 | static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = { |
2107 | .master = &am33xx_l4_ls_hwmod, | |
2108 | .slave = &am33xx_i2c2_hwmod, | |
2109 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2110 | .user = OCP_USER_MPU, |
2111 | }; | |
2112 | ||
a2cfc509 VH |
2113 | static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = { |
2114 | .master = &am33xx_l4_ls_hwmod, | |
2115 | .slave = &am33xx_i2c3_hwmod, | |
2116 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2117 | .user = OCP_USER_MPU, |
2118 | }; | |
2119 | ||
2120 | static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = { | |
2121 | { | |
2122 | .pa_start = 0x4830E000, | |
2123 | .pa_end = 0x4830E000 + SZ_8K - 1, | |
2124 | .flags = ADDR_TYPE_RT, | |
2125 | }, | |
2126 | { } | |
2127 | }; | |
2128 | ||
2129 | static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = { | |
2130 | .master = &am33xx_l3_main_hwmod, | |
2131 | .slave = &am33xx_lcdc_hwmod, | |
2132 | .clk = "dpll_core_m4_ck", | |
2133 | .addr = am33xx_lcdc_addr_space, | |
2134 | .user = OCP_USER_MPU, | |
2135 | }; | |
2136 | ||
2137 | static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = { | |
2138 | { | |
2139 | .pa_start = 0x480C8000, | |
2140 | .pa_end = 0x480C8000 + (SZ_4K - 1), | |
2141 | .flags = ADDR_TYPE_RT | |
2142 | }, | |
2143 | { } | |
2144 | }; | |
2145 | ||
2146 | /* l4 ls -> mailbox */ | |
2147 | static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = { | |
2148 | .master = &am33xx_l4_ls_hwmod, | |
2149 | .slave = &am33xx_mailbox_hwmod, | |
2150 | .clk = "l4ls_gclk", | |
2151 | .addr = am33xx_mailbox_addrs, | |
2152 | .user = OCP_USER_MPU, | |
2153 | }; | |
2154 | ||
2155 | /* l4 ls -> spinlock */ | |
a2cfc509 VH |
2156 | static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = { |
2157 | .master = &am33xx_l4_ls_hwmod, | |
2158 | .slave = &am33xx_spinlock_hwmod, | |
2159 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2160 | .user = OCP_USER_MPU, |
2161 | }; | |
2162 | ||
2163 | /* l4 ls -> mcasp0 */ | |
2164 | static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = { | |
2165 | { | |
2166 | .pa_start = 0x48038000, | |
2167 | .pa_end = 0x48038000 + SZ_8K - 1, | |
2168 | .flags = ADDR_TYPE_RT | |
2169 | }, | |
2170 | { } | |
2171 | }; | |
2172 | ||
2173 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = { | |
2174 | .master = &am33xx_l4_ls_hwmod, | |
2175 | .slave = &am33xx_mcasp0_hwmod, | |
2176 | .clk = "l4ls_gclk", | |
2177 | .addr = am33xx_mcasp0_addr_space, | |
2178 | .user = OCP_USER_MPU, | |
2179 | }; | |
2180 | ||
a2cfc509 VH |
2181 | /* l4 ls -> mcasp1 */ |
2182 | static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = { | |
2183 | { | |
2184 | .pa_start = 0x4803C000, | |
2185 | .pa_end = 0x4803C000 + SZ_8K - 1, | |
2186 | .flags = ADDR_TYPE_RT | |
2187 | }, | |
2188 | { } | |
2189 | }; | |
2190 | ||
2191 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = { | |
2192 | .master = &am33xx_l4_ls_hwmod, | |
2193 | .slave = &am33xx_mcasp1_hwmod, | |
2194 | .clk = "l4ls_gclk", | |
2195 | .addr = am33xx_mcasp1_addr_space, | |
2196 | .user = OCP_USER_MPU, | |
2197 | }; | |
2198 | ||
a2cfc509 VH |
2199 | /* l4 ls -> mmc0 */ |
2200 | static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = { | |
2201 | { | |
2202 | .pa_start = 0x48060100, | |
2203 | .pa_end = 0x48060100 + SZ_4K - 1, | |
2204 | .flags = ADDR_TYPE_RT, | |
2205 | }, | |
2206 | { } | |
2207 | }; | |
2208 | ||
2209 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = { | |
2210 | .master = &am33xx_l4_ls_hwmod, | |
2211 | .slave = &am33xx_mmc0_hwmod, | |
2212 | .clk = "l4ls_gclk", | |
2213 | .addr = am33xx_mmc0_addr_space, | |
2214 | .user = OCP_USER_MPU, | |
2215 | }; | |
2216 | ||
2217 | /* l4 ls -> mmc1 */ | |
2218 | static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = { | |
2219 | { | |
2220 | .pa_start = 0x481d8100, | |
2221 | .pa_end = 0x481d8100 + SZ_4K - 1, | |
2222 | .flags = ADDR_TYPE_RT, | |
2223 | }, | |
2224 | { } | |
2225 | }; | |
2226 | ||
2227 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = { | |
2228 | .master = &am33xx_l4_ls_hwmod, | |
2229 | .slave = &am33xx_mmc1_hwmod, | |
2230 | .clk = "l4ls_gclk", | |
2231 | .addr = am33xx_mmc1_addr_space, | |
2232 | .user = OCP_USER_MPU, | |
2233 | }; | |
2234 | ||
2235 | /* l3 s -> mmc2 */ | |
2236 | static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = { | |
2237 | { | |
2238 | .pa_start = 0x47810100, | |
2239 | .pa_end = 0x47810100 + SZ_64K - 1, | |
2240 | .flags = ADDR_TYPE_RT, | |
2241 | }, | |
2242 | { } | |
2243 | }; | |
2244 | ||
2245 | static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = { | |
2246 | .master = &am33xx_l3_s_hwmod, | |
2247 | .slave = &am33xx_mmc2_hwmod, | |
2248 | .clk = "l3s_gclk", | |
2249 | .addr = am33xx_mmc2_addr_space, | |
2250 | .user = OCP_USER_MPU, | |
2251 | }; | |
2252 | ||
2253 | /* l4 ls -> mcspi0 */ | |
a2cfc509 VH |
2254 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = { |
2255 | .master = &am33xx_l4_ls_hwmod, | |
2256 | .slave = &am33xx_spi0_hwmod, | |
2257 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2258 | .user = OCP_USER_MPU, |
2259 | }; | |
2260 | ||
2261 | /* l4 ls -> mcspi1 */ | |
a2cfc509 VH |
2262 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = { |
2263 | .master = &am33xx_l4_ls_hwmod, | |
2264 | .slave = &am33xx_spi1_hwmod, | |
2265 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2266 | .user = OCP_USER_MPU, |
2267 | }; | |
2268 | ||
2269 | /* l4 wkup -> timer1 */ | |
a2cfc509 VH |
2270 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = { |
2271 | .master = &am33xx_l4_wkup_hwmod, | |
2272 | .slave = &am33xx_timer1_hwmod, | |
2273 | .clk = "dpll_core_m4_div2_ck", | |
a2cfc509 VH |
2274 | .user = OCP_USER_MPU, |
2275 | }; | |
2276 | ||
2277 | /* l4 per -> timer2 */ | |
a2cfc509 VH |
2278 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { |
2279 | .master = &am33xx_l4_ls_hwmod, | |
2280 | .slave = &am33xx_timer2_hwmod, | |
2281 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2282 | .user = OCP_USER_MPU, |
2283 | }; | |
2284 | ||
2285 | /* l4 per -> timer3 */ | |
a2cfc509 VH |
2286 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = { |
2287 | .master = &am33xx_l4_ls_hwmod, | |
2288 | .slave = &am33xx_timer3_hwmod, | |
2289 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2290 | .user = OCP_USER_MPU, |
2291 | }; | |
2292 | ||
2293 | /* l4 per -> timer4 */ | |
a2cfc509 VH |
2294 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = { |
2295 | .master = &am33xx_l4_ls_hwmod, | |
2296 | .slave = &am33xx_timer4_hwmod, | |
2297 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2298 | .user = OCP_USER_MPU, |
2299 | }; | |
2300 | ||
2301 | /* l4 per -> timer5 */ | |
a2cfc509 VH |
2302 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = { |
2303 | .master = &am33xx_l4_ls_hwmod, | |
2304 | .slave = &am33xx_timer5_hwmod, | |
2305 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2306 | .user = OCP_USER_MPU, |
2307 | }; | |
2308 | ||
2309 | /* l4 per -> timer6 */ | |
a2cfc509 VH |
2310 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = { |
2311 | .master = &am33xx_l4_ls_hwmod, | |
2312 | .slave = &am33xx_timer6_hwmod, | |
2313 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2314 | .user = OCP_USER_MPU, |
2315 | }; | |
2316 | ||
2317 | /* l4 per -> timer7 */ | |
a2cfc509 VH |
2318 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = { |
2319 | .master = &am33xx_l4_ls_hwmod, | |
2320 | .slave = &am33xx_timer7_hwmod, | |
2321 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2322 | .user = OCP_USER_MPU, |
2323 | }; | |
2324 | ||
2325 | /* l3 main -> tpcc */ | |
a2cfc509 VH |
2326 | static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = { |
2327 | .master = &am33xx_l3_main_hwmod, | |
2328 | .slave = &am33xx_tpcc_hwmod, | |
2329 | .clk = "l3_gclk", | |
a2cfc509 VH |
2330 | .user = OCP_USER_MPU, |
2331 | }; | |
2332 | ||
2333 | /* l3 main -> tpcc0 */ | |
2334 | static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = { | |
2335 | { | |
2336 | .pa_start = 0x49800000, | |
2337 | .pa_end = 0x49800000 + SZ_8K - 1, | |
2338 | .flags = ADDR_TYPE_RT, | |
2339 | }, | |
2340 | { } | |
2341 | }; | |
2342 | ||
2343 | static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = { | |
2344 | .master = &am33xx_l3_main_hwmod, | |
2345 | .slave = &am33xx_tptc0_hwmod, | |
2346 | .clk = "l3_gclk", | |
2347 | .addr = am33xx_tptc0_addr_space, | |
2348 | .user = OCP_USER_MPU, | |
2349 | }; | |
2350 | ||
2351 | /* l3 main -> tpcc1 */ | |
2352 | static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = { | |
2353 | { | |
2354 | .pa_start = 0x49900000, | |
2355 | .pa_end = 0x49900000 + SZ_8K - 1, | |
2356 | .flags = ADDR_TYPE_RT, | |
2357 | }, | |
2358 | { } | |
2359 | }; | |
2360 | ||
2361 | static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = { | |
2362 | .master = &am33xx_l3_main_hwmod, | |
2363 | .slave = &am33xx_tptc1_hwmod, | |
2364 | .clk = "l3_gclk", | |
2365 | .addr = am33xx_tptc1_addr_space, | |
2366 | .user = OCP_USER_MPU, | |
2367 | }; | |
2368 | ||
2369 | /* l3 main -> tpcc2 */ | |
2370 | static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = { | |
2371 | { | |
2372 | .pa_start = 0x49a00000, | |
2373 | .pa_end = 0x49a00000 + SZ_8K - 1, | |
2374 | .flags = ADDR_TYPE_RT, | |
2375 | }, | |
2376 | { } | |
2377 | }; | |
2378 | ||
2379 | static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = { | |
2380 | .master = &am33xx_l3_main_hwmod, | |
2381 | .slave = &am33xx_tptc2_hwmod, | |
2382 | .clk = "l3_gclk", | |
2383 | .addr = am33xx_tptc2_addr_space, | |
2384 | .user = OCP_USER_MPU, | |
2385 | }; | |
2386 | ||
2387 | /* l4 wkup -> uart1 */ | |
a2cfc509 VH |
2388 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = { |
2389 | .master = &am33xx_l4_wkup_hwmod, | |
2390 | .slave = &am33xx_uart1_hwmod, | |
2391 | .clk = "dpll_core_m4_div2_ck", | |
a2cfc509 VH |
2392 | .user = OCP_USER_MPU, |
2393 | }; | |
2394 | ||
2395 | /* l4 ls -> uart2 */ | |
a2cfc509 VH |
2396 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = { |
2397 | .master = &am33xx_l4_ls_hwmod, | |
2398 | .slave = &am33xx_uart2_hwmod, | |
2399 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2400 | .user = OCP_USER_MPU, |
2401 | }; | |
2402 | ||
2403 | /* l4 ls -> uart3 */ | |
a2cfc509 VH |
2404 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = { |
2405 | .master = &am33xx_l4_ls_hwmod, | |
2406 | .slave = &am33xx_uart3_hwmod, | |
2407 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2408 | .user = OCP_USER_MPU, |
2409 | }; | |
2410 | ||
2411 | /* l4 ls -> uart4 */ | |
a2cfc509 VH |
2412 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = { |
2413 | .master = &am33xx_l4_ls_hwmod, | |
2414 | .slave = &am33xx_uart4_hwmod, | |
2415 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2416 | .user = OCP_USER_MPU, |
2417 | }; | |
2418 | ||
2419 | /* l4 ls -> uart5 */ | |
a2cfc509 VH |
2420 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = { |
2421 | .master = &am33xx_l4_ls_hwmod, | |
2422 | .slave = &am33xx_uart5_hwmod, | |
2423 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2424 | .user = OCP_USER_MPU, |
2425 | }; | |
2426 | ||
2427 | /* l4 ls -> uart6 */ | |
a2cfc509 VH |
2428 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = { |
2429 | .master = &am33xx_l4_ls_hwmod, | |
2430 | .slave = &am33xx_uart6_hwmod, | |
2431 | .clk = "l4ls_gclk", | |
a2cfc509 VH |
2432 | .user = OCP_USER_MPU, |
2433 | }; | |
2434 | ||
2435 | /* l4 wkup -> wd_timer1 */ | |
a2cfc509 VH |
2436 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = { |
2437 | .master = &am33xx_l4_wkup_hwmod, | |
2438 | .slave = &am33xx_wd_timer1_hwmod, | |
2439 | .clk = "dpll_core_m4_div2_ck", | |
a2cfc509 VH |
2440 | .user = OCP_USER_MPU, |
2441 | }; | |
2442 | ||
2443 | /* usbss */ | |
2444 | /* l3 s -> USBSS interface */ | |
a2cfc509 VH |
2445 | static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = { |
2446 | .master = &am33xx_l3_s_hwmod, | |
2447 | .slave = &am33xx_usbss_hwmod, | |
2448 | .clk = "l3s_gclk", | |
a2cfc509 VH |
2449 | .user = OCP_USER_MPU, |
2450 | .flags = OCPIF_SWSUP_IDLE, | |
2451 | }; | |
2452 | ||
ca903b6f VB |
2453 | /* l3 main -> ocmc */ |
2454 | static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = { | |
2455 | .master = &am33xx_l3_main_hwmod, | |
2456 | .slave = &am33xx_ocmcram_hwmod, | |
2457 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2458 | }; | |
2459 | ||
aec94bf5 MG |
2460 | /* l3 main -> sha0 HIB2 */ |
2461 | static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = { | |
2462 | { | |
2463 | .pa_start = 0x53100000, | |
2464 | .pa_end = 0x53100000 + SZ_512 - 1, | |
2465 | .flags = ADDR_TYPE_RT | |
2466 | }, | |
2467 | { } | |
2468 | }; | |
2469 | ||
2470 | static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = { | |
2471 | .master = &am33xx_l3_main_hwmod, | |
2472 | .slave = &am33xx_sha0_hwmod, | |
2473 | .clk = "sha0_fck", | |
2474 | .addr = am33xx_sha0_addrs, | |
2475 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2476 | }; | |
2477 | ||
1cb804b9 MG |
2478 | /* l3 main -> AES0 HIB2 */ |
2479 | static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = { | |
2480 | { | |
2481 | .pa_start = 0x53500000, | |
2482 | .pa_end = 0x53500000 + SZ_1M - 1, | |
2483 | .flags = ADDR_TYPE_RT | |
2484 | }, | |
2485 | { } | |
2486 | }; | |
2487 | ||
2488 | static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = { | |
2489 | .master = &am33xx_l3_main_hwmod, | |
2490 | .slave = &am33xx_aes0_hwmod, | |
2491 | .clk = "aes0_fck", | |
2492 | .addr = am33xx_aes0_addrs, | |
2493 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2494 | }; | |
2495 | ||
a2cfc509 | 2496 | static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { |
a2cfc509 VH |
2497 | &am33xx_l3_main__emif, |
2498 | &am33xx_mpu__l3_main, | |
2499 | &am33xx_mpu__prcm, | |
2500 | &am33xx_l3_s__l4_ls, | |
2501 | &am33xx_l3_s__l4_wkup, | |
a2cfc509 VH |
2502 | &am33xx_l3_main__l4_hs, |
2503 | &am33xx_l3_main__l3_s, | |
2504 | &am33xx_l3_main__l3_instr, | |
2505 | &am33xx_l3_main__gfx, | |
2506 | &am33xx_l3_s__l3_main, | |
2507 | &am33xx_pruss__l3_main, | |
2508 | &am33xx_wkup_m3__l4_wkup, | |
2509 | &am33xx_gfx__l3_main, | |
1721c702 | 2510 | &am33xx_l3_main__debugss, |
a2cfc509 VH |
2511 | &am33xx_l4_wkup__wkup_m3, |
2512 | &am33xx_l4_wkup__control, | |
2513 | &am33xx_l4_wkup__smartreflex0, | |
2514 | &am33xx_l4_wkup__smartreflex1, | |
2515 | &am33xx_l4_wkup__uart1, | |
2516 | &am33xx_l4_wkup__timer1, | |
2517 | &am33xx_l4_wkup__rtc, | |
2518 | &am33xx_l4_wkup__i2c1, | |
2519 | &am33xx_l4_wkup__gpio0, | |
2520 | &am33xx_l4_wkup__adc_tsc, | |
2521 | &am33xx_l4_wkup__wd_timer1, | |
2522 | &am33xx_l4_hs__pruss, | |
2523 | &am33xx_l4_per__dcan0, | |
2524 | &am33xx_l4_per__dcan1, | |
2525 | &am33xx_l4_per__gpio1, | |
2526 | &am33xx_l4_per__gpio2, | |
2527 | &am33xx_l4_per__gpio3, | |
2528 | &am33xx_l4_per__i2c2, | |
2529 | &am33xx_l4_per__i2c3, | |
2530 | &am33xx_l4_per__mailbox, | |
2531 | &am33xx_l4_ls__mcasp0, | |
a2cfc509 | 2532 | &am33xx_l4_ls__mcasp1, |
a2cfc509 VH |
2533 | &am33xx_l4_ls__mmc0, |
2534 | &am33xx_l4_ls__mmc1, | |
2535 | &am33xx_l3_s__mmc2, | |
2536 | &am33xx_l4_ls__timer2, | |
2537 | &am33xx_l4_ls__timer3, | |
2538 | &am33xx_l4_ls__timer4, | |
2539 | &am33xx_l4_ls__timer5, | |
2540 | &am33xx_l4_ls__timer6, | |
2541 | &am33xx_l4_ls__timer7, | |
2542 | &am33xx_l3_main__tpcc, | |
2543 | &am33xx_l4_ls__uart2, | |
2544 | &am33xx_l4_ls__uart3, | |
2545 | &am33xx_l4_ls__uart4, | |
2546 | &am33xx_l4_ls__uart5, | |
2547 | &am33xx_l4_ls__uart6, | |
2548 | &am33xx_l4_ls__spinlock, | |
2549 | &am33xx_l4_ls__elm, | |
9652d19a PA |
2550 | &am33xx_l4_ls__epwmss0, |
2551 | &am33xx_epwmss0__ecap0, | |
2552 | &am33xx_epwmss0__eqep0, | |
2553 | &am33xx_epwmss0__ehrpwm0, | |
2554 | &am33xx_l4_ls__epwmss1, | |
2555 | &am33xx_epwmss1__ecap1, | |
2556 | &am33xx_epwmss1__eqep1, | |
2557 | &am33xx_epwmss1__ehrpwm1, | |
2558 | &am33xx_l4_ls__epwmss2, | |
2559 | &am33xx_epwmss2__ecap2, | |
2560 | &am33xx_epwmss2__eqep2, | |
2561 | &am33xx_epwmss2__ehrpwm2, | |
a2cfc509 VH |
2562 | &am33xx_l3_s__gpmc, |
2563 | &am33xx_l3_main__lcdc, | |
2564 | &am33xx_l4_ls__mcspi0, | |
2565 | &am33xx_l4_ls__mcspi1, | |
2566 | &am33xx_l3_main__tptc0, | |
2567 | &am33xx_l3_main__tptc1, | |
2568 | &am33xx_l3_main__tptc2, | |
ca903b6f | 2569 | &am33xx_l3_main__ocmc, |
a2cfc509 VH |
2570 | &am33xx_l3_s__usbss, |
2571 | &am33xx_l4_hs__cpgmac0, | |
70384a6a | 2572 | &am33xx_cpgmac0__mdio, |
aec94bf5 | 2573 | &am33xx_l3_main__sha0, |
1cb804b9 | 2574 | &am33xx_l3_main__aes0, |
a2cfc509 VH |
2575 | NULL, |
2576 | }; | |
2577 | ||
2578 | int __init am33xx_hwmod_init(void) | |
2579 | { | |
2580 | omap_hwmod_init(); | |
2581 | return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs); | |
2582 | } |