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7359154e PW |
1 | /* |
2 | * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips | |
3 | * | |
78183f3f | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
0a78c5c5 | 5 | * Copyright (C) 2012 Texas Instruments, Inc. |
7359154e PW |
6 | * Paul Walmsley |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * The data in this file should be completely autogeneratable from | |
13 | * the TI hardware database or other technical documentation. | |
14 | * | |
15 | * XXX these should be marked initdata for multi-OMAP kernels | |
16 | */ | |
17 | #include <plat/omap_hwmod.h> | |
18 | #include <mach/irqs.h> | |
19 | #include <plat/cpu.h> | |
20 | #include <plat/dma.h> | |
046465b7 | 21 | #include <plat/serial.h> |
e04d9e1e | 22 | #include <plat/l3_3xxx.h> |
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23 | #include <plat/l4_3xxx.h> |
24 | #include <plat/i2c.h> | |
70034d38 | 25 | #include <plat/gpio.h> |
6ab8946f | 26 | #include <plat/mmc.h> |
dc48e5fc | 27 | #include <plat/mcbsp.h> |
0f616a4e | 28 | #include <plat/mcspi.h> |
ce722d26 | 29 | #include <plat/dmtimer.h> |
7359154e | 30 | |
43b40992 PW |
31 | #include "omap_hwmod_common_data.h" |
32 | ||
cea6b942 | 33 | #include "smartreflex.h" |
7359154e | 34 | #include "prm-regbits-34xx.h" |
6b667f88 | 35 | #include "cm-regbits-34xx.h" |
ff2516fb | 36 | #include "wd_timer.h" |
273ff8c3 | 37 | #include <mach/am35xx.h> |
7359154e PW |
38 | |
39 | /* | |
40 | * OMAP3xxx hardware module integration data | |
41 | * | |
844a3b63 | 42 | * All of the data in this section should be autogeneratable from the |
7359154e PW |
43 | * TI hardware database or other technical documentation. Data that |
44 | * is driver-specific or driver-kernel integration-specific belongs | |
45 | * elsewhere. | |
46 | */ | |
47 | ||
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48 | /* |
49 | * IP blocks | |
50 | */ | |
7359154e | 51 | |
844a3b63 | 52 | /* L3 */ |
4bb194dc | 53 | static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { |
54 | { .irq = INT_34XX_L3_DBG_IRQ }, | |
55 | { .irq = INT_34XX_L3_APP_IRQ }, | |
212738a4 | 56 | { .irq = -1 } |
4bb194dc | 57 | }; |
58 | ||
4a7cf90a | 59 | static struct omap_hwmod omap3xxx_l3_main_hwmod = { |
fa98347e | 60 | .name = "l3_main", |
43b40992 | 61 | .class = &l3_hwmod_class, |
0d619a89 | 62 | .mpu_irqs = omap3xxx_l3_main_irqs, |
2eb1875d | 63 | .flags = HWMOD_NO_IDLEST, |
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64 | }; |
65 | ||
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66 | /* L4 CORE */ |
67 | static struct omap_hwmod omap3xxx_l4_core_hwmod = { | |
68 | .name = "l4_core", | |
69 | .class = &l4_hwmod_class, | |
70 | .flags = HWMOD_NO_IDLEST, | |
870ea2b8 | 71 | }; |
7359154e | 72 | |
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73 | /* L4 PER */ |
74 | static struct omap_hwmod omap3xxx_l4_per_hwmod = { | |
75 | .name = "l4_per", | |
76 | .class = &l4_hwmod_class, | |
77 | .flags = HWMOD_NO_IDLEST, | |
273ff8c3 | 78 | }; |
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79 | |
80 | /* L4 WKUP */ | |
81 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { | |
82 | .name = "l4_wkup", | |
83 | .class = &l4_hwmod_class, | |
84 | .flags = HWMOD_NO_IDLEST, | |
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85 | }; |
86 | ||
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87 | /* L4 SEC */ |
88 | static struct omap_hwmod omap3xxx_l4_sec_hwmod = { | |
89 | .name = "l4_sec", | |
90 | .class = &l4_hwmod_class, | |
91 | .flags = HWMOD_NO_IDLEST, | |
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92 | }; |
93 | ||
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94 | /* MPU */ |
95 | static struct omap_hwmod omap3xxx_mpu_hwmod = { | |
96 | .name = "mpu", | |
97 | .class = &mpu_hwmod_class, | |
98 | .main_clk = "arm_fck", | |
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99 | }; |
100 | ||
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101 | /* IVA2 (IVA2) */ |
102 | static struct omap_hwmod omap3xxx_iva_hwmod = { | |
103 | .name = "iva", | |
104 | .class = &iva_hwmod_class, | |
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105 | }; |
106 | ||
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107 | /* timer class */ |
108 | static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = { | |
109 | .rev_offs = 0x0000, | |
110 | .sysc_offs = 0x0010, | |
111 | .syss_offs = 0x0014, | |
112 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
113 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
114 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), | |
115 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
116 | .sysc_fields = &omap_hwmod_sysc_type1, | |
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117 | }; |
118 | ||
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119 | static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = { |
120 | .name = "timer", | |
121 | .sysc = &omap3xxx_timer_1ms_sysc, | |
122 | .rev = OMAP_TIMER_IP_VERSION_1, | |
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123 | }; |
124 | ||
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125 | static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { |
126 | .rev_offs = 0x0000, | |
127 | .sysc_offs = 0x0010, | |
128 | .syss_offs = 0x0014, | |
129 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
130 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
131 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
132 | .sysc_fields = &omap_hwmod_sysc_type1, | |
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133 | }; |
134 | ||
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135 | static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { |
136 | .name = "timer", | |
137 | .sysc = &omap3xxx_timer_sysc, | |
138 | .rev = OMAP_TIMER_IP_VERSION_1, | |
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139 | }; |
140 | ||
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141 | /* secure timers dev attribute */ |
142 | static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { | |
143 | .timer_capability = OMAP_TIMER_SECURE, | |
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144 | }; |
145 | ||
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146 | /* always-on timers dev attribute */ |
147 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
148 | .timer_capability = OMAP_TIMER_ALWON, | |
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149 | }; |
150 | ||
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151 | /* pwm timers dev attribute */ |
152 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
153 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
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154 | }; |
155 | ||
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156 | /* timer1 */ |
157 | static struct omap_hwmod omap3xxx_timer1_hwmod = { | |
158 | .name = "timer1", | |
159 | .mpu_irqs = omap2_timer1_mpu_irqs, | |
160 | .main_clk = "gpt1_fck", | |
161 | .prcm = { | |
162 | .omap2 = { | |
163 | .prcm_reg_id = 1, | |
164 | .module_bit = OMAP3430_EN_GPT1_SHIFT, | |
165 | .module_offs = WKUP_MOD, | |
166 | .idlest_reg_id = 1, | |
167 | .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, | |
168 | }, | |
046465b7 | 169 | }, |
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170 | .dev_attr = &capability_alwon_dev_attr, |
171 | .class = &omap3xxx_timer_1ms_hwmod_class, | |
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172 | }; |
173 | ||
844a3b63 PW |
174 | /* timer2 */ |
175 | static struct omap_hwmod omap3xxx_timer2_hwmod = { | |
176 | .name = "timer2", | |
177 | .mpu_irqs = omap2_timer2_mpu_irqs, | |
178 | .main_clk = "gpt2_fck", | |
179 | .prcm = { | |
180 | .omap2 = { | |
181 | .prcm_reg_id = 1, | |
182 | .module_bit = OMAP3430_EN_GPT2_SHIFT, | |
183 | .module_offs = OMAP3430_PER_MOD, | |
184 | .idlest_reg_id = 1, | |
185 | .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, | |
186 | }, | |
187 | }, | |
188 | .dev_attr = &capability_alwon_dev_attr, | |
189 | .class = &omap3xxx_timer_1ms_hwmod_class, | |
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190 | }; |
191 | ||
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192 | /* timer3 */ |
193 | static struct omap_hwmod omap3xxx_timer3_hwmod = { | |
194 | .name = "timer3", | |
195 | .mpu_irqs = omap2_timer3_mpu_irqs, | |
196 | .main_clk = "gpt3_fck", | |
197 | .prcm = { | |
198 | .omap2 = { | |
199 | .prcm_reg_id = 1, | |
200 | .module_bit = OMAP3430_EN_GPT3_SHIFT, | |
201 | .module_offs = OMAP3430_PER_MOD, | |
202 | .idlest_reg_id = 1, | |
203 | .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, | |
204 | }, | |
205 | }, | |
206 | .dev_attr = &capability_alwon_dev_attr, | |
207 | .class = &omap3xxx_timer_hwmod_class, | |
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208 | }; |
209 | ||
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210 | /* timer4 */ |
211 | static struct omap_hwmod omap3xxx_timer4_hwmod = { | |
212 | .name = "timer4", | |
213 | .mpu_irqs = omap2_timer4_mpu_irqs, | |
214 | .main_clk = "gpt4_fck", | |
215 | .prcm = { | |
216 | .omap2 = { | |
217 | .prcm_reg_id = 1, | |
218 | .module_bit = OMAP3430_EN_GPT4_SHIFT, | |
219 | .module_offs = OMAP3430_PER_MOD, | |
220 | .idlest_reg_id = 1, | |
221 | .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, | |
222 | }, | |
223 | }, | |
224 | .dev_attr = &capability_alwon_dev_attr, | |
225 | .class = &omap3xxx_timer_hwmod_class, | |
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226 | }; |
227 | ||
844a3b63 PW |
228 | /* timer5 */ |
229 | static struct omap_hwmod omap3xxx_timer5_hwmod = { | |
230 | .name = "timer5", | |
231 | .mpu_irqs = omap2_timer5_mpu_irqs, | |
232 | .main_clk = "gpt5_fck", | |
233 | .prcm = { | |
234 | .omap2 = { | |
235 | .prcm_reg_id = 1, | |
236 | .module_bit = OMAP3430_EN_GPT5_SHIFT, | |
237 | .module_offs = OMAP3430_PER_MOD, | |
238 | .idlest_reg_id = 1, | |
239 | .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, | |
240 | }, | |
4bf90f65 | 241 | }, |
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242 | .dev_attr = &capability_alwon_dev_attr, |
243 | .class = &omap3xxx_timer_hwmod_class, | |
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244 | }; |
245 | ||
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246 | /* timer6 */ |
247 | static struct omap_hwmod omap3xxx_timer6_hwmod = { | |
248 | .name = "timer6", | |
249 | .mpu_irqs = omap2_timer6_mpu_irqs, | |
250 | .main_clk = "gpt6_fck", | |
251 | .prcm = { | |
252 | .omap2 = { | |
253 | .prcm_reg_id = 1, | |
254 | .module_bit = OMAP3430_EN_GPT6_SHIFT, | |
255 | .module_offs = OMAP3430_PER_MOD, | |
256 | .idlest_reg_id = 1, | |
257 | .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, | |
258 | }, | |
259 | }, | |
260 | .dev_attr = &capability_alwon_dev_attr, | |
261 | .class = &omap3xxx_timer_hwmod_class, | |
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262 | }; |
263 | ||
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264 | /* timer7 */ |
265 | static struct omap_hwmod omap3xxx_timer7_hwmod = { | |
266 | .name = "timer7", | |
267 | .mpu_irqs = omap2_timer7_mpu_irqs, | |
268 | .main_clk = "gpt7_fck", | |
269 | .prcm = { | |
4fe20e97 | 270 | .omap2 = { |
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271 | .prcm_reg_id = 1, |
272 | .module_bit = OMAP3430_EN_GPT7_SHIFT, | |
273 | .module_offs = OMAP3430_PER_MOD, | |
274 | .idlest_reg_id = 1, | |
275 | .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, | |
276 | }, | |
4fe20e97 | 277 | }, |
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278 | .dev_attr = &capability_alwon_dev_attr, |
279 | .class = &omap3xxx_timer_hwmod_class, | |
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280 | }; |
281 | ||
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282 | /* timer8 */ |
283 | static struct omap_hwmod omap3xxx_timer8_hwmod = { | |
284 | .name = "timer8", | |
285 | .mpu_irqs = omap2_timer8_mpu_irqs, | |
286 | .main_clk = "gpt8_fck", | |
287 | .prcm = { | |
4fe20e97 | 288 | .omap2 = { |
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289 | .prcm_reg_id = 1, |
290 | .module_bit = OMAP3430_EN_GPT8_SHIFT, | |
291 | .module_offs = OMAP3430_PER_MOD, | |
292 | .idlest_reg_id = 1, | |
293 | .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, | |
294 | }, | |
4fe20e97 | 295 | }, |
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296 | .dev_attr = &capability_pwm_dev_attr, |
297 | .class = &omap3xxx_timer_hwmod_class, | |
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298 | }; |
299 | ||
844a3b63 PW |
300 | /* timer9 */ |
301 | static struct omap_hwmod omap3xxx_timer9_hwmod = { | |
302 | .name = "timer9", | |
303 | .mpu_irqs = omap2_timer9_mpu_irqs, | |
304 | .main_clk = "gpt9_fck", | |
305 | .prcm = { | |
306 | .omap2 = { | |
307 | .prcm_reg_id = 1, | |
308 | .module_bit = OMAP3430_EN_GPT9_SHIFT, | |
309 | .module_offs = OMAP3430_PER_MOD, | |
310 | .idlest_reg_id = 1, | |
311 | .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, | |
312 | }, | |
4fe20e97 | 313 | }, |
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314 | .dev_attr = &capability_pwm_dev_attr, |
315 | .class = &omap3xxx_timer_hwmod_class, | |
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316 | }; |
317 | ||
844a3b63 PW |
318 | /* timer10 */ |
319 | static struct omap_hwmod omap3xxx_timer10_hwmod = { | |
320 | .name = "timer10", | |
321 | .mpu_irqs = omap2_timer10_mpu_irqs, | |
322 | .main_clk = "gpt10_fck", | |
323 | .prcm = { | |
4fe20e97 | 324 | .omap2 = { |
844a3b63 PW |
325 | .prcm_reg_id = 1, |
326 | .module_bit = OMAP3430_EN_GPT10_SHIFT, | |
327 | .module_offs = CORE_MOD, | |
328 | .idlest_reg_id = 1, | |
329 | .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, | |
330 | }, | |
4fe20e97 | 331 | }, |
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332 | .dev_attr = &capability_pwm_dev_attr, |
333 | .class = &omap3xxx_timer_1ms_hwmod_class, | |
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334 | }; |
335 | ||
844a3b63 PW |
336 | /* timer11 */ |
337 | static struct omap_hwmod omap3xxx_timer11_hwmod = { | |
338 | .name = "timer11", | |
339 | .mpu_irqs = omap2_timer11_mpu_irqs, | |
340 | .main_clk = "gpt11_fck", | |
341 | .prcm = { | |
342 | .omap2 = { | |
343 | .prcm_reg_id = 1, | |
344 | .module_bit = OMAP3430_EN_GPT11_SHIFT, | |
345 | .module_offs = CORE_MOD, | |
346 | .idlest_reg_id = 1, | |
347 | .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, | |
348 | }, | |
349 | }, | |
350 | .dev_attr = &capability_pwm_dev_attr, | |
351 | .class = &omap3xxx_timer_hwmod_class, | |
d62bc78a NM |
352 | }; |
353 | ||
844a3b63 PW |
354 | /* timer12 */ |
355 | static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { | |
356 | { .irq = 95, }, | |
d62bc78a NM |
357 | { .irq = -1 } |
358 | }; | |
359 | ||
844a3b63 PW |
360 | static struct omap_hwmod omap3xxx_timer12_hwmod = { |
361 | .name = "timer12", | |
362 | .mpu_irqs = omap3xxx_timer12_mpu_irqs, | |
363 | .main_clk = "gpt12_fck", | |
364 | .prcm = { | |
365 | .omap2 = { | |
366 | .prcm_reg_id = 1, | |
367 | .module_bit = OMAP3430_EN_GPT12_SHIFT, | |
368 | .module_offs = WKUP_MOD, | |
369 | .idlest_reg_id = 1, | |
370 | .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, | |
371 | }, | |
d3442726 | 372 | }, |
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373 | .dev_attr = &capability_secure_dev_attr, |
374 | .class = &omap3xxx_timer_hwmod_class, | |
d3442726 TG |
375 | }; |
376 | ||
844a3b63 PW |
377 | /* |
378 | * 'wd_timer' class | |
379 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
380 | * overflow condition | |
381 | */ | |
382 | ||
383 | static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { | |
384 | .rev_offs = 0x0000, | |
385 | .sysc_offs = 0x0010, | |
386 | .syss_offs = 0x0014, | |
387 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | | |
388 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
389 | SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
390 | SYSS_HAS_RESET_STATUS), | |
391 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
392 | .sysc_fields = &omap_hwmod_sysc_type1, | |
d3442726 TG |
393 | }; |
394 | ||
844a3b63 PW |
395 | /* I2C common */ |
396 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
397 | .rev_offs = 0x00, | |
398 | .sysc_offs = 0x20, | |
399 | .syss_offs = 0x10, | |
400 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
401 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
402 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
403 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
404 | .clockact = CLOCKACT_TEST_ICLK, | |
405 | .sysc_fields = &omap_hwmod_sysc_type1, | |
d3442726 TG |
406 | }; |
407 | ||
844a3b63 PW |
408 | static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { |
409 | .name = "wd_timer", | |
410 | .sysc = &omap3xxx_wd_timer_sysc, | |
411 | .pre_shutdown = &omap2_wd_timer_disable | |
d3442726 TG |
412 | }; |
413 | ||
844a3b63 PW |
414 | static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { |
415 | .name = "wd_timer2", | |
416 | .class = &omap3xxx_wd_timer_hwmod_class, | |
417 | .main_clk = "wdt2_fck", | |
418 | .prcm = { | |
419 | .omap2 = { | |
420 | .prcm_reg_id = 1, | |
421 | .module_bit = OMAP3430_EN_WDT2_SHIFT, | |
422 | .module_offs = WKUP_MOD, | |
423 | .idlest_reg_id = 1, | |
424 | .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, | |
425 | }, | |
426 | }, | |
427 | /* | |
428 | * XXX: Use software supervised mode, HW supervised smartidle seems to | |
429 | * block CORE power domain idle transitions. Maybe a HW bug in wdt2? | |
430 | */ | |
431 | .flags = HWMOD_SWSUP_SIDLE, | |
432 | }; | |
870ea2b8 | 433 | |
844a3b63 PW |
434 | /* UART1 */ |
435 | static struct omap_hwmod omap3xxx_uart1_hwmod = { | |
436 | .name = "uart1", | |
437 | .mpu_irqs = omap2_uart1_mpu_irqs, | |
438 | .sdma_reqs = omap2_uart1_sdma_reqs, | |
439 | .main_clk = "uart1_fck", | |
440 | .prcm = { | |
441 | .omap2 = { | |
442 | .module_offs = CORE_MOD, | |
443 | .prcm_reg_id = 1, | |
444 | .module_bit = OMAP3430_EN_UART1_SHIFT, | |
445 | .idlest_reg_id = 1, | |
446 | .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, | |
447 | }, | |
870ea2b8 | 448 | }, |
844a3b63 | 449 | .class = &omap2_uart_class, |
870ea2b8 HH |
450 | }; |
451 | ||
844a3b63 PW |
452 | /* UART2 */ |
453 | static struct omap_hwmod omap3xxx_uart2_hwmod = { | |
454 | .name = "uart2", | |
455 | .mpu_irqs = omap2_uart2_mpu_irqs, | |
456 | .sdma_reqs = omap2_uart2_sdma_reqs, | |
457 | .main_clk = "uart2_fck", | |
458 | .prcm = { | |
459 | .omap2 = { | |
460 | .module_offs = CORE_MOD, | |
461 | .prcm_reg_id = 1, | |
462 | .module_bit = OMAP3430_EN_UART2_SHIFT, | |
463 | .idlest_reg_id = 1, | |
464 | .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, | |
465 | }, | |
466 | }, | |
467 | .class = &omap2_uart_class, | |
870ea2b8 HH |
468 | }; |
469 | ||
844a3b63 PW |
470 | /* UART3 */ |
471 | static struct omap_hwmod omap3xxx_uart3_hwmod = { | |
472 | .name = "uart3", | |
473 | .mpu_irqs = omap2_uart3_mpu_irqs, | |
474 | .sdma_reqs = omap2_uart3_sdma_reqs, | |
475 | .main_clk = "uart3_fck", | |
476 | .prcm = { | |
477 | .omap2 = { | |
478 | .module_offs = OMAP3430_PER_MOD, | |
479 | .prcm_reg_id = 1, | |
480 | .module_bit = OMAP3430_EN_UART3_SHIFT, | |
481 | .idlest_reg_id = 1, | |
482 | .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, | |
483 | }, | |
273ff8c3 | 484 | }, |
844a3b63 | 485 | .class = &omap2_uart_class, |
273ff8c3 HH |
486 | }; |
487 | ||
844a3b63 PW |
488 | /* UART4 */ |
489 | static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { | |
490 | { .irq = INT_36XX_UART4_IRQ, }, | |
491 | { .irq = -1 } | |
273ff8c3 HH |
492 | }; |
493 | ||
844a3b63 PW |
494 | static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { |
495 | { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, | |
496 | { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, | |
497 | { .dma_req = -1 } | |
7359154e PW |
498 | }; |
499 | ||
844a3b63 PW |
500 | static struct omap_hwmod omap36xx_uart4_hwmod = { |
501 | .name = "uart4", | |
502 | .mpu_irqs = uart4_mpu_irqs, | |
503 | .sdma_reqs = uart4_sdma_reqs, | |
504 | .main_clk = "uart4_fck", | |
505 | .prcm = { | |
506 | .omap2 = { | |
507 | .module_offs = OMAP3430_PER_MOD, | |
508 | .prcm_reg_id = 1, | |
509 | .module_bit = OMAP3630_EN_UART4_SHIFT, | |
510 | .idlest_reg_id = 1, | |
511 | .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, | |
512 | }, | |
513 | }, | |
514 | .class = &omap2_uart_class, | |
7359154e PW |
515 | }; |
516 | ||
844a3b63 PW |
517 | static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { |
518 | { .irq = INT_35XX_UART4_IRQ, }, | |
43085705 PW |
519 | }; |
520 | ||
844a3b63 PW |
521 | static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { |
522 | { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, | |
523 | { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, | |
7359154e PW |
524 | }; |
525 | ||
844a3b63 PW |
526 | static struct omap_hwmod am35xx_uart4_hwmod = { |
527 | .name = "uart4", | |
528 | .mpu_irqs = am35xx_uart4_mpu_irqs, | |
529 | .sdma_reqs = am35xx_uart4_sdma_reqs, | |
530 | .main_clk = "uart4_fck", | |
531 | .prcm = { | |
532 | .omap2 = { | |
533 | .module_offs = CORE_MOD, | |
534 | .prcm_reg_id = 1, | |
535 | .module_bit = OMAP3430_EN_UART4_SHIFT, | |
536 | .idlest_reg_id = 1, | |
537 | .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT, | |
538 | }, | |
539 | }, | |
540 | .class = &omap2_uart_class, | |
541 | }; | |
542 | ||
543 | static struct omap_hwmod_class i2c_class = { | |
544 | .name = "i2c", | |
545 | .sysc = &i2c_sysc, | |
546 | .rev = OMAP_I2C_IP_VERSION_1, | |
547 | .reset = &omap_i2c_reset, | |
548 | }; | |
549 | ||
550 | static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { | |
551 | { .name = "dispc", .dma_req = 5 }, | |
552 | { .name = "dsi1", .dma_req = 74 }, | |
553 | { .dma_req = -1 } | |
43085705 PW |
554 | }; |
555 | ||
844a3b63 PW |
556 | /* dss */ |
557 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |
558 | /* | |
559 | * The DSS HW needs all DSS clocks enabled during reset. The dss_core | |
560 | * driver does not use these clocks. | |
561 | */ | |
562 | { .role = "sys_clk", .clk = "dss2_alwon_fck" }, | |
563 | { .role = "tv_clk", .clk = "dss_tv_fck" }, | |
564 | /* required only on OMAP3430 */ | |
565 | { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, | |
7359154e PW |
566 | }; |
567 | ||
844a3b63 PW |
568 | static struct omap_hwmod omap3430es1_dss_core_hwmod = { |
569 | .name = "dss_core", | |
570 | .class = &omap2_dss_hwmod_class, | |
571 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ | |
572 | .sdma_reqs = omap3xxx_dss_sdma_chs, | |
573 | .prcm = { | |
574 | .omap2 = { | |
575 | .prcm_reg_id = 1, | |
576 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
577 | .module_offs = OMAP3430_DSS_MOD, | |
578 | .idlest_reg_id = 1, | |
579 | .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, | |
580 | }, | |
581 | }, | |
582 | .opt_clks = dss_opt_clks, | |
583 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
584 | .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
585 | }; | |
540064bf | 586 | |
844a3b63 PW |
587 | static struct omap_hwmod omap3xxx_dss_core_hwmod = { |
588 | .name = "dss_core", | |
589 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
590 | .class = &omap2_dss_hwmod_class, | |
591 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ | |
592 | .sdma_reqs = omap3xxx_dss_sdma_chs, | |
593 | .prcm = { | |
594 | .omap2 = { | |
595 | .prcm_reg_id = 1, | |
596 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
597 | .module_offs = OMAP3430_DSS_MOD, | |
598 | .idlest_reg_id = 1, | |
599 | .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, | |
600 | .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, | |
601 | }, | |
602 | }, | |
603 | .opt_clks = dss_opt_clks, | |
604 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
540064bf KH |
605 | }; |
606 | ||
540064bf | 607 | /* |
844a3b63 PW |
608 | * 'dispc' class |
609 | * display controller | |
540064bf KH |
610 | */ |
611 | ||
844a3b63 | 612 | static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { |
ce722d26 TG |
613 | .rev_offs = 0x0000, |
614 | .sysc_offs = 0x0010, | |
615 | .syss_offs = 0x0014, | |
844a3b63 PW |
616 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | |
617 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
618 | SYSC_HAS_ENAWAKEUP), | |
619 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
620 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
ce722d26 | 621 | .sysc_fields = &omap_hwmod_sysc_type1, |
6b667f88 VC |
622 | }; |
623 | ||
844a3b63 PW |
624 | static struct omap_hwmod_class omap3_dispc_hwmod_class = { |
625 | .name = "dispc", | |
626 | .sysc = &omap3_dispc_sysc, | |
6b667f88 VC |
627 | }; |
628 | ||
844a3b63 PW |
629 | static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { |
630 | .name = "dss_dispc", | |
631 | .class = &omap3_dispc_hwmod_class, | |
632 | .mpu_irqs = omap2_dispc_irqs, | |
633 | .main_clk = "dss1_alwon_fck", | |
634 | .prcm = { | |
635 | .omap2 = { | |
636 | .prcm_reg_id = 1, | |
637 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
638 | .module_offs = OMAP3430_DSS_MOD, | |
639 | }, | |
640 | }, | |
641 | .flags = HWMOD_NO_IDLEST, | |
642 | .dev_attr = &omap2_3_dss_dispc_dev_attr | |
6b667f88 VC |
643 | }; |
644 | ||
844a3b63 PW |
645 | /* |
646 | * 'dsi' class | |
647 | * display serial interface controller | |
648 | */ | |
4fe20e97 | 649 | |
844a3b63 PW |
650 | static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { |
651 | .name = "dsi", | |
c345c8b0 TKD |
652 | }; |
653 | ||
844a3b63 PW |
654 | static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { |
655 | { .irq = 25 }, | |
656 | { .irq = -1 } | |
c345c8b0 TKD |
657 | }; |
658 | ||
844a3b63 PW |
659 | /* dss_dsi1 */ |
660 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { | |
661 | { .role = "sys_clk", .clk = "dss2_alwon_fck" }, | |
c345c8b0 TKD |
662 | }; |
663 | ||
844a3b63 PW |
664 | static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { |
665 | .name = "dss_dsi1", | |
666 | .class = &omap3xxx_dsi_hwmod_class, | |
667 | .mpu_irqs = omap3xxx_dsi1_irqs, | |
668 | .main_clk = "dss1_alwon_fck", | |
669 | .prcm = { | |
670 | .omap2 = { | |
671 | .prcm_reg_id = 1, | |
672 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
673 | .module_offs = OMAP3430_DSS_MOD, | |
674 | }, | |
ce722d26 | 675 | }, |
844a3b63 PW |
676 | .opt_clks = dss_dsi1_opt_clks, |
677 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
678 | .flags = HWMOD_NO_IDLEST, | |
6b667f88 VC |
679 | }; |
680 | ||
844a3b63 PW |
681 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
682 | { .role = "ick", .clk = "dss_ick" }, | |
ce722d26 TG |
683 | }; |
684 | ||
844a3b63 PW |
685 | static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { |
686 | .name = "dss_rfbi", | |
687 | .class = &omap2_rfbi_hwmod_class, | |
688 | .main_clk = "dss1_alwon_fck", | |
6b667f88 VC |
689 | .prcm = { |
690 | .omap2 = { | |
691 | .prcm_reg_id = 1, | |
844a3b63 PW |
692 | .module_bit = OMAP3430_EN_DSS1_SHIFT, |
693 | .module_offs = OMAP3430_DSS_MOD, | |
6b667f88 VC |
694 | }, |
695 | }, | |
844a3b63 PW |
696 | .opt_clks = dss_rfbi_opt_clks, |
697 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
698 | .flags = HWMOD_NO_IDLEST, | |
046465b7 KH |
699 | }; |
700 | ||
844a3b63 PW |
701 | static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { |
702 | /* required only on OMAP3430 */ | |
703 | { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, | |
046465b7 KH |
704 | }; |
705 | ||
844a3b63 PW |
706 | static struct omap_hwmod omap3xxx_dss_venc_hwmod = { |
707 | .name = "dss_venc", | |
708 | .class = &omap2_venc_hwmod_class, | |
709 | .main_clk = "dss_tv_fck", | |
046465b7 KH |
710 | .prcm = { |
711 | .omap2 = { | |
046465b7 | 712 | .prcm_reg_id = 1, |
844a3b63 PW |
713 | .module_bit = OMAP3430_EN_DSS1_SHIFT, |
714 | .module_offs = OMAP3430_DSS_MOD, | |
046465b7 KH |
715 | }, |
716 | }, | |
844a3b63 PW |
717 | .opt_clks = dss_venc_opt_clks, |
718 | .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), | |
719 | .flags = HWMOD_NO_IDLEST, | |
046465b7 KH |
720 | }; |
721 | ||
844a3b63 PW |
722 | /* I2C1 */ |
723 | static struct omap_i2c_dev_attr i2c1_dev_attr = { | |
724 | .fifo_depth = 8, /* bytes */ | |
725 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
726 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
727 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
046465b7 KH |
728 | }; |
729 | ||
844a3b63 PW |
730 | static struct omap_hwmod omap3xxx_i2c1_hwmod = { |
731 | .name = "i2c1", | |
732 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
733 | .mpu_irqs = omap2_i2c1_mpu_irqs, | |
734 | .sdma_reqs = omap2_i2c1_sdma_reqs, | |
735 | .main_clk = "i2c1_fck", | |
046465b7 KH |
736 | .prcm = { |
737 | .omap2 = { | |
844a3b63 | 738 | .module_offs = CORE_MOD, |
046465b7 | 739 | .prcm_reg_id = 1, |
844a3b63 | 740 | .module_bit = OMAP3430_EN_I2C1_SHIFT, |
046465b7 | 741 | .idlest_reg_id = 1, |
844a3b63 | 742 | .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, |
046465b7 KH |
743 | }, |
744 | }, | |
844a3b63 PW |
745 | .class = &i2c_class, |
746 | .dev_attr = &i2c1_dev_attr, | |
046465b7 KH |
747 | }; |
748 | ||
844a3b63 PW |
749 | /* I2C2 */ |
750 | static struct omap_i2c_dev_attr i2c2_dev_attr = { | |
751 | .fifo_depth = 8, /* bytes */ | |
752 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
753 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
754 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
046465b7 KH |
755 | }; |
756 | ||
844a3b63 PW |
757 | static struct omap_hwmod omap3xxx_i2c2_hwmod = { |
758 | .name = "i2c2", | |
759 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
760 | .mpu_irqs = omap2_i2c2_mpu_irqs, | |
761 | .sdma_reqs = omap2_i2c2_sdma_reqs, | |
762 | .main_clk = "i2c2_fck", | |
046465b7 KH |
763 | .prcm = { |
764 | .omap2 = { | |
844a3b63 | 765 | .module_offs = CORE_MOD, |
046465b7 | 766 | .prcm_reg_id = 1, |
844a3b63 | 767 | .module_bit = OMAP3430_EN_I2C2_SHIFT, |
046465b7 | 768 | .idlest_reg_id = 1, |
844a3b63 | 769 | .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, |
046465b7 KH |
770 | }, |
771 | }, | |
844a3b63 PW |
772 | .class = &i2c_class, |
773 | .dev_attr = &i2c2_dev_attr, | |
046465b7 KH |
774 | }; |
775 | ||
844a3b63 PW |
776 | /* I2C3 */ |
777 | static struct omap_i2c_dev_attr i2c3_dev_attr = { | |
778 | .fifo_depth = 64, /* bytes */ | |
779 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
780 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
781 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
782 | }; | |
046465b7 | 783 | |
844a3b63 PW |
784 | static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { |
785 | { .irq = INT_34XX_I2C3_IRQ, }, | |
786 | { .irq = -1 } | |
046465b7 KH |
787 | }; |
788 | ||
844a3b63 PW |
789 | static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { |
790 | { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, | |
791 | { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, | |
792 | { .dma_req = -1 } | |
046465b7 KH |
793 | }; |
794 | ||
844a3b63 PW |
795 | static struct omap_hwmod omap3xxx_i2c3_hwmod = { |
796 | .name = "i2c3", | |
797 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
798 | .mpu_irqs = i2c3_mpu_irqs, | |
799 | .sdma_reqs = i2c3_sdma_reqs, | |
800 | .main_clk = "i2c3_fck", | |
046465b7 KH |
801 | .prcm = { |
802 | .omap2 = { | |
844a3b63 | 803 | .module_offs = CORE_MOD, |
046465b7 | 804 | .prcm_reg_id = 1, |
844a3b63 | 805 | .module_bit = OMAP3430_EN_I2C3_SHIFT, |
046465b7 | 806 | .idlest_reg_id = 1, |
844a3b63 | 807 | .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, |
046465b7 KH |
808 | }, |
809 | }, | |
844a3b63 PW |
810 | .class = &i2c_class, |
811 | .dev_attr = &i2c3_dev_attr, | |
4fe20e97 RN |
812 | }; |
813 | ||
844a3b63 PW |
814 | /* |
815 | * 'gpio' class | |
816 | * general purpose io module | |
817 | */ | |
4fe20e97 | 818 | |
844a3b63 PW |
819 | static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { |
820 | .rev_offs = 0x0000, | |
821 | .sysc_offs = 0x0010, | |
822 | .syss_offs = 0x0014, | |
823 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
824 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
825 | SYSS_HAS_RESET_STATUS), | |
826 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
827 | .sysc_fields = &omap_hwmod_sysc_type1, | |
4fe20e97 RN |
828 | }; |
829 | ||
844a3b63 PW |
830 | static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { |
831 | .name = "gpio", | |
832 | .sysc = &omap3xxx_gpio_sysc, | |
833 | .rev = 1, | |
4fe20e97 RN |
834 | }; |
835 | ||
844a3b63 PW |
836 | /* gpio_dev_attr */ |
837 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
838 | .bank_width = 32, | |
839 | .dbck_flag = true, | |
840 | }; | |
841 | ||
842 | /* gpio1 */ | |
843 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | |
844 | { .role = "dbclk", .clk = "gpio1_dbck", }, | |
845 | }; | |
846 | ||
847 | static struct omap_hwmod omap3xxx_gpio1_hwmod = { | |
848 | .name = "gpio1", | |
849 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
850 | .mpu_irqs = omap2_gpio1_irqs, | |
851 | .main_clk = "gpio1_ick", | |
852 | .opt_clks = gpio1_opt_clks, | |
853 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
4fe20e97 RN |
854 | .prcm = { |
855 | .omap2 = { | |
4fe20e97 | 856 | .prcm_reg_id = 1, |
844a3b63 PW |
857 | .module_bit = OMAP3430_EN_GPIO1_SHIFT, |
858 | .module_offs = WKUP_MOD, | |
4fe20e97 | 859 | .idlest_reg_id = 1, |
844a3b63 | 860 | .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, |
4fe20e97 RN |
861 | }, |
862 | }, | |
844a3b63 PW |
863 | .class = &omap3xxx_gpio_hwmod_class, |
864 | .dev_attr = &gpio_dev_attr, | |
4fe20e97 RN |
865 | }; |
866 | ||
844a3b63 PW |
867 | /* gpio2 */ |
868 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | |
869 | { .role = "dbclk", .clk = "gpio2_dbck", }, | |
4fe20e97 RN |
870 | }; |
871 | ||
844a3b63 PW |
872 | static struct omap_hwmod omap3xxx_gpio2_hwmod = { |
873 | .name = "gpio2", | |
874 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
875 | .mpu_irqs = omap2_gpio2_irqs, | |
876 | .main_clk = "gpio2_ick", | |
877 | .opt_clks = gpio2_opt_clks, | |
878 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
4fe20e97 RN |
879 | .prcm = { |
880 | .omap2 = { | |
4fe20e97 | 881 | .prcm_reg_id = 1, |
844a3b63 | 882 | .module_bit = OMAP3430_EN_GPIO2_SHIFT, |
ce722d26 | 883 | .module_offs = OMAP3430_PER_MOD, |
4fe20e97 | 884 | .idlest_reg_id = 1, |
844a3b63 | 885 | .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, |
4fe20e97 RN |
886 | }, |
887 | }, | |
844a3b63 PW |
888 | .class = &omap3xxx_gpio_hwmod_class, |
889 | .dev_attr = &gpio_dev_attr, | |
4fe20e97 RN |
890 | }; |
891 | ||
844a3b63 PW |
892 | /* gpio3 */ |
893 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { | |
894 | { .role = "dbclk", .clk = "gpio3_dbck", }, | |
4fe20e97 RN |
895 | }; |
896 | ||
844a3b63 PW |
897 | static struct omap_hwmod omap3xxx_gpio3_hwmod = { |
898 | .name = "gpio3", | |
899 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
900 | .mpu_irqs = omap2_gpio3_irqs, | |
901 | .main_clk = "gpio3_ick", | |
902 | .opt_clks = gpio3_opt_clks, | |
903 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
4fe20e97 RN |
904 | .prcm = { |
905 | .omap2 = { | |
4fe20e97 | 906 | .prcm_reg_id = 1, |
844a3b63 | 907 | .module_bit = OMAP3430_EN_GPIO3_SHIFT, |
ce722d26 | 908 | .module_offs = OMAP3430_PER_MOD, |
4fe20e97 | 909 | .idlest_reg_id = 1, |
844a3b63 | 910 | .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, |
4fe20e97 RN |
911 | }, |
912 | }, | |
844a3b63 PW |
913 | .class = &omap3xxx_gpio_hwmod_class, |
914 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
915 | }; |
916 | ||
844a3b63 PW |
917 | /* gpio4 */ |
918 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { | |
919 | { .role = "dbclk", .clk = "gpio4_dbck", }, | |
70034d38 VC |
920 | }; |
921 | ||
844a3b63 PW |
922 | static struct omap_hwmod omap3xxx_gpio4_hwmod = { |
923 | .name = "gpio4", | |
924 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
925 | .mpu_irqs = omap2_gpio4_irqs, | |
926 | .main_clk = "gpio4_ick", | |
927 | .opt_clks = gpio4_opt_clks, | |
928 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
ce722d26 TG |
929 | .prcm = { |
930 | .omap2 = { | |
931 | .prcm_reg_id = 1, | |
844a3b63 | 932 | .module_bit = OMAP3430_EN_GPIO4_SHIFT, |
ce722d26 TG |
933 | .module_offs = OMAP3430_PER_MOD, |
934 | .idlest_reg_id = 1, | |
844a3b63 | 935 | .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, |
ce722d26 | 936 | }, |
70034d38 | 937 | }, |
844a3b63 PW |
938 | .class = &omap3xxx_gpio_hwmod_class, |
939 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
940 | }; |
941 | ||
844a3b63 PW |
942 | /* gpio5 */ |
943 | static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { | |
944 | { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */ | |
945 | { .irq = -1 } | |
946 | }; | |
70034d38 | 947 | |
844a3b63 PW |
948 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
949 | { .role = "dbclk", .clk = "gpio5_dbck", }, | |
70034d38 VC |
950 | }; |
951 | ||
844a3b63 PW |
952 | static struct omap_hwmod omap3xxx_gpio5_hwmod = { |
953 | .name = "gpio5", | |
954 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
955 | .mpu_irqs = omap3xxx_gpio5_irqs, | |
956 | .main_clk = "gpio5_ick", | |
957 | .opt_clks = gpio5_opt_clks, | |
958 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
ce722d26 TG |
959 | .prcm = { |
960 | .omap2 = { | |
961 | .prcm_reg_id = 1, | |
844a3b63 PW |
962 | .module_bit = OMAP3430_EN_GPIO5_SHIFT, |
963 | .module_offs = OMAP3430_PER_MOD, | |
ce722d26 | 964 | .idlest_reg_id = 1, |
844a3b63 | 965 | .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, |
ce722d26 | 966 | }, |
70034d38 | 967 | }, |
844a3b63 PW |
968 | .class = &omap3xxx_gpio_hwmod_class, |
969 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
970 | }; |
971 | ||
844a3b63 PW |
972 | /* gpio6 */ |
973 | static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { | |
974 | { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */ | |
975 | { .irq = -1 } | |
976 | }; | |
70034d38 | 977 | |
844a3b63 PW |
978 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
979 | { .role = "dbclk", .clk = "gpio6_dbck", }, | |
70034d38 VC |
980 | }; |
981 | ||
844a3b63 PW |
982 | static struct omap_hwmod omap3xxx_gpio6_hwmod = { |
983 | .name = "gpio6", | |
984 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
985 | .mpu_irqs = omap3xxx_gpio6_irqs, | |
986 | .main_clk = "gpio6_ick", | |
987 | .opt_clks = gpio6_opt_clks, | |
988 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
ce722d26 TG |
989 | .prcm = { |
990 | .omap2 = { | |
991 | .prcm_reg_id = 1, | |
844a3b63 PW |
992 | .module_bit = OMAP3430_EN_GPIO6_SHIFT, |
993 | .module_offs = OMAP3430_PER_MOD, | |
ce722d26 | 994 | .idlest_reg_id = 1, |
844a3b63 | 995 | .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, |
ce722d26 TG |
996 | }, |
997 | }, | |
844a3b63 PW |
998 | .class = &omap3xxx_gpio_hwmod_class, |
999 | .dev_attr = &gpio_dev_attr, | |
ce722d26 TG |
1000 | }; |
1001 | ||
844a3b63 PW |
1002 | /* dma attributes */ |
1003 | static struct omap_dma_dev_attr dma_dev_attr = { | |
1004 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
1005 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
1006 | .lch_count = 32, | |
ce722d26 TG |
1007 | }; |
1008 | ||
844a3b63 PW |
1009 | static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { |
1010 | .rev_offs = 0x0000, | |
1011 | .sysc_offs = 0x002c, | |
1012 | .syss_offs = 0x0028, | |
1013 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1014 | SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
1015 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | | |
1016 | SYSS_HAS_RESET_STATUS), | |
1017 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1018 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1019 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1020 | }; |
1021 | ||
844a3b63 PW |
1022 | static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { |
1023 | .name = "dma", | |
1024 | .sysc = &omap3xxx_dma_sysc, | |
70034d38 VC |
1025 | }; |
1026 | ||
844a3b63 PW |
1027 | /* dma_system */ |
1028 | static struct omap_hwmod omap3xxx_dma_system_hwmod = { | |
1029 | .name = "dma", | |
1030 | .class = &omap3xxx_dma_hwmod_class, | |
1031 | .mpu_irqs = omap2_dma_system_irqs, | |
1032 | .main_clk = "core_l3_ick", | |
1033 | .prcm = { | |
ce722d26 | 1034 | .omap2 = { |
844a3b63 PW |
1035 | .module_offs = CORE_MOD, |
1036 | .prcm_reg_id = 1, | |
1037 | .module_bit = OMAP3430_ST_SDMA_SHIFT, | |
1038 | .idlest_reg_id = 1, | |
1039 | .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, | |
ce722d26 TG |
1040 | }, |
1041 | }, | |
844a3b63 PW |
1042 | .dev_attr = &dma_dev_attr, |
1043 | .flags = HWMOD_NO_IDLEST, | |
70034d38 VC |
1044 | }; |
1045 | ||
844a3b63 PW |
1046 | /* |
1047 | * 'mcbsp' class | |
1048 | * multi channel buffered serial port controller | |
1049 | */ | |
1050 | ||
1051 | static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { | |
1052 | .sysc_offs = 0x008c, | |
1053 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
1054 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1055 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1056 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1057 | .clockact = 0x2, | |
70034d38 VC |
1058 | }; |
1059 | ||
844a3b63 PW |
1060 | static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { |
1061 | .name = "mcbsp", | |
1062 | .sysc = &omap3xxx_mcbsp_sysc, | |
1063 | .rev = MCBSP_CONFIG_TYPE3, | |
70034d38 VC |
1064 | }; |
1065 | ||
844a3b63 PW |
1066 | /* mcbsp1 */ |
1067 | static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { | |
1068 | { .name = "irq", .irq = 16 }, | |
1069 | { .name = "tx", .irq = 59 }, | |
1070 | { .name = "rx", .irq = 60 }, | |
1071 | { .irq = -1 } | |
1072 | }; | |
6b667f88 | 1073 | |
844a3b63 PW |
1074 | static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { |
1075 | .name = "mcbsp1", | |
1076 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1077 | .mpu_irqs = omap3xxx_mcbsp1_irqs, | |
1078 | .sdma_reqs = omap2_mcbsp1_sdma_reqs, | |
1079 | .main_clk = "mcbsp1_fck", | |
1080 | .prcm = { | |
1081 | .omap2 = { | |
1082 | .prcm_reg_id = 1, | |
1083 | .module_bit = OMAP3430_EN_MCBSP1_SHIFT, | |
1084 | .module_offs = CORE_MOD, | |
1085 | .idlest_reg_id = 1, | |
1086 | .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, | |
1087 | }, | |
1088 | }, | |
70034d38 VC |
1089 | }; |
1090 | ||
844a3b63 PW |
1091 | /* mcbsp2 */ |
1092 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { | |
1093 | { .name = "irq", .irq = 17 }, | |
1094 | { .name = "tx", .irq = 62 }, | |
1095 | { .name = "rx", .irq = 63 }, | |
1096 | { .irq = -1 } | |
70034d38 VC |
1097 | }; |
1098 | ||
844a3b63 PW |
1099 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { |
1100 | .sidetone = "mcbsp2_sidetone", | |
70034d38 VC |
1101 | }; |
1102 | ||
844a3b63 PW |
1103 | static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { |
1104 | .name = "mcbsp2", | |
1105 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1106 | .mpu_irqs = omap3xxx_mcbsp2_irqs, | |
1107 | .sdma_reqs = omap2_mcbsp2_sdma_reqs, | |
1108 | .main_clk = "mcbsp2_fck", | |
70034d38 VC |
1109 | .prcm = { |
1110 | .omap2 = { | |
1111 | .prcm_reg_id = 1, | |
844a3b63 PW |
1112 | .module_bit = OMAP3430_EN_MCBSP2_SHIFT, |
1113 | .module_offs = OMAP3430_PER_MOD, | |
70034d38 | 1114 | .idlest_reg_id = 1, |
844a3b63 | 1115 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, |
70034d38 VC |
1116 | }, |
1117 | }, | |
844a3b63 | 1118 | .dev_attr = &omap34xx_mcbsp2_dev_attr, |
70034d38 VC |
1119 | }; |
1120 | ||
844a3b63 PW |
1121 | /* mcbsp3 */ |
1122 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { | |
1123 | { .name = "irq", .irq = 22 }, | |
1124 | { .name = "tx", .irq = 89 }, | |
1125 | { .name = "rx", .irq = 90 }, | |
1126 | { .irq = -1 } | |
1127 | }; | |
1128 | ||
1129 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { | |
1130 | .sidetone = "mcbsp3_sidetone", | |
1131 | }; | |
1132 | ||
1133 | static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { | |
1134 | .name = "mcbsp3", | |
1135 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1136 | .mpu_irqs = omap3xxx_mcbsp3_irqs, | |
1137 | .sdma_reqs = omap2_mcbsp3_sdma_reqs, | |
1138 | .main_clk = "mcbsp3_fck", | |
70034d38 VC |
1139 | .prcm = { |
1140 | .omap2 = { | |
1141 | .prcm_reg_id = 1, | |
844a3b63 PW |
1142 | .module_bit = OMAP3430_EN_MCBSP3_SHIFT, |
1143 | .module_offs = OMAP3430_PER_MOD, | |
70034d38 | 1144 | .idlest_reg_id = 1, |
844a3b63 | 1145 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, |
70034d38 VC |
1146 | }, |
1147 | }, | |
844a3b63 | 1148 | .dev_attr = &omap34xx_mcbsp3_dev_attr, |
70034d38 VC |
1149 | }; |
1150 | ||
844a3b63 PW |
1151 | /* mcbsp4 */ |
1152 | static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { | |
1153 | { .name = "irq", .irq = 23 }, | |
1154 | { .name = "tx", .irq = 54 }, | |
1155 | { .name = "rx", .irq = 55 }, | |
1156 | { .irq = -1 } | |
1157 | }; | |
1158 | ||
1159 | static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { | |
1160 | { .name = "rx", .dma_req = 20 }, | |
1161 | { .name = "tx", .dma_req = 19 }, | |
1162 | { .dma_req = -1 } | |
1163 | }; | |
1164 | ||
1165 | static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { | |
1166 | .name = "mcbsp4", | |
1167 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1168 | .mpu_irqs = omap3xxx_mcbsp4_irqs, | |
1169 | .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, | |
1170 | .main_clk = "mcbsp4_fck", | |
70034d38 VC |
1171 | .prcm = { |
1172 | .omap2 = { | |
1173 | .prcm_reg_id = 1, | |
844a3b63 PW |
1174 | .module_bit = OMAP3430_EN_MCBSP4_SHIFT, |
1175 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 1176 | .idlest_reg_id = 1, |
844a3b63 | 1177 | .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, |
046465b7 KH |
1178 | }, |
1179 | }, | |
046465b7 KH |
1180 | }; |
1181 | ||
844a3b63 PW |
1182 | /* mcbsp5 */ |
1183 | static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { | |
1184 | { .name = "irq", .irq = 27 }, | |
1185 | { .name = "tx", .irq = 81 }, | |
1186 | { .name = "rx", .irq = 82 }, | |
1187 | { .irq = -1 } | |
1188 | }; | |
1189 | ||
1190 | static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { | |
1191 | { .name = "rx", .dma_req = 22 }, | |
1192 | { .name = "tx", .dma_req = 21 }, | |
1193 | { .dma_req = -1 } | |
1194 | }; | |
1195 | ||
1196 | static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { | |
1197 | .name = "mcbsp5", | |
1198 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1199 | .mpu_irqs = omap3xxx_mcbsp5_irqs, | |
1200 | .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, | |
1201 | .main_clk = "mcbsp5_fck", | |
046465b7 KH |
1202 | .prcm = { |
1203 | .omap2 = { | |
046465b7 | 1204 | .prcm_reg_id = 1, |
844a3b63 PW |
1205 | .module_bit = OMAP3430_EN_MCBSP5_SHIFT, |
1206 | .module_offs = CORE_MOD, | |
70034d38 | 1207 | .idlest_reg_id = 1, |
844a3b63 | 1208 | .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, |
70034d38 VC |
1209 | }, |
1210 | }, | |
70034d38 VC |
1211 | }; |
1212 | ||
844a3b63 PW |
1213 | /* 'mcbsp sidetone' class */ |
1214 | static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { | |
1215 | .sysc_offs = 0x0010, | |
1216 | .sysc_flags = SYSC_HAS_AUTOIDLE, | |
1217 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1218 | }; | |
046465b7 | 1219 | |
844a3b63 PW |
1220 | static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { |
1221 | .name = "mcbsp_sidetone", | |
1222 | .sysc = &omap3xxx_mcbsp_sidetone_sysc, | |
70034d38 VC |
1223 | }; |
1224 | ||
844a3b63 PW |
1225 | /* mcbsp2_sidetone */ |
1226 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { | |
1227 | { .name = "irq", .irq = 4 }, | |
1228 | { .irq = -1 } | |
70034d38 VC |
1229 | }; |
1230 | ||
844a3b63 PW |
1231 | static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { |
1232 | .name = "mcbsp2_sidetone", | |
1233 | .class = &omap3xxx_mcbsp_sidetone_hwmod_class, | |
1234 | .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, | |
1235 | .main_clk = "mcbsp2_fck", | |
046465b7 KH |
1236 | .prcm = { |
1237 | .omap2 = { | |
046465b7 | 1238 | .prcm_reg_id = 1, |
844a3b63 PW |
1239 | .module_bit = OMAP3430_EN_MCBSP2_SHIFT, |
1240 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 1241 | .idlest_reg_id = 1, |
844a3b63 | 1242 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, |
046465b7 KH |
1243 | }, |
1244 | }, | |
4bf90f65 KM |
1245 | }; |
1246 | ||
844a3b63 PW |
1247 | /* mcbsp3_sidetone */ |
1248 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { | |
1249 | { .name = "irq", .irq = 5 }, | |
1250 | { .irq = -1 } | |
4bf90f65 KM |
1251 | }; |
1252 | ||
844a3b63 PW |
1253 | static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { |
1254 | .name = "mcbsp3_sidetone", | |
1255 | .class = &omap3xxx_mcbsp_sidetone_hwmod_class, | |
1256 | .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, | |
1257 | .main_clk = "mcbsp3_fck", | |
0a78c5c5 | 1258 | .prcm = { |
4bf90f65 | 1259 | .omap2 = { |
4bf90f65 | 1260 | .prcm_reg_id = 1, |
844a3b63 PW |
1261 | .module_bit = OMAP3430_EN_MCBSP3_SHIFT, |
1262 | .module_offs = OMAP3430_PER_MOD, | |
4bf90f65 | 1263 | .idlest_reg_id = 1, |
844a3b63 | 1264 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, |
4bf90f65 KM |
1265 | }, |
1266 | }, | |
4bf90f65 KM |
1267 | }; |
1268 | ||
844a3b63 PW |
1269 | /* SR common */ |
1270 | static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { | |
1271 | .clkact_shift = 20, | |
1272 | }; | |
4bf90f65 | 1273 | |
844a3b63 PW |
1274 | static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { |
1275 | .sysc_offs = 0x24, | |
1276 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), | |
1277 | .clockact = CLOCKACT_TEST_ICLK, | |
1278 | .sysc_fields = &omap34xx_sr_sysc_fields, | |
4fe20e97 RN |
1279 | }; |
1280 | ||
844a3b63 PW |
1281 | static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { |
1282 | .name = "smartreflex", | |
1283 | .sysc = &omap34xx_sr_sysc, | |
1284 | .rev = 1, | |
e04d9e1e SG |
1285 | }; |
1286 | ||
844a3b63 PW |
1287 | static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { |
1288 | .sidle_shift = 24, | |
1289 | .enwkup_shift = 26, | |
1290 | }; | |
e04d9e1e | 1291 | |
844a3b63 PW |
1292 | static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { |
1293 | .sysc_offs = 0x38, | |
1294 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1295 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
1296 | SYSC_NO_CACHE), | |
1297 | .sysc_fields = &omap36xx_sr_sysc_fields, | |
1298 | }; | |
1299 | ||
1300 | static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { | |
1301 | .name = "smartreflex", | |
1302 | .sysc = &omap36xx_sr_sysc, | |
1303 | .rev = 2, | |
1304 | }; | |
1305 | ||
1306 | /* SR1 */ | |
1307 | static struct omap_smartreflex_dev_attr sr1_dev_attr = { | |
1308 | .sensor_voltdm_name = "mpu_iva", | |
1309 | }; | |
1310 | ||
1311 | static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { | |
1312 | { .irq = 18 }, | |
1313 | { .irq = -1 } | |
1314 | }; | |
1315 | ||
1316 | static struct omap_hwmod omap34xx_sr1_hwmod = { | |
1317 | .name = "sr1", | |
1318 | .class = &omap34xx_smartreflex_hwmod_class, | |
1319 | .main_clk = "sr1_fck", | |
1320 | .prcm = { | |
e04d9e1e | 1321 | .omap2 = { |
844a3b63 PW |
1322 | .prcm_reg_id = 1, |
1323 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
1324 | .module_offs = WKUP_MOD, | |
1325 | .idlest_reg_id = 1, | |
1326 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
1327 | }, | |
e04d9e1e | 1328 | }, |
844a3b63 PW |
1329 | .dev_attr = &sr1_dev_attr, |
1330 | .mpu_irqs = omap3_smartreflex_mpu_irqs, | |
1331 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
e04d9e1e SG |
1332 | }; |
1333 | ||
844a3b63 PW |
1334 | static struct omap_hwmod omap36xx_sr1_hwmod = { |
1335 | .name = "sr1", | |
1336 | .class = &omap36xx_smartreflex_hwmod_class, | |
1337 | .main_clk = "sr1_fck", | |
1338 | .prcm = { | |
e04d9e1e | 1339 | .omap2 = { |
844a3b63 PW |
1340 | .prcm_reg_id = 1, |
1341 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
1342 | .module_offs = WKUP_MOD, | |
1343 | .idlest_reg_id = 1, | |
1344 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
1345 | }, | |
e04d9e1e | 1346 | }, |
844a3b63 PW |
1347 | .dev_attr = &sr1_dev_attr, |
1348 | .mpu_irqs = omap3_smartreflex_mpu_irqs, | |
e04d9e1e SG |
1349 | }; |
1350 | ||
844a3b63 PW |
1351 | /* SR2 */ |
1352 | static struct omap_smartreflex_dev_attr sr2_dev_attr = { | |
1353 | .sensor_voltdm_name = "core", | |
e04d9e1e SG |
1354 | }; |
1355 | ||
844a3b63 PW |
1356 | static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { |
1357 | { .irq = 19 }, | |
1358 | { .irq = -1 } | |
1359 | }; | |
1360 | ||
1361 | static struct omap_hwmod omap34xx_sr2_hwmod = { | |
1362 | .name = "sr2", | |
1363 | .class = &omap34xx_smartreflex_hwmod_class, | |
1364 | .main_clk = "sr2_fck", | |
e04d9e1e SG |
1365 | .prcm = { |
1366 | .omap2 = { | |
1367 | .prcm_reg_id = 1, | |
844a3b63 PW |
1368 | .module_bit = OMAP3430_EN_SR2_SHIFT, |
1369 | .module_offs = WKUP_MOD, | |
e04d9e1e | 1370 | .idlest_reg_id = 1, |
844a3b63 | 1371 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, |
e04d9e1e SG |
1372 | }, |
1373 | }, | |
844a3b63 PW |
1374 | .dev_attr = &sr2_dev_attr, |
1375 | .mpu_irqs = omap3_smartreflex_core_irqs, | |
1376 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
e04d9e1e SG |
1377 | }; |
1378 | ||
844a3b63 PW |
1379 | static struct omap_hwmod omap36xx_sr2_hwmod = { |
1380 | .name = "sr2", | |
1381 | .class = &omap36xx_smartreflex_hwmod_class, | |
1382 | .main_clk = "sr2_fck", | |
e04d9e1e SG |
1383 | .prcm = { |
1384 | .omap2 = { | |
1385 | .prcm_reg_id = 1, | |
844a3b63 PW |
1386 | .module_bit = OMAP3430_EN_SR2_SHIFT, |
1387 | .module_offs = WKUP_MOD, | |
e04d9e1e | 1388 | .idlest_reg_id = 1, |
844a3b63 | 1389 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, |
e04d9e1e SG |
1390 | }, |
1391 | }, | |
844a3b63 PW |
1392 | .dev_attr = &sr2_dev_attr, |
1393 | .mpu_irqs = omap3_smartreflex_core_irqs, | |
e04d9e1e SG |
1394 | }; |
1395 | ||
1ac6d46e | 1396 | /* |
844a3b63 PW |
1397 | * 'mailbox' class |
1398 | * mailbox module allowing communication between the on-chip processors | |
1399 | * using a queued mailbox-interrupt mechanism. | |
1ac6d46e TV |
1400 | */ |
1401 | ||
844a3b63 PW |
1402 | static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { |
1403 | .rev_offs = 0x000, | |
1404 | .sysc_offs = 0x010, | |
1405 | .syss_offs = 0x014, | |
1406 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1407 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1408 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1ac6d46e TV |
1409 | .sysc_fields = &omap_hwmod_sysc_type1, |
1410 | }; | |
1411 | ||
844a3b63 PW |
1412 | static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { |
1413 | .name = "mailbox", | |
1414 | .sysc = &omap3xxx_mailbox_sysc, | |
1ac6d46e TV |
1415 | }; |
1416 | ||
844a3b63 PW |
1417 | static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { |
1418 | { .irq = 26 }, | |
1419 | { .irq = -1 } | |
e04d9e1e SG |
1420 | }; |
1421 | ||
844a3b63 PW |
1422 | static struct omap_hwmod omap3xxx_mailbox_hwmod = { |
1423 | .name = "mailbox", | |
1424 | .class = &omap3xxx_mailbox_hwmod_class, | |
1425 | .mpu_irqs = omap3xxx_mailbox_irqs, | |
1426 | .main_clk = "mailboxes_ick", | |
e04d9e1e SG |
1427 | .prcm = { |
1428 | .omap2 = { | |
1429 | .prcm_reg_id = 1, | |
844a3b63 PW |
1430 | .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, |
1431 | .module_offs = CORE_MOD, | |
1432 | .idlest_reg_id = 1, | |
1433 | .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, | |
e04d9e1e SG |
1434 | }, |
1435 | }, | |
e04d9e1e SG |
1436 | }; |
1437 | ||
1438 | /* | |
844a3b63 PW |
1439 | * 'mcspi' class |
1440 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
1441 | * bus | |
e04d9e1e SG |
1442 | */ |
1443 | ||
844a3b63 PW |
1444 | static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { |
1445 | .rev_offs = 0x0000, | |
1446 | .sysc_offs = 0x0010, | |
1447 | .syss_offs = 0x0014, | |
1448 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1449 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1450 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1451 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1452 | .sysc_fields = &omap_hwmod_sysc_type1, | |
e04d9e1e SG |
1453 | }; |
1454 | ||
844a3b63 PW |
1455 | static struct omap_hwmod_class omap34xx_mcspi_class = { |
1456 | .name = "mcspi", | |
1457 | .sysc = &omap34xx_mcspi_sysc, | |
1458 | .rev = OMAP3_MCSPI_REV, | |
affe360d | 1459 | }; |
1460 | ||
844a3b63 PW |
1461 | /* mcspi1 */ |
1462 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { | |
1463 | .num_chipselect = 4, | |
e04d9e1e SG |
1464 | }; |
1465 | ||
844a3b63 PW |
1466 | static struct omap_hwmod omap34xx_mcspi1 = { |
1467 | .name = "mcspi1", | |
1468 | .mpu_irqs = omap2_mcspi1_mpu_irqs, | |
1469 | .sdma_reqs = omap2_mcspi1_sdma_reqs, | |
1470 | .main_clk = "mcspi1_fck", | |
1471 | .prcm = { | |
e04d9e1e | 1472 | .omap2 = { |
844a3b63 PW |
1473 | .module_offs = CORE_MOD, |
1474 | .prcm_reg_id = 1, | |
1475 | .module_bit = OMAP3430_EN_MCSPI1_SHIFT, | |
1476 | .idlest_reg_id = 1, | |
1477 | .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, | |
1478 | }, | |
e04d9e1e | 1479 | }, |
844a3b63 PW |
1480 | .class = &omap34xx_mcspi_class, |
1481 | .dev_attr = &omap_mcspi1_dev_attr, | |
e04d9e1e SG |
1482 | }; |
1483 | ||
844a3b63 PW |
1484 | /* mcspi2 */ |
1485 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { | |
1486 | .num_chipselect = 2, | |
6c3d7e34 TV |
1487 | }; |
1488 | ||
844a3b63 PW |
1489 | static struct omap_hwmod omap34xx_mcspi2 = { |
1490 | .name = "mcspi2", | |
1491 | .mpu_irqs = omap2_mcspi2_mpu_irqs, | |
1492 | .sdma_reqs = omap2_mcspi2_sdma_reqs, | |
1493 | .main_clk = "mcspi2_fck", | |
e04d9e1e SG |
1494 | .prcm = { |
1495 | .omap2 = { | |
844a3b63 | 1496 | .module_offs = CORE_MOD, |
e04d9e1e | 1497 | .prcm_reg_id = 1, |
844a3b63 PW |
1498 | .module_bit = OMAP3430_EN_MCSPI2_SHIFT, |
1499 | .idlest_reg_id = 1, | |
1500 | .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, | |
e04d9e1e SG |
1501 | }, |
1502 | }, | |
844a3b63 PW |
1503 | .class = &omap34xx_mcspi_class, |
1504 | .dev_attr = &omap_mcspi2_dev_attr, | |
e04d9e1e SG |
1505 | }; |
1506 | ||
844a3b63 PW |
1507 | /* mcspi3 */ |
1508 | static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { | |
1509 | { .name = "irq", .irq = 91 }, /* 91 */ | |
1510 | { .irq = -1 } | |
1511 | }; | |
1512 | ||
1513 | static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { | |
1514 | { .name = "tx0", .dma_req = 15 }, | |
1515 | { .name = "rx0", .dma_req = 16 }, | |
1516 | { .name = "tx1", .dma_req = 23 }, | |
1517 | { .name = "rx1", .dma_req = 24 }, | |
1518 | { .dma_req = -1 } | |
e04d9e1e SG |
1519 | }; |
1520 | ||
844a3b63 PW |
1521 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { |
1522 | .num_chipselect = 2, | |
6c3d7e34 TV |
1523 | }; |
1524 | ||
844a3b63 PW |
1525 | static struct omap_hwmod omap34xx_mcspi3 = { |
1526 | .name = "mcspi3", | |
1527 | .mpu_irqs = omap34xx_mcspi3_mpu_irqs, | |
1528 | .sdma_reqs = omap34xx_mcspi3_sdma_reqs, | |
1529 | .main_clk = "mcspi3_fck", | |
e04d9e1e SG |
1530 | .prcm = { |
1531 | .omap2 = { | |
844a3b63 | 1532 | .module_offs = CORE_MOD, |
e04d9e1e | 1533 | .prcm_reg_id = 1, |
844a3b63 PW |
1534 | .module_bit = OMAP3430_EN_MCSPI3_SHIFT, |
1535 | .idlest_reg_id = 1, | |
1536 | .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, | |
e04d9e1e SG |
1537 | }, |
1538 | }, | |
844a3b63 PW |
1539 | .class = &omap34xx_mcspi_class, |
1540 | .dev_attr = &omap_mcspi3_dev_attr, | |
e04d9e1e SG |
1541 | }; |
1542 | ||
844a3b63 PW |
1543 | /* mcspi4 */ |
1544 | static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { | |
1545 | { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ | |
1546 | { .irq = -1 } | |
e04d9e1e SG |
1547 | }; |
1548 | ||
844a3b63 PW |
1549 | static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { |
1550 | { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ | |
1551 | { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ | |
1552 | { .dma_req = -1 } | |
6c3d7e34 TV |
1553 | }; |
1554 | ||
844a3b63 PW |
1555 | static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { |
1556 | .num_chipselect = 1, | |
1557 | }; | |
1558 | ||
1559 | static struct omap_hwmod omap34xx_mcspi4 = { | |
1560 | .name = "mcspi4", | |
1561 | .mpu_irqs = omap34xx_mcspi4_mpu_irqs, | |
1562 | .sdma_reqs = omap34xx_mcspi4_sdma_reqs, | |
1563 | .main_clk = "mcspi4_fck", | |
e04d9e1e SG |
1564 | .prcm = { |
1565 | .omap2 = { | |
844a3b63 | 1566 | .module_offs = CORE_MOD, |
e04d9e1e | 1567 | .prcm_reg_id = 1, |
844a3b63 PW |
1568 | .module_bit = OMAP3430_EN_MCSPI4_SHIFT, |
1569 | .idlest_reg_id = 1, | |
1570 | .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, | |
e04d9e1e SG |
1571 | }, |
1572 | }, | |
844a3b63 PW |
1573 | .class = &omap34xx_mcspi_class, |
1574 | .dev_attr = &omap_mcspi4_dev_attr, | |
e04d9e1e SG |
1575 | }; |
1576 | ||
844a3b63 PW |
1577 | /* usbhsotg */ |
1578 | static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { | |
1579 | .rev_offs = 0x0400, | |
1580 | .sysc_offs = 0x0404, | |
1581 | .syss_offs = 0x0408, | |
1582 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| | |
1583 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1584 | SYSC_HAS_AUTOIDLE), | |
1585 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1586 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1587 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1588 | }; | |
4fe20e97 | 1589 | |
844a3b63 PW |
1590 | static struct omap_hwmod_class usbotg_class = { |
1591 | .name = "usbotg", | |
1592 | .sysc = &omap3xxx_usbhsotg_sysc, | |
4fe20e97 RN |
1593 | }; |
1594 | ||
844a3b63 PW |
1595 | /* usb_otg_hs */ |
1596 | static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { | |
1597 | ||
1598 | { .name = "mc", .irq = 92 }, | |
1599 | { .name = "dma", .irq = 93 }, | |
1600 | { .irq = -1 } | |
1601 | }; | |
1602 | ||
1603 | static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { | |
1604 | .name = "usb_otg_hs", | |
1605 | .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, | |
1606 | .main_clk = "hsotgusb_ick", | |
4fe20e97 RN |
1607 | .prcm = { |
1608 | .omap2 = { | |
4fe20e97 | 1609 | .prcm_reg_id = 1, |
844a3b63 PW |
1610 | .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, |
1611 | .module_offs = CORE_MOD, | |
4fe20e97 | 1612 | .idlest_reg_id = 1, |
844a3b63 PW |
1613 | .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, |
1614 | .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT | |
4fe20e97 RN |
1615 | }, |
1616 | }, | |
844a3b63 PW |
1617 | .class = &usbotg_class, |
1618 | ||
1619 | /* | |
1620 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially | |
1621 | * broken when autoidle is enabled | |
1622 | * workaround is to disable the autoidle bit at module level. | |
1623 | */ | |
1624 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | |
1625 | | HWMOD_SWSUP_MSTANDBY, | |
4fe20e97 RN |
1626 | }; |
1627 | ||
844a3b63 PW |
1628 | /* usb_otg_hs */ |
1629 | static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { | |
4fe20e97 | 1630 | |
844a3b63 PW |
1631 | { .name = "mc", .irq = 71 }, |
1632 | { .irq = -1 } | |
4fe20e97 RN |
1633 | }; |
1634 | ||
844a3b63 PW |
1635 | static struct omap_hwmod_class am35xx_usbotg_class = { |
1636 | .name = "am35xx_usbotg", | |
1637 | .sysc = NULL, | |
1638 | }; | |
1639 | ||
1640 | static struct omap_hwmod am35xx_usbhsotg_hwmod = { | |
1641 | .name = "am35x_otg_hs", | |
1642 | .mpu_irqs = am35xx_usbhsotg_mpu_irqs, | |
1643 | .main_clk = NULL, | |
1644 | .prcm = { | |
4fe20e97 | 1645 | .omap2 = { |
4fe20e97 RN |
1646 | }, |
1647 | }, | |
844a3b63 | 1648 | .class = &am35xx_usbotg_class, |
4fe20e97 RN |
1649 | }; |
1650 | ||
844a3b63 PW |
1651 | /* MMC/SD/SDIO common */ |
1652 | static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { | |
1653 | .rev_offs = 0x1fc, | |
1654 | .sysc_offs = 0x10, | |
1655 | .syss_offs = 0x14, | |
1656 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1657 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1658 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1659 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1660 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1661 | }; | |
4fe20e97 | 1662 | |
844a3b63 PW |
1663 | static struct omap_hwmod_class omap34xx_mmc_class = { |
1664 | .name = "mmc", | |
1665 | .sysc = &omap34xx_mmc_sysc, | |
4fe20e97 RN |
1666 | }; |
1667 | ||
844a3b63 PW |
1668 | /* MMC/SD/SDIO1 */ |
1669 | ||
1670 | static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { | |
1671 | { .irq = 83, }, | |
212738a4 | 1672 | { .irq = -1 } |
4fe20e97 RN |
1673 | }; |
1674 | ||
844a3b63 PW |
1675 | static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { |
1676 | { .name = "tx", .dma_req = 61, }, | |
1677 | { .name = "rx", .dma_req = 62, }, | |
bc614958 | 1678 | { .dma_req = -1 } |
4fe20e97 RN |
1679 | }; |
1680 | ||
844a3b63 PW |
1681 | static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { |
1682 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
1683 | }; | |
1684 | ||
1685 | static struct omap_mmc_dev_attr mmc1_dev_attr = { | |
1686 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
1687 | }; | |
1688 | ||
1689 | /* See 35xx errata 2.1.1.128 in SPRZ278F */ | |
1690 | static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = { | |
1691 | .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | | |
1692 | OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), | |
1693 | }; | |
1694 | ||
1695 | static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { | |
1696 | .name = "mmc1", | |
1697 | .mpu_irqs = omap34xx_mmc1_mpu_irqs, | |
1698 | .sdma_reqs = omap34xx_mmc1_sdma_reqs, | |
1699 | .opt_clks = omap34xx_mmc1_opt_clks, | |
1700 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), | |
1701 | .main_clk = "mmchs1_fck", | |
4fe20e97 RN |
1702 | .prcm = { |
1703 | .omap2 = { | |
1704 | .module_offs = CORE_MOD, | |
1705 | .prcm_reg_id = 1, | |
844a3b63 | 1706 | .module_bit = OMAP3430_EN_MMC1_SHIFT, |
4fe20e97 | 1707 | .idlest_reg_id = 1, |
844a3b63 | 1708 | .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, |
4fe20e97 RN |
1709 | }, |
1710 | }, | |
844a3b63 PW |
1711 | .dev_attr = &mmc1_pre_es3_dev_attr, |
1712 | .class = &omap34xx_mmc_class, | |
4fe20e97 RN |
1713 | }; |
1714 | ||
844a3b63 PW |
1715 | static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { |
1716 | .name = "mmc1", | |
1717 | .mpu_irqs = omap34xx_mmc1_mpu_irqs, | |
1718 | .sdma_reqs = omap34xx_mmc1_sdma_reqs, | |
1719 | .opt_clks = omap34xx_mmc1_opt_clks, | |
1720 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), | |
1721 | .main_clk = "mmchs1_fck", | |
1722 | .prcm = { | |
1723 | .omap2 = { | |
1724 | .module_offs = CORE_MOD, | |
1725 | .prcm_reg_id = 1, | |
1726 | .module_bit = OMAP3430_EN_MMC1_SHIFT, | |
1727 | .idlest_reg_id = 1, | |
1728 | .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, | |
1729 | }, | |
70034d38 | 1730 | }, |
844a3b63 PW |
1731 | .dev_attr = &mmc1_dev_attr, |
1732 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1733 | }; |
1734 | ||
844a3b63 | 1735 | /* MMC/SD/SDIO2 */ |
70034d38 | 1736 | |
844a3b63 PW |
1737 | static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { |
1738 | { .irq = INT_24XX_MMC2_IRQ, }, | |
1739 | { .irq = -1 } | |
70034d38 VC |
1740 | }; |
1741 | ||
844a3b63 PW |
1742 | static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { |
1743 | { .name = "tx", .dma_req = 47, }, | |
1744 | { .name = "rx", .dma_req = 48, }, | |
1745 | { .dma_req = -1 } | |
70034d38 VC |
1746 | }; |
1747 | ||
844a3b63 PW |
1748 | static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { |
1749 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
70034d38 VC |
1750 | }; |
1751 | ||
844a3b63 PW |
1752 | /* See 35xx errata 2.1.1.128 in SPRZ278F */ |
1753 | static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = { | |
1754 | .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, | |
70034d38 VC |
1755 | }; |
1756 | ||
844a3b63 PW |
1757 | static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { |
1758 | .name = "mmc2", | |
1759 | .mpu_irqs = omap34xx_mmc2_mpu_irqs, | |
1760 | .sdma_reqs = omap34xx_mmc2_sdma_reqs, | |
1761 | .opt_clks = omap34xx_mmc2_opt_clks, | |
1762 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), | |
1763 | .main_clk = "mmchs2_fck", | |
1764 | .prcm = { | |
1765 | .omap2 = { | |
1766 | .module_offs = CORE_MOD, | |
1767 | .prcm_reg_id = 1, | |
1768 | .module_bit = OMAP3430_EN_MMC2_SHIFT, | |
1769 | .idlest_reg_id = 1, | |
1770 | .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, | |
1771 | }, | |
70034d38 | 1772 | }, |
844a3b63 PW |
1773 | .dev_attr = &mmc2_pre_es3_dev_attr, |
1774 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1775 | }; |
1776 | ||
844a3b63 PW |
1777 | static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { |
1778 | .name = "mmc2", | |
1779 | .mpu_irqs = omap34xx_mmc2_mpu_irqs, | |
1780 | .sdma_reqs = omap34xx_mmc2_sdma_reqs, | |
1781 | .opt_clks = omap34xx_mmc2_opt_clks, | |
1782 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), | |
1783 | .main_clk = "mmchs2_fck", | |
1784 | .prcm = { | |
1785 | .omap2 = { | |
1786 | .module_offs = CORE_MOD, | |
1787 | .prcm_reg_id = 1, | |
1788 | .module_bit = OMAP3430_EN_MMC2_SHIFT, | |
1789 | .idlest_reg_id = 1, | |
1790 | .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, | |
1791 | }, | |
1792 | }, | |
1793 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1794 | }; |
1795 | ||
844a3b63 PW |
1796 | /* MMC/SD/SDIO3 */ |
1797 | ||
1798 | static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { | |
1799 | { .irq = 94, }, | |
1800 | { .irq = -1 } | |
70034d38 VC |
1801 | }; |
1802 | ||
844a3b63 PW |
1803 | static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { |
1804 | { .name = "tx", .dma_req = 77, }, | |
1805 | { .name = "rx", .dma_req = 78, }, | |
1806 | { .dma_req = -1 } | |
70034d38 VC |
1807 | }; |
1808 | ||
844a3b63 PW |
1809 | static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { |
1810 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
70034d38 VC |
1811 | }; |
1812 | ||
844a3b63 PW |
1813 | static struct omap_hwmod omap3xxx_mmc3_hwmod = { |
1814 | .name = "mmc3", | |
1815 | .mpu_irqs = omap34xx_mmc3_mpu_irqs, | |
1816 | .sdma_reqs = omap34xx_mmc3_sdma_reqs, | |
1817 | .opt_clks = omap34xx_mmc3_opt_clks, | |
1818 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), | |
1819 | .main_clk = "mmchs3_fck", | |
1820 | .prcm = { | |
1821 | .omap2 = { | |
1822 | .prcm_reg_id = 1, | |
1823 | .module_bit = OMAP3430_EN_MMC3_SHIFT, | |
1824 | .idlest_reg_id = 1, | |
1825 | .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, | |
1826 | }, | |
1827 | }, | |
1828 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1829 | }; |
1830 | ||
1831 | /* | |
844a3b63 PW |
1832 | * 'usb_host_hs' class |
1833 | * high-speed multi-port usb host controller | |
70034d38 VC |
1834 | */ |
1835 | ||
844a3b63 | 1836 | static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { |
70034d38 VC |
1837 | .rev_offs = 0x0000, |
1838 | .sysc_offs = 0x0010, | |
1839 | .syss_offs = 0x0014, | |
844a3b63 PW |
1840 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | |
1841 | SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
1842 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1843 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1844 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1845 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1846 | }; |
1847 | ||
844a3b63 PW |
1848 | static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { |
1849 | .name = "usb_host_hs", | |
1850 | .sysc = &omap3xxx_usb_host_hs_sysc, | |
70034d38 VC |
1851 | }; |
1852 | ||
844a3b63 PW |
1853 | static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { |
1854 | { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", }, | |
70034d38 VC |
1855 | }; |
1856 | ||
844a3b63 PW |
1857 | static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = { |
1858 | { .name = "ohci-irq", .irq = 76 }, | |
1859 | { .name = "ehci-irq", .irq = 77 }, | |
1860 | { .irq = -1 } | |
70034d38 VC |
1861 | }; |
1862 | ||
844a3b63 PW |
1863 | static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { |
1864 | .name = "usb_host_hs", | |
1865 | .class = &omap3xxx_usb_host_hs_hwmod_class, | |
1866 | .clkdm_name = "l3_init_clkdm", | |
1867 | .mpu_irqs = omap3xxx_usb_host_hs_irqs, | |
1868 | .main_clk = "usbhost_48m_fck", | |
1869 | .prcm = { | |
70034d38 | 1870 | .omap2 = { |
844a3b63 | 1871 | .module_offs = OMAP3430ES2_USBHOST_MOD, |
70034d38 | 1872 | .prcm_reg_id = 1, |
844a3b63 | 1873 | .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, |
70034d38 | 1874 | .idlest_reg_id = 1, |
844a3b63 PW |
1875 | .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, |
1876 | .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT, | |
70034d38 VC |
1877 | }, |
1878 | }, | |
844a3b63 PW |
1879 | .opt_clks = omap3xxx_usb_host_hs_opt_clks, |
1880 | .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks), | |
70034d38 | 1881 | |
844a3b63 PW |
1882 | /* |
1883 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
1884 | * id: i660 | |
1885 | * | |
1886 | * Description: | |
1887 | * In the following configuration : | |
1888 | * - USBHOST module is set to smart-idle mode | |
1889 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
1890 | * happens when the system is going to a low power mode : all ports | |
1891 | * have been suspended, the master part of the USBHOST module has | |
1892 | * entered the standby state, and SW has cut the functional clocks) | |
1893 | * - an USBHOST interrupt occurs before the module is able to answer | |
1894 | * idle_ack, typically a remote wakeup IRQ. | |
1895 | * Then the USB HOST module will enter a deadlock situation where it | |
1896 | * is no more accessible nor functional. | |
1897 | * | |
1898 | * Workaround: | |
1899 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
1900 | */ | |
1901 | ||
1902 | /* | |
1903 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
1904 | * Id: i571 | |
1905 | * | |
1906 | * Description: | |
1907 | * When the USBHOST module is set to smart-standby mode, and when it is | |
1908 | * ready to enter the standby state (i.e. all ports are suspended and | |
1909 | * all attached devices are in suspend mode), then it can wrongly assert | |
1910 | * the Mstandby signal too early while there are still some residual OCP | |
1911 | * transactions ongoing. If this condition occurs, the internal state | |
1912 | * machine may go to an undefined state and the USB link may be stuck | |
1913 | * upon the next resume. | |
1914 | * | |
1915 | * Workaround: | |
1916 | * Don't use smart standby; use only force standby, | |
1917 | * hence HWMOD_SWSUP_MSTANDBY | |
1918 | */ | |
1919 | ||
1920 | /* | |
1921 | * During system boot; If the hwmod framework resets the module | |
1922 | * the module will have smart idle settings; which can lead to deadlock | |
1923 | * (above Errata Id:i660); so, dont reset the module during boot; | |
1924 | * Use HWMOD_INIT_NO_RESET. | |
1925 | */ | |
70034d38 | 1926 | |
844a3b63 PW |
1927 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | |
1928 | HWMOD_INIT_NO_RESET, | |
70034d38 VC |
1929 | }; |
1930 | ||
844a3b63 PW |
1931 | /* |
1932 | * 'usb_tll_hs' class | |
1933 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
1934 | */ | |
1935 | static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = { | |
1936 | .rev_offs = 0x0000, | |
1937 | .sysc_offs = 0x0010, | |
1938 | .syss_offs = 0x0014, | |
1939 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1940 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1941 | SYSC_HAS_AUTOIDLE), | |
1942 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1943 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1944 | }; |
1945 | ||
844a3b63 PW |
1946 | static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { |
1947 | .name = "usb_tll_hs", | |
1948 | .sysc = &omap3xxx_usb_tll_hs_sysc, | |
70034d38 VC |
1949 | }; |
1950 | ||
844a3b63 PW |
1951 | static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { |
1952 | { .name = "tll-irq", .irq = 78 }, | |
1953 | { .irq = -1 } | |
70034d38 VC |
1954 | }; |
1955 | ||
844a3b63 PW |
1956 | static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { |
1957 | .name = "usb_tll_hs", | |
1958 | .class = &omap3xxx_usb_tll_hs_hwmod_class, | |
1959 | .clkdm_name = "l3_init_clkdm", | |
1960 | .mpu_irqs = omap3xxx_usb_tll_hs_irqs, | |
1961 | .main_clk = "usbtll_fck", | |
1962 | .prcm = { | |
70034d38 | 1963 | .omap2 = { |
844a3b63 PW |
1964 | .module_offs = CORE_MOD, |
1965 | .prcm_reg_id = 3, | |
1966 | .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | |
1967 | .idlest_reg_id = 3, | |
1968 | .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, | |
70034d38 VC |
1969 | }, |
1970 | }, | |
70034d38 VC |
1971 | }; |
1972 | ||
844a3b63 PW |
1973 | /* |
1974 | * interfaces | |
1975 | */ | |
1976 | ||
1977 | /* L3 -> L4_CORE interface */ | |
1978 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { | |
1979 | .master = &omap3xxx_l3_main_hwmod, | |
1980 | .slave = &omap3xxx_l4_core_hwmod, | |
1981 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
1982 | }; |
1983 | ||
844a3b63 PW |
1984 | /* L3 -> L4_PER interface */ |
1985 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { | |
1986 | .master = &omap3xxx_l3_main_hwmod, | |
1987 | .slave = &omap3xxx_l4_per_hwmod, | |
1988 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
1989 | }; |
1990 | ||
844a3b63 PW |
1991 | static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { |
1992 | { | |
1993 | .pa_start = 0x68000000, | |
1994 | .pa_end = 0x6800ffff, | |
1995 | .flags = ADDR_TYPE_RT, | |
70034d38 | 1996 | }, |
844a3b63 | 1997 | { } |
70034d38 VC |
1998 | }; |
1999 | ||
844a3b63 PW |
2000 | /* MPU -> L3 interface */ |
2001 | static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { | |
2002 | .master = &omap3xxx_mpu_hwmod, | |
2003 | .slave = &omap3xxx_l3_main_hwmod, | |
2004 | .addr = omap3xxx_l3_main_addrs, | |
2005 | .user = OCP_USER_MPU, | |
70034d38 VC |
2006 | }; |
2007 | ||
844a3b63 PW |
2008 | /* DSS -> l3 */ |
2009 | static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = { | |
2010 | .master = &omap3430es1_dss_core_hwmod, | |
2011 | .slave = &omap3xxx_l3_main_hwmod, | |
2012 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2013 | }; |
2014 | ||
844a3b63 PW |
2015 | static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { |
2016 | .master = &omap3xxx_dss_core_hwmod, | |
2017 | .slave = &omap3xxx_l3_main_hwmod, | |
2018 | .fw = { | |
70034d38 | 2019 | .omap2 = { |
844a3b63 PW |
2020 | .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, |
2021 | .flags = OMAP_FIREWALL_L3, | |
2022 | } | |
70034d38 | 2023 | }, |
844a3b63 | 2024 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2025 | }; |
2026 | ||
844a3b63 PW |
2027 | /* l3_core -> usbhsotg interface */ |
2028 | static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { | |
2029 | .master = &omap3xxx_usbhsotg_hwmod, | |
01438ab6 MK |
2030 | .slave = &omap3xxx_l3_main_hwmod, |
2031 | .clk = "core_l3_ick", | |
844a3b63 | 2032 | .user = OCP_USER_MPU, |
01438ab6 MK |
2033 | }; |
2034 | ||
844a3b63 PW |
2035 | /* l3_core -> am35xx_usbhsotg interface */ |
2036 | static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { | |
2037 | .master = &am35xx_usbhsotg_hwmod, | |
2038 | .slave = &omap3xxx_l3_main_hwmod, | |
2039 | .clk = "core_l3_ick", | |
2040 | .user = OCP_USER_MPU, | |
01438ab6 | 2041 | }; |
844a3b63 PW |
2042 | /* L4_CORE -> L4_WKUP interface */ |
2043 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { | |
2044 | .master = &omap3xxx_l4_core_hwmod, | |
2045 | .slave = &omap3xxx_l4_wkup_hwmod, | |
2046 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2047 | }; |
2048 | ||
844a3b63 PW |
2049 | /* L4 CORE -> MMC1 interface */ |
2050 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = { | |
01438ab6 | 2051 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2052 | .slave = &omap3xxx_pre_es3_mmc1_hwmod, |
2053 | .clk = "mmchs1_ick", | |
2054 | .addr = omap2430_mmc1_addr_space, | |
01438ab6 | 2055 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 | 2056 | .flags = OMAP_FIREWALL_L4 |
01438ab6 MK |
2057 | }; |
2058 | ||
844a3b63 PW |
2059 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = { |
2060 | .master = &omap3xxx_l4_core_hwmod, | |
2061 | .slave = &omap3xxx_es3plus_mmc1_hwmod, | |
2062 | .clk = "mmchs1_ick", | |
2063 | .addr = omap2430_mmc1_addr_space, | |
2064 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2065 | .flags = OMAP_FIREWALL_L4 | |
01438ab6 MK |
2066 | }; |
2067 | ||
844a3b63 PW |
2068 | /* L4 CORE -> MMC2 interface */ |
2069 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = { | |
2070 | .master = &omap3xxx_l4_core_hwmod, | |
2071 | .slave = &omap3xxx_pre_es3_mmc2_hwmod, | |
2072 | .clk = "mmchs2_ick", | |
2073 | .addr = omap2430_mmc2_addr_space, | |
2074 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2075 | .flags = OMAP_FIREWALL_L4 | |
2076 | }; | |
70034d38 | 2077 | |
844a3b63 PW |
2078 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = { |
2079 | .master = &omap3xxx_l4_core_hwmod, | |
2080 | .slave = &omap3xxx_es3plus_mmc2_hwmod, | |
2081 | .clk = "mmchs2_ick", | |
2082 | .addr = omap2430_mmc2_addr_space, | |
2083 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2084 | .flags = OMAP_FIREWALL_L4 | |
70034d38 VC |
2085 | }; |
2086 | ||
844a3b63 PW |
2087 | /* L4 CORE -> MMC3 interface */ |
2088 | static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { | |
2089 | { | |
2090 | .pa_start = 0x480ad000, | |
2091 | .pa_end = 0x480ad1ff, | |
2092 | .flags = ADDR_TYPE_RT, | |
2093 | }, | |
2094 | { } | |
70034d38 VC |
2095 | }; |
2096 | ||
844a3b63 PW |
2097 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { |
2098 | .master = &omap3xxx_l4_core_hwmod, | |
2099 | .slave = &omap3xxx_mmc3_hwmod, | |
2100 | .clk = "mmchs3_ick", | |
2101 | .addr = omap3xxx_mmc3_addr_space, | |
2102 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2103 | .flags = OMAP_FIREWALL_L4 | |
70034d38 VC |
2104 | }; |
2105 | ||
844a3b63 PW |
2106 | /* L4 CORE -> UART1 interface */ |
2107 | static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { | |
dc48e5fc | 2108 | { |
844a3b63 PW |
2109 | .pa_start = OMAP3_UART1_BASE, |
2110 | .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, | |
2111 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
dc48e5fc | 2112 | }, |
78183f3f | 2113 | { } |
70034d38 VC |
2114 | }; |
2115 | ||
844a3b63 | 2116 | static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { |
dc48e5fc | 2117 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2118 | .slave = &omap3xxx_uart1_hwmod, |
2119 | .clk = "uart1_ick", | |
2120 | .addr = omap3xxx_uart1_addr_space, | |
dc48e5fc | 2121 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2122 | }; |
2123 | ||
844a3b63 PW |
2124 | /* L4 CORE -> UART2 interface */ |
2125 | static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { | |
2126 | { | |
2127 | .pa_start = OMAP3_UART2_BASE, | |
2128 | .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, | |
2129 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2130 | }, |
844a3b63 | 2131 | { } |
70034d38 VC |
2132 | }; |
2133 | ||
844a3b63 PW |
2134 | static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { |
2135 | .master = &omap3xxx_l4_core_hwmod, | |
2136 | .slave = &omap3xxx_uart2_hwmod, | |
2137 | .clk = "uart2_ick", | |
2138 | .addr = omap3xxx_uart2_addr_space, | |
2139 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2140 | }; |
2141 | ||
844a3b63 PW |
2142 | /* L4 PER -> UART3 interface */ |
2143 | static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { | |
dc48e5fc | 2144 | { |
844a3b63 PW |
2145 | .pa_start = OMAP3_UART3_BASE, |
2146 | .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, | |
2147 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2148 | }, |
78183f3f | 2149 | { } |
70034d38 VC |
2150 | }; |
2151 | ||
844a3b63 | 2152 | static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { |
dc48e5fc | 2153 | .master = &omap3xxx_l4_per_hwmod, |
844a3b63 PW |
2154 | .slave = &omap3xxx_uart3_hwmod, |
2155 | .clk = "uart3_ick", | |
2156 | .addr = omap3xxx_uart3_addr_space, | |
dc48e5fc | 2157 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2158 | }; |
2159 | ||
844a3b63 PW |
2160 | /* L4 PER -> UART4 interface */ |
2161 | static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = { | |
2162 | { | |
2163 | .pa_start = OMAP3_UART4_BASE, | |
2164 | .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, | |
2165 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2166 | }, |
844a3b63 | 2167 | { } |
70034d38 VC |
2168 | }; |
2169 | ||
844a3b63 PW |
2170 | static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { |
2171 | .master = &omap3xxx_l4_per_hwmod, | |
2172 | .slave = &omap36xx_uart4_hwmod, | |
2173 | .clk = "uart4_ick", | |
2174 | .addr = omap36xx_uart4_addr_space, | |
2175 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2176 | }; |
2177 | ||
844a3b63 PW |
2178 | /* AM35xx: L4 CORE -> UART4 interface */ |
2179 | static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { | |
dc48e5fc | 2180 | { |
844a3b63 PW |
2181 | .pa_start = OMAP3_UART4_AM35XX_BASE, |
2182 | .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, | |
2183 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
dc48e5fc | 2184 | }, |
70034d38 VC |
2185 | }; |
2186 | ||
844a3b63 PW |
2187 | static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { |
2188 | .master = &omap3xxx_l4_core_hwmod, | |
2189 | .slave = &am35xx_uart4_hwmod, | |
2190 | .clk = "uart4_ick", | |
2191 | .addr = am35xx_uart4_addr_space, | |
dc48e5fc C |
2192 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2193 | }; | |
2194 | ||
844a3b63 PW |
2195 | /* L4 CORE -> I2C1 interface */ |
2196 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { | |
2197 | .master = &omap3xxx_l4_core_hwmod, | |
2198 | .slave = &omap3xxx_i2c1_hwmod, | |
2199 | .clk = "i2c1_ick", | |
2200 | .addr = omap2_i2c1_addr_space, | |
2201 | .fw = { | |
2202 | .omap2 = { | |
2203 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, | |
2204 | .l4_prot_group = 7, | |
2205 | .flags = OMAP_FIREWALL_L4, | |
2206 | } | |
2207 | }, | |
2208 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
8b1906f1 KVA |
2209 | }; |
2210 | ||
844a3b63 PW |
2211 | /* L4 CORE -> I2C2 interface */ |
2212 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { | |
2213 | .master = &omap3xxx_l4_core_hwmod, | |
2214 | .slave = &omap3xxx_i2c2_hwmod, | |
2215 | .clk = "i2c2_ick", | |
2216 | .addr = omap2_i2c2_addr_space, | |
2217 | .fw = { | |
70034d38 | 2218 | .omap2 = { |
844a3b63 PW |
2219 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, |
2220 | .l4_prot_group = 7, | |
2221 | .flags = OMAP_FIREWALL_L4, | |
2222 | } | |
70034d38 | 2223 | }, |
844a3b63 | 2224 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2225 | }; |
2226 | ||
844a3b63 PW |
2227 | /* L4 CORE -> I2C3 interface */ |
2228 | static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { | |
2229 | { | |
2230 | .pa_start = 0x48060000, | |
2231 | .pa_end = 0x48060000 + SZ_128 - 1, | |
2232 | .flags = ADDR_TYPE_RT, | |
2233 | }, | |
2234 | { } | |
70034d38 VC |
2235 | }; |
2236 | ||
844a3b63 PW |
2237 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { |
2238 | .master = &omap3xxx_l4_core_hwmod, | |
2239 | .slave = &omap3xxx_i2c3_hwmod, | |
2240 | .clk = "i2c3_ick", | |
2241 | .addr = omap3xxx_i2c3_addr_space, | |
2242 | .fw = { | |
2243 | .omap2 = { | |
2244 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, | |
2245 | .l4_prot_group = 7, | |
2246 | .flags = OMAP_FIREWALL_L4, | |
2247 | } | |
2248 | }, | |
2249 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2250 | }; |
2251 | ||
844a3b63 PW |
2252 | /* L4 CORE -> SR1 interface */ |
2253 | static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { | |
dc48e5fc | 2254 | { |
844a3b63 PW |
2255 | .pa_start = OMAP34XX_SR1_BASE, |
2256 | .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, | |
2257 | .flags = ADDR_TYPE_RT, | |
dc48e5fc | 2258 | }, |
78183f3f | 2259 | { } |
70034d38 VC |
2260 | }; |
2261 | ||
844a3b63 PW |
2262 | static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { |
2263 | .master = &omap3xxx_l4_core_hwmod, | |
2264 | .slave = &omap34xx_sr1_hwmod, | |
2265 | .clk = "sr_l4_ick", | |
2266 | .addr = omap3_sr1_addr_space, | |
2267 | .user = OCP_USER_MPU, | |
70034d38 VC |
2268 | }; |
2269 | ||
844a3b63 PW |
2270 | static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = { |
2271 | .master = &omap3xxx_l4_core_hwmod, | |
2272 | .slave = &omap36xx_sr1_hwmod, | |
2273 | .clk = "sr_l4_ick", | |
2274 | .addr = omap3_sr1_addr_space, | |
2275 | .user = OCP_USER_MPU, | |
2276 | }; | |
2277 | ||
2278 | /* L4 CORE -> SR1 interface */ | |
2279 | static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { | |
2280 | { | |
2281 | .pa_start = OMAP34XX_SR2_BASE, | |
2282 | .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, | |
2283 | .flags = ADDR_TYPE_RT, | |
70034d38 | 2284 | }, |
844a3b63 | 2285 | { } |
70034d38 VC |
2286 | }; |
2287 | ||
844a3b63 PW |
2288 | static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { |
2289 | .master = &omap3xxx_l4_core_hwmod, | |
2290 | .slave = &omap34xx_sr2_hwmod, | |
2291 | .clk = "sr_l4_ick", | |
2292 | .addr = omap3_sr2_addr_space, | |
2293 | .user = OCP_USER_MPU, | |
70034d38 VC |
2294 | }; |
2295 | ||
844a3b63 PW |
2296 | static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = { |
2297 | .master = &omap3xxx_l4_core_hwmod, | |
2298 | .slave = &omap36xx_sr2_hwmod, | |
2299 | .clk = "sr_l4_ick", | |
2300 | .addr = omap3_sr2_addr_space, | |
2301 | .user = OCP_USER_MPU, | |
70034d38 VC |
2302 | }; |
2303 | ||
844a3b63 | 2304 | static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { |
dc48e5fc | 2305 | { |
844a3b63 PW |
2306 | .pa_start = OMAP34XX_HSUSB_OTG_BASE, |
2307 | .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, | |
dc48e5fc C |
2308 | .flags = ADDR_TYPE_RT |
2309 | }, | |
78183f3f | 2310 | { } |
70034d38 VC |
2311 | }; |
2312 | ||
844a3b63 PW |
2313 | /* l4_core -> usbhsotg */ |
2314 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { | |
dc48e5fc | 2315 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2316 | .slave = &omap3xxx_usbhsotg_hwmod, |
2317 | .clk = "l4_ick", | |
2318 | .addr = omap3xxx_usbhsotg_addrs, | |
2319 | .user = OCP_USER_MPU, | |
dc48e5fc C |
2320 | }; |
2321 | ||
844a3b63 PW |
2322 | static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { |
2323 | { | |
2324 | .pa_start = AM35XX_IPSS_USBOTGSS_BASE, | |
2325 | .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, | |
2326 | .flags = ADDR_TYPE_RT | |
70034d38 | 2327 | }, |
844a3b63 | 2328 | { } |
70034d38 VC |
2329 | }; |
2330 | ||
844a3b63 PW |
2331 | /* l4_core -> usbhsotg */ |
2332 | static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { | |
2333 | .master = &omap3xxx_l4_core_hwmod, | |
2334 | .slave = &am35xx_usbhsotg_hwmod, | |
2335 | .clk = "l4_ick", | |
2336 | .addr = am35xx_usbhsotg_addrs, | |
2337 | .user = OCP_USER_MPU, | |
01438ab6 MK |
2338 | }; |
2339 | ||
844a3b63 PW |
2340 | /* L4_WKUP -> L4_SEC interface */ |
2341 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = { | |
2342 | .master = &omap3xxx_l4_wkup_hwmod, | |
2343 | .slave = &omap3xxx_l4_sec_hwmod, | |
2344 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2345 | }; |
2346 | ||
844a3b63 PW |
2347 | /* IVA2 <- L3 interface */ |
2348 | static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { | |
2349 | .master = &omap3xxx_l3_main_hwmod, | |
2350 | .slave = &omap3xxx_iva_hwmod, | |
2351 | .clk = "iva2_ck", | |
2352 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2353 | }; |
2354 | ||
844a3b63 | 2355 | static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { |
dc48e5fc | 2356 | { |
844a3b63 PW |
2357 | .pa_start = 0x48318000, |
2358 | .pa_end = 0x48318000 + SZ_1K - 1, | |
dc48e5fc C |
2359 | .flags = ADDR_TYPE_RT |
2360 | }, | |
78183f3f | 2361 | { } |
01438ab6 MK |
2362 | }; |
2363 | ||
844a3b63 PW |
2364 | /* l4_wkup -> timer1 */ |
2365 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { | |
2366 | .master = &omap3xxx_l4_wkup_hwmod, | |
2367 | .slave = &omap3xxx_timer1_hwmod, | |
2368 | .clk = "gpt1_ick", | |
2369 | .addr = omap3xxx_timer1_addrs, | |
2370 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2371 | }; |
2372 | ||
844a3b63 PW |
2373 | static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { |
2374 | { | |
2375 | .pa_start = 0x49032000, | |
2376 | .pa_end = 0x49032000 + SZ_1K - 1, | |
2377 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2378 | }, |
844a3b63 | 2379 | { } |
01438ab6 MK |
2380 | }; |
2381 | ||
844a3b63 PW |
2382 | /* l4_per -> timer2 */ |
2383 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { | |
2384 | .master = &omap3xxx_l4_per_hwmod, | |
2385 | .slave = &omap3xxx_timer2_hwmod, | |
2386 | .clk = "gpt2_ick", | |
2387 | .addr = omap3xxx_timer2_addrs, | |
2388 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2389 | }; |
2390 | ||
844a3b63 | 2391 | static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { |
dc48e5fc | 2392 | { |
844a3b63 PW |
2393 | .pa_start = 0x49034000, |
2394 | .pa_end = 0x49034000 + SZ_1K - 1, | |
dc48e5fc C |
2395 | .flags = ADDR_TYPE_RT |
2396 | }, | |
78183f3f | 2397 | { } |
01438ab6 MK |
2398 | }; |
2399 | ||
844a3b63 PW |
2400 | /* l4_per -> timer3 */ |
2401 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { | |
dc48e5fc | 2402 | .master = &omap3xxx_l4_per_hwmod, |
844a3b63 PW |
2403 | .slave = &omap3xxx_timer3_hwmod, |
2404 | .clk = "gpt3_ick", | |
2405 | .addr = omap3xxx_timer3_addrs, | |
2406 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2407 | }; |
2408 | ||
844a3b63 PW |
2409 | static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { |
2410 | { | |
2411 | .pa_start = 0x49036000, | |
2412 | .pa_end = 0x49036000 + SZ_1K - 1, | |
2413 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2414 | }, |
844a3b63 | 2415 | { } |
01438ab6 MK |
2416 | }; |
2417 | ||
844a3b63 PW |
2418 | /* l4_per -> timer4 */ |
2419 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { | |
2420 | .master = &omap3xxx_l4_per_hwmod, | |
2421 | .slave = &omap3xxx_timer4_hwmod, | |
2422 | .clk = "gpt4_ick", | |
2423 | .addr = omap3xxx_timer4_addrs, | |
2424 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2425 | }; |
2426 | ||
844a3b63 PW |
2427 | static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { |
2428 | { | |
2429 | .pa_start = 0x49038000, | |
2430 | .pa_end = 0x49038000 + SZ_1K - 1, | |
2431 | .flags = ADDR_TYPE_RT | |
2432 | }, | |
2433 | { } | |
d3442726 TG |
2434 | }; |
2435 | ||
844a3b63 PW |
2436 | /* l4_per -> timer5 */ |
2437 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { | |
2438 | .master = &omap3xxx_l4_per_hwmod, | |
2439 | .slave = &omap3xxx_timer5_hwmod, | |
2440 | .clk = "gpt5_ick", | |
2441 | .addr = omap3xxx_timer5_addrs, | |
2442 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2443 | }; |
2444 | ||
844a3b63 PW |
2445 | static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { |
2446 | { | |
2447 | .pa_start = 0x4903A000, | |
2448 | .pa_end = 0x4903A000 + SZ_1K - 1, | |
2449 | .flags = ADDR_TYPE_RT | |
2450 | }, | |
2451 | { } | |
cea6b942 SG |
2452 | }; |
2453 | ||
844a3b63 PW |
2454 | /* l4_per -> timer6 */ |
2455 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { | |
2456 | .master = &omap3xxx_l4_per_hwmod, | |
2457 | .slave = &omap3xxx_timer6_hwmod, | |
2458 | .clk = "gpt6_ick", | |
2459 | .addr = omap3xxx_timer6_addrs, | |
2460 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2461 | }; |
2462 | ||
844a3b63 PW |
2463 | static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { |
2464 | { | |
2465 | .pa_start = 0x4903C000, | |
2466 | .pa_end = 0x4903C000 + SZ_1K - 1, | |
2467 | .flags = ADDR_TYPE_RT | |
d3442726 | 2468 | }, |
844a3b63 | 2469 | { } |
d3442726 TG |
2470 | }; |
2471 | ||
844a3b63 PW |
2472 | /* l4_per -> timer7 */ |
2473 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { | |
2474 | .master = &omap3xxx_l4_per_hwmod, | |
2475 | .slave = &omap3xxx_timer7_hwmod, | |
2476 | .clk = "gpt7_ick", | |
2477 | .addr = omap3xxx_timer7_addrs, | |
2478 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
cea6b942 SG |
2479 | }; |
2480 | ||
844a3b63 PW |
2481 | static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { |
2482 | { | |
2483 | .pa_start = 0x4903E000, | |
2484 | .pa_end = 0x4903E000 + SZ_1K - 1, | |
2485 | .flags = ADDR_TYPE_RT | |
d3442726 | 2486 | }, |
844a3b63 | 2487 | { } |
d3442726 TG |
2488 | }; |
2489 | ||
844a3b63 PW |
2490 | /* l4_per -> timer8 */ |
2491 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { | |
2492 | .master = &omap3xxx_l4_per_hwmod, | |
2493 | .slave = &omap3xxx_timer8_hwmod, | |
2494 | .clk = "gpt8_ick", | |
2495 | .addr = omap3xxx_timer8_addrs, | |
2496 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2497 | }; |
2498 | ||
844a3b63 PW |
2499 | static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { |
2500 | { | |
2501 | .pa_start = 0x49040000, | |
2502 | .pa_end = 0x49040000 + SZ_1K - 1, | |
2503 | .flags = ADDR_TYPE_RT | |
2504 | }, | |
2505 | { } | |
2506 | }; | |
0f9dfdd3 | 2507 | |
844a3b63 PW |
2508 | /* l4_per -> timer9 */ |
2509 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { | |
2510 | .master = &omap3xxx_l4_per_hwmod, | |
2511 | .slave = &omap3xxx_timer9_hwmod, | |
2512 | .clk = "gpt9_ick", | |
2513 | .addr = omap3xxx_timer9_addrs, | |
2514 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2515 | }; |
2516 | ||
844a3b63 PW |
2517 | /* l4_core -> timer10 */ |
2518 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { | |
2519 | .master = &omap3xxx_l4_core_hwmod, | |
2520 | .slave = &omap3xxx_timer10_hwmod, | |
2521 | .clk = "gpt10_ick", | |
2522 | .addr = omap2_timer10_addrs, | |
2523 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2524 | }; |
2525 | ||
844a3b63 PW |
2526 | /* l4_core -> timer11 */ |
2527 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { | |
2528 | .master = &omap3xxx_l4_core_hwmod, | |
2529 | .slave = &omap3xxx_timer11_hwmod, | |
2530 | .clk = "gpt11_ick", | |
2531 | .addr = omap2_timer11_addrs, | |
2532 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2533 | }; |
2534 | ||
844a3b63 | 2535 | static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { |
0f9dfdd3 | 2536 | { |
844a3b63 PW |
2537 | .pa_start = 0x48304000, |
2538 | .pa_end = 0x48304000 + SZ_1K - 1, | |
2539 | .flags = ADDR_TYPE_RT | |
0f9dfdd3 | 2540 | }, |
78183f3f | 2541 | { } |
0f9dfdd3 FC |
2542 | }; |
2543 | ||
844a3b63 PW |
2544 | /* l4_core -> timer12 */ |
2545 | static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { | |
2546 | .master = &omap3xxx_l4_sec_hwmod, | |
2547 | .slave = &omap3xxx_timer12_hwmod, | |
2548 | .clk = "gpt12_ick", | |
2549 | .addr = omap3xxx_timer12_addrs, | |
0f9dfdd3 FC |
2550 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2551 | }; | |
2552 | ||
844a3b63 PW |
2553 | /* l4_wkup -> wd_timer2 */ |
2554 | static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { | |
2555 | { | |
2556 | .pa_start = 0x48314000, | |
2557 | .pa_end = 0x4831407f, | |
2558 | .flags = ADDR_TYPE_RT | |
0f9dfdd3 | 2559 | }, |
844a3b63 | 2560 | { } |
0f9dfdd3 FC |
2561 | }; |
2562 | ||
844a3b63 PW |
2563 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { |
2564 | .master = &omap3xxx_l4_wkup_hwmod, | |
2565 | .slave = &omap3xxx_wd_timer2_hwmod, | |
2566 | .clk = "wdt2_ick", | |
2567 | .addr = omap3xxx_wd_timer2_addrs, | |
2568 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2569 | }; | |
2570 | ||
2571 | /* l4_core -> dss */ | |
2572 | static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { | |
0f616a4e | 2573 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2574 | .slave = &omap3430es1_dss_core_hwmod, |
2575 | .clk = "dss_ick", | |
2576 | .addr = omap2_dss_addrs, | |
2577 | .fw = { | |
2578 | .omap2 = { | |
2579 | .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, | |
2580 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2581 | .flags = OMAP_FIREWALL_L4, | |
2582 | } | |
2583 | }, | |
0f616a4e C |
2584 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2585 | }; | |
2586 | ||
844a3b63 | 2587 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { |
0f616a4e | 2588 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2589 | .slave = &omap3xxx_dss_core_hwmod, |
2590 | .clk = "dss_ick", | |
2591 | .addr = omap2_dss_addrs, | |
2592 | .fw = { | |
2593 | .omap2 = { | |
2594 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, | |
2595 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2596 | .flags = OMAP_FIREWALL_L4, | |
2597 | } | |
2598 | }, | |
0f616a4e C |
2599 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2600 | }; | |
2601 | ||
844a3b63 PW |
2602 | /* l4_core -> dss_dispc */ |
2603 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { | |
0f616a4e | 2604 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2605 | .slave = &omap3xxx_dss_dispc_hwmod, |
2606 | .clk = "dss_ick", | |
2607 | .addr = omap2_dss_dispc_addrs, | |
2608 | .fw = { | |
2609 | .omap2 = { | |
2610 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, | |
2611 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2612 | .flags = OMAP_FIREWALL_L4, | |
2613 | } | |
2614 | }, | |
0f616a4e C |
2615 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2616 | }; | |
2617 | ||
844a3b63 | 2618 | static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { |
0f616a4e | 2619 | { |
844a3b63 PW |
2620 | .pa_start = 0x4804FC00, |
2621 | .pa_end = 0x4804FFFF, | |
2622 | .flags = ADDR_TYPE_RT | |
0f616a4e | 2623 | }, |
78183f3f | 2624 | { } |
0f616a4e C |
2625 | }; |
2626 | ||
844a3b63 PW |
2627 | /* l4_core -> dss_dsi1 */ |
2628 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { | |
0f616a4e | 2629 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2630 | .slave = &omap3xxx_dss_dsi1_hwmod, |
2631 | .clk = "dss_ick", | |
2632 | .addr = omap3xxx_dss_dsi1_addrs, | |
2633 | .fw = { | |
2634 | .omap2 = { | |
2635 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, | |
2636 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2637 | .flags = OMAP_FIREWALL_L4, | |
2638 | } | |
2639 | }, | |
0f616a4e C |
2640 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2641 | }; | |
2642 | ||
844a3b63 PW |
2643 | /* l4_core -> dss_rfbi */ |
2644 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { | |
2645 | .master = &omap3xxx_l4_core_hwmod, | |
2646 | .slave = &omap3xxx_dss_rfbi_hwmod, | |
2647 | .clk = "dss_ick", | |
2648 | .addr = omap2_dss_rfbi_addrs, | |
2649 | .fw = { | |
0f616a4e | 2650 | .omap2 = { |
844a3b63 PW |
2651 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, |
2652 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , | |
2653 | .flags = OMAP_FIREWALL_L4, | |
2654 | } | |
0f616a4e | 2655 | }, |
844a3b63 | 2656 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
0f616a4e C |
2657 | }; |
2658 | ||
844a3b63 PW |
2659 | /* l4_core -> dss_venc */ |
2660 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { | |
2661 | .master = &omap3xxx_l4_core_hwmod, | |
2662 | .slave = &omap3xxx_dss_venc_hwmod, | |
2663 | .clk = "dss_ick", | |
2664 | .addr = omap2_dss_venc_addrs, | |
2665 | .fw = { | |
70034d38 | 2666 | .omap2 = { |
844a3b63 PW |
2667 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, |
2668 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2669 | .flags = OMAP_FIREWALL_L4, | |
2670 | } | |
70034d38 | 2671 | }, |
844a3b63 PW |
2672 | .flags = OCPIF_SWSUP_IDLE, |
2673 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2674 | }; |
2675 | ||
844a3b63 PW |
2676 | /* l4_wkup -> gpio1 */ |
2677 | static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { | |
2678 | { | |
2679 | .pa_start = 0x48310000, | |
2680 | .pa_end = 0x483101ff, | |
2681 | .flags = ADDR_TYPE_RT | |
2682 | }, | |
2683 | { } | |
70034d38 VC |
2684 | }; |
2685 | ||
844a3b63 PW |
2686 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { |
2687 | .master = &omap3xxx_l4_wkup_hwmod, | |
2688 | .slave = &omap3xxx_gpio1_hwmod, | |
2689 | .addr = omap3xxx_gpio1_addrs, | |
2690 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f616a4e C |
2691 | }; |
2692 | ||
844a3b63 PW |
2693 | /* l4_per -> gpio2 */ |
2694 | static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { | |
2695 | { | |
2696 | .pa_start = 0x49050000, | |
2697 | .pa_end = 0x490501ff, | |
2698 | .flags = ADDR_TYPE_RT | |
70034d38 | 2699 | }, |
844a3b63 | 2700 | { } |
70034d38 VC |
2701 | }; |
2702 | ||
844a3b63 PW |
2703 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { |
2704 | .master = &omap3xxx_l4_per_hwmod, | |
2705 | .slave = &omap3xxx_gpio2_hwmod, | |
2706 | .addr = omap3xxx_gpio2_addrs, | |
2707 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2708 | }; |
2709 | ||
844a3b63 PW |
2710 | /* l4_per -> gpio3 */ |
2711 | static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { | |
2712 | { | |
2713 | .pa_start = 0x49052000, | |
2714 | .pa_end = 0x490521ff, | |
2715 | .flags = ADDR_TYPE_RT | |
2716 | }, | |
2717 | { } | |
70034d38 VC |
2718 | }; |
2719 | ||
844a3b63 PW |
2720 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { |
2721 | .master = &omap3xxx_l4_per_hwmod, | |
2722 | .slave = &omap3xxx_gpio3_hwmod, | |
2723 | .addr = omap3xxx_gpio3_addrs, | |
2724 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f616a4e C |
2725 | }; |
2726 | ||
844a3b63 PW |
2727 | /* l4_per -> gpio4 */ |
2728 | static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { | |
2729 | { | |
2730 | .pa_start = 0x49054000, | |
2731 | .pa_end = 0x490541ff, | |
2732 | .flags = ADDR_TYPE_RT | |
70034d38 | 2733 | }, |
844a3b63 | 2734 | { } |
70034d38 VC |
2735 | }; |
2736 | ||
844a3b63 PW |
2737 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { |
2738 | .master = &omap3xxx_l4_per_hwmod, | |
2739 | .slave = &omap3xxx_gpio4_hwmod, | |
2740 | .addr = omap3xxx_gpio4_addrs, | |
2741 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2742 | }; |
2743 | ||
844a3b63 PW |
2744 | /* l4_per -> gpio5 */ |
2745 | static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { | |
2746 | { | |
2747 | .pa_start = 0x49056000, | |
2748 | .pa_end = 0x490561ff, | |
2749 | .flags = ADDR_TYPE_RT | |
2750 | }, | |
2751 | { } | |
01438ab6 MK |
2752 | }; |
2753 | ||
844a3b63 PW |
2754 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { |
2755 | .master = &omap3xxx_l4_per_hwmod, | |
2756 | .slave = &omap3xxx_gpio5_hwmod, | |
2757 | .addr = omap3xxx_gpio5_addrs, | |
2758 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2759 | }; |
2760 | ||
844a3b63 PW |
2761 | /* l4_per -> gpio6 */ |
2762 | static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { | |
2763 | { | |
2764 | .pa_start = 0x49058000, | |
2765 | .pa_end = 0x490581ff, | |
2766 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2767 | }, |
844a3b63 | 2768 | { } |
01438ab6 MK |
2769 | }; |
2770 | ||
844a3b63 PW |
2771 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { |
2772 | .master = &omap3xxx_l4_per_hwmod, | |
2773 | .slave = &omap3xxx_gpio6_hwmod, | |
2774 | .addr = omap3xxx_gpio6_addrs, | |
2775 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2776 | }; |
2777 | ||
844a3b63 PW |
2778 | /* dma_system -> L3 */ |
2779 | static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { | |
2780 | .master = &omap3xxx_dma_system_hwmod, | |
2781 | .slave = &omap3xxx_l3_main_hwmod, | |
2782 | .clk = "core_l3_ick", | |
2783 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2784 | }; |
2785 | ||
844a3b63 PW |
2786 | static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { |
2787 | { | |
2788 | .pa_start = 0x48056000, | |
2789 | .pa_end = 0x48056fff, | |
2790 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2791 | }, |
844a3b63 | 2792 | { } |
01438ab6 MK |
2793 | }; |
2794 | ||
844a3b63 PW |
2795 | /* l4_cfg -> dma_system */ |
2796 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { | |
2797 | .master = &omap3xxx_l4_core_hwmod, | |
2798 | .slave = &omap3xxx_dma_system_hwmod, | |
2799 | .clk = "core_l4_ick", | |
2800 | .addr = omap3xxx_dma_system_addrs, | |
2801 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2802 | }; |
2803 | ||
844a3b63 PW |
2804 | static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { |
2805 | { | |
2806 | .name = "mpu", | |
2807 | .pa_start = 0x48074000, | |
2808 | .pa_end = 0x480740ff, | |
2809 | .flags = ADDR_TYPE_RT | |
2810 | }, | |
2811 | { } | |
d3442726 TG |
2812 | }; |
2813 | ||
844a3b63 PW |
2814 | /* l4_core -> mcbsp1 */ |
2815 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { | |
2816 | .master = &omap3xxx_l4_core_hwmod, | |
2817 | .slave = &omap3xxx_mcbsp1_hwmod, | |
2818 | .clk = "mcbsp1_ick", | |
2819 | .addr = omap3xxx_mcbsp1_addrs, | |
2820 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2821 | }; |
2822 | ||
844a3b63 PW |
2823 | static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { |
2824 | { | |
2825 | .name = "mpu", | |
2826 | .pa_start = 0x49022000, | |
2827 | .pa_end = 0x490220ff, | |
2828 | .flags = ADDR_TYPE_RT | |
2829 | }, | |
2830 | { } | |
d3442726 TG |
2831 | }; |
2832 | ||
844a3b63 PW |
2833 | /* l4_per -> mcbsp2 */ |
2834 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { | |
2835 | .master = &omap3xxx_l4_per_hwmod, | |
2836 | .slave = &omap3xxx_mcbsp2_hwmod, | |
2837 | .clk = "mcbsp2_ick", | |
2838 | .addr = omap3xxx_mcbsp2_addrs, | |
2839 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2840 | }; |
2841 | ||
844a3b63 PW |
2842 | static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { |
2843 | { | |
2844 | .name = "mpu", | |
2845 | .pa_start = 0x49024000, | |
2846 | .pa_end = 0x490240ff, | |
2847 | .flags = ADDR_TYPE_RT | |
2848 | }, | |
2849 | { } | |
d3442726 TG |
2850 | }; |
2851 | ||
844a3b63 PW |
2852 | /* l4_per -> mcbsp3 */ |
2853 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { | |
2854 | .master = &omap3xxx_l4_per_hwmod, | |
2855 | .slave = &omap3xxx_mcbsp3_hwmod, | |
2856 | .clk = "mcbsp3_ick", | |
2857 | .addr = omap3xxx_mcbsp3_addrs, | |
2858 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
a52e2ab6 PW |
2859 | }; |
2860 | ||
844a3b63 PW |
2861 | static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { |
2862 | { | |
2863 | .name = "mpu", | |
2864 | .pa_start = 0x49026000, | |
2865 | .pa_end = 0x490260ff, | |
2866 | .flags = ADDR_TYPE_RT | |
a52e2ab6 | 2867 | }, |
844a3b63 | 2868 | { } |
a52e2ab6 PW |
2869 | }; |
2870 | ||
844a3b63 PW |
2871 | /* l4_per -> mcbsp4 */ |
2872 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { | |
2873 | .master = &omap3xxx_l4_per_hwmod, | |
2874 | .slave = &omap3xxx_mcbsp4_hwmod, | |
2875 | .clk = "mcbsp4_ick", | |
2876 | .addr = omap3xxx_mcbsp4_addrs, | |
2877 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2878 | }; |
2879 | ||
844a3b63 PW |
2880 | static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { |
2881 | { | |
2882 | .name = "mpu", | |
2883 | .pa_start = 0x48096000, | |
2884 | .pa_end = 0x480960ff, | |
2885 | .flags = ADDR_TYPE_RT | |
2886 | }, | |
2887 | { } | |
2888 | }; | |
b163605e | 2889 | |
844a3b63 PW |
2890 | /* l4_core -> mcbsp5 */ |
2891 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { | |
2892 | .master = &omap3xxx_l4_core_hwmod, | |
2893 | .slave = &omap3xxx_mcbsp5_hwmod, | |
2894 | .clk = "mcbsp5_ick", | |
2895 | .addr = omap3xxx_mcbsp5_addrs, | |
2896 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2897 | }; |
2898 | ||
844a3b63 PW |
2899 | static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { |
2900 | { | |
2901 | .name = "sidetone", | |
2902 | .pa_start = 0x49028000, | |
2903 | .pa_end = 0x490280ff, | |
2904 | .flags = ADDR_TYPE_RT | |
2905 | }, | |
2906 | { } | |
d3442726 TG |
2907 | }; |
2908 | ||
844a3b63 PW |
2909 | /* l4_per -> mcbsp2_sidetone */ |
2910 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { | |
2911 | .master = &omap3xxx_l4_per_hwmod, | |
2912 | .slave = &omap3xxx_mcbsp2_sidetone_hwmod, | |
2913 | .clk = "mcbsp2_ick", | |
2914 | .addr = omap3xxx_mcbsp2_sidetone_addrs, | |
2915 | .user = OCP_USER_MPU, | |
b163605e PW |
2916 | }; |
2917 | ||
844a3b63 PW |
2918 | static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { |
2919 | { | |
2920 | .name = "sidetone", | |
2921 | .pa_start = 0x4902A000, | |
2922 | .pa_end = 0x4902A0ff, | |
2923 | .flags = ADDR_TYPE_RT | |
2924 | }, | |
2925 | { } | |
a52e2ab6 PW |
2926 | }; |
2927 | ||
844a3b63 PW |
2928 | /* l4_per -> mcbsp3_sidetone */ |
2929 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { | |
2930 | .master = &omap3xxx_l4_per_hwmod, | |
2931 | .slave = &omap3xxx_mcbsp3_sidetone_hwmod, | |
2932 | .clk = "mcbsp3_ick", | |
2933 | .addr = omap3xxx_mcbsp3_sidetone_addrs, | |
2934 | .user = OCP_USER_MPU, | |
a52e2ab6 PW |
2935 | }; |
2936 | ||
844a3b63 PW |
2937 | static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { |
2938 | { | |
2939 | .pa_start = 0x48094000, | |
2940 | .pa_end = 0x480941ff, | |
2941 | .flags = ADDR_TYPE_RT, | |
d3442726 | 2942 | }, |
844a3b63 | 2943 | { } |
d3442726 TG |
2944 | }; |
2945 | ||
844a3b63 PW |
2946 | /* l4_core -> mailbox */ |
2947 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { | |
2948 | .master = &omap3xxx_l4_core_hwmod, | |
2949 | .slave = &omap3xxx_mailbox_hwmod, | |
2950 | .addr = omap3xxx_mailbox_addrs, | |
2951 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2952 | }; | |
b163605e | 2953 | |
844a3b63 PW |
2954 | /* l4 core -> mcspi1 interface */ |
2955 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { | |
2956 | .master = &omap3xxx_l4_core_hwmod, | |
2957 | .slave = &omap34xx_mcspi1, | |
2958 | .clk = "mcspi1_ick", | |
2959 | .addr = omap2_mcspi1_addr_space, | |
2960 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
2961 | }; |
2962 | ||
844a3b63 PW |
2963 | /* l4 core -> mcspi2 interface */ |
2964 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { | |
2965 | .master = &omap3xxx_l4_core_hwmod, | |
2966 | .slave = &omap34xx_mcspi2, | |
2967 | .clk = "mcspi2_ick", | |
2968 | .addr = omap2_mcspi2_addr_space, | |
2969 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
2970 | }; |
2971 | ||
844a3b63 PW |
2972 | /* l4 core -> mcspi3 interface */ |
2973 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { | |
2974 | .master = &omap3xxx_l4_core_hwmod, | |
2975 | .slave = &omap34xx_mcspi3, | |
2976 | .clk = "mcspi3_ick", | |
2977 | .addr = omap2430_mcspi3_addr_space, | |
2978 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
2979 | }; |
2980 | ||
844a3b63 PW |
2981 | /* l4 core -> mcspi4 interface */ |
2982 | static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { | |
2983 | { | |
2984 | .pa_start = 0x480ba000, | |
2985 | .pa_end = 0x480ba0ff, | |
2986 | .flags = ADDR_TYPE_RT, | |
d3442726 | 2987 | }, |
844a3b63 PW |
2988 | { } |
2989 | }; | |
2990 | ||
2991 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { | |
2992 | .master = &omap3xxx_l4_core_hwmod, | |
2993 | .slave = &omap34xx_mcspi4, | |
2994 | .clk = "mcspi4_ick", | |
2995 | .addr = omap34xx_mcspi4_addr_space, | |
2996 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2997 | }; |
2998 | ||
de231388 KM |
2999 | static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { |
3000 | .master = &omap3xxx_usb_host_hs_hwmod, | |
3001 | .slave = &omap3xxx_l3_main_hwmod, | |
3002 | .clk = "core_l3_ick", | |
3003 | .user = OCP_USER_MPU, | |
3004 | }; | |
3005 | ||
de231388 KM |
3006 | static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = { |
3007 | { | |
3008 | .name = "uhh", | |
3009 | .pa_start = 0x48064000, | |
3010 | .pa_end = 0x480643ff, | |
3011 | .flags = ADDR_TYPE_RT | |
3012 | }, | |
3013 | { | |
3014 | .name = "ohci", | |
3015 | .pa_start = 0x48064400, | |
3016 | .pa_end = 0x480647ff, | |
3017 | }, | |
3018 | { | |
3019 | .name = "ehci", | |
3020 | .pa_start = 0x48064800, | |
3021 | .pa_end = 0x48064cff, | |
3022 | }, | |
3023 | {} | |
3024 | }; | |
3025 | ||
3026 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { | |
3027 | .master = &omap3xxx_l4_core_hwmod, | |
3028 | .slave = &omap3xxx_usb_host_hs_hwmod, | |
3029 | .clk = "usbhost_ick", | |
3030 | .addr = omap3xxx_usb_host_hs_addrs, | |
3031 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3032 | }; | |
3033 | ||
de231388 KM |
3034 | static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = { |
3035 | { | |
3036 | .name = "tll", | |
3037 | .pa_start = 0x48062000, | |
3038 | .pa_end = 0x48062fff, | |
3039 | .flags = ADDR_TYPE_RT | |
3040 | }, | |
3041 | {} | |
3042 | }; | |
3043 | ||
3044 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { | |
3045 | .master = &omap3xxx_l4_core_hwmod, | |
3046 | .slave = &omap3xxx_usb_tll_hs_hwmod, | |
3047 | .clk = "usbtll_ick", | |
3048 | .addr = omap3xxx_usb_tll_hs_addrs, | |
3049 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3050 | }; | |
3051 | ||
0a78c5c5 PW |
3052 | static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { |
3053 | &omap3xxx_l3_main__l4_core, | |
3054 | &omap3xxx_l3_main__l4_per, | |
3055 | &omap3xxx_mpu__l3_main, | |
3056 | &omap3xxx_l4_core__l4_wkup, | |
3057 | &omap3xxx_l4_core__mmc3, | |
3058 | &omap3_l4_core__uart1, | |
3059 | &omap3_l4_core__uart2, | |
3060 | &omap3_l4_per__uart3, | |
3061 | &omap3_l4_core__i2c1, | |
3062 | &omap3_l4_core__i2c2, | |
3063 | &omap3_l4_core__i2c3, | |
3064 | &omap3xxx_l4_wkup__l4_sec, | |
3065 | &omap3xxx_l4_wkup__timer1, | |
3066 | &omap3xxx_l4_per__timer2, | |
3067 | &omap3xxx_l4_per__timer3, | |
3068 | &omap3xxx_l4_per__timer4, | |
3069 | &omap3xxx_l4_per__timer5, | |
3070 | &omap3xxx_l4_per__timer6, | |
3071 | &omap3xxx_l4_per__timer7, | |
3072 | &omap3xxx_l4_per__timer8, | |
3073 | &omap3xxx_l4_per__timer9, | |
3074 | &omap3xxx_l4_core__timer10, | |
3075 | &omap3xxx_l4_core__timer11, | |
3076 | &omap3xxx_l4_wkup__wd_timer2, | |
3077 | &omap3xxx_l4_wkup__gpio1, | |
3078 | &omap3xxx_l4_per__gpio2, | |
3079 | &omap3xxx_l4_per__gpio3, | |
3080 | &omap3xxx_l4_per__gpio4, | |
3081 | &omap3xxx_l4_per__gpio5, | |
3082 | &omap3xxx_l4_per__gpio6, | |
3083 | &omap3xxx_dma_system__l3, | |
3084 | &omap3xxx_l4_core__dma_system, | |
3085 | &omap3xxx_l4_core__mcbsp1, | |
3086 | &omap3xxx_l4_per__mcbsp2, | |
3087 | &omap3xxx_l4_per__mcbsp3, | |
3088 | &omap3xxx_l4_per__mcbsp4, | |
3089 | &omap3xxx_l4_core__mcbsp5, | |
3090 | &omap3xxx_l4_per__mcbsp2_sidetone, | |
3091 | &omap3xxx_l4_per__mcbsp3_sidetone, | |
3092 | &omap34xx_l4_core__mcspi1, | |
3093 | &omap34xx_l4_core__mcspi2, | |
3094 | &omap34xx_l4_core__mcspi3, | |
3095 | &omap34xx_l4_core__mcspi4, | |
d6504acd PW |
3096 | NULL, |
3097 | }; | |
3098 | ||
0a78c5c5 PW |
3099 | /* GP-only hwmod links */ |
3100 | static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = { | |
3101 | &omap3xxx_l4_sec__timer12, | |
91a36bdb AK |
3102 | NULL |
3103 | }; | |
3104 | ||
0a78c5c5 PW |
3105 | /* 3430ES1-only hwmod links */ |
3106 | static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = { | |
3107 | &omap3430es1_dss__l3, | |
3108 | &omap3430es1_l4_core__dss, | |
d6504acd PW |
3109 | NULL |
3110 | }; | |
3111 | ||
0a78c5c5 PW |
3112 | /* 3430ES2+-only hwmod links */ |
3113 | static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = { | |
3114 | &omap3xxx_dss__l3, | |
3115 | &omap3xxx_l4_core__dss, | |
3116 | &omap3xxx_usbhsotg__l3, | |
3117 | &omap3xxx_l4_core__usbhsotg, | |
3118 | &omap3xxx_usb_host_hs__l3_main_2, | |
3119 | &omap3xxx_l4_core__usb_host_hs, | |
3120 | &omap3xxx_l4_core__usb_tll_hs, | |
d6504acd PW |
3121 | NULL |
3122 | }; | |
870ea2b8 | 3123 | |
0a78c5c5 PW |
3124 | /* <= 3430ES3-only hwmod links */ |
3125 | static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = { | |
3126 | &omap3xxx_l4_core__pre_es3_mmc1, | |
3127 | &omap3xxx_l4_core__pre_es3_mmc2, | |
a52e2ab6 PW |
3128 | NULL |
3129 | }; | |
3130 | ||
0a78c5c5 PW |
3131 | /* 3430ES3+-only hwmod links */ |
3132 | static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = { | |
3133 | &omap3xxx_l4_core__es3plus_mmc1, | |
3134 | &omap3xxx_l4_core__es3plus_mmc2, | |
a52e2ab6 PW |
3135 | NULL |
3136 | }; | |
3137 | ||
0a78c5c5 PW |
3138 | /* 34xx-only hwmod links (all ES revisions) */ |
3139 | static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { | |
3140 | &omap3xxx_l3__iva, | |
3141 | &omap34xx_l4_core__sr1, | |
3142 | &omap34xx_l4_core__sr2, | |
3143 | &omap3xxx_l4_core__mailbox, | |
d6504acd PW |
3144 | NULL |
3145 | }; | |
273ff8c3 | 3146 | |
0a78c5c5 PW |
3147 | /* 36xx-only hwmod links (all ES revisions) */ |
3148 | static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { | |
3149 | &omap3xxx_l3__iva, | |
3150 | &omap36xx_l4_per__uart4, | |
3151 | &omap3xxx_dss__l3, | |
3152 | &omap3xxx_l4_core__dss, | |
3153 | &omap36xx_l4_core__sr1, | |
3154 | &omap36xx_l4_core__sr2, | |
3155 | &omap3xxx_usbhsotg__l3, | |
3156 | &omap3xxx_l4_core__usbhsotg, | |
3157 | &omap3xxx_l4_core__mailbox, | |
3158 | &omap3xxx_usb_host_hs__l3_main_2, | |
3159 | &omap3xxx_l4_core__usb_host_hs, | |
3160 | &omap3xxx_l4_core__usb_tll_hs, | |
3161 | &omap3xxx_l4_core__es3plus_mmc1, | |
3162 | &omap3xxx_l4_core__es3plus_mmc2, | |
d6504acd PW |
3163 | NULL |
3164 | }; | |
3165 | ||
0a78c5c5 PW |
3166 | static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { |
3167 | &omap3xxx_dss__l3, | |
3168 | &omap3xxx_l4_core__dss, | |
3169 | &am35xx_usbhsotg__l3, | |
3170 | &am35xx_l4_core__usbhsotg, | |
3171 | &am35xx_l4_core__uart4, | |
3172 | &omap3xxx_usb_host_hs__l3_main_2, | |
3173 | &omap3xxx_l4_core__usb_host_hs, | |
3174 | &omap3xxx_l4_core__usb_tll_hs, | |
3175 | &omap3xxx_l4_core__es3plus_mmc1, | |
3176 | &omap3xxx_l4_core__es3plus_mmc2, | |
d6504acd | 3177 | NULL |
7359154e PW |
3178 | }; |
3179 | ||
0a78c5c5 PW |
3180 | static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { |
3181 | &omap3xxx_l4_core__dss_dispc, | |
3182 | &omap3xxx_l4_core__dss_dsi1, | |
3183 | &omap3xxx_l4_core__dss_rfbi, | |
3184 | &omap3xxx_l4_core__dss_venc, | |
1d2f56c8 IY |
3185 | NULL |
3186 | }; | |
3187 | ||
7359154e PW |
3188 | int __init omap3xxx_hwmod_init(void) |
3189 | { | |
d6504acd | 3190 | int r; |
0a78c5c5 | 3191 | struct omap_hwmod_ocp_if **h = NULL; |
d6504acd PW |
3192 | unsigned int rev; |
3193 | ||
0a78c5c5 PW |
3194 | /* Register hwmod links common to all OMAP3 */ |
3195 | r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); | |
ace90216 | 3196 | if (r < 0) |
d6504acd PW |
3197 | return r; |
3198 | ||
0a78c5c5 | 3199 | /* Register GP-only hwmod links. */ |
91a36bdb | 3200 | if (omap_type() == OMAP2_DEVICE_TYPE_GP) { |
0a78c5c5 | 3201 | r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs); |
91a36bdb AK |
3202 | if (r < 0) |
3203 | return r; | |
3204 | } | |
3205 | ||
d6504acd PW |
3206 | rev = omap_rev(); |
3207 | ||
3208 | /* | |
0a78c5c5 | 3209 | * Register hwmod links common to individual OMAP3 families, all |
d6504acd PW |
3210 | * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) |
3211 | * All possible revisions should be included in this conditional. | |
3212 | */ | |
3213 | if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || | |
3214 | rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || | |
3215 | rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3216 | h = omap34xx_hwmod_ocp_ifs; |
d6504acd | 3217 | } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) { |
0a78c5c5 | 3218 | h = am35xx_hwmod_ocp_ifs; |
d6504acd PW |
3219 | } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || |
3220 | rev == OMAP3630_REV_ES1_2) { | |
0a78c5c5 | 3221 | h = omap36xx_hwmod_ocp_ifs; |
d6504acd PW |
3222 | } else { |
3223 | WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); | |
3224 | return -EINVAL; | |
3225 | }; | |
3226 | ||
0a78c5c5 | 3227 | r = omap_hwmod_register_links(h); |
ace90216 | 3228 | if (r < 0) |
d6504acd PW |
3229 | return r; |
3230 | ||
3231 | /* | |
0a78c5c5 | 3232 | * Register hwmod links specific to certain ES levels of a |
d6504acd PW |
3233 | * particular family of silicon (e.g., 34xx ES1.0) |
3234 | */ | |
3235 | h = NULL; | |
3236 | if (rev == OMAP3430_REV_ES1_0) { | |
0a78c5c5 | 3237 | h = omap3430es1_hwmod_ocp_ifs; |
d6504acd PW |
3238 | } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || |
3239 | rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || | |
3240 | rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3241 | h = omap3430es2plus_hwmod_ocp_ifs; |
d6504acd PW |
3242 | }; |
3243 | ||
a52e2ab6 | 3244 | if (h) { |
0a78c5c5 | 3245 | r = omap_hwmod_register_links(h); |
a52e2ab6 PW |
3246 | if (r < 0) |
3247 | return r; | |
3248 | } | |
3249 | ||
3250 | h = NULL; | |
3251 | if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || | |
3252 | rev == OMAP3430_REV_ES2_1) { | |
0a78c5c5 | 3253 | h = omap3430_pre_es3_hwmod_ocp_ifs; |
a52e2ab6 PW |
3254 | } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || |
3255 | rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3256 | h = omap3430_es3plus_hwmod_ocp_ifs; |
a52e2ab6 PW |
3257 | }; |
3258 | ||
d6504acd | 3259 | if (h) |
0a78c5c5 | 3260 | r = omap_hwmod_register_links(h); |
1d2f56c8 IY |
3261 | if (r < 0) |
3262 | return r; | |
3263 | ||
3264 | /* | |
3265 | * DSS code presumes that dss_core hwmod is handled first, | |
3266 | * _before_ any other DSS related hwmods so register common | |
0a78c5c5 PW |
3267 | * DSS hwmod links last to ensure that dss_core is already |
3268 | * registered. Otherwise some change things may happen, for | |
3269 | * ex. if dispc is handled before dss_core and DSS is enabled | |
3270 | * in bootloader DISPC will be reset with outputs enabled | |
3271 | * which sometimes leads to unrecoverable L3 error. XXX The | |
3272 | * long-term fix to this is to ensure hwmods are set up in | |
3273 | * dependency order in the hwmod core code. | |
1d2f56c8 | 3274 | */ |
0a78c5c5 | 3275 | r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs); |
d6504acd PW |
3276 | |
3277 | return r; | |
7359154e | 3278 | } |