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7359154e PW |
1 | /* |
2 | * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips | |
3 | * | |
78183f3f | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
0a78c5c5 | 5 | * Copyright (C) 2012 Texas Instruments, Inc. |
7359154e PW |
6 | * Paul Walmsley |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * The data in this file should be completely autogeneratable from | |
13 | * the TI hardware database or other technical documentation. | |
14 | * | |
15 | * XXX these should be marked initdata for multi-OMAP kernels | |
16 | */ | |
b86aeafc | 17 | #include <linux/power/smartreflex.h> |
4b25408f | 18 | #include <linux/platform_data/gpio-omap.h> |
b86aeafc | 19 | |
7359154e | 20 | #include <plat/omap_hwmod.h> |
7359154e | 21 | #include <plat/dma.h> |
046465b7 | 22 | #include <plat/serial.h> |
e04d9e1e | 23 | #include <plat/l3_3xxx.h> |
4fe20e97 RN |
24 | #include <plat/l4_3xxx.h> |
25 | #include <plat/i2c.h> | |
6ab8946f | 26 | #include <plat/mmc.h> |
dc48e5fc | 27 | #include <plat/mcbsp.h> |
0f616a4e | 28 | #include <plat/mcspi.h> |
ce722d26 | 29 | #include <plat/dmtimer.h> |
7359154e | 30 | |
7d7e1eba TL |
31 | #include <mach/am35xx.h> |
32 | ||
dbc04161 | 33 | #include "soc.h" |
43b40992 | 34 | #include "omap_hwmod_common_data.h" |
7359154e | 35 | #include "prm-regbits-34xx.h" |
6b667f88 | 36 | #include "cm-regbits-34xx.h" |
ff2516fb | 37 | #include "wd_timer.h" |
7359154e PW |
38 | |
39 | /* | |
40 | * OMAP3xxx hardware module integration data | |
41 | * | |
844a3b63 | 42 | * All of the data in this section should be autogeneratable from the |
7359154e PW |
43 | * TI hardware database or other technical documentation. Data that |
44 | * is driver-specific or driver-kernel integration-specific belongs | |
45 | * elsewhere. | |
46 | */ | |
47 | ||
844a3b63 PW |
48 | /* |
49 | * IP blocks | |
50 | */ | |
7359154e | 51 | |
844a3b63 | 52 | /* L3 */ |
4bb194dc | 53 | static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { |
7d7e1eba TL |
54 | { .irq = 9 + OMAP_INTC_START, }, |
55 | { .irq = 10 + OMAP_INTC_START, }, | |
56 | { .irq = -1 }, | |
4bb194dc | 57 | }; |
58 | ||
4a7cf90a | 59 | static struct omap_hwmod omap3xxx_l3_main_hwmod = { |
fa98347e | 60 | .name = "l3_main", |
43b40992 | 61 | .class = &l3_hwmod_class, |
0d619a89 | 62 | .mpu_irqs = omap3xxx_l3_main_irqs, |
2eb1875d | 63 | .flags = HWMOD_NO_IDLEST, |
7359154e PW |
64 | }; |
65 | ||
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66 | /* L4 CORE */ |
67 | static struct omap_hwmod omap3xxx_l4_core_hwmod = { | |
68 | .name = "l4_core", | |
69 | .class = &l4_hwmod_class, | |
70 | .flags = HWMOD_NO_IDLEST, | |
870ea2b8 | 71 | }; |
7359154e | 72 | |
844a3b63 PW |
73 | /* L4 PER */ |
74 | static struct omap_hwmod omap3xxx_l4_per_hwmod = { | |
75 | .name = "l4_per", | |
76 | .class = &l4_hwmod_class, | |
77 | .flags = HWMOD_NO_IDLEST, | |
273ff8c3 | 78 | }; |
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79 | |
80 | /* L4 WKUP */ | |
81 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { | |
82 | .name = "l4_wkup", | |
83 | .class = &l4_hwmod_class, | |
84 | .flags = HWMOD_NO_IDLEST, | |
7359154e PW |
85 | }; |
86 | ||
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87 | /* L4 SEC */ |
88 | static struct omap_hwmod omap3xxx_l4_sec_hwmod = { | |
89 | .name = "l4_sec", | |
90 | .class = &l4_hwmod_class, | |
91 | .flags = HWMOD_NO_IDLEST, | |
4a9efb62 PW |
92 | }; |
93 | ||
844a3b63 PW |
94 | /* MPU */ |
95 | static struct omap_hwmod omap3xxx_mpu_hwmod = { | |
96 | .name = "mpu", | |
97 | .class = &mpu_hwmod_class, | |
98 | .main_clk = "arm_fck", | |
b163605e PW |
99 | }; |
100 | ||
844a3b63 | 101 | /* IVA2 (IVA2) */ |
f42c5496 | 102 | static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = { |
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103 | { .name = "logic", .rst_shift = 0, .st_shift = 8 }, |
104 | { .name = "seq0", .rst_shift = 1, .st_shift = 9 }, | |
105 | { .name = "seq1", .rst_shift = 2, .st_shift = 10 }, | |
f42c5496 PW |
106 | }; |
107 | ||
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108 | static struct omap_hwmod omap3xxx_iva_hwmod = { |
109 | .name = "iva", | |
110 | .class = &iva_hwmod_class, | |
f42c5496 PW |
111 | .clkdm_name = "iva2_clkdm", |
112 | .rst_lines = omap3xxx_iva_resets, | |
113 | .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets), | |
114 | .main_clk = "iva2_ck", | |
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115 | .prcm = { |
116 | .omap2 = { | |
117 | .module_offs = OMAP3430_IVA2_MOD, | |
118 | .prcm_reg_id = 1, | |
119 | .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, | |
120 | .idlest_reg_id = 1, | |
121 | .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, | |
122 | } | |
123 | }, | |
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124 | }; |
125 | ||
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126 | /* timer class */ |
127 | static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = { | |
128 | .rev_offs = 0x0000, | |
129 | .sysc_offs = 0x0010, | |
130 | .syss_offs = 0x0014, | |
131 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
132 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
133 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), | |
134 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
135 | .sysc_fields = &omap_hwmod_sysc_type1, | |
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136 | }; |
137 | ||
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138 | static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = { |
139 | .name = "timer", | |
140 | .sysc = &omap3xxx_timer_1ms_sysc, | |
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141 | }; |
142 | ||
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143 | static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { |
144 | .rev_offs = 0x0000, | |
145 | .sysc_offs = 0x0010, | |
146 | .syss_offs = 0x0014, | |
147 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
148 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
149 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
150 | .sysc_fields = &omap_hwmod_sysc_type1, | |
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151 | }; |
152 | ||
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153 | static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { |
154 | .name = "timer", | |
155 | .sysc = &omap3xxx_timer_sysc, | |
046465b7 KH |
156 | }; |
157 | ||
844a3b63 PW |
158 | /* secure timers dev attribute */ |
159 | static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { | |
139486fa | 160 | .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE, |
046465b7 KH |
161 | }; |
162 | ||
844a3b63 PW |
163 | /* always-on timers dev attribute */ |
164 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
165 | .timer_capability = OMAP_TIMER_ALWON, | |
046465b7 KH |
166 | }; |
167 | ||
844a3b63 PW |
168 | /* pwm timers dev attribute */ |
169 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
170 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
046465b7 KH |
171 | }; |
172 | ||
844a3b63 PW |
173 | /* timer1 */ |
174 | static struct omap_hwmod omap3xxx_timer1_hwmod = { | |
175 | .name = "timer1", | |
176 | .mpu_irqs = omap2_timer1_mpu_irqs, | |
177 | .main_clk = "gpt1_fck", | |
178 | .prcm = { | |
179 | .omap2 = { | |
180 | .prcm_reg_id = 1, | |
181 | .module_bit = OMAP3430_EN_GPT1_SHIFT, | |
182 | .module_offs = WKUP_MOD, | |
183 | .idlest_reg_id = 1, | |
184 | .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, | |
185 | }, | |
046465b7 | 186 | }, |
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187 | .dev_attr = &capability_alwon_dev_attr, |
188 | .class = &omap3xxx_timer_1ms_hwmod_class, | |
046465b7 KH |
189 | }; |
190 | ||
844a3b63 PW |
191 | /* timer2 */ |
192 | static struct omap_hwmod omap3xxx_timer2_hwmod = { | |
193 | .name = "timer2", | |
194 | .mpu_irqs = omap2_timer2_mpu_irqs, | |
195 | .main_clk = "gpt2_fck", | |
196 | .prcm = { | |
197 | .omap2 = { | |
198 | .prcm_reg_id = 1, | |
199 | .module_bit = OMAP3430_EN_GPT2_SHIFT, | |
200 | .module_offs = OMAP3430_PER_MOD, | |
201 | .idlest_reg_id = 1, | |
202 | .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, | |
203 | }, | |
204 | }, | |
844a3b63 | 205 | .class = &omap3xxx_timer_1ms_hwmod_class, |
046465b7 KH |
206 | }; |
207 | ||
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208 | /* timer3 */ |
209 | static struct omap_hwmod omap3xxx_timer3_hwmod = { | |
210 | .name = "timer3", | |
211 | .mpu_irqs = omap2_timer3_mpu_irqs, | |
212 | .main_clk = "gpt3_fck", | |
213 | .prcm = { | |
214 | .omap2 = { | |
215 | .prcm_reg_id = 1, | |
216 | .module_bit = OMAP3430_EN_GPT3_SHIFT, | |
217 | .module_offs = OMAP3430_PER_MOD, | |
218 | .idlest_reg_id = 1, | |
219 | .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, | |
220 | }, | |
221 | }, | |
844a3b63 | 222 | .class = &omap3xxx_timer_hwmod_class, |
046465b7 KH |
223 | }; |
224 | ||
844a3b63 PW |
225 | /* timer4 */ |
226 | static struct omap_hwmod omap3xxx_timer4_hwmod = { | |
227 | .name = "timer4", | |
228 | .mpu_irqs = omap2_timer4_mpu_irqs, | |
229 | .main_clk = "gpt4_fck", | |
230 | .prcm = { | |
231 | .omap2 = { | |
232 | .prcm_reg_id = 1, | |
233 | .module_bit = OMAP3430_EN_GPT4_SHIFT, | |
234 | .module_offs = OMAP3430_PER_MOD, | |
235 | .idlest_reg_id = 1, | |
236 | .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, | |
237 | }, | |
238 | }, | |
844a3b63 | 239 | .class = &omap3xxx_timer_hwmod_class, |
046465b7 KH |
240 | }; |
241 | ||
844a3b63 PW |
242 | /* timer5 */ |
243 | static struct omap_hwmod omap3xxx_timer5_hwmod = { | |
244 | .name = "timer5", | |
245 | .mpu_irqs = omap2_timer5_mpu_irqs, | |
246 | .main_clk = "gpt5_fck", | |
247 | .prcm = { | |
248 | .omap2 = { | |
249 | .prcm_reg_id = 1, | |
250 | .module_bit = OMAP3430_EN_GPT5_SHIFT, | |
251 | .module_offs = OMAP3430_PER_MOD, | |
252 | .idlest_reg_id = 1, | |
253 | .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, | |
254 | }, | |
4bf90f65 | 255 | }, |
844a3b63 | 256 | .class = &omap3xxx_timer_hwmod_class, |
4bf90f65 KM |
257 | }; |
258 | ||
844a3b63 PW |
259 | /* timer6 */ |
260 | static struct omap_hwmod omap3xxx_timer6_hwmod = { | |
261 | .name = "timer6", | |
262 | .mpu_irqs = omap2_timer6_mpu_irqs, | |
263 | .main_clk = "gpt6_fck", | |
264 | .prcm = { | |
265 | .omap2 = { | |
266 | .prcm_reg_id = 1, | |
267 | .module_bit = OMAP3430_EN_GPT6_SHIFT, | |
268 | .module_offs = OMAP3430_PER_MOD, | |
269 | .idlest_reg_id = 1, | |
270 | .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, | |
271 | }, | |
272 | }, | |
844a3b63 | 273 | .class = &omap3xxx_timer_hwmod_class, |
4bf90f65 KM |
274 | }; |
275 | ||
844a3b63 PW |
276 | /* timer7 */ |
277 | static struct omap_hwmod omap3xxx_timer7_hwmod = { | |
278 | .name = "timer7", | |
279 | .mpu_irqs = omap2_timer7_mpu_irqs, | |
280 | .main_clk = "gpt7_fck", | |
281 | .prcm = { | |
4fe20e97 | 282 | .omap2 = { |
844a3b63 PW |
283 | .prcm_reg_id = 1, |
284 | .module_bit = OMAP3430_EN_GPT7_SHIFT, | |
285 | .module_offs = OMAP3430_PER_MOD, | |
286 | .idlest_reg_id = 1, | |
287 | .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, | |
288 | }, | |
4fe20e97 | 289 | }, |
844a3b63 | 290 | .class = &omap3xxx_timer_hwmod_class, |
4fe20e97 RN |
291 | }; |
292 | ||
844a3b63 PW |
293 | /* timer8 */ |
294 | static struct omap_hwmod omap3xxx_timer8_hwmod = { | |
295 | .name = "timer8", | |
296 | .mpu_irqs = omap2_timer8_mpu_irqs, | |
297 | .main_clk = "gpt8_fck", | |
298 | .prcm = { | |
4fe20e97 | 299 | .omap2 = { |
844a3b63 PW |
300 | .prcm_reg_id = 1, |
301 | .module_bit = OMAP3430_EN_GPT8_SHIFT, | |
302 | .module_offs = OMAP3430_PER_MOD, | |
303 | .idlest_reg_id = 1, | |
304 | .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, | |
305 | }, | |
4fe20e97 | 306 | }, |
844a3b63 PW |
307 | .dev_attr = &capability_pwm_dev_attr, |
308 | .class = &omap3xxx_timer_hwmod_class, | |
4fe20e97 RN |
309 | }; |
310 | ||
844a3b63 PW |
311 | /* timer9 */ |
312 | static struct omap_hwmod omap3xxx_timer9_hwmod = { | |
313 | .name = "timer9", | |
314 | .mpu_irqs = omap2_timer9_mpu_irqs, | |
315 | .main_clk = "gpt9_fck", | |
316 | .prcm = { | |
317 | .omap2 = { | |
318 | .prcm_reg_id = 1, | |
319 | .module_bit = OMAP3430_EN_GPT9_SHIFT, | |
320 | .module_offs = OMAP3430_PER_MOD, | |
321 | .idlest_reg_id = 1, | |
322 | .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, | |
323 | }, | |
4fe20e97 | 324 | }, |
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325 | .dev_attr = &capability_pwm_dev_attr, |
326 | .class = &omap3xxx_timer_hwmod_class, | |
4fe20e97 RN |
327 | }; |
328 | ||
844a3b63 PW |
329 | /* timer10 */ |
330 | static struct omap_hwmod omap3xxx_timer10_hwmod = { | |
331 | .name = "timer10", | |
332 | .mpu_irqs = omap2_timer10_mpu_irqs, | |
333 | .main_clk = "gpt10_fck", | |
334 | .prcm = { | |
4fe20e97 | 335 | .omap2 = { |
844a3b63 PW |
336 | .prcm_reg_id = 1, |
337 | .module_bit = OMAP3430_EN_GPT10_SHIFT, | |
338 | .module_offs = CORE_MOD, | |
339 | .idlest_reg_id = 1, | |
340 | .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, | |
341 | }, | |
4fe20e97 | 342 | }, |
844a3b63 PW |
343 | .dev_attr = &capability_pwm_dev_attr, |
344 | .class = &omap3xxx_timer_1ms_hwmod_class, | |
4fe20e97 RN |
345 | }; |
346 | ||
844a3b63 PW |
347 | /* timer11 */ |
348 | static struct omap_hwmod omap3xxx_timer11_hwmod = { | |
349 | .name = "timer11", | |
350 | .mpu_irqs = omap2_timer11_mpu_irqs, | |
351 | .main_clk = "gpt11_fck", | |
352 | .prcm = { | |
353 | .omap2 = { | |
354 | .prcm_reg_id = 1, | |
355 | .module_bit = OMAP3430_EN_GPT11_SHIFT, | |
356 | .module_offs = CORE_MOD, | |
357 | .idlest_reg_id = 1, | |
358 | .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, | |
359 | }, | |
360 | }, | |
361 | .dev_attr = &capability_pwm_dev_attr, | |
362 | .class = &omap3xxx_timer_hwmod_class, | |
d62bc78a NM |
363 | }; |
364 | ||
844a3b63 PW |
365 | /* timer12 */ |
366 | static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { | |
7d7e1eba TL |
367 | { .irq = 95 + OMAP_INTC_START, }, |
368 | { .irq = -1 }, | |
d62bc78a NM |
369 | }; |
370 | ||
844a3b63 PW |
371 | static struct omap_hwmod omap3xxx_timer12_hwmod = { |
372 | .name = "timer12", | |
373 | .mpu_irqs = omap3xxx_timer12_mpu_irqs, | |
374 | .main_clk = "gpt12_fck", | |
375 | .prcm = { | |
376 | .omap2 = { | |
377 | .prcm_reg_id = 1, | |
378 | .module_bit = OMAP3430_EN_GPT12_SHIFT, | |
379 | .module_offs = WKUP_MOD, | |
380 | .idlest_reg_id = 1, | |
381 | .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, | |
382 | }, | |
d3442726 | 383 | }, |
844a3b63 PW |
384 | .dev_attr = &capability_secure_dev_attr, |
385 | .class = &omap3xxx_timer_hwmod_class, | |
d3442726 TG |
386 | }; |
387 | ||
844a3b63 PW |
388 | /* |
389 | * 'wd_timer' class | |
390 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
391 | * overflow condition | |
392 | */ | |
393 | ||
394 | static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { | |
395 | .rev_offs = 0x0000, | |
396 | .sysc_offs = 0x0010, | |
397 | .syss_offs = 0x0014, | |
398 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | | |
399 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
400 | SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
401 | SYSS_HAS_RESET_STATUS), | |
402 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
403 | .sysc_fields = &omap_hwmod_sysc_type1, | |
d3442726 TG |
404 | }; |
405 | ||
844a3b63 PW |
406 | /* I2C common */ |
407 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
408 | .rev_offs = 0x00, | |
409 | .sysc_offs = 0x20, | |
410 | .syss_offs = 0x10, | |
411 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
412 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
413 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
414 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
415 | .clockact = CLOCKACT_TEST_ICLK, | |
416 | .sysc_fields = &omap_hwmod_sysc_type1, | |
d3442726 TG |
417 | }; |
418 | ||
844a3b63 PW |
419 | static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { |
420 | .name = "wd_timer", | |
421 | .sysc = &omap3xxx_wd_timer_sysc, | |
414e4128 KH |
422 | .pre_shutdown = &omap2_wd_timer_disable, |
423 | .reset = &omap2_wd_timer_reset, | |
d3442726 TG |
424 | }; |
425 | ||
844a3b63 PW |
426 | static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { |
427 | .name = "wd_timer2", | |
428 | .class = &omap3xxx_wd_timer_hwmod_class, | |
429 | .main_clk = "wdt2_fck", | |
430 | .prcm = { | |
431 | .omap2 = { | |
432 | .prcm_reg_id = 1, | |
433 | .module_bit = OMAP3430_EN_WDT2_SHIFT, | |
434 | .module_offs = WKUP_MOD, | |
435 | .idlest_reg_id = 1, | |
436 | .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, | |
437 | }, | |
438 | }, | |
439 | /* | |
440 | * XXX: Use software supervised mode, HW supervised smartidle seems to | |
441 | * block CORE power domain idle transitions. Maybe a HW bug in wdt2? | |
442 | */ | |
443 | .flags = HWMOD_SWSUP_SIDLE, | |
444 | }; | |
870ea2b8 | 445 | |
844a3b63 PW |
446 | /* UART1 */ |
447 | static struct omap_hwmod omap3xxx_uart1_hwmod = { | |
448 | .name = "uart1", | |
449 | .mpu_irqs = omap2_uart1_mpu_irqs, | |
450 | .sdma_reqs = omap2_uart1_sdma_reqs, | |
451 | .main_clk = "uart1_fck", | |
452 | .prcm = { | |
453 | .omap2 = { | |
454 | .module_offs = CORE_MOD, | |
455 | .prcm_reg_id = 1, | |
456 | .module_bit = OMAP3430_EN_UART1_SHIFT, | |
457 | .idlest_reg_id = 1, | |
458 | .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, | |
459 | }, | |
870ea2b8 | 460 | }, |
844a3b63 | 461 | .class = &omap2_uart_class, |
870ea2b8 HH |
462 | }; |
463 | ||
844a3b63 PW |
464 | /* UART2 */ |
465 | static struct omap_hwmod omap3xxx_uart2_hwmod = { | |
466 | .name = "uart2", | |
467 | .mpu_irqs = omap2_uart2_mpu_irqs, | |
468 | .sdma_reqs = omap2_uart2_sdma_reqs, | |
469 | .main_clk = "uart2_fck", | |
470 | .prcm = { | |
471 | .omap2 = { | |
472 | .module_offs = CORE_MOD, | |
473 | .prcm_reg_id = 1, | |
474 | .module_bit = OMAP3430_EN_UART2_SHIFT, | |
475 | .idlest_reg_id = 1, | |
476 | .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, | |
477 | }, | |
478 | }, | |
479 | .class = &omap2_uart_class, | |
870ea2b8 HH |
480 | }; |
481 | ||
844a3b63 PW |
482 | /* UART3 */ |
483 | static struct omap_hwmod omap3xxx_uart3_hwmod = { | |
484 | .name = "uart3", | |
485 | .mpu_irqs = omap2_uart3_mpu_irqs, | |
486 | .sdma_reqs = omap2_uart3_sdma_reqs, | |
487 | .main_clk = "uart3_fck", | |
488 | .prcm = { | |
489 | .omap2 = { | |
490 | .module_offs = OMAP3430_PER_MOD, | |
491 | .prcm_reg_id = 1, | |
492 | .module_bit = OMAP3430_EN_UART3_SHIFT, | |
493 | .idlest_reg_id = 1, | |
494 | .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, | |
495 | }, | |
273ff8c3 | 496 | }, |
844a3b63 | 497 | .class = &omap2_uart_class, |
273ff8c3 HH |
498 | }; |
499 | ||
844a3b63 PW |
500 | /* UART4 */ |
501 | static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { | |
7d7e1eba TL |
502 | { .irq = 80 + OMAP_INTC_START, }, |
503 | { .irq = -1 }, | |
273ff8c3 HH |
504 | }; |
505 | ||
844a3b63 PW |
506 | static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { |
507 | { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, | |
508 | { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, | |
509 | { .dma_req = -1 } | |
7359154e PW |
510 | }; |
511 | ||
844a3b63 PW |
512 | static struct omap_hwmod omap36xx_uart4_hwmod = { |
513 | .name = "uart4", | |
514 | .mpu_irqs = uart4_mpu_irqs, | |
515 | .sdma_reqs = uart4_sdma_reqs, | |
516 | .main_clk = "uart4_fck", | |
517 | .prcm = { | |
518 | .omap2 = { | |
519 | .module_offs = OMAP3430_PER_MOD, | |
520 | .prcm_reg_id = 1, | |
521 | .module_bit = OMAP3630_EN_UART4_SHIFT, | |
522 | .idlest_reg_id = 1, | |
523 | .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, | |
524 | }, | |
525 | }, | |
526 | .class = &omap2_uart_class, | |
7359154e PW |
527 | }; |
528 | ||
844a3b63 | 529 | static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { |
7d7e1eba TL |
530 | { .irq = 84 + OMAP_INTC_START, }, |
531 | { .irq = -1 }, | |
43085705 PW |
532 | }; |
533 | ||
844a3b63 PW |
534 | static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { |
535 | { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, | |
536 | { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, | |
bf765237 | 537 | { .dma_req = -1 } |
7359154e PW |
538 | }; |
539 | ||
82ee620d PW |
540 | /* |
541 | * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or | |
542 | * uart2_fck being enabled. So we add uart1_fck as an optional clock, | |
543 | * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really | |
544 | * should not be needed. The functional clock structure of the AM35xx | |
545 | * UART4 is extremely unclear and opaque; it is unclear what the role | |
546 | * of uart1/2_fck is for the UART4. Any clarification from either | |
547 | * empirical testing or the AM3505/3517 hardware designers would be | |
548 | * most welcome. | |
549 | */ | |
550 | static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = { | |
551 | { .role = "softreset_uart1_fck", .clk = "uart1_fck" }, | |
552 | }; | |
553 | ||
844a3b63 PW |
554 | static struct omap_hwmod am35xx_uart4_hwmod = { |
555 | .name = "uart4", | |
556 | .mpu_irqs = am35xx_uart4_mpu_irqs, | |
557 | .sdma_reqs = am35xx_uart4_sdma_reqs, | |
558 | .main_clk = "uart4_fck", | |
559 | .prcm = { | |
560 | .omap2 = { | |
561 | .module_offs = CORE_MOD, | |
562 | .prcm_reg_id = 1, | |
bf765237 | 563 | .module_bit = AM35XX_EN_UART4_SHIFT, |
844a3b63 | 564 | .idlest_reg_id = 1, |
bf765237 | 565 | .idlest_idle_bit = AM35XX_ST_UART4_SHIFT, |
844a3b63 PW |
566 | }, |
567 | }, | |
82ee620d PW |
568 | .opt_clks = am35xx_uart4_opt_clks, |
569 | .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks), | |
570 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
844a3b63 PW |
571 | .class = &omap2_uart_class, |
572 | }; | |
573 | ||
574 | static struct omap_hwmod_class i2c_class = { | |
575 | .name = "i2c", | |
576 | .sysc = &i2c_sysc, | |
577 | .rev = OMAP_I2C_IP_VERSION_1, | |
578 | .reset = &omap_i2c_reset, | |
579 | }; | |
580 | ||
581 | static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { | |
582 | { .name = "dispc", .dma_req = 5 }, | |
583 | { .name = "dsi1", .dma_req = 74 }, | |
584 | { .dma_req = -1 } | |
43085705 PW |
585 | }; |
586 | ||
844a3b63 PW |
587 | /* dss */ |
588 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |
589 | /* | |
590 | * The DSS HW needs all DSS clocks enabled during reset. The dss_core | |
591 | * driver does not use these clocks. | |
592 | */ | |
593 | { .role = "sys_clk", .clk = "dss2_alwon_fck" }, | |
594 | { .role = "tv_clk", .clk = "dss_tv_fck" }, | |
595 | /* required only on OMAP3430 */ | |
596 | { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, | |
7359154e PW |
597 | }; |
598 | ||
844a3b63 PW |
599 | static struct omap_hwmod omap3430es1_dss_core_hwmod = { |
600 | .name = "dss_core", | |
601 | .class = &omap2_dss_hwmod_class, | |
602 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ | |
603 | .sdma_reqs = omap3xxx_dss_sdma_chs, | |
604 | .prcm = { | |
605 | .omap2 = { | |
606 | .prcm_reg_id = 1, | |
607 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
608 | .module_offs = OMAP3430_DSS_MOD, | |
609 | .idlest_reg_id = 1, | |
610 | .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, | |
611 | }, | |
612 | }, | |
613 | .opt_clks = dss_opt_clks, | |
614 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
615 | .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
616 | }; | |
540064bf | 617 | |
844a3b63 PW |
618 | static struct omap_hwmod omap3xxx_dss_core_hwmod = { |
619 | .name = "dss_core", | |
620 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
621 | .class = &omap2_dss_hwmod_class, | |
622 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ | |
623 | .sdma_reqs = omap3xxx_dss_sdma_chs, | |
624 | .prcm = { | |
625 | .omap2 = { | |
626 | .prcm_reg_id = 1, | |
627 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
628 | .module_offs = OMAP3430_DSS_MOD, | |
629 | .idlest_reg_id = 1, | |
630 | .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, | |
631 | .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, | |
632 | }, | |
633 | }, | |
634 | .opt_clks = dss_opt_clks, | |
635 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
540064bf KH |
636 | }; |
637 | ||
540064bf | 638 | /* |
844a3b63 PW |
639 | * 'dispc' class |
640 | * display controller | |
540064bf KH |
641 | */ |
642 | ||
844a3b63 | 643 | static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { |
ce722d26 TG |
644 | .rev_offs = 0x0000, |
645 | .sysc_offs = 0x0010, | |
646 | .syss_offs = 0x0014, | |
844a3b63 PW |
647 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | |
648 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
649 | SYSC_HAS_ENAWAKEUP), | |
650 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
651 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
ce722d26 | 652 | .sysc_fields = &omap_hwmod_sysc_type1, |
6b667f88 VC |
653 | }; |
654 | ||
844a3b63 PW |
655 | static struct omap_hwmod_class omap3_dispc_hwmod_class = { |
656 | .name = "dispc", | |
657 | .sysc = &omap3_dispc_sysc, | |
6b667f88 VC |
658 | }; |
659 | ||
844a3b63 PW |
660 | static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { |
661 | .name = "dss_dispc", | |
662 | .class = &omap3_dispc_hwmod_class, | |
663 | .mpu_irqs = omap2_dispc_irqs, | |
664 | .main_clk = "dss1_alwon_fck", | |
665 | .prcm = { | |
666 | .omap2 = { | |
667 | .prcm_reg_id = 1, | |
668 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
669 | .module_offs = OMAP3430_DSS_MOD, | |
670 | }, | |
671 | }, | |
672 | .flags = HWMOD_NO_IDLEST, | |
673 | .dev_attr = &omap2_3_dss_dispc_dev_attr | |
6b667f88 VC |
674 | }; |
675 | ||
844a3b63 PW |
676 | /* |
677 | * 'dsi' class | |
678 | * display serial interface controller | |
679 | */ | |
4fe20e97 | 680 | |
844a3b63 PW |
681 | static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { |
682 | .name = "dsi", | |
c345c8b0 TKD |
683 | }; |
684 | ||
844a3b63 | 685 | static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { |
7d7e1eba TL |
686 | { .irq = 25 + OMAP_INTC_START, }, |
687 | { .irq = -1 }, | |
c345c8b0 TKD |
688 | }; |
689 | ||
844a3b63 PW |
690 | /* dss_dsi1 */ |
691 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { | |
692 | { .role = "sys_clk", .clk = "dss2_alwon_fck" }, | |
c345c8b0 TKD |
693 | }; |
694 | ||
844a3b63 PW |
695 | static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { |
696 | .name = "dss_dsi1", | |
697 | .class = &omap3xxx_dsi_hwmod_class, | |
698 | .mpu_irqs = omap3xxx_dsi1_irqs, | |
699 | .main_clk = "dss1_alwon_fck", | |
700 | .prcm = { | |
701 | .omap2 = { | |
702 | .prcm_reg_id = 1, | |
703 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
704 | .module_offs = OMAP3430_DSS_MOD, | |
705 | }, | |
ce722d26 | 706 | }, |
844a3b63 PW |
707 | .opt_clks = dss_dsi1_opt_clks, |
708 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
709 | .flags = HWMOD_NO_IDLEST, | |
6b667f88 VC |
710 | }; |
711 | ||
844a3b63 PW |
712 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
713 | { .role = "ick", .clk = "dss_ick" }, | |
ce722d26 TG |
714 | }; |
715 | ||
844a3b63 PW |
716 | static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { |
717 | .name = "dss_rfbi", | |
718 | .class = &omap2_rfbi_hwmod_class, | |
719 | .main_clk = "dss1_alwon_fck", | |
6b667f88 VC |
720 | .prcm = { |
721 | .omap2 = { | |
722 | .prcm_reg_id = 1, | |
844a3b63 PW |
723 | .module_bit = OMAP3430_EN_DSS1_SHIFT, |
724 | .module_offs = OMAP3430_DSS_MOD, | |
6b667f88 VC |
725 | }, |
726 | }, | |
844a3b63 PW |
727 | .opt_clks = dss_rfbi_opt_clks, |
728 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
729 | .flags = HWMOD_NO_IDLEST, | |
046465b7 KH |
730 | }; |
731 | ||
844a3b63 PW |
732 | static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { |
733 | /* required only on OMAP3430 */ | |
734 | { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, | |
046465b7 KH |
735 | }; |
736 | ||
844a3b63 PW |
737 | static struct omap_hwmod omap3xxx_dss_venc_hwmod = { |
738 | .name = "dss_venc", | |
739 | .class = &omap2_venc_hwmod_class, | |
740 | .main_clk = "dss_tv_fck", | |
046465b7 KH |
741 | .prcm = { |
742 | .omap2 = { | |
046465b7 | 743 | .prcm_reg_id = 1, |
844a3b63 PW |
744 | .module_bit = OMAP3430_EN_DSS1_SHIFT, |
745 | .module_offs = OMAP3430_DSS_MOD, | |
046465b7 KH |
746 | }, |
747 | }, | |
844a3b63 PW |
748 | .opt_clks = dss_venc_opt_clks, |
749 | .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), | |
750 | .flags = HWMOD_NO_IDLEST, | |
046465b7 KH |
751 | }; |
752 | ||
844a3b63 PW |
753 | /* I2C1 */ |
754 | static struct omap_i2c_dev_attr i2c1_dev_attr = { | |
755 | .fifo_depth = 8, /* bytes */ | |
756 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
757 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
758 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
046465b7 KH |
759 | }; |
760 | ||
844a3b63 PW |
761 | static struct omap_hwmod omap3xxx_i2c1_hwmod = { |
762 | .name = "i2c1", | |
763 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
764 | .mpu_irqs = omap2_i2c1_mpu_irqs, | |
765 | .sdma_reqs = omap2_i2c1_sdma_reqs, | |
766 | .main_clk = "i2c1_fck", | |
046465b7 KH |
767 | .prcm = { |
768 | .omap2 = { | |
844a3b63 | 769 | .module_offs = CORE_MOD, |
046465b7 | 770 | .prcm_reg_id = 1, |
844a3b63 | 771 | .module_bit = OMAP3430_EN_I2C1_SHIFT, |
046465b7 | 772 | .idlest_reg_id = 1, |
844a3b63 | 773 | .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, |
046465b7 KH |
774 | }, |
775 | }, | |
844a3b63 PW |
776 | .class = &i2c_class, |
777 | .dev_attr = &i2c1_dev_attr, | |
046465b7 KH |
778 | }; |
779 | ||
844a3b63 PW |
780 | /* I2C2 */ |
781 | static struct omap_i2c_dev_attr i2c2_dev_attr = { | |
782 | .fifo_depth = 8, /* bytes */ | |
783 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
784 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
785 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
046465b7 KH |
786 | }; |
787 | ||
844a3b63 PW |
788 | static struct omap_hwmod omap3xxx_i2c2_hwmod = { |
789 | .name = "i2c2", | |
790 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
791 | .mpu_irqs = omap2_i2c2_mpu_irqs, | |
792 | .sdma_reqs = omap2_i2c2_sdma_reqs, | |
793 | .main_clk = "i2c2_fck", | |
046465b7 KH |
794 | .prcm = { |
795 | .omap2 = { | |
844a3b63 | 796 | .module_offs = CORE_MOD, |
046465b7 | 797 | .prcm_reg_id = 1, |
844a3b63 | 798 | .module_bit = OMAP3430_EN_I2C2_SHIFT, |
046465b7 | 799 | .idlest_reg_id = 1, |
844a3b63 | 800 | .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, |
046465b7 KH |
801 | }, |
802 | }, | |
844a3b63 PW |
803 | .class = &i2c_class, |
804 | .dev_attr = &i2c2_dev_attr, | |
046465b7 KH |
805 | }; |
806 | ||
844a3b63 PW |
807 | /* I2C3 */ |
808 | static struct omap_i2c_dev_attr i2c3_dev_attr = { | |
809 | .fifo_depth = 64, /* bytes */ | |
810 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
811 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
812 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
813 | }; | |
046465b7 | 814 | |
844a3b63 | 815 | static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { |
7d7e1eba TL |
816 | { .irq = 61 + OMAP_INTC_START, }, |
817 | { .irq = -1 }, | |
046465b7 KH |
818 | }; |
819 | ||
844a3b63 PW |
820 | static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { |
821 | { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, | |
822 | { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, | |
823 | { .dma_req = -1 } | |
046465b7 KH |
824 | }; |
825 | ||
844a3b63 PW |
826 | static struct omap_hwmod omap3xxx_i2c3_hwmod = { |
827 | .name = "i2c3", | |
828 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
829 | .mpu_irqs = i2c3_mpu_irqs, | |
830 | .sdma_reqs = i2c3_sdma_reqs, | |
831 | .main_clk = "i2c3_fck", | |
046465b7 KH |
832 | .prcm = { |
833 | .omap2 = { | |
844a3b63 | 834 | .module_offs = CORE_MOD, |
046465b7 | 835 | .prcm_reg_id = 1, |
844a3b63 | 836 | .module_bit = OMAP3430_EN_I2C3_SHIFT, |
046465b7 | 837 | .idlest_reg_id = 1, |
844a3b63 | 838 | .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, |
046465b7 KH |
839 | }, |
840 | }, | |
844a3b63 PW |
841 | .class = &i2c_class, |
842 | .dev_attr = &i2c3_dev_attr, | |
4fe20e97 RN |
843 | }; |
844 | ||
844a3b63 PW |
845 | /* |
846 | * 'gpio' class | |
847 | * general purpose io module | |
848 | */ | |
4fe20e97 | 849 | |
844a3b63 PW |
850 | static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { |
851 | .rev_offs = 0x0000, | |
852 | .sysc_offs = 0x0010, | |
853 | .syss_offs = 0x0014, | |
854 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
855 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
856 | SYSS_HAS_RESET_STATUS), | |
857 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
858 | .sysc_fields = &omap_hwmod_sysc_type1, | |
4fe20e97 RN |
859 | }; |
860 | ||
844a3b63 PW |
861 | static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { |
862 | .name = "gpio", | |
863 | .sysc = &omap3xxx_gpio_sysc, | |
864 | .rev = 1, | |
4fe20e97 RN |
865 | }; |
866 | ||
844a3b63 PW |
867 | /* gpio_dev_attr */ |
868 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
869 | .bank_width = 32, | |
870 | .dbck_flag = true, | |
871 | }; | |
872 | ||
873 | /* gpio1 */ | |
874 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | |
875 | { .role = "dbclk", .clk = "gpio1_dbck", }, | |
876 | }; | |
877 | ||
878 | static struct omap_hwmod omap3xxx_gpio1_hwmod = { | |
879 | .name = "gpio1", | |
880 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
881 | .mpu_irqs = omap2_gpio1_irqs, | |
882 | .main_clk = "gpio1_ick", | |
883 | .opt_clks = gpio1_opt_clks, | |
884 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
4fe20e97 RN |
885 | .prcm = { |
886 | .omap2 = { | |
4fe20e97 | 887 | .prcm_reg_id = 1, |
844a3b63 PW |
888 | .module_bit = OMAP3430_EN_GPIO1_SHIFT, |
889 | .module_offs = WKUP_MOD, | |
4fe20e97 | 890 | .idlest_reg_id = 1, |
844a3b63 | 891 | .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, |
4fe20e97 RN |
892 | }, |
893 | }, | |
844a3b63 PW |
894 | .class = &omap3xxx_gpio_hwmod_class, |
895 | .dev_attr = &gpio_dev_attr, | |
4fe20e97 RN |
896 | }; |
897 | ||
844a3b63 PW |
898 | /* gpio2 */ |
899 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | |
900 | { .role = "dbclk", .clk = "gpio2_dbck", }, | |
4fe20e97 RN |
901 | }; |
902 | ||
844a3b63 PW |
903 | static struct omap_hwmod omap3xxx_gpio2_hwmod = { |
904 | .name = "gpio2", | |
905 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
906 | .mpu_irqs = omap2_gpio2_irqs, | |
907 | .main_clk = "gpio2_ick", | |
908 | .opt_clks = gpio2_opt_clks, | |
909 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
4fe20e97 RN |
910 | .prcm = { |
911 | .omap2 = { | |
4fe20e97 | 912 | .prcm_reg_id = 1, |
844a3b63 | 913 | .module_bit = OMAP3430_EN_GPIO2_SHIFT, |
ce722d26 | 914 | .module_offs = OMAP3430_PER_MOD, |
4fe20e97 | 915 | .idlest_reg_id = 1, |
844a3b63 | 916 | .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, |
4fe20e97 RN |
917 | }, |
918 | }, | |
844a3b63 PW |
919 | .class = &omap3xxx_gpio_hwmod_class, |
920 | .dev_attr = &gpio_dev_attr, | |
4fe20e97 RN |
921 | }; |
922 | ||
844a3b63 PW |
923 | /* gpio3 */ |
924 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { | |
925 | { .role = "dbclk", .clk = "gpio3_dbck", }, | |
4fe20e97 RN |
926 | }; |
927 | ||
844a3b63 PW |
928 | static struct omap_hwmod omap3xxx_gpio3_hwmod = { |
929 | .name = "gpio3", | |
930 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
931 | .mpu_irqs = omap2_gpio3_irqs, | |
932 | .main_clk = "gpio3_ick", | |
933 | .opt_clks = gpio3_opt_clks, | |
934 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
4fe20e97 RN |
935 | .prcm = { |
936 | .omap2 = { | |
4fe20e97 | 937 | .prcm_reg_id = 1, |
844a3b63 | 938 | .module_bit = OMAP3430_EN_GPIO3_SHIFT, |
ce722d26 | 939 | .module_offs = OMAP3430_PER_MOD, |
4fe20e97 | 940 | .idlest_reg_id = 1, |
844a3b63 | 941 | .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, |
4fe20e97 RN |
942 | }, |
943 | }, | |
844a3b63 PW |
944 | .class = &omap3xxx_gpio_hwmod_class, |
945 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
946 | }; |
947 | ||
844a3b63 PW |
948 | /* gpio4 */ |
949 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { | |
950 | { .role = "dbclk", .clk = "gpio4_dbck", }, | |
70034d38 VC |
951 | }; |
952 | ||
844a3b63 PW |
953 | static struct omap_hwmod omap3xxx_gpio4_hwmod = { |
954 | .name = "gpio4", | |
955 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
956 | .mpu_irqs = omap2_gpio4_irqs, | |
957 | .main_clk = "gpio4_ick", | |
958 | .opt_clks = gpio4_opt_clks, | |
959 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
ce722d26 TG |
960 | .prcm = { |
961 | .omap2 = { | |
962 | .prcm_reg_id = 1, | |
844a3b63 | 963 | .module_bit = OMAP3430_EN_GPIO4_SHIFT, |
ce722d26 TG |
964 | .module_offs = OMAP3430_PER_MOD, |
965 | .idlest_reg_id = 1, | |
844a3b63 | 966 | .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, |
ce722d26 | 967 | }, |
70034d38 | 968 | }, |
844a3b63 PW |
969 | .class = &omap3xxx_gpio_hwmod_class, |
970 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
971 | }; |
972 | ||
844a3b63 PW |
973 | /* gpio5 */ |
974 | static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { | |
7d7e1eba TL |
975 | { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */ |
976 | { .irq = -1 }, | |
844a3b63 | 977 | }; |
70034d38 | 978 | |
844a3b63 PW |
979 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
980 | { .role = "dbclk", .clk = "gpio5_dbck", }, | |
70034d38 VC |
981 | }; |
982 | ||
844a3b63 PW |
983 | static struct omap_hwmod omap3xxx_gpio5_hwmod = { |
984 | .name = "gpio5", | |
985 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
986 | .mpu_irqs = omap3xxx_gpio5_irqs, | |
987 | .main_clk = "gpio5_ick", | |
988 | .opt_clks = gpio5_opt_clks, | |
989 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
ce722d26 TG |
990 | .prcm = { |
991 | .omap2 = { | |
992 | .prcm_reg_id = 1, | |
844a3b63 PW |
993 | .module_bit = OMAP3430_EN_GPIO5_SHIFT, |
994 | .module_offs = OMAP3430_PER_MOD, | |
ce722d26 | 995 | .idlest_reg_id = 1, |
844a3b63 | 996 | .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, |
ce722d26 | 997 | }, |
70034d38 | 998 | }, |
844a3b63 PW |
999 | .class = &omap3xxx_gpio_hwmod_class, |
1000 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
1001 | }; |
1002 | ||
844a3b63 PW |
1003 | /* gpio6 */ |
1004 | static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { | |
7d7e1eba TL |
1005 | { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */ |
1006 | { .irq = -1 }, | |
844a3b63 | 1007 | }; |
70034d38 | 1008 | |
844a3b63 PW |
1009 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
1010 | { .role = "dbclk", .clk = "gpio6_dbck", }, | |
70034d38 VC |
1011 | }; |
1012 | ||
844a3b63 PW |
1013 | static struct omap_hwmod omap3xxx_gpio6_hwmod = { |
1014 | .name = "gpio6", | |
1015 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
1016 | .mpu_irqs = omap3xxx_gpio6_irqs, | |
1017 | .main_clk = "gpio6_ick", | |
1018 | .opt_clks = gpio6_opt_clks, | |
1019 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
ce722d26 TG |
1020 | .prcm = { |
1021 | .omap2 = { | |
1022 | .prcm_reg_id = 1, | |
844a3b63 PW |
1023 | .module_bit = OMAP3430_EN_GPIO6_SHIFT, |
1024 | .module_offs = OMAP3430_PER_MOD, | |
ce722d26 | 1025 | .idlest_reg_id = 1, |
844a3b63 | 1026 | .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, |
ce722d26 TG |
1027 | }, |
1028 | }, | |
844a3b63 PW |
1029 | .class = &omap3xxx_gpio_hwmod_class, |
1030 | .dev_attr = &gpio_dev_attr, | |
ce722d26 TG |
1031 | }; |
1032 | ||
844a3b63 PW |
1033 | /* dma attributes */ |
1034 | static struct omap_dma_dev_attr dma_dev_attr = { | |
1035 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
1036 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
1037 | .lch_count = 32, | |
ce722d26 TG |
1038 | }; |
1039 | ||
844a3b63 PW |
1040 | static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { |
1041 | .rev_offs = 0x0000, | |
1042 | .sysc_offs = 0x002c, | |
1043 | .syss_offs = 0x0028, | |
1044 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1045 | SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
1046 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | | |
1047 | SYSS_HAS_RESET_STATUS), | |
1048 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1049 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1050 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1051 | }; |
1052 | ||
844a3b63 PW |
1053 | static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { |
1054 | .name = "dma", | |
1055 | .sysc = &omap3xxx_dma_sysc, | |
70034d38 VC |
1056 | }; |
1057 | ||
844a3b63 PW |
1058 | /* dma_system */ |
1059 | static struct omap_hwmod omap3xxx_dma_system_hwmod = { | |
1060 | .name = "dma", | |
1061 | .class = &omap3xxx_dma_hwmod_class, | |
1062 | .mpu_irqs = omap2_dma_system_irqs, | |
1063 | .main_clk = "core_l3_ick", | |
1064 | .prcm = { | |
ce722d26 | 1065 | .omap2 = { |
844a3b63 PW |
1066 | .module_offs = CORE_MOD, |
1067 | .prcm_reg_id = 1, | |
1068 | .module_bit = OMAP3430_ST_SDMA_SHIFT, | |
1069 | .idlest_reg_id = 1, | |
1070 | .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, | |
ce722d26 TG |
1071 | }, |
1072 | }, | |
844a3b63 PW |
1073 | .dev_attr = &dma_dev_attr, |
1074 | .flags = HWMOD_NO_IDLEST, | |
70034d38 VC |
1075 | }; |
1076 | ||
844a3b63 PW |
1077 | /* |
1078 | * 'mcbsp' class | |
1079 | * multi channel buffered serial port controller | |
1080 | */ | |
1081 | ||
1082 | static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { | |
1083 | .sysc_offs = 0x008c, | |
1084 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
1085 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1086 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1087 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1088 | .clockact = 0x2, | |
70034d38 VC |
1089 | }; |
1090 | ||
844a3b63 PW |
1091 | static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { |
1092 | .name = "mcbsp", | |
1093 | .sysc = &omap3xxx_mcbsp_sysc, | |
1094 | .rev = MCBSP_CONFIG_TYPE3, | |
70034d38 VC |
1095 | }; |
1096 | ||
7039154b PU |
1097 | /* McBSP functional clock mapping */ |
1098 | static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = { | |
1099 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | |
1100 | { .role = "prcm_fck", .clk = "core_96m_fck" }, | |
1101 | }; | |
1102 | ||
1103 | static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = { | |
1104 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | |
1105 | { .role = "prcm_fck", .clk = "per_96m_fck" }, | |
1106 | }; | |
1107 | ||
844a3b63 PW |
1108 | /* mcbsp1 */ |
1109 | static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { | |
7d7e1eba TL |
1110 | { .name = "common", .irq = 16 + OMAP_INTC_START, }, |
1111 | { .name = "tx", .irq = 59 + OMAP_INTC_START, }, | |
1112 | { .name = "rx", .irq = 60 + OMAP_INTC_START, }, | |
1113 | { .irq = -1 }, | |
844a3b63 | 1114 | }; |
6b667f88 | 1115 | |
844a3b63 PW |
1116 | static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { |
1117 | .name = "mcbsp1", | |
1118 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1119 | .mpu_irqs = omap3xxx_mcbsp1_irqs, | |
1120 | .sdma_reqs = omap2_mcbsp1_sdma_reqs, | |
1121 | .main_clk = "mcbsp1_fck", | |
1122 | .prcm = { | |
1123 | .omap2 = { | |
1124 | .prcm_reg_id = 1, | |
1125 | .module_bit = OMAP3430_EN_MCBSP1_SHIFT, | |
1126 | .module_offs = CORE_MOD, | |
1127 | .idlest_reg_id = 1, | |
1128 | .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, | |
1129 | }, | |
1130 | }, | |
7039154b PU |
1131 | .opt_clks = mcbsp15_opt_clks, |
1132 | .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), | |
70034d38 VC |
1133 | }; |
1134 | ||
844a3b63 PW |
1135 | /* mcbsp2 */ |
1136 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { | |
7d7e1eba TL |
1137 | { .name = "common", .irq = 17 + OMAP_INTC_START, }, |
1138 | { .name = "tx", .irq = 62 + OMAP_INTC_START, }, | |
1139 | { .name = "rx", .irq = 63 + OMAP_INTC_START, }, | |
1140 | { .irq = -1 }, | |
70034d38 VC |
1141 | }; |
1142 | ||
844a3b63 PW |
1143 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { |
1144 | .sidetone = "mcbsp2_sidetone", | |
70034d38 VC |
1145 | }; |
1146 | ||
844a3b63 PW |
1147 | static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { |
1148 | .name = "mcbsp2", | |
1149 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1150 | .mpu_irqs = omap3xxx_mcbsp2_irqs, | |
1151 | .sdma_reqs = omap2_mcbsp2_sdma_reqs, | |
1152 | .main_clk = "mcbsp2_fck", | |
70034d38 VC |
1153 | .prcm = { |
1154 | .omap2 = { | |
1155 | .prcm_reg_id = 1, | |
844a3b63 PW |
1156 | .module_bit = OMAP3430_EN_MCBSP2_SHIFT, |
1157 | .module_offs = OMAP3430_PER_MOD, | |
70034d38 | 1158 | .idlest_reg_id = 1, |
844a3b63 | 1159 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, |
70034d38 VC |
1160 | }, |
1161 | }, | |
7039154b PU |
1162 | .opt_clks = mcbsp234_opt_clks, |
1163 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | |
844a3b63 | 1164 | .dev_attr = &omap34xx_mcbsp2_dev_attr, |
70034d38 VC |
1165 | }; |
1166 | ||
844a3b63 PW |
1167 | /* mcbsp3 */ |
1168 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { | |
7d7e1eba TL |
1169 | { .name = "common", .irq = 22 + OMAP_INTC_START, }, |
1170 | { .name = "tx", .irq = 89 + OMAP_INTC_START, }, | |
1171 | { .name = "rx", .irq = 90 + OMAP_INTC_START, }, | |
1172 | { .irq = -1 }, | |
844a3b63 PW |
1173 | }; |
1174 | ||
1175 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { | |
1176 | .sidetone = "mcbsp3_sidetone", | |
1177 | }; | |
1178 | ||
1179 | static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { | |
1180 | .name = "mcbsp3", | |
1181 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1182 | .mpu_irqs = omap3xxx_mcbsp3_irqs, | |
1183 | .sdma_reqs = omap2_mcbsp3_sdma_reqs, | |
1184 | .main_clk = "mcbsp3_fck", | |
70034d38 VC |
1185 | .prcm = { |
1186 | .omap2 = { | |
1187 | .prcm_reg_id = 1, | |
844a3b63 PW |
1188 | .module_bit = OMAP3430_EN_MCBSP3_SHIFT, |
1189 | .module_offs = OMAP3430_PER_MOD, | |
70034d38 | 1190 | .idlest_reg_id = 1, |
844a3b63 | 1191 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, |
70034d38 VC |
1192 | }, |
1193 | }, | |
7039154b PU |
1194 | .opt_clks = mcbsp234_opt_clks, |
1195 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | |
844a3b63 | 1196 | .dev_attr = &omap34xx_mcbsp3_dev_attr, |
70034d38 VC |
1197 | }; |
1198 | ||
844a3b63 PW |
1199 | /* mcbsp4 */ |
1200 | static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { | |
7d7e1eba TL |
1201 | { .name = "common", .irq = 23 + OMAP_INTC_START, }, |
1202 | { .name = "tx", .irq = 54 + OMAP_INTC_START, }, | |
1203 | { .name = "rx", .irq = 55 + OMAP_INTC_START, }, | |
1204 | { .irq = -1 }, | |
844a3b63 PW |
1205 | }; |
1206 | ||
1207 | static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { | |
1208 | { .name = "rx", .dma_req = 20 }, | |
1209 | { .name = "tx", .dma_req = 19 }, | |
1210 | { .dma_req = -1 } | |
1211 | }; | |
1212 | ||
1213 | static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { | |
1214 | .name = "mcbsp4", | |
1215 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1216 | .mpu_irqs = omap3xxx_mcbsp4_irqs, | |
1217 | .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, | |
1218 | .main_clk = "mcbsp4_fck", | |
70034d38 VC |
1219 | .prcm = { |
1220 | .omap2 = { | |
1221 | .prcm_reg_id = 1, | |
844a3b63 PW |
1222 | .module_bit = OMAP3430_EN_MCBSP4_SHIFT, |
1223 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 1224 | .idlest_reg_id = 1, |
844a3b63 | 1225 | .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, |
046465b7 KH |
1226 | }, |
1227 | }, | |
7039154b PU |
1228 | .opt_clks = mcbsp234_opt_clks, |
1229 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | |
046465b7 KH |
1230 | }; |
1231 | ||
844a3b63 PW |
1232 | /* mcbsp5 */ |
1233 | static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { | |
7d7e1eba TL |
1234 | { .name = "common", .irq = 27 + OMAP_INTC_START, }, |
1235 | { .name = "tx", .irq = 81 + OMAP_INTC_START, }, | |
1236 | { .name = "rx", .irq = 82 + OMAP_INTC_START, }, | |
1237 | { .irq = -1 }, | |
844a3b63 PW |
1238 | }; |
1239 | ||
1240 | static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { | |
1241 | { .name = "rx", .dma_req = 22 }, | |
1242 | { .name = "tx", .dma_req = 21 }, | |
1243 | { .dma_req = -1 } | |
1244 | }; | |
1245 | ||
1246 | static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { | |
1247 | .name = "mcbsp5", | |
1248 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1249 | .mpu_irqs = omap3xxx_mcbsp5_irqs, | |
1250 | .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, | |
1251 | .main_clk = "mcbsp5_fck", | |
046465b7 KH |
1252 | .prcm = { |
1253 | .omap2 = { | |
046465b7 | 1254 | .prcm_reg_id = 1, |
844a3b63 PW |
1255 | .module_bit = OMAP3430_EN_MCBSP5_SHIFT, |
1256 | .module_offs = CORE_MOD, | |
70034d38 | 1257 | .idlest_reg_id = 1, |
844a3b63 | 1258 | .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, |
70034d38 VC |
1259 | }, |
1260 | }, | |
7039154b PU |
1261 | .opt_clks = mcbsp15_opt_clks, |
1262 | .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), | |
70034d38 VC |
1263 | }; |
1264 | ||
844a3b63 PW |
1265 | /* 'mcbsp sidetone' class */ |
1266 | static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { | |
1267 | .sysc_offs = 0x0010, | |
1268 | .sysc_flags = SYSC_HAS_AUTOIDLE, | |
1269 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1270 | }; | |
046465b7 | 1271 | |
844a3b63 PW |
1272 | static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { |
1273 | .name = "mcbsp_sidetone", | |
1274 | .sysc = &omap3xxx_mcbsp_sidetone_sysc, | |
70034d38 VC |
1275 | }; |
1276 | ||
844a3b63 PW |
1277 | /* mcbsp2_sidetone */ |
1278 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { | |
7d7e1eba TL |
1279 | { .name = "irq", .irq = 4 + OMAP_INTC_START, }, |
1280 | { .irq = -1 }, | |
70034d38 VC |
1281 | }; |
1282 | ||
844a3b63 PW |
1283 | static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { |
1284 | .name = "mcbsp2_sidetone", | |
1285 | .class = &omap3xxx_mcbsp_sidetone_hwmod_class, | |
1286 | .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, | |
1287 | .main_clk = "mcbsp2_fck", | |
046465b7 KH |
1288 | .prcm = { |
1289 | .omap2 = { | |
046465b7 | 1290 | .prcm_reg_id = 1, |
844a3b63 PW |
1291 | .module_bit = OMAP3430_EN_MCBSP2_SHIFT, |
1292 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 1293 | .idlest_reg_id = 1, |
844a3b63 | 1294 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, |
046465b7 KH |
1295 | }, |
1296 | }, | |
4bf90f65 KM |
1297 | }; |
1298 | ||
844a3b63 PW |
1299 | /* mcbsp3_sidetone */ |
1300 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { | |
7d7e1eba TL |
1301 | { .name = "irq", .irq = 5 + OMAP_INTC_START, }, |
1302 | { .irq = -1 }, | |
4bf90f65 KM |
1303 | }; |
1304 | ||
844a3b63 PW |
1305 | static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { |
1306 | .name = "mcbsp3_sidetone", | |
1307 | .class = &omap3xxx_mcbsp_sidetone_hwmod_class, | |
1308 | .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, | |
1309 | .main_clk = "mcbsp3_fck", | |
0a78c5c5 | 1310 | .prcm = { |
4bf90f65 | 1311 | .omap2 = { |
4bf90f65 | 1312 | .prcm_reg_id = 1, |
844a3b63 PW |
1313 | .module_bit = OMAP3430_EN_MCBSP3_SHIFT, |
1314 | .module_offs = OMAP3430_PER_MOD, | |
4bf90f65 | 1315 | .idlest_reg_id = 1, |
844a3b63 | 1316 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, |
4bf90f65 KM |
1317 | }, |
1318 | }, | |
4bf90f65 KM |
1319 | }; |
1320 | ||
844a3b63 PW |
1321 | /* SR common */ |
1322 | static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { | |
1323 | .clkact_shift = 20, | |
1324 | }; | |
4bf90f65 | 1325 | |
844a3b63 PW |
1326 | static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { |
1327 | .sysc_offs = 0x24, | |
1328 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), | |
1329 | .clockact = CLOCKACT_TEST_ICLK, | |
1330 | .sysc_fields = &omap34xx_sr_sysc_fields, | |
4fe20e97 RN |
1331 | }; |
1332 | ||
844a3b63 PW |
1333 | static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { |
1334 | .name = "smartreflex", | |
1335 | .sysc = &omap34xx_sr_sysc, | |
1336 | .rev = 1, | |
e04d9e1e SG |
1337 | }; |
1338 | ||
844a3b63 PW |
1339 | static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { |
1340 | .sidle_shift = 24, | |
1341 | .enwkup_shift = 26, | |
1342 | }; | |
e04d9e1e | 1343 | |
844a3b63 PW |
1344 | static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { |
1345 | .sysc_offs = 0x38, | |
1346 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1347 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
1348 | SYSC_NO_CACHE), | |
1349 | .sysc_fields = &omap36xx_sr_sysc_fields, | |
1350 | }; | |
1351 | ||
1352 | static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { | |
1353 | .name = "smartreflex", | |
1354 | .sysc = &omap36xx_sr_sysc, | |
1355 | .rev = 2, | |
1356 | }; | |
1357 | ||
1358 | /* SR1 */ | |
1359 | static struct omap_smartreflex_dev_attr sr1_dev_attr = { | |
1360 | .sensor_voltdm_name = "mpu_iva", | |
1361 | }; | |
1362 | ||
1363 | static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { | |
7d7e1eba TL |
1364 | { .irq = 18 + OMAP_INTC_START, }, |
1365 | { .irq = -1 }, | |
844a3b63 PW |
1366 | }; |
1367 | ||
1368 | static struct omap_hwmod omap34xx_sr1_hwmod = { | |
1fcd3069 | 1369 | .name = "smartreflex_mpu_iva", |
844a3b63 PW |
1370 | .class = &omap34xx_smartreflex_hwmod_class, |
1371 | .main_clk = "sr1_fck", | |
1372 | .prcm = { | |
e04d9e1e | 1373 | .omap2 = { |
844a3b63 PW |
1374 | .prcm_reg_id = 1, |
1375 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
1376 | .module_offs = WKUP_MOD, | |
1377 | .idlest_reg_id = 1, | |
1378 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
1379 | }, | |
e04d9e1e | 1380 | }, |
844a3b63 PW |
1381 | .dev_attr = &sr1_dev_attr, |
1382 | .mpu_irqs = omap3_smartreflex_mpu_irqs, | |
1383 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
e04d9e1e SG |
1384 | }; |
1385 | ||
844a3b63 | 1386 | static struct omap_hwmod omap36xx_sr1_hwmod = { |
1fcd3069 | 1387 | .name = "smartreflex_mpu_iva", |
844a3b63 PW |
1388 | .class = &omap36xx_smartreflex_hwmod_class, |
1389 | .main_clk = "sr1_fck", | |
1390 | .prcm = { | |
e04d9e1e | 1391 | .omap2 = { |
844a3b63 PW |
1392 | .prcm_reg_id = 1, |
1393 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
1394 | .module_offs = WKUP_MOD, | |
1395 | .idlest_reg_id = 1, | |
1396 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
1397 | }, | |
e04d9e1e | 1398 | }, |
844a3b63 PW |
1399 | .dev_attr = &sr1_dev_attr, |
1400 | .mpu_irqs = omap3_smartreflex_mpu_irqs, | |
e04d9e1e SG |
1401 | }; |
1402 | ||
844a3b63 PW |
1403 | /* SR2 */ |
1404 | static struct omap_smartreflex_dev_attr sr2_dev_attr = { | |
1405 | .sensor_voltdm_name = "core", | |
e04d9e1e SG |
1406 | }; |
1407 | ||
844a3b63 | 1408 | static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { |
7d7e1eba TL |
1409 | { .irq = 19 + OMAP_INTC_START, }, |
1410 | { .irq = -1 }, | |
844a3b63 PW |
1411 | }; |
1412 | ||
1413 | static struct omap_hwmod omap34xx_sr2_hwmod = { | |
1fcd3069 | 1414 | .name = "smartreflex_core", |
844a3b63 PW |
1415 | .class = &omap34xx_smartreflex_hwmod_class, |
1416 | .main_clk = "sr2_fck", | |
e04d9e1e SG |
1417 | .prcm = { |
1418 | .omap2 = { | |
1419 | .prcm_reg_id = 1, | |
844a3b63 PW |
1420 | .module_bit = OMAP3430_EN_SR2_SHIFT, |
1421 | .module_offs = WKUP_MOD, | |
e04d9e1e | 1422 | .idlest_reg_id = 1, |
844a3b63 | 1423 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, |
e04d9e1e SG |
1424 | }, |
1425 | }, | |
844a3b63 PW |
1426 | .dev_attr = &sr2_dev_attr, |
1427 | .mpu_irqs = omap3_smartreflex_core_irqs, | |
1428 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
e04d9e1e SG |
1429 | }; |
1430 | ||
844a3b63 | 1431 | static struct omap_hwmod omap36xx_sr2_hwmod = { |
1fcd3069 | 1432 | .name = "smartreflex_core", |
844a3b63 PW |
1433 | .class = &omap36xx_smartreflex_hwmod_class, |
1434 | .main_clk = "sr2_fck", | |
e04d9e1e SG |
1435 | .prcm = { |
1436 | .omap2 = { | |
1437 | .prcm_reg_id = 1, | |
844a3b63 PW |
1438 | .module_bit = OMAP3430_EN_SR2_SHIFT, |
1439 | .module_offs = WKUP_MOD, | |
e04d9e1e | 1440 | .idlest_reg_id = 1, |
844a3b63 | 1441 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, |
e04d9e1e SG |
1442 | }, |
1443 | }, | |
844a3b63 PW |
1444 | .dev_attr = &sr2_dev_attr, |
1445 | .mpu_irqs = omap3_smartreflex_core_irqs, | |
e04d9e1e SG |
1446 | }; |
1447 | ||
1ac6d46e | 1448 | /* |
844a3b63 PW |
1449 | * 'mailbox' class |
1450 | * mailbox module allowing communication between the on-chip processors | |
1451 | * using a queued mailbox-interrupt mechanism. | |
1ac6d46e TV |
1452 | */ |
1453 | ||
844a3b63 PW |
1454 | static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { |
1455 | .rev_offs = 0x000, | |
1456 | .sysc_offs = 0x010, | |
1457 | .syss_offs = 0x014, | |
1458 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1459 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1460 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1ac6d46e TV |
1461 | .sysc_fields = &omap_hwmod_sysc_type1, |
1462 | }; | |
1463 | ||
844a3b63 PW |
1464 | static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { |
1465 | .name = "mailbox", | |
1466 | .sysc = &omap3xxx_mailbox_sysc, | |
1ac6d46e TV |
1467 | }; |
1468 | ||
844a3b63 | 1469 | static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { |
7d7e1eba TL |
1470 | { .irq = 26 + OMAP_INTC_START, }, |
1471 | { .irq = -1 }, | |
e04d9e1e SG |
1472 | }; |
1473 | ||
844a3b63 PW |
1474 | static struct omap_hwmod omap3xxx_mailbox_hwmod = { |
1475 | .name = "mailbox", | |
1476 | .class = &omap3xxx_mailbox_hwmod_class, | |
1477 | .mpu_irqs = omap3xxx_mailbox_irqs, | |
1478 | .main_clk = "mailboxes_ick", | |
e04d9e1e SG |
1479 | .prcm = { |
1480 | .omap2 = { | |
1481 | .prcm_reg_id = 1, | |
844a3b63 PW |
1482 | .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, |
1483 | .module_offs = CORE_MOD, | |
1484 | .idlest_reg_id = 1, | |
1485 | .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, | |
e04d9e1e SG |
1486 | }, |
1487 | }, | |
e04d9e1e SG |
1488 | }; |
1489 | ||
1490 | /* | |
844a3b63 PW |
1491 | * 'mcspi' class |
1492 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
1493 | * bus | |
e04d9e1e SG |
1494 | */ |
1495 | ||
844a3b63 PW |
1496 | static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { |
1497 | .rev_offs = 0x0000, | |
1498 | .sysc_offs = 0x0010, | |
1499 | .syss_offs = 0x0014, | |
1500 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1501 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1502 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1503 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1504 | .sysc_fields = &omap_hwmod_sysc_type1, | |
e04d9e1e SG |
1505 | }; |
1506 | ||
844a3b63 PW |
1507 | static struct omap_hwmod_class omap34xx_mcspi_class = { |
1508 | .name = "mcspi", | |
1509 | .sysc = &omap34xx_mcspi_sysc, | |
1510 | .rev = OMAP3_MCSPI_REV, | |
affe360d | 1511 | }; |
1512 | ||
844a3b63 PW |
1513 | /* mcspi1 */ |
1514 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { | |
1515 | .num_chipselect = 4, | |
e04d9e1e SG |
1516 | }; |
1517 | ||
844a3b63 PW |
1518 | static struct omap_hwmod omap34xx_mcspi1 = { |
1519 | .name = "mcspi1", | |
1520 | .mpu_irqs = omap2_mcspi1_mpu_irqs, | |
1521 | .sdma_reqs = omap2_mcspi1_sdma_reqs, | |
1522 | .main_clk = "mcspi1_fck", | |
1523 | .prcm = { | |
e04d9e1e | 1524 | .omap2 = { |
844a3b63 PW |
1525 | .module_offs = CORE_MOD, |
1526 | .prcm_reg_id = 1, | |
1527 | .module_bit = OMAP3430_EN_MCSPI1_SHIFT, | |
1528 | .idlest_reg_id = 1, | |
1529 | .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, | |
1530 | }, | |
e04d9e1e | 1531 | }, |
844a3b63 PW |
1532 | .class = &omap34xx_mcspi_class, |
1533 | .dev_attr = &omap_mcspi1_dev_attr, | |
e04d9e1e SG |
1534 | }; |
1535 | ||
844a3b63 PW |
1536 | /* mcspi2 */ |
1537 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { | |
1538 | .num_chipselect = 2, | |
6c3d7e34 TV |
1539 | }; |
1540 | ||
844a3b63 PW |
1541 | static struct omap_hwmod omap34xx_mcspi2 = { |
1542 | .name = "mcspi2", | |
1543 | .mpu_irqs = omap2_mcspi2_mpu_irqs, | |
1544 | .sdma_reqs = omap2_mcspi2_sdma_reqs, | |
1545 | .main_clk = "mcspi2_fck", | |
e04d9e1e SG |
1546 | .prcm = { |
1547 | .omap2 = { | |
844a3b63 | 1548 | .module_offs = CORE_MOD, |
e04d9e1e | 1549 | .prcm_reg_id = 1, |
844a3b63 PW |
1550 | .module_bit = OMAP3430_EN_MCSPI2_SHIFT, |
1551 | .idlest_reg_id = 1, | |
1552 | .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, | |
e04d9e1e SG |
1553 | }, |
1554 | }, | |
844a3b63 PW |
1555 | .class = &omap34xx_mcspi_class, |
1556 | .dev_attr = &omap_mcspi2_dev_attr, | |
e04d9e1e SG |
1557 | }; |
1558 | ||
844a3b63 PW |
1559 | /* mcspi3 */ |
1560 | static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { | |
7d7e1eba TL |
1561 | { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */ |
1562 | { .irq = -1 }, | |
844a3b63 PW |
1563 | }; |
1564 | ||
1565 | static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { | |
1566 | { .name = "tx0", .dma_req = 15 }, | |
1567 | { .name = "rx0", .dma_req = 16 }, | |
1568 | { .name = "tx1", .dma_req = 23 }, | |
1569 | { .name = "rx1", .dma_req = 24 }, | |
1570 | { .dma_req = -1 } | |
e04d9e1e SG |
1571 | }; |
1572 | ||
844a3b63 PW |
1573 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { |
1574 | .num_chipselect = 2, | |
6c3d7e34 TV |
1575 | }; |
1576 | ||
844a3b63 PW |
1577 | static struct omap_hwmod omap34xx_mcspi3 = { |
1578 | .name = "mcspi3", | |
1579 | .mpu_irqs = omap34xx_mcspi3_mpu_irqs, | |
1580 | .sdma_reqs = omap34xx_mcspi3_sdma_reqs, | |
1581 | .main_clk = "mcspi3_fck", | |
e04d9e1e SG |
1582 | .prcm = { |
1583 | .omap2 = { | |
844a3b63 | 1584 | .module_offs = CORE_MOD, |
e04d9e1e | 1585 | .prcm_reg_id = 1, |
844a3b63 PW |
1586 | .module_bit = OMAP3430_EN_MCSPI3_SHIFT, |
1587 | .idlest_reg_id = 1, | |
1588 | .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, | |
e04d9e1e SG |
1589 | }, |
1590 | }, | |
844a3b63 PW |
1591 | .class = &omap34xx_mcspi_class, |
1592 | .dev_attr = &omap_mcspi3_dev_attr, | |
e04d9e1e SG |
1593 | }; |
1594 | ||
844a3b63 PW |
1595 | /* mcspi4 */ |
1596 | static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { | |
7d7e1eba TL |
1597 | { .name = "irq", .irq = 48 + OMAP_INTC_START, }, |
1598 | { .irq = -1 }, | |
e04d9e1e SG |
1599 | }; |
1600 | ||
844a3b63 PW |
1601 | static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { |
1602 | { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ | |
1603 | { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ | |
1604 | { .dma_req = -1 } | |
6c3d7e34 TV |
1605 | }; |
1606 | ||
844a3b63 PW |
1607 | static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { |
1608 | .num_chipselect = 1, | |
1609 | }; | |
1610 | ||
1611 | static struct omap_hwmod omap34xx_mcspi4 = { | |
1612 | .name = "mcspi4", | |
1613 | .mpu_irqs = omap34xx_mcspi4_mpu_irqs, | |
1614 | .sdma_reqs = omap34xx_mcspi4_sdma_reqs, | |
1615 | .main_clk = "mcspi4_fck", | |
e04d9e1e SG |
1616 | .prcm = { |
1617 | .omap2 = { | |
844a3b63 | 1618 | .module_offs = CORE_MOD, |
e04d9e1e | 1619 | .prcm_reg_id = 1, |
844a3b63 PW |
1620 | .module_bit = OMAP3430_EN_MCSPI4_SHIFT, |
1621 | .idlest_reg_id = 1, | |
1622 | .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, | |
e04d9e1e SG |
1623 | }, |
1624 | }, | |
844a3b63 PW |
1625 | .class = &omap34xx_mcspi_class, |
1626 | .dev_attr = &omap_mcspi4_dev_attr, | |
e04d9e1e SG |
1627 | }; |
1628 | ||
844a3b63 PW |
1629 | /* usbhsotg */ |
1630 | static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { | |
1631 | .rev_offs = 0x0400, | |
1632 | .sysc_offs = 0x0404, | |
1633 | .syss_offs = 0x0408, | |
1634 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| | |
1635 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1636 | SYSC_HAS_AUTOIDLE), | |
1637 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1638 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1639 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1640 | }; | |
4fe20e97 | 1641 | |
844a3b63 PW |
1642 | static struct omap_hwmod_class usbotg_class = { |
1643 | .name = "usbotg", | |
1644 | .sysc = &omap3xxx_usbhsotg_sysc, | |
4fe20e97 RN |
1645 | }; |
1646 | ||
844a3b63 PW |
1647 | /* usb_otg_hs */ |
1648 | static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { | |
1649 | ||
7d7e1eba TL |
1650 | { .name = "mc", .irq = 92 + OMAP_INTC_START, }, |
1651 | { .name = "dma", .irq = 93 + OMAP_INTC_START, }, | |
1652 | { .irq = -1 }, | |
844a3b63 PW |
1653 | }; |
1654 | ||
1655 | static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { | |
1656 | .name = "usb_otg_hs", | |
1657 | .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, | |
1658 | .main_clk = "hsotgusb_ick", | |
4fe20e97 RN |
1659 | .prcm = { |
1660 | .omap2 = { | |
4fe20e97 | 1661 | .prcm_reg_id = 1, |
844a3b63 PW |
1662 | .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, |
1663 | .module_offs = CORE_MOD, | |
4fe20e97 | 1664 | .idlest_reg_id = 1, |
844a3b63 PW |
1665 | .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, |
1666 | .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT | |
4fe20e97 RN |
1667 | }, |
1668 | }, | |
844a3b63 PW |
1669 | .class = &usbotg_class, |
1670 | ||
1671 | /* | |
1672 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially | |
1673 | * broken when autoidle is enabled | |
1674 | * workaround is to disable the autoidle bit at module level. | |
1675 | */ | |
1676 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | |
1677 | | HWMOD_SWSUP_MSTANDBY, | |
4fe20e97 RN |
1678 | }; |
1679 | ||
844a3b63 PW |
1680 | /* usb_otg_hs */ |
1681 | static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { | |
7d7e1eba TL |
1682 | { .name = "mc", .irq = 71 + OMAP_INTC_START, }, |
1683 | { .irq = -1 }, | |
4fe20e97 RN |
1684 | }; |
1685 | ||
844a3b63 PW |
1686 | static struct omap_hwmod_class am35xx_usbotg_class = { |
1687 | .name = "am35xx_usbotg", | |
844a3b63 PW |
1688 | }; |
1689 | ||
1690 | static struct omap_hwmod am35xx_usbhsotg_hwmod = { | |
1691 | .name = "am35x_otg_hs", | |
1692 | .mpu_irqs = am35xx_usbhsotg_mpu_irqs, | |
89ea2583 | 1693 | .main_clk = "hsotgusb_fck", |
844a3b63 | 1694 | .class = &am35xx_usbotg_class, |
89ea2583 | 1695 | .flags = HWMOD_NO_IDLEST, |
4fe20e97 RN |
1696 | }; |
1697 | ||
844a3b63 PW |
1698 | /* MMC/SD/SDIO common */ |
1699 | static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { | |
1700 | .rev_offs = 0x1fc, | |
1701 | .sysc_offs = 0x10, | |
1702 | .syss_offs = 0x14, | |
1703 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1704 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1705 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1706 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1707 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1708 | }; | |
4fe20e97 | 1709 | |
844a3b63 PW |
1710 | static struct omap_hwmod_class omap34xx_mmc_class = { |
1711 | .name = "mmc", | |
1712 | .sysc = &omap34xx_mmc_sysc, | |
4fe20e97 RN |
1713 | }; |
1714 | ||
844a3b63 PW |
1715 | /* MMC/SD/SDIO1 */ |
1716 | ||
1717 | static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { | |
7d7e1eba TL |
1718 | { .irq = 83 + OMAP_INTC_START, }, |
1719 | { .irq = -1 }, | |
4fe20e97 RN |
1720 | }; |
1721 | ||
844a3b63 PW |
1722 | static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { |
1723 | { .name = "tx", .dma_req = 61, }, | |
1724 | { .name = "rx", .dma_req = 62, }, | |
bc614958 | 1725 | { .dma_req = -1 } |
4fe20e97 RN |
1726 | }; |
1727 | ||
844a3b63 PW |
1728 | static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { |
1729 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
1730 | }; | |
1731 | ||
1732 | static struct omap_mmc_dev_attr mmc1_dev_attr = { | |
1733 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
1734 | }; | |
1735 | ||
1736 | /* See 35xx errata 2.1.1.128 in SPRZ278F */ | |
1737 | static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = { | |
1738 | .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | | |
1739 | OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), | |
1740 | }; | |
1741 | ||
1742 | static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { | |
1743 | .name = "mmc1", | |
1744 | .mpu_irqs = omap34xx_mmc1_mpu_irqs, | |
1745 | .sdma_reqs = omap34xx_mmc1_sdma_reqs, | |
1746 | .opt_clks = omap34xx_mmc1_opt_clks, | |
1747 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), | |
1748 | .main_clk = "mmchs1_fck", | |
4fe20e97 RN |
1749 | .prcm = { |
1750 | .omap2 = { | |
1751 | .module_offs = CORE_MOD, | |
1752 | .prcm_reg_id = 1, | |
844a3b63 | 1753 | .module_bit = OMAP3430_EN_MMC1_SHIFT, |
4fe20e97 | 1754 | .idlest_reg_id = 1, |
844a3b63 | 1755 | .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, |
4fe20e97 RN |
1756 | }, |
1757 | }, | |
844a3b63 PW |
1758 | .dev_attr = &mmc1_pre_es3_dev_attr, |
1759 | .class = &omap34xx_mmc_class, | |
4fe20e97 RN |
1760 | }; |
1761 | ||
844a3b63 PW |
1762 | static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { |
1763 | .name = "mmc1", | |
1764 | .mpu_irqs = omap34xx_mmc1_mpu_irqs, | |
1765 | .sdma_reqs = omap34xx_mmc1_sdma_reqs, | |
1766 | .opt_clks = omap34xx_mmc1_opt_clks, | |
1767 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), | |
1768 | .main_clk = "mmchs1_fck", | |
1769 | .prcm = { | |
1770 | .omap2 = { | |
1771 | .module_offs = CORE_MOD, | |
1772 | .prcm_reg_id = 1, | |
1773 | .module_bit = OMAP3430_EN_MMC1_SHIFT, | |
1774 | .idlest_reg_id = 1, | |
1775 | .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, | |
1776 | }, | |
70034d38 | 1777 | }, |
844a3b63 PW |
1778 | .dev_attr = &mmc1_dev_attr, |
1779 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1780 | }; |
1781 | ||
844a3b63 | 1782 | /* MMC/SD/SDIO2 */ |
70034d38 | 1783 | |
844a3b63 | 1784 | static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { |
7d7e1eba TL |
1785 | { .irq = 86 + OMAP_INTC_START, }, |
1786 | { .irq = -1 }, | |
70034d38 VC |
1787 | }; |
1788 | ||
844a3b63 PW |
1789 | static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { |
1790 | { .name = "tx", .dma_req = 47, }, | |
1791 | { .name = "rx", .dma_req = 48, }, | |
1792 | { .dma_req = -1 } | |
70034d38 VC |
1793 | }; |
1794 | ||
844a3b63 PW |
1795 | static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { |
1796 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
70034d38 VC |
1797 | }; |
1798 | ||
844a3b63 PW |
1799 | /* See 35xx errata 2.1.1.128 in SPRZ278F */ |
1800 | static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = { | |
1801 | .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, | |
70034d38 VC |
1802 | }; |
1803 | ||
844a3b63 PW |
1804 | static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { |
1805 | .name = "mmc2", | |
1806 | .mpu_irqs = omap34xx_mmc2_mpu_irqs, | |
1807 | .sdma_reqs = omap34xx_mmc2_sdma_reqs, | |
1808 | .opt_clks = omap34xx_mmc2_opt_clks, | |
1809 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), | |
1810 | .main_clk = "mmchs2_fck", | |
1811 | .prcm = { | |
1812 | .omap2 = { | |
1813 | .module_offs = CORE_MOD, | |
1814 | .prcm_reg_id = 1, | |
1815 | .module_bit = OMAP3430_EN_MMC2_SHIFT, | |
1816 | .idlest_reg_id = 1, | |
1817 | .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, | |
1818 | }, | |
70034d38 | 1819 | }, |
844a3b63 PW |
1820 | .dev_attr = &mmc2_pre_es3_dev_attr, |
1821 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1822 | }; |
1823 | ||
844a3b63 PW |
1824 | static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { |
1825 | .name = "mmc2", | |
1826 | .mpu_irqs = omap34xx_mmc2_mpu_irqs, | |
1827 | .sdma_reqs = omap34xx_mmc2_sdma_reqs, | |
1828 | .opt_clks = omap34xx_mmc2_opt_clks, | |
1829 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), | |
1830 | .main_clk = "mmchs2_fck", | |
1831 | .prcm = { | |
1832 | .omap2 = { | |
1833 | .module_offs = CORE_MOD, | |
1834 | .prcm_reg_id = 1, | |
1835 | .module_bit = OMAP3430_EN_MMC2_SHIFT, | |
1836 | .idlest_reg_id = 1, | |
1837 | .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, | |
1838 | }, | |
1839 | }, | |
1840 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1841 | }; |
1842 | ||
844a3b63 PW |
1843 | /* MMC/SD/SDIO3 */ |
1844 | ||
1845 | static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { | |
7d7e1eba TL |
1846 | { .irq = 94 + OMAP_INTC_START, }, |
1847 | { .irq = -1 }, | |
70034d38 VC |
1848 | }; |
1849 | ||
844a3b63 PW |
1850 | static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { |
1851 | { .name = "tx", .dma_req = 77, }, | |
1852 | { .name = "rx", .dma_req = 78, }, | |
1853 | { .dma_req = -1 } | |
70034d38 VC |
1854 | }; |
1855 | ||
844a3b63 PW |
1856 | static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { |
1857 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
70034d38 VC |
1858 | }; |
1859 | ||
844a3b63 PW |
1860 | static struct omap_hwmod omap3xxx_mmc3_hwmod = { |
1861 | .name = "mmc3", | |
1862 | .mpu_irqs = omap34xx_mmc3_mpu_irqs, | |
1863 | .sdma_reqs = omap34xx_mmc3_sdma_reqs, | |
1864 | .opt_clks = omap34xx_mmc3_opt_clks, | |
1865 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), | |
1866 | .main_clk = "mmchs3_fck", | |
1867 | .prcm = { | |
1868 | .omap2 = { | |
1869 | .prcm_reg_id = 1, | |
1870 | .module_bit = OMAP3430_EN_MMC3_SHIFT, | |
1871 | .idlest_reg_id = 1, | |
1872 | .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, | |
1873 | }, | |
1874 | }, | |
1875 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1876 | }; |
1877 | ||
1878 | /* | |
844a3b63 PW |
1879 | * 'usb_host_hs' class |
1880 | * high-speed multi-port usb host controller | |
70034d38 VC |
1881 | */ |
1882 | ||
844a3b63 | 1883 | static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { |
70034d38 VC |
1884 | .rev_offs = 0x0000, |
1885 | .sysc_offs = 0x0010, | |
1886 | .syss_offs = 0x0014, | |
844a3b63 PW |
1887 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | |
1888 | SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
1889 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1890 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1891 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1892 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1893 | }; |
1894 | ||
844a3b63 PW |
1895 | static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { |
1896 | .name = "usb_host_hs", | |
1897 | .sysc = &omap3xxx_usb_host_hs_sysc, | |
70034d38 VC |
1898 | }; |
1899 | ||
844a3b63 PW |
1900 | static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { |
1901 | { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", }, | |
70034d38 VC |
1902 | }; |
1903 | ||
844a3b63 | 1904 | static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = { |
7d7e1eba TL |
1905 | { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, }, |
1906 | { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, }, | |
1907 | { .irq = -1 }, | |
70034d38 VC |
1908 | }; |
1909 | ||
844a3b63 PW |
1910 | static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { |
1911 | .name = "usb_host_hs", | |
1912 | .class = &omap3xxx_usb_host_hs_hwmod_class, | |
1913 | .clkdm_name = "l3_init_clkdm", | |
1914 | .mpu_irqs = omap3xxx_usb_host_hs_irqs, | |
1915 | .main_clk = "usbhost_48m_fck", | |
1916 | .prcm = { | |
70034d38 | 1917 | .omap2 = { |
844a3b63 | 1918 | .module_offs = OMAP3430ES2_USBHOST_MOD, |
70034d38 | 1919 | .prcm_reg_id = 1, |
844a3b63 | 1920 | .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, |
70034d38 | 1921 | .idlest_reg_id = 1, |
844a3b63 PW |
1922 | .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, |
1923 | .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT, | |
70034d38 VC |
1924 | }, |
1925 | }, | |
844a3b63 PW |
1926 | .opt_clks = omap3xxx_usb_host_hs_opt_clks, |
1927 | .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks), | |
70034d38 | 1928 | |
844a3b63 PW |
1929 | /* |
1930 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
1931 | * id: i660 | |
1932 | * | |
1933 | * Description: | |
1934 | * In the following configuration : | |
1935 | * - USBHOST module is set to smart-idle mode | |
1936 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
1937 | * happens when the system is going to a low power mode : all ports | |
1938 | * have been suspended, the master part of the USBHOST module has | |
1939 | * entered the standby state, and SW has cut the functional clocks) | |
1940 | * - an USBHOST interrupt occurs before the module is able to answer | |
1941 | * idle_ack, typically a remote wakeup IRQ. | |
1942 | * Then the USB HOST module will enter a deadlock situation where it | |
1943 | * is no more accessible nor functional. | |
1944 | * | |
1945 | * Workaround: | |
1946 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
1947 | */ | |
1948 | ||
1949 | /* | |
1950 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
1951 | * Id: i571 | |
1952 | * | |
1953 | * Description: | |
1954 | * When the USBHOST module is set to smart-standby mode, and when it is | |
1955 | * ready to enter the standby state (i.e. all ports are suspended and | |
1956 | * all attached devices are in suspend mode), then it can wrongly assert | |
1957 | * the Mstandby signal too early while there are still some residual OCP | |
1958 | * transactions ongoing. If this condition occurs, the internal state | |
1959 | * machine may go to an undefined state and the USB link may be stuck | |
1960 | * upon the next resume. | |
1961 | * | |
1962 | * Workaround: | |
1963 | * Don't use smart standby; use only force standby, | |
1964 | * hence HWMOD_SWSUP_MSTANDBY | |
1965 | */ | |
1966 | ||
1967 | /* | |
1968 | * During system boot; If the hwmod framework resets the module | |
1969 | * the module will have smart idle settings; which can lead to deadlock | |
1970 | * (above Errata Id:i660); so, dont reset the module during boot; | |
1971 | * Use HWMOD_INIT_NO_RESET. | |
1972 | */ | |
70034d38 | 1973 | |
844a3b63 PW |
1974 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | |
1975 | HWMOD_INIT_NO_RESET, | |
70034d38 VC |
1976 | }; |
1977 | ||
844a3b63 PW |
1978 | /* |
1979 | * 'usb_tll_hs' class | |
1980 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
1981 | */ | |
1982 | static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = { | |
1983 | .rev_offs = 0x0000, | |
1984 | .sysc_offs = 0x0010, | |
1985 | .syss_offs = 0x0014, | |
1986 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1987 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1988 | SYSC_HAS_AUTOIDLE), | |
1989 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1990 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1991 | }; |
1992 | ||
844a3b63 PW |
1993 | static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { |
1994 | .name = "usb_tll_hs", | |
1995 | .sysc = &omap3xxx_usb_tll_hs_sysc, | |
70034d38 VC |
1996 | }; |
1997 | ||
844a3b63 | 1998 | static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { |
7d7e1eba TL |
1999 | { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, }, |
2000 | { .irq = -1 }, | |
70034d38 VC |
2001 | }; |
2002 | ||
844a3b63 PW |
2003 | static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { |
2004 | .name = "usb_tll_hs", | |
2005 | .class = &omap3xxx_usb_tll_hs_hwmod_class, | |
2006 | .clkdm_name = "l3_init_clkdm", | |
2007 | .mpu_irqs = omap3xxx_usb_tll_hs_irqs, | |
2008 | .main_clk = "usbtll_fck", | |
2009 | .prcm = { | |
70034d38 | 2010 | .omap2 = { |
844a3b63 PW |
2011 | .module_offs = CORE_MOD, |
2012 | .prcm_reg_id = 3, | |
2013 | .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | |
2014 | .idlest_reg_id = 3, | |
2015 | .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, | |
70034d38 VC |
2016 | }, |
2017 | }, | |
70034d38 VC |
2018 | }; |
2019 | ||
45a4bb06 PW |
2020 | static struct omap_hwmod omap3xxx_hdq1w_hwmod = { |
2021 | .name = "hdq1w", | |
2022 | .mpu_irqs = omap2_hdq1w_mpu_irqs, | |
2023 | .main_clk = "hdq_fck", | |
2024 | .prcm = { | |
2025 | .omap2 = { | |
2026 | .module_offs = CORE_MOD, | |
2027 | .prcm_reg_id = 1, | |
2028 | .module_bit = OMAP3430_EN_HDQ_SHIFT, | |
2029 | .idlest_reg_id = 1, | |
2030 | .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT, | |
2031 | }, | |
2032 | }, | |
2033 | .class = &omap2_hdq1w_class, | |
2034 | }; | |
2035 | ||
8f993a01 TK |
2036 | /* SAD2D */ |
2037 | static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = { | |
2038 | { .name = "rst_modem_pwron_sw", .rst_shift = 0 }, | |
2039 | { .name = "rst_modem_sw", .rst_shift = 1 }, | |
2040 | }; | |
2041 | ||
2042 | static struct omap_hwmod_class omap3xxx_sad2d_class = { | |
2043 | .name = "sad2d", | |
2044 | }; | |
2045 | ||
2046 | static struct omap_hwmod omap3xxx_sad2d_hwmod = { | |
2047 | .name = "sad2d", | |
2048 | .rst_lines = omap3xxx_sad2d_resets, | |
2049 | .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets), | |
2050 | .main_clk = "sad2d_ick", | |
2051 | .prcm = { | |
2052 | .omap2 = { | |
2053 | .module_offs = CORE_MOD, | |
2054 | .prcm_reg_id = 1, | |
2055 | .module_bit = OMAP3430_EN_SAD2D_SHIFT, | |
2056 | .idlest_reg_id = 1, | |
2057 | .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT, | |
2058 | }, | |
2059 | }, | |
2060 | .class = &omap3xxx_sad2d_class, | |
2061 | }; | |
2062 | ||
c8d82ff6 VH |
2063 | /* |
2064 | * '32K sync counter' class | |
2065 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock | |
2066 | */ | |
2067 | static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = { | |
2068 | .rev_offs = 0x0000, | |
2069 | .sysc_offs = 0x0004, | |
2070 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
2071 | .idlemodes = (SIDLE_FORCE | SIDLE_NO), | |
2072 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2073 | }; | |
2074 | ||
2075 | static struct omap_hwmod_class omap3xxx_counter_hwmod_class = { | |
2076 | .name = "counter", | |
2077 | .sysc = &omap3xxx_counter_sysc, | |
2078 | }; | |
2079 | ||
2080 | static struct omap_hwmod omap3xxx_counter_32k_hwmod = { | |
2081 | .name = "counter_32k", | |
2082 | .class = &omap3xxx_counter_hwmod_class, | |
2083 | .clkdm_name = "wkup_clkdm", | |
2084 | .flags = HWMOD_SWSUP_SIDLE, | |
2085 | .main_clk = "wkup_32k_fck", | |
2086 | .prcm = { | |
2087 | .omap2 = { | |
2088 | .module_offs = WKUP_MOD, | |
2089 | .prcm_reg_id = 1, | |
2090 | .module_bit = OMAP3430_ST_32KSYNC_SHIFT, | |
2091 | .idlest_reg_id = 1, | |
2092 | .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT, | |
2093 | }, | |
2094 | }, | |
2095 | }; | |
2096 | ||
844a3b63 PW |
2097 | /* |
2098 | * interfaces | |
2099 | */ | |
2100 | ||
2101 | /* L3 -> L4_CORE interface */ | |
2102 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { | |
2103 | .master = &omap3xxx_l3_main_hwmod, | |
2104 | .slave = &omap3xxx_l4_core_hwmod, | |
2105 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2106 | }; |
2107 | ||
844a3b63 PW |
2108 | /* L3 -> L4_PER interface */ |
2109 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { | |
2110 | .master = &omap3xxx_l3_main_hwmod, | |
2111 | .slave = &omap3xxx_l4_per_hwmod, | |
2112 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2113 | }; |
2114 | ||
844a3b63 PW |
2115 | static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { |
2116 | { | |
2117 | .pa_start = 0x68000000, | |
2118 | .pa_end = 0x6800ffff, | |
2119 | .flags = ADDR_TYPE_RT, | |
70034d38 | 2120 | }, |
844a3b63 | 2121 | { } |
70034d38 VC |
2122 | }; |
2123 | ||
844a3b63 PW |
2124 | /* MPU -> L3 interface */ |
2125 | static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { | |
2126 | .master = &omap3xxx_mpu_hwmod, | |
2127 | .slave = &omap3xxx_l3_main_hwmod, | |
2128 | .addr = omap3xxx_l3_main_addrs, | |
2129 | .user = OCP_USER_MPU, | |
70034d38 VC |
2130 | }; |
2131 | ||
844a3b63 PW |
2132 | /* DSS -> l3 */ |
2133 | static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = { | |
2134 | .master = &omap3430es1_dss_core_hwmod, | |
2135 | .slave = &omap3xxx_l3_main_hwmod, | |
2136 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2137 | }; |
2138 | ||
844a3b63 PW |
2139 | static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { |
2140 | .master = &omap3xxx_dss_core_hwmod, | |
2141 | .slave = &omap3xxx_l3_main_hwmod, | |
2142 | .fw = { | |
70034d38 | 2143 | .omap2 = { |
844a3b63 PW |
2144 | .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, |
2145 | .flags = OMAP_FIREWALL_L3, | |
2146 | } | |
70034d38 | 2147 | }, |
844a3b63 | 2148 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2149 | }; |
2150 | ||
844a3b63 PW |
2151 | /* l3_core -> usbhsotg interface */ |
2152 | static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { | |
2153 | .master = &omap3xxx_usbhsotg_hwmod, | |
01438ab6 MK |
2154 | .slave = &omap3xxx_l3_main_hwmod, |
2155 | .clk = "core_l3_ick", | |
844a3b63 | 2156 | .user = OCP_USER_MPU, |
01438ab6 MK |
2157 | }; |
2158 | ||
844a3b63 PW |
2159 | /* l3_core -> am35xx_usbhsotg interface */ |
2160 | static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { | |
2161 | .master = &am35xx_usbhsotg_hwmod, | |
2162 | .slave = &omap3xxx_l3_main_hwmod, | |
89ea2583 | 2163 | .clk = "hsotgusb_ick", |
844a3b63 | 2164 | .user = OCP_USER_MPU, |
01438ab6 | 2165 | }; |
89ea2583 | 2166 | |
8f993a01 TK |
2167 | /* l3_core -> sad2d interface */ |
2168 | static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = { | |
2169 | .master = &omap3xxx_sad2d_hwmod, | |
2170 | .slave = &omap3xxx_l3_main_hwmod, | |
2171 | .clk = "core_l3_ick", | |
2172 | .user = OCP_USER_MPU, | |
2173 | }; | |
2174 | ||
844a3b63 PW |
2175 | /* L4_CORE -> L4_WKUP interface */ |
2176 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { | |
2177 | .master = &omap3xxx_l4_core_hwmod, | |
2178 | .slave = &omap3xxx_l4_wkup_hwmod, | |
2179 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2180 | }; |
2181 | ||
844a3b63 PW |
2182 | /* L4 CORE -> MMC1 interface */ |
2183 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = { | |
01438ab6 | 2184 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2185 | .slave = &omap3xxx_pre_es3_mmc1_hwmod, |
2186 | .clk = "mmchs1_ick", | |
2187 | .addr = omap2430_mmc1_addr_space, | |
01438ab6 | 2188 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 | 2189 | .flags = OMAP_FIREWALL_L4 |
01438ab6 MK |
2190 | }; |
2191 | ||
844a3b63 PW |
2192 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = { |
2193 | .master = &omap3xxx_l4_core_hwmod, | |
2194 | .slave = &omap3xxx_es3plus_mmc1_hwmod, | |
2195 | .clk = "mmchs1_ick", | |
2196 | .addr = omap2430_mmc1_addr_space, | |
2197 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2198 | .flags = OMAP_FIREWALL_L4 | |
01438ab6 MK |
2199 | }; |
2200 | ||
844a3b63 PW |
2201 | /* L4 CORE -> MMC2 interface */ |
2202 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = { | |
2203 | .master = &omap3xxx_l4_core_hwmod, | |
2204 | .slave = &omap3xxx_pre_es3_mmc2_hwmod, | |
2205 | .clk = "mmchs2_ick", | |
2206 | .addr = omap2430_mmc2_addr_space, | |
2207 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2208 | .flags = OMAP_FIREWALL_L4 | |
2209 | }; | |
70034d38 | 2210 | |
844a3b63 PW |
2211 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = { |
2212 | .master = &omap3xxx_l4_core_hwmod, | |
2213 | .slave = &omap3xxx_es3plus_mmc2_hwmod, | |
2214 | .clk = "mmchs2_ick", | |
2215 | .addr = omap2430_mmc2_addr_space, | |
2216 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2217 | .flags = OMAP_FIREWALL_L4 | |
70034d38 VC |
2218 | }; |
2219 | ||
844a3b63 PW |
2220 | /* L4 CORE -> MMC3 interface */ |
2221 | static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { | |
2222 | { | |
2223 | .pa_start = 0x480ad000, | |
2224 | .pa_end = 0x480ad1ff, | |
2225 | .flags = ADDR_TYPE_RT, | |
2226 | }, | |
2227 | { } | |
70034d38 VC |
2228 | }; |
2229 | ||
844a3b63 PW |
2230 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { |
2231 | .master = &omap3xxx_l4_core_hwmod, | |
2232 | .slave = &omap3xxx_mmc3_hwmod, | |
2233 | .clk = "mmchs3_ick", | |
2234 | .addr = omap3xxx_mmc3_addr_space, | |
2235 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2236 | .flags = OMAP_FIREWALL_L4 | |
70034d38 VC |
2237 | }; |
2238 | ||
844a3b63 PW |
2239 | /* L4 CORE -> UART1 interface */ |
2240 | static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { | |
dc48e5fc | 2241 | { |
844a3b63 PW |
2242 | .pa_start = OMAP3_UART1_BASE, |
2243 | .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, | |
2244 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
dc48e5fc | 2245 | }, |
78183f3f | 2246 | { } |
70034d38 VC |
2247 | }; |
2248 | ||
844a3b63 | 2249 | static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { |
dc48e5fc | 2250 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2251 | .slave = &omap3xxx_uart1_hwmod, |
2252 | .clk = "uart1_ick", | |
2253 | .addr = omap3xxx_uart1_addr_space, | |
dc48e5fc | 2254 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2255 | }; |
2256 | ||
844a3b63 PW |
2257 | /* L4 CORE -> UART2 interface */ |
2258 | static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { | |
2259 | { | |
2260 | .pa_start = OMAP3_UART2_BASE, | |
2261 | .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, | |
2262 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2263 | }, |
844a3b63 | 2264 | { } |
70034d38 VC |
2265 | }; |
2266 | ||
844a3b63 PW |
2267 | static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { |
2268 | .master = &omap3xxx_l4_core_hwmod, | |
2269 | .slave = &omap3xxx_uart2_hwmod, | |
2270 | .clk = "uart2_ick", | |
2271 | .addr = omap3xxx_uart2_addr_space, | |
2272 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2273 | }; |
2274 | ||
844a3b63 PW |
2275 | /* L4 PER -> UART3 interface */ |
2276 | static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { | |
dc48e5fc | 2277 | { |
844a3b63 PW |
2278 | .pa_start = OMAP3_UART3_BASE, |
2279 | .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, | |
2280 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2281 | }, |
78183f3f | 2282 | { } |
70034d38 VC |
2283 | }; |
2284 | ||
844a3b63 | 2285 | static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { |
dc48e5fc | 2286 | .master = &omap3xxx_l4_per_hwmod, |
844a3b63 PW |
2287 | .slave = &omap3xxx_uart3_hwmod, |
2288 | .clk = "uart3_ick", | |
2289 | .addr = omap3xxx_uart3_addr_space, | |
dc48e5fc | 2290 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2291 | }; |
2292 | ||
844a3b63 PW |
2293 | /* L4 PER -> UART4 interface */ |
2294 | static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = { | |
2295 | { | |
2296 | .pa_start = OMAP3_UART4_BASE, | |
2297 | .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, | |
2298 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2299 | }, |
844a3b63 | 2300 | { } |
70034d38 VC |
2301 | }; |
2302 | ||
844a3b63 PW |
2303 | static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { |
2304 | .master = &omap3xxx_l4_per_hwmod, | |
2305 | .slave = &omap36xx_uart4_hwmod, | |
2306 | .clk = "uart4_ick", | |
2307 | .addr = omap36xx_uart4_addr_space, | |
2308 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2309 | }; |
2310 | ||
844a3b63 PW |
2311 | /* AM35xx: L4 CORE -> UART4 interface */ |
2312 | static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { | |
dc48e5fc | 2313 | { |
844a3b63 PW |
2314 | .pa_start = OMAP3_UART4_AM35XX_BASE, |
2315 | .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, | |
2316 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
dc48e5fc | 2317 | }, |
bf765237 | 2318 | { } |
70034d38 VC |
2319 | }; |
2320 | ||
844a3b63 PW |
2321 | static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { |
2322 | .master = &omap3xxx_l4_core_hwmod, | |
2323 | .slave = &am35xx_uart4_hwmod, | |
2324 | .clk = "uart4_ick", | |
2325 | .addr = am35xx_uart4_addr_space, | |
dc48e5fc C |
2326 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2327 | }; | |
2328 | ||
844a3b63 PW |
2329 | /* L4 CORE -> I2C1 interface */ |
2330 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { | |
2331 | .master = &omap3xxx_l4_core_hwmod, | |
2332 | .slave = &omap3xxx_i2c1_hwmod, | |
2333 | .clk = "i2c1_ick", | |
2334 | .addr = omap2_i2c1_addr_space, | |
2335 | .fw = { | |
2336 | .omap2 = { | |
2337 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, | |
2338 | .l4_prot_group = 7, | |
2339 | .flags = OMAP_FIREWALL_L4, | |
2340 | } | |
2341 | }, | |
2342 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
8b1906f1 KVA |
2343 | }; |
2344 | ||
844a3b63 PW |
2345 | /* L4 CORE -> I2C2 interface */ |
2346 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { | |
2347 | .master = &omap3xxx_l4_core_hwmod, | |
2348 | .slave = &omap3xxx_i2c2_hwmod, | |
2349 | .clk = "i2c2_ick", | |
2350 | .addr = omap2_i2c2_addr_space, | |
2351 | .fw = { | |
70034d38 | 2352 | .omap2 = { |
844a3b63 PW |
2353 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, |
2354 | .l4_prot_group = 7, | |
2355 | .flags = OMAP_FIREWALL_L4, | |
2356 | } | |
70034d38 | 2357 | }, |
844a3b63 | 2358 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2359 | }; |
2360 | ||
844a3b63 PW |
2361 | /* L4 CORE -> I2C3 interface */ |
2362 | static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { | |
2363 | { | |
2364 | .pa_start = 0x48060000, | |
2365 | .pa_end = 0x48060000 + SZ_128 - 1, | |
2366 | .flags = ADDR_TYPE_RT, | |
2367 | }, | |
2368 | { } | |
70034d38 VC |
2369 | }; |
2370 | ||
844a3b63 PW |
2371 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { |
2372 | .master = &omap3xxx_l4_core_hwmod, | |
2373 | .slave = &omap3xxx_i2c3_hwmod, | |
2374 | .clk = "i2c3_ick", | |
2375 | .addr = omap3xxx_i2c3_addr_space, | |
2376 | .fw = { | |
2377 | .omap2 = { | |
2378 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, | |
2379 | .l4_prot_group = 7, | |
2380 | .flags = OMAP_FIREWALL_L4, | |
2381 | } | |
2382 | }, | |
2383 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2384 | }; |
2385 | ||
844a3b63 PW |
2386 | /* L4 CORE -> SR1 interface */ |
2387 | static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { | |
dc48e5fc | 2388 | { |
844a3b63 PW |
2389 | .pa_start = OMAP34XX_SR1_BASE, |
2390 | .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, | |
2391 | .flags = ADDR_TYPE_RT, | |
dc48e5fc | 2392 | }, |
78183f3f | 2393 | { } |
70034d38 VC |
2394 | }; |
2395 | ||
844a3b63 PW |
2396 | static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { |
2397 | .master = &omap3xxx_l4_core_hwmod, | |
2398 | .slave = &omap34xx_sr1_hwmod, | |
2399 | .clk = "sr_l4_ick", | |
2400 | .addr = omap3_sr1_addr_space, | |
2401 | .user = OCP_USER_MPU, | |
70034d38 VC |
2402 | }; |
2403 | ||
844a3b63 PW |
2404 | static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = { |
2405 | .master = &omap3xxx_l4_core_hwmod, | |
2406 | .slave = &omap36xx_sr1_hwmod, | |
2407 | .clk = "sr_l4_ick", | |
2408 | .addr = omap3_sr1_addr_space, | |
2409 | .user = OCP_USER_MPU, | |
2410 | }; | |
2411 | ||
2412 | /* L4 CORE -> SR1 interface */ | |
2413 | static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { | |
2414 | { | |
2415 | .pa_start = OMAP34XX_SR2_BASE, | |
2416 | .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, | |
2417 | .flags = ADDR_TYPE_RT, | |
70034d38 | 2418 | }, |
844a3b63 | 2419 | { } |
70034d38 VC |
2420 | }; |
2421 | ||
844a3b63 PW |
2422 | static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { |
2423 | .master = &omap3xxx_l4_core_hwmod, | |
2424 | .slave = &omap34xx_sr2_hwmod, | |
2425 | .clk = "sr_l4_ick", | |
2426 | .addr = omap3_sr2_addr_space, | |
2427 | .user = OCP_USER_MPU, | |
70034d38 VC |
2428 | }; |
2429 | ||
844a3b63 PW |
2430 | static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = { |
2431 | .master = &omap3xxx_l4_core_hwmod, | |
2432 | .slave = &omap36xx_sr2_hwmod, | |
2433 | .clk = "sr_l4_ick", | |
2434 | .addr = omap3_sr2_addr_space, | |
2435 | .user = OCP_USER_MPU, | |
70034d38 VC |
2436 | }; |
2437 | ||
844a3b63 | 2438 | static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { |
dc48e5fc | 2439 | { |
844a3b63 PW |
2440 | .pa_start = OMAP34XX_HSUSB_OTG_BASE, |
2441 | .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, | |
dc48e5fc C |
2442 | .flags = ADDR_TYPE_RT |
2443 | }, | |
78183f3f | 2444 | { } |
70034d38 VC |
2445 | }; |
2446 | ||
844a3b63 PW |
2447 | /* l4_core -> usbhsotg */ |
2448 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { | |
dc48e5fc | 2449 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2450 | .slave = &omap3xxx_usbhsotg_hwmod, |
2451 | .clk = "l4_ick", | |
2452 | .addr = omap3xxx_usbhsotg_addrs, | |
2453 | .user = OCP_USER_MPU, | |
dc48e5fc C |
2454 | }; |
2455 | ||
844a3b63 PW |
2456 | static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { |
2457 | { | |
2458 | .pa_start = AM35XX_IPSS_USBOTGSS_BASE, | |
2459 | .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, | |
2460 | .flags = ADDR_TYPE_RT | |
70034d38 | 2461 | }, |
844a3b63 | 2462 | { } |
70034d38 VC |
2463 | }; |
2464 | ||
844a3b63 PW |
2465 | /* l4_core -> usbhsotg */ |
2466 | static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { | |
2467 | .master = &omap3xxx_l4_core_hwmod, | |
2468 | .slave = &am35xx_usbhsotg_hwmod, | |
89ea2583 | 2469 | .clk = "hsotgusb_ick", |
844a3b63 PW |
2470 | .addr = am35xx_usbhsotg_addrs, |
2471 | .user = OCP_USER_MPU, | |
01438ab6 MK |
2472 | }; |
2473 | ||
844a3b63 PW |
2474 | /* L4_WKUP -> L4_SEC interface */ |
2475 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = { | |
2476 | .master = &omap3xxx_l4_wkup_hwmod, | |
2477 | .slave = &omap3xxx_l4_sec_hwmod, | |
2478 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2479 | }; |
2480 | ||
844a3b63 PW |
2481 | /* IVA2 <- L3 interface */ |
2482 | static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { | |
2483 | .master = &omap3xxx_l3_main_hwmod, | |
2484 | .slave = &omap3xxx_iva_hwmod, | |
064931ab | 2485 | .clk = "core_l3_ick", |
844a3b63 | 2486 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
01438ab6 MK |
2487 | }; |
2488 | ||
844a3b63 | 2489 | static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { |
dc48e5fc | 2490 | { |
844a3b63 PW |
2491 | .pa_start = 0x48318000, |
2492 | .pa_end = 0x48318000 + SZ_1K - 1, | |
dc48e5fc C |
2493 | .flags = ADDR_TYPE_RT |
2494 | }, | |
78183f3f | 2495 | { } |
01438ab6 MK |
2496 | }; |
2497 | ||
844a3b63 PW |
2498 | /* l4_wkup -> timer1 */ |
2499 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { | |
2500 | .master = &omap3xxx_l4_wkup_hwmod, | |
2501 | .slave = &omap3xxx_timer1_hwmod, | |
2502 | .clk = "gpt1_ick", | |
2503 | .addr = omap3xxx_timer1_addrs, | |
2504 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2505 | }; |
2506 | ||
844a3b63 PW |
2507 | static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { |
2508 | { | |
2509 | .pa_start = 0x49032000, | |
2510 | .pa_end = 0x49032000 + SZ_1K - 1, | |
2511 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2512 | }, |
844a3b63 | 2513 | { } |
01438ab6 MK |
2514 | }; |
2515 | ||
844a3b63 PW |
2516 | /* l4_per -> timer2 */ |
2517 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { | |
2518 | .master = &omap3xxx_l4_per_hwmod, | |
2519 | .slave = &omap3xxx_timer2_hwmod, | |
2520 | .clk = "gpt2_ick", | |
2521 | .addr = omap3xxx_timer2_addrs, | |
2522 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2523 | }; |
2524 | ||
844a3b63 | 2525 | static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { |
dc48e5fc | 2526 | { |
844a3b63 PW |
2527 | .pa_start = 0x49034000, |
2528 | .pa_end = 0x49034000 + SZ_1K - 1, | |
dc48e5fc C |
2529 | .flags = ADDR_TYPE_RT |
2530 | }, | |
78183f3f | 2531 | { } |
01438ab6 MK |
2532 | }; |
2533 | ||
844a3b63 PW |
2534 | /* l4_per -> timer3 */ |
2535 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { | |
dc48e5fc | 2536 | .master = &omap3xxx_l4_per_hwmod, |
844a3b63 PW |
2537 | .slave = &omap3xxx_timer3_hwmod, |
2538 | .clk = "gpt3_ick", | |
2539 | .addr = omap3xxx_timer3_addrs, | |
2540 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2541 | }; |
2542 | ||
844a3b63 PW |
2543 | static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { |
2544 | { | |
2545 | .pa_start = 0x49036000, | |
2546 | .pa_end = 0x49036000 + SZ_1K - 1, | |
2547 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2548 | }, |
844a3b63 | 2549 | { } |
01438ab6 MK |
2550 | }; |
2551 | ||
844a3b63 PW |
2552 | /* l4_per -> timer4 */ |
2553 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { | |
2554 | .master = &omap3xxx_l4_per_hwmod, | |
2555 | .slave = &omap3xxx_timer4_hwmod, | |
2556 | .clk = "gpt4_ick", | |
2557 | .addr = omap3xxx_timer4_addrs, | |
2558 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2559 | }; |
2560 | ||
844a3b63 PW |
2561 | static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { |
2562 | { | |
2563 | .pa_start = 0x49038000, | |
2564 | .pa_end = 0x49038000 + SZ_1K - 1, | |
2565 | .flags = ADDR_TYPE_RT | |
2566 | }, | |
2567 | { } | |
d3442726 TG |
2568 | }; |
2569 | ||
844a3b63 PW |
2570 | /* l4_per -> timer5 */ |
2571 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { | |
2572 | .master = &omap3xxx_l4_per_hwmod, | |
2573 | .slave = &omap3xxx_timer5_hwmod, | |
2574 | .clk = "gpt5_ick", | |
2575 | .addr = omap3xxx_timer5_addrs, | |
2576 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2577 | }; |
2578 | ||
844a3b63 PW |
2579 | static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { |
2580 | { | |
2581 | .pa_start = 0x4903A000, | |
2582 | .pa_end = 0x4903A000 + SZ_1K - 1, | |
2583 | .flags = ADDR_TYPE_RT | |
2584 | }, | |
2585 | { } | |
cea6b942 SG |
2586 | }; |
2587 | ||
844a3b63 PW |
2588 | /* l4_per -> timer6 */ |
2589 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { | |
2590 | .master = &omap3xxx_l4_per_hwmod, | |
2591 | .slave = &omap3xxx_timer6_hwmod, | |
2592 | .clk = "gpt6_ick", | |
2593 | .addr = omap3xxx_timer6_addrs, | |
2594 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2595 | }; |
2596 | ||
844a3b63 PW |
2597 | static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { |
2598 | { | |
2599 | .pa_start = 0x4903C000, | |
2600 | .pa_end = 0x4903C000 + SZ_1K - 1, | |
2601 | .flags = ADDR_TYPE_RT | |
d3442726 | 2602 | }, |
844a3b63 | 2603 | { } |
d3442726 TG |
2604 | }; |
2605 | ||
844a3b63 PW |
2606 | /* l4_per -> timer7 */ |
2607 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { | |
2608 | .master = &omap3xxx_l4_per_hwmod, | |
2609 | .slave = &omap3xxx_timer7_hwmod, | |
2610 | .clk = "gpt7_ick", | |
2611 | .addr = omap3xxx_timer7_addrs, | |
2612 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
cea6b942 SG |
2613 | }; |
2614 | ||
844a3b63 PW |
2615 | static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { |
2616 | { | |
2617 | .pa_start = 0x4903E000, | |
2618 | .pa_end = 0x4903E000 + SZ_1K - 1, | |
2619 | .flags = ADDR_TYPE_RT | |
d3442726 | 2620 | }, |
844a3b63 | 2621 | { } |
d3442726 TG |
2622 | }; |
2623 | ||
844a3b63 PW |
2624 | /* l4_per -> timer8 */ |
2625 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { | |
2626 | .master = &omap3xxx_l4_per_hwmod, | |
2627 | .slave = &omap3xxx_timer8_hwmod, | |
2628 | .clk = "gpt8_ick", | |
2629 | .addr = omap3xxx_timer8_addrs, | |
2630 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2631 | }; |
2632 | ||
844a3b63 PW |
2633 | static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { |
2634 | { | |
2635 | .pa_start = 0x49040000, | |
2636 | .pa_end = 0x49040000 + SZ_1K - 1, | |
2637 | .flags = ADDR_TYPE_RT | |
2638 | }, | |
2639 | { } | |
2640 | }; | |
0f9dfdd3 | 2641 | |
844a3b63 PW |
2642 | /* l4_per -> timer9 */ |
2643 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { | |
2644 | .master = &omap3xxx_l4_per_hwmod, | |
2645 | .slave = &omap3xxx_timer9_hwmod, | |
2646 | .clk = "gpt9_ick", | |
2647 | .addr = omap3xxx_timer9_addrs, | |
2648 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2649 | }; |
2650 | ||
844a3b63 PW |
2651 | /* l4_core -> timer10 */ |
2652 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { | |
2653 | .master = &omap3xxx_l4_core_hwmod, | |
2654 | .slave = &omap3xxx_timer10_hwmod, | |
2655 | .clk = "gpt10_ick", | |
2656 | .addr = omap2_timer10_addrs, | |
2657 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2658 | }; |
2659 | ||
844a3b63 PW |
2660 | /* l4_core -> timer11 */ |
2661 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { | |
2662 | .master = &omap3xxx_l4_core_hwmod, | |
2663 | .slave = &omap3xxx_timer11_hwmod, | |
2664 | .clk = "gpt11_ick", | |
2665 | .addr = omap2_timer11_addrs, | |
2666 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2667 | }; |
2668 | ||
844a3b63 | 2669 | static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { |
0f9dfdd3 | 2670 | { |
844a3b63 PW |
2671 | .pa_start = 0x48304000, |
2672 | .pa_end = 0x48304000 + SZ_1K - 1, | |
2673 | .flags = ADDR_TYPE_RT | |
0f9dfdd3 | 2674 | }, |
78183f3f | 2675 | { } |
0f9dfdd3 FC |
2676 | }; |
2677 | ||
844a3b63 PW |
2678 | /* l4_core -> timer12 */ |
2679 | static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { | |
2680 | .master = &omap3xxx_l4_sec_hwmod, | |
2681 | .slave = &omap3xxx_timer12_hwmod, | |
2682 | .clk = "gpt12_ick", | |
2683 | .addr = omap3xxx_timer12_addrs, | |
0f9dfdd3 FC |
2684 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2685 | }; | |
2686 | ||
844a3b63 PW |
2687 | /* l4_wkup -> wd_timer2 */ |
2688 | static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { | |
2689 | { | |
2690 | .pa_start = 0x48314000, | |
2691 | .pa_end = 0x4831407f, | |
2692 | .flags = ADDR_TYPE_RT | |
0f9dfdd3 | 2693 | }, |
844a3b63 | 2694 | { } |
0f9dfdd3 FC |
2695 | }; |
2696 | ||
844a3b63 PW |
2697 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { |
2698 | .master = &omap3xxx_l4_wkup_hwmod, | |
2699 | .slave = &omap3xxx_wd_timer2_hwmod, | |
2700 | .clk = "wdt2_ick", | |
2701 | .addr = omap3xxx_wd_timer2_addrs, | |
2702 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2703 | }; | |
2704 | ||
2705 | /* l4_core -> dss */ | |
2706 | static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { | |
0f616a4e | 2707 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2708 | .slave = &omap3430es1_dss_core_hwmod, |
2709 | .clk = "dss_ick", | |
2710 | .addr = omap2_dss_addrs, | |
2711 | .fw = { | |
2712 | .omap2 = { | |
2713 | .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, | |
2714 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2715 | .flags = OMAP_FIREWALL_L4, | |
2716 | } | |
2717 | }, | |
0f616a4e C |
2718 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2719 | }; | |
2720 | ||
844a3b63 | 2721 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { |
0f616a4e | 2722 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2723 | .slave = &omap3xxx_dss_core_hwmod, |
2724 | .clk = "dss_ick", | |
2725 | .addr = omap2_dss_addrs, | |
2726 | .fw = { | |
2727 | .omap2 = { | |
2728 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, | |
2729 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2730 | .flags = OMAP_FIREWALL_L4, | |
2731 | } | |
2732 | }, | |
0f616a4e C |
2733 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2734 | }; | |
2735 | ||
844a3b63 PW |
2736 | /* l4_core -> dss_dispc */ |
2737 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { | |
0f616a4e | 2738 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2739 | .slave = &omap3xxx_dss_dispc_hwmod, |
2740 | .clk = "dss_ick", | |
2741 | .addr = omap2_dss_dispc_addrs, | |
2742 | .fw = { | |
2743 | .omap2 = { | |
2744 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, | |
2745 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2746 | .flags = OMAP_FIREWALL_L4, | |
2747 | } | |
2748 | }, | |
0f616a4e C |
2749 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2750 | }; | |
2751 | ||
844a3b63 | 2752 | static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { |
0f616a4e | 2753 | { |
844a3b63 PW |
2754 | .pa_start = 0x4804FC00, |
2755 | .pa_end = 0x4804FFFF, | |
2756 | .flags = ADDR_TYPE_RT | |
0f616a4e | 2757 | }, |
78183f3f | 2758 | { } |
0f616a4e C |
2759 | }; |
2760 | ||
844a3b63 PW |
2761 | /* l4_core -> dss_dsi1 */ |
2762 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { | |
0f616a4e | 2763 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2764 | .slave = &omap3xxx_dss_dsi1_hwmod, |
2765 | .clk = "dss_ick", | |
2766 | .addr = omap3xxx_dss_dsi1_addrs, | |
2767 | .fw = { | |
2768 | .omap2 = { | |
2769 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, | |
2770 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2771 | .flags = OMAP_FIREWALL_L4, | |
2772 | } | |
2773 | }, | |
0f616a4e C |
2774 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2775 | }; | |
2776 | ||
844a3b63 PW |
2777 | /* l4_core -> dss_rfbi */ |
2778 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { | |
2779 | .master = &omap3xxx_l4_core_hwmod, | |
2780 | .slave = &omap3xxx_dss_rfbi_hwmod, | |
2781 | .clk = "dss_ick", | |
2782 | .addr = omap2_dss_rfbi_addrs, | |
2783 | .fw = { | |
0f616a4e | 2784 | .omap2 = { |
844a3b63 PW |
2785 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, |
2786 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , | |
2787 | .flags = OMAP_FIREWALL_L4, | |
2788 | } | |
0f616a4e | 2789 | }, |
844a3b63 | 2790 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
0f616a4e C |
2791 | }; |
2792 | ||
844a3b63 PW |
2793 | /* l4_core -> dss_venc */ |
2794 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { | |
2795 | .master = &omap3xxx_l4_core_hwmod, | |
2796 | .slave = &omap3xxx_dss_venc_hwmod, | |
2797 | .clk = "dss_ick", | |
2798 | .addr = omap2_dss_venc_addrs, | |
2799 | .fw = { | |
70034d38 | 2800 | .omap2 = { |
844a3b63 PW |
2801 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, |
2802 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2803 | .flags = OMAP_FIREWALL_L4, | |
2804 | } | |
70034d38 | 2805 | }, |
844a3b63 PW |
2806 | .flags = OCPIF_SWSUP_IDLE, |
2807 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2808 | }; |
2809 | ||
844a3b63 PW |
2810 | /* l4_wkup -> gpio1 */ |
2811 | static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { | |
2812 | { | |
2813 | .pa_start = 0x48310000, | |
2814 | .pa_end = 0x483101ff, | |
2815 | .flags = ADDR_TYPE_RT | |
2816 | }, | |
2817 | { } | |
70034d38 VC |
2818 | }; |
2819 | ||
844a3b63 PW |
2820 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { |
2821 | .master = &omap3xxx_l4_wkup_hwmod, | |
2822 | .slave = &omap3xxx_gpio1_hwmod, | |
2823 | .addr = omap3xxx_gpio1_addrs, | |
2824 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f616a4e C |
2825 | }; |
2826 | ||
844a3b63 PW |
2827 | /* l4_per -> gpio2 */ |
2828 | static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { | |
2829 | { | |
2830 | .pa_start = 0x49050000, | |
2831 | .pa_end = 0x490501ff, | |
2832 | .flags = ADDR_TYPE_RT | |
70034d38 | 2833 | }, |
844a3b63 | 2834 | { } |
70034d38 VC |
2835 | }; |
2836 | ||
844a3b63 PW |
2837 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { |
2838 | .master = &omap3xxx_l4_per_hwmod, | |
2839 | .slave = &omap3xxx_gpio2_hwmod, | |
2840 | .addr = omap3xxx_gpio2_addrs, | |
2841 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2842 | }; |
2843 | ||
844a3b63 PW |
2844 | /* l4_per -> gpio3 */ |
2845 | static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { | |
2846 | { | |
2847 | .pa_start = 0x49052000, | |
2848 | .pa_end = 0x490521ff, | |
2849 | .flags = ADDR_TYPE_RT | |
2850 | }, | |
2851 | { } | |
70034d38 VC |
2852 | }; |
2853 | ||
844a3b63 PW |
2854 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { |
2855 | .master = &omap3xxx_l4_per_hwmod, | |
2856 | .slave = &omap3xxx_gpio3_hwmod, | |
2857 | .addr = omap3xxx_gpio3_addrs, | |
2858 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f616a4e C |
2859 | }; |
2860 | ||
844a3b63 PW |
2861 | /* l4_per -> gpio4 */ |
2862 | static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { | |
2863 | { | |
2864 | .pa_start = 0x49054000, | |
2865 | .pa_end = 0x490541ff, | |
2866 | .flags = ADDR_TYPE_RT | |
70034d38 | 2867 | }, |
844a3b63 | 2868 | { } |
70034d38 VC |
2869 | }; |
2870 | ||
844a3b63 PW |
2871 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { |
2872 | .master = &omap3xxx_l4_per_hwmod, | |
2873 | .slave = &omap3xxx_gpio4_hwmod, | |
2874 | .addr = omap3xxx_gpio4_addrs, | |
2875 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2876 | }; |
2877 | ||
844a3b63 PW |
2878 | /* l4_per -> gpio5 */ |
2879 | static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { | |
2880 | { | |
2881 | .pa_start = 0x49056000, | |
2882 | .pa_end = 0x490561ff, | |
2883 | .flags = ADDR_TYPE_RT | |
2884 | }, | |
2885 | { } | |
01438ab6 MK |
2886 | }; |
2887 | ||
844a3b63 PW |
2888 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { |
2889 | .master = &omap3xxx_l4_per_hwmod, | |
2890 | .slave = &omap3xxx_gpio5_hwmod, | |
2891 | .addr = omap3xxx_gpio5_addrs, | |
2892 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2893 | }; |
2894 | ||
844a3b63 PW |
2895 | /* l4_per -> gpio6 */ |
2896 | static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { | |
2897 | { | |
2898 | .pa_start = 0x49058000, | |
2899 | .pa_end = 0x490581ff, | |
2900 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2901 | }, |
844a3b63 | 2902 | { } |
01438ab6 MK |
2903 | }; |
2904 | ||
844a3b63 PW |
2905 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { |
2906 | .master = &omap3xxx_l4_per_hwmod, | |
2907 | .slave = &omap3xxx_gpio6_hwmod, | |
2908 | .addr = omap3xxx_gpio6_addrs, | |
2909 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2910 | }; |
2911 | ||
844a3b63 PW |
2912 | /* dma_system -> L3 */ |
2913 | static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { | |
2914 | .master = &omap3xxx_dma_system_hwmod, | |
2915 | .slave = &omap3xxx_l3_main_hwmod, | |
2916 | .clk = "core_l3_ick", | |
2917 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2918 | }; |
2919 | ||
844a3b63 PW |
2920 | static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { |
2921 | { | |
2922 | .pa_start = 0x48056000, | |
2923 | .pa_end = 0x48056fff, | |
2924 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2925 | }, |
844a3b63 | 2926 | { } |
01438ab6 MK |
2927 | }; |
2928 | ||
844a3b63 PW |
2929 | /* l4_cfg -> dma_system */ |
2930 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { | |
2931 | .master = &omap3xxx_l4_core_hwmod, | |
2932 | .slave = &omap3xxx_dma_system_hwmod, | |
2933 | .clk = "core_l4_ick", | |
2934 | .addr = omap3xxx_dma_system_addrs, | |
2935 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2936 | }; |
2937 | ||
844a3b63 PW |
2938 | static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { |
2939 | { | |
2940 | .name = "mpu", | |
2941 | .pa_start = 0x48074000, | |
2942 | .pa_end = 0x480740ff, | |
2943 | .flags = ADDR_TYPE_RT | |
2944 | }, | |
2945 | { } | |
d3442726 TG |
2946 | }; |
2947 | ||
844a3b63 PW |
2948 | /* l4_core -> mcbsp1 */ |
2949 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { | |
2950 | .master = &omap3xxx_l4_core_hwmod, | |
2951 | .slave = &omap3xxx_mcbsp1_hwmod, | |
2952 | .clk = "mcbsp1_ick", | |
2953 | .addr = omap3xxx_mcbsp1_addrs, | |
2954 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2955 | }; |
2956 | ||
844a3b63 PW |
2957 | static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { |
2958 | { | |
2959 | .name = "mpu", | |
2960 | .pa_start = 0x49022000, | |
2961 | .pa_end = 0x490220ff, | |
2962 | .flags = ADDR_TYPE_RT | |
2963 | }, | |
2964 | { } | |
d3442726 TG |
2965 | }; |
2966 | ||
844a3b63 PW |
2967 | /* l4_per -> mcbsp2 */ |
2968 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { | |
2969 | .master = &omap3xxx_l4_per_hwmod, | |
2970 | .slave = &omap3xxx_mcbsp2_hwmod, | |
2971 | .clk = "mcbsp2_ick", | |
2972 | .addr = omap3xxx_mcbsp2_addrs, | |
2973 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2974 | }; |
2975 | ||
844a3b63 PW |
2976 | static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { |
2977 | { | |
2978 | .name = "mpu", | |
2979 | .pa_start = 0x49024000, | |
2980 | .pa_end = 0x490240ff, | |
2981 | .flags = ADDR_TYPE_RT | |
2982 | }, | |
2983 | { } | |
d3442726 TG |
2984 | }; |
2985 | ||
844a3b63 PW |
2986 | /* l4_per -> mcbsp3 */ |
2987 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { | |
2988 | .master = &omap3xxx_l4_per_hwmod, | |
2989 | .slave = &omap3xxx_mcbsp3_hwmod, | |
2990 | .clk = "mcbsp3_ick", | |
2991 | .addr = omap3xxx_mcbsp3_addrs, | |
2992 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
a52e2ab6 PW |
2993 | }; |
2994 | ||
844a3b63 PW |
2995 | static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { |
2996 | { | |
2997 | .name = "mpu", | |
2998 | .pa_start = 0x49026000, | |
2999 | .pa_end = 0x490260ff, | |
3000 | .flags = ADDR_TYPE_RT | |
a52e2ab6 | 3001 | }, |
844a3b63 | 3002 | { } |
a52e2ab6 PW |
3003 | }; |
3004 | ||
844a3b63 PW |
3005 | /* l4_per -> mcbsp4 */ |
3006 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { | |
3007 | .master = &omap3xxx_l4_per_hwmod, | |
3008 | .slave = &omap3xxx_mcbsp4_hwmod, | |
3009 | .clk = "mcbsp4_ick", | |
3010 | .addr = omap3xxx_mcbsp4_addrs, | |
3011 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3012 | }; |
3013 | ||
844a3b63 PW |
3014 | static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { |
3015 | { | |
3016 | .name = "mpu", | |
3017 | .pa_start = 0x48096000, | |
3018 | .pa_end = 0x480960ff, | |
3019 | .flags = ADDR_TYPE_RT | |
3020 | }, | |
3021 | { } | |
3022 | }; | |
b163605e | 3023 | |
844a3b63 PW |
3024 | /* l4_core -> mcbsp5 */ |
3025 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { | |
3026 | .master = &omap3xxx_l4_core_hwmod, | |
3027 | .slave = &omap3xxx_mcbsp5_hwmod, | |
3028 | .clk = "mcbsp5_ick", | |
3029 | .addr = omap3xxx_mcbsp5_addrs, | |
3030 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3031 | }; |
3032 | ||
844a3b63 PW |
3033 | static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { |
3034 | { | |
3035 | .name = "sidetone", | |
3036 | .pa_start = 0x49028000, | |
3037 | .pa_end = 0x490280ff, | |
3038 | .flags = ADDR_TYPE_RT | |
3039 | }, | |
3040 | { } | |
d3442726 TG |
3041 | }; |
3042 | ||
844a3b63 PW |
3043 | /* l4_per -> mcbsp2_sidetone */ |
3044 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { | |
3045 | .master = &omap3xxx_l4_per_hwmod, | |
3046 | .slave = &omap3xxx_mcbsp2_sidetone_hwmod, | |
3047 | .clk = "mcbsp2_ick", | |
3048 | .addr = omap3xxx_mcbsp2_sidetone_addrs, | |
3049 | .user = OCP_USER_MPU, | |
b163605e PW |
3050 | }; |
3051 | ||
844a3b63 PW |
3052 | static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { |
3053 | { | |
3054 | .name = "sidetone", | |
3055 | .pa_start = 0x4902A000, | |
3056 | .pa_end = 0x4902A0ff, | |
3057 | .flags = ADDR_TYPE_RT | |
3058 | }, | |
3059 | { } | |
a52e2ab6 PW |
3060 | }; |
3061 | ||
844a3b63 PW |
3062 | /* l4_per -> mcbsp3_sidetone */ |
3063 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { | |
3064 | .master = &omap3xxx_l4_per_hwmod, | |
3065 | .slave = &omap3xxx_mcbsp3_sidetone_hwmod, | |
3066 | .clk = "mcbsp3_ick", | |
3067 | .addr = omap3xxx_mcbsp3_sidetone_addrs, | |
3068 | .user = OCP_USER_MPU, | |
a52e2ab6 PW |
3069 | }; |
3070 | ||
844a3b63 PW |
3071 | static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { |
3072 | { | |
3073 | .pa_start = 0x48094000, | |
3074 | .pa_end = 0x480941ff, | |
3075 | .flags = ADDR_TYPE_RT, | |
d3442726 | 3076 | }, |
844a3b63 | 3077 | { } |
d3442726 TG |
3078 | }; |
3079 | ||
844a3b63 PW |
3080 | /* l4_core -> mailbox */ |
3081 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { | |
3082 | .master = &omap3xxx_l4_core_hwmod, | |
3083 | .slave = &omap3xxx_mailbox_hwmod, | |
3084 | .addr = omap3xxx_mailbox_addrs, | |
3085 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3086 | }; | |
b163605e | 3087 | |
844a3b63 PW |
3088 | /* l4 core -> mcspi1 interface */ |
3089 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { | |
3090 | .master = &omap3xxx_l4_core_hwmod, | |
3091 | .slave = &omap34xx_mcspi1, | |
3092 | .clk = "mcspi1_ick", | |
3093 | .addr = omap2_mcspi1_addr_space, | |
3094 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
3095 | }; |
3096 | ||
844a3b63 PW |
3097 | /* l4 core -> mcspi2 interface */ |
3098 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { | |
3099 | .master = &omap3xxx_l4_core_hwmod, | |
3100 | .slave = &omap34xx_mcspi2, | |
3101 | .clk = "mcspi2_ick", | |
3102 | .addr = omap2_mcspi2_addr_space, | |
3103 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
3104 | }; |
3105 | ||
844a3b63 PW |
3106 | /* l4 core -> mcspi3 interface */ |
3107 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { | |
3108 | .master = &omap3xxx_l4_core_hwmod, | |
3109 | .slave = &omap34xx_mcspi3, | |
3110 | .clk = "mcspi3_ick", | |
3111 | .addr = omap2430_mcspi3_addr_space, | |
3112 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
3113 | }; |
3114 | ||
844a3b63 PW |
3115 | /* l4 core -> mcspi4 interface */ |
3116 | static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { | |
3117 | { | |
3118 | .pa_start = 0x480ba000, | |
3119 | .pa_end = 0x480ba0ff, | |
3120 | .flags = ADDR_TYPE_RT, | |
d3442726 | 3121 | }, |
844a3b63 PW |
3122 | { } |
3123 | }; | |
3124 | ||
3125 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { | |
3126 | .master = &omap3xxx_l4_core_hwmod, | |
3127 | .slave = &omap34xx_mcspi4, | |
3128 | .clk = "mcspi4_ick", | |
3129 | .addr = omap34xx_mcspi4_addr_space, | |
3130 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3131 | }; |
3132 | ||
de231388 KM |
3133 | static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { |
3134 | .master = &omap3xxx_usb_host_hs_hwmod, | |
3135 | .slave = &omap3xxx_l3_main_hwmod, | |
3136 | .clk = "core_l3_ick", | |
3137 | .user = OCP_USER_MPU, | |
3138 | }; | |
3139 | ||
de231388 KM |
3140 | static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = { |
3141 | { | |
3142 | .name = "uhh", | |
3143 | .pa_start = 0x48064000, | |
3144 | .pa_end = 0x480643ff, | |
3145 | .flags = ADDR_TYPE_RT | |
3146 | }, | |
3147 | { | |
3148 | .name = "ohci", | |
3149 | .pa_start = 0x48064400, | |
3150 | .pa_end = 0x480647ff, | |
3151 | }, | |
3152 | { | |
3153 | .name = "ehci", | |
3154 | .pa_start = 0x48064800, | |
3155 | .pa_end = 0x48064cff, | |
3156 | }, | |
3157 | {} | |
3158 | }; | |
3159 | ||
3160 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { | |
3161 | .master = &omap3xxx_l4_core_hwmod, | |
3162 | .slave = &omap3xxx_usb_host_hs_hwmod, | |
3163 | .clk = "usbhost_ick", | |
3164 | .addr = omap3xxx_usb_host_hs_addrs, | |
3165 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3166 | }; | |
3167 | ||
de231388 KM |
3168 | static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = { |
3169 | { | |
3170 | .name = "tll", | |
3171 | .pa_start = 0x48062000, | |
3172 | .pa_end = 0x48062fff, | |
3173 | .flags = ADDR_TYPE_RT | |
3174 | }, | |
3175 | {} | |
3176 | }; | |
3177 | ||
3178 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { | |
3179 | .master = &omap3xxx_l4_core_hwmod, | |
3180 | .slave = &omap3xxx_usb_tll_hs_hwmod, | |
3181 | .clk = "usbtll_ick", | |
3182 | .addr = omap3xxx_usb_tll_hs_addrs, | |
3183 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3184 | }; | |
3185 | ||
45a4bb06 PW |
3186 | /* l4_core -> hdq1w interface */ |
3187 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = { | |
3188 | .master = &omap3xxx_l4_core_hwmod, | |
3189 | .slave = &omap3xxx_hdq1w_hwmod, | |
3190 | .clk = "hdq_ick", | |
3191 | .addr = omap2_hdq1w_addr_space, | |
3192 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3193 | .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, | |
3194 | }; | |
3195 | ||
c8d82ff6 VH |
3196 | /* l4_wkup -> 32ksync_counter */ |
3197 | static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = { | |
3198 | { | |
3199 | .pa_start = 0x48320000, | |
3200 | .pa_end = 0x4832001f, | |
3201 | .flags = ADDR_TYPE_RT | |
3202 | }, | |
3203 | { } | |
3204 | }; | |
3205 | ||
3206 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = { | |
3207 | .master = &omap3xxx_l4_wkup_hwmod, | |
3208 | .slave = &omap3xxx_counter_32k_hwmod, | |
3209 | .clk = "omap_32ksync_ick", | |
3210 | .addr = omap3xxx_counter_32k_addrs, | |
3211 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3212 | }; | |
3213 | ||
31ba8808 MG |
3214 | /* am35xx has Davinci MDIO & EMAC */ |
3215 | static struct omap_hwmod_class am35xx_mdio_class = { | |
3216 | .name = "davinci_mdio", | |
3217 | }; | |
3218 | ||
3219 | static struct omap_hwmod am35xx_mdio_hwmod = { | |
3220 | .name = "davinci_mdio", | |
3221 | .class = &am35xx_mdio_class, | |
3222 | .flags = HWMOD_NO_IDLEST, | |
3223 | }; | |
3224 | ||
3225 | /* | |
3226 | * XXX Should be connected to an IPSS hwmod, not the L3 directly; | |
3227 | * but this will probably require some additional hwmod core support, | |
3228 | * so is left as a future to-do item. | |
3229 | */ | |
3230 | static struct omap_hwmod_ocp_if am35xx_mdio__l3 = { | |
3231 | .master = &am35xx_mdio_hwmod, | |
3232 | .slave = &omap3xxx_l3_main_hwmod, | |
3233 | .clk = "emac_fck", | |
3234 | .user = OCP_USER_MPU, | |
3235 | }; | |
3236 | ||
3237 | static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = { | |
3238 | { | |
3239 | .pa_start = AM35XX_IPSS_MDIO_BASE, | |
3240 | .pa_end = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1, | |
3241 | .flags = ADDR_TYPE_RT, | |
3242 | }, | |
3243 | { } | |
3244 | }; | |
3245 | ||
3246 | /* l4_core -> davinci mdio */ | |
3247 | /* | |
3248 | * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; | |
3249 | * but this will probably require some additional hwmod core support, | |
3250 | * so is left as a future to-do item. | |
3251 | */ | |
3252 | static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = { | |
3253 | .master = &omap3xxx_l4_core_hwmod, | |
3254 | .slave = &am35xx_mdio_hwmod, | |
3255 | .clk = "emac_fck", | |
3256 | .addr = am35xx_mdio_addrs, | |
3257 | .user = OCP_USER_MPU, | |
3258 | }; | |
3259 | ||
3260 | static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = { | |
7d7e1eba TL |
3261 | { .name = "rxthresh", .irq = 67 + OMAP_INTC_START, }, |
3262 | { .name = "rx_pulse", .irq = 68 + OMAP_INTC_START, }, | |
3263 | { .name = "tx_pulse", .irq = 69 + OMAP_INTC_START }, | |
3264 | { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START }, | |
3265 | { .irq = -1 }, | |
31ba8808 MG |
3266 | }; |
3267 | ||
3268 | static struct omap_hwmod_class am35xx_emac_class = { | |
3269 | .name = "davinci_emac", | |
3270 | }; | |
3271 | ||
3272 | static struct omap_hwmod am35xx_emac_hwmod = { | |
3273 | .name = "davinci_emac", | |
3274 | .mpu_irqs = am35xx_emac_mpu_irqs, | |
3275 | .class = &am35xx_emac_class, | |
3276 | .flags = HWMOD_NO_IDLEST, | |
3277 | }; | |
3278 | ||
3279 | /* l3_core -> davinci emac interface */ | |
3280 | /* | |
3281 | * XXX Should be connected to an IPSS hwmod, not the L3 directly; | |
3282 | * but this will probably require some additional hwmod core support, | |
3283 | * so is left as a future to-do item. | |
3284 | */ | |
3285 | static struct omap_hwmod_ocp_if am35xx_emac__l3 = { | |
3286 | .master = &am35xx_emac_hwmod, | |
3287 | .slave = &omap3xxx_l3_main_hwmod, | |
3288 | .clk = "emac_ick", | |
3289 | .user = OCP_USER_MPU, | |
3290 | }; | |
3291 | ||
3292 | static struct omap_hwmod_addr_space am35xx_emac_addrs[] = { | |
3293 | { | |
3294 | .pa_start = AM35XX_IPSS_EMAC_BASE, | |
3295 | .pa_end = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1, | |
3296 | .flags = ADDR_TYPE_RT, | |
3297 | }, | |
3298 | { } | |
3299 | }; | |
3300 | ||
3301 | /* l4_core -> davinci emac */ | |
3302 | /* | |
3303 | * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; | |
3304 | * but this will probably require some additional hwmod core support, | |
3305 | * so is left as a future to-do item. | |
3306 | */ | |
3307 | static struct omap_hwmod_ocp_if am35xx_l4_core__emac = { | |
3308 | .master = &omap3xxx_l4_core_hwmod, | |
3309 | .slave = &am35xx_emac_hwmod, | |
3310 | .clk = "emac_ick", | |
3311 | .addr = am35xx_emac_addrs, | |
3312 | .user = OCP_USER_MPU, | |
3313 | }; | |
3314 | ||
0a78c5c5 PW |
3315 | static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { |
3316 | &omap3xxx_l3_main__l4_core, | |
3317 | &omap3xxx_l3_main__l4_per, | |
3318 | &omap3xxx_mpu__l3_main, | |
3319 | &omap3xxx_l4_core__l4_wkup, | |
3320 | &omap3xxx_l4_core__mmc3, | |
3321 | &omap3_l4_core__uart1, | |
3322 | &omap3_l4_core__uart2, | |
3323 | &omap3_l4_per__uart3, | |
3324 | &omap3_l4_core__i2c1, | |
3325 | &omap3_l4_core__i2c2, | |
3326 | &omap3_l4_core__i2c3, | |
3327 | &omap3xxx_l4_wkup__l4_sec, | |
3328 | &omap3xxx_l4_wkup__timer1, | |
3329 | &omap3xxx_l4_per__timer2, | |
3330 | &omap3xxx_l4_per__timer3, | |
3331 | &omap3xxx_l4_per__timer4, | |
3332 | &omap3xxx_l4_per__timer5, | |
3333 | &omap3xxx_l4_per__timer6, | |
3334 | &omap3xxx_l4_per__timer7, | |
3335 | &omap3xxx_l4_per__timer8, | |
3336 | &omap3xxx_l4_per__timer9, | |
3337 | &omap3xxx_l4_core__timer10, | |
3338 | &omap3xxx_l4_core__timer11, | |
3339 | &omap3xxx_l4_wkup__wd_timer2, | |
3340 | &omap3xxx_l4_wkup__gpio1, | |
3341 | &omap3xxx_l4_per__gpio2, | |
3342 | &omap3xxx_l4_per__gpio3, | |
3343 | &omap3xxx_l4_per__gpio4, | |
3344 | &omap3xxx_l4_per__gpio5, | |
3345 | &omap3xxx_l4_per__gpio6, | |
3346 | &omap3xxx_dma_system__l3, | |
3347 | &omap3xxx_l4_core__dma_system, | |
3348 | &omap3xxx_l4_core__mcbsp1, | |
3349 | &omap3xxx_l4_per__mcbsp2, | |
3350 | &omap3xxx_l4_per__mcbsp3, | |
3351 | &omap3xxx_l4_per__mcbsp4, | |
3352 | &omap3xxx_l4_core__mcbsp5, | |
3353 | &omap3xxx_l4_per__mcbsp2_sidetone, | |
3354 | &omap3xxx_l4_per__mcbsp3_sidetone, | |
3355 | &omap34xx_l4_core__mcspi1, | |
3356 | &omap34xx_l4_core__mcspi2, | |
3357 | &omap34xx_l4_core__mcspi3, | |
3358 | &omap34xx_l4_core__mcspi4, | |
c8d82ff6 | 3359 | &omap3xxx_l4_wkup__counter_32k, |
d6504acd PW |
3360 | NULL, |
3361 | }; | |
3362 | ||
0a78c5c5 PW |
3363 | /* GP-only hwmod links */ |
3364 | static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = { | |
3365 | &omap3xxx_l4_sec__timer12, | |
91a36bdb AK |
3366 | NULL |
3367 | }; | |
3368 | ||
0a78c5c5 PW |
3369 | /* 3430ES1-only hwmod links */ |
3370 | static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = { | |
3371 | &omap3430es1_dss__l3, | |
3372 | &omap3430es1_l4_core__dss, | |
d6504acd PW |
3373 | NULL |
3374 | }; | |
3375 | ||
0a78c5c5 PW |
3376 | /* 3430ES2+-only hwmod links */ |
3377 | static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = { | |
3378 | &omap3xxx_dss__l3, | |
3379 | &omap3xxx_l4_core__dss, | |
3380 | &omap3xxx_usbhsotg__l3, | |
3381 | &omap3xxx_l4_core__usbhsotg, | |
3382 | &omap3xxx_usb_host_hs__l3_main_2, | |
3383 | &omap3xxx_l4_core__usb_host_hs, | |
3384 | &omap3xxx_l4_core__usb_tll_hs, | |
d6504acd PW |
3385 | NULL |
3386 | }; | |
870ea2b8 | 3387 | |
0a78c5c5 PW |
3388 | /* <= 3430ES3-only hwmod links */ |
3389 | static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = { | |
3390 | &omap3xxx_l4_core__pre_es3_mmc1, | |
3391 | &omap3xxx_l4_core__pre_es3_mmc2, | |
a52e2ab6 PW |
3392 | NULL |
3393 | }; | |
3394 | ||
0a78c5c5 PW |
3395 | /* 3430ES3+-only hwmod links */ |
3396 | static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = { | |
3397 | &omap3xxx_l4_core__es3plus_mmc1, | |
3398 | &omap3xxx_l4_core__es3plus_mmc2, | |
a52e2ab6 PW |
3399 | NULL |
3400 | }; | |
3401 | ||
0a78c5c5 PW |
3402 | /* 34xx-only hwmod links (all ES revisions) */ |
3403 | static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { | |
3404 | &omap3xxx_l3__iva, | |
3405 | &omap34xx_l4_core__sr1, | |
3406 | &omap34xx_l4_core__sr2, | |
3407 | &omap3xxx_l4_core__mailbox, | |
45a4bb06 | 3408 | &omap3xxx_l4_core__hdq1w, |
8f993a01 | 3409 | &omap3xxx_sad2d__l3, |
d6504acd PW |
3410 | NULL |
3411 | }; | |
273ff8c3 | 3412 | |
0a78c5c5 PW |
3413 | /* 36xx-only hwmod links (all ES revisions) */ |
3414 | static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { | |
3415 | &omap3xxx_l3__iva, | |
3416 | &omap36xx_l4_per__uart4, | |
3417 | &omap3xxx_dss__l3, | |
3418 | &omap3xxx_l4_core__dss, | |
3419 | &omap36xx_l4_core__sr1, | |
3420 | &omap36xx_l4_core__sr2, | |
3421 | &omap3xxx_usbhsotg__l3, | |
3422 | &omap3xxx_l4_core__usbhsotg, | |
3423 | &omap3xxx_l4_core__mailbox, | |
3424 | &omap3xxx_usb_host_hs__l3_main_2, | |
3425 | &omap3xxx_l4_core__usb_host_hs, | |
3426 | &omap3xxx_l4_core__usb_tll_hs, | |
3427 | &omap3xxx_l4_core__es3plus_mmc1, | |
3428 | &omap3xxx_l4_core__es3plus_mmc2, | |
45a4bb06 | 3429 | &omap3xxx_l4_core__hdq1w, |
8f993a01 | 3430 | &omap3xxx_sad2d__l3, |
d6504acd PW |
3431 | NULL |
3432 | }; | |
3433 | ||
0a78c5c5 PW |
3434 | static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { |
3435 | &omap3xxx_dss__l3, | |
3436 | &omap3xxx_l4_core__dss, | |
3437 | &am35xx_usbhsotg__l3, | |
3438 | &am35xx_l4_core__usbhsotg, | |
3439 | &am35xx_l4_core__uart4, | |
3440 | &omap3xxx_usb_host_hs__l3_main_2, | |
3441 | &omap3xxx_l4_core__usb_host_hs, | |
3442 | &omap3xxx_l4_core__usb_tll_hs, | |
3443 | &omap3xxx_l4_core__es3plus_mmc1, | |
3444 | &omap3xxx_l4_core__es3plus_mmc2, | |
31ba8808 MG |
3445 | &am35xx_mdio__l3, |
3446 | &am35xx_l4_core__mdio, | |
3447 | &am35xx_emac__l3, | |
3448 | &am35xx_l4_core__emac, | |
d6504acd | 3449 | NULL |
7359154e PW |
3450 | }; |
3451 | ||
0a78c5c5 PW |
3452 | static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { |
3453 | &omap3xxx_l4_core__dss_dispc, | |
3454 | &omap3xxx_l4_core__dss_dsi1, | |
3455 | &omap3xxx_l4_core__dss_rfbi, | |
3456 | &omap3xxx_l4_core__dss_venc, | |
1d2f56c8 IY |
3457 | NULL |
3458 | }; | |
3459 | ||
7359154e PW |
3460 | int __init omap3xxx_hwmod_init(void) |
3461 | { | |
d6504acd | 3462 | int r; |
0a78c5c5 | 3463 | struct omap_hwmod_ocp_if **h = NULL; |
d6504acd PW |
3464 | unsigned int rev; |
3465 | ||
9ebfd285 KH |
3466 | omap_hwmod_init(); |
3467 | ||
0a78c5c5 PW |
3468 | /* Register hwmod links common to all OMAP3 */ |
3469 | r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); | |
ace90216 | 3470 | if (r < 0) |
d6504acd PW |
3471 | return r; |
3472 | ||
0a78c5c5 | 3473 | /* Register GP-only hwmod links. */ |
91a36bdb | 3474 | if (omap_type() == OMAP2_DEVICE_TYPE_GP) { |
0a78c5c5 | 3475 | r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs); |
91a36bdb AK |
3476 | if (r < 0) |
3477 | return r; | |
3478 | } | |
3479 | ||
d6504acd PW |
3480 | rev = omap_rev(); |
3481 | ||
3482 | /* | |
0a78c5c5 | 3483 | * Register hwmod links common to individual OMAP3 families, all |
d6504acd PW |
3484 | * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) |
3485 | * All possible revisions should be included in this conditional. | |
3486 | */ | |
3487 | if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || | |
3488 | rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || | |
3489 | rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3490 | h = omap34xx_hwmod_ocp_ifs; |
68a88b98 | 3491 | } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { |
0a78c5c5 | 3492 | h = am35xx_hwmod_ocp_ifs; |
d6504acd PW |
3493 | } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || |
3494 | rev == OMAP3630_REV_ES1_2) { | |
0a78c5c5 | 3495 | h = omap36xx_hwmod_ocp_ifs; |
d6504acd PW |
3496 | } else { |
3497 | WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); | |
3498 | return -EINVAL; | |
3499 | }; | |
3500 | ||
0a78c5c5 | 3501 | r = omap_hwmod_register_links(h); |
ace90216 | 3502 | if (r < 0) |
d6504acd PW |
3503 | return r; |
3504 | ||
3505 | /* | |
0a78c5c5 | 3506 | * Register hwmod links specific to certain ES levels of a |
d6504acd PW |
3507 | * particular family of silicon (e.g., 34xx ES1.0) |
3508 | */ | |
3509 | h = NULL; | |
3510 | if (rev == OMAP3430_REV_ES1_0) { | |
0a78c5c5 | 3511 | h = omap3430es1_hwmod_ocp_ifs; |
d6504acd PW |
3512 | } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || |
3513 | rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || | |
3514 | rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3515 | h = omap3430es2plus_hwmod_ocp_ifs; |
d6504acd PW |
3516 | }; |
3517 | ||
a52e2ab6 | 3518 | if (h) { |
0a78c5c5 | 3519 | r = omap_hwmod_register_links(h); |
a52e2ab6 PW |
3520 | if (r < 0) |
3521 | return r; | |
3522 | } | |
3523 | ||
3524 | h = NULL; | |
3525 | if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || | |
3526 | rev == OMAP3430_REV_ES2_1) { | |
0a78c5c5 | 3527 | h = omap3430_pre_es3_hwmod_ocp_ifs; |
a52e2ab6 PW |
3528 | } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || |
3529 | rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3530 | h = omap3430_es3plus_hwmod_ocp_ifs; |
a52e2ab6 PW |
3531 | }; |
3532 | ||
d6504acd | 3533 | if (h) |
0a78c5c5 | 3534 | r = omap_hwmod_register_links(h); |
1d2f56c8 IY |
3535 | if (r < 0) |
3536 | return r; | |
3537 | ||
3538 | /* | |
3539 | * DSS code presumes that dss_core hwmod is handled first, | |
3540 | * _before_ any other DSS related hwmods so register common | |
0a78c5c5 PW |
3541 | * DSS hwmod links last to ensure that dss_core is already |
3542 | * registered. Otherwise some change things may happen, for | |
3543 | * ex. if dispc is handled before dss_core and DSS is enabled | |
3544 | * in bootloader DISPC will be reset with outputs enabled | |
3545 | * which sometimes leads to unrecoverable L3 error. XXX The | |
3546 | * long-term fix to this is to ensure hwmods are set up in | |
3547 | * dependency order in the hwmod core code. | |
1d2f56c8 | 3548 | */ |
0a78c5c5 | 3549 | r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs); |
d6504acd PW |
3550 | |
3551 | return r; | |
7359154e | 3552 | } |