ARM: OMAP2+: Make board-zoom.h local
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_3xxx_data.c
CommitLineData
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1/*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 *
78183f3f 4 * Copyright (C) 2009-2011 Nokia Corporation
0a78c5c5 5 * Copyright (C) 2012 Texas Instruments, Inc.
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6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * The data in this file should be completely autogeneratable from
13 * the TI hardware database or other technical documentation.
14 *
15 * XXX these should be marked initdata for multi-OMAP kernels
16 */
b86aeafc 17#include <linux/power/smartreflex.h>
4b25408f 18#include <linux/platform_data/gpio-omap.h>
b86aeafc 19
7359154e 20#include <plat/omap_hwmod.h>
2b6c4e73 21#include <plat-omap/dma-omap.h>
046465b7 22#include <plat/serial.h>
79e3cb22 23#include "l3_3xxx.h"
957988c7 24#include "l4_3xxx.h"
4fe20e97 25#include <plat/i2c.h>
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26#include <linux/platform_data/asoc-ti-mcbsp.h>
27#include <linux/platform_data/spi-omap2-mcspi.h>
ce722d26 28#include <plat/dmtimer.h>
5486474c 29#include <plat/iommu.h>
7359154e 30
4f9ed545 31#include "am35xx.h"
7d7e1eba 32
dbc04161 33#include "soc.h"
43b40992 34#include "omap_hwmod_common_data.h"
7359154e 35#include "prm-regbits-34xx.h"
6b667f88 36#include "cm-regbits-34xx.h"
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37
38#include "dma.h"
68f39e74 39#include "mmc.h"
ff2516fb 40#include "wd_timer.h"
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41
42/*
43 * OMAP3xxx hardware module integration data
44 *
844a3b63 45 * All of the data in this section should be autogeneratable from the
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46 * TI hardware database or other technical documentation. Data that
47 * is driver-specific or driver-kernel integration-specific belongs
48 * elsewhere.
49 */
50
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51/*
52 * IP blocks
53 */
7359154e 54
844a3b63 55/* L3 */
4bb194dc 56static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
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57 { .irq = 9 + OMAP_INTC_START, },
58 { .irq = 10 + OMAP_INTC_START, },
59 { .irq = -1 },
4bb194dc 60};
61
4a7cf90a 62static struct omap_hwmod omap3xxx_l3_main_hwmod = {
fa98347e 63 .name = "l3_main",
43b40992 64 .class = &l3_hwmod_class,
0d619a89 65 .mpu_irqs = omap3xxx_l3_main_irqs,
2eb1875d 66 .flags = HWMOD_NO_IDLEST,
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67};
68
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69/* L4 CORE */
70static struct omap_hwmod omap3xxx_l4_core_hwmod = {
71 .name = "l4_core",
72 .class = &l4_hwmod_class,
73 .flags = HWMOD_NO_IDLEST,
870ea2b8 74};
7359154e 75
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76/* L4 PER */
77static struct omap_hwmod omap3xxx_l4_per_hwmod = {
78 .name = "l4_per",
79 .class = &l4_hwmod_class,
80 .flags = HWMOD_NO_IDLEST,
273ff8c3 81};
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82
83/* L4 WKUP */
84static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
85 .name = "l4_wkup",
86 .class = &l4_hwmod_class,
87 .flags = HWMOD_NO_IDLEST,
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88};
89
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90/* L4 SEC */
91static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
92 .name = "l4_sec",
93 .class = &l4_hwmod_class,
94 .flags = HWMOD_NO_IDLEST,
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95};
96
844a3b63 97/* MPU */
ee75d95c 98static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
3dc3401c 99 { .name = "pmu", .irq = 3 + OMAP_INTC_START },
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100 { .irq = -1 }
101};
102
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103static struct omap_hwmod omap3xxx_mpu_hwmod = {
104 .name = "mpu",
ee75d95c 105 .mpu_irqs = omap3xxx_mpu_irqs,
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106 .class = &mpu_hwmod_class,
107 .main_clk = "arm_fck",
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108};
109
844a3b63 110/* IVA2 (IVA2) */
f42c5496 111static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
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112 { .name = "logic", .rst_shift = 0, .st_shift = 8 },
113 { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
114 { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
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115};
116
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117static struct omap_hwmod omap3xxx_iva_hwmod = {
118 .name = "iva",
119 .class = &iva_hwmod_class,
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120 .clkdm_name = "iva2_clkdm",
121 .rst_lines = omap3xxx_iva_resets,
122 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
123 .main_clk = "iva2_ck",
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124 .prcm = {
125 .omap2 = {
126 .module_offs = OMAP3430_IVA2_MOD,
127 .prcm_reg_id = 1,
128 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
129 .idlest_reg_id = 1,
130 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
131 }
132 },
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133};
134
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135/*
136 * 'debugss' class
137 * debug and emulation sub system
138 */
139
140static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
141 .name = "debugss",
142};
143
144/* debugss */
145static struct omap_hwmod omap3xxx_debugss_hwmod = {
146 .name = "debugss",
147 .class = &omap3xxx_debugss_hwmod_class,
148 .clkdm_name = "emu_clkdm",
149 .main_clk = "emu_src_ck",
150 .flags = HWMOD_NO_IDLEST,
151};
152
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153/* timer class */
154static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
155 .rev_offs = 0x0000,
156 .sysc_offs = 0x0010,
157 .syss_offs = 0x0014,
158 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
159 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
160 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
161 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
162 .sysc_fields = &omap_hwmod_sysc_type1,
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163};
164
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165static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
166 .name = "timer",
167 .sysc = &omap3xxx_timer_1ms_sysc,
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168};
169
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170static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
171 .rev_offs = 0x0000,
172 .sysc_offs = 0x0010,
173 .syss_offs = 0x0014,
174 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
175 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
176 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
177 .sysc_fields = &omap_hwmod_sysc_type1,
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178};
179
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180static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
181 .name = "timer",
182 .sysc = &omap3xxx_timer_sysc,
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183};
184
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185/* secure timers dev attribute */
186static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
139486fa 187 .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
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188};
189
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190/* always-on timers dev attribute */
191static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
192 .timer_capability = OMAP_TIMER_ALWON,
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193};
194
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195/* pwm timers dev attribute */
196static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
197 .timer_capability = OMAP_TIMER_HAS_PWM,
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198};
199
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200/* timers with DSP interrupt dev attribute */
201static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
202 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
203};
204
205/* pwm timers with DSP interrupt dev attribute */
206static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
207 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
208};
209
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210/* timer1 */
211static struct omap_hwmod omap3xxx_timer1_hwmod = {
212 .name = "timer1",
213 .mpu_irqs = omap2_timer1_mpu_irqs,
214 .main_clk = "gpt1_fck",
215 .prcm = {
216 .omap2 = {
217 .prcm_reg_id = 1,
218 .module_bit = OMAP3430_EN_GPT1_SHIFT,
219 .module_offs = WKUP_MOD,
220 .idlest_reg_id = 1,
221 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
222 },
046465b7 223 },
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224 .dev_attr = &capability_alwon_dev_attr,
225 .class = &omap3xxx_timer_1ms_hwmod_class,
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226};
227
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228/* timer2 */
229static struct omap_hwmod omap3xxx_timer2_hwmod = {
230 .name = "timer2",
231 .mpu_irqs = omap2_timer2_mpu_irqs,
232 .main_clk = "gpt2_fck",
233 .prcm = {
234 .omap2 = {
235 .prcm_reg_id = 1,
236 .module_bit = OMAP3430_EN_GPT2_SHIFT,
237 .module_offs = OMAP3430_PER_MOD,
238 .idlest_reg_id = 1,
239 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
240 },
241 },
844a3b63 242 .class = &omap3xxx_timer_1ms_hwmod_class,
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243};
244
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245/* timer3 */
246static struct omap_hwmod omap3xxx_timer3_hwmod = {
247 .name = "timer3",
248 .mpu_irqs = omap2_timer3_mpu_irqs,
249 .main_clk = "gpt3_fck",
250 .prcm = {
251 .omap2 = {
252 .prcm_reg_id = 1,
253 .module_bit = OMAP3430_EN_GPT3_SHIFT,
254 .module_offs = OMAP3430_PER_MOD,
255 .idlest_reg_id = 1,
256 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
257 },
258 },
844a3b63 259 .class = &omap3xxx_timer_hwmod_class,
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260};
261
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262/* timer4 */
263static struct omap_hwmod omap3xxx_timer4_hwmod = {
264 .name = "timer4",
265 .mpu_irqs = omap2_timer4_mpu_irqs,
266 .main_clk = "gpt4_fck",
267 .prcm = {
268 .omap2 = {
269 .prcm_reg_id = 1,
270 .module_bit = OMAP3430_EN_GPT4_SHIFT,
271 .module_offs = OMAP3430_PER_MOD,
272 .idlest_reg_id = 1,
273 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
274 },
275 },
844a3b63 276 .class = &omap3xxx_timer_hwmod_class,
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277};
278
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279/* timer5 */
280static struct omap_hwmod omap3xxx_timer5_hwmod = {
281 .name = "timer5",
282 .mpu_irqs = omap2_timer5_mpu_irqs,
283 .main_clk = "gpt5_fck",
284 .prcm = {
285 .omap2 = {
286 .prcm_reg_id = 1,
287 .module_bit = OMAP3430_EN_GPT5_SHIFT,
288 .module_offs = OMAP3430_PER_MOD,
289 .idlest_reg_id = 1,
290 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
291 },
4bf90f65 292 },
5c3e4ec4 293 .dev_attr = &capability_dsp_dev_attr,
844a3b63 294 .class = &omap3xxx_timer_hwmod_class,
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295};
296
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297/* timer6 */
298static struct omap_hwmod omap3xxx_timer6_hwmod = {
299 .name = "timer6",
300 .mpu_irqs = omap2_timer6_mpu_irqs,
301 .main_clk = "gpt6_fck",
302 .prcm = {
303 .omap2 = {
304 .prcm_reg_id = 1,
305 .module_bit = OMAP3430_EN_GPT6_SHIFT,
306 .module_offs = OMAP3430_PER_MOD,
307 .idlest_reg_id = 1,
308 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
309 },
310 },
5c3e4ec4 311 .dev_attr = &capability_dsp_dev_attr,
844a3b63 312 .class = &omap3xxx_timer_hwmod_class,
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313};
314
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315/* timer7 */
316static struct omap_hwmod omap3xxx_timer7_hwmod = {
317 .name = "timer7",
318 .mpu_irqs = omap2_timer7_mpu_irqs,
319 .main_clk = "gpt7_fck",
320 .prcm = {
4fe20e97 321 .omap2 = {
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322 .prcm_reg_id = 1,
323 .module_bit = OMAP3430_EN_GPT7_SHIFT,
324 .module_offs = OMAP3430_PER_MOD,
325 .idlest_reg_id = 1,
326 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
327 },
4fe20e97 328 },
5c3e4ec4 329 .dev_attr = &capability_dsp_dev_attr,
844a3b63 330 .class = &omap3xxx_timer_hwmod_class,
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331};
332
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333/* timer8 */
334static struct omap_hwmod omap3xxx_timer8_hwmod = {
335 .name = "timer8",
336 .mpu_irqs = omap2_timer8_mpu_irqs,
337 .main_clk = "gpt8_fck",
338 .prcm = {
4fe20e97 339 .omap2 = {
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340 .prcm_reg_id = 1,
341 .module_bit = OMAP3430_EN_GPT8_SHIFT,
342 .module_offs = OMAP3430_PER_MOD,
343 .idlest_reg_id = 1,
344 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
345 },
4fe20e97 346 },
5c3e4ec4 347 .dev_attr = &capability_dsp_pwm_dev_attr,
844a3b63 348 .class = &omap3xxx_timer_hwmod_class,
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349};
350
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351/* timer9 */
352static struct omap_hwmod omap3xxx_timer9_hwmod = {
353 .name = "timer9",
354 .mpu_irqs = omap2_timer9_mpu_irqs,
355 .main_clk = "gpt9_fck",
356 .prcm = {
357 .omap2 = {
358 .prcm_reg_id = 1,
359 .module_bit = OMAP3430_EN_GPT9_SHIFT,
360 .module_offs = OMAP3430_PER_MOD,
361 .idlest_reg_id = 1,
362 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
363 },
4fe20e97 364 },
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365 .dev_attr = &capability_pwm_dev_attr,
366 .class = &omap3xxx_timer_hwmod_class,
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367};
368
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369/* timer10 */
370static struct omap_hwmod omap3xxx_timer10_hwmod = {
371 .name = "timer10",
372 .mpu_irqs = omap2_timer10_mpu_irqs,
373 .main_clk = "gpt10_fck",
374 .prcm = {
4fe20e97 375 .omap2 = {
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376 .prcm_reg_id = 1,
377 .module_bit = OMAP3430_EN_GPT10_SHIFT,
378 .module_offs = CORE_MOD,
379 .idlest_reg_id = 1,
380 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
381 },
4fe20e97 382 },
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383 .dev_attr = &capability_pwm_dev_attr,
384 .class = &omap3xxx_timer_1ms_hwmod_class,
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385};
386
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387/* timer11 */
388static struct omap_hwmod omap3xxx_timer11_hwmod = {
389 .name = "timer11",
390 .mpu_irqs = omap2_timer11_mpu_irqs,
391 .main_clk = "gpt11_fck",
392 .prcm = {
393 .omap2 = {
394 .prcm_reg_id = 1,
395 .module_bit = OMAP3430_EN_GPT11_SHIFT,
396 .module_offs = CORE_MOD,
397 .idlest_reg_id = 1,
398 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
399 },
400 },
401 .dev_attr = &capability_pwm_dev_attr,
402 .class = &omap3xxx_timer_hwmod_class,
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403};
404
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405/* timer12 */
406static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
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407 { .irq = 95 + OMAP_INTC_START, },
408 { .irq = -1 },
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409};
410
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411static struct omap_hwmod omap3xxx_timer12_hwmod = {
412 .name = "timer12",
413 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
414 .main_clk = "gpt12_fck",
415 .prcm = {
416 .omap2 = {
417 .prcm_reg_id = 1,
418 .module_bit = OMAP3430_EN_GPT12_SHIFT,
419 .module_offs = WKUP_MOD,
420 .idlest_reg_id = 1,
421 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
422 },
d3442726 423 },
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424 .dev_attr = &capability_secure_dev_attr,
425 .class = &omap3xxx_timer_hwmod_class,
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426};
427
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428/*
429 * 'wd_timer' class
430 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
431 * overflow condition
432 */
433
434static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
435 .rev_offs = 0x0000,
436 .sysc_offs = 0x0010,
437 .syss_offs = 0x0014,
438 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
439 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
440 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
441 SYSS_HAS_RESET_STATUS),
442 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
443 .sysc_fields = &omap_hwmod_sysc_type1,
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444};
445
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446/* I2C common */
447static struct omap_hwmod_class_sysconfig i2c_sysc = {
448 .rev_offs = 0x00,
449 .sysc_offs = 0x20,
450 .syss_offs = 0x10,
451 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
452 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
453 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
454 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
455 .clockact = CLOCKACT_TEST_ICLK,
456 .sysc_fields = &omap_hwmod_sysc_type1,
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457};
458
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459static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
460 .name = "wd_timer",
461 .sysc = &omap3xxx_wd_timer_sysc,
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462 .pre_shutdown = &omap2_wd_timer_disable,
463 .reset = &omap2_wd_timer_reset,
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464};
465
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466static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
467 .name = "wd_timer2",
468 .class = &omap3xxx_wd_timer_hwmod_class,
469 .main_clk = "wdt2_fck",
470 .prcm = {
471 .omap2 = {
472 .prcm_reg_id = 1,
473 .module_bit = OMAP3430_EN_WDT2_SHIFT,
474 .module_offs = WKUP_MOD,
475 .idlest_reg_id = 1,
476 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
477 },
478 },
479 /*
480 * XXX: Use software supervised mode, HW supervised smartidle seems to
481 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
482 */
483 .flags = HWMOD_SWSUP_SIDLE,
484};
870ea2b8 485
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486/* UART1 */
487static struct omap_hwmod omap3xxx_uart1_hwmod = {
488 .name = "uart1",
489 .mpu_irqs = omap2_uart1_mpu_irqs,
490 .sdma_reqs = omap2_uart1_sdma_reqs,
491 .main_clk = "uart1_fck",
492 .prcm = {
493 .omap2 = {
494 .module_offs = CORE_MOD,
495 .prcm_reg_id = 1,
496 .module_bit = OMAP3430_EN_UART1_SHIFT,
497 .idlest_reg_id = 1,
498 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
499 },
870ea2b8 500 },
844a3b63 501 .class = &omap2_uart_class,
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502};
503
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504/* UART2 */
505static struct omap_hwmod omap3xxx_uart2_hwmod = {
506 .name = "uart2",
507 .mpu_irqs = omap2_uart2_mpu_irqs,
508 .sdma_reqs = omap2_uart2_sdma_reqs,
509 .main_clk = "uart2_fck",
510 .prcm = {
511 .omap2 = {
512 .module_offs = CORE_MOD,
513 .prcm_reg_id = 1,
514 .module_bit = OMAP3430_EN_UART2_SHIFT,
515 .idlest_reg_id = 1,
516 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
517 },
518 },
519 .class = &omap2_uart_class,
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520};
521
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522/* UART3 */
523static struct omap_hwmod omap3xxx_uart3_hwmod = {
524 .name = "uart3",
525 .mpu_irqs = omap2_uart3_mpu_irqs,
526 .sdma_reqs = omap2_uart3_sdma_reqs,
527 .main_clk = "uart3_fck",
528 .prcm = {
529 .omap2 = {
530 .module_offs = OMAP3430_PER_MOD,
531 .prcm_reg_id = 1,
532 .module_bit = OMAP3430_EN_UART3_SHIFT,
533 .idlest_reg_id = 1,
534 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
535 },
273ff8c3 536 },
844a3b63 537 .class = &omap2_uart_class,
273ff8c3
HH
538};
539
844a3b63
PW
540/* UART4 */
541static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
7d7e1eba
TL
542 { .irq = 80 + OMAP_INTC_START, },
543 { .irq = -1 },
273ff8c3
HH
544};
545
844a3b63
PW
546static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
547 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
548 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
549 { .dma_req = -1 }
7359154e
PW
550};
551
844a3b63
PW
552static struct omap_hwmod omap36xx_uart4_hwmod = {
553 .name = "uart4",
554 .mpu_irqs = uart4_mpu_irqs,
555 .sdma_reqs = uart4_sdma_reqs,
556 .main_clk = "uart4_fck",
557 .prcm = {
558 .omap2 = {
559 .module_offs = OMAP3430_PER_MOD,
560 .prcm_reg_id = 1,
561 .module_bit = OMAP3630_EN_UART4_SHIFT,
562 .idlest_reg_id = 1,
563 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
564 },
565 },
566 .class = &omap2_uart_class,
7359154e
PW
567};
568
844a3b63 569static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
7d7e1eba
TL
570 { .irq = 84 + OMAP_INTC_START, },
571 { .irq = -1 },
43085705
PW
572};
573
844a3b63
PW
574static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
575 { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
576 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
bf765237 577 { .dma_req = -1 }
7359154e
PW
578};
579
82ee620d
PW
580/*
581 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
582 * uart2_fck being enabled. So we add uart1_fck as an optional clock,
583 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really
584 * should not be needed. The functional clock structure of the AM35xx
585 * UART4 is extremely unclear and opaque; it is unclear what the role
586 * of uart1/2_fck is for the UART4. Any clarification from either
587 * empirical testing or the AM3505/3517 hardware designers would be
588 * most welcome.
589 */
590static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
591 { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
592};
593
844a3b63
PW
594static struct omap_hwmod am35xx_uart4_hwmod = {
595 .name = "uart4",
596 .mpu_irqs = am35xx_uart4_mpu_irqs,
597 .sdma_reqs = am35xx_uart4_sdma_reqs,
598 .main_clk = "uart4_fck",
599 .prcm = {
600 .omap2 = {
601 .module_offs = CORE_MOD,
602 .prcm_reg_id = 1,
bf765237 603 .module_bit = AM35XX_EN_UART4_SHIFT,
844a3b63 604 .idlest_reg_id = 1,
bf765237 605 .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
844a3b63
PW
606 },
607 },
82ee620d
PW
608 .opt_clks = am35xx_uart4_opt_clks,
609 .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks),
610 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
844a3b63
PW
611 .class = &omap2_uart_class,
612};
613
614static struct omap_hwmod_class i2c_class = {
615 .name = "i2c",
616 .sysc = &i2c_sysc,
617 .rev = OMAP_I2C_IP_VERSION_1,
618 .reset = &omap_i2c_reset,
619};
620
621static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
622 { .name = "dispc", .dma_req = 5 },
623 { .name = "dsi1", .dma_req = 74 },
624 { .dma_req = -1 }
43085705
PW
625};
626
844a3b63
PW
627/* dss */
628static struct omap_hwmod_opt_clk dss_opt_clks[] = {
629 /*
630 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
631 * driver does not use these clocks.
632 */
633 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
634 { .role = "tv_clk", .clk = "dss_tv_fck" },
635 /* required only on OMAP3430 */
636 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
7359154e
PW
637};
638
844a3b63
PW
639static struct omap_hwmod omap3430es1_dss_core_hwmod = {
640 .name = "dss_core",
641 .class = &omap2_dss_hwmod_class,
642 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
643 .sdma_reqs = omap3xxx_dss_sdma_chs,
644 .prcm = {
645 .omap2 = {
646 .prcm_reg_id = 1,
647 .module_bit = OMAP3430_EN_DSS1_SHIFT,
648 .module_offs = OMAP3430_DSS_MOD,
649 .idlest_reg_id = 1,
650 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
651 },
652 },
653 .opt_clks = dss_opt_clks,
654 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
655 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
656};
540064bf 657
844a3b63
PW
658static struct omap_hwmod omap3xxx_dss_core_hwmod = {
659 .name = "dss_core",
660 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
661 .class = &omap2_dss_hwmod_class,
662 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
663 .sdma_reqs = omap3xxx_dss_sdma_chs,
664 .prcm = {
665 .omap2 = {
666 .prcm_reg_id = 1,
667 .module_bit = OMAP3430_EN_DSS1_SHIFT,
668 .module_offs = OMAP3430_DSS_MOD,
669 .idlest_reg_id = 1,
670 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
671 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
672 },
673 },
674 .opt_clks = dss_opt_clks,
675 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
540064bf
KH
676};
677
540064bf 678/*
844a3b63
PW
679 * 'dispc' class
680 * display controller
540064bf
KH
681 */
682
844a3b63 683static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
ce722d26
TG
684 .rev_offs = 0x0000,
685 .sysc_offs = 0x0010,
686 .syss_offs = 0x0014,
844a3b63
PW
687 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
688 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
689 SYSC_HAS_ENAWAKEUP),
690 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
691 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
ce722d26 692 .sysc_fields = &omap_hwmod_sysc_type1,
6b667f88
VC
693};
694
844a3b63
PW
695static struct omap_hwmod_class omap3_dispc_hwmod_class = {
696 .name = "dispc",
697 .sysc = &omap3_dispc_sysc,
6b667f88
VC
698};
699
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PW
700static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
701 .name = "dss_dispc",
702 .class = &omap3_dispc_hwmod_class,
703 .mpu_irqs = omap2_dispc_irqs,
704 .main_clk = "dss1_alwon_fck",
705 .prcm = {
706 .omap2 = {
707 .prcm_reg_id = 1,
708 .module_bit = OMAP3430_EN_DSS1_SHIFT,
709 .module_offs = OMAP3430_DSS_MOD,
710 },
711 },
712 .flags = HWMOD_NO_IDLEST,
713 .dev_attr = &omap2_3_dss_dispc_dev_attr
6b667f88
VC
714};
715
844a3b63
PW
716/*
717 * 'dsi' class
718 * display serial interface controller
719 */
4fe20e97 720
844a3b63
PW
721static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
722 .name = "dsi",
c345c8b0
TKD
723};
724
844a3b63 725static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
7d7e1eba
TL
726 { .irq = 25 + OMAP_INTC_START, },
727 { .irq = -1 },
c345c8b0
TKD
728};
729
844a3b63
PW
730/* dss_dsi1 */
731static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
732 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
c345c8b0
TKD
733};
734
844a3b63
PW
735static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
736 .name = "dss_dsi1",
737 .class = &omap3xxx_dsi_hwmod_class,
738 .mpu_irqs = omap3xxx_dsi1_irqs,
739 .main_clk = "dss1_alwon_fck",
740 .prcm = {
741 .omap2 = {
742 .prcm_reg_id = 1,
743 .module_bit = OMAP3430_EN_DSS1_SHIFT,
744 .module_offs = OMAP3430_DSS_MOD,
745 },
ce722d26 746 },
844a3b63
PW
747 .opt_clks = dss_dsi1_opt_clks,
748 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
749 .flags = HWMOD_NO_IDLEST,
6b667f88
VC
750};
751
844a3b63
PW
752static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
753 { .role = "ick", .clk = "dss_ick" },
ce722d26
TG
754};
755
844a3b63
PW
756static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
757 .name = "dss_rfbi",
758 .class = &omap2_rfbi_hwmod_class,
759 .main_clk = "dss1_alwon_fck",
6b667f88
VC
760 .prcm = {
761 .omap2 = {
762 .prcm_reg_id = 1,
844a3b63
PW
763 .module_bit = OMAP3430_EN_DSS1_SHIFT,
764 .module_offs = OMAP3430_DSS_MOD,
6b667f88
VC
765 },
766 },
844a3b63
PW
767 .opt_clks = dss_rfbi_opt_clks,
768 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
769 .flags = HWMOD_NO_IDLEST,
046465b7
KH
770};
771
844a3b63
PW
772static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
773 /* required only on OMAP3430 */
774 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
046465b7
KH
775};
776
844a3b63
PW
777static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
778 .name = "dss_venc",
779 .class = &omap2_venc_hwmod_class,
780 .main_clk = "dss_tv_fck",
046465b7
KH
781 .prcm = {
782 .omap2 = {
046465b7 783 .prcm_reg_id = 1,
844a3b63
PW
784 .module_bit = OMAP3430_EN_DSS1_SHIFT,
785 .module_offs = OMAP3430_DSS_MOD,
046465b7
KH
786 },
787 },
844a3b63
PW
788 .opt_clks = dss_venc_opt_clks,
789 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
790 .flags = HWMOD_NO_IDLEST,
046465b7
KH
791};
792
844a3b63
PW
793/* I2C1 */
794static struct omap_i2c_dev_attr i2c1_dev_attr = {
795 .fifo_depth = 8, /* bytes */
796 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
797 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
798 OMAP_I2C_FLAG_BUS_SHIFT_2,
046465b7
KH
799};
800
844a3b63
PW
801static struct omap_hwmod omap3xxx_i2c1_hwmod = {
802 .name = "i2c1",
803 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
804 .mpu_irqs = omap2_i2c1_mpu_irqs,
805 .sdma_reqs = omap2_i2c1_sdma_reqs,
806 .main_clk = "i2c1_fck",
046465b7
KH
807 .prcm = {
808 .omap2 = {
844a3b63 809 .module_offs = CORE_MOD,
046465b7 810 .prcm_reg_id = 1,
844a3b63 811 .module_bit = OMAP3430_EN_I2C1_SHIFT,
046465b7 812 .idlest_reg_id = 1,
844a3b63 813 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
046465b7
KH
814 },
815 },
844a3b63
PW
816 .class = &i2c_class,
817 .dev_attr = &i2c1_dev_attr,
046465b7
KH
818};
819
844a3b63
PW
820/* I2C2 */
821static struct omap_i2c_dev_attr i2c2_dev_attr = {
822 .fifo_depth = 8, /* bytes */
823 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
824 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
825 OMAP_I2C_FLAG_BUS_SHIFT_2,
046465b7
KH
826};
827
844a3b63
PW
828static struct omap_hwmod omap3xxx_i2c2_hwmod = {
829 .name = "i2c2",
830 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
831 .mpu_irqs = omap2_i2c2_mpu_irqs,
832 .sdma_reqs = omap2_i2c2_sdma_reqs,
833 .main_clk = "i2c2_fck",
046465b7
KH
834 .prcm = {
835 .omap2 = {
844a3b63 836 .module_offs = CORE_MOD,
046465b7 837 .prcm_reg_id = 1,
844a3b63 838 .module_bit = OMAP3430_EN_I2C2_SHIFT,
046465b7 839 .idlest_reg_id = 1,
844a3b63 840 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
046465b7
KH
841 },
842 },
844a3b63
PW
843 .class = &i2c_class,
844 .dev_attr = &i2c2_dev_attr,
046465b7
KH
845};
846
844a3b63
PW
847/* I2C3 */
848static struct omap_i2c_dev_attr i2c3_dev_attr = {
849 .fifo_depth = 64, /* bytes */
850 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
851 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
852 OMAP_I2C_FLAG_BUS_SHIFT_2,
853};
046465b7 854
844a3b63 855static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
7d7e1eba
TL
856 { .irq = 61 + OMAP_INTC_START, },
857 { .irq = -1 },
046465b7
KH
858};
859
844a3b63
PW
860static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
861 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
862 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
863 { .dma_req = -1 }
046465b7
KH
864};
865
844a3b63
PW
866static struct omap_hwmod omap3xxx_i2c3_hwmod = {
867 .name = "i2c3",
868 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
869 .mpu_irqs = i2c3_mpu_irqs,
870 .sdma_reqs = i2c3_sdma_reqs,
871 .main_clk = "i2c3_fck",
046465b7
KH
872 .prcm = {
873 .omap2 = {
844a3b63 874 .module_offs = CORE_MOD,
046465b7 875 .prcm_reg_id = 1,
844a3b63 876 .module_bit = OMAP3430_EN_I2C3_SHIFT,
046465b7 877 .idlest_reg_id = 1,
844a3b63 878 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
046465b7
KH
879 },
880 },
844a3b63
PW
881 .class = &i2c_class,
882 .dev_attr = &i2c3_dev_attr,
4fe20e97
RN
883};
884
844a3b63
PW
885/*
886 * 'gpio' class
887 * general purpose io module
888 */
4fe20e97 889
844a3b63
PW
890static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
891 .rev_offs = 0x0000,
892 .sysc_offs = 0x0010,
893 .syss_offs = 0x0014,
894 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
895 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
896 SYSS_HAS_RESET_STATUS),
897 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
898 .sysc_fields = &omap_hwmod_sysc_type1,
4fe20e97
RN
899};
900
844a3b63
PW
901static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
902 .name = "gpio",
903 .sysc = &omap3xxx_gpio_sysc,
904 .rev = 1,
4fe20e97
RN
905};
906
844a3b63
PW
907/* gpio_dev_attr */
908static struct omap_gpio_dev_attr gpio_dev_attr = {
909 .bank_width = 32,
910 .dbck_flag = true,
911};
912
913/* gpio1 */
914static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
915 { .role = "dbclk", .clk = "gpio1_dbck", },
916};
917
918static struct omap_hwmod omap3xxx_gpio1_hwmod = {
919 .name = "gpio1",
920 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
921 .mpu_irqs = omap2_gpio1_irqs,
922 .main_clk = "gpio1_ick",
923 .opt_clks = gpio1_opt_clks,
924 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
4fe20e97
RN
925 .prcm = {
926 .omap2 = {
4fe20e97 927 .prcm_reg_id = 1,
844a3b63
PW
928 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
929 .module_offs = WKUP_MOD,
4fe20e97 930 .idlest_reg_id = 1,
844a3b63 931 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
4fe20e97
RN
932 },
933 },
844a3b63
PW
934 .class = &omap3xxx_gpio_hwmod_class,
935 .dev_attr = &gpio_dev_attr,
4fe20e97
RN
936};
937
844a3b63
PW
938/* gpio2 */
939static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
940 { .role = "dbclk", .clk = "gpio2_dbck", },
4fe20e97
RN
941};
942
844a3b63
PW
943static struct omap_hwmod omap3xxx_gpio2_hwmod = {
944 .name = "gpio2",
945 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
946 .mpu_irqs = omap2_gpio2_irqs,
947 .main_clk = "gpio2_ick",
948 .opt_clks = gpio2_opt_clks,
949 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
4fe20e97
RN
950 .prcm = {
951 .omap2 = {
4fe20e97 952 .prcm_reg_id = 1,
844a3b63 953 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
ce722d26 954 .module_offs = OMAP3430_PER_MOD,
4fe20e97 955 .idlest_reg_id = 1,
844a3b63 956 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
4fe20e97
RN
957 },
958 },
844a3b63
PW
959 .class = &omap3xxx_gpio_hwmod_class,
960 .dev_attr = &gpio_dev_attr,
4fe20e97
RN
961};
962
844a3b63
PW
963/* gpio3 */
964static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
965 { .role = "dbclk", .clk = "gpio3_dbck", },
4fe20e97
RN
966};
967
844a3b63
PW
968static struct omap_hwmod omap3xxx_gpio3_hwmod = {
969 .name = "gpio3",
970 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
971 .mpu_irqs = omap2_gpio3_irqs,
972 .main_clk = "gpio3_ick",
973 .opt_clks = gpio3_opt_clks,
974 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
4fe20e97
RN
975 .prcm = {
976 .omap2 = {
4fe20e97 977 .prcm_reg_id = 1,
844a3b63 978 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
ce722d26 979 .module_offs = OMAP3430_PER_MOD,
4fe20e97 980 .idlest_reg_id = 1,
844a3b63 981 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
4fe20e97
RN
982 },
983 },
844a3b63
PW
984 .class = &omap3xxx_gpio_hwmod_class,
985 .dev_attr = &gpio_dev_attr,
70034d38
VC
986};
987
844a3b63
PW
988/* gpio4 */
989static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
990 { .role = "dbclk", .clk = "gpio4_dbck", },
70034d38
VC
991};
992
844a3b63
PW
993static struct omap_hwmod omap3xxx_gpio4_hwmod = {
994 .name = "gpio4",
995 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
996 .mpu_irqs = omap2_gpio4_irqs,
997 .main_clk = "gpio4_ick",
998 .opt_clks = gpio4_opt_clks,
999 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
ce722d26
TG
1000 .prcm = {
1001 .omap2 = {
1002 .prcm_reg_id = 1,
844a3b63 1003 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
ce722d26
TG
1004 .module_offs = OMAP3430_PER_MOD,
1005 .idlest_reg_id = 1,
844a3b63 1006 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
ce722d26 1007 },
70034d38 1008 },
844a3b63
PW
1009 .class = &omap3xxx_gpio_hwmod_class,
1010 .dev_attr = &gpio_dev_attr,
70034d38
VC
1011};
1012
844a3b63
PW
1013/* gpio5 */
1014static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
7d7e1eba
TL
1015 { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
1016 { .irq = -1 },
844a3b63 1017};
70034d38 1018
844a3b63
PW
1019static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1020 { .role = "dbclk", .clk = "gpio5_dbck", },
70034d38
VC
1021};
1022
844a3b63
PW
1023static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1024 .name = "gpio5",
1025 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1026 .mpu_irqs = omap3xxx_gpio5_irqs,
1027 .main_clk = "gpio5_ick",
1028 .opt_clks = gpio5_opt_clks,
1029 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
ce722d26
TG
1030 .prcm = {
1031 .omap2 = {
1032 .prcm_reg_id = 1,
844a3b63
PW
1033 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1034 .module_offs = OMAP3430_PER_MOD,
ce722d26 1035 .idlest_reg_id = 1,
844a3b63 1036 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
ce722d26 1037 },
70034d38 1038 },
844a3b63
PW
1039 .class = &omap3xxx_gpio_hwmod_class,
1040 .dev_attr = &gpio_dev_attr,
70034d38
VC
1041};
1042
844a3b63
PW
1043/* gpio6 */
1044static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
7d7e1eba
TL
1045 { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
1046 { .irq = -1 },
844a3b63 1047};
70034d38 1048
844a3b63
PW
1049static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1050 { .role = "dbclk", .clk = "gpio6_dbck", },
70034d38
VC
1051};
1052
844a3b63
PW
1053static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1054 .name = "gpio6",
1055 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1056 .mpu_irqs = omap3xxx_gpio6_irqs,
1057 .main_clk = "gpio6_ick",
1058 .opt_clks = gpio6_opt_clks,
1059 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
ce722d26
TG
1060 .prcm = {
1061 .omap2 = {
1062 .prcm_reg_id = 1,
844a3b63
PW
1063 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1064 .module_offs = OMAP3430_PER_MOD,
ce722d26 1065 .idlest_reg_id = 1,
844a3b63 1066 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
ce722d26
TG
1067 },
1068 },
844a3b63
PW
1069 .class = &omap3xxx_gpio_hwmod_class,
1070 .dev_attr = &gpio_dev_attr,
ce722d26
TG
1071};
1072
844a3b63
PW
1073/* dma attributes */
1074static struct omap_dma_dev_attr dma_dev_attr = {
1075 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1076 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1077 .lch_count = 32,
ce722d26
TG
1078};
1079
844a3b63
PW
1080static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1081 .rev_offs = 0x0000,
1082 .sysc_offs = 0x002c,
1083 .syss_offs = 0x0028,
1084 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1085 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1086 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1087 SYSS_HAS_RESET_STATUS),
1088 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1089 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1090 .sysc_fields = &omap_hwmod_sysc_type1,
70034d38
VC
1091};
1092
844a3b63
PW
1093static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1094 .name = "dma",
1095 .sysc = &omap3xxx_dma_sysc,
70034d38
VC
1096};
1097
844a3b63
PW
1098/* dma_system */
1099static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1100 .name = "dma",
1101 .class = &omap3xxx_dma_hwmod_class,
1102 .mpu_irqs = omap2_dma_system_irqs,
1103 .main_clk = "core_l3_ick",
1104 .prcm = {
ce722d26 1105 .omap2 = {
844a3b63
PW
1106 .module_offs = CORE_MOD,
1107 .prcm_reg_id = 1,
1108 .module_bit = OMAP3430_ST_SDMA_SHIFT,
1109 .idlest_reg_id = 1,
1110 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
ce722d26
TG
1111 },
1112 },
844a3b63
PW
1113 .dev_attr = &dma_dev_attr,
1114 .flags = HWMOD_NO_IDLEST,
70034d38
VC
1115};
1116
844a3b63
PW
1117/*
1118 * 'mcbsp' class
1119 * multi channel buffered serial port controller
1120 */
1121
1122static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1123 .sysc_offs = 0x008c,
1124 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1125 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1126 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1127 .sysc_fields = &omap_hwmod_sysc_type1,
1128 .clockact = 0x2,
70034d38
VC
1129};
1130
844a3b63
PW
1131static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1132 .name = "mcbsp",
1133 .sysc = &omap3xxx_mcbsp_sysc,
1134 .rev = MCBSP_CONFIG_TYPE3,
70034d38
VC
1135};
1136
7039154b
PU
1137/* McBSP functional clock mapping */
1138static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1139 { .role = "pad_fck", .clk = "mcbsp_clks" },
1140 { .role = "prcm_fck", .clk = "core_96m_fck" },
1141};
1142
1143static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1144 { .role = "pad_fck", .clk = "mcbsp_clks" },
1145 { .role = "prcm_fck", .clk = "per_96m_fck" },
1146};
1147
844a3b63
PW
1148/* mcbsp1 */
1149static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
7d7e1eba
TL
1150 { .name = "common", .irq = 16 + OMAP_INTC_START, },
1151 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
1152 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
1153 { .irq = -1 },
844a3b63 1154};
6b667f88 1155
844a3b63
PW
1156static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1157 .name = "mcbsp1",
1158 .class = &omap3xxx_mcbsp_hwmod_class,
1159 .mpu_irqs = omap3xxx_mcbsp1_irqs,
1160 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
1161 .main_clk = "mcbsp1_fck",
1162 .prcm = {
1163 .omap2 = {
1164 .prcm_reg_id = 1,
1165 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1166 .module_offs = CORE_MOD,
1167 .idlest_reg_id = 1,
1168 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1169 },
1170 },
7039154b
PU
1171 .opt_clks = mcbsp15_opt_clks,
1172 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
70034d38
VC
1173};
1174
844a3b63
PW
1175/* mcbsp2 */
1176static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
7d7e1eba
TL
1177 { .name = "common", .irq = 17 + OMAP_INTC_START, },
1178 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
1179 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
1180 { .irq = -1 },
70034d38
VC
1181};
1182
844a3b63
PW
1183static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1184 .sidetone = "mcbsp2_sidetone",
70034d38
VC
1185};
1186
844a3b63
PW
1187static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1188 .name = "mcbsp2",
1189 .class = &omap3xxx_mcbsp_hwmod_class,
1190 .mpu_irqs = omap3xxx_mcbsp2_irqs,
1191 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
1192 .main_clk = "mcbsp2_fck",
70034d38
VC
1193 .prcm = {
1194 .omap2 = {
1195 .prcm_reg_id = 1,
844a3b63
PW
1196 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1197 .module_offs = OMAP3430_PER_MOD,
70034d38 1198 .idlest_reg_id = 1,
844a3b63 1199 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
70034d38
VC
1200 },
1201 },
7039154b
PU
1202 .opt_clks = mcbsp234_opt_clks,
1203 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
844a3b63 1204 .dev_attr = &omap34xx_mcbsp2_dev_attr,
70034d38
VC
1205};
1206
844a3b63
PW
1207/* mcbsp3 */
1208static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
7d7e1eba
TL
1209 { .name = "common", .irq = 22 + OMAP_INTC_START, },
1210 { .name = "tx", .irq = 89 + OMAP_INTC_START, },
1211 { .name = "rx", .irq = 90 + OMAP_INTC_START, },
1212 { .irq = -1 },
844a3b63
PW
1213};
1214
1215static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1216 .sidetone = "mcbsp3_sidetone",
1217};
1218
1219static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1220 .name = "mcbsp3",
1221 .class = &omap3xxx_mcbsp_hwmod_class,
1222 .mpu_irqs = omap3xxx_mcbsp3_irqs,
1223 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
1224 .main_clk = "mcbsp3_fck",
70034d38
VC
1225 .prcm = {
1226 .omap2 = {
1227 .prcm_reg_id = 1,
844a3b63
PW
1228 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1229 .module_offs = OMAP3430_PER_MOD,
70034d38 1230 .idlest_reg_id = 1,
844a3b63 1231 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
70034d38
VC
1232 },
1233 },
7039154b
PU
1234 .opt_clks = mcbsp234_opt_clks,
1235 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
844a3b63 1236 .dev_attr = &omap34xx_mcbsp3_dev_attr,
70034d38
VC
1237};
1238
844a3b63
PW
1239/* mcbsp4 */
1240static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
7d7e1eba
TL
1241 { .name = "common", .irq = 23 + OMAP_INTC_START, },
1242 { .name = "tx", .irq = 54 + OMAP_INTC_START, },
1243 { .name = "rx", .irq = 55 + OMAP_INTC_START, },
1244 { .irq = -1 },
844a3b63
PW
1245};
1246
1247static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1248 { .name = "rx", .dma_req = 20 },
1249 { .name = "tx", .dma_req = 19 },
1250 { .dma_req = -1 }
1251};
1252
1253static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1254 .name = "mcbsp4",
1255 .class = &omap3xxx_mcbsp_hwmod_class,
1256 .mpu_irqs = omap3xxx_mcbsp4_irqs,
1257 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
1258 .main_clk = "mcbsp4_fck",
70034d38
VC
1259 .prcm = {
1260 .omap2 = {
1261 .prcm_reg_id = 1,
844a3b63
PW
1262 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1263 .module_offs = OMAP3430_PER_MOD,
046465b7 1264 .idlest_reg_id = 1,
844a3b63 1265 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
046465b7
KH
1266 },
1267 },
7039154b
PU
1268 .opt_clks = mcbsp234_opt_clks,
1269 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
046465b7
KH
1270};
1271
844a3b63
PW
1272/* mcbsp5 */
1273static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
7d7e1eba
TL
1274 { .name = "common", .irq = 27 + OMAP_INTC_START, },
1275 { .name = "tx", .irq = 81 + OMAP_INTC_START, },
1276 { .name = "rx", .irq = 82 + OMAP_INTC_START, },
1277 { .irq = -1 },
844a3b63
PW
1278};
1279
1280static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1281 { .name = "rx", .dma_req = 22 },
1282 { .name = "tx", .dma_req = 21 },
1283 { .dma_req = -1 }
1284};
1285
1286static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1287 .name = "mcbsp5",
1288 .class = &omap3xxx_mcbsp_hwmod_class,
1289 .mpu_irqs = omap3xxx_mcbsp5_irqs,
1290 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
1291 .main_clk = "mcbsp5_fck",
046465b7
KH
1292 .prcm = {
1293 .omap2 = {
046465b7 1294 .prcm_reg_id = 1,
844a3b63
PW
1295 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1296 .module_offs = CORE_MOD,
70034d38 1297 .idlest_reg_id = 1,
844a3b63 1298 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
70034d38
VC
1299 },
1300 },
7039154b
PU
1301 .opt_clks = mcbsp15_opt_clks,
1302 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
70034d38
VC
1303};
1304
844a3b63
PW
1305/* 'mcbsp sidetone' class */
1306static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1307 .sysc_offs = 0x0010,
1308 .sysc_flags = SYSC_HAS_AUTOIDLE,
1309 .sysc_fields = &omap_hwmod_sysc_type1,
1310};
046465b7 1311
844a3b63
PW
1312static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1313 .name = "mcbsp_sidetone",
1314 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
70034d38
VC
1315};
1316
844a3b63
PW
1317/* mcbsp2_sidetone */
1318static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
7d7e1eba
TL
1319 { .name = "irq", .irq = 4 + OMAP_INTC_START, },
1320 { .irq = -1 },
70034d38
VC
1321};
1322
844a3b63
PW
1323static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1324 .name = "mcbsp2_sidetone",
1325 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1326 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
1327 .main_clk = "mcbsp2_fck",
046465b7
KH
1328 .prcm = {
1329 .omap2 = {
046465b7 1330 .prcm_reg_id = 1,
844a3b63
PW
1331 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1332 .module_offs = OMAP3430_PER_MOD,
046465b7 1333 .idlest_reg_id = 1,
844a3b63 1334 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
046465b7
KH
1335 },
1336 },
4bf90f65
KM
1337};
1338
844a3b63
PW
1339/* mcbsp3_sidetone */
1340static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
7d7e1eba
TL
1341 { .name = "irq", .irq = 5 + OMAP_INTC_START, },
1342 { .irq = -1 },
4bf90f65
KM
1343};
1344
844a3b63
PW
1345static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1346 .name = "mcbsp3_sidetone",
1347 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1348 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
1349 .main_clk = "mcbsp3_fck",
0a78c5c5 1350 .prcm = {
4bf90f65 1351 .omap2 = {
4bf90f65 1352 .prcm_reg_id = 1,
844a3b63
PW
1353 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1354 .module_offs = OMAP3430_PER_MOD,
4bf90f65 1355 .idlest_reg_id = 1,
844a3b63 1356 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
4bf90f65
KM
1357 },
1358 },
4bf90f65
KM
1359};
1360
844a3b63
PW
1361/* SR common */
1362static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1363 .clkact_shift = 20,
1364};
4bf90f65 1365
844a3b63
PW
1366static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1367 .sysc_offs = 0x24,
1368 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1369 .clockact = CLOCKACT_TEST_ICLK,
1370 .sysc_fields = &omap34xx_sr_sysc_fields,
4fe20e97
RN
1371};
1372
844a3b63
PW
1373static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1374 .name = "smartreflex",
1375 .sysc = &omap34xx_sr_sysc,
1376 .rev = 1,
e04d9e1e
SG
1377};
1378
844a3b63
PW
1379static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1380 .sidle_shift = 24,
1381 .enwkup_shift = 26,
1382};
e04d9e1e 1383
844a3b63
PW
1384static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1385 .sysc_offs = 0x38,
1386 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1387 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1388 SYSC_NO_CACHE),
1389 .sysc_fields = &omap36xx_sr_sysc_fields,
1390};
1391
1392static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1393 .name = "smartreflex",
1394 .sysc = &omap36xx_sr_sysc,
1395 .rev = 2,
1396};
1397
1398/* SR1 */
1399static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1400 .sensor_voltdm_name = "mpu_iva",
1401};
1402
1403static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
7d7e1eba
TL
1404 { .irq = 18 + OMAP_INTC_START, },
1405 { .irq = -1 },
844a3b63
PW
1406};
1407
1408static struct omap_hwmod omap34xx_sr1_hwmod = {
1fcd3069 1409 .name = "smartreflex_mpu_iva",
844a3b63
PW
1410 .class = &omap34xx_smartreflex_hwmod_class,
1411 .main_clk = "sr1_fck",
1412 .prcm = {
e04d9e1e 1413 .omap2 = {
844a3b63
PW
1414 .prcm_reg_id = 1,
1415 .module_bit = OMAP3430_EN_SR1_SHIFT,
1416 .module_offs = WKUP_MOD,
1417 .idlest_reg_id = 1,
1418 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1419 },
e04d9e1e 1420 },
844a3b63
PW
1421 .dev_attr = &sr1_dev_attr,
1422 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1423 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
e04d9e1e
SG
1424};
1425
844a3b63 1426static struct omap_hwmod omap36xx_sr1_hwmod = {
1fcd3069 1427 .name = "smartreflex_mpu_iva",
844a3b63
PW
1428 .class = &omap36xx_smartreflex_hwmod_class,
1429 .main_clk = "sr1_fck",
1430 .prcm = {
e04d9e1e 1431 .omap2 = {
844a3b63
PW
1432 .prcm_reg_id = 1,
1433 .module_bit = OMAP3430_EN_SR1_SHIFT,
1434 .module_offs = WKUP_MOD,
1435 .idlest_reg_id = 1,
1436 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1437 },
e04d9e1e 1438 },
844a3b63
PW
1439 .dev_attr = &sr1_dev_attr,
1440 .mpu_irqs = omap3_smartreflex_mpu_irqs,
e04d9e1e
SG
1441};
1442
844a3b63
PW
1443/* SR2 */
1444static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1445 .sensor_voltdm_name = "core",
e04d9e1e
SG
1446};
1447
844a3b63 1448static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
7d7e1eba
TL
1449 { .irq = 19 + OMAP_INTC_START, },
1450 { .irq = -1 },
844a3b63
PW
1451};
1452
1453static struct omap_hwmod omap34xx_sr2_hwmod = {
1fcd3069 1454 .name = "smartreflex_core",
844a3b63
PW
1455 .class = &omap34xx_smartreflex_hwmod_class,
1456 .main_clk = "sr2_fck",
e04d9e1e
SG
1457 .prcm = {
1458 .omap2 = {
1459 .prcm_reg_id = 1,
844a3b63
PW
1460 .module_bit = OMAP3430_EN_SR2_SHIFT,
1461 .module_offs = WKUP_MOD,
e04d9e1e 1462 .idlest_reg_id = 1,
844a3b63 1463 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
e04d9e1e
SG
1464 },
1465 },
844a3b63
PW
1466 .dev_attr = &sr2_dev_attr,
1467 .mpu_irqs = omap3_smartreflex_core_irqs,
1468 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
e04d9e1e
SG
1469};
1470
844a3b63 1471static struct omap_hwmod omap36xx_sr2_hwmod = {
1fcd3069 1472 .name = "smartreflex_core",
844a3b63
PW
1473 .class = &omap36xx_smartreflex_hwmod_class,
1474 .main_clk = "sr2_fck",
e04d9e1e
SG
1475 .prcm = {
1476 .omap2 = {
1477 .prcm_reg_id = 1,
844a3b63
PW
1478 .module_bit = OMAP3430_EN_SR2_SHIFT,
1479 .module_offs = WKUP_MOD,
e04d9e1e 1480 .idlest_reg_id = 1,
844a3b63 1481 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
e04d9e1e
SG
1482 },
1483 },
844a3b63
PW
1484 .dev_attr = &sr2_dev_attr,
1485 .mpu_irqs = omap3_smartreflex_core_irqs,
e04d9e1e
SG
1486};
1487
1ac6d46e 1488/*
844a3b63
PW
1489 * 'mailbox' class
1490 * mailbox module allowing communication between the on-chip processors
1491 * using a queued mailbox-interrupt mechanism.
1ac6d46e
TV
1492 */
1493
844a3b63
PW
1494static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1495 .rev_offs = 0x000,
1496 .sysc_offs = 0x010,
1497 .syss_offs = 0x014,
1498 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1499 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1500 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1ac6d46e
TV
1501 .sysc_fields = &omap_hwmod_sysc_type1,
1502};
1503
844a3b63
PW
1504static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1505 .name = "mailbox",
1506 .sysc = &omap3xxx_mailbox_sysc,
1ac6d46e
TV
1507};
1508
844a3b63 1509static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
7d7e1eba
TL
1510 { .irq = 26 + OMAP_INTC_START, },
1511 { .irq = -1 },
e04d9e1e
SG
1512};
1513
844a3b63
PW
1514static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1515 .name = "mailbox",
1516 .class = &omap3xxx_mailbox_hwmod_class,
1517 .mpu_irqs = omap3xxx_mailbox_irqs,
1518 .main_clk = "mailboxes_ick",
e04d9e1e
SG
1519 .prcm = {
1520 .omap2 = {
1521 .prcm_reg_id = 1,
844a3b63
PW
1522 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1523 .module_offs = CORE_MOD,
1524 .idlest_reg_id = 1,
1525 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
e04d9e1e
SG
1526 },
1527 },
e04d9e1e
SG
1528};
1529
1530/*
844a3b63
PW
1531 * 'mcspi' class
1532 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1533 * bus
e04d9e1e
SG
1534 */
1535
844a3b63
PW
1536static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1537 .rev_offs = 0x0000,
1538 .sysc_offs = 0x0010,
1539 .syss_offs = 0x0014,
1540 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1541 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1542 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1543 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1544 .sysc_fields = &omap_hwmod_sysc_type1,
e04d9e1e
SG
1545};
1546
844a3b63
PW
1547static struct omap_hwmod_class omap34xx_mcspi_class = {
1548 .name = "mcspi",
1549 .sysc = &omap34xx_mcspi_sysc,
1550 .rev = OMAP3_MCSPI_REV,
affe360d 1551};
1552
844a3b63
PW
1553/* mcspi1 */
1554static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1555 .num_chipselect = 4,
e04d9e1e
SG
1556};
1557
844a3b63
PW
1558static struct omap_hwmod omap34xx_mcspi1 = {
1559 .name = "mcspi1",
1560 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1561 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1562 .main_clk = "mcspi1_fck",
1563 .prcm = {
e04d9e1e 1564 .omap2 = {
844a3b63
PW
1565 .module_offs = CORE_MOD,
1566 .prcm_reg_id = 1,
1567 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1568 .idlest_reg_id = 1,
1569 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1570 },
e04d9e1e 1571 },
844a3b63
PW
1572 .class = &omap34xx_mcspi_class,
1573 .dev_attr = &omap_mcspi1_dev_attr,
e04d9e1e
SG
1574};
1575
844a3b63
PW
1576/* mcspi2 */
1577static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1578 .num_chipselect = 2,
6c3d7e34
TV
1579};
1580
844a3b63
PW
1581static struct omap_hwmod omap34xx_mcspi2 = {
1582 .name = "mcspi2",
1583 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1584 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1585 .main_clk = "mcspi2_fck",
e04d9e1e
SG
1586 .prcm = {
1587 .omap2 = {
844a3b63 1588 .module_offs = CORE_MOD,
e04d9e1e 1589 .prcm_reg_id = 1,
844a3b63
PW
1590 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1591 .idlest_reg_id = 1,
1592 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
e04d9e1e
SG
1593 },
1594 },
844a3b63
PW
1595 .class = &omap34xx_mcspi_class,
1596 .dev_attr = &omap_mcspi2_dev_attr,
e04d9e1e
SG
1597};
1598
844a3b63
PW
1599/* mcspi3 */
1600static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
7d7e1eba
TL
1601 { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
1602 { .irq = -1 },
844a3b63
PW
1603};
1604
1605static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1606 { .name = "tx0", .dma_req = 15 },
1607 { .name = "rx0", .dma_req = 16 },
1608 { .name = "tx1", .dma_req = 23 },
1609 { .name = "rx1", .dma_req = 24 },
1610 { .dma_req = -1 }
e04d9e1e
SG
1611};
1612
844a3b63
PW
1613static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1614 .num_chipselect = 2,
6c3d7e34
TV
1615};
1616
844a3b63
PW
1617static struct omap_hwmod omap34xx_mcspi3 = {
1618 .name = "mcspi3",
1619 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
1620 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
1621 .main_clk = "mcspi3_fck",
e04d9e1e
SG
1622 .prcm = {
1623 .omap2 = {
844a3b63 1624 .module_offs = CORE_MOD,
e04d9e1e 1625 .prcm_reg_id = 1,
844a3b63
PW
1626 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1627 .idlest_reg_id = 1,
1628 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
e04d9e1e
SG
1629 },
1630 },
844a3b63
PW
1631 .class = &omap34xx_mcspi_class,
1632 .dev_attr = &omap_mcspi3_dev_attr,
e04d9e1e
SG
1633};
1634
844a3b63
PW
1635/* mcspi4 */
1636static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
7d7e1eba
TL
1637 { .name = "irq", .irq = 48 + OMAP_INTC_START, },
1638 { .irq = -1 },
e04d9e1e
SG
1639};
1640
844a3b63
PW
1641static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1642 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1643 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1644 { .dma_req = -1 }
6c3d7e34
TV
1645};
1646
844a3b63
PW
1647static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1648 .num_chipselect = 1,
1649};
1650
1651static struct omap_hwmod omap34xx_mcspi4 = {
1652 .name = "mcspi4",
1653 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
1654 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
1655 .main_clk = "mcspi4_fck",
e04d9e1e
SG
1656 .prcm = {
1657 .omap2 = {
844a3b63 1658 .module_offs = CORE_MOD,
e04d9e1e 1659 .prcm_reg_id = 1,
844a3b63
PW
1660 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1661 .idlest_reg_id = 1,
1662 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
e04d9e1e
SG
1663 },
1664 },
844a3b63
PW
1665 .class = &omap34xx_mcspi_class,
1666 .dev_attr = &omap_mcspi4_dev_attr,
e04d9e1e
SG
1667};
1668
844a3b63
PW
1669/* usbhsotg */
1670static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1671 .rev_offs = 0x0400,
1672 .sysc_offs = 0x0404,
1673 .syss_offs = 0x0408,
1674 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1675 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1676 SYSC_HAS_AUTOIDLE),
1677 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1678 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1679 .sysc_fields = &omap_hwmod_sysc_type1,
1680};
4fe20e97 1681
844a3b63
PW
1682static struct omap_hwmod_class usbotg_class = {
1683 .name = "usbotg",
1684 .sysc = &omap3xxx_usbhsotg_sysc,
4fe20e97
RN
1685};
1686
844a3b63
PW
1687/* usb_otg_hs */
1688static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1689
7d7e1eba
TL
1690 { .name = "mc", .irq = 92 + OMAP_INTC_START, },
1691 { .name = "dma", .irq = 93 + OMAP_INTC_START, },
1692 { .irq = -1 },
844a3b63
PW
1693};
1694
1695static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1696 .name = "usb_otg_hs",
1697 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
1698 .main_clk = "hsotgusb_ick",
4fe20e97
RN
1699 .prcm = {
1700 .omap2 = {
4fe20e97 1701 .prcm_reg_id = 1,
844a3b63
PW
1702 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1703 .module_offs = CORE_MOD,
4fe20e97 1704 .idlest_reg_id = 1,
844a3b63
PW
1705 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1706 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
4fe20e97
RN
1707 },
1708 },
844a3b63
PW
1709 .class = &usbotg_class,
1710
1711 /*
1712 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1713 * broken when autoidle is enabled
1714 * workaround is to disable the autoidle bit at module level.
1715 */
1716 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1717 | HWMOD_SWSUP_MSTANDBY,
4fe20e97
RN
1718};
1719
844a3b63
PW
1720/* usb_otg_hs */
1721static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
7d7e1eba
TL
1722 { .name = "mc", .irq = 71 + OMAP_INTC_START, },
1723 { .irq = -1 },
4fe20e97
RN
1724};
1725
844a3b63
PW
1726static struct omap_hwmod_class am35xx_usbotg_class = {
1727 .name = "am35xx_usbotg",
844a3b63
PW
1728};
1729
1730static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1731 .name = "am35x_otg_hs",
1732 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
89ea2583 1733 .main_clk = "hsotgusb_fck",
844a3b63 1734 .class = &am35xx_usbotg_class,
89ea2583 1735 .flags = HWMOD_NO_IDLEST,
4fe20e97
RN
1736};
1737
844a3b63
PW
1738/* MMC/SD/SDIO common */
1739static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1740 .rev_offs = 0x1fc,
1741 .sysc_offs = 0x10,
1742 .syss_offs = 0x14,
1743 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1744 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1745 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1746 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1747 .sysc_fields = &omap_hwmod_sysc_type1,
1748};
4fe20e97 1749
844a3b63
PW
1750static struct omap_hwmod_class omap34xx_mmc_class = {
1751 .name = "mmc",
1752 .sysc = &omap34xx_mmc_sysc,
4fe20e97
RN
1753};
1754
844a3b63
PW
1755/* MMC/SD/SDIO1 */
1756
1757static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
7d7e1eba
TL
1758 { .irq = 83 + OMAP_INTC_START, },
1759 { .irq = -1 },
4fe20e97
RN
1760};
1761
844a3b63
PW
1762static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1763 { .name = "tx", .dma_req = 61, },
1764 { .name = "rx", .dma_req = 62, },
bc614958 1765 { .dma_req = -1 }
4fe20e97
RN
1766};
1767
844a3b63
PW
1768static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1769 { .role = "dbck", .clk = "omap_32k_fck", },
1770};
1771
1772static struct omap_mmc_dev_attr mmc1_dev_attr = {
1773 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1774};
1775
1776/* See 35xx errata 2.1.1.128 in SPRZ278F */
1777static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1778 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1779 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1780};
1781
1782static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1783 .name = "mmc1",
1784 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1785 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1786 .opt_clks = omap34xx_mmc1_opt_clks,
1787 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1788 .main_clk = "mmchs1_fck",
4fe20e97
RN
1789 .prcm = {
1790 .omap2 = {
1791 .module_offs = CORE_MOD,
1792 .prcm_reg_id = 1,
844a3b63 1793 .module_bit = OMAP3430_EN_MMC1_SHIFT,
4fe20e97 1794 .idlest_reg_id = 1,
844a3b63 1795 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
4fe20e97
RN
1796 },
1797 },
844a3b63
PW
1798 .dev_attr = &mmc1_pre_es3_dev_attr,
1799 .class = &omap34xx_mmc_class,
4fe20e97
RN
1800};
1801
844a3b63
PW
1802static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1803 .name = "mmc1",
1804 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1805 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1806 .opt_clks = omap34xx_mmc1_opt_clks,
1807 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1808 .main_clk = "mmchs1_fck",
1809 .prcm = {
1810 .omap2 = {
1811 .module_offs = CORE_MOD,
1812 .prcm_reg_id = 1,
1813 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1814 .idlest_reg_id = 1,
1815 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1816 },
70034d38 1817 },
844a3b63
PW
1818 .dev_attr = &mmc1_dev_attr,
1819 .class = &omap34xx_mmc_class,
70034d38
VC
1820};
1821
844a3b63 1822/* MMC/SD/SDIO2 */
70034d38 1823
844a3b63 1824static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
7d7e1eba
TL
1825 { .irq = 86 + OMAP_INTC_START, },
1826 { .irq = -1 },
70034d38
VC
1827};
1828
844a3b63
PW
1829static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1830 { .name = "tx", .dma_req = 47, },
1831 { .name = "rx", .dma_req = 48, },
1832 { .dma_req = -1 }
70034d38
VC
1833};
1834
844a3b63
PW
1835static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1836 { .role = "dbck", .clk = "omap_32k_fck", },
70034d38
VC
1837};
1838
844a3b63
PW
1839/* See 35xx errata 2.1.1.128 in SPRZ278F */
1840static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1841 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
70034d38
VC
1842};
1843
844a3b63
PW
1844static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1845 .name = "mmc2",
1846 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1847 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1848 .opt_clks = omap34xx_mmc2_opt_clks,
1849 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1850 .main_clk = "mmchs2_fck",
1851 .prcm = {
1852 .omap2 = {
1853 .module_offs = CORE_MOD,
1854 .prcm_reg_id = 1,
1855 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1856 .idlest_reg_id = 1,
1857 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1858 },
70034d38 1859 },
844a3b63
PW
1860 .dev_attr = &mmc2_pre_es3_dev_attr,
1861 .class = &omap34xx_mmc_class,
70034d38
VC
1862};
1863
844a3b63
PW
1864static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1865 .name = "mmc2",
1866 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1867 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1868 .opt_clks = omap34xx_mmc2_opt_clks,
1869 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1870 .main_clk = "mmchs2_fck",
1871 .prcm = {
1872 .omap2 = {
1873 .module_offs = CORE_MOD,
1874 .prcm_reg_id = 1,
1875 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1876 .idlest_reg_id = 1,
1877 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1878 },
1879 },
1880 .class = &omap34xx_mmc_class,
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1881};
1882
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PW
1883/* MMC/SD/SDIO3 */
1884
1885static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
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TL
1886 { .irq = 94 + OMAP_INTC_START, },
1887 { .irq = -1 },
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1888};
1889
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PW
1890static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1891 { .name = "tx", .dma_req = 77, },
1892 { .name = "rx", .dma_req = 78, },
1893 { .dma_req = -1 }
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1894};
1895
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PW
1896static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1897 { .role = "dbck", .clk = "omap_32k_fck", },
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1898};
1899
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1900static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1901 .name = "mmc3",
1902 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
1903 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
1904 .opt_clks = omap34xx_mmc3_opt_clks,
1905 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1906 .main_clk = "mmchs3_fck",
1907 .prcm = {
1908 .omap2 = {
1909 .prcm_reg_id = 1,
1910 .module_bit = OMAP3430_EN_MMC3_SHIFT,
1911 .idlest_reg_id = 1,
1912 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1913 },
1914 },
1915 .class = &omap34xx_mmc_class,
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1916};
1917
1918/*
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1919 * 'usb_host_hs' class
1920 * high-speed multi-port usb host controller
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1921 */
1922
844a3b63 1923static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
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VC
1924 .rev_offs = 0x0000,
1925 .sysc_offs = 0x0010,
1926 .syss_offs = 0x0014,
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PW
1927 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1928 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1929 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1930 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1931 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1932 .sysc_fields = &omap_hwmod_sysc_type1,
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1933};
1934
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PW
1935static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1936 .name = "usb_host_hs",
1937 .sysc = &omap3xxx_usb_host_hs_sysc,
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1938};
1939
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1940static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1941 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
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1942};
1943
844a3b63 1944static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
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TL
1945 { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
1946 { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
1947 { .irq = -1 },
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1948};
1949
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1950static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1951 .name = "usb_host_hs",
1952 .class = &omap3xxx_usb_host_hs_hwmod_class,
1953 .clkdm_name = "l3_init_clkdm",
1954 .mpu_irqs = omap3xxx_usb_host_hs_irqs,
1955 .main_clk = "usbhost_48m_fck",
1956 .prcm = {
70034d38 1957 .omap2 = {
844a3b63 1958 .module_offs = OMAP3430ES2_USBHOST_MOD,
70034d38 1959 .prcm_reg_id = 1,
844a3b63 1960 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
70034d38 1961 .idlest_reg_id = 1,
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PW
1962 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1963 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
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VC
1964 },
1965 },
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PW
1966 .opt_clks = omap3xxx_usb_host_hs_opt_clks,
1967 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
70034d38 1968
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PW
1969 /*
1970 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1971 * id: i660
1972 *
1973 * Description:
1974 * In the following configuration :
1975 * - USBHOST module is set to smart-idle mode
1976 * - PRCM asserts idle_req to the USBHOST module ( This typically
1977 * happens when the system is going to a low power mode : all ports
1978 * have been suspended, the master part of the USBHOST module has
1979 * entered the standby state, and SW has cut the functional clocks)
1980 * - an USBHOST interrupt occurs before the module is able to answer
1981 * idle_ack, typically a remote wakeup IRQ.
1982 * Then the USB HOST module will enter a deadlock situation where it
1983 * is no more accessible nor functional.
1984 *
1985 * Workaround:
1986 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1987 */
1988
1989 /*
1990 * Errata: USB host EHCI may stall when entering smart-standby mode
1991 * Id: i571
1992 *
1993 * Description:
1994 * When the USBHOST module is set to smart-standby mode, and when it is
1995 * ready to enter the standby state (i.e. all ports are suspended and
1996 * all attached devices are in suspend mode), then it can wrongly assert
1997 * the Mstandby signal too early while there are still some residual OCP
1998 * transactions ongoing. If this condition occurs, the internal state
1999 * machine may go to an undefined state and the USB link may be stuck
2000 * upon the next resume.
2001 *
2002 * Workaround:
2003 * Don't use smart standby; use only force standby,
2004 * hence HWMOD_SWSUP_MSTANDBY
2005 */
2006
2007 /*
2008 * During system boot; If the hwmod framework resets the module
2009 * the module will have smart idle settings; which can lead to deadlock
2010 * (above Errata Id:i660); so, dont reset the module during boot;
2011 * Use HWMOD_INIT_NO_RESET.
2012 */
70034d38 2013
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PW
2014 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
2015 HWMOD_INIT_NO_RESET,
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VC
2016};
2017
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PW
2018/*
2019 * 'usb_tll_hs' class
2020 * usb_tll_hs module is the adapter on the usb_host_hs ports
2021 */
2022static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
2023 .rev_offs = 0x0000,
2024 .sysc_offs = 0x0010,
2025 .syss_offs = 0x0014,
2026 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2027 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2028 SYSC_HAS_AUTOIDLE),
2029 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2030 .sysc_fields = &omap_hwmod_sysc_type1,
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VC
2031};
2032
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PW
2033static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
2034 .name = "usb_tll_hs",
2035 .sysc = &omap3xxx_usb_tll_hs_sysc,
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VC
2036};
2037
844a3b63 2038static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
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TL
2039 { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
2040 { .irq = -1 },
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VC
2041};
2042
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PW
2043static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2044 .name = "usb_tll_hs",
2045 .class = &omap3xxx_usb_tll_hs_hwmod_class,
2046 .clkdm_name = "l3_init_clkdm",
2047 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
2048 .main_clk = "usbtll_fck",
2049 .prcm = {
70034d38 2050 .omap2 = {
844a3b63
PW
2051 .module_offs = CORE_MOD,
2052 .prcm_reg_id = 3,
2053 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
2054 .idlest_reg_id = 3,
2055 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
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VC
2056 },
2057 },
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VC
2058};
2059
45a4bb06
PW
2060static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2061 .name = "hdq1w",
2062 .mpu_irqs = omap2_hdq1w_mpu_irqs,
2063 .main_clk = "hdq_fck",
2064 .prcm = {
2065 .omap2 = {
2066 .module_offs = CORE_MOD,
2067 .prcm_reg_id = 1,
2068 .module_bit = OMAP3430_EN_HDQ_SHIFT,
2069 .idlest_reg_id = 1,
2070 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2071 },
2072 },
2073 .class = &omap2_hdq1w_class,
2074};
2075
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TK
2076/* SAD2D */
2077static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
2078 { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
2079 { .name = "rst_modem_sw", .rst_shift = 1 },
2080};
2081
2082static struct omap_hwmod_class omap3xxx_sad2d_class = {
2083 .name = "sad2d",
2084};
2085
2086static struct omap_hwmod omap3xxx_sad2d_hwmod = {
2087 .name = "sad2d",
2088 .rst_lines = omap3xxx_sad2d_resets,
2089 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets),
2090 .main_clk = "sad2d_ick",
2091 .prcm = {
2092 .omap2 = {
2093 .module_offs = CORE_MOD,
2094 .prcm_reg_id = 1,
2095 .module_bit = OMAP3430_EN_SAD2D_SHIFT,
2096 .idlest_reg_id = 1,
2097 .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
2098 },
2099 },
2100 .class = &omap3xxx_sad2d_class,
2101};
2102
c8d82ff6
VH
2103/*
2104 * '32K sync counter' class
2105 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2106 */
2107static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2108 .rev_offs = 0x0000,
2109 .sysc_offs = 0x0004,
2110 .sysc_flags = SYSC_HAS_SIDLEMODE,
2111 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
2112 .sysc_fields = &omap_hwmod_sysc_type1,
2113};
2114
2115static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2116 .name = "counter",
2117 .sysc = &omap3xxx_counter_sysc,
2118};
2119
2120static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2121 .name = "counter_32k",
2122 .class = &omap3xxx_counter_hwmod_class,
2123 .clkdm_name = "wkup_clkdm",
2124 .flags = HWMOD_SWSUP_SIDLE,
2125 .main_clk = "wkup_32k_fck",
2126 .prcm = {
2127 .omap2 = {
2128 .module_offs = WKUP_MOD,
2129 .prcm_reg_id = 1,
2130 .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2131 .idlest_reg_id = 1,
2132 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2133 },
2134 },
2135};
2136
49484a60
AM
2137/*
2138 * 'gpmc' class
2139 * general purpose memory controller
2140 */
2141
2142static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
2143 .rev_offs = 0x0000,
2144 .sysc_offs = 0x0010,
2145 .syss_offs = 0x0014,
2146 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2147 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2148 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2149 .sysc_fields = &omap_hwmod_sysc_type1,
2150};
2151
2152static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
2153 .name = "gpmc",
2154 .sysc = &omap3xxx_gpmc_sysc,
2155};
2156
2157static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
2158 { .irq = 20 },
2159 { .irq = -1 }
2160};
2161
2162static struct omap_hwmod omap3xxx_gpmc_hwmod = {
2163 .name = "gpmc",
2164 .class = &omap3xxx_gpmc_hwmod_class,
2165 .clkdm_name = "core_l3_clkdm",
2166 .mpu_irqs = omap3xxx_gpmc_irqs,
2167 .main_clk = "gpmc_fck",
2168 /*
2169 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
2170 * block. It is not being added due to any known bugs with
2171 * resetting the GPMC IP block, but rather because any timings
2172 * set by the bootloader are not being correctly programmed by
2173 * the kernel from the board file or DT data.
2174 * HWMOD_INIT_NO_RESET should be removed ASAP.
2175 */
2176 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
2177 HWMOD_NO_IDLEST),
2178};
2179
844a3b63
PW
2180/*
2181 * interfaces
2182 */
2183
2184/* L3 -> L4_CORE interface */
2185static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2186 .master = &omap3xxx_l3_main_hwmod,
2187 .slave = &omap3xxx_l4_core_hwmod,
2188 .user = OCP_USER_MPU | OCP_USER_SDMA,
70034d38
VC
2189};
2190
844a3b63
PW
2191/* L3 -> L4_PER interface */
2192static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2193 .master = &omap3xxx_l3_main_hwmod,
2194 .slave = &omap3xxx_l4_per_hwmod,
2195 .user = OCP_USER_MPU | OCP_USER_SDMA,
70034d38
VC
2196};
2197
844a3b63
PW
2198static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2199 {
2200 .pa_start = 0x68000000,
2201 .pa_end = 0x6800ffff,
2202 .flags = ADDR_TYPE_RT,
70034d38 2203 },
844a3b63 2204 { }
70034d38
VC
2205};
2206
844a3b63
PW
2207/* MPU -> L3 interface */
2208static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2209 .master = &omap3xxx_mpu_hwmod,
2210 .slave = &omap3xxx_l3_main_hwmod,
2211 .addr = omap3xxx_l3_main_addrs,
2212 .user = OCP_USER_MPU,
70034d38
VC
2213};
2214
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JH
2215static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
2216 {
2217 .pa_start = 0x54000000,
2218 .pa_end = 0x547fffff,
2219 .flags = ADDR_TYPE_RT,
2220 },
2221 { }
2222};
2223
2224/* l3 -> debugss */
2225static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
2226 .master = &omap3xxx_l3_main_hwmod,
2227 .slave = &omap3xxx_debugss_hwmod,
76a5d9bf 2228 .addr = omap3xxx_l4_emu_addrs,
c7dad45f
JH
2229 .user = OCP_USER_MPU,
2230};
2231
844a3b63
PW
2232/* DSS -> l3 */
2233static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2234 .master = &omap3430es1_dss_core_hwmod,
2235 .slave = &omap3xxx_l3_main_hwmod,
2236 .user = OCP_USER_MPU | OCP_USER_SDMA,
70034d38
VC
2237};
2238
844a3b63
PW
2239static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2240 .master = &omap3xxx_dss_core_hwmod,
2241 .slave = &omap3xxx_l3_main_hwmod,
2242 .fw = {
70034d38 2243 .omap2 = {
844a3b63
PW
2244 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2245 .flags = OMAP_FIREWALL_L3,
2246 }
70034d38 2247 },
844a3b63 2248 .user = OCP_USER_MPU | OCP_USER_SDMA,
70034d38
VC
2249};
2250
844a3b63
PW
2251/* l3_core -> usbhsotg interface */
2252static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2253 .master = &omap3xxx_usbhsotg_hwmod,
01438ab6
MK
2254 .slave = &omap3xxx_l3_main_hwmod,
2255 .clk = "core_l3_ick",
844a3b63 2256 .user = OCP_USER_MPU,
01438ab6
MK
2257};
2258
844a3b63
PW
2259/* l3_core -> am35xx_usbhsotg interface */
2260static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2261 .master = &am35xx_usbhsotg_hwmod,
2262 .slave = &omap3xxx_l3_main_hwmod,
89ea2583 2263 .clk = "hsotgusb_ick",
844a3b63 2264 .user = OCP_USER_MPU,
01438ab6 2265};
89ea2583 2266
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TK
2267/* l3_core -> sad2d interface */
2268static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
2269 .master = &omap3xxx_sad2d_hwmod,
2270 .slave = &omap3xxx_l3_main_hwmod,
2271 .clk = "core_l3_ick",
2272 .user = OCP_USER_MPU,
2273};
2274
844a3b63
PW
2275/* L4_CORE -> L4_WKUP interface */
2276static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2277 .master = &omap3xxx_l4_core_hwmod,
2278 .slave = &omap3xxx_l4_wkup_hwmod,
2279 .user = OCP_USER_MPU | OCP_USER_SDMA,
01438ab6
MK
2280};
2281
844a3b63
PW
2282/* L4 CORE -> MMC1 interface */
2283static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
01438ab6 2284 .master = &omap3xxx_l4_core_hwmod,
844a3b63
PW
2285 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
2286 .clk = "mmchs1_ick",
2287 .addr = omap2430_mmc1_addr_space,
01438ab6 2288 .user = OCP_USER_MPU | OCP_USER_SDMA,
844a3b63 2289 .flags = OMAP_FIREWALL_L4
01438ab6
MK
2290};
2291
844a3b63
PW
2292static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2293 .master = &omap3xxx_l4_core_hwmod,
2294 .slave = &omap3xxx_es3plus_mmc1_hwmod,
2295 .clk = "mmchs1_ick",
2296 .addr = omap2430_mmc1_addr_space,
2297 .user = OCP_USER_MPU | OCP_USER_SDMA,
2298 .flags = OMAP_FIREWALL_L4
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MK
2299};
2300
844a3b63
PW
2301/* L4 CORE -> MMC2 interface */
2302static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2303 .master = &omap3xxx_l4_core_hwmod,
2304 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
2305 .clk = "mmchs2_ick",
2306 .addr = omap2430_mmc2_addr_space,
2307 .user = OCP_USER_MPU | OCP_USER_SDMA,
2308 .flags = OMAP_FIREWALL_L4
2309};
70034d38 2310
844a3b63
PW
2311static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2312 .master = &omap3xxx_l4_core_hwmod,
2313 .slave = &omap3xxx_es3plus_mmc2_hwmod,
2314 .clk = "mmchs2_ick",
2315 .addr = omap2430_mmc2_addr_space,
2316 .user = OCP_USER_MPU | OCP_USER_SDMA,
2317 .flags = OMAP_FIREWALL_L4
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VC
2318};
2319
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PW
2320/* L4 CORE -> MMC3 interface */
2321static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2322 {
2323 .pa_start = 0x480ad000,
2324 .pa_end = 0x480ad1ff,
2325 .flags = ADDR_TYPE_RT,
2326 },
2327 { }
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VC
2328};
2329
844a3b63
PW
2330static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2331 .master = &omap3xxx_l4_core_hwmod,
2332 .slave = &omap3xxx_mmc3_hwmod,
2333 .clk = "mmchs3_ick",
2334 .addr = omap3xxx_mmc3_addr_space,
2335 .user = OCP_USER_MPU | OCP_USER_SDMA,
2336 .flags = OMAP_FIREWALL_L4
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VC
2337};
2338
844a3b63
PW
2339/* L4 CORE -> UART1 interface */
2340static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
dc48e5fc 2341 {
844a3b63
PW
2342 .pa_start = OMAP3_UART1_BASE,
2343 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
2344 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
dc48e5fc 2345 },
78183f3f 2346 { }
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VC
2347};
2348
844a3b63 2349static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
dc48e5fc 2350 .master = &omap3xxx_l4_core_hwmod,
844a3b63
PW
2351 .slave = &omap3xxx_uart1_hwmod,
2352 .clk = "uart1_ick",
2353 .addr = omap3xxx_uart1_addr_space,
dc48e5fc 2354 .user = OCP_USER_MPU | OCP_USER_SDMA,
70034d38
VC
2355};
2356
844a3b63
PW
2357/* L4 CORE -> UART2 interface */
2358static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2359 {
2360 .pa_start = OMAP3_UART2_BASE,
2361 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
2362 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
70034d38 2363 },
844a3b63 2364 { }
70034d38
VC
2365};
2366
844a3b63
PW
2367static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2368 .master = &omap3xxx_l4_core_hwmod,
2369 .slave = &omap3xxx_uart2_hwmod,
2370 .clk = "uart2_ick",
2371 .addr = omap3xxx_uart2_addr_space,
2372 .user = OCP_USER_MPU | OCP_USER_SDMA,
70034d38
VC
2373};
2374
844a3b63
PW
2375/* L4 PER -> UART3 interface */
2376static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
dc48e5fc 2377 {
844a3b63
PW
2378 .pa_start = OMAP3_UART3_BASE,
2379 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
2380 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
70034d38 2381 },
78183f3f 2382 { }
70034d38
VC
2383};
2384
844a3b63 2385static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
dc48e5fc 2386 .master = &omap3xxx_l4_per_hwmod,
844a3b63
PW
2387 .slave = &omap3xxx_uart3_hwmod,
2388 .clk = "uart3_ick",
2389 .addr = omap3xxx_uart3_addr_space,
dc48e5fc 2390 .user = OCP_USER_MPU | OCP_USER_SDMA,
70034d38
VC
2391};
2392
844a3b63
PW
2393/* L4 PER -> UART4 interface */
2394static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2395 {
2396 .pa_start = OMAP3_UART4_BASE,
2397 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
2398 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
70034d38 2399 },
844a3b63 2400 { }
70034d38
VC
2401};
2402
844a3b63
PW
2403static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2404 .master = &omap3xxx_l4_per_hwmod,
2405 .slave = &omap36xx_uart4_hwmod,
2406 .clk = "uart4_ick",
2407 .addr = omap36xx_uart4_addr_space,
2408 .user = OCP_USER_MPU | OCP_USER_SDMA,
70034d38
VC
2409};
2410
844a3b63
PW
2411/* AM35xx: L4 CORE -> UART4 interface */
2412static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
dc48e5fc 2413 {
844a3b63
PW
2414 .pa_start = OMAP3_UART4_AM35XX_BASE,
2415 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2416 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
dc48e5fc 2417 },
bf765237 2418 { }
70034d38
VC
2419};
2420
844a3b63
PW
2421static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2422 .master = &omap3xxx_l4_core_hwmod,
2423 .slave = &am35xx_uart4_hwmod,
2424 .clk = "uart4_ick",
2425 .addr = am35xx_uart4_addr_space,
dc48e5fc
C
2426 .user = OCP_USER_MPU | OCP_USER_SDMA,
2427};
2428
844a3b63
PW
2429/* L4 CORE -> I2C1 interface */
2430static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2431 .master = &omap3xxx_l4_core_hwmod,
2432 .slave = &omap3xxx_i2c1_hwmod,
2433 .clk = "i2c1_ick",
2434 .addr = omap2_i2c1_addr_space,
2435 .fw = {
2436 .omap2 = {
2437 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
2438 .l4_prot_group = 7,
2439 .flags = OMAP_FIREWALL_L4,
2440 }
2441 },
2442 .user = OCP_USER_MPU | OCP_USER_SDMA,
8b1906f1
KVA
2443};
2444
844a3b63
PW
2445/* L4 CORE -> I2C2 interface */
2446static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2447 .master = &omap3xxx_l4_core_hwmod,
2448 .slave = &omap3xxx_i2c2_hwmod,
2449 .clk = "i2c2_ick",
2450 .addr = omap2_i2c2_addr_space,
2451 .fw = {
70034d38 2452 .omap2 = {
844a3b63
PW
2453 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
2454 .l4_prot_group = 7,
2455 .flags = OMAP_FIREWALL_L4,
2456 }
70034d38 2457 },
844a3b63 2458 .user = OCP_USER_MPU | OCP_USER_SDMA,
70034d38
VC
2459};
2460
844a3b63
PW
2461/* L4 CORE -> I2C3 interface */
2462static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2463 {
2464 .pa_start = 0x48060000,
2465 .pa_end = 0x48060000 + SZ_128 - 1,
2466 .flags = ADDR_TYPE_RT,
2467 },
2468 { }
70034d38
VC
2469};
2470
844a3b63
PW
2471static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2472 .master = &omap3xxx_l4_core_hwmod,
2473 .slave = &omap3xxx_i2c3_hwmod,
2474 .clk = "i2c3_ick",
2475 .addr = omap3xxx_i2c3_addr_space,
2476 .fw = {
2477 .omap2 = {
2478 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
2479 .l4_prot_group = 7,
2480 .flags = OMAP_FIREWALL_L4,
2481 }
2482 },
2483 .user = OCP_USER_MPU | OCP_USER_SDMA,
70034d38
VC
2484};
2485
844a3b63
PW
2486/* L4 CORE -> SR1 interface */
2487static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
dc48e5fc 2488 {
844a3b63
PW
2489 .pa_start = OMAP34XX_SR1_BASE,
2490 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
2491 .flags = ADDR_TYPE_RT,
dc48e5fc 2492 },
78183f3f 2493 { }
70034d38
VC
2494};
2495
844a3b63
PW
2496static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2497 .master = &omap3xxx_l4_core_hwmod,
2498 .slave = &omap34xx_sr1_hwmod,
2499 .clk = "sr_l4_ick",
2500 .addr = omap3_sr1_addr_space,
2501 .user = OCP_USER_MPU,
70034d38
VC
2502};
2503
844a3b63
PW
2504static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2505 .master = &omap3xxx_l4_core_hwmod,
2506 .slave = &omap36xx_sr1_hwmod,
2507 .clk = "sr_l4_ick",
2508 .addr = omap3_sr1_addr_space,
2509 .user = OCP_USER_MPU,
2510};
2511
2512/* L4 CORE -> SR1 interface */
2513static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2514 {
2515 .pa_start = OMAP34XX_SR2_BASE,
2516 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
2517 .flags = ADDR_TYPE_RT,
70034d38 2518 },
844a3b63 2519 { }
70034d38
VC
2520};
2521
844a3b63
PW
2522static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2523 .master = &omap3xxx_l4_core_hwmod,
2524 .slave = &omap34xx_sr2_hwmod,
2525 .clk = "sr_l4_ick",
2526 .addr = omap3_sr2_addr_space,
2527 .user = OCP_USER_MPU,
70034d38
VC
2528};
2529
844a3b63
PW
2530static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2531 .master = &omap3xxx_l4_core_hwmod,
2532 .slave = &omap36xx_sr2_hwmod,
2533 .clk = "sr_l4_ick",
2534 .addr = omap3_sr2_addr_space,
2535 .user = OCP_USER_MPU,
70034d38
VC
2536};
2537
844a3b63 2538static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
dc48e5fc 2539 {
844a3b63
PW
2540 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
2541 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
dc48e5fc
C
2542 .flags = ADDR_TYPE_RT
2543 },
78183f3f 2544 { }
70034d38
VC
2545};
2546
844a3b63
PW
2547/* l4_core -> usbhsotg */
2548static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
dc48e5fc 2549 .master = &omap3xxx_l4_core_hwmod,
844a3b63
PW
2550 .slave = &omap3xxx_usbhsotg_hwmod,
2551 .clk = "l4_ick",
2552 .addr = omap3xxx_usbhsotg_addrs,
2553 .user = OCP_USER_MPU,
dc48e5fc
C
2554};
2555
844a3b63
PW
2556static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2557 {
2558 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
2559 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2560 .flags = ADDR_TYPE_RT
70034d38 2561 },
844a3b63 2562 { }
70034d38
VC
2563};
2564
844a3b63
PW
2565/* l4_core -> usbhsotg */
2566static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2567 .master = &omap3xxx_l4_core_hwmod,
2568 .slave = &am35xx_usbhsotg_hwmod,
89ea2583 2569 .clk = "hsotgusb_ick",
844a3b63
PW
2570 .addr = am35xx_usbhsotg_addrs,
2571 .user = OCP_USER_MPU,
01438ab6
MK
2572};
2573
844a3b63
PW
2574/* L4_WKUP -> L4_SEC interface */
2575static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2576 .master = &omap3xxx_l4_wkup_hwmod,
2577 .slave = &omap3xxx_l4_sec_hwmod,
2578 .user = OCP_USER_MPU | OCP_USER_SDMA,
01438ab6
MK
2579};
2580
844a3b63
PW
2581/* IVA2 <- L3 interface */
2582static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2583 .master = &omap3xxx_l3_main_hwmod,
2584 .slave = &omap3xxx_iva_hwmod,
064931ab 2585 .clk = "core_l3_ick",
844a3b63 2586 .user = OCP_USER_MPU | OCP_USER_SDMA,
01438ab6
MK
2587};
2588
844a3b63 2589static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
dc48e5fc 2590 {
844a3b63
PW
2591 .pa_start = 0x48318000,
2592 .pa_end = 0x48318000 + SZ_1K - 1,
dc48e5fc
C
2593 .flags = ADDR_TYPE_RT
2594 },
78183f3f 2595 { }
01438ab6
MK
2596};
2597
844a3b63
PW
2598/* l4_wkup -> timer1 */
2599static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2600 .master = &omap3xxx_l4_wkup_hwmod,
2601 .slave = &omap3xxx_timer1_hwmod,
2602 .clk = "gpt1_ick",
2603 .addr = omap3xxx_timer1_addrs,
2604 .user = OCP_USER_MPU | OCP_USER_SDMA,
01438ab6
MK
2605};
2606
844a3b63
PW
2607static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2608 {
2609 .pa_start = 0x49032000,
2610 .pa_end = 0x49032000 + SZ_1K - 1,
2611 .flags = ADDR_TYPE_RT
01438ab6 2612 },
844a3b63 2613 { }
01438ab6
MK
2614};
2615
844a3b63
PW
2616/* l4_per -> timer2 */
2617static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2618 .master = &omap3xxx_l4_per_hwmod,
2619 .slave = &omap3xxx_timer2_hwmod,
2620 .clk = "gpt2_ick",
2621 .addr = omap3xxx_timer2_addrs,
2622 .user = OCP_USER_MPU | OCP_USER_SDMA,
01438ab6
MK
2623};
2624
844a3b63 2625static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
dc48e5fc 2626 {
844a3b63
PW
2627 .pa_start = 0x49034000,
2628 .pa_end = 0x49034000 + SZ_1K - 1,
dc48e5fc
C
2629 .flags = ADDR_TYPE_RT
2630 },
78183f3f 2631 { }
01438ab6
MK
2632};
2633
844a3b63
PW
2634/* l4_per -> timer3 */
2635static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
dc48e5fc 2636 .master = &omap3xxx_l4_per_hwmod,
844a3b63
PW
2637 .slave = &omap3xxx_timer3_hwmod,
2638 .clk = "gpt3_ick",
2639 .addr = omap3xxx_timer3_addrs,
2640 .user = OCP_USER_MPU | OCP_USER_SDMA,
01438ab6
MK
2641};
2642
844a3b63
PW
2643static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2644 {
2645 .pa_start = 0x49036000,
2646 .pa_end = 0x49036000 + SZ_1K - 1,
2647 .flags = ADDR_TYPE_RT
01438ab6 2648 },
844a3b63 2649 { }
01438ab6
MK
2650};
2651
844a3b63
PW
2652/* l4_per -> timer4 */
2653static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2654 .master = &omap3xxx_l4_per_hwmod,
2655 .slave = &omap3xxx_timer4_hwmod,
2656 .clk = "gpt4_ick",
2657 .addr = omap3xxx_timer4_addrs,
2658 .user = OCP_USER_MPU | OCP_USER_SDMA,
d3442726
TG
2659};
2660
844a3b63
PW
2661static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2662 {
2663 .pa_start = 0x49038000,
2664 .pa_end = 0x49038000 + SZ_1K - 1,
2665 .flags = ADDR_TYPE_RT
2666 },
2667 { }
d3442726
TG
2668};
2669
844a3b63
PW
2670/* l4_per -> timer5 */
2671static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2672 .master = &omap3xxx_l4_per_hwmod,
2673 .slave = &omap3xxx_timer5_hwmod,
2674 .clk = "gpt5_ick",
2675 .addr = omap3xxx_timer5_addrs,
2676 .user = OCP_USER_MPU | OCP_USER_SDMA,
d3442726
TG
2677};
2678
844a3b63
PW
2679static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2680 {
2681 .pa_start = 0x4903A000,
2682 .pa_end = 0x4903A000 + SZ_1K - 1,
2683 .flags = ADDR_TYPE_RT
2684 },
2685 { }
cea6b942
SG
2686};
2687
844a3b63
PW
2688/* l4_per -> timer6 */
2689static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2690 .master = &omap3xxx_l4_per_hwmod,
2691 .slave = &omap3xxx_timer6_hwmod,
2692 .clk = "gpt6_ick",
2693 .addr = omap3xxx_timer6_addrs,
2694 .user = OCP_USER_MPU | OCP_USER_SDMA,
d3442726
TG
2695};
2696
844a3b63
PW
2697static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2698 {
2699 .pa_start = 0x4903C000,
2700 .pa_end = 0x4903C000 + SZ_1K - 1,
2701 .flags = ADDR_TYPE_RT
d3442726 2702 },
844a3b63 2703 { }
d3442726
TG
2704};
2705
844a3b63
PW
2706/* l4_per -> timer7 */
2707static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2708 .master = &omap3xxx_l4_per_hwmod,
2709 .slave = &omap3xxx_timer7_hwmod,
2710 .clk = "gpt7_ick",
2711 .addr = omap3xxx_timer7_addrs,
2712 .user = OCP_USER_MPU | OCP_USER_SDMA,
cea6b942
SG
2713};
2714
844a3b63
PW
2715static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2716 {
2717 .pa_start = 0x4903E000,
2718 .pa_end = 0x4903E000 + SZ_1K - 1,
2719 .flags = ADDR_TYPE_RT
d3442726 2720 },
844a3b63 2721 { }
d3442726
TG
2722};
2723
844a3b63
PW
2724/* l4_per -> timer8 */
2725static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2726 .master = &omap3xxx_l4_per_hwmod,
2727 .slave = &omap3xxx_timer8_hwmod,
2728 .clk = "gpt8_ick",
2729 .addr = omap3xxx_timer8_addrs,
2730 .user = OCP_USER_MPU | OCP_USER_SDMA,
d3442726
TG
2731};
2732
844a3b63
PW
2733static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2734 {
2735 .pa_start = 0x49040000,
2736 .pa_end = 0x49040000 + SZ_1K - 1,
2737 .flags = ADDR_TYPE_RT
2738 },
2739 { }
2740};
0f9dfdd3 2741
844a3b63
PW
2742/* l4_per -> timer9 */
2743static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2744 .master = &omap3xxx_l4_per_hwmod,
2745 .slave = &omap3xxx_timer9_hwmod,
2746 .clk = "gpt9_ick",
2747 .addr = omap3xxx_timer9_addrs,
2748 .user = OCP_USER_MPU | OCP_USER_SDMA,
0f9dfdd3
FC
2749};
2750
844a3b63
PW
2751/* l4_core -> timer10 */
2752static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2753 .master = &omap3xxx_l4_core_hwmod,
2754 .slave = &omap3xxx_timer10_hwmod,
2755 .clk = "gpt10_ick",
2756 .addr = omap2_timer10_addrs,
2757 .user = OCP_USER_MPU | OCP_USER_SDMA,
0f9dfdd3
FC
2758};
2759
844a3b63
PW
2760/* l4_core -> timer11 */
2761static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2762 .master = &omap3xxx_l4_core_hwmod,
2763 .slave = &omap3xxx_timer11_hwmod,
2764 .clk = "gpt11_ick",
2765 .addr = omap2_timer11_addrs,
2766 .user = OCP_USER_MPU | OCP_USER_SDMA,
0f9dfdd3
FC
2767};
2768
844a3b63 2769static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
0f9dfdd3 2770 {
844a3b63
PW
2771 .pa_start = 0x48304000,
2772 .pa_end = 0x48304000 + SZ_1K - 1,
2773 .flags = ADDR_TYPE_RT
0f9dfdd3 2774 },
78183f3f 2775 { }
0f9dfdd3
FC
2776};
2777
844a3b63
PW
2778/* l4_core -> timer12 */
2779static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2780 .master = &omap3xxx_l4_sec_hwmod,
2781 .slave = &omap3xxx_timer12_hwmod,
2782 .clk = "gpt12_ick",
2783 .addr = omap3xxx_timer12_addrs,
0f9dfdd3
FC
2784 .user = OCP_USER_MPU | OCP_USER_SDMA,
2785};
2786
844a3b63
PW
2787/* l4_wkup -> wd_timer2 */
2788static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2789 {
2790 .pa_start = 0x48314000,
2791 .pa_end = 0x4831407f,
2792 .flags = ADDR_TYPE_RT
0f9dfdd3 2793 },
844a3b63 2794 { }
0f9dfdd3
FC
2795};
2796
844a3b63
PW
2797static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2798 .master = &omap3xxx_l4_wkup_hwmod,
2799 .slave = &omap3xxx_wd_timer2_hwmod,
2800 .clk = "wdt2_ick",
2801 .addr = omap3xxx_wd_timer2_addrs,
2802 .user = OCP_USER_MPU | OCP_USER_SDMA,
2803};
2804
2805/* l4_core -> dss */
2806static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
0f616a4e 2807 .master = &omap3xxx_l4_core_hwmod,
844a3b63
PW
2808 .slave = &omap3430es1_dss_core_hwmod,
2809 .clk = "dss_ick",
2810 .addr = omap2_dss_addrs,
2811 .fw = {
2812 .omap2 = {
2813 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2814 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2815 .flags = OMAP_FIREWALL_L4,
2816 }
2817 },
0f616a4e
C
2818 .user = OCP_USER_MPU | OCP_USER_SDMA,
2819};
2820
844a3b63 2821static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
0f616a4e 2822 .master = &omap3xxx_l4_core_hwmod,
844a3b63
PW
2823 .slave = &omap3xxx_dss_core_hwmod,
2824 .clk = "dss_ick",
2825 .addr = omap2_dss_addrs,
2826 .fw = {
2827 .omap2 = {
2828 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2829 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2830 .flags = OMAP_FIREWALL_L4,
2831 }
2832 },
0f616a4e
C
2833 .user = OCP_USER_MPU | OCP_USER_SDMA,
2834};
2835
844a3b63
PW
2836/* l4_core -> dss_dispc */
2837static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
0f616a4e 2838 .master = &omap3xxx_l4_core_hwmod,
844a3b63
PW
2839 .slave = &omap3xxx_dss_dispc_hwmod,
2840 .clk = "dss_ick",
2841 .addr = omap2_dss_dispc_addrs,
2842 .fw = {
2843 .omap2 = {
2844 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2845 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2846 .flags = OMAP_FIREWALL_L4,
2847 }
2848 },
0f616a4e
C
2849 .user = OCP_USER_MPU | OCP_USER_SDMA,
2850};
2851
844a3b63 2852static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
0f616a4e 2853 {
844a3b63
PW
2854 .pa_start = 0x4804FC00,
2855 .pa_end = 0x4804FFFF,
2856 .flags = ADDR_TYPE_RT
0f616a4e 2857 },
78183f3f 2858 { }
0f616a4e
C
2859};
2860
844a3b63
PW
2861/* l4_core -> dss_dsi1 */
2862static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
0f616a4e 2863 .master = &omap3xxx_l4_core_hwmod,
844a3b63
PW
2864 .slave = &omap3xxx_dss_dsi1_hwmod,
2865 .clk = "dss_ick",
2866 .addr = omap3xxx_dss_dsi1_addrs,
2867 .fw = {
2868 .omap2 = {
2869 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2870 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2871 .flags = OMAP_FIREWALL_L4,
2872 }
2873 },
0f616a4e
C
2874 .user = OCP_USER_MPU | OCP_USER_SDMA,
2875};
2876
844a3b63
PW
2877/* l4_core -> dss_rfbi */
2878static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2879 .master = &omap3xxx_l4_core_hwmod,
2880 .slave = &omap3xxx_dss_rfbi_hwmod,
2881 .clk = "dss_ick",
2882 .addr = omap2_dss_rfbi_addrs,
2883 .fw = {
0f616a4e 2884 .omap2 = {
844a3b63
PW
2885 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2886 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2887 .flags = OMAP_FIREWALL_L4,
2888 }
0f616a4e 2889 },
844a3b63 2890 .user = OCP_USER_MPU | OCP_USER_SDMA,
0f616a4e
C
2891};
2892
844a3b63
PW
2893/* l4_core -> dss_venc */
2894static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2895 .master = &omap3xxx_l4_core_hwmod,
2896 .slave = &omap3xxx_dss_venc_hwmod,
2897 .clk = "dss_ick",
2898 .addr = omap2_dss_venc_addrs,
2899 .fw = {
70034d38 2900 .omap2 = {
844a3b63
PW
2901 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2902 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2903 .flags = OMAP_FIREWALL_L4,
2904 }
70034d38 2905 },
844a3b63
PW
2906 .flags = OCPIF_SWSUP_IDLE,
2907 .user = OCP_USER_MPU | OCP_USER_SDMA,
70034d38
VC
2908};
2909
844a3b63
PW
2910/* l4_wkup -> gpio1 */
2911static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2912 {
2913 .pa_start = 0x48310000,
2914 .pa_end = 0x483101ff,
2915 .flags = ADDR_TYPE_RT
2916 },
2917 { }
70034d38
VC
2918};
2919
844a3b63
PW
2920static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2921 .master = &omap3xxx_l4_wkup_hwmod,
2922 .slave = &omap3xxx_gpio1_hwmod,
2923 .addr = omap3xxx_gpio1_addrs,
2924 .user = OCP_USER_MPU | OCP_USER_SDMA,
0f616a4e
C
2925};
2926
844a3b63
PW
2927/* l4_per -> gpio2 */
2928static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2929 {
2930 .pa_start = 0x49050000,
2931 .pa_end = 0x490501ff,
2932 .flags = ADDR_TYPE_RT
70034d38 2933 },
844a3b63 2934 { }
70034d38
VC
2935};
2936
844a3b63
PW
2937static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2938 .master = &omap3xxx_l4_per_hwmod,
2939 .slave = &omap3xxx_gpio2_hwmod,
2940 .addr = omap3xxx_gpio2_addrs,
2941 .user = OCP_USER_MPU | OCP_USER_SDMA,
70034d38
VC
2942};
2943
844a3b63
PW
2944/* l4_per -> gpio3 */
2945static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2946 {
2947 .pa_start = 0x49052000,
2948 .pa_end = 0x490521ff,
2949 .flags = ADDR_TYPE_RT
2950 },
2951 { }
70034d38
VC
2952};
2953
844a3b63
PW
2954static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2955 .master = &omap3xxx_l4_per_hwmod,
2956 .slave = &omap3xxx_gpio3_hwmod,
2957 .addr = omap3xxx_gpio3_addrs,
2958 .user = OCP_USER_MPU | OCP_USER_SDMA,
0f616a4e
C
2959};
2960
5486474c
PW
2961/*
2962 * 'mmu' class
2963 * The memory management unit performs virtual to physical address translation
2964 * for its requestors.
2965 */
2966
2967static struct omap_hwmod_class_sysconfig mmu_sysc = {
2968 .rev_offs = 0x000,
2969 .sysc_offs = 0x010,
2970 .syss_offs = 0x014,
2971 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2972 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2973 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2974 .sysc_fields = &omap_hwmod_sysc_type1,
2975};
2976
2977static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2978 .name = "mmu",
2979 .sysc = &mmu_sysc,
2980};
2981
2982/* mmu isp */
2983
2984static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
2985 .da_start = 0x0,
2986 .da_end = 0xfffff000,
2987 .nr_tlb_entries = 8,
2988};
2989
2990static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2991static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
2992 { .irq = 24 },
2993 { .irq = -1 }
2994};
2995
2996static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = {
2997 {
2998 .pa_start = 0x480bd400,
2999 .pa_end = 0x480bd47f,
3000 .flags = ADDR_TYPE_RT,
3001 },
3002 { }
3003};
3004
3005/* l4_core -> mmu isp */
3006static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
3007 .master = &omap3xxx_l4_core_hwmod,
3008 .slave = &omap3xxx_mmu_isp_hwmod,
3009 .addr = omap3xxx_mmu_isp_addrs,
3010 .user = OCP_USER_MPU | OCP_USER_SDMA,
3011};
3012
3013static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
3014 .name = "mmu_isp",
3015 .class = &omap3xxx_mmu_hwmod_class,
3016 .mpu_irqs = omap3xxx_mmu_isp_irqs,
3017 .main_clk = "cam_ick",
3018 .dev_attr = &mmu_isp_dev_attr,
3019 .flags = HWMOD_NO_IDLEST,
3020};
3021
3022#ifdef CONFIG_OMAP_IOMMU_IVA2
3023
3024/* mmu iva */
3025
3026static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
3027 .da_start = 0x11000000,
3028 .da_end = 0xfffff000,
3029 .nr_tlb_entries = 32,
3030};
3031
3032static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
3033static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
3034 { .irq = 28 },
3035 { .irq = -1 }
3036};
3037
3038static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
3039 { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
3040};
3041
3042static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = {
3043 {
3044 .pa_start = 0x5d000000,
3045 .pa_end = 0x5d00007f,
3046 .flags = ADDR_TYPE_RT,
3047 },
3048 { }
3049};
3050
3051/* l3_main -> iva mmu */
3052static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
3053 .master = &omap3xxx_l3_main_hwmod,
3054 .slave = &omap3xxx_mmu_iva_hwmod,
3055 .addr = omap3xxx_mmu_iva_addrs,
3056 .user = OCP_USER_MPU | OCP_USER_SDMA,
3057};
3058
3059static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
3060 .name = "mmu_iva",
3061 .class = &omap3xxx_mmu_hwmod_class,
3062 .mpu_irqs = omap3xxx_mmu_iva_irqs,
3063 .rst_lines = omap3xxx_mmu_iva_resets,
3064 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
3065 .main_clk = "iva2_ck",
3066 .prcm = {
3067 .omap2 = {
3068 .module_offs = OMAP3430_IVA2_MOD,
3069 },
3070 },
3071 .dev_attr = &mmu_iva_dev_attr,
3072 .flags = HWMOD_NO_IDLEST,
3073};
3074
3075#endif
3076
844a3b63
PW
3077/* l4_per -> gpio4 */
3078static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
3079 {
3080 .pa_start = 0x49054000,
3081 .pa_end = 0x490541ff,
3082 .flags = ADDR_TYPE_RT
70034d38 3083 },
844a3b63 3084 { }
70034d38
VC
3085};
3086
844a3b63
PW
3087static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
3088 .master = &omap3xxx_l4_per_hwmod,
3089 .slave = &omap3xxx_gpio4_hwmod,
3090 .addr = omap3xxx_gpio4_addrs,
3091 .user = OCP_USER_MPU | OCP_USER_SDMA,
01438ab6
MK
3092};
3093
844a3b63
PW
3094/* l4_per -> gpio5 */
3095static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
3096 {
3097 .pa_start = 0x49056000,
3098 .pa_end = 0x490561ff,
3099 .flags = ADDR_TYPE_RT
3100 },
3101 { }
01438ab6
MK
3102};
3103
844a3b63
PW
3104static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
3105 .master = &omap3xxx_l4_per_hwmod,
3106 .slave = &omap3xxx_gpio5_hwmod,
3107 .addr = omap3xxx_gpio5_addrs,
3108 .user = OCP_USER_MPU | OCP_USER_SDMA,
01438ab6
MK
3109};
3110
844a3b63
PW
3111/* l4_per -> gpio6 */
3112static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
3113 {
3114 .pa_start = 0x49058000,
3115 .pa_end = 0x490581ff,
3116 .flags = ADDR_TYPE_RT
01438ab6 3117 },
844a3b63 3118 { }
01438ab6
MK
3119};
3120
844a3b63
PW
3121static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
3122 .master = &omap3xxx_l4_per_hwmod,
3123 .slave = &omap3xxx_gpio6_hwmod,
3124 .addr = omap3xxx_gpio6_addrs,
3125 .user = OCP_USER_MPU | OCP_USER_SDMA,
01438ab6
MK
3126};
3127
844a3b63
PW
3128/* dma_system -> L3 */
3129static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
3130 .master = &omap3xxx_dma_system_hwmod,
3131 .slave = &omap3xxx_l3_main_hwmod,
3132 .clk = "core_l3_ick",
3133 .user = OCP_USER_MPU | OCP_USER_SDMA,
01438ab6
MK
3134};
3135
844a3b63
PW
3136static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
3137 {
3138 .pa_start = 0x48056000,
3139 .pa_end = 0x48056fff,
3140 .flags = ADDR_TYPE_RT
01438ab6 3141 },
844a3b63 3142 { }
01438ab6
MK
3143};
3144
844a3b63
PW
3145/* l4_cfg -> dma_system */
3146static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
3147 .master = &omap3xxx_l4_core_hwmod,
3148 .slave = &omap3xxx_dma_system_hwmod,
3149 .clk = "core_l4_ick",
3150 .addr = omap3xxx_dma_system_addrs,
3151 .user = OCP_USER_MPU | OCP_USER_SDMA,
d3442726
TG
3152};
3153
844a3b63
PW
3154static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
3155 {
3156 .name = "mpu",
3157 .pa_start = 0x48074000,
3158 .pa_end = 0x480740ff,
3159 .flags = ADDR_TYPE_RT
3160 },
3161 { }
d3442726
TG
3162};
3163
844a3b63
PW
3164/* l4_core -> mcbsp1 */
3165static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
3166 .master = &omap3xxx_l4_core_hwmod,
3167 .slave = &omap3xxx_mcbsp1_hwmod,
3168 .clk = "mcbsp1_ick",
3169 .addr = omap3xxx_mcbsp1_addrs,
3170 .user = OCP_USER_MPU | OCP_USER_SDMA,
d3442726
TG
3171};
3172
844a3b63
PW
3173static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
3174 {
3175 .name = "mpu",
3176 .pa_start = 0x49022000,
3177 .pa_end = 0x490220ff,
3178 .flags = ADDR_TYPE_RT
3179 },
3180 { }
d3442726
TG
3181};
3182
844a3b63
PW
3183/* l4_per -> mcbsp2 */
3184static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
3185 .master = &omap3xxx_l4_per_hwmod,
3186 .slave = &omap3xxx_mcbsp2_hwmod,
3187 .clk = "mcbsp2_ick",
3188 .addr = omap3xxx_mcbsp2_addrs,
3189 .user = OCP_USER_MPU | OCP_USER_SDMA,
d3442726
TG
3190};
3191
844a3b63
PW
3192static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
3193 {
3194 .name = "mpu",
3195 .pa_start = 0x49024000,
3196 .pa_end = 0x490240ff,
3197 .flags = ADDR_TYPE_RT
3198 },
3199 { }
d3442726
TG
3200};
3201
844a3b63
PW
3202/* l4_per -> mcbsp3 */
3203static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
3204 .master = &omap3xxx_l4_per_hwmod,
3205 .slave = &omap3xxx_mcbsp3_hwmod,
3206 .clk = "mcbsp3_ick",
3207 .addr = omap3xxx_mcbsp3_addrs,
3208 .user = OCP_USER_MPU | OCP_USER_SDMA,
a52e2ab6
PW
3209};
3210
844a3b63
PW
3211static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
3212 {
3213 .name = "mpu",
3214 .pa_start = 0x49026000,
3215 .pa_end = 0x490260ff,
3216 .flags = ADDR_TYPE_RT
a52e2ab6 3217 },
844a3b63 3218 { }
a52e2ab6
PW
3219};
3220
844a3b63
PW
3221/* l4_per -> mcbsp4 */
3222static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
3223 .master = &omap3xxx_l4_per_hwmod,
3224 .slave = &omap3xxx_mcbsp4_hwmod,
3225 .clk = "mcbsp4_ick",
3226 .addr = omap3xxx_mcbsp4_addrs,
3227 .user = OCP_USER_MPU | OCP_USER_SDMA,
d3442726
TG
3228};
3229
844a3b63
PW
3230static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
3231 {
3232 .name = "mpu",
3233 .pa_start = 0x48096000,
3234 .pa_end = 0x480960ff,
3235 .flags = ADDR_TYPE_RT
3236 },
3237 { }
3238};
b163605e 3239
844a3b63
PW
3240/* l4_core -> mcbsp5 */
3241static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
3242 .master = &omap3xxx_l4_core_hwmod,
3243 .slave = &omap3xxx_mcbsp5_hwmod,
3244 .clk = "mcbsp5_ick",
3245 .addr = omap3xxx_mcbsp5_addrs,
3246 .user = OCP_USER_MPU | OCP_USER_SDMA,
d3442726
TG
3247};
3248
844a3b63
PW
3249static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
3250 {
3251 .name = "sidetone",
3252 .pa_start = 0x49028000,
3253 .pa_end = 0x490280ff,
3254 .flags = ADDR_TYPE_RT
3255 },
3256 { }
d3442726
TG
3257};
3258
844a3b63
PW
3259/* l4_per -> mcbsp2_sidetone */
3260static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3261 .master = &omap3xxx_l4_per_hwmod,
3262 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
3263 .clk = "mcbsp2_ick",
3264 .addr = omap3xxx_mcbsp2_sidetone_addrs,
3265 .user = OCP_USER_MPU,
b163605e
PW
3266};
3267
844a3b63
PW
3268static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3269 {
3270 .name = "sidetone",
3271 .pa_start = 0x4902A000,
3272 .pa_end = 0x4902A0ff,
3273 .flags = ADDR_TYPE_RT
3274 },
3275 { }
a52e2ab6
PW
3276};
3277
844a3b63
PW
3278/* l4_per -> mcbsp3_sidetone */
3279static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3280 .master = &omap3xxx_l4_per_hwmod,
3281 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
3282 .clk = "mcbsp3_ick",
3283 .addr = omap3xxx_mcbsp3_sidetone_addrs,
3284 .user = OCP_USER_MPU,
a52e2ab6
PW
3285};
3286
844a3b63
PW
3287static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3288 {
3289 .pa_start = 0x48094000,
3290 .pa_end = 0x480941ff,
3291 .flags = ADDR_TYPE_RT,
d3442726 3292 },
844a3b63 3293 { }
d3442726
TG
3294};
3295
844a3b63
PW
3296/* l4_core -> mailbox */
3297static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3298 .master = &omap3xxx_l4_core_hwmod,
3299 .slave = &omap3xxx_mailbox_hwmod,
3300 .addr = omap3xxx_mailbox_addrs,
3301 .user = OCP_USER_MPU | OCP_USER_SDMA,
3302};
b163605e 3303
844a3b63
PW
3304/* l4 core -> mcspi1 interface */
3305static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3306 .master = &omap3xxx_l4_core_hwmod,
3307 .slave = &omap34xx_mcspi1,
3308 .clk = "mcspi1_ick",
3309 .addr = omap2_mcspi1_addr_space,
3310 .user = OCP_USER_MPU | OCP_USER_SDMA,
b163605e
PW
3311};
3312
844a3b63
PW
3313/* l4 core -> mcspi2 interface */
3314static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3315 .master = &omap3xxx_l4_core_hwmod,
3316 .slave = &omap34xx_mcspi2,
3317 .clk = "mcspi2_ick",
3318 .addr = omap2_mcspi2_addr_space,
3319 .user = OCP_USER_MPU | OCP_USER_SDMA,
b163605e
PW
3320};
3321
844a3b63
PW
3322/* l4 core -> mcspi3 interface */
3323static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3324 .master = &omap3xxx_l4_core_hwmod,
3325 .slave = &omap34xx_mcspi3,
3326 .clk = "mcspi3_ick",
3327 .addr = omap2430_mcspi3_addr_space,
3328 .user = OCP_USER_MPU | OCP_USER_SDMA,
b163605e
PW
3329};
3330
844a3b63
PW
3331/* l4 core -> mcspi4 interface */
3332static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3333 {
3334 .pa_start = 0x480ba000,
3335 .pa_end = 0x480ba0ff,
3336 .flags = ADDR_TYPE_RT,
d3442726 3337 },
844a3b63
PW
3338 { }
3339};
3340
3341static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3342 .master = &omap3xxx_l4_core_hwmod,
3343 .slave = &omap34xx_mcspi4,
3344 .clk = "mcspi4_ick",
3345 .addr = omap34xx_mcspi4_addr_space,
3346 .user = OCP_USER_MPU | OCP_USER_SDMA,
d3442726
TG
3347};
3348
de231388
KM
3349static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3350 .master = &omap3xxx_usb_host_hs_hwmod,
3351 .slave = &omap3xxx_l3_main_hwmod,
3352 .clk = "core_l3_ick",
3353 .user = OCP_USER_MPU,
3354};
3355
de231388
KM
3356static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3357 {
3358 .name = "uhh",
3359 .pa_start = 0x48064000,
3360 .pa_end = 0x480643ff,
3361 .flags = ADDR_TYPE_RT
3362 },
3363 {
3364 .name = "ohci",
3365 .pa_start = 0x48064400,
3366 .pa_end = 0x480647ff,
3367 },
3368 {
3369 .name = "ehci",
3370 .pa_start = 0x48064800,
3371 .pa_end = 0x48064cff,
3372 },
3373 {}
3374};
3375
3376static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3377 .master = &omap3xxx_l4_core_hwmod,
3378 .slave = &omap3xxx_usb_host_hs_hwmod,
3379 .clk = "usbhost_ick",
3380 .addr = omap3xxx_usb_host_hs_addrs,
3381 .user = OCP_USER_MPU | OCP_USER_SDMA,
3382};
3383
de231388
KM
3384static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3385 {
3386 .name = "tll",
3387 .pa_start = 0x48062000,
3388 .pa_end = 0x48062fff,
3389 .flags = ADDR_TYPE_RT
3390 },
3391 {}
3392};
3393
3394static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3395 .master = &omap3xxx_l4_core_hwmod,
3396 .slave = &omap3xxx_usb_tll_hs_hwmod,
3397 .clk = "usbtll_ick",
3398 .addr = omap3xxx_usb_tll_hs_addrs,
3399 .user = OCP_USER_MPU | OCP_USER_SDMA,
3400};
3401
45a4bb06
PW
3402/* l4_core -> hdq1w interface */
3403static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3404 .master = &omap3xxx_l4_core_hwmod,
3405 .slave = &omap3xxx_hdq1w_hwmod,
3406 .clk = "hdq_ick",
3407 .addr = omap2_hdq1w_addr_space,
3408 .user = OCP_USER_MPU | OCP_USER_SDMA,
3409 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3410};
3411
c8d82ff6
VH
3412/* l4_wkup -> 32ksync_counter */
3413static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3414 {
3415 .pa_start = 0x48320000,
3416 .pa_end = 0x4832001f,
3417 .flags = ADDR_TYPE_RT
3418 },
3419 { }
3420};
3421
49484a60
AM
3422static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
3423 {
3424 .pa_start = 0x6e000000,
3425 .pa_end = 0x6e000fff,
3426 .flags = ADDR_TYPE_RT
3427 },
3428 { }
3429};
3430
c8d82ff6
VH
3431static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3432 .master = &omap3xxx_l4_wkup_hwmod,
3433 .slave = &omap3xxx_counter_32k_hwmod,
3434 .clk = "omap_32ksync_ick",
3435 .addr = omap3xxx_counter_32k_addrs,
3436 .user = OCP_USER_MPU | OCP_USER_SDMA,
3437};
3438
31ba8808
MG
3439/* am35xx has Davinci MDIO & EMAC */
3440static struct omap_hwmod_class am35xx_mdio_class = {
3441 .name = "davinci_mdio",
3442};
3443
3444static struct omap_hwmod am35xx_mdio_hwmod = {
3445 .name = "davinci_mdio",
3446 .class = &am35xx_mdio_class,
3447 .flags = HWMOD_NO_IDLEST,
3448};
3449
3450/*
3451 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3452 * but this will probably require some additional hwmod core support,
3453 * so is left as a future to-do item.
3454 */
3455static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3456 .master = &am35xx_mdio_hwmod,
3457 .slave = &omap3xxx_l3_main_hwmod,
3458 .clk = "emac_fck",
3459 .user = OCP_USER_MPU,
3460};
3461
3462static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
3463 {
3464 .pa_start = AM35XX_IPSS_MDIO_BASE,
3465 .pa_end = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
3466 .flags = ADDR_TYPE_RT,
3467 },
3468 { }
3469};
3470
3471/* l4_core -> davinci mdio */
3472/*
3473 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3474 * but this will probably require some additional hwmod core support,
3475 * so is left as a future to-do item.
3476 */
3477static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3478 .master = &omap3xxx_l4_core_hwmod,
3479 .slave = &am35xx_mdio_hwmod,
3480 .clk = "emac_fck",
3481 .addr = am35xx_mdio_addrs,
3482 .user = OCP_USER_MPU,
3483};
3484
3485static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
7d7e1eba
TL
3486 { .name = "rxthresh", .irq = 67 + OMAP_INTC_START, },
3487 { .name = "rx_pulse", .irq = 68 + OMAP_INTC_START, },
3488 { .name = "tx_pulse", .irq = 69 + OMAP_INTC_START },
3489 { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START },
3490 { .irq = -1 },
31ba8808
MG
3491};
3492
3493static struct omap_hwmod_class am35xx_emac_class = {
3494 .name = "davinci_emac",
3495};
3496
3497static struct omap_hwmod am35xx_emac_hwmod = {
3498 .name = "davinci_emac",
3499 .mpu_irqs = am35xx_emac_mpu_irqs,
3500 .class = &am35xx_emac_class,
3501 .flags = HWMOD_NO_IDLEST,
3502};
3503
3504/* l3_core -> davinci emac interface */
3505/*
3506 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3507 * but this will probably require some additional hwmod core support,
3508 * so is left as a future to-do item.
3509 */
3510static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3511 .master = &am35xx_emac_hwmod,
3512 .slave = &omap3xxx_l3_main_hwmod,
3513 .clk = "emac_ick",
3514 .user = OCP_USER_MPU,
3515};
3516
3517static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
3518 {
3519 .pa_start = AM35XX_IPSS_EMAC_BASE,
3520 .pa_end = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
3521 .flags = ADDR_TYPE_RT,
3522 },
3523 { }
3524};
3525
3526/* l4_core -> davinci emac */
3527/*
3528 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3529 * but this will probably require some additional hwmod core support,
3530 * so is left as a future to-do item.
3531 */
3532static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3533 .master = &omap3xxx_l4_core_hwmod,
3534 .slave = &am35xx_emac_hwmod,
3535 .clk = "emac_ick",
3536 .addr = am35xx_emac_addrs,
3537 .user = OCP_USER_MPU,
3538};
3539
49484a60
AM
3540static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
3541 .master = &omap3xxx_l3_main_hwmod,
3542 .slave = &omap3xxx_gpmc_hwmod,
3543 .clk = "core_l3_ick",
3544 .addr = omap3xxx_gpmc_addrs,
3545 .user = OCP_USER_MPU | OCP_USER_SDMA,
3546};
3547
0a78c5c5
PW
3548static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3549 &omap3xxx_l3_main__l4_core,
3550 &omap3xxx_l3_main__l4_per,
3551 &omap3xxx_mpu__l3_main,
c7dad45f 3552 &omap3xxx_l3_main__l4_debugss,
0a78c5c5
PW
3553 &omap3xxx_l4_core__l4_wkup,
3554 &omap3xxx_l4_core__mmc3,
3555 &omap3_l4_core__uart1,
3556 &omap3_l4_core__uart2,
3557 &omap3_l4_per__uart3,
3558 &omap3_l4_core__i2c1,
3559 &omap3_l4_core__i2c2,
3560 &omap3_l4_core__i2c3,
3561 &omap3xxx_l4_wkup__l4_sec,
3562 &omap3xxx_l4_wkup__timer1,
3563 &omap3xxx_l4_per__timer2,
3564 &omap3xxx_l4_per__timer3,
3565 &omap3xxx_l4_per__timer4,
3566 &omap3xxx_l4_per__timer5,
3567 &omap3xxx_l4_per__timer6,
3568 &omap3xxx_l4_per__timer7,
3569 &omap3xxx_l4_per__timer8,
3570 &omap3xxx_l4_per__timer9,
3571 &omap3xxx_l4_core__timer10,
3572 &omap3xxx_l4_core__timer11,
3573 &omap3xxx_l4_wkup__wd_timer2,
3574 &omap3xxx_l4_wkup__gpio1,
3575 &omap3xxx_l4_per__gpio2,
3576 &omap3xxx_l4_per__gpio3,
3577 &omap3xxx_l4_per__gpio4,
3578 &omap3xxx_l4_per__gpio5,
3579 &omap3xxx_l4_per__gpio6,
3580 &omap3xxx_dma_system__l3,
3581 &omap3xxx_l4_core__dma_system,
3582 &omap3xxx_l4_core__mcbsp1,
3583 &omap3xxx_l4_per__mcbsp2,
3584 &omap3xxx_l4_per__mcbsp3,
3585 &omap3xxx_l4_per__mcbsp4,
3586 &omap3xxx_l4_core__mcbsp5,
3587 &omap3xxx_l4_per__mcbsp2_sidetone,
3588 &omap3xxx_l4_per__mcbsp3_sidetone,
3589 &omap34xx_l4_core__mcspi1,
3590 &omap34xx_l4_core__mcspi2,
3591 &omap34xx_l4_core__mcspi3,
3592 &omap34xx_l4_core__mcspi4,
c8d82ff6 3593 &omap3xxx_l4_wkup__counter_32k,
49484a60 3594 &omap3xxx_l3_main__gpmc,
d6504acd
PW
3595 NULL,
3596};
3597
0a78c5c5
PW
3598/* GP-only hwmod links */
3599static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
3600 &omap3xxx_l4_sec__timer12,
91a36bdb
AK
3601 NULL
3602};
3603
0a78c5c5
PW
3604/* 3430ES1-only hwmod links */
3605static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3606 &omap3430es1_dss__l3,
3607 &omap3430es1_l4_core__dss,
d6504acd
PW
3608 NULL
3609};
3610
0a78c5c5
PW
3611/* 3430ES2+-only hwmod links */
3612static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3613 &omap3xxx_dss__l3,
3614 &omap3xxx_l4_core__dss,
3615 &omap3xxx_usbhsotg__l3,
3616 &omap3xxx_l4_core__usbhsotg,
3617 &omap3xxx_usb_host_hs__l3_main_2,
3618 &omap3xxx_l4_core__usb_host_hs,
3619 &omap3xxx_l4_core__usb_tll_hs,
d6504acd
PW
3620 NULL
3621};
870ea2b8 3622
0a78c5c5
PW
3623/* <= 3430ES3-only hwmod links */
3624static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3625 &omap3xxx_l4_core__pre_es3_mmc1,
3626 &omap3xxx_l4_core__pre_es3_mmc2,
a52e2ab6
PW
3627 NULL
3628};
3629
0a78c5c5
PW
3630/* 3430ES3+-only hwmod links */
3631static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3632 &omap3xxx_l4_core__es3plus_mmc1,
3633 &omap3xxx_l4_core__es3plus_mmc2,
a52e2ab6
PW
3634 NULL
3635};
3636
0a78c5c5
PW
3637/* 34xx-only hwmod links (all ES revisions) */
3638static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3639 &omap3xxx_l3__iva,
3640 &omap34xx_l4_core__sr1,
3641 &omap34xx_l4_core__sr2,
3642 &omap3xxx_l4_core__mailbox,
45a4bb06 3643 &omap3xxx_l4_core__hdq1w,
8f993a01 3644 &omap3xxx_sad2d__l3,
5486474c
PW
3645 &omap3xxx_l4_core__mmu_isp,
3646#ifdef CONFIG_OMAP_IOMMU_IVA2
3647 &omap3xxx_l3_main__mmu_iva,
3648#endif
d6504acd
PW
3649 NULL
3650};
273ff8c3 3651
0a78c5c5
PW
3652/* 36xx-only hwmod links (all ES revisions) */
3653static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3654 &omap3xxx_l3__iva,
3655 &omap36xx_l4_per__uart4,
3656 &omap3xxx_dss__l3,
3657 &omap3xxx_l4_core__dss,
3658 &omap36xx_l4_core__sr1,
3659 &omap36xx_l4_core__sr2,
3660 &omap3xxx_usbhsotg__l3,
3661 &omap3xxx_l4_core__usbhsotg,
3662 &omap3xxx_l4_core__mailbox,
3663 &omap3xxx_usb_host_hs__l3_main_2,
3664 &omap3xxx_l4_core__usb_host_hs,
3665 &omap3xxx_l4_core__usb_tll_hs,
3666 &omap3xxx_l4_core__es3plus_mmc1,
3667 &omap3xxx_l4_core__es3plus_mmc2,
45a4bb06 3668 &omap3xxx_l4_core__hdq1w,
8f993a01 3669 &omap3xxx_sad2d__l3,
5486474c
PW
3670 &omap3xxx_l4_core__mmu_isp,
3671#ifdef CONFIG_OMAP_IOMMU_IVA2
3672 &omap3xxx_l3_main__mmu_iva,
3673#endif
d6504acd
PW
3674 NULL
3675};
3676
0a78c5c5
PW
3677static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3678 &omap3xxx_dss__l3,
3679 &omap3xxx_l4_core__dss,
3680 &am35xx_usbhsotg__l3,
3681 &am35xx_l4_core__usbhsotg,
3682 &am35xx_l4_core__uart4,
3683 &omap3xxx_usb_host_hs__l3_main_2,
3684 &omap3xxx_l4_core__usb_host_hs,
3685 &omap3xxx_l4_core__usb_tll_hs,
3686 &omap3xxx_l4_core__es3plus_mmc1,
3687 &omap3xxx_l4_core__es3plus_mmc2,
b1a923d0 3688 &omap3xxx_l4_core__hdq1w,
31ba8808
MG
3689 &am35xx_mdio__l3,
3690 &am35xx_l4_core__mdio,
3691 &am35xx_emac__l3,
3692 &am35xx_l4_core__emac,
d6504acd 3693 NULL
7359154e
PW
3694};
3695
0a78c5c5
PW
3696static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3697 &omap3xxx_l4_core__dss_dispc,
3698 &omap3xxx_l4_core__dss_dsi1,
3699 &omap3xxx_l4_core__dss_rfbi,
3700 &omap3xxx_l4_core__dss_venc,
1d2f56c8
IY
3701 NULL
3702};
3703
7359154e
PW
3704int __init omap3xxx_hwmod_init(void)
3705{
d6504acd 3706 int r;
0a78c5c5 3707 struct omap_hwmod_ocp_if **h = NULL;
d6504acd
PW
3708 unsigned int rev;
3709
9ebfd285
KH
3710 omap_hwmod_init();
3711
0a78c5c5
PW
3712 /* Register hwmod links common to all OMAP3 */
3713 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
ace90216 3714 if (r < 0)
d6504acd
PW
3715 return r;
3716
0a78c5c5 3717 /* Register GP-only hwmod links. */
91a36bdb 3718 if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
0a78c5c5 3719 r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
91a36bdb
AK
3720 if (r < 0)
3721 return r;
3722 }
3723
d6504acd
PW
3724 rev = omap_rev();
3725
3726 /*
0a78c5c5 3727 * Register hwmod links common to individual OMAP3 families, all
d6504acd
PW
3728 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3729 * All possible revisions should be included in this conditional.
3730 */
3731 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3732 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3733 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
0a78c5c5 3734 h = omap34xx_hwmod_ocp_ifs;
68a88b98 3735 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
0a78c5c5 3736 h = am35xx_hwmod_ocp_ifs;
d6504acd
PW
3737 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3738 rev == OMAP3630_REV_ES1_2) {
0a78c5c5 3739 h = omap36xx_hwmod_ocp_ifs;
d6504acd
PW
3740 } else {
3741 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3742 return -EINVAL;
c09fcc43 3743 }
d6504acd 3744
0a78c5c5 3745 r = omap_hwmod_register_links(h);
ace90216 3746 if (r < 0)
d6504acd
PW
3747 return r;
3748
3749 /*
0a78c5c5 3750 * Register hwmod links specific to certain ES levels of a
d6504acd
PW
3751 * particular family of silicon (e.g., 34xx ES1.0)
3752 */
3753 h = NULL;
3754 if (rev == OMAP3430_REV_ES1_0) {
0a78c5c5 3755 h = omap3430es1_hwmod_ocp_ifs;
d6504acd
PW
3756 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3757 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3758 rev == OMAP3430_REV_ES3_1_2) {
0a78c5c5 3759 h = omap3430es2plus_hwmod_ocp_ifs;
c09fcc43 3760 }
d6504acd 3761
a52e2ab6 3762 if (h) {
0a78c5c5 3763 r = omap_hwmod_register_links(h);
a52e2ab6
PW
3764 if (r < 0)
3765 return r;
3766 }
3767
3768 h = NULL;
3769 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3770 rev == OMAP3430_REV_ES2_1) {
0a78c5c5 3771 h = omap3430_pre_es3_hwmod_ocp_ifs;
a52e2ab6
PW
3772 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3773 rev == OMAP3430_REV_ES3_1_2) {
0a78c5c5 3774 h = omap3430_es3plus_hwmod_ocp_ifs;
c09fcc43 3775 }
a52e2ab6 3776
d6504acd 3777 if (h)
0a78c5c5 3778 r = omap_hwmod_register_links(h);
1d2f56c8
IY
3779 if (r < 0)
3780 return r;
3781
3782 /*
3783 * DSS code presumes that dss_core hwmod is handled first,
3784 * _before_ any other DSS related hwmods so register common
0a78c5c5
PW
3785 * DSS hwmod links last to ensure that dss_core is already
3786 * registered. Otherwise some change things may happen, for
3787 * ex. if dispc is handled before dss_core and DSS is enabled
3788 * in bootloader DISPC will be reset with outputs enabled
3789 * which sometimes leads to unrecoverable L3 error. XXX The
3790 * long-term fix to this is to ensure hwmods are set up in
3791 * dependency order in the hwmod core code.
1d2f56c8 3792 */
0a78c5c5 3793 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
d6504acd
PW
3794
3795 return r;
7359154e 3796}
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