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6913952f AM |
1 | /* |
2 | * Copyright (C) 2013 Texas Instruments Incorporated | |
3 | * | |
4 | * Hwmod present only in AM43x and those that differ other than register | |
5 | * offsets as compared to AM335x. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation version 2. | |
10 | * | |
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
12 | * kind, whether express or implied; without even the implied warranty | |
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/platform_data/gpio-omap.h> | |
18 | #include <linux/platform_data/spi-omap2-mcspi.h> | |
19 | #include "omap_hwmod.h" | |
20 | #include "omap_hwmod_33xx_43xx_common_data.h" | |
21 | #include "prcm43xx.h" | |
509efaf3 | 22 | #include "omap_hwmod_common_data.h" |
89122aa8 | 23 | #include "hdq1w.h" |
509efaf3 | 24 | |
6913952f AM |
25 | |
26 | /* IP blocks */ | |
fabbe6df DG |
27 | static struct omap_hwmod am43xx_emif_hwmod = { |
28 | .name = "emif", | |
29 | .class = &am33xx_emif_hwmod_class, | |
30 | .clkdm_name = "emif_clkdm", | |
31 | .flags = HWMOD_INIT_NO_IDLE, | |
32 | .main_clk = "dpll_ddr_m2_ck", | |
33 | .prcm = { | |
34 | .omap4 = { | |
35 | .clkctrl_offs = AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET, | |
36 | .modulemode = MODULEMODE_SWCTRL, | |
37 | }, | |
38 | }, | |
39 | }; | |
40 | ||
6913952f AM |
41 | static struct omap_hwmod am43xx_l4_hs_hwmod = { |
42 | .name = "l4_hs", | |
43 | .class = &am33xx_l4_hwmod_class, | |
44 | .clkdm_name = "l3_clkdm", | |
45 | .flags = HWMOD_INIT_NO_IDLE, | |
46 | .main_clk = "l4hs_gclk", | |
47 | .prcm = { | |
48 | .omap4 = { | |
49 | .clkctrl_offs = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET, | |
50 | .modulemode = MODULEMODE_SWCTRL, | |
51 | }, | |
52 | }, | |
53 | }; | |
54 | ||
55 | static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = { | |
56 | { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, | |
57 | }; | |
58 | ||
59 | static struct omap_hwmod am43xx_wkup_m3_hwmod = { | |
60 | .name = "wkup_m3", | |
61 | .class = &am33xx_wkup_m3_hwmod_class, | |
62 | .clkdm_name = "l4_wkup_aon_clkdm", | |
63 | /* Keep hardreset asserted */ | |
64 | .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST, | |
65 | .main_clk = "sys_clkin_ck", | |
66 | .prcm = { | |
67 | .omap4 = { | |
68 | .clkctrl_offs = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET, | |
69 | .rstctrl_offs = AM43XX_RM_WKUP_RSTCTRL_OFFSET, | |
70 | .rstst_offs = AM43XX_RM_WKUP_RSTST_OFFSET, | |
71 | .modulemode = MODULEMODE_SWCTRL, | |
72 | }, | |
73 | }, | |
74 | .rst_lines = am33xx_wkup_m3_resets, | |
75 | .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets), | |
76 | }; | |
77 | ||
78 | static struct omap_hwmod am43xx_control_hwmod = { | |
79 | .name = "control", | |
80 | .class = &am33xx_control_hwmod_class, | |
81 | .clkdm_name = "l4_wkup_clkdm", | |
82 | .flags = HWMOD_INIT_NO_IDLE, | |
83 | .main_clk = "sys_clkin_ck", | |
84 | .prcm = { | |
85 | .omap4 = { | |
86 | .clkctrl_offs = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET, | |
87 | .modulemode = MODULEMODE_SWCTRL, | |
88 | }, | |
89 | }, | |
90 | }; | |
91 | ||
92 | static struct omap_hwmod_opt_clk gpio0_opt_clks[] = { | |
93 | { .role = "dbclk", .clk = "gpio0_dbclk" }, | |
94 | }; | |
95 | ||
96 | static struct omap_hwmod am43xx_gpio0_hwmod = { | |
97 | .name = "gpio1", | |
98 | .class = &am33xx_gpio_hwmod_class, | |
99 | .clkdm_name = "l4_wkup_clkdm", | |
100 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
101 | .main_clk = "sys_clkin_ck", | |
102 | .prcm = { | |
103 | .omap4 = { | |
104 | .clkctrl_offs = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET, | |
105 | .modulemode = MODULEMODE_SWCTRL, | |
106 | }, | |
107 | }, | |
108 | .opt_clks = gpio0_opt_clks, | |
109 | .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks), | |
110 | .dev_attr = &gpio_dev_attr, | |
111 | }; | |
112 | ||
113 | static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = { | |
114 | .rev_offs = 0x0, | |
115 | .sysc_offs = 0x4, | |
116 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
117 | .idlemodes = (SIDLE_FORCE | SIDLE_NO), | |
118 | .sysc_fields = &omap_hwmod_sysc_type1, | |
119 | }; | |
120 | ||
121 | static struct omap_hwmod_class am43xx_synctimer_hwmod_class = { | |
122 | .name = "synctimer", | |
123 | .sysc = &am43xx_synctimer_sysc, | |
124 | }; | |
125 | ||
126 | static struct omap_hwmod am43xx_synctimer_hwmod = { | |
127 | .name = "counter_32k", | |
128 | .class = &am43xx_synctimer_hwmod_class, | |
129 | .clkdm_name = "l4_wkup_aon_clkdm", | |
130 | .flags = HWMOD_SWSUP_SIDLE, | |
131 | .main_clk = "synctimer_32kclk", | |
132 | .prcm = { | |
133 | .omap4 = { | |
134 | .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, | |
135 | .modulemode = MODULEMODE_SWCTRL, | |
136 | }, | |
137 | }, | |
138 | }; | |
139 | ||
140 | static struct omap_hwmod am43xx_timer8_hwmod = { | |
141 | .name = "timer8", | |
142 | .class = &am33xx_timer_hwmod_class, | |
143 | .clkdm_name = "l4ls_clkdm", | |
144 | .main_clk = "timer8_fck", | |
145 | .prcm = { | |
146 | .omap4 = { | |
147 | .clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET, | |
148 | .modulemode = MODULEMODE_SWCTRL, | |
149 | }, | |
150 | }, | |
151 | }; | |
152 | ||
153 | static struct omap_hwmod am43xx_timer9_hwmod = { | |
154 | .name = "timer9", | |
155 | .class = &am33xx_timer_hwmod_class, | |
156 | .clkdm_name = "l4ls_clkdm", | |
157 | .main_clk = "timer9_fck", | |
158 | .prcm = { | |
159 | .omap4 = { | |
160 | .clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET, | |
161 | .modulemode = MODULEMODE_SWCTRL, | |
162 | }, | |
163 | }, | |
164 | }; | |
165 | ||
166 | static struct omap_hwmod am43xx_timer10_hwmod = { | |
167 | .name = "timer10", | |
168 | .class = &am33xx_timer_hwmod_class, | |
169 | .clkdm_name = "l4ls_clkdm", | |
170 | .main_clk = "timer10_fck", | |
171 | .prcm = { | |
172 | .omap4 = { | |
173 | .clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET, | |
174 | .modulemode = MODULEMODE_SWCTRL, | |
175 | }, | |
176 | }, | |
177 | }; | |
178 | ||
179 | static struct omap_hwmod am43xx_timer11_hwmod = { | |
180 | .name = "timer11", | |
181 | .class = &am33xx_timer_hwmod_class, | |
182 | .clkdm_name = "l4ls_clkdm", | |
183 | .main_clk = "timer11_fck", | |
184 | .prcm = { | |
185 | .omap4 = { | |
186 | .clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET, | |
187 | .modulemode = MODULEMODE_SWCTRL, | |
188 | }, | |
189 | }, | |
190 | }; | |
191 | ||
192 | static struct omap_hwmod am43xx_epwmss3_hwmod = { | |
193 | .name = "epwmss3", | |
194 | .class = &am33xx_epwmss_hwmod_class, | |
195 | .clkdm_name = "l4ls_clkdm", | |
196 | .main_clk = "l4ls_gclk", | |
197 | .prcm = { | |
198 | .omap4 = { | |
199 | .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET, | |
200 | .modulemode = MODULEMODE_SWCTRL, | |
201 | }, | |
202 | }, | |
203 | }; | |
204 | ||
205 | static struct omap_hwmod am43xx_ehrpwm3_hwmod = { | |
206 | .name = "ehrpwm3", | |
207 | .class = &am33xx_ehrpwm_hwmod_class, | |
208 | .clkdm_name = "l4ls_clkdm", | |
209 | .main_clk = "l4ls_gclk", | |
210 | }; | |
211 | ||
212 | static struct omap_hwmod am43xx_epwmss4_hwmod = { | |
213 | .name = "epwmss4", | |
214 | .class = &am33xx_epwmss_hwmod_class, | |
215 | .clkdm_name = "l4ls_clkdm", | |
216 | .main_clk = "l4ls_gclk", | |
217 | .prcm = { | |
218 | .omap4 = { | |
219 | .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET, | |
220 | .modulemode = MODULEMODE_SWCTRL, | |
221 | }, | |
222 | }, | |
223 | }; | |
224 | ||
225 | static struct omap_hwmod am43xx_ehrpwm4_hwmod = { | |
226 | .name = "ehrpwm4", | |
227 | .class = &am33xx_ehrpwm_hwmod_class, | |
228 | .clkdm_name = "l4ls_clkdm", | |
229 | .main_clk = "l4ls_gclk", | |
230 | }; | |
231 | ||
232 | static struct omap_hwmod am43xx_epwmss5_hwmod = { | |
233 | .name = "epwmss5", | |
234 | .class = &am33xx_epwmss_hwmod_class, | |
235 | .clkdm_name = "l4ls_clkdm", | |
236 | .main_clk = "l4ls_gclk", | |
237 | .prcm = { | |
238 | .omap4 = { | |
239 | .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET, | |
240 | .modulemode = MODULEMODE_SWCTRL, | |
241 | }, | |
242 | }, | |
243 | }; | |
244 | ||
245 | static struct omap_hwmod am43xx_ehrpwm5_hwmod = { | |
246 | .name = "ehrpwm5", | |
247 | .class = &am33xx_ehrpwm_hwmod_class, | |
248 | .clkdm_name = "l4ls_clkdm", | |
249 | .main_clk = "l4ls_gclk", | |
250 | }; | |
251 | ||
252 | static struct omap_hwmod am43xx_spi2_hwmod = { | |
253 | .name = "spi2", | |
254 | .class = &am33xx_spi_hwmod_class, | |
255 | .clkdm_name = "l4ls_clkdm", | |
256 | .main_clk = "dpll_per_m2_div4_ck", | |
257 | .prcm = { | |
258 | .omap4 = { | |
259 | .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET, | |
260 | .modulemode = MODULEMODE_SWCTRL, | |
261 | }, | |
262 | }, | |
263 | .dev_attr = &mcspi_attrib, | |
264 | }; | |
265 | ||
266 | static struct omap_hwmod am43xx_spi3_hwmod = { | |
267 | .name = "spi3", | |
268 | .class = &am33xx_spi_hwmod_class, | |
269 | .clkdm_name = "l4ls_clkdm", | |
270 | .main_clk = "dpll_per_m2_div4_ck", | |
271 | .prcm = { | |
272 | .omap4 = { | |
273 | .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET, | |
274 | .modulemode = MODULEMODE_SWCTRL, | |
275 | }, | |
276 | }, | |
277 | .dev_attr = &mcspi_attrib, | |
278 | }; | |
279 | ||
280 | static struct omap_hwmod am43xx_spi4_hwmod = { | |
281 | .name = "spi4", | |
282 | .class = &am33xx_spi_hwmod_class, | |
283 | .clkdm_name = "l4ls_clkdm", | |
284 | .main_clk = "dpll_per_m2_div4_ck", | |
285 | .prcm = { | |
286 | .omap4 = { | |
287 | .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET, | |
288 | .modulemode = MODULEMODE_SWCTRL, | |
289 | }, | |
290 | }, | |
291 | .dev_attr = &mcspi_attrib, | |
292 | }; | |
293 | ||
294 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { | |
295 | { .role = "dbclk", .clk = "gpio4_dbclk" }, | |
296 | }; | |
297 | ||
298 | static struct omap_hwmod am43xx_gpio4_hwmod = { | |
299 | .name = "gpio5", | |
300 | .class = &am33xx_gpio_hwmod_class, | |
301 | .clkdm_name = "l4ls_clkdm", | |
302 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
303 | .main_clk = "l4ls_gclk", | |
304 | .prcm = { | |
305 | .omap4 = { | |
306 | .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET, | |
307 | .modulemode = MODULEMODE_SWCTRL, | |
308 | }, | |
309 | }, | |
310 | .opt_clks = gpio4_opt_clks, | |
311 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
312 | .dev_attr = &gpio_dev_attr, | |
313 | }; | |
314 | ||
315 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { | |
316 | { .role = "dbclk", .clk = "gpio5_dbclk" }, | |
317 | }; | |
318 | ||
319 | static struct omap_hwmod am43xx_gpio5_hwmod = { | |
320 | .name = "gpio6", | |
321 | .class = &am33xx_gpio_hwmod_class, | |
322 | .clkdm_name = "l4ls_clkdm", | |
323 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
324 | .main_clk = "l4ls_gclk", | |
325 | .prcm = { | |
326 | .omap4 = { | |
327 | .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET, | |
328 | .modulemode = MODULEMODE_SWCTRL, | |
329 | }, | |
330 | }, | |
331 | .opt_clks = gpio5_opt_clks, | |
332 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
333 | .dev_attr = &gpio_dev_attr, | |
334 | }; | |
335 | ||
facfbc49 GC |
336 | static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = { |
337 | .name = "ocp2scp", | |
338 | }; | |
339 | ||
340 | static struct omap_hwmod am43xx_ocp2scp0_hwmod = { | |
341 | .name = "ocp2scp0", | |
342 | .class = &am43xx_ocp2scp_hwmod_class, | |
343 | .clkdm_name = "l4ls_clkdm", | |
344 | .main_clk = "l4ls_gclk", | |
345 | .prcm = { | |
346 | .omap4 = { | |
347 | .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET, | |
348 | .modulemode = MODULEMODE_SWCTRL, | |
349 | }, | |
350 | }, | |
351 | }; | |
352 | ||
353 | static struct omap_hwmod am43xx_ocp2scp1_hwmod = { | |
354 | .name = "ocp2scp1", | |
355 | .class = &am43xx_ocp2scp_hwmod_class, | |
356 | .clkdm_name = "l4ls_clkdm", | |
357 | .main_clk = "l4ls_gclk", | |
358 | .prcm = { | |
359 | .omap4 = { | |
360 | .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET, | |
361 | .modulemode = MODULEMODE_SWCTRL, | |
362 | }, | |
363 | }, | |
364 | }; | |
365 | ||
366 | static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = { | |
367 | .rev_offs = 0x0000, | |
368 | .sysc_offs = 0x0010, | |
369 | .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE | | |
370 | SYSC_HAS_SIDLEMODE), | |
371 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
372 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | | |
373 | MSTANDBY_NO | MSTANDBY_SMART | | |
374 | MSTANDBY_SMART_WKUP), | |
375 | .sysc_fields = &omap_hwmod_sysc_type2, | |
376 | }; | |
377 | ||
378 | static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = { | |
379 | .name = "usb_otg_ss", | |
380 | .sysc = &am43xx_usb_otg_ss_sysc, | |
381 | }; | |
382 | ||
383 | static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = { | |
384 | .name = "usb_otg_ss0", | |
385 | .class = &am43xx_usb_otg_ss_hwmod_class, | |
386 | .clkdm_name = "l3s_clkdm", | |
387 | .main_clk = "l3s_gclk", | |
388 | .prcm = { | |
389 | .omap4 = { | |
390 | .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET, | |
391 | .modulemode = MODULEMODE_SWCTRL, | |
392 | }, | |
393 | }, | |
394 | }; | |
395 | ||
396 | static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = { | |
397 | .name = "usb_otg_ss1", | |
398 | .class = &am43xx_usb_otg_ss_hwmod_class, | |
399 | .clkdm_name = "l3s_clkdm", | |
400 | .main_clk = "l3s_gclk", | |
401 | .prcm = { | |
402 | .omap4 = { | |
403 | .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET, | |
404 | .modulemode = MODULEMODE_SWCTRL, | |
405 | }, | |
406 | }, | |
407 | }; | |
408 | ||
70b0d5f5 SP |
409 | static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = { |
410 | .sysc_offs = 0x0010, | |
411 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
412 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
413 | SIDLE_SMART_WKUP), | |
414 | .sysc_fields = &omap_hwmod_sysc_type2, | |
415 | }; | |
416 | ||
417 | static struct omap_hwmod_class am43xx_qspi_hwmod_class = { | |
418 | .name = "qspi", | |
419 | .sysc = &am43xx_qspi_sysc, | |
420 | }; | |
421 | ||
422 | static struct omap_hwmod am43xx_qspi_hwmod = { | |
423 | .name = "qspi", | |
424 | .class = &am43xx_qspi_hwmod_class, | |
425 | .clkdm_name = "l3s_clkdm", | |
426 | .main_clk = "l3s_gclk", | |
427 | .prcm = { | |
428 | .omap4 = { | |
429 | .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET, | |
430 | .modulemode = MODULEMODE_SWCTRL, | |
431 | }, | |
432 | }, | |
433 | }; | |
434 | ||
d1180f69 V |
435 | /* |
436 | * 'adc/tsc' class | |
437 | * TouchScreen Controller (Analog-To-Digital Converter) | |
438 | */ | |
439 | static struct omap_hwmod_class_sysconfig am43xx_adc_tsc_sysc = { | |
440 | .rev_offs = 0x00, | |
441 | .sysc_offs = 0x10, | |
442 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
443 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
444 | SIDLE_SMART_WKUP), | |
445 | .sysc_fields = &omap_hwmod_sysc_type2, | |
446 | }; | |
447 | ||
448 | static struct omap_hwmod_class am43xx_adc_tsc_hwmod_class = { | |
449 | .name = "adc_tsc", | |
450 | .sysc = &am43xx_adc_tsc_sysc, | |
451 | }; | |
452 | ||
453 | static struct omap_hwmod am43xx_adc_tsc_hwmod = { | |
454 | .name = "adc_tsc", | |
455 | .class = &am43xx_adc_tsc_hwmod_class, | |
456 | .clkdm_name = "l3s_tsc_clkdm", | |
457 | .main_clk = "adc_tsc_fck", | |
458 | .prcm = { | |
459 | .omap4 = { | |
460 | .clkctrl_offs = AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET, | |
461 | .modulemode = MODULEMODE_SWCTRL, | |
462 | }, | |
463 | }, | |
464 | }; | |
465 | ||
509efaf3 SP |
466 | /* dss */ |
467 | ||
468 | static struct omap_hwmod am43xx_dss_core_hwmod = { | |
469 | .name = "dss_core", | |
470 | .class = &omap2_dss_hwmod_class, | |
471 | .clkdm_name = "dss_clkdm", | |
472 | .main_clk = "disp_clk", | |
473 | .prcm = { | |
474 | .omap4 = { | |
475 | .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET, | |
476 | .modulemode = MODULEMODE_SWCTRL, | |
477 | }, | |
478 | }, | |
479 | }; | |
480 | ||
481 | /* dispc */ | |
482 | ||
f734a9b3 | 483 | static struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = { |
509efaf3 SP |
484 | .manager_count = 1, |
485 | .has_framedonetv_irq = 0 | |
486 | }; | |
487 | ||
488 | static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = { | |
489 | .rev_offs = 0x0000, | |
490 | .sysc_offs = 0x0010, | |
491 | .syss_offs = 0x0014, | |
492 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET | | |
493 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
494 | SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE), | |
495 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
496 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
497 | .sysc_fields = &omap_hwmod_sysc_type1, | |
498 | }; | |
499 | ||
500 | static struct omap_hwmod_class am43xx_dispc_hwmod_class = { | |
501 | .name = "dispc", | |
502 | .sysc = &am43xx_dispc_sysc, | |
503 | }; | |
504 | ||
505 | static struct omap_hwmod am43xx_dss_dispc_hwmod = { | |
506 | .name = "dss_dispc", | |
507 | .class = &am43xx_dispc_hwmod_class, | |
508 | .clkdm_name = "dss_clkdm", | |
509 | .main_clk = "disp_clk", | |
510 | .prcm = { | |
511 | .omap4 = { | |
512 | .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET, | |
513 | }, | |
514 | }, | |
515 | .dev_attr = &am43xx_dss_dispc_dev_attr, | |
ccfb24e3 | 516 | .parent_hwmod = &am43xx_dss_core_hwmod, |
509efaf3 SP |
517 | }; |
518 | ||
519 | /* rfbi */ | |
520 | ||
521 | static struct omap_hwmod am43xx_dss_rfbi_hwmod = { | |
522 | .name = "dss_rfbi", | |
523 | .class = &omap2_rfbi_hwmod_class, | |
524 | .clkdm_name = "dss_clkdm", | |
525 | .main_clk = "disp_clk", | |
526 | .prcm = { | |
527 | .omap4 = { | |
528 | .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET, | |
529 | }, | |
530 | }, | |
ccfb24e3 | 531 | .parent_hwmod = &am43xx_dss_core_hwmod, |
509efaf3 SP |
532 | }; |
533 | ||
89122aa8 SP |
534 | /* HDQ1W */ |
535 | static struct omap_hwmod_class_sysconfig am43xx_hdq1w_sysc = { | |
536 | .rev_offs = 0x0000, | |
537 | .sysc_offs = 0x0014, | |
538 | .syss_offs = 0x0018, | |
539 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
540 | .sysc_fields = &omap_hwmod_sysc_type1, | |
541 | }; | |
542 | ||
543 | static struct omap_hwmod_class am43xx_hdq1w_hwmod_class = { | |
544 | .name = "hdq1w", | |
545 | .sysc = &am43xx_hdq1w_sysc, | |
546 | .reset = &omap_hdq1w_reset, | |
547 | }; | |
548 | ||
549 | static struct omap_hwmod am43xx_hdq1w_hwmod = { | |
550 | .name = "hdq1w", | |
551 | .class = &am43xx_hdq1w_hwmod_class, | |
552 | .clkdm_name = "l4ls_clkdm", | |
553 | .prcm = { | |
554 | .omap4 = { | |
555 | .clkctrl_offs = AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET, | |
556 | .modulemode = MODULEMODE_SWCTRL, | |
557 | }, | |
558 | }, | |
559 | }; | |
560 | ||
9a557062 BP |
561 | static struct omap_hwmod_class_sysconfig am43xx_vpfe_sysc = { |
562 | .rev_offs = 0x0, | |
563 | .sysc_offs = 0x104, | |
564 | .sysc_flags = SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE, | |
565 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
566 | MSTANDBY_FORCE | MSTANDBY_SMART | MSTANDBY_NO), | |
567 | .sysc_fields = &omap_hwmod_sysc_type2, | |
568 | }; | |
569 | ||
570 | static struct omap_hwmod_class am43xx_vpfe_hwmod_class = { | |
571 | .name = "vpfe", | |
572 | .sysc = &am43xx_vpfe_sysc, | |
573 | }; | |
574 | ||
575 | static struct omap_hwmod am43xx_vpfe0_hwmod = { | |
576 | .name = "vpfe0", | |
577 | .class = &am43xx_vpfe_hwmod_class, | |
578 | .clkdm_name = "l3s_clkdm", | |
579 | .prcm = { | |
580 | .omap4 = { | |
581 | .modulemode = MODULEMODE_SWCTRL, | |
582 | .clkctrl_offs = AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET, | |
583 | }, | |
584 | }, | |
585 | }; | |
586 | ||
587 | static struct omap_hwmod am43xx_vpfe1_hwmod = { | |
588 | .name = "vpfe1", | |
589 | .class = &am43xx_vpfe_hwmod_class, | |
590 | .clkdm_name = "l3s_clkdm", | |
591 | .prcm = { | |
592 | .omap4 = { | |
593 | .modulemode = MODULEMODE_SWCTRL, | |
594 | .clkctrl_offs = AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET, | |
595 | }, | |
596 | }, | |
597 | }; | |
598 | ||
6913952f | 599 | /* Interfaces */ |
fabbe6df DG |
600 | static struct omap_hwmod_ocp_if am43xx_l3_main__emif = { |
601 | .master = &am33xx_l3_main_hwmod, | |
602 | .slave = &am43xx_emif_hwmod, | |
603 | .clk = "dpll_core_m4_ck", | |
604 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
605 | }; | |
606 | ||
6913952f AM |
607 | static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = { |
608 | .master = &am33xx_l3_main_hwmod, | |
609 | .slave = &am43xx_l4_hs_hwmod, | |
610 | .clk = "l3s_gclk", | |
611 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
612 | }; | |
613 | ||
614 | static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = { | |
615 | .master = &am43xx_wkup_m3_hwmod, | |
616 | .slave = &am33xx_l4_wkup_hwmod, | |
617 | .clk = "sys_clkin_ck", | |
618 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
619 | }; | |
620 | ||
621 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = { | |
622 | .master = &am33xx_l4_wkup_hwmod, | |
623 | .slave = &am43xx_wkup_m3_hwmod, | |
624 | .clk = "sys_clkin_ck", | |
625 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
626 | }; | |
627 | ||
628 | static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = { | |
629 | .master = &am33xx_l3_main_hwmod, | |
630 | .slave = &am33xx_pruss_hwmod, | |
631 | .clk = "dpll_core_m4_ck", | |
632 | .user = OCP_USER_MPU, | |
633 | }; | |
634 | ||
635 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = { | |
636 | .master = &am33xx_l4_wkup_hwmod, | |
637 | .slave = &am33xx_smartreflex0_hwmod, | |
638 | .clk = "sys_clkin_ck", | |
639 | .user = OCP_USER_MPU, | |
640 | }; | |
641 | ||
642 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = { | |
643 | .master = &am33xx_l4_wkup_hwmod, | |
644 | .slave = &am33xx_smartreflex1_hwmod, | |
645 | .clk = "sys_clkin_ck", | |
646 | .user = OCP_USER_MPU, | |
647 | }; | |
648 | ||
649 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = { | |
650 | .master = &am33xx_l4_wkup_hwmod, | |
651 | .slave = &am43xx_control_hwmod, | |
652 | .clk = "sys_clkin_ck", | |
653 | .user = OCP_USER_MPU, | |
654 | }; | |
655 | ||
656 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__i2c1 = { | |
657 | .master = &am33xx_l4_wkup_hwmod, | |
658 | .slave = &am33xx_i2c1_hwmod, | |
659 | .clk = "sys_clkin_ck", | |
660 | .user = OCP_USER_MPU, | |
661 | }; | |
662 | ||
663 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = { | |
664 | .master = &am33xx_l4_wkup_hwmod, | |
665 | .slave = &am43xx_gpio0_hwmod, | |
666 | .clk = "sys_clkin_ck", | |
667 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
668 | }; | |
669 | ||
d1180f69 V |
670 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = { |
671 | .master = &am33xx_l4_wkup_hwmod, | |
672 | .slave = &am43xx_adc_tsc_hwmod, | |
673 | .clk = "dpll_core_m4_div2_ck", | |
674 | .user = OCP_USER_MPU, | |
675 | }; | |
676 | ||
6913952f AM |
677 | static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = { |
678 | .master = &am43xx_l4_hs_hwmod, | |
679 | .slave = &am33xx_cpgmac0_hwmod, | |
680 | .clk = "cpsw_125mhz_gclk", | |
681 | .user = OCP_USER_MPU, | |
682 | }; | |
683 | ||
684 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = { | |
685 | .master = &am33xx_l4_wkup_hwmod, | |
686 | .slave = &am33xx_timer1_hwmod, | |
687 | .clk = "sys_clkin_ck", | |
688 | .user = OCP_USER_MPU, | |
689 | }; | |
690 | ||
691 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__uart1 = { | |
692 | .master = &am33xx_l4_wkup_hwmod, | |
693 | .slave = &am33xx_uart1_hwmod, | |
694 | .clk = "sys_clkin_ck", | |
695 | .user = OCP_USER_MPU, | |
696 | }; | |
697 | ||
698 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = { | |
699 | .master = &am33xx_l4_wkup_hwmod, | |
700 | .slave = &am33xx_wd_timer1_hwmod, | |
701 | .clk = "sys_clkin_ck", | |
702 | .user = OCP_USER_MPU, | |
703 | }; | |
704 | ||
705 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = { | |
706 | .master = &am33xx_l4_wkup_hwmod, | |
707 | .slave = &am43xx_synctimer_hwmod, | |
708 | .clk = "sys_clkin_ck", | |
709 | .user = OCP_USER_MPU, | |
710 | }; | |
711 | ||
712 | static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = { | |
713 | .master = &am33xx_l4_ls_hwmod, | |
714 | .slave = &am43xx_timer8_hwmod, | |
715 | .clk = "l4ls_gclk", | |
716 | .user = OCP_USER_MPU, | |
717 | }; | |
718 | ||
719 | static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = { | |
720 | .master = &am33xx_l4_ls_hwmod, | |
721 | .slave = &am43xx_timer9_hwmod, | |
722 | .clk = "l4ls_gclk", | |
723 | .user = OCP_USER_MPU, | |
724 | }; | |
725 | ||
726 | static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = { | |
727 | .master = &am33xx_l4_ls_hwmod, | |
728 | .slave = &am43xx_timer10_hwmod, | |
729 | .clk = "l4ls_gclk", | |
730 | .user = OCP_USER_MPU, | |
731 | }; | |
732 | ||
733 | static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = { | |
734 | .master = &am33xx_l4_ls_hwmod, | |
735 | .slave = &am43xx_timer11_hwmod, | |
736 | .clk = "l4ls_gclk", | |
737 | .user = OCP_USER_MPU, | |
738 | }; | |
739 | ||
740 | static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = { | |
741 | .master = &am33xx_l4_ls_hwmod, | |
742 | .slave = &am43xx_epwmss3_hwmod, | |
743 | .clk = "l4ls_gclk", | |
744 | .user = OCP_USER_MPU, | |
745 | }; | |
746 | ||
747 | static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = { | |
748 | .master = &am43xx_epwmss3_hwmod, | |
749 | .slave = &am43xx_ehrpwm3_hwmod, | |
750 | .clk = "l4ls_gclk", | |
751 | .user = OCP_USER_MPU, | |
752 | }; | |
753 | ||
754 | static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = { | |
755 | .master = &am33xx_l4_ls_hwmod, | |
756 | .slave = &am43xx_epwmss4_hwmod, | |
757 | .clk = "l4ls_gclk", | |
758 | .user = OCP_USER_MPU, | |
759 | }; | |
760 | ||
761 | static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = { | |
762 | .master = &am43xx_epwmss4_hwmod, | |
763 | .slave = &am43xx_ehrpwm4_hwmod, | |
764 | .clk = "l4ls_gclk", | |
765 | .user = OCP_USER_MPU, | |
766 | }; | |
767 | ||
768 | static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = { | |
769 | .master = &am33xx_l4_ls_hwmod, | |
770 | .slave = &am43xx_epwmss5_hwmod, | |
771 | .clk = "l4ls_gclk", | |
772 | .user = OCP_USER_MPU, | |
773 | }; | |
774 | ||
775 | static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = { | |
776 | .master = &am43xx_epwmss5_hwmod, | |
777 | .slave = &am43xx_ehrpwm5_hwmod, | |
778 | .clk = "l4ls_gclk", | |
779 | .user = OCP_USER_MPU, | |
780 | }; | |
781 | ||
782 | static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = { | |
783 | .master = &am33xx_l4_ls_hwmod, | |
784 | .slave = &am43xx_spi2_hwmod, | |
785 | .clk = "l4ls_gclk", | |
786 | .user = OCP_USER_MPU, | |
787 | }; | |
788 | ||
789 | static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = { | |
790 | .master = &am33xx_l4_ls_hwmod, | |
791 | .slave = &am43xx_spi3_hwmod, | |
792 | .clk = "l4ls_gclk", | |
793 | .user = OCP_USER_MPU, | |
794 | }; | |
795 | ||
796 | static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = { | |
797 | .master = &am33xx_l4_ls_hwmod, | |
798 | .slave = &am43xx_spi4_hwmod, | |
799 | .clk = "l4ls_gclk", | |
800 | .user = OCP_USER_MPU, | |
801 | }; | |
802 | ||
803 | static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = { | |
804 | .master = &am33xx_l4_ls_hwmod, | |
805 | .slave = &am43xx_gpio4_hwmod, | |
806 | .clk = "l4ls_gclk", | |
807 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
808 | }; | |
809 | ||
810 | static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = { | |
811 | .master = &am33xx_l4_ls_hwmod, | |
812 | .slave = &am43xx_gpio5_hwmod, | |
813 | .clk = "l4ls_gclk", | |
814 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
815 | }; | |
816 | ||
facfbc49 GC |
817 | static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = { |
818 | .master = &am33xx_l4_ls_hwmod, | |
819 | .slave = &am43xx_ocp2scp0_hwmod, | |
820 | .clk = "l4ls_gclk", | |
821 | .user = OCP_USER_MPU, | |
822 | }; | |
823 | ||
824 | static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = { | |
825 | .master = &am33xx_l4_ls_hwmod, | |
826 | .slave = &am43xx_ocp2scp1_hwmod, | |
827 | .clk = "l4ls_gclk", | |
828 | .user = OCP_USER_MPU, | |
829 | }; | |
830 | ||
831 | static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = { | |
832 | .master = &am33xx_l3_s_hwmod, | |
833 | .slave = &am43xx_usb_otg_ss0_hwmod, | |
834 | .clk = "l3s_gclk", | |
835 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
836 | }; | |
837 | ||
838 | static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = { | |
839 | .master = &am33xx_l3_s_hwmod, | |
840 | .slave = &am43xx_usb_otg_ss1_hwmod, | |
841 | .clk = "l3s_gclk", | |
842 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
843 | }; | |
844 | ||
70b0d5f5 SP |
845 | static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = { |
846 | .master = &am33xx_l3_s_hwmod, | |
847 | .slave = &am43xx_qspi_hwmod, | |
848 | .clk = "l3s_gclk", | |
849 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
850 | }; | |
851 | ||
509efaf3 SP |
852 | static struct omap_hwmod_ocp_if am43xx_dss__l3_main = { |
853 | .master = &am43xx_dss_core_hwmod, | |
854 | .slave = &am33xx_l3_main_hwmod, | |
855 | .clk = "l3_gclk", | |
856 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
857 | }; | |
858 | ||
859 | static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = { | |
860 | .master = &am33xx_l4_ls_hwmod, | |
861 | .slave = &am43xx_dss_core_hwmod, | |
862 | .clk = "l4ls_gclk", | |
863 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
864 | }; | |
865 | ||
866 | static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = { | |
867 | .master = &am33xx_l4_ls_hwmod, | |
868 | .slave = &am43xx_dss_dispc_hwmod, | |
869 | .clk = "l4ls_gclk", | |
870 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
871 | }; | |
872 | ||
873 | static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = { | |
874 | .master = &am33xx_l4_ls_hwmod, | |
875 | .slave = &am43xx_dss_rfbi_hwmod, | |
876 | .clk = "l4ls_gclk", | |
877 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
878 | }; | |
879 | ||
89122aa8 SP |
880 | static struct omap_hwmod_ocp_if am43xx_l4_ls__hdq1w = { |
881 | .master = &am33xx_l4_ls_hwmod, | |
882 | .slave = &am43xx_hdq1w_hwmod, | |
883 | .clk = "l4ls_gclk", | |
884 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
885 | }; | |
886 | ||
9a557062 BP |
887 | static struct omap_hwmod_ocp_if am43xx_l3__vpfe0 = { |
888 | .master = &am43xx_vpfe0_hwmod, | |
889 | .slave = &am33xx_l3_main_hwmod, | |
890 | .clk = "l3_gclk", | |
891 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
892 | }; | |
893 | ||
894 | static struct omap_hwmod_ocp_if am43xx_l3__vpfe1 = { | |
895 | .master = &am43xx_vpfe1_hwmod, | |
896 | .slave = &am33xx_l3_main_hwmod, | |
897 | .clk = "l3_gclk", | |
898 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
899 | }; | |
900 | ||
901 | static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe0 = { | |
902 | .master = &am33xx_l4_ls_hwmod, | |
903 | .slave = &am43xx_vpfe0_hwmod, | |
904 | .clk = "l4ls_gclk", | |
905 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
906 | }; | |
907 | ||
908 | static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe1 = { | |
909 | .master = &am33xx_l4_ls_hwmod, | |
910 | .slave = &am43xx_vpfe1_hwmod, | |
911 | .clk = "l4ls_gclk", | |
912 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
913 | }; | |
914 | ||
6913952f AM |
915 | static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { |
916 | &am33xx_l4_wkup__synctimer, | |
917 | &am43xx_l4_ls__timer8, | |
918 | &am43xx_l4_ls__timer9, | |
919 | &am43xx_l4_ls__timer10, | |
920 | &am43xx_l4_ls__timer11, | |
921 | &am43xx_l4_ls__epwmss3, | |
922 | &am43xx_epwmss3__ehrpwm3, | |
923 | &am43xx_l4_ls__epwmss4, | |
924 | &am43xx_epwmss4__ehrpwm4, | |
925 | &am43xx_l4_ls__epwmss5, | |
926 | &am43xx_epwmss5__ehrpwm5, | |
927 | &am43xx_l4_ls__mcspi2, | |
928 | &am43xx_l4_ls__mcspi3, | |
929 | &am43xx_l4_ls__mcspi4, | |
930 | &am43xx_l4_ls__gpio4, | |
931 | &am43xx_l4_ls__gpio5, | |
932 | &am43xx_l3_main__pruss, | |
933 | &am33xx_mpu__l3_main, | |
934 | &am33xx_mpu__prcm, | |
935 | &am33xx_l3_s__l4_ls, | |
936 | &am33xx_l3_s__l4_wkup, | |
937 | &am43xx_l3_main__l4_hs, | |
938 | &am33xx_l3_main__l3_s, | |
939 | &am33xx_l3_main__l3_instr, | |
940 | &am33xx_l3_main__gfx, | |
941 | &am33xx_l3_s__l3_main, | |
fabbe6df | 942 | &am43xx_l3_main__emif, |
6913952f AM |
943 | &am33xx_pruss__l3_main, |
944 | &am43xx_wkup_m3__l4_wkup, | |
945 | &am33xx_gfx__l3_main, | |
946 | &am43xx_l4_wkup__wkup_m3, | |
947 | &am43xx_l4_wkup__control, | |
948 | &am43xx_l4_wkup__smartreflex0, | |
949 | &am43xx_l4_wkup__smartreflex1, | |
950 | &am43xx_l4_wkup__uart1, | |
951 | &am43xx_l4_wkup__timer1, | |
952 | &am43xx_l4_wkup__i2c1, | |
953 | &am43xx_l4_wkup__gpio0, | |
954 | &am43xx_l4_wkup__wd_timer1, | |
d1180f69 | 955 | &am43xx_l4_wkup__adc_tsc, |
70b0d5f5 | 956 | &am43xx_l3_s__qspi, |
6913952f AM |
957 | &am33xx_l4_per__dcan0, |
958 | &am33xx_l4_per__dcan1, | |
959 | &am33xx_l4_per__gpio1, | |
960 | &am33xx_l4_per__gpio2, | |
961 | &am33xx_l4_per__gpio3, | |
962 | &am33xx_l4_per__i2c2, | |
963 | &am33xx_l4_per__i2c3, | |
964 | &am33xx_l4_per__mailbox, | |
965 | &am33xx_l4_ls__mcasp0, | |
966 | &am33xx_l4_ls__mcasp1, | |
967 | &am33xx_l4_ls__mmc0, | |
968 | &am33xx_l4_ls__mmc1, | |
969 | &am33xx_l3_s__mmc2, | |
970 | &am33xx_l4_ls__timer2, | |
971 | &am33xx_l4_ls__timer3, | |
972 | &am33xx_l4_ls__timer4, | |
973 | &am33xx_l4_ls__timer5, | |
974 | &am33xx_l4_ls__timer6, | |
975 | &am33xx_l4_ls__timer7, | |
976 | &am33xx_l3_main__tpcc, | |
977 | &am33xx_l4_ls__uart2, | |
978 | &am33xx_l4_ls__uart3, | |
979 | &am33xx_l4_ls__uart4, | |
980 | &am33xx_l4_ls__uart5, | |
981 | &am33xx_l4_ls__uart6, | |
64b61067 | 982 | &am33xx_l4_ls__spinlock, |
6913952f AM |
983 | &am33xx_l4_ls__elm, |
984 | &am33xx_l4_ls__epwmss0, | |
985 | &am33xx_epwmss0__ecap0, | |
986 | &am33xx_epwmss0__eqep0, | |
987 | &am33xx_epwmss0__ehrpwm0, | |
988 | &am33xx_l4_ls__epwmss1, | |
989 | &am33xx_epwmss1__ecap1, | |
990 | &am33xx_epwmss1__eqep1, | |
991 | &am33xx_epwmss1__ehrpwm1, | |
992 | &am33xx_l4_ls__epwmss2, | |
993 | &am33xx_epwmss2__ecap2, | |
994 | &am33xx_epwmss2__eqep2, | |
995 | &am33xx_epwmss2__ehrpwm2, | |
996 | &am33xx_l3_s__gpmc, | |
997 | &am33xx_l4_ls__mcspi0, | |
998 | &am33xx_l4_ls__mcspi1, | |
999 | &am33xx_l3_main__tptc0, | |
1000 | &am33xx_l3_main__tptc1, | |
1001 | &am33xx_l3_main__tptc2, | |
1002 | &am33xx_l3_main__ocmc, | |
1003 | &am43xx_l4_hs__cpgmac0, | |
1004 | &am33xx_cpgmac0__mdio, | |
1005 | &am33xx_l3_main__sha0, | |
1006 | &am33xx_l3_main__aes0, | |
facfbc49 GC |
1007 | &am43xx_l4_ls__ocp2scp0, |
1008 | &am43xx_l4_ls__ocp2scp1, | |
1009 | &am43xx_l3_s__usbotgss0, | |
1010 | &am43xx_l3_s__usbotgss1, | |
509efaf3 SP |
1011 | &am43xx_dss__l3_main, |
1012 | &am43xx_l4_ls__dss, | |
1013 | &am43xx_l4_ls__dss_dispc, | |
1014 | &am43xx_l4_ls__dss_rfbi, | |
89122aa8 | 1015 | &am43xx_l4_ls__hdq1w, |
9a557062 BP |
1016 | &am43xx_l3__vpfe0, |
1017 | &am43xx_l3__vpfe1, | |
1018 | &am43xx_l4_ls__vpfe0, | |
1019 | &am43xx_l4_ls__vpfe1, | |
6913952f AM |
1020 | NULL, |
1021 | }; | |
1022 | ||
4321dc8d K |
1023 | static struct omap_hwmod_ocp_if *am43xx_rtc_hwmod_ocp_ifs[] __initdata = { |
1024 | &am33xx_l4_wkup__rtc, | |
1025 | NULL, | |
1026 | }; | |
1027 | ||
6913952f AM |
1028 | int __init am43xx_hwmod_init(void) |
1029 | { | |
4321dc8d K |
1030 | int ret; |
1031 | ||
6913952f AM |
1032 | omap_hwmod_am43xx_reg(); |
1033 | omap_hwmod_init(); | |
4321dc8d K |
1034 | ret = omap_hwmod_register_links(am43xx_hwmod_ocp_ifs); |
1035 | ||
1036 | if (!ret && of_machine_is_compatible("ti,am4372")) | |
1037 | ret = omap_hwmod_register_links(am43xx_rtc_hwmod_ocp_ifs); | |
1038 | ||
1039 | return ret; | |
6913952f | 1040 | } |