[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_43xx_data.c

/*
 * Copyright (C) 2013 Texas Instruments Incorporated
 *
 * Hwmod present only in AM43x and those that differ other than register
 * offsets as compared to AM335x.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

#include <linux/platform_data/gpio-omap.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include "omap_hwmod.h"
#include "omap_hwmod_33xx_43xx_common_data.h"
#include "prcm43xx.h"

/* IP blocks */
static struct omap_hwmod am43xx_l4_hs_hwmod = {
	.name		= "l4_hs",
	.class		= &am33xx_l4_hwmod_class,
	.clkdm_name	= "l3_clkdm",
	.flags		= HWMOD_INIT_NO_IDLE,
	.main_clk	= "l4hs_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
	{ .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
};

static struct omap_hwmod am43xx_wkup_m3_hwmod = {
	.name		= "wkup_m3",
	.class		= &am33xx_wkup_m3_hwmod_class,
	.clkdm_name	= "l4_wkup_aon_clkdm",
	/* Keep hardreset asserted */
	.flags		= HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
	.main_clk	= "sys_clkin_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
			.rstctrl_offs	= AM43XX_RM_WKUP_RSTCTRL_OFFSET,
			.rstst_offs	= AM43XX_RM_WKUP_RSTST_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
	.rst_lines	= am33xx_wkup_m3_resets,
	.rst_lines_cnt	= ARRAY_SIZE(am33xx_wkup_m3_resets),
};

static struct omap_hwmod am43xx_control_hwmod = {
	.name		= "control",
	.class		= &am33xx_control_hwmod_class,
	.clkdm_name	= "l4_wkup_clkdm",
	.flags		= HWMOD_INIT_NO_IDLE,
	.main_clk	= "sys_clkin_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
	{ .role = "dbclk", .clk = "gpio0_dbclk" },
};

static struct omap_hwmod am43xx_gpio0_hwmod = {
	.name		= "gpio1",
	.class		= &am33xx_gpio_hwmod_class,
	.clkdm_name	= "l4_wkup_clkdm",
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.main_clk	= "sys_clkin_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
	.opt_clks	= gpio0_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio0_opt_clks),
	.dev_attr	= &gpio_dev_attr,
};

static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
	.rev_offs	= 0x0,
	.sysc_offs	= 0x4,
	.sysc_flags	= SYSC_HAS_SIDLEMODE,
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
	.name	= "synctimer",
	.sysc	= &am43xx_synctimer_sysc,
};

static struct omap_hwmod am43xx_synctimer_hwmod = {
	.name		= "counter_32k",
	.class		= &am43xx_synctimer_hwmod_class,
	.clkdm_name	= "l4_wkup_aon_clkdm",
	.flags		= HWMOD_SWSUP_SIDLE,
	.main_clk	= "synctimer_32kclk",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod am43xx_timer8_hwmod = {
	.name		= "timer8",
	.class		= &am33xx_timer_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.main_clk	= "timer8_fck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod am43xx_timer9_hwmod = {
	.name		= "timer9",
	.class		= &am33xx_timer_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.main_clk	= "timer9_fck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod am43xx_timer10_hwmod = {
	.name		= "timer10",
	.class		= &am33xx_timer_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.main_clk	= "timer10_fck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod am43xx_timer11_hwmod = {
	.name		= "timer11",
	.class		= &am33xx_timer_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.main_clk	= "timer11_fck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod am43xx_epwmss3_hwmod = {
	.name		= "epwmss3",
	.class		= &am33xx_epwmss_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.main_clk	= "l4ls_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod am43xx_ehrpwm3_hwmod = {
	.name		= "ehrpwm3",
	.class		= &am33xx_ehrpwm_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.main_clk	= "l4ls_gclk",
};

static struct omap_hwmod am43xx_epwmss4_hwmod = {
	.name		= "epwmss4",
	.class		= &am33xx_epwmss_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.main_clk	= "l4ls_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod am43xx_ehrpwm4_hwmod = {
	.name		= "ehrpwm4",
	.class		= &am33xx_ehrpwm_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.main_clk	= "l4ls_gclk",
};

static struct omap_hwmod am43xx_epwmss5_hwmod = {
	.name		= "epwmss5",
	.class		= &am33xx_epwmss_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.main_clk	= "l4ls_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod am43xx_ehrpwm5_hwmod = {
	.name		= "ehrpwm5",
	.class		= &am33xx_ehrpwm_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.main_clk	= "l4ls_gclk",
};

static struct omap_hwmod am43xx_spi2_hwmod = {
	.name		= "spi2",
	.class		= &am33xx_spi_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.main_clk	= "dpll_per_m2_div4_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &mcspi_attrib,
};

static struct omap_hwmod am43xx_spi3_hwmod = {
	.name		= "spi3",
	.class		= &am33xx_spi_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.main_clk	= "dpll_per_m2_div4_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &mcspi_attrib,
};

static struct omap_hwmod am43xx_spi4_hwmod = {
	.name		= "spi4",
	.class		= &am33xx_spi_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.main_clk	= "dpll_per_m2_div4_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &mcspi_attrib,
};

static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
	{ .role = "dbclk", .clk = "gpio4_dbclk" },
};

static struct omap_hwmod am43xx_gpio4_hwmod = {
	.name		= "gpio5",
	.class		= &am33xx_gpio_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.main_clk	= "l4ls_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
	.opt_clks	= gpio4_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio4_opt_clks),
	.dev_attr	= &gpio_dev_attr,
};

static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
	{ .role = "dbclk", .clk = "gpio5_dbclk" },
};

static struct omap_hwmod am43xx_gpio5_hwmod = {
	.name		= "gpio6",
	.class		= &am33xx_gpio_hwmod_class,
	.clkdm_name	= "l4ls_clkdm",
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.main_clk	= "l4ls_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET,
			.modulemode   = MODULEMODE_SWCTRL,
		},
	},
	.opt_clks	= gpio5_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio5_opt_clks),
	.dev_attr	= &gpio_dev_attr,
};

/* Interfaces */
static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
	.master		= &am33xx_l3_main_hwmod,
	.slave		= &am43xx_l4_hs_hwmod,
	.clk		= "l3s_gclk",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = {
	.master		= &am43xx_wkup_m3_hwmod,
	.slave		= &am33xx_l4_wkup_hwmod,
	.clk		= "sys_clkin_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am43xx_wkup_m3_hwmod,
	.clk		= "sys_clkin_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
	.master		= &am33xx_l3_main_hwmod,
	.slave		= &am33xx_pruss_hwmod,
	.clk		= "dpll_core_m4_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am33xx_smartreflex0_hwmod,
	.clk		= "sys_clkin_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am33xx_smartreflex1_hwmod,
	.clk		= "sys_clkin_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am43xx_control_hwmod,
	.clk		= "sys_clkin_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am43xx_l4_wkup__i2c1 = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am33xx_i2c1_hwmod,
	.clk		= "sys_clkin_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am43xx_gpio0_hwmod,
	.clk		= "sys_clkin_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
	.master		= &am43xx_l4_hs_hwmod,
	.slave		= &am33xx_cpgmac0_hwmod,
	.clk		= "cpsw_125mhz_gclk",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am33xx_timer1_hwmod,
	.clk		= "sys_clkin_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am43xx_l4_wkup__uart1 = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am33xx_uart1_hwmod,
	.clk		= "sys_clkin_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am33xx_wd_timer1_hwmod,
	.clk		= "sys_clkin_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
	.master		= &am33xx_l4_wkup_hwmod,
	.slave		= &am43xx_synctimer_hwmod,
	.clk		= "sys_clkin_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
	.master		= &am33xx_l4_ls_hwmod,
	.slave		= &am43xx_timer8_hwmod,
	.clk		= "l4ls_gclk",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
	.master		= &am33xx_l4_ls_hwmod,
	.slave		= &am43xx_timer9_hwmod,
	.clk		= "l4ls_gclk",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
	.master		= &am33xx_l4_ls_hwmod,
	.slave		= &am43xx_timer10_hwmod,
	.clk		= "l4ls_gclk",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
	.master		= &am33xx_l4_ls_hwmod,
	.slave		= &am43xx_timer11_hwmod,
	.clk		= "l4ls_gclk",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
	.master		= &am33xx_l4_ls_hwmod,
	.slave		= &am43xx_epwmss3_hwmod,
	.clk		= "l4ls_gclk",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = {
	.master		= &am43xx_epwmss3_hwmod,
	.slave		= &am43xx_ehrpwm3_hwmod,
	.clk		= "l4ls_gclk",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
	.master		= &am33xx_l4_ls_hwmod,
	.slave		= &am43xx_epwmss4_hwmod,
	.clk		= "l4ls_gclk",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = {
	.master		= &am43xx_epwmss4_hwmod,
	.slave		= &am43xx_ehrpwm4_hwmod,
	.clk		= "l4ls_gclk",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
	.master		= &am33xx_l4_ls_hwmod,
	.slave		= &am43xx_epwmss5_hwmod,
	.clk		= "l4ls_gclk",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = {
	.master		= &am43xx_epwmss5_hwmod,
	.slave		= &am43xx_ehrpwm5_hwmod,
	.clk		= "l4ls_gclk",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
	.master		= &am33xx_l4_ls_hwmod,
	.slave		= &am43xx_spi2_hwmod,
	.clk		= "l4ls_gclk",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
	.master		= &am33xx_l4_ls_hwmod,
	.slave		= &am43xx_spi3_hwmod,
	.clk		= "l4ls_gclk",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
	.master		= &am33xx_l4_ls_hwmod,
	.slave		= &am43xx_spi4_hwmod,
	.clk		= "l4ls_gclk",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = {
	.master		= &am33xx_l4_ls_hwmod,
	.slave		= &am43xx_gpio4_hwmod,
	.clk		= "l4ls_gclk",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = {
	.master		= &am33xx_l4_ls_hwmod,
	.slave		= &am43xx_gpio5_hwmod,
	.clk		= "l4ls_gclk",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
	&am33xx_l4_wkup__synctimer,
	&am43xx_l4_ls__timer8,
	&am43xx_l4_ls__timer9,
	&am43xx_l4_ls__timer10,
	&am43xx_l4_ls__timer11,
	&am43xx_l4_ls__epwmss3,
	&am43xx_epwmss3__ehrpwm3,
	&am43xx_l4_ls__epwmss4,
	&am43xx_epwmss4__ehrpwm4,
	&am43xx_l4_ls__epwmss5,
	&am43xx_epwmss5__ehrpwm5,
	&am43xx_l4_ls__mcspi2,
	&am43xx_l4_ls__mcspi3,
	&am43xx_l4_ls__mcspi4,
	&am43xx_l4_ls__gpio4,
	&am43xx_l4_ls__gpio5,
	&am43xx_l3_main__pruss,
	&am33xx_mpu__l3_main,
	&am33xx_mpu__prcm,
	&am33xx_l3_s__l4_ls,
	&am33xx_l3_s__l4_wkup,
	&am43xx_l3_main__l4_hs,
	&am33xx_l3_main__l3_s,
	&am33xx_l3_main__l3_instr,
	&am33xx_l3_main__gfx,
	&am33xx_l3_s__l3_main,
	&am33xx_pruss__l3_main,
	&am43xx_wkup_m3__l4_wkup,
	&am33xx_gfx__l3_main,
	&am43xx_l4_wkup__wkup_m3,
	&am43xx_l4_wkup__control,
	&am43xx_l4_wkup__smartreflex0,
	&am43xx_l4_wkup__smartreflex1,
	&am43xx_l4_wkup__uart1,
	&am43xx_l4_wkup__timer1,
	&am43xx_l4_wkup__i2c1,
	&am43xx_l4_wkup__gpio0,
	&am43xx_l4_wkup__wd_timer1,
	&am33xx_l4_per__dcan0,
	&am33xx_l4_per__dcan1,
	&am33xx_l4_per__gpio1,
	&am33xx_l4_per__gpio2,
	&am33xx_l4_per__gpio3,
	&am33xx_l4_per__i2c2,
	&am33xx_l4_per__i2c3,
	&am33xx_l4_per__mailbox,
	&am33xx_l4_ls__mcasp0,
	&am33xx_l4_ls__mcasp1,
	&am33xx_l4_ls__mmc0,
	&am33xx_l4_ls__mmc1,
	&am33xx_l3_s__mmc2,
	&am33xx_l4_ls__timer2,
	&am33xx_l4_ls__timer3,
	&am33xx_l4_ls__timer4,
	&am33xx_l4_ls__timer5,
	&am33xx_l4_ls__timer6,
	&am33xx_l4_ls__timer7,
	&am33xx_l3_main__tpcc,
	&am33xx_l4_ls__uart2,
	&am33xx_l4_ls__uart3,
	&am33xx_l4_ls__uart4,
	&am33xx_l4_ls__uart5,
	&am33xx_l4_ls__uart6,
	&am33xx_l4_ls__elm,
	&am33xx_l4_ls__epwmss0,
	&am33xx_epwmss0__ecap0,
	&am33xx_epwmss0__eqep0,
	&am33xx_epwmss0__ehrpwm0,
	&am33xx_l4_ls__epwmss1,
	&am33xx_epwmss1__ecap1,
	&am33xx_epwmss1__eqep1,
	&am33xx_epwmss1__ehrpwm1,
	&am33xx_l4_ls__epwmss2,
	&am33xx_epwmss2__ecap2,
	&am33xx_epwmss2__eqep2,
	&am33xx_epwmss2__ehrpwm2,
	&am33xx_l3_s__gpmc,
	&am33xx_l4_ls__mcspi0,
	&am33xx_l4_ls__mcspi1,
	&am33xx_l3_main__tptc0,
	&am33xx_l3_main__tptc1,
	&am33xx_l3_main__tptc2,
	&am33xx_l3_main__ocmc,
	&am43xx_l4_hs__cpgmac0,
	&am33xx_cpgmac0__mdio,
	&am33xx_l3_main__sha0,
	&am33xx_l3_main__aes0,
	NULL,
};

int __init am43xx_hwmod_init(void)
{
	omap_hwmod_am43xx_reg();
	omap_hwmod_init();
	return omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
}
Commit	Line	Data
6913952f AM	1	/*
	2	* Copyright (C) 2013 Texas Instruments Incorporated
	3	*
	4	* Hwmod present only in AM43x and those that differ other than register
	5	* offsets as compared to AM335x.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation version 2.
	10	*
	11	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	12	* kind, whether express or implied; without even the implied warranty
	13	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*/
	16
	17	#include <linux/platform_data/gpio-omap.h>
	18	#include <linux/platform_data/spi-omap2-mcspi.h>
	19	#include "omap_hwmod.h"
	20	#include "omap_hwmod_33xx_43xx_common_data.h"
	21	#include "prcm43xx.h"
	22
	23	/* IP blocks */
	24	static struct omap_hwmod am43xx_l4_hs_hwmod = {
	25	.name = "l4_hs",
	26	.class = &am33xx_l4_hwmod_class,
	27	.clkdm_name = "l3_clkdm",
	28	.flags = HWMOD_INIT_NO_IDLE,
	29	.main_clk = "l4hs_gclk",
	30	.prcm = {
	31	.omap4 = {
	32	.clkctrl_offs = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
	33	.modulemode = MODULEMODE_SWCTRL,
	34	},
	35	},
	36	};
	37
	38	static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
	39	{ .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
	40	};
	41
	42	static struct omap_hwmod am43xx_wkup_m3_hwmod = {
	43	.name = "wkup_m3",
	44	.class = &am33xx_wkup_m3_hwmod_class,
	45	.clkdm_name = "l4_wkup_aon_clkdm",
	46	/* Keep hardreset asserted */
	47	.flags = HWMOD_INIT_NO_RESET \| HWMOD_NO_IDLEST,
	48	.main_clk = "sys_clkin_ck",
	49	.prcm = {
	50	.omap4 = {
	51	.clkctrl_offs = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
	52	.rstctrl_offs = AM43XX_RM_WKUP_RSTCTRL_OFFSET,
	53	.rstst_offs = AM43XX_RM_WKUP_RSTST_OFFSET,
	54	.modulemode = MODULEMODE_SWCTRL,
	55	},
	56	},
	57	.rst_lines = am33xx_wkup_m3_resets,
	58	.rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
	59	};
	60
	61	static struct omap_hwmod am43xx_control_hwmod = {
	62	.name = "control",
	63	.class = &am33xx_control_hwmod_class,
	64	.clkdm_name = "l4_wkup_clkdm",
65	.flags = HWMOD_INIT_NO_IDLE,
66	.main_clk = "sys_clkin_ck",
67	.prcm = {
68	.omap4 = {
69	.clkctrl_offs = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
70	.modulemode = MODULEMODE_SWCTRL,
71	},
72	},
73	};
74
75	static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
76	{ .role = "dbclk", .clk = "gpio0_dbclk" },
77	};
78
79	static struct omap_hwmod am43xx_gpio0_hwmod = {
80	.name = "gpio1",
81	.class = &am33xx_gpio_hwmod_class,
82	.clkdm_name = "l4_wkup_clkdm",
83	.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
84	.main_clk = "sys_clkin_ck",
85	.prcm = {
86	.omap4 = {
87	.clkctrl_offs = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
88	.modulemode = MODULEMODE_SWCTRL,
89	},
90	},
91	.opt_clks = gpio0_opt_clks,
92	.opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
93	.dev_attr = &gpio_dev_attr,
94	};
95
96	static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
97	.rev_offs = 0x0,
98	.sysc_offs = 0x4,
99	.sysc_flags = SYSC_HAS_SIDLEMODE,
100	.idlemodes = (SIDLE_FORCE \| SIDLE_NO),
101	.sysc_fields = &omap_hwmod_sysc_type1,
102	};
103
104	static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
105	.name = "synctimer",
106	.sysc = &am43xx_synctimer_sysc,
107	};
108
109	static struct omap_hwmod am43xx_synctimer_hwmod = {
110	.name = "counter_32k",
111	.class = &am43xx_synctimer_hwmod_class,
112	.clkdm_name = "l4_wkup_aon_clkdm",
113	.flags = HWMOD_SWSUP_SIDLE,
114	.main_clk = "synctimer_32kclk",
115	.prcm = {
116	.omap4 = {
117	.clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
118	.modulemode = MODULEMODE_SWCTRL,
119	},
120	},
121	};
122
123	static struct omap_hwmod am43xx_timer8_hwmod = {
124	.name = "timer8",
125	.class = &am33xx_timer_hwmod_class,
126	.clkdm_name = "l4ls_clkdm",
127	.main_clk = "timer8_fck",
128	.prcm = {
129	.omap4 = {
130	.clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
131	.modulemode = MODULEMODE_SWCTRL,
132	},
133	},
134	};
135
136	static struct omap_hwmod am43xx_timer9_hwmod = {
137	.name = "timer9",
138	.class = &am33xx_timer_hwmod_class,
139	.clkdm_name = "l4ls_clkdm",
140	.main_clk = "timer9_fck",
141	.prcm = {
142	.omap4 = {
143	.clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
144	.modulemode = MODULEMODE_SWCTRL,
145	},
146	},
147	};
148
149	static struct omap_hwmod am43xx_timer10_hwmod = {
150	.name = "timer10",
151	.class = &am33xx_timer_hwmod_class,
152	.clkdm_name = "l4ls_clkdm",
153	.main_clk = "timer10_fck",
154	.prcm = {
155	.omap4 = {
156	.clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
157	.modulemode = MODULEMODE_SWCTRL,
158	},
159	},
160	};
161
162	static struct omap_hwmod am43xx_timer11_hwmod = {
163	.name = "timer11",
164	.class = &am33xx_timer_hwmod_class,
165	.clkdm_name = "l4ls_clkdm",
166	.main_clk = "timer11_fck",
167	.prcm = {
168	.omap4 = {
169	.clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
170	.modulemode = MODULEMODE_SWCTRL,
171	},
172	},
173	};
174
175	static struct omap_hwmod am43xx_epwmss3_hwmod = {
176	.name = "epwmss3",
177	.class = &am33xx_epwmss_hwmod_class,
178	.clkdm_name = "l4ls_clkdm",
179	.main_clk = "l4ls_gclk",
180	.prcm = {
181	.omap4 = {
182	.clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
183	.modulemode = MODULEMODE_SWCTRL,
184	},
185	},
186	};
187
188	static struct omap_hwmod am43xx_ehrpwm3_hwmod = {
189	.name = "ehrpwm3",
190	.class = &am33xx_ehrpwm_hwmod_class,
191	.clkdm_name = "l4ls_clkdm",
192	.main_clk = "l4ls_gclk",
193	};
194
195	static struct omap_hwmod am43xx_epwmss4_hwmod = {
196	.name = "epwmss4",
197	.class = &am33xx_epwmss_hwmod_class,
198	.clkdm_name = "l4ls_clkdm",
199	.main_clk = "l4ls_gclk",
200	.prcm = {
201	.omap4 = {
202	.clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
203	.modulemode = MODULEMODE_SWCTRL,
204	},
205	},
206	};
207
208	static struct omap_hwmod am43xx_ehrpwm4_hwmod = {
209	.name = "ehrpwm4",
210	.class = &am33xx_ehrpwm_hwmod_class,
211	.clkdm_name = "l4ls_clkdm",
212	.main_clk = "l4ls_gclk",
213	};
214
215	static struct omap_hwmod am43xx_epwmss5_hwmod = {
216	.name = "epwmss5",
217	.class = &am33xx_epwmss_hwmod_class,
218	.clkdm_name = "l4ls_clkdm",
219	.main_clk = "l4ls_gclk",
220	.prcm = {
221	.omap4 = {
222	.clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
223	.modulemode = MODULEMODE_SWCTRL,
224	},
225	},
226	};
227
228	static struct omap_hwmod am43xx_ehrpwm5_hwmod = {
229	.name = "ehrpwm5",
230	.class = &am33xx_ehrpwm_hwmod_class,
231	.clkdm_name = "l4ls_clkdm",
232	.main_clk = "l4ls_gclk",
233	};
234
235	static struct omap_hwmod am43xx_spi2_hwmod = {
236	.name = "spi2",
237	.class = &am33xx_spi_hwmod_class,
238	.clkdm_name = "l4ls_clkdm",
239	.main_clk = "dpll_per_m2_div4_ck",
240	.prcm = {
241	.omap4 = {
242	.clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
243	.modulemode = MODULEMODE_SWCTRL,
244	},
245	},
246	.dev_attr = &mcspi_attrib,
247	};
248
249	static struct omap_hwmod am43xx_spi3_hwmod = {
250	.name = "spi3",
251	.class = &am33xx_spi_hwmod_class,
252	.clkdm_name = "l4ls_clkdm",
253	.main_clk = "dpll_per_m2_div4_ck",
254	.prcm = {
255	.omap4 = {
256	.clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
257	.modulemode = MODULEMODE_SWCTRL,
258	},
259	},
260	.dev_attr = &mcspi_attrib,
261	};
262
263	static struct omap_hwmod am43xx_spi4_hwmod = {
264	.name = "spi4",
265	.class = &am33xx_spi_hwmod_class,
266	.clkdm_name = "l4ls_clkdm",
267	.main_clk = "dpll_per_m2_div4_ck",
268	.prcm = {
269	.omap4 = {
270	.clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
271	.modulemode = MODULEMODE_SWCTRL,
272	},
273	},
274	.dev_attr = &mcspi_attrib,
275	};
276
277	static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
278	{ .role = "dbclk", .clk = "gpio4_dbclk" },
279	};
280
281	static struct omap_hwmod am43xx_gpio4_hwmod = {
282	.name = "gpio5",
283	.class = &am33xx_gpio_hwmod_class,
284	.clkdm_name = "l4ls_clkdm",
285	.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
286	.main_clk = "l4ls_gclk",
287	.prcm = {
288	.omap4 = {
289	.clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET,
290	.modulemode = MODULEMODE_SWCTRL,
291	},
292	},
293	.opt_clks = gpio4_opt_clks,
294	.opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
295	.dev_attr = &gpio_dev_attr,
296	};
297
298	static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
299	{ .role = "dbclk", .clk = "gpio5_dbclk" },
300	};
301
302	static struct omap_hwmod am43xx_gpio5_hwmod = {
303	.name = "gpio6",
304	.class = &am33xx_gpio_hwmod_class,
305	.clkdm_name = "l4ls_clkdm",
306	.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
307	.main_clk = "l4ls_gclk",
308	.prcm = {
309	.omap4 = {
310	.clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET,
311	.modulemode = MODULEMODE_SWCTRL,
312	},
313	},
314	.opt_clks = gpio5_opt_clks,
315	.opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
316	.dev_attr = &gpio_dev_attr,
317	};
318
319	/* Interfaces */
320	static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
321	.master = &am33xx_l3_main_hwmod,
322	.slave = &am43xx_l4_hs_hwmod,
323	.clk = "l3s_gclk",
324	.user = OCP_USER_MPU \| OCP_USER_SDMA,
325	};
326
327	static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = {
328	.master = &am43xx_wkup_m3_hwmod,
329	.slave = &am33xx_l4_wkup_hwmod,
330	.clk = "sys_clkin_ck",
331	.user = OCP_USER_MPU \| OCP_USER_SDMA,
332	};
333
334	static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = {
335	.master = &am33xx_l4_wkup_hwmod,
336	.slave = &am43xx_wkup_m3_hwmod,
337	.clk = "sys_clkin_ck",
338	.user = OCP_USER_MPU \| OCP_USER_SDMA,
339	};
340
341	static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
342	.master = &am33xx_l3_main_hwmod,
343	.slave = &am33xx_pruss_hwmod,
344	.clk = "dpll_core_m4_ck",
345	.user = OCP_USER_MPU,
346	};
347
348	static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
349	.master = &am33xx_l4_wkup_hwmod,
350	.slave = &am33xx_smartreflex0_hwmod,
351	.clk = "sys_clkin_ck",
352	.user = OCP_USER_MPU,
353	};
354
355	static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = {
356	.master = &am33xx_l4_wkup_hwmod,
357	.slave = &am33xx_smartreflex1_hwmod,
358	.clk = "sys_clkin_ck",
359	.user = OCP_USER_MPU,
360	};
361
362	static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
363	.master = &am33xx_l4_wkup_hwmod,
364	.slave = &am43xx_control_hwmod,
365	.clk = "sys_clkin_ck",
366	.user = OCP_USER_MPU,
367	};
368
369	static struct omap_hwmod_ocp_if am43xx_l4_wkup__i2c1 = {
370	.master = &am33xx_l4_wkup_hwmod,
371	.slave = &am33xx_i2c1_hwmod,
372	.clk = "sys_clkin_ck",
373	.user = OCP_USER_MPU,
374	};
375
376	static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = {
377	.master = &am33xx_l4_wkup_hwmod,
378	.slave = &am43xx_gpio0_hwmod,
379	.clk = "sys_clkin_ck",
380	.user = OCP_USER_MPU \| OCP_USER_SDMA,
381	};
382
383	static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
384	.master = &am43xx_l4_hs_hwmod,
385	.slave = &am33xx_cpgmac0_hwmod,
386	.clk = "cpsw_125mhz_gclk",
387	.user = OCP_USER_MPU,
388	};
389
390	static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
391	.master = &am33xx_l4_wkup_hwmod,
392	.slave = &am33xx_timer1_hwmod,
393	.clk = "sys_clkin_ck",
394	.user = OCP_USER_MPU,
395	};
396
397	static struct omap_hwmod_ocp_if am43xx_l4_wkup__uart1 = {
398	.master = &am33xx_l4_wkup_hwmod,
399	.slave = &am33xx_uart1_hwmod,
400	.clk = "sys_clkin_ck",
401	.user = OCP_USER_MPU,
402	};
403
404	static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = {
405	.master = &am33xx_l4_wkup_hwmod,
406	.slave = &am33xx_wd_timer1_hwmod,
407	.clk = "sys_clkin_ck",
408	.user = OCP_USER_MPU,
409	};
410
411	static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
412	.master = &am33xx_l4_wkup_hwmod,
413	.slave = &am43xx_synctimer_hwmod,
414	.clk = "sys_clkin_ck",
415	.user = OCP_USER_MPU,
416	};
417
418	static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
419	.master = &am33xx_l4_ls_hwmod,
420	.slave = &am43xx_timer8_hwmod,
421	.clk = "l4ls_gclk",
422	.user = OCP_USER_MPU,
423	};
424
425	static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
426	.master = &am33xx_l4_ls_hwmod,
427	.slave = &am43xx_timer9_hwmod,
428	.clk = "l4ls_gclk",
429	.user = OCP_USER_MPU,
430	};
431
432	static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
433	.master = &am33xx_l4_ls_hwmod,
434	.slave = &am43xx_timer10_hwmod,
435	.clk = "l4ls_gclk",
436	.user = OCP_USER_MPU,
437	};
438
439	static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
440	.master = &am33xx_l4_ls_hwmod,
441	.slave = &am43xx_timer11_hwmod,
442	.clk = "l4ls_gclk",
443	.user = OCP_USER_MPU,
444	};
445
446	static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
447	.master = &am33xx_l4_ls_hwmod,
448	.slave = &am43xx_epwmss3_hwmod,
449	.clk = "l4ls_gclk",
450	.user = OCP_USER_MPU,
451	};
452
453	static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = {
454	.master = &am43xx_epwmss3_hwmod,
455	.slave = &am43xx_ehrpwm3_hwmod,
456	.clk = "l4ls_gclk",
457	.user = OCP_USER_MPU,
458	};
459
460	static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
461	.master = &am33xx_l4_ls_hwmod,
462	.slave = &am43xx_epwmss4_hwmod,
463	.clk = "l4ls_gclk",
464	.user = OCP_USER_MPU,
465	};
466
467	static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = {
468	.master = &am43xx_epwmss4_hwmod,
469	.slave = &am43xx_ehrpwm4_hwmod,
470	.clk = "l4ls_gclk",
471	.user = OCP_USER_MPU,
472	};
473
474	static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
475	.master = &am33xx_l4_ls_hwmod,
476	.slave = &am43xx_epwmss5_hwmod,
477	.clk = "l4ls_gclk",
478	.user = OCP_USER_MPU,
479	};
480
481	static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = {
482	.master = &am43xx_epwmss5_hwmod,
483	.slave = &am43xx_ehrpwm5_hwmod,
484	.clk = "l4ls_gclk",
485	.user = OCP_USER_MPU,
486	};
487
488	static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
489	.master = &am33xx_l4_ls_hwmod,
490	.slave = &am43xx_spi2_hwmod,
491	.clk = "l4ls_gclk",
492	.user = OCP_USER_MPU,
493	};
494
495	static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
496	.master = &am33xx_l4_ls_hwmod,
497	.slave = &am43xx_spi3_hwmod,
498	.clk = "l4ls_gclk",
499	.user = OCP_USER_MPU,
500	};
501
502	static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
503	.master = &am33xx_l4_ls_hwmod,
504	.slave = &am43xx_spi4_hwmod,
505	.clk = "l4ls_gclk",
506	.user = OCP_USER_MPU,
507	};
508
509	static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = {
510	.master = &am33xx_l4_ls_hwmod,
511	.slave = &am43xx_gpio4_hwmod,
512	.clk = "l4ls_gclk",
513	.user = OCP_USER_MPU \| OCP_USER_SDMA,
514	};
515
516	static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = {
517	.master = &am33xx_l4_ls_hwmod,
518	.slave = &am43xx_gpio5_hwmod,
519	.clk = "l4ls_gclk",
520	.user = OCP_USER_MPU \| OCP_USER_SDMA,
521	};
522
523	static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
524	&am33xx_l4_wkup__synctimer,
525	&am43xx_l4_ls__timer8,
526	&am43xx_l4_ls__timer9,
527	&am43xx_l4_ls__timer10,
528	&am43xx_l4_ls__timer11,
529	&am43xx_l4_ls__epwmss3,
530	&am43xx_epwmss3__ehrpwm3,
531	&am43xx_l4_ls__epwmss4,
532	&am43xx_epwmss4__ehrpwm4,
533	&am43xx_l4_ls__epwmss5,
534	&am43xx_epwmss5__ehrpwm5,
535	&am43xx_l4_ls__mcspi2,
536	&am43xx_l4_ls__mcspi3,
537	&am43xx_l4_ls__mcspi4,
538	&am43xx_l4_ls__gpio4,
539	&am43xx_l4_ls__gpio5,
540	&am43xx_l3_main__pruss,
541	&am33xx_mpu__l3_main,
542	&am33xx_mpu__prcm,
543	&am33xx_l3_s__l4_ls,
544	&am33xx_l3_s__l4_wkup,
545	&am43xx_l3_main__l4_hs,
546	&am33xx_l3_main__l3_s,
547	&am33xx_l3_main__l3_instr,
548	&am33xx_l3_main__gfx,
549	&am33xx_l3_s__l3_main,
550	&am33xx_pruss__l3_main,
551	&am43xx_wkup_m3__l4_wkup,
552	&am33xx_gfx__l3_main,
553	&am43xx_l4_wkup__wkup_m3,
554	&am43xx_l4_wkup__control,
555	&am43xx_l4_wkup__smartreflex0,
556	&am43xx_l4_wkup__smartreflex1,
557	&am43xx_l4_wkup__uart1,
558	&am43xx_l4_wkup__timer1,
559	&am43xx_l4_wkup__i2c1,
560	&am43xx_l4_wkup__gpio0,
561	&am43xx_l4_wkup__wd_timer1,
562	&am33xx_l4_per__dcan0,
563	&am33xx_l4_per__dcan1,
564	&am33xx_l4_per__gpio1,
565	&am33xx_l4_per__gpio2,
566	&am33xx_l4_per__gpio3,
567	&am33xx_l4_per__i2c2,
568	&am33xx_l4_per__i2c3,
569	&am33xx_l4_per__mailbox,
570	&am33xx_l4_ls__mcasp0,
571	&am33xx_l4_ls__mcasp1,
572	&am33xx_l4_ls__mmc0,
573	&am33xx_l4_ls__mmc1,
574	&am33xx_l3_s__mmc2,
575	&am33xx_l4_ls__timer2,
576	&am33xx_l4_ls__timer3,
577	&am33xx_l4_ls__timer4,
578	&am33xx_l4_ls__timer5,
579	&am33xx_l4_ls__timer6,
580	&am33xx_l4_ls__timer7,
581	&am33xx_l3_main__tpcc,
582	&am33xx_l4_ls__uart2,
583	&am33xx_l4_ls__uart3,
584	&am33xx_l4_ls__uart4,
585	&am33xx_l4_ls__uart5,
586	&am33xx_l4_ls__uart6,
587	&am33xx_l4_ls__elm,
588	&am33xx_l4_ls__epwmss0,
589	&am33xx_epwmss0__ecap0,
590	&am33xx_epwmss0__eqep0,
591	&am33xx_epwmss0__ehrpwm0,
592	&am33xx_l4_ls__epwmss1,
593	&am33xx_epwmss1__ecap1,
594	&am33xx_epwmss1__eqep1,
595	&am33xx_epwmss1__ehrpwm1,
596	&am33xx_l4_ls__epwmss2,
597	&am33xx_epwmss2__ecap2,
598	&am33xx_epwmss2__eqep2,
599	&am33xx_epwmss2__ehrpwm2,
600	&am33xx_l3_s__gpmc,
601	&am33xx_l4_ls__mcspi0,
602	&am33xx_l4_ls__mcspi1,
603	&am33xx_l3_main__tptc0,
604	&am33xx_l3_main__tptc1,
605	&am33xx_l3_main__tptc2,
606	&am33xx_l3_main__ocmc,
607	&am43xx_l4_hs__cpgmac0,
608	&am33xx_cpgmac0__mdio,
609	&am33xx_l3_main__sha0,
610	&am33xx_l3_main__aes0,
611	NULL,
612	};
613
614	int __init am43xx_hwmod_init(void)
615	{
616	omap_hwmod_am43xx_reg();
617	omap_hwmod_init();
618	return omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
619	}