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6913952f AM |
1 | /* |
2 | * Copyright (C) 2013 Texas Instruments Incorporated | |
3 | * | |
4 | * Hwmod present only in AM43x and those that differ other than register | |
5 | * offsets as compared to AM335x. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation version 2. | |
10 | * | |
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
12 | * kind, whether express or implied; without even the implied warranty | |
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/platform_data/gpio-omap.h> | |
18 | #include <linux/platform_data/spi-omap2-mcspi.h> | |
19 | #include "omap_hwmod.h" | |
20 | #include "omap_hwmod_33xx_43xx_common_data.h" | |
21 | #include "prcm43xx.h" | |
509efaf3 | 22 | #include "omap_hwmod_common_data.h" |
89122aa8 | 23 | #include "hdq1w.h" |
509efaf3 | 24 | |
6913952f AM |
25 | |
26 | /* IP blocks */ | |
27 | static struct omap_hwmod am43xx_l4_hs_hwmod = { | |
28 | .name = "l4_hs", | |
29 | .class = &am33xx_l4_hwmod_class, | |
30 | .clkdm_name = "l3_clkdm", | |
31 | .flags = HWMOD_INIT_NO_IDLE, | |
32 | .main_clk = "l4hs_gclk", | |
33 | .prcm = { | |
34 | .omap4 = { | |
35 | .clkctrl_offs = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET, | |
36 | .modulemode = MODULEMODE_SWCTRL, | |
37 | }, | |
38 | }, | |
39 | }; | |
40 | ||
41 | static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = { | |
42 | { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, | |
43 | }; | |
44 | ||
45 | static struct omap_hwmod am43xx_wkup_m3_hwmod = { | |
46 | .name = "wkup_m3", | |
47 | .class = &am33xx_wkup_m3_hwmod_class, | |
48 | .clkdm_name = "l4_wkup_aon_clkdm", | |
49 | /* Keep hardreset asserted */ | |
50 | .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST, | |
51 | .main_clk = "sys_clkin_ck", | |
52 | .prcm = { | |
53 | .omap4 = { | |
54 | .clkctrl_offs = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET, | |
55 | .rstctrl_offs = AM43XX_RM_WKUP_RSTCTRL_OFFSET, | |
56 | .rstst_offs = AM43XX_RM_WKUP_RSTST_OFFSET, | |
57 | .modulemode = MODULEMODE_SWCTRL, | |
58 | }, | |
59 | }, | |
60 | .rst_lines = am33xx_wkup_m3_resets, | |
61 | .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets), | |
62 | }; | |
63 | ||
64 | static struct omap_hwmod am43xx_control_hwmod = { | |
65 | .name = "control", | |
66 | .class = &am33xx_control_hwmod_class, | |
67 | .clkdm_name = "l4_wkup_clkdm", | |
68 | .flags = HWMOD_INIT_NO_IDLE, | |
69 | .main_clk = "sys_clkin_ck", | |
70 | .prcm = { | |
71 | .omap4 = { | |
72 | .clkctrl_offs = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET, | |
73 | .modulemode = MODULEMODE_SWCTRL, | |
74 | }, | |
75 | }, | |
76 | }; | |
77 | ||
78 | static struct omap_hwmod_opt_clk gpio0_opt_clks[] = { | |
79 | { .role = "dbclk", .clk = "gpio0_dbclk" }, | |
80 | }; | |
81 | ||
82 | static struct omap_hwmod am43xx_gpio0_hwmod = { | |
83 | .name = "gpio1", | |
84 | .class = &am33xx_gpio_hwmod_class, | |
85 | .clkdm_name = "l4_wkup_clkdm", | |
86 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
87 | .main_clk = "sys_clkin_ck", | |
88 | .prcm = { | |
89 | .omap4 = { | |
90 | .clkctrl_offs = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET, | |
91 | .modulemode = MODULEMODE_SWCTRL, | |
92 | }, | |
93 | }, | |
94 | .opt_clks = gpio0_opt_clks, | |
95 | .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks), | |
96 | .dev_attr = &gpio_dev_attr, | |
97 | }; | |
98 | ||
99 | static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = { | |
100 | .rev_offs = 0x0, | |
101 | .sysc_offs = 0x4, | |
102 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
103 | .idlemodes = (SIDLE_FORCE | SIDLE_NO), | |
104 | .sysc_fields = &omap_hwmod_sysc_type1, | |
105 | }; | |
106 | ||
107 | static struct omap_hwmod_class am43xx_synctimer_hwmod_class = { | |
108 | .name = "synctimer", | |
109 | .sysc = &am43xx_synctimer_sysc, | |
110 | }; | |
111 | ||
112 | static struct omap_hwmod am43xx_synctimer_hwmod = { | |
113 | .name = "counter_32k", | |
114 | .class = &am43xx_synctimer_hwmod_class, | |
115 | .clkdm_name = "l4_wkup_aon_clkdm", | |
116 | .flags = HWMOD_SWSUP_SIDLE, | |
117 | .main_clk = "synctimer_32kclk", | |
118 | .prcm = { | |
119 | .omap4 = { | |
120 | .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, | |
121 | .modulemode = MODULEMODE_SWCTRL, | |
122 | }, | |
123 | }, | |
124 | }; | |
125 | ||
126 | static struct omap_hwmod am43xx_timer8_hwmod = { | |
127 | .name = "timer8", | |
128 | .class = &am33xx_timer_hwmod_class, | |
129 | .clkdm_name = "l4ls_clkdm", | |
130 | .main_clk = "timer8_fck", | |
131 | .prcm = { | |
132 | .omap4 = { | |
133 | .clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET, | |
134 | .modulemode = MODULEMODE_SWCTRL, | |
135 | }, | |
136 | }, | |
137 | }; | |
138 | ||
139 | static struct omap_hwmod am43xx_timer9_hwmod = { | |
140 | .name = "timer9", | |
141 | .class = &am33xx_timer_hwmod_class, | |
142 | .clkdm_name = "l4ls_clkdm", | |
143 | .main_clk = "timer9_fck", | |
144 | .prcm = { | |
145 | .omap4 = { | |
146 | .clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET, | |
147 | .modulemode = MODULEMODE_SWCTRL, | |
148 | }, | |
149 | }, | |
150 | }; | |
151 | ||
152 | static struct omap_hwmod am43xx_timer10_hwmod = { | |
153 | .name = "timer10", | |
154 | .class = &am33xx_timer_hwmod_class, | |
155 | .clkdm_name = "l4ls_clkdm", | |
156 | .main_clk = "timer10_fck", | |
157 | .prcm = { | |
158 | .omap4 = { | |
159 | .clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET, | |
160 | .modulemode = MODULEMODE_SWCTRL, | |
161 | }, | |
162 | }, | |
163 | }; | |
164 | ||
165 | static struct omap_hwmod am43xx_timer11_hwmod = { | |
166 | .name = "timer11", | |
167 | .class = &am33xx_timer_hwmod_class, | |
168 | .clkdm_name = "l4ls_clkdm", | |
169 | .main_clk = "timer11_fck", | |
170 | .prcm = { | |
171 | .omap4 = { | |
172 | .clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET, | |
173 | .modulemode = MODULEMODE_SWCTRL, | |
174 | }, | |
175 | }, | |
176 | }; | |
177 | ||
178 | static struct omap_hwmod am43xx_epwmss3_hwmod = { | |
179 | .name = "epwmss3", | |
180 | .class = &am33xx_epwmss_hwmod_class, | |
181 | .clkdm_name = "l4ls_clkdm", | |
182 | .main_clk = "l4ls_gclk", | |
183 | .prcm = { | |
184 | .omap4 = { | |
185 | .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET, | |
186 | .modulemode = MODULEMODE_SWCTRL, | |
187 | }, | |
188 | }, | |
189 | }; | |
190 | ||
191 | static struct omap_hwmod am43xx_ehrpwm3_hwmod = { | |
192 | .name = "ehrpwm3", | |
193 | .class = &am33xx_ehrpwm_hwmod_class, | |
194 | .clkdm_name = "l4ls_clkdm", | |
195 | .main_clk = "l4ls_gclk", | |
196 | }; | |
197 | ||
198 | static struct omap_hwmod am43xx_epwmss4_hwmod = { | |
199 | .name = "epwmss4", | |
200 | .class = &am33xx_epwmss_hwmod_class, | |
201 | .clkdm_name = "l4ls_clkdm", | |
202 | .main_clk = "l4ls_gclk", | |
203 | .prcm = { | |
204 | .omap4 = { | |
205 | .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET, | |
206 | .modulemode = MODULEMODE_SWCTRL, | |
207 | }, | |
208 | }, | |
209 | }; | |
210 | ||
211 | static struct omap_hwmod am43xx_ehrpwm4_hwmod = { | |
212 | .name = "ehrpwm4", | |
213 | .class = &am33xx_ehrpwm_hwmod_class, | |
214 | .clkdm_name = "l4ls_clkdm", | |
215 | .main_clk = "l4ls_gclk", | |
216 | }; | |
217 | ||
218 | static struct omap_hwmod am43xx_epwmss5_hwmod = { | |
219 | .name = "epwmss5", | |
220 | .class = &am33xx_epwmss_hwmod_class, | |
221 | .clkdm_name = "l4ls_clkdm", | |
222 | .main_clk = "l4ls_gclk", | |
223 | .prcm = { | |
224 | .omap4 = { | |
225 | .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET, | |
226 | .modulemode = MODULEMODE_SWCTRL, | |
227 | }, | |
228 | }, | |
229 | }; | |
230 | ||
231 | static struct omap_hwmod am43xx_ehrpwm5_hwmod = { | |
232 | .name = "ehrpwm5", | |
233 | .class = &am33xx_ehrpwm_hwmod_class, | |
234 | .clkdm_name = "l4ls_clkdm", | |
235 | .main_clk = "l4ls_gclk", | |
236 | }; | |
237 | ||
238 | static struct omap_hwmod am43xx_spi2_hwmod = { | |
239 | .name = "spi2", | |
240 | .class = &am33xx_spi_hwmod_class, | |
241 | .clkdm_name = "l4ls_clkdm", | |
242 | .main_clk = "dpll_per_m2_div4_ck", | |
243 | .prcm = { | |
244 | .omap4 = { | |
245 | .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET, | |
246 | .modulemode = MODULEMODE_SWCTRL, | |
247 | }, | |
248 | }, | |
249 | .dev_attr = &mcspi_attrib, | |
250 | }; | |
251 | ||
252 | static struct omap_hwmod am43xx_spi3_hwmod = { | |
253 | .name = "spi3", | |
254 | .class = &am33xx_spi_hwmod_class, | |
255 | .clkdm_name = "l4ls_clkdm", | |
256 | .main_clk = "dpll_per_m2_div4_ck", | |
257 | .prcm = { | |
258 | .omap4 = { | |
259 | .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET, | |
260 | .modulemode = MODULEMODE_SWCTRL, | |
261 | }, | |
262 | }, | |
263 | .dev_attr = &mcspi_attrib, | |
264 | }; | |
265 | ||
266 | static struct omap_hwmod am43xx_spi4_hwmod = { | |
267 | .name = "spi4", | |
268 | .class = &am33xx_spi_hwmod_class, | |
269 | .clkdm_name = "l4ls_clkdm", | |
270 | .main_clk = "dpll_per_m2_div4_ck", | |
271 | .prcm = { | |
272 | .omap4 = { | |
273 | .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET, | |
274 | .modulemode = MODULEMODE_SWCTRL, | |
275 | }, | |
276 | }, | |
277 | .dev_attr = &mcspi_attrib, | |
278 | }; | |
279 | ||
280 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { | |
281 | { .role = "dbclk", .clk = "gpio4_dbclk" }, | |
282 | }; | |
283 | ||
284 | static struct omap_hwmod am43xx_gpio4_hwmod = { | |
285 | .name = "gpio5", | |
286 | .class = &am33xx_gpio_hwmod_class, | |
287 | .clkdm_name = "l4ls_clkdm", | |
288 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
289 | .main_clk = "l4ls_gclk", | |
290 | .prcm = { | |
291 | .omap4 = { | |
292 | .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET, | |
293 | .modulemode = MODULEMODE_SWCTRL, | |
294 | }, | |
295 | }, | |
296 | .opt_clks = gpio4_opt_clks, | |
297 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
298 | .dev_attr = &gpio_dev_attr, | |
299 | }; | |
300 | ||
301 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { | |
302 | { .role = "dbclk", .clk = "gpio5_dbclk" }, | |
303 | }; | |
304 | ||
305 | static struct omap_hwmod am43xx_gpio5_hwmod = { | |
306 | .name = "gpio6", | |
307 | .class = &am33xx_gpio_hwmod_class, | |
308 | .clkdm_name = "l4ls_clkdm", | |
309 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
310 | .main_clk = "l4ls_gclk", | |
311 | .prcm = { | |
312 | .omap4 = { | |
313 | .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET, | |
314 | .modulemode = MODULEMODE_SWCTRL, | |
315 | }, | |
316 | }, | |
317 | .opt_clks = gpio5_opt_clks, | |
318 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
319 | .dev_attr = &gpio_dev_attr, | |
320 | }; | |
321 | ||
facfbc49 GC |
322 | static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = { |
323 | .name = "ocp2scp", | |
324 | }; | |
325 | ||
326 | static struct omap_hwmod am43xx_ocp2scp0_hwmod = { | |
327 | .name = "ocp2scp0", | |
328 | .class = &am43xx_ocp2scp_hwmod_class, | |
329 | .clkdm_name = "l4ls_clkdm", | |
330 | .main_clk = "l4ls_gclk", | |
331 | .prcm = { | |
332 | .omap4 = { | |
333 | .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET, | |
334 | .modulemode = MODULEMODE_SWCTRL, | |
335 | }, | |
336 | }, | |
337 | }; | |
338 | ||
339 | static struct omap_hwmod am43xx_ocp2scp1_hwmod = { | |
340 | .name = "ocp2scp1", | |
341 | .class = &am43xx_ocp2scp_hwmod_class, | |
342 | .clkdm_name = "l4ls_clkdm", | |
343 | .main_clk = "l4ls_gclk", | |
344 | .prcm = { | |
345 | .omap4 = { | |
346 | .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET, | |
347 | .modulemode = MODULEMODE_SWCTRL, | |
348 | }, | |
349 | }, | |
350 | }; | |
351 | ||
352 | static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = { | |
353 | .rev_offs = 0x0000, | |
354 | .sysc_offs = 0x0010, | |
355 | .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE | | |
356 | SYSC_HAS_SIDLEMODE), | |
357 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
358 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | | |
359 | MSTANDBY_NO | MSTANDBY_SMART | | |
360 | MSTANDBY_SMART_WKUP), | |
361 | .sysc_fields = &omap_hwmod_sysc_type2, | |
362 | }; | |
363 | ||
364 | static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = { | |
365 | .name = "usb_otg_ss", | |
366 | .sysc = &am43xx_usb_otg_ss_sysc, | |
367 | }; | |
368 | ||
369 | static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = { | |
370 | .name = "usb_otg_ss0", | |
371 | .class = &am43xx_usb_otg_ss_hwmod_class, | |
372 | .clkdm_name = "l3s_clkdm", | |
373 | .main_clk = "l3s_gclk", | |
374 | .prcm = { | |
375 | .omap4 = { | |
376 | .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET, | |
377 | .modulemode = MODULEMODE_SWCTRL, | |
378 | }, | |
379 | }, | |
380 | }; | |
381 | ||
382 | static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = { | |
383 | .name = "usb_otg_ss1", | |
384 | .class = &am43xx_usb_otg_ss_hwmod_class, | |
385 | .clkdm_name = "l3s_clkdm", | |
386 | .main_clk = "l3s_gclk", | |
387 | .prcm = { | |
388 | .omap4 = { | |
389 | .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET, | |
390 | .modulemode = MODULEMODE_SWCTRL, | |
391 | }, | |
392 | }, | |
393 | }; | |
394 | ||
70b0d5f5 SP |
395 | static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = { |
396 | .sysc_offs = 0x0010, | |
397 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
398 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
399 | SIDLE_SMART_WKUP), | |
400 | .sysc_fields = &omap_hwmod_sysc_type2, | |
401 | }; | |
402 | ||
403 | static struct omap_hwmod_class am43xx_qspi_hwmod_class = { | |
404 | .name = "qspi", | |
405 | .sysc = &am43xx_qspi_sysc, | |
406 | }; | |
407 | ||
408 | static struct omap_hwmod am43xx_qspi_hwmod = { | |
409 | .name = "qspi", | |
410 | .class = &am43xx_qspi_hwmod_class, | |
411 | .clkdm_name = "l3s_clkdm", | |
412 | .main_clk = "l3s_gclk", | |
413 | .prcm = { | |
414 | .omap4 = { | |
415 | .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET, | |
416 | .modulemode = MODULEMODE_SWCTRL, | |
417 | }, | |
418 | }, | |
419 | }; | |
420 | ||
d1180f69 V |
421 | /* |
422 | * 'adc/tsc' class | |
423 | * TouchScreen Controller (Analog-To-Digital Converter) | |
424 | */ | |
425 | static struct omap_hwmod_class_sysconfig am43xx_adc_tsc_sysc = { | |
426 | .rev_offs = 0x00, | |
427 | .sysc_offs = 0x10, | |
428 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
429 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
430 | SIDLE_SMART_WKUP), | |
431 | .sysc_fields = &omap_hwmod_sysc_type2, | |
432 | }; | |
433 | ||
434 | static struct omap_hwmod_class am43xx_adc_tsc_hwmod_class = { | |
435 | .name = "adc_tsc", | |
436 | .sysc = &am43xx_adc_tsc_sysc, | |
437 | }; | |
438 | ||
439 | static struct omap_hwmod am43xx_adc_tsc_hwmod = { | |
440 | .name = "adc_tsc", | |
441 | .class = &am43xx_adc_tsc_hwmod_class, | |
442 | .clkdm_name = "l3s_tsc_clkdm", | |
443 | .main_clk = "adc_tsc_fck", | |
444 | .prcm = { | |
445 | .omap4 = { | |
446 | .clkctrl_offs = AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET, | |
447 | .modulemode = MODULEMODE_SWCTRL, | |
448 | }, | |
449 | }, | |
450 | }; | |
451 | ||
509efaf3 SP |
452 | /* dss */ |
453 | ||
454 | static struct omap_hwmod am43xx_dss_core_hwmod = { | |
455 | .name = "dss_core", | |
456 | .class = &omap2_dss_hwmod_class, | |
457 | .clkdm_name = "dss_clkdm", | |
458 | .main_clk = "disp_clk", | |
459 | .prcm = { | |
460 | .omap4 = { | |
461 | .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET, | |
462 | .modulemode = MODULEMODE_SWCTRL, | |
463 | }, | |
464 | }, | |
465 | }; | |
466 | ||
467 | /* dispc */ | |
468 | ||
469 | struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = { | |
470 | .manager_count = 1, | |
471 | .has_framedonetv_irq = 0 | |
472 | }; | |
473 | ||
474 | static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = { | |
475 | .rev_offs = 0x0000, | |
476 | .sysc_offs = 0x0010, | |
477 | .syss_offs = 0x0014, | |
478 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET | | |
479 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
480 | SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE), | |
481 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
482 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
483 | .sysc_fields = &omap_hwmod_sysc_type1, | |
484 | }; | |
485 | ||
486 | static struct omap_hwmod_class am43xx_dispc_hwmod_class = { | |
487 | .name = "dispc", | |
488 | .sysc = &am43xx_dispc_sysc, | |
489 | }; | |
490 | ||
491 | static struct omap_hwmod am43xx_dss_dispc_hwmod = { | |
492 | .name = "dss_dispc", | |
493 | .class = &am43xx_dispc_hwmod_class, | |
494 | .clkdm_name = "dss_clkdm", | |
495 | .main_clk = "disp_clk", | |
496 | .prcm = { | |
497 | .omap4 = { | |
498 | .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET, | |
499 | }, | |
500 | }, | |
501 | .dev_attr = &am43xx_dss_dispc_dev_attr, | |
ccfb24e3 | 502 | .parent_hwmod = &am43xx_dss_core_hwmod, |
509efaf3 SP |
503 | }; |
504 | ||
505 | /* rfbi */ | |
506 | ||
507 | static struct omap_hwmod am43xx_dss_rfbi_hwmod = { | |
508 | .name = "dss_rfbi", | |
509 | .class = &omap2_rfbi_hwmod_class, | |
510 | .clkdm_name = "dss_clkdm", | |
511 | .main_clk = "disp_clk", | |
512 | .prcm = { | |
513 | .omap4 = { | |
514 | .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET, | |
515 | }, | |
516 | }, | |
ccfb24e3 | 517 | .parent_hwmod = &am43xx_dss_core_hwmod, |
509efaf3 SP |
518 | }; |
519 | ||
89122aa8 SP |
520 | /* HDQ1W */ |
521 | static struct omap_hwmod_class_sysconfig am43xx_hdq1w_sysc = { | |
522 | .rev_offs = 0x0000, | |
523 | .sysc_offs = 0x0014, | |
524 | .syss_offs = 0x0018, | |
525 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
526 | .sysc_fields = &omap_hwmod_sysc_type1, | |
527 | }; | |
528 | ||
529 | static struct omap_hwmod_class am43xx_hdq1w_hwmod_class = { | |
530 | .name = "hdq1w", | |
531 | .sysc = &am43xx_hdq1w_sysc, | |
532 | .reset = &omap_hdq1w_reset, | |
533 | }; | |
534 | ||
535 | static struct omap_hwmod am43xx_hdq1w_hwmod = { | |
536 | .name = "hdq1w", | |
537 | .class = &am43xx_hdq1w_hwmod_class, | |
538 | .clkdm_name = "l4ls_clkdm", | |
539 | .prcm = { | |
540 | .omap4 = { | |
541 | .clkctrl_offs = AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET, | |
542 | .modulemode = MODULEMODE_SWCTRL, | |
543 | }, | |
544 | }, | |
545 | }; | |
546 | ||
6913952f AM |
547 | /* Interfaces */ |
548 | static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = { | |
549 | .master = &am33xx_l3_main_hwmod, | |
550 | .slave = &am43xx_l4_hs_hwmod, | |
551 | .clk = "l3s_gclk", | |
552 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
553 | }; | |
554 | ||
555 | static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = { | |
556 | .master = &am43xx_wkup_m3_hwmod, | |
557 | .slave = &am33xx_l4_wkup_hwmod, | |
558 | .clk = "sys_clkin_ck", | |
559 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
560 | }; | |
561 | ||
562 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = { | |
563 | .master = &am33xx_l4_wkup_hwmod, | |
564 | .slave = &am43xx_wkup_m3_hwmod, | |
565 | .clk = "sys_clkin_ck", | |
566 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
567 | }; | |
568 | ||
569 | static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = { | |
570 | .master = &am33xx_l3_main_hwmod, | |
571 | .slave = &am33xx_pruss_hwmod, | |
572 | .clk = "dpll_core_m4_ck", | |
573 | .user = OCP_USER_MPU, | |
574 | }; | |
575 | ||
576 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = { | |
577 | .master = &am33xx_l4_wkup_hwmod, | |
578 | .slave = &am33xx_smartreflex0_hwmod, | |
579 | .clk = "sys_clkin_ck", | |
580 | .user = OCP_USER_MPU, | |
581 | }; | |
582 | ||
583 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = { | |
584 | .master = &am33xx_l4_wkup_hwmod, | |
585 | .slave = &am33xx_smartreflex1_hwmod, | |
586 | .clk = "sys_clkin_ck", | |
587 | .user = OCP_USER_MPU, | |
588 | }; | |
589 | ||
590 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = { | |
591 | .master = &am33xx_l4_wkup_hwmod, | |
592 | .slave = &am43xx_control_hwmod, | |
593 | .clk = "sys_clkin_ck", | |
594 | .user = OCP_USER_MPU, | |
595 | }; | |
596 | ||
597 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__i2c1 = { | |
598 | .master = &am33xx_l4_wkup_hwmod, | |
599 | .slave = &am33xx_i2c1_hwmod, | |
600 | .clk = "sys_clkin_ck", | |
601 | .user = OCP_USER_MPU, | |
602 | }; | |
603 | ||
604 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = { | |
605 | .master = &am33xx_l4_wkup_hwmod, | |
606 | .slave = &am43xx_gpio0_hwmod, | |
607 | .clk = "sys_clkin_ck", | |
608 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
609 | }; | |
610 | ||
d1180f69 V |
611 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = { |
612 | .master = &am33xx_l4_wkup_hwmod, | |
613 | .slave = &am43xx_adc_tsc_hwmod, | |
614 | .clk = "dpll_core_m4_div2_ck", | |
615 | .user = OCP_USER_MPU, | |
616 | }; | |
617 | ||
6913952f AM |
618 | static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = { |
619 | .master = &am43xx_l4_hs_hwmod, | |
620 | .slave = &am33xx_cpgmac0_hwmod, | |
621 | .clk = "cpsw_125mhz_gclk", | |
622 | .user = OCP_USER_MPU, | |
623 | }; | |
624 | ||
625 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = { | |
626 | .master = &am33xx_l4_wkup_hwmod, | |
627 | .slave = &am33xx_timer1_hwmod, | |
628 | .clk = "sys_clkin_ck", | |
629 | .user = OCP_USER_MPU, | |
630 | }; | |
631 | ||
632 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__uart1 = { | |
633 | .master = &am33xx_l4_wkup_hwmod, | |
634 | .slave = &am33xx_uart1_hwmod, | |
635 | .clk = "sys_clkin_ck", | |
636 | .user = OCP_USER_MPU, | |
637 | }; | |
638 | ||
639 | static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = { | |
640 | .master = &am33xx_l4_wkup_hwmod, | |
641 | .slave = &am33xx_wd_timer1_hwmod, | |
642 | .clk = "sys_clkin_ck", | |
643 | .user = OCP_USER_MPU, | |
644 | }; | |
645 | ||
646 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = { | |
647 | .master = &am33xx_l4_wkup_hwmod, | |
648 | .slave = &am43xx_synctimer_hwmod, | |
649 | .clk = "sys_clkin_ck", | |
650 | .user = OCP_USER_MPU, | |
651 | }; | |
652 | ||
653 | static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = { | |
654 | .master = &am33xx_l4_ls_hwmod, | |
655 | .slave = &am43xx_timer8_hwmod, | |
656 | .clk = "l4ls_gclk", | |
657 | .user = OCP_USER_MPU, | |
658 | }; | |
659 | ||
660 | static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = { | |
661 | .master = &am33xx_l4_ls_hwmod, | |
662 | .slave = &am43xx_timer9_hwmod, | |
663 | .clk = "l4ls_gclk", | |
664 | .user = OCP_USER_MPU, | |
665 | }; | |
666 | ||
667 | static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = { | |
668 | .master = &am33xx_l4_ls_hwmod, | |
669 | .slave = &am43xx_timer10_hwmod, | |
670 | .clk = "l4ls_gclk", | |
671 | .user = OCP_USER_MPU, | |
672 | }; | |
673 | ||
674 | static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = { | |
675 | .master = &am33xx_l4_ls_hwmod, | |
676 | .slave = &am43xx_timer11_hwmod, | |
677 | .clk = "l4ls_gclk", | |
678 | .user = OCP_USER_MPU, | |
679 | }; | |
680 | ||
681 | static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = { | |
682 | .master = &am33xx_l4_ls_hwmod, | |
683 | .slave = &am43xx_epwmss3_hwmod, | |
684 | .clk = "l4ls_gclk", | |
685 | .user = OCP_USER_MPU, | |
686 | }; | |
687 | ||
688 | static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = { | |
689 | .master = &am43xx_epwmss3_hwmod, | |
690 | .slave = &am43xx_ehrpwm3_hwmod, | |
691 | .clk = "l4ls_gclk", | |
692 | .user = OCP_USER_MPU, | |
693 | }; | |
694 | ||
695 | static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = { | |
696 | .master = &am33xx_l4_ls_hwmod, | |
697 | .slave = &am43xx_epwmss4_hwmod, | |
698 | .clk = "l4ls_gclk", | |
699 | .user = OCP_USER_MPU, | |
700 | }; | |
701 | ||
702 | static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = { | |
703 | .master = &am43xx_epwmss4_hwmod, | |
704 | .slave = &am43xx_ehrpwm4_hwmod, | |
705 | .clk = "l4ls_gclk", | |
706 | .user = OCP_USER_MPU, | |
707 | }; | |
708 | ||
709 | static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = { | |
710 | .master = &am33xx_l4_ls_hwmod, | |
711 | .slave = &am43xx_epwmss5_hwmod, | |
712 | .clk = "l4ls_gclk", | |
713 | .user = OCP_USER_MPU, | |
714 | }; | |
715 | ||
716 | static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = { | |
717 | .master = &am43xx_epwmss5_hwmod, | |
718 | .slave = &am43xx_ehrpwm5_hwmod, | |
719 | .clk = "l4ls_gclk", | |
720 | .user = OCP_USER_MPU, | |
721 | }; | |
722 | ||
723 | static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = { | |
724 | .master = &am33xx_l4_ls_hwmod, | |
725 | .slave = &am43xx_spi2_hwmod, | |
726 | .clk = "l4ls_gclk", | |
727 | .user = OCP_USER_MPU, | |
728 | }; | |
729 | ||
730 | static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = { | |
731 | .master = &am33xx_l4_ls_hwmod, | |
732 | .slave = &am43xx_spi3_hwmod, | |
733 | .clk = "l4ls_gclk", | |
734 | .user = OCP_USER_MPU, | |
735 | }; | |
736 | ||
737 | static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = { | |
738 | .master = &am33xx_l4_ls_hwmod, | |
739 | .slave = &am43xx_spi4_hwmod, | |
740 | .clk = "l4ls_gclk", | |
741 | .user = OCP_USER_MPU, | |
742 | }; | |
743 | ||
744 | static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = { | |
745 | .master = &am33xx_l4_ls_hwmod, | |
746 | .slave = &am43xx_gpio4_hwmod, | |
747 | .clk = "l4ls_gclk", | |
748 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
749 | }; | |
750 | ||
751 | static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = { | |
752 | .master = &am33xx_l4_ls_hwmod, | |
753 | .slave = &am43xx_gpio5_hwmod, | |
754 | .clk = "l4ls_gclk", | |
755 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
756 | }; | |
757 | ||
facfbc49 GC |
758 | static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = { |
759 | .master = &am33xx_l4_ls_hwmod, | |
760 | .slave = &am43xx_ocp2scp0_hwmod, | |
761 | .clk = "l4ls_gclk", | |
762 | .user = OCP_USER_MPU, | |
763 | }; | |
764 | ||
765 | static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = { | |
766 | .master = &am33xx_l4_ls_hwmod, | |
767 | .slave = &am43xx_ocp2scp1_hwmod, | |
768 | .clk = "l4ls_gclk", | |
769 | .user = OCP_USER_MPU, | |
770 | }; | |
771 | ||
772 | static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = { | |
773 | .master = &am33xx_l3_s_hwmod, | |
774 | .slave = &am43xx_usb_otg_ss0_hwmod, | |
775 | .clk = "l3s_gclk", | |
776 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
777 | }; | |
778 | ||
779 | static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = { | |
780 | .master = &am33xx_l3_s_hwmod, | |
781 | .slave = &am43xx_usb_otg_ss1_hwmod, | |
782 | .clk = "l3s_gclk", | |
783 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
784 | }; | |
785 | ||
70b0d5f5 SP |
786 | static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = { |
787 | .master = &am33xx_l3_s_hwmod, | |
788 | .slave = &am43xx_qspi_hwmod, | |
789 | .clk = "l3s_gclk", | |
790 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
791 | }; | |
792 | ||
509efaf3 SP |
793 | static struct omap_hwmod_ocp_if am43xx_dss__l3_main = { |
794 | .master = &am43xx_dss_core_hwmod, | |
795 | .slave = &am33xx_l3_main_hwmod, | |
796 | .clk = "l3_gclk", | |
797 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
798 | }; | |
799 | ||
800 | static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = { | |
801 | .master = &am33xx_l4_ls_hwmod, | |
802 | .slave = &am43xx_dss_core_hwmod, | |
803 | .clk = "l4ls_gclk", | |
804 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
805 | }; | |
806 | ||
807 | static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = { | |
808 | .master = &am33xx_l4_ls_hwmod, | |
809 | .slave = &am43xx_dss_dispc_hwmod, | |
810 | .clk = "l4ls_gclk", | |
811 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
812 | }; | |
813 | ||
814 | static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = { | |
815 | .master = &am33xx_l4_ls_hwmod, | |
816 | .slave = &am43xx_dss_rfbi_hwmod, | |
817 | .clk = "l4ls_gclk", | |
818 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
819 | }; | |
820 | ||
89122aa8 SP |
821 | static struct omap_hwmod_ocp_if am43xx_l4_ls__hdq1w = { |
822 | .master = &am33xx_l4_ls_hwmod, | |
823 | .slave = &am43xx_hdq1w_hwmod, | |
824 | .clk = "l4ls_gclk", | |
825 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
826 | }; | |
827 | ||
6913952f AM |
828 | static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { |
829 | &am33xx_l4_wkup__synctimer, | |
830 | &am43xx_l4_ls__timer8, | |
831 | &am43xx_l4_ls__timer9, | |
832 | &am43xx_l4_ls__timer10, | |
833 | &am43xx_l4_ls__timer11, | |
834 | &am43xx_l4_ls__epwmss3, | |
835 | &am43xx_epwmss3__ehrpwm3, | |
836 | &am43xx_l4_ls__epwmss4, | |
837 | &am43xx_epwmss4__ehrpwm4, | |
838 | &am43xx_l4_ls__epwmss5, | |
839 | &am43xx_epwmss5__ehrpwm5, | |
840 | &am43xx_l4_ls__mcspi2, | |
841 | &am43xx_l4_ls__mcspi3, | |
842 | &am43xx_l4_ls__mcspi4, | |
843 | &am43xx_l4_ls__gpio4, | |
844 | &am43xx_l4_ls__gpio5, | |
845 | &am43xx_l3_main__pruss, | |
846 | &am33xx_mpu__l3_main, | |
847 | &am33xx_mpu__prcm, | |
848 | &am33xx_l3_s__l4_ls, | |
849 | &am33xx_l3_s__l4_wkup, | |
850 | &am43xx_l3_main__l4_hs, | |
851 | &am33xx_l3_main__l3_s, | |
852 | &am33xx_l3_main__l3_instr, | |
853 | &am33xx_l3_main__gfx, | |
854 | &am33xx_l3_s__l3_main, | |
855 | &am33xx_pruss__l3_main, | |
856 | &am43xx_wkup_m3__l4_wkup, | |
857 | &am33xx_gfx__l3_main, | |
858 | &am43xx_l4_wkup__wkup_m3, | |
859 | &am43xx_l4_wkup__control, | |
860 | &am43xx_l4_wkup__smartreflex0, | |
861 | &am43xx_l4_wkup__smartreflex1, | |
862 | &am43xx_l4_wkup__uart1, | |
863 | &am43xx_l4_wkup__timer1, | |
864 | &am43xx_l4_wkup__i2c1, | |
865 | &am43xx_l4_wkup__gpio0, | |
866 | &am43xx_l4_wkup__wd_timer1, | |
d1180f69 | 867 | &am43xx_l4_wkup__adc_tsc, |
70b0d5f5 | 868 | &am43xx_l3_s__qspi, |
6913952f AM |
869 | &am33xx_l4_per__dcan0, |
870 | &am33xx_l4_per__dcan1, | |
871 | &am33xx_l4_per__gpio1, | |
872 | &am33xx_l4_per__gpio2, | |
873 | &am33xx_l4_per__gpio3, | |
874 | &am33xx_l4_per__i2c2, | |
875 | &am33xx_l4_per__i2c3, | |
876 | &am33xx_l4_per__mailbox, | |
877 | &am33xx_l4_ls__mcasp0, | |
878 | &am33xx_l4_ls__mcasp1, | |
879 | &am33xx_l4_ls__mmc0, | |
880 | &am33xx_l4_ls__mmc1, | |
881 | &am33xx_l3_s__mmc2, | |
882 | &am33xx_l4_ls__timer2, | |
883 | &am33xx_l4_ls__timer3, | |
884 | &am33xx_l4_ls__timer4, | |
885 | &am33xx_l4_ls__timer5, | |
886 | &am33xx_l4_ls__timer6, | |
887 | &am33xx_l4_ls__timer7, | |
888 | &am33xx_l3_main__tpcc, | |
889 | &am33xx_l4_ls__uart2, | |
890 | &am33xx_l4_ls__uart3, | |
891 | &am33xx_l4_ls__uart4, | |
892 | &am33xx_l4_ls__uart5, | |
893 | &am33xx_l4_ls__uart6, | |
64b61067 | 894 | &am33xx_l4_ls__spinlock, |
6913952f AM |
895 | &am33xx_l4_ls__elm, |
896 | &am33xx_l4_ls__epwmss0, | |
897 | &am33xx_epwmss0__ecap0, | |
898 | &am33xx_epwmss0__eqep0, | |
899 | &am33xx_epwmss0__ehrpwm0, | |
900 | &am33xx_l4_ls__epwmss1, | |
901 | &am33xx_epwmss1__ecap1, | |
902 | &am33xx_epwmss1__eqep1, | |
903 | &am33xx_epwmss1__ehrpwm1, | |
904 | &am33xx_l4_ls__epwmss2, | |
905 | &am33xx_epwmss2__ecap2, | |
906 | &am33xx_epwmss2__eqep2, | |
907 | &am33xx_epwmss2__ehrpwm2, | |
908 | &am33xx_l3_s__gpmc, | |
909 | &am33xx_l4_ls__mcspi0, | |
910 | &am33xx_l4_ls__mcspi1, | |
911 | &am33xx_l3_main__tptc0, | |
912 | &am33xx_l3_main__tptc1, | |
913 | &am33xx_l3_main__tptc2, | |
914 | &am33xx_l3_main__ocmc, | |
915 | &am43xx_l4_hs__cpgmac0, | |
916 | &am33xx_cpgmac0__mdio, | |
917 | &am33xx_l3_main__sha0, | |
918 | &am33xx_l3_main__aes0, | |
facfbc49 GC |
919 | &am43xx_l4_ls__ocp2scp0, |
920 | &am43xx_l4_ls__ocp2scp1, | |
921 | &am43xx_l3_s__usbotgss0, | |
922 | &am43xx_l3_s__usbotgss1, | |
509efaf3 SP |
923 | &am43xx_dss__l3_main, |
924 | &am43xx_l4_ls__dss, | |
925 | &am43xx_l4_ls__dss_dispc, | |
926 | &am43xx_l4_ls__dss_rfbi, | |
89122aa8 | 927 | &am43xx_l4_ls__hdq1w, |
6913952f AM |
928 | NULL, |
929 | }; | |
930 | ||
931 | int __init am43xx_hwmod_init(void) | |
932 | { | |
933 | omap_hwmod_am43xx_reg(); | |
934 | omap_hwmod_init(); | |
935 | return omap_hwmod_register_links(am43xx_hwmod_ocp_ifs); | |
936 | } |