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55d2cb08 BC |
1 | /* |
2 | * Hardware modules present on the OMAP44xx chips | |
3 | * | |
0a78c5c5 | 4 | * Copyright (C) 2009-2012 Texas Instruments, Inc. |
55d2cb08 BC |
5 | * Copyright (C) 2009-2010 Nokia Corporation |
6 | * | |
7 | * Paul Walmsley | |
8 | * Benoit Cousson | |
9 | * | |
10 | * This file is automatically generated from the OMAP hardware databases. | |
11 | * We respectfully ask that any modifications to this file be coordinated | |
12 | * with the public linux-omap@vger.kernel.org mailing list and the | |
13 | * authors above to ensure that the autogeneration scripts are kept | |
14 | * up-to-date with the file contents. | |
3b9b1015 S |
15 | * Note that this file is currently not in sync with autogeneration scripts. |
16 | * The above note to be removed, once it is synced up. | |
55d2cb08 BC |
17 | * |
18 | * This program is free software; you can redistribute it and/or modify | |
19 | * it under the terms of the GNU General Public License version 2 as | |
20 | * published by the Free Software Foundation. | |
21 | */ | |
22 | ||
23 | #include <linux/io.h> | |
4b25408f | 24 | #include <linux/platform_data/gpio-omap.h> |
b86aeafc | 25 | #include <linux/power/smartreflex.h> |
3a8761c0 | 26 | #include <linux/i2c-omap.h> |
55d2cb08 | 27 | |
45c3eb7d | 28 | #include <linux/omap-dma.h> |
2a296c8f | 29 | |
2203747c AB |
30 | #include <linux/platform_data/spi-omap2-mcspi.h> |
31 | #include <linux/platform_data/asoc-ti-mcbsp.h> | |
2ab7c848 | 32 | #include <linux/platform_data/iommu-omap.h> |
c345c8b0 | 33 | #include <plat/dmtimer.h> |
55d2cb08 | 34 | |
2a296c8f | 35 | #include "omap_hwmod.h" |
55d2cb08 | 36 | #include "omap_hwmod_common_data.h" |
d198b514 PW |
37 | #include "cm1_44xx.h" |
38 | #include "cm2_44xx.h" | |
39 | #include "prm44xx.h" | |
55d2cb08 | 40 | #include "prm-regbits-44xx.h" |
3a8761c0 | 41 | #include "i2c.h" |
68f39e74 | 42 | #include "mmc.h" |
ff2516fb | 43 | #include "wd_timer.h" |
55d2cb08 BC |
44 | |
45 | /* Base offset for all OMAP4 interrupts external to MPUSS */ | |
46 | #define OMAP44XX_IRQ_GIC_START 32 | |
47 | ||
48 | /* Base offset for all OMAP4 dma requests */ | |
844a3b63 | 49 | #define OMAP44XX_DMA_REQ_START 1 |
55d2cb08 BC |
50 | |
51 | /* | |
844a3b63 | 52 | * IP blocks |
55d2cb08 BC |
53 | */ |
54 | ||
55 | /* | |
56 | * 'dmm' class | |
57 | * instance(s): dmm | |
58 | */ | |
59 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { | |
fe13471c | 60 | .name = "dmm", |
55d2cb08 BC |
61 | }; |
62 | ||
7e69ed97 | 63 | /* dmm */ |
55d2cb08 BC |
64 | static struct omap_hwmod omap44xx_dmm_hwmod = { |
65 | .name = "dmm", | |
66 | .class = &omap44xx_dmm_hwmod_class, | |
a5322c6f | 67 | .clkdm_name = "l3_emif_clkdm", |
d0f0631d BC |
68 | .prcm = { |
69 | .omap4 = { | |
70 | .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, | |
27bb00b5 | 71 | .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, |
d0f0631d BC |
72 | }, |
73 | }, | |
55d2cb08 BC |
74 | }; |
75 | ||
55d2cb08 BC |
76 | /* |
77 | * 'l3' class | |
78 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 | |
79 | */ | |
80 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { | |
fe13471c | 81 | .name = "l3", |
55d2cb08 BC |
82 | }; |
83 | ||
7e69ed97 | 84 | /* l3_instr */ |
55d2cb08 BC |
85 | static struct omap_hwmod omap44xx_l3_instr_hwmod = { |
86 | .name = "l3_instr", | |
87 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 88 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
89 | .prcm = { |
90 | .omap4 = { | |
91 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, | |
27bb00b5 | 92 | .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, |
03fdefe5 | 93 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
94 | }, |
95 | }, | |
55d2cb08 BC |
96 | }; |
97 | ||
7e69ed97 | 98 | /* l3_main_1 */ |
55d2cb08 BC |
99 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { |
100 | .name = "l3_main_1", | |
101 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 102 | .clkdm_name = "l3_1_clkdm", |
d0f0631d BC |
103 | .prcm = { |
104 | .omap4 = { | |
105 | .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, | |
27bb00b5 | 106 | .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, |
d0f0631d BC |
107 | }, |
108 | }, | |
55d2cb08 BC |
109 | }; |
110 | ||
7e69ed97 | 111 | /* l3_main_2 */ |
55d2cb08 BC |
112 | static struct omap_hwmod omap44xx_l3_main_2_hwmod = { |
113 | .name = "l3_main_2", | |
114 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 115 | .clkdm_name = "l3_2_clkdm", |
d0f0631d BC |
116 | .prcm = { |
117 | .omap4 = { | |
118 | .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET, | |
27bb00b5 | 119 | .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, |
d0f0631d BC |
120 | }, |
121 | }, | |
55d2cb08 BC |
122 | }; |
123 | ||
7e69ed97 | 124 | /* l3_main_3 */ |
55d2cb08 BC |
125 | static struct omap_hwmod omap44xx_l3_main_3_hwmod = { |
126 | .name = "l3_main_3", | |
127 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 128 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
129 | .prcm = { |
130 | .omap4 = { | |
131 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET, | |
27bb00b5 | 132 | .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET, |
03fdefe5 | 133 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
134 | }, |
135 | }, | |
55d2cb08 BC |
136 | }; |
137 | ||
138 | /* | |
139 | * 'l4' class | |
140 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup | |
141 | */ | |
142 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { | |
fe13471c | 143 | .name = "l4", |
55d2cb08 BC |
144 | }; |
145 | ||
7e69ed97 | 146 | /* l4_abe */ |
55d2cb08 BC |
147 | static struct omap_hwmod omap44xx_l4_abe_hwmod = { |
148 | .name = "l4_abe", | |
149 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 150 | .clkdm_name = "abe_clkdm", |
d0f0631d BC |
151 | .prcm = { |
152 | .omap4 = { | |
153 | .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, | |
ce80979a TK |
154 | .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, |
155 | .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK, | |
46b3af27 | 156 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, |
d0f0631d BC |
157 | }, |
158 | }, | |
55d2cb08 BC |
159 | }; |
160 | ||
7e69ed97 | 161 | /* l4_cfg */ |
55d2cb08 BC |
162 | static struct omap_hwmod omap44xx_l4_cfg_hwmod = { |
163 | .name = "l4_cfg", | |
164 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 165 | .clkdm_name = "l4_cfg_clkdm", |
d0f0631d BC |
166 | .prcm = { |
167 | .omap4 = { | |
168 | .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, | |
27bb00b5 | 169 | .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, |
d0f0631d BC |
170 | }, |
171 | }, | |
55d2cb08 BC |
172 | }; |
173 | ||
7e69ed97 | 174 | /* l4_per */ |
55d2cb08 BC |
175 | static struct omap_hwmod omap44xx_l4_per_hwmod = { |
176 | .name = "l4_per", | |
177 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 178 | .clkdm_name = "l4_per_clkdm", |
d0f0631d BC |
179 | .prcm = { |
180 | .omap4 = { | |
181 | .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET, | |
27bb00b5 | 182 | .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, |
d0f0631d BC |
183 | }, |
184 | }, | |
55d2cb08 BC |
185 | }; |
186 | ||
7e69ed97 | 187 | /* l4_wkup */ |
55d2cb08 BC |
188 | static struct omap_hwmod omap44xx_l4_wkup_hwmod = { |
189 | .name = "l4_wkup", | |
190 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 191 | .clkdm_name = "l4_wkup_clkdm", |
d0f0631d BC |
192 | .prcm = { |
193 | .omap4 = { | |
194 | .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, | |
27bb00b5 | 195 | .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, |
d0f0631d BC |
196 | }, |
197 | }, | |
55d2cb08 BC |
198 | }; |
199 | ||
f776471f | 200 | /* |
3b54baad BC |
201 | * 'mpu_bus' class |
202 | * instance(s): mpu_private | |
f776471f | 203 | */ |
3b54baad | 204 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { |
fe13471c | 205 | .name = "mpu_bus", |
3b54baad | 206 | }; |
f776471f | 207 | |
7e69ed97 | 208 | /* mpu_private */ |
3b54baad BC |
209 | static struct omap_hwmod omap44xx_mpu_private_hwmod = { |
210 | .name = "mpu_private", | |
211 | .class = &omap44xx_mpu_bus_hwmod_class, | |
a5322c6f | 212 | .clkdm_name = "mpuss_clkdm", |
46b3af27 TK |
213 | .prcm = { |
214 | .omap4 = { | |
215 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
216 | }, | |
217 | }, | |
3b54baad BC |
218 | }; |
219 | ||
9a817bc8 BC |
220 | /* |
221 | * 'ocp_wp_noc' class | |
222 | * instance(s): ocp_wp_noc | |
223 | */ | |
224 | static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = { | |
225 | .name = "ocp_wp_noc", | |
226 | }; | |
227 | ||
228 | /* ocp_wp_noc */ | |
229 | static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = { | |
230 | .name = "ocp_wp_noc", | |
231 | .class = &omap44xx_ocp_wp_noc_hwmod_class, | |
232 | .clkdm_name = "l3_instr_clkdm", | |
233 | .prcm = { | |
234 | .omap4 = { | |
235 | .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET, | |
236 | .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET, | |
237 | .modulemode = MODULEMODE_HWCTRL, | |
238 | }, | |
239 | }, | |
240 | }; | |
241 | ||
3b54baad BC |
242 | /* |
243 | * Modules omap_hwmod structures | |
244 | * | |
245 | * The following IPs are excluded for the moment because: | |
246 | * - They do not need an explicit SW control using omap_hwmod API. | |
247 | * - They still need to be validated with the driver | |
248 | * properly adapted to omap_hwmod / omap_device | |
249 | * | |
96566043 | 250 | * usim |
3b54baad BC |
251 | */ |
252 | ||
407a6888 BC |
253 | /* |
254 | * 'aess' class | |
255 | * audio engine sub system | |
256 | */ | |
257 | ||
258 | static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = { | |
259 | .rev_offs = 0x0000, | |
260 | .sysc_offs = 0x0010, | |
261 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
262 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
c614ebf6 BC |
263 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART | |
264 | MSTANDBY_SMART_WKUP), | |
407a6888 BC |
265 | .sysc_fields = &omap_hwmod_sysc_type2, |
266 | }; | |
267 | ||
268 | static struct omap_hwmod_class omap44xx_aess_hwmod_class = { | |
269 | .name = "aess", | |
270 | .sysc = &omap44xx_aess_sysc, | |
c02060d8 | 271 | .enable_preprogram = omap_hwmod_aess_preprogram, |
407a6888 BC |
272 | }; |
273 | ||
274 | /* aess */ | |
407a6888 BC |
275 | static struct omap_hwmod omap44xx_aess_hwmod = { |
276 | .name = "aess", | |
277 | .class = &omap44xx_aess_hwmod_class, | |
a5322c6f | 278 | .clkdm_name = "abe_clkdm", |
9f0c5996 | 279 | .main_clk = "aess_fclk", |
00fe610b | 280 | .prcm = { |
407a6888 | 281 | .omap4 = { |
d0f0631d | 282 | .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, |
27bb00b5 | 283 | .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, |
ce80979a | 284 | .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK, |
03fdefe5 | 285 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
286 | }, |
287 | }, | |
407a6888 BC |
288 | }; |
289 | ||
42b9e387 PW |
290 | /* |
291 | * 'c2c' class | |
292 | * chip 2 chip interface used to plug the ape soc (omap) with an external modem | |
293 | * soc | |
294 | */ | |
295 | ||
296 | static struct omap_hwmod_class omap44xx_c2c_hwmod_class = { | |
297 | .name = "c2c", | |
298 | }; | |
299 | ||
300 | /* c2c */ | |
42b9e387 PW |
301 | static struct omap_hwmod omap44xx_c2c_hwmod = { |
302 | .name = "c2c", | |
303 | .class = &omap44xx_c2c_hwmod_class, | |
304 | .clkdm_name = "d2d_clkdm", | |
42b9e387 PW |
305 | .prcm = { |
306 | .omap4 = { | |
307 | .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET, | |
308 | .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET, | |
309 | }, | |
310 | }, | |
311 | }; | |
312 | ||
407a6888 BC |
313 | /* |
314 | * 'counter' class | |
315 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock | |
316 | */ | |
317 | ||
318 | static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = { | |
319 | .rev_offs = 0x0000, | |
320 | .sysc_offs = 0x0004, | |
321 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
252a4c54 | 322 | .idlemodes = (SIDLE_FORCE | SIDLE_NO), |
407a6888 BC |
323 | .sysc_fields = &omap_hwmod_sysc_type1, |
324 | }; | |
325 | ||
326 | static struct omap_hwmod_class omap44xx_counter_hwmod_class = { | |
327 | .name = "counter", | |
328 | .sysc = &omap44xx_counter_sysc, | |
329 | }; | |
330 | ||
331 | /* counter_32k */ | |
407a6888 BC |
332 | static struct omap_hwmod omap44xx_counter_32k_hwmod = { |
333 | .name = "counter_32k", | |
334 | .class = &omap44xx_counter_hwmod_class, | |
a5322c6f | 335 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 BC |
336 | .flags = HWMOD_SWSUP_SIDLE, |
337 | .main_clk = "sys_32k_ck", | |
00fe610b | 338 | .prcm = { |
407a6888 | 339 | .omap4 = { |
d0f0631d | 340 | .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, |
27bb00b5 | 341 | .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, |
407a6888 BC |
342 | }, |
343 | }, | |
407a6888 BC |
344 | }; |
345 | ||
a0b5d813 PW |
346 | /* |
347 | * 'ctrl_module' class | |
348 | * attila core control module + core pad control module + wkup pad control | |
349 | * module + attila wkup control module | |
350 | */ | |
351 | ||
352 | static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = { | |
353 | .rev_offs = 0x0000, | |
354 | .sysc_offs = 0x0010, | |
355 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
356 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
357 | SIDLE_SMART_WKUP), | |
358 | .sysc_fields = &omap_hwmod_sysc_type2, | |
359 | }; | |
360 | ||
361 | static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = { | |
362 | .name = "ctrl_module", | |
363 | .sysc = &omap44xx_ctrl_module_sysc, | |
364 | }; | |
365 | ||
366 | /* ctrl_module_core */ | |
a0b5d813 PW |
367 | static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = { |
368 | .name = "ctrl_module_core", | |
369 | .class = &omap44xx_ctrl_module_hwmod_class, | |
370 | .clkdm_name = "l4_cfg_clkdm", | |
46b3af27 TK |
371 | .prcm = { |
372 | .omap4 = { | |
373 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
374 | }, | |
375 | }, | |
a0b5d813 PW |
376 | }; |
377 | ||
378 | /* ctrl_module_pad_core */ | |
379 | static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = { | |
380 | .name = "ctrl_module_pad_core", | |
381 | .class = &omap44xx_ctrl_module_hwmod_class, | |
382 | .clkdm_name = "l4_cfg_clkdm", | |
46b3af27 TK |
383 | .prcm = { |
384 | .omap4 = { | |
385 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
386 | }, | |
387 | }, | |
a0b5d813 PW |
388 | }; |
389 | ||
390 | /* ctrl_module_wkup */ | |
391 | static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = { | |
392 | .name = "ctrl_module_wkup", | |
393 | .class = &omap44xx_ctrl_module_hwmod_class, | |
394 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
395 | .prcm = { |
396 | .omap4 = { | |
397 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
398 | }, | |
399 | }, | |
a0b5d813 PW |
400 | }; |
401 | ||
402 | /* ctrl_module_pad_wkup */ | |
403 | static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = { | |
404 | .name = "ctrl_module_pad_wkup", | |
405 | .class = &omap44xx_ctrl_module_hwmod_class, | |
406 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
407 | .prcm = { |
408 | .omap4 = { | |
409 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
410 | }, | |
411 | }, | |
a0b5d813 PW |
412 | }; |
413 | ||
96566043 BC |
414 | /* |
415 | * 'debugss' class | |
416 | * debug and emulation sub system | |
417 | */ | |
418 | ||
419 | static struct omap_hwmod_class omap44xx_debugss_hwmod_class = { | |
420 | .name = "debugss", | |
421 | }; | |
422 | ||
423 | /* debugss */ | |
424 | static struct omap_hwmod omap44xx_debugss_hwmod = { | |
425 | .name = "debugss", | |
426 | .class = &omap44xx_debugss_hwmod_class, | |
427 | .clkdm_name = "emu_sys_clkdm", | |
428 | .main_clk = "trace_clk_div_ck", | |
429 | .prcm = { | |
430 | .omap4 = { | |
431 | .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET, | |
432 | .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET, | |
433 | }, | |
434 | }, | |
435 | }; | |
436 | ||
d7cf5f33 BC |
437 | /* |
438 | * 'dma' class | |
439 | * dma controller for data exchange between memory to memory (i.e. internal or | |
440 | * external memory) and gp peripherals to memory or memory to gp peripherals | |
441 | */ | |
442 | ||
443 | static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { | |
444 | .rev_offs = 0x0000, | |
445 | .sysc_offs = 0x002c, | |
446 | .syss_offs = 0x0028, | |
447 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
448 | SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
449 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
450 | SYSS_HAS_RESET_STATUS), | |
451 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
452 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
453 | .sysc_fields = &omap_hwmod_sysc_type1, | |
454 | }; | |
455 | ||
456 | static struct omap_hwmod_class omap44xx_dma_hwmod_class = { | |
457 | .name = "dma", | |
458 | .sysc = &omap44xx_dma_sysc, | |
459 | }; | |
460 | ||
461 | /* dma dev_attr */ | |
462 | static struct omap_dma_dev_attr dma_dev_attr = { | |
463 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
464 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
465 | .lch_count = 32, | |
466 | }; | |
467 | ||
468 | /* dma_system */ | |
469 | static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { | |
470 | { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, | |
471 | { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, | |
472 | { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, | |
473 | { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 474 | { .irq = -1 } |
d7cf5f33 BC |
475 | }; |
476 | ||
d7cf5f33 BC |
477 | static struct omap_hwmod omap44xx_dma_system_hwmod = { |
478 | .name = "dma_system", | |
479 | .class = &omap44xx_dma_hwmod_class, | |
a5322c6f | 480 | .clkdm_name = "l3_dma_clkdm", |
d7cf5f33 | 481 | .mpu_irqs = omap44xx_dma_system_irqs, |
d7cf5f33 BC |
482 | .main_clk = "l3_div_ck", |
483 | .prcm = { | |
484 | .omap4 = { | |
d0f0631d | 485 | .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET, |
27bb00b5 | 486 | .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET, |
d7cf5f33 BC |
487 | }, |
488 | }, | |
489 | .dev_attr = &dma_dev_attr, | |
d7cf5f33 BC |
490 | }; |
491 | ||
8ca476da BC |
492 | /* |
493 | * 'dmic' class | |
494 | * digital microphone controller | |
495 | */ | |
496 | ||
497 | static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = { | |
498 | .rev_offs = 0x0000, | |
499 | .sysc_offs = 0x0010, | |
500 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
501 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
502 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
503 | SIDLE_SMART_WKUP), | |
504 | .sysc_fields = &omap_hwmod_sysc_type2, | |
505 | }; | |
506 | ||
507 | static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { | |
508 | .name = "dmic", | |
509 | .sysc = &omap44xx_dmic_sysc, | |
510 | }; | |
511 | ||
512 | /* dmic */ | |
8ca476da BC |
513 | static struct omap_hwmod omap44xx_dmic_hwmod = { |
514 | .name = "dmic", | |
515 | .class = &omap44xx_dmic_hwmod_class, | |
a5322c6f | 516 | .clkdm_name = "abe_clkdm", |
ee877acd | 517 | .main_clk = "func_dmic_abe_gfclk", |
00fe610b | 518 | .prcm = { |
8ca476da | 519 | .omap4 = { |
d0f0631d | 520 | .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, |
27bb00b5 | 521 | .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET, |
03fdefe5 | 522 | .modulemode = MODULEMODE_SWCTRL, |
8ca476da BC |
523 | }, |
524 | }, | |
8ca476da BC |
525 | }; |
526 | ||
8f25bdc5 BC |
527 | /* |
528 | * 'dsp' class | |
529 | * dsp sub-system | |
530 | */ | |
531 | ||
532 | static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { | |
fe13471c | 533 | .name = "dsp", |
8f25bdc5 BC |
534 | }; |
535 | ||
536 | /* dsp */ | |
8f25bdc5 | 537 | static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { |
8f25bdc5 BC |
538 | { .name = "dsp", .rst_shift = 0 }, |
539 | }; | |
540 | ||
8f25bdc5 BC |
541 | static struct omap_hwmod omap44xx_dsp_hwmod = { |
542 | .name = "dsp", | |
543 | .class = &omap44xx_dsp_hwmod_class, | |
a5322c6f | 544 | .clkdm_name = "tesla_clkdm", |
8f25bdc5 BC |
545 | .rst_lines = omap44xx_dsp_resets, |
546 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), | |
298ea44f | 547 | .main_clk = "dpll_iva_m4x2_ck", |
8f25bdc5 BC |
548 | .prcm = { |
549 | .omap4 = { | |
d0f0631d | 550 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, |
eaac329d | 551 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, |
27bb00b5 | 552 | .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, |
03fdefe5 | 553 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
554 | }, |
555 | }, | |
8f25bdc5 BC |
556 | }; |
557 | ||
d63bd74f BC |
558 | /* |
559 | * 'dss' class | |
560 | * display sub-system | |
561 | */ | |
562 | ||
563 | static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = { | |
564 | .rev_offs = 0x0000, | |
565 | .syss_offs = 0x0014, | |
566 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
567 | }; | |
568 | ||
569 | static struct omap_hwmod_class omap44xx_dss_hwmod_class = { | |
570 | .name = "dss", | |
571 | .sysc = &omap44xx_dss_sysc, | |
13662dc5 | 572 | .reset = omap_dss_reset, |
d63bd74f BC |
573 | }; |
574 | ||
575 | /* dss */ | |
d63bd74f BC |
576 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { |
577 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
578 | { .role = "tv_clk", .clk = "dss_tv_clk" }, | |
4d0698d9 | 579 | { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, |
d63bd74f BC |
580 | }; |
581 | ||
582 | static struct omap_hwmod omap44xx_dss_hwmod = { | |
583 | .name = "dss_core", | |
37ad0855 | 584 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
d63bd74f | 585 | .class = &omap44xx_dss_hwmod_class, |
a5322c6f | 586 | .clkdm_name = "l3_dss_clkdm", |
da7cdfac | 587 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
588 | .prcm = { |
589 | .omap4 = { | |
d0f0631d | 590 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 591 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
592 | }, |
593 | }, | |
594 | .opt_clks = dss_opt_clks, | |
595 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
d63bd74f BC |
596 | }; |
597 | ||
598 | /* | |
599 | * 'dispc' class | |
600 | * display controller | |
601 | */ | |
602 | ||
603 | static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = { | |
604 | .rev_offs = 0x0000, | |
605 | .sysc_offs = 0x0010, | |
606 | .syss_offs = 0x0014, | |
607 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
608 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | | |
609 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
610 | SYSS_HAS_RESET_STATUS), | |
611 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
612 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
613 | .sysc_fields = &omap_hwmod_sysc_type1, | |
614 | }; | |
615 | ||
616 | static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { | |
617 | .name = "dispc", | |
618 | .sysc = &omap44xx_dispc_sysc, | |
619 | }; | |
620 | ||
621 | /* dss_dispc */ | |
b38911f3 TV |
622 | static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { |
623 | { .irq = 25 + OMAP44XX_IRQ_GIC_START }, | |
624 | { .irq = -1 } | |
625 | }; | |
626 | ||
627 | static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { | |
628 | { .dma_req = 5 + OMAP44XX_DMA_REQ_START }, | |
629 | { .dma_req = -1 } | |
630 | }; | |
631 | ||
b923d40d AT |
632 | static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { |
633 | .manager_count = 3, | |
634 | .has_framedonetv_irq = 1 | |
635 | }; | |
636 | ||
d63bd74f BC |
637 | static struct omap_hwmod omap44xx_dss_dispc_hwmod = { |
638 | .name = "dss_dispc", | |
639 | .class = &omap44xx_dispc_hwmod_class, | |
a5322c6f | 640 | .clkdm_name = "l3_dss_clkdm", |
b38911f3 TV |
641 | .mpu_irqs = omap44xx_dss_dispc_irqs, |
642 | .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, | |
da7cdfac | 643 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
644 | .prcm = { |
645 | .omap4 = { | |
d0f0631d | 646 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 647 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
648 | }, |
649 | }, | |
b923d40d | 650 | .dev_attr = &omap44xx_dss_dispc_dev_attr |
d63bd74f BC |
651 | }; |
652 | ||
653 | /* | |
654 | * 'dsi' class | |
655 | * display serial interface controller | |
656 | */ | |
657 | ||
658 | static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = { | |
659 | .rev_offs = 0x0000, | |
660 | .sysc_offs = 0x0010, | |
661 | .syss_offs = 0x0014, | |
662 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
663 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
664 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
665 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
666 | .sysc_fields = &omap_hwmod_sysc_type1, | |
667 | }; | |
668 | ||
669 | static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { | |
670 | .name = "dsi", | |
671 | .sysc = &omap44xx_dsi_sysc, | |
672 | }; | |
673 | ||
674 | /* dss_dsi1 */ | |
b38911f3 TV |
675 | static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { |
676 | { .irq = 53 + OMAP44XX_IRQ_GIC_START }, | |
677 | { .irq = -1 } | |
678 | }; | |
679 | ||
680 | static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { | |
681 | { .dma_req = 74 + OMAP44XX_DMA_REQ_START }, | |
682 | { .dma_req = -1 } | |
683 | }; | |
684 | ||
3a23aafc TV |
685 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { |
686 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
687 | }; | |
688 | ||
d63bd74f BC |
689 | static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { |
690 | .name = "dss_dsi1", | |
691 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 692 | .clkdm_name = "l3_dss_clkdm", |
b38911f3 TV |
693 | .mpu_irqs = omap44xx_dss_dsi1_irqs, |
694 | .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, | |
da7cdfac | 695 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
696 | .prcm = { |
697 | .omap4 = { | |
d0f0631d | 698 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 699 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
700 | }, |
701 | }, | |
3a23aafc TV |
702 | .opt_clks = dss_dsi1_opt_clks, |
703 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
d63bd74f BC |
704 | }; |
705 | ||
706 | /* dss_dsi2 */ | |
b38911f3 TV |
707 | static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { |
708 | { .irq = 84 + OMAP44XX_IRQ_GIC_START }, | |
709 | { .irq = -1 } | |
710 | }; | |
711 | ||
712 | static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { | |
713 | { .dma_req = 83 + OMAP44XX_DMA_REQ_START }, | |
714 | { .dma_req = -1 } | |
715 | }; | |
716 | ||
3a23aafc TV |
717 | static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { |
718 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
719 | }; | |
720 | ||
d63bd74f BC |
721 | static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { |
722 | .name = "dss_dsi2", | |
723 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 724 | .clkdm_name = "l3_dss_clkdm", |
b38911f3 TV |
725 | .mpu_irqs = omap44xx_dss_dsi2_irqs, |
726 | .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, | |
da7cdfac | 727 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
728 | .prcm = { |
729 | .omap4 = { | |
d0f0631d | 730 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 731 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
732 | }, |
733 | }, | |
3a23aafc TV |
734 | .opt_clks = dss_dsi2_opt_clks, |
735 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), | |
d63bd74f BC |
736 | }; |
737 | ||
738 | /* | |
739 | * 'hdmi' class | |
740 | * hdmi controller | |
741 | */ | |
742 | ||
743 | static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = { | |
744 | .rev_offs = 0x0000, | |
745 | .sysc_offs = 0x0010, | |
746 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
747 | SYSC_HAS_SOFTRESET), | |
748 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
749 | SIDLE_SMART_WKUP), | |
750 | .sysc_fields = &omap_hwmod_sysc_type2, | |
751 | }; | |
752 | ||
753 | static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { | |
754 | .name = "hdmi", | |
755 | .sysc = &omap44xx_hdmi_sysc, | |
756 | }; | |
757 | ||
758 | /* dss_hdmi */ | |
b38911f3 TV |
759 | static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { |
760 | { .irq = 101 + OMAP44XX_IRQ_GIC_START }, | |
761 | { .irq = -1 } | |
762 | }; | |
763 | ||
764 | static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { | |
765 | { .dma_req = 75 + OMAP44XX_DMA_REQ_START }, | |
766 | { .dma_req = -1 } | |
767 | }; | |
768 | ||
3a23aafc TV |
769 | static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { |
770 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
771 | }; | |
772 | ||
d63bd74f BC |
773 | static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { |
774 | .name = "dss_hdmi", | |
775 | .class = &omap44xx_hdmi_hwmod_class, | |
a5322c6f | 776 | .clkdm_name = "l3_dss_clkdm", |
dc57aef5 RN |
777 | /* |
778 | * HDMI audio requires to use no-idle mode. Hence, | |
779 | * set idle mode by software. | |
780 | */ | |
781 | .flags = HWMOD_SWSUP_SIDLE, | |
b38911f3 TV |
782 | .mpu_irqs = omap44xx_dss_hdmi_irqs, |
783 | .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, | |
4d0698d9 | 784 | .main_clk = "dss_48mhz_clk", |
d63bd74f BC |
785 | .prcm = { |
786 | .omap4 = { | |
d0f0631d | 787 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 788 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
789 | }, |
790 | }, | |
3a23aafc TV |
791 | .opt_clks = dss_hdmi_opt_clks, |
792 | .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), | |
d63bd74f BC |
793 | }; |
794 | ||
795 | /* | |
796 | * 'rfbi' class | |
797 | * remote frame buffer interface | |
798 | */ | |
799 | ||
800 | static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = { | |
801 | .rev_offs = 0x0000, | |
802 | .sysc_offs = 0x0010, | |
803 | .syss_offs = 0x0014, | |
804 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
805 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
806 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
807 | .sysc_fields = &omap_hwmod_sysc_type1, | |
808 | }; | |
809 | ||
810 | static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { | |
811 | .name = "rfbi", | |
812 | .sysc = &omap44xx_rfbi_sysc, | |
813 | }; | |
814 | ||
815 | /* dss_rfbi */ | |
b38911f3 TV |
816 | static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { |
817 | { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, | |
818 | { .dma_req = -1 } | |
819 | }; | |
820 | ||
3a23aafc TV |
821 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
822 | { .role = "ick", .clk = "dss_fck" }, | |
823 | }; | |
824 | ||
d63bd74f BC |
825 | static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { |
826 | .name = "dss_rfbi", | |
827 | .class = &omap44xx_rfbi_hwmod_class, | |
a5322c6f | 828 | .clkdm_name = "l3_dss_clkdm", |
b38911f3 | 829 | .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, |
da7cdfac | 830 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
831 | .prcm = { |
832 | .omap4 = { | |
d0f0631d | 833 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 834 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
835 | }, |
836 | }, | |
3a23aafc TV |
837 | .opt_clks = dss_rfbi_opt_clks, |
838 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
d63bd74f BC |
839 | }; |
840 | ||
841 | /* | |
842 | * 'venc' class | |
843 | * video encoder | |
844 | */ | |
845 | ||
846 | static struct omap_hwmod_class omap44xx_venc_hwmod_class = { | |
847 | .name = "venc", | |
848 | }; | |
849 | ||
850 | /* dss_venc */ | |
d63bd74f BC |
851 | static struct omap_hwmod omap44xx_dss_venc_hwmod = { |
852 | .name = "dss_venc", | |
853 | .class = &omap44xx_venc_hwmod_class, | |
a5322c6f | 854 | .clkdm_name = "l3_dss_clkdm", |
4d0698d9 | 855 | .main_clk = "dss_tv_clk", |
d63bd74f BC |
856 | .prcm = { |
857 | .omap4 = { | |
d0f0631d | 858 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 859 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
860 | }, |
861 | }, | |
d63bd74f BC |
862 | }; |
863 | ||
42b9e387 PW |
864 | /* |
865 | * 'elm' class | |
866 | * bch error location module | |
867 | */ | |
868 | ||
869 | static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = { | |
870 | .rev_offs = 0x0000, | |
871 | .sysc_offs = 0x0010, | |
872 | .syss_offs = 0x0014, | |
873 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
874 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
875 | SYSS_HAS_RESET_STATUS), | |
876 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
877 | .sysc_fields = &omap_hwmod_sysc_type1, | |
878 | }; | |
879 | ||
880 | static struct omap_hwmod_class omap44xx_elm_hwmod_class = { | |
881 | .name = "elm", | |
882 | .sysc = &omap44xx_elm_sysc, | |
883 | }; | |
884 | ||
885 | /* elm */ | |
42b9e387 PW |
886 | static struct omap_hwmod omap44xx_elm_hwmod = { |
887 | .name = "elm", | |
888 | .class = &omap44xx_elm_hwmod_class, | |
889 | .clkdm_name = "l4_per_clkdm", | |
42b9e387 PW |
890 | .prcm = { |
891 | .omap4 = { | |
892 | .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET, | |
893 | .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET, | |
894 | }, | |
895 | }, | |
896 | }; | |
897 | ||
bf30f950 PW |
898 | /* |
899 | * 'emif' class | |
900 | * external memory interface no1 | |
901 | */ | |
902 | ||
903 | static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = { | |
904 | .rev_offs = 0x0000, | |
905 | }; | |
906 | ||
907 | static struct omap_hwmod_class omap44xx_emif_hwmod_class = { | |
908 | .name = "emif", | |
909 | .sysc = &omap44xx_emif_sysc, | |
910 | }; | |
911 | ||
912 | /* emif1 */ | |
bf30f950 PW |
913 | static struct omap_hwmod omap44xx_emif1_hwmod = { |
914 | .name = "emif1", | |
915 | .class = &omap44xx_emif_hwmod_class, | |
916 | .clkdm_name = "l3_emif_clkdm", | |
b2eb0002 | 917 | .flags = HWMOD_INIT_NO_IDLE, |
bf30f950 PW |
918 | .main_clk = "ddrphy_ck", |
919 | .prcm = { | |
920 | .omap4 = { | |
921 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET, | |
922 | .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET, | |
923 | .modulemode = MODULEMODE_HWCTRL, | |
924 | }, | |
925 | }, | |
926 | }; | |
927 | ||
928 | /* emif2 */ | |
bf30f950 PW |
929 | static struct omap_hwmod omap44xx_emif2_hwmod = { |
930 | .name = "emif2", | |
931 | .class = &omap44xx_emif_hwmod_class, | |
932 | .clkdm_name = "l3_emif_clkdm", | |
b2eb0002 | 933 | .flags = HWMOD_INIT_NO_IDLE, |
bf30f950 PW |
934 | .main_clk = "ddrphy_ck", |
935 | .prcm = { | |
936 | .omap4 = { | |
937 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET, | |
938 | .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET, | |
939 | .modulemode = MODULEMODE_HWCTRL, | |
940 | }, | |
941 | }, | |
942 | }; | |
943 | ||
b050f688 ML |
944 | /* |
945 | * 'fdif' class | |
946 | * face detection hw accelerator module | |
947 | */ | |
948 | ||
949 | static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = { | |
950 | .rev_offs = 0x0000, | |
951 | .sysc_offs = 0x0010, | |
952 | /* | |
953 | * FDIF needs 100 OCP clk cycles delay after a softreset before | |
954 | * accessing sysconfig again. | |
955 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
956 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
957 | * | |
958 | * TODO: Indicate errata when available. | |
959 | */ | |
960 | .srst_udelay = 2, | |
961 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | | |
962 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
963 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
964 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
965 | .sysc_fields = &omap_hwmod_sysc_type2, | |
966 | }; | |
967 | ||
968 | static struct omap_hwmod_class omap44xx_fdif_hwmod_class = { | |
969 | .name = "fdif", | |
970 | .sysc = &omap44xx_fdif_sysc, | |
971 | }; | |
972 | ||
973 | /* fdif */ | |
b050f688 ML |
974 | static struct omap_hwmod omap44xx_fdif_hwmod = { |
975 | .name = "fdif", | |
976 | .class = &omap44xx_fdif_hwmod_class, | |
977 | .clkdm_name = "iss_clkdm", | |
b050f688 ML |
978 | .main_clk = "fdif_fck", |
979 | .prcm = { | |
980 | .omap4 = { | |
981 | .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET, | |
982 | .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET, | |
983 | .modulemode = MODULEMODE_SWCTRL, | |
984 | }, | |
985 | }, | |
986 | }; | |
987 | ||
3b54baad BC |
988 | /* |
989 | * 'gpio' class | |
990 | * general purpose io module | |
991 | */ | |
992 | ||
993 | static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { | |
994 | .rev_offs = 0x0000, | |
f776471f | 995 | .sysc_offs = 0x0010, |
3b54baad | 996 | .syss_offs = 0x0114, |
0cfe8751 BC |
997 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
998 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
999 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
1000 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1001 | SIDLE_SMART_WKUP), | |
f776471f BC |
1002 | .sysc_fields = &omap_hwmod_sysc_type1, |
1003 | }; | |
1004 | ||
3b54baad | 1005 | static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { |
fe13471c BC |
1006 | .name = "gpio", |
1007 | .sysc = &omap44xx_gpio_sysc, | |
1008 | .rev = 2, | |
f776471f BC |
1009 | }; |
1010 | ||
3b54baad BC |
1011 | /* gpio dev_attr */ |
1012 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
fe13471c BC |
1013 | .bank_width = 32, |
1014 | .dbck_flag = true, | |
f776471f BC |
1015 | }; |
1016 | ||
3b54baad | 1017 | /* gpio1 */ |
3b54baad | 1018 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
b399bca8 | 1019 | { .role = "dbclk", .clk = "gpio1_dbclk" }, |
3b54baad BC |
1020 | }; |
1021 | ||
1022 | static struct omap_hwmod omap44xx_gpio1_hwmod = { | |
1023 | .name = "gpio1", | |
1024 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1025 | .clkdm_name = "l4_wkup_clkdm", |
17b7e7d3 | 1026 | .main_clk = "l4_wkup_clk_mux_ck", |
f776471f BC |
1027 | .prcm = { |
1028 | .omap4 = { | |
d0f0631d | 1029 | .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, |
27bb00b5 | 1030 | .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET, |
03fdefe5 | 1031 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1032 | }, |
1033 | }, | |
3b54baad BC |
1034 | .opt_clks = gpio1_opt_clks, |
1035 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
1036 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1037 | }; |
1038 | ||
3b54baad | 1039 | /* gpio2 */ |
3b54baad | 1040 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
b399bca8 | 1041 | { .role = "dbclk", .clk = "gpio2_dbclk" }, |
3b54baad BC |
1042 | }; |
1043 | ||
1044 | static struct omap_hwmod omap44xx_gpio2_hwmod = { | |
1045 | .name = "gpio2", | |
1046 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1047 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1048 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
17b7e7d3 | 1049 | .main_clk = "l4_div_ck", |
f776471f BC |
1050 | .prcm = { |
1051 | .omap4 = { | |
d0f0631d | 1052 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET, |
27bb00b5 | 1053 | .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET, |
03fdefe5 | 1054 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1055 | }, |
1056 | }, | |
3b54baad BC |
1057 | .opt_clks = gpio2_opt_clks, |
1058 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
1059 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1060 | }; |
1061 | ||
3b54baad | 1062 | /* gpio3 */ |
3b54baad | 1063 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
b399bca8 | 1064 | { .role = "dbclk", .clk = "gpio3_dbclk" }, |
3b54baad BC |
1065 | }; |
1066 | ||
1067 | static struct omap_hwmod omap44xx_gpio3_hwmod = { | |
1068 | .name = "gpio3", | |
1069 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1070 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1071 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
17b7e7d3 | 1072 | .main_clk = "l4_div_ck", |
f776471f BC |
1073 | .prcm = { |
1074 | .omap4 = { | |
d0f0631d | 1075 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET, |
27bb00b5 | 1076 | .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET, |
03fdefe5 | 1077 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1078 | }, |
1079 | }, | |
3b54baad BC |
1080 | .opt_clks = gpio3_opt_clks, |
1081 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
1082 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1083 | }; |
1084 | ||
3b54baad | 1085 | /* gpio4 */ |
3b54baad | 1086 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { |
b399bca8 | 1087 | { .role = "dbclk", .clk = "gpio4_dbclk" }, |
3b54baad BC |
1088 | }; |
1089 | ||
1090 | static struct omap_hwmod omap44xx_gpio4_hwmod = { | |
1091 | .name = "gpio4", | |
1092 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1093 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1094 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
17b7e7d3 | 1095 | .main_clk = "l4_div_ck", |
f776471f BC |
1096 | .prcm = { |
1097 | .omap4 = { | |
d0f0631d | 1098 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET, |
27bb00b5 | 1099 | .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET, |
03fdefe5 | 1100 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1101 | }, |
1102 | }, | |
3b54baad BC |
1103 | .opt_clks = gpio4_opt_clks, |
1104 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
1105 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1106 | }; |
1107 | ||
3b54baad | 1108 | /* gpio5 */ |
844a3b63 PW |
1109 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
1110 | { .role = "dbclk", .clk = "gpio5_dbclk" }, | |
55d2cb08 BC |
1111 | }; |
1112 | ||
3b54baad BC |
1113 | static struct omap_hwmod omap44xx_gpio5_hwmod = { |
1114 | .name = "gpio5", | |
1115 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1116 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1117 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
17b7e7d3 | 1118 | .main_clk = "l4_div_ck", |
55d2cb08 BC |
1119 | .prcm = { |
1120 | .omap4 = { | |
d0f0631d | 1121 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET, |
27bb00b5 | 1122 | .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET, |
03fdefe5 | 1123 | .modulemode = MODULEMODE_HWCTRL, |
55d2cb08 BC |
1124 | }, |
1125 | }, | |
3b54baad BC |
1126 | .opt_clks = gpio5_opt_clks, |
1127 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
1128 | .dev_attr = &gpio_dev_attr, | |
55d2cb08 BC |
1129 | }; |
1130 | ||
3b54baad | 1131 | /* gpio6 */ |
3b54baad | 1132 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
b399bca8 | 1133 | { .role = "dbclk", .clk = "gpio6_dbclk" }, |
db12ba53 BC |
1134 | }; |
1135 | ||
3b54baad BC |
1136 | static struct omap_hwmod omap44xx_gpio6_hwmod = { |
1137 | .name = "gpio6", | |
1138 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1139 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1140 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
17b7e7d3 | 1141 | .main_clk = "l4_div_ck", |
3b54baad BC |
1142 | .prcm = { |
1143 | .omap4 = { | |
d0f0631d | 1144 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET, |
27bb00b5 | 1145 | .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET, |
03fdefe5 | 1146 | .modulemode = MODULEMODE_HWCTRL, |
3b54baad | 1147 | }, |
db12ba53 | 1148 | }, |
3b54baad BC |
1149 | .opt_clks = gpio6_opt_clks, |
1150 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
1151 | .dev_attr = &gpio_dev_attr, | |
db12ba53 BC |
1152 | }; |
1153 | ||
eb42b5d3 BC |
1154 | /* |
1155 | * 'gpmc' class | |
1156 | * general purpose memory controller | |
1157 | */ | |
1158 | ||
1159 | static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = { | |
1160 | .rev_offs = 0x0000, | |
1161 | .sysc_offs = 0x0010, | |
1162 | .syss_offs = 0x0014, | |
1163 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
1164 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1165 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1166 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1167 | }; | |
1168 | ||
1169 | static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = { | |
1170 | .name = "gpmc", | |
1171 | .sysc = &omap44xx_gpmc_sysc, | |
1172 | }; | |
1173 | ||
1174 | /* gpmc */ | |
eb42b5d3 BC |
1175 | static struct omap_hwmod omap44xx_gpmc_hwmod = { |
1176 | .name = "gpmc", | |
1177 | .class = &omap44xx_gpmc_hwmod_class, | |
1178 | .clkdm_name = "l3_2_clkdm", | |
49484a60 AM |
1179 | /* |
1180 | * XXX HWMOD_INIT_NO_RESET should not be needed for this IP | |
1181 | * block. It is not being added due to any known bugs with | |
1182 | * resetting the GPMC IP block, but rather because any timings | |
1183 | * set by the bootloader are not being correctly programmed by | |
1184 | * the kernel from the board file or DT data. | |
1185 | * HWMOD_INIT_NO_RESET should be removed ASAP. | |
1186 | */ | |
eb42b5d3 | 1187 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
eb42b5d3 BC |
1188 | .prcm = { |
1189 | .omap4 = { | |
1190 | .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET, | |
1191 | .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET, | |
1192 | .modulemode = MODULEMODE_HWCTRL, | |
1193 | }, | |
1194 | }, | |
1195 | }; | |
1196 | ||
9def390e PW |
1197 | /* |
1198 | * 'gpu' class | |
1199 | * 2d/3d graphics accelerator | |
1200 | */ | |
1201 | ||
1202 | static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = { | |
1203 | .rev_offs = 0x1fc00, | |
1204 | .sysc_offs = 0x1fc10, | |
1205 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
1206 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1207 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
1208 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
1209 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1210 | }; | |
1211 | ||
1212 | static struct omap_hwmod_class omap44xx_gpu_hwmod_class = { | |
1213 | .name = "gpu", | |
1214 | .sysc = &omap44xx_gpu_sysc, | |
1215 | }; | |
1216 | ||
1217 | /* gpu */ | |
9def390e PW |
1218 | static struct omap_hwmod omap44xx_gpu_hwmod = { |
1219 | .name = "gpu", | |
1220 | .class = &omap44xx_gpu_hwmod_class, | |
1221 | .clkdm_name = "l3_gfx_clkdm", | |
ee877acd | 1222 | .main_clk = "sgx_clk_mux", |
9def390e PW |
1223 | .prcm = { |
1224 | .omap4 = { | |
1225 | .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET, | |
1226 | .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET, | |
1227 | .modulemode = MODULEMODE_SWCTRL, | |
1228 | }, | |
1229 | }, | |
1230 | }; | |
1231 | ||
a091c08e PW |
1232 | /* |
1233 | * 'hdq1w' class | |
1234 | * hdq / 1-wire serial interface controller | |
1235 | */ | |
1236 | ||
1237 | static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = { | |
1238 | .rev_offs = 0x0000, | |
1239 | .sysc_offs = 0x0014, | |
1240 | .syss_offs = 0x0018, | |
1241 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET | | |
1242 | SYSS_HAS_RESET_STATUS), | |
1243 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1244 | }; | |
1245 | ||
1246 | static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = { | |
1247 | .name = "hdq1w", | |
1248 | .sysc = &omap44xx_hdq1w_sysc, | |
1249 | }; | |
1250 | ||
1251 | /* hdq1w */ | |
a091c08e PW |
1252 | static struct omap_hwmod omap44xx_hdq1w_hwmod = { |
1253 | .name = "hdq1w", | |
1254 | .class = &omap44xx_hdq1w_hwmod_class, | |
1255 | .clkdm_name = "l4_per_clkdm", | |
1256 | .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ | |
17b7e7d3 | 1257 | .main_clk = "func_12m_fclk", |
a091c08e PW |
1258 | .prcm = { |
1259 | .omap4 = { | |
1260 | .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, | |
1261 | .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET, | |
1262 | .modulemode = MODULEMODE_SWCTRL, | |
1263 | }, | |
1264 | }, | |
1265 | }; | |
1266 | ||
407a6888 BC |
1267 | /* |
1268 | * 'hsi' class | |
1269 | * mipi high-speed synchronous serial interface (multichannel and full-duplex | |
1270 | * serial if) | |
1271 | */ | |
1272 | ||
1273 | static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = { | |
1274 | .rev_offs = 0x0000, | |
1275 | .sysc_offs = 0x0010, | |
1276 | .syss_offs = 0x0014, | |
1277 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | | |
1278 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
1279 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1280 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1281 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1282 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1283 | .sysc_fields = &omap_hwmod_sysc_type1, |
1284 | }; | |
1285 | ||
1286 | static struct omap_hwmod_class omap44xx_hsi_hwmod_class = { | |
1287 | .name = "hsi", | |
1288 | .sysc = &omap44xx_hsi_sysc, | |
1289 | }; | |
1290 | ||
1291 | /* hsi */ | |
407a6888 BC |
1292 | static struct omap_hwmod omap44xx_hsi_hwmod = { |
1293 | .name = "hsi", | |
1294 | .class = &omap44xx_hsi_hwmod_class, | |
a5322c6f | 1295 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 1296 | .main_clk = "hsi_fck", |
00fe610b | 1297 | .prcm = { |
407a6888 | 1298 | .omap4 = { |
d0f0631d | 1299 | .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET, |
27bb00b5 | 1300 | .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET, |
03fdefe5 | 1301 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1302 | }, |
1303 | }, | |
407a6888 BC |
1304 | }; |
1305 | ||
3b54baad BC |
1306 | /* |
1307 | * 'i2c' class | |
1308 | * multimaster high-speed i2c controller | |
1309 | */ | |
db12ba53 | 1310 | |
3b54baad BC |
1311 | static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { |
1312 | .sysc_offs = 0x0010, | |
1313 | .syss_offs = 0x0090, | |
1314 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1315 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 1316 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
1317 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1318 | SIDLE_SMART_WKUP), | |
3e47dc6a | 1319 | .clockact = CLOCKACT_TEST_ICLK, |
3b54baad | 1320 | .sysc_fields = &omap_hwmod_sysc_type1, |
db12ba53 BC |
1321 | }; |
1322 | ||
3b54baad | 1323 | static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { |
fe13471c BC |
1324 | .name = "i2c", |
1325 | .sysc = &omap44xx_i2c_sysc, | |
db791a75 | 1326 | .rev = OMAP_I2C_IP_VERSION_2, |
6d3c55fd | 1327 | .reset = &omap_i2c_reset, |
db12ba53 BC |
1328 | }; |
1329 | ||
4d4441a6 | 1330 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
972deb4f | 1331 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, |
4d4441a6 AG |
1332 | }; |
1333 | ||
3b54baad | 1334 | /* i2c1 */ |
3b54baad BC |
1335 | static struct omap_hwmod omap44xx_i2c1_hwmod = { |
1336 | .name = "i2c1", | |
1337 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1338 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1339 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
17b7e7d3 | 1340 | .main_clk = "func_96m_fclk", |
92b18d1c BC |
1341 | .prcm = { |
1342 | .omap4 = { | |
d0f0631d | 1343 | .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET, |
27bb00b5 | 1344 | .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET, |
03fdefe5 | 1345 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
1346 | }, |
1347 | }, | |
4d4441a6 | 1348 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
1349 | }; |
1350 | ||
3b54baad | 1351 | /* i2c2 */ |
3b54baad BC |
1352 | static struct omap_hwmod omap44xx_i2c2_hwmod = { |
1353 | .name = "i2c2", | |
1354 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1355 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1356 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
17b7e7d3 | 1357 | .main_clk = "func_96m_fclk", |
db12ba53 BC |
1358 | .prcm = { |
1359 | .omap4 = { | |
d0f0631d | 1360 | .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, |
27bb00b5 | 1361 | .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET, |
03fdefe5 | 1362 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
1363 | }, |
1364 | }, | |
4d4441a6 | 1365 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
1366 | }; |
1367 | ||
3b54baad | 1368 | /* i2c3 */ |
3b54baad BC |
1369 | static struct omap_hwmod omap44xx_i2c3_hwmod = { |
1370 | .name = "i2c3", | |
1371 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1372 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1373 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
17b7e7d3 | 1374 | .main_clk = "func_96m_fclk", |
db12ba53 BC |
1375 | .prcm = { |
1376 | .omap4 = { | |
d0f0631d | 1377 | .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET, |
27bb00b5 | 1378 | .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET, |
03fdefe5 | 1379 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
1380 | }, |
1381 | }, | |
4d4441a6 | 1382 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
1383 | }; |
1384 | ||
3b54baad | 1385 | /* i2c4 */ |
3b54baad BC |
1386 | static struct omap_hwmod omap44xx_i2c4_hwmod = { |
1387 | .name = "i2c4", | |
1388 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1389 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1390 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
17b7e7d3 | 1391 | .main_clk = "func_96m_fclk", |
92b18d1c BC |
1392 | .prcm = { |
1393 | .omap4 = { | |
d0f0631d | 1394 | .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET, |
27bb00b5 | 1395 | .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET, |
03fdefe5 | 1396 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
1397 | }, |
1398 | }, | |
4d4441a6 | 1399 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
1400 | }; |
1401 | ||
407a6888 BC |
1402 | /* |
1403 | * 'ipu' class | |
1404 | * imaging processor unit | |
1405 | */ | |
1406 | ||
1407 | static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { | |
1408 | .name = "ipu", | |
1409 | }; | |
1410 | ||
1411 | /* ipu */ | |
f2f5736c | 1412 | static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { |
407a6888 | 1413 | { .name = "cpu0", .rst_shift = 0 }, |
407a6888 | 1414 | { .name = "cpu1", .rst_shift = 1 }, |
407a6888 BC |
1415 | }; |
1416 | ||
407a6888 BC |
1417 | static struct omap_hwmod omap44xx_ipu_hwmod = { |
1418 | .name = "ipu", | |
1419 | .class = &omap44xx_ipu_hwmod_class, | |
a5322c6f | 1420 | .clkdm_name = "ducati_clkdm", |
407a6888 BC |
1421 | .rst_lines = omap44xx_ipu_resets, |
1422 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), | |
298ea44f | 1423 | .main_clk = "ducati_clk_mux_ck", |
00fe610b | 1424 | .prcm = { |
407a6888 | 1425 | .omap4 = { |
d0f0631d | 1426 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, |
eaac329d | 1427 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, |
27bb00b5 | 1428 | .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, |
03fdefe5 | 1429 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1430 | }, |
1431 | }, | |
407a6888 BC |
1432 | }; |
1433 | ||
1434 | /* | |
1435 | * 'iss' class | |
1436 | * external images sensor pixel data processor | |
1437 | */ | |
1438 | ||
1439 | static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { | |
1440 | .rev_offs = 0x0000, | |
1441 | .sysc_offs = 0x0010, | |
d99de7f5 FGL |
1442 | /* |
1443 | * ISS needs 100 OCP clk cycles delay after a softreset before | |
1444 | * accessing sysconfig again. | |
1445 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
1446 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
1447 | * | |
1448 | * TODO: Indicate errata when available. | |
1449 | */ | |
1450 | .srst_udelay = 2, | |
407a6888 BC |
1451 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | |
1452 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1453 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1454 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1455 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1456 | .sysc_fields = &omap_hwmod_sysc_type2, |
1457 | }; | |
1458 | ||
1459 | static struct omap_hwmod_class omap44xx_iss_hwmod_class = { | |
1460 | .name = "iss", | |
1461 | .sysc = &omap44xx_iss_sysc, | |
1462 | }; | |
1463 | ||
1464 | /* iss */ | |
407a6888 BC |
1465 | static struct omap_hwmod_opt_clk iss_opt_clks[] = { |
1466 | { .role = "ctrlclk", .clk = "iss_ctrlclk" }, | |
1467 | }; | |
1468 | ||
1469 | static struct omap_hwmod omap44xx_iss_hwmod = { | |
1470 | .name = "iss", | |
1471 | .class = &omap44xx_iss_hwmod_class, | |
a5322c6f | 1472 | .clkdm_name = "iss_clkdm", |
17b7e7d3 | 1473 | .main_clk = "ducati_clk_mux_ck", |
00fe610b | 1474 | .prcm = { |
407a6888 | 1475 | .omap4 = { |
d0f0631d | 1476 | .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, |
27bb00b5 | 1477 | .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET, |
03fdefe5 | 1478 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1479 | }, |
1480 | }, | |
1481 | .opt_clks = iss_opt_clks, | |
1482 | .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), | |
407a6888 BC |
1483 | }; |
1484 | ||
8f25bdc5 BC |
1485 | /* |
1486 | * 'iva' class | |
1487 | * multi-standard video encoder/decoder hardware accelerator | |
1488 | */ | |
1489 | ||
1490 | static struct omap_hwmod_class omap44xx_iva_hwmod_class = { | |
fe13471c | 1491 | .name = "iva", |
8f25bdc5 BC |
1492 | }; |
1493 | ||
1494 | /* iva */ | |
8f25bdc5 | 1495 | static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { |
8f25bdc5 | 1496 | { .name = "seq0", .rst_shift = 0 }, |
8f25bdc5 | 1497 | { .name = "seq1", .rst_shift = 1 }, |
f2f5736c | 1498 | { .name = "logic", .rst_shift = 2 }, |
8f25bdc5 BC |
1499 | }; |
1500 | ||
8f25bdc5 BC |
1501 | static struct omap_hwmod omap44xx_iva_hwmod = { |
1502 | .name = "iva", | |
1503 | .class = &omap44xx_iva_hwmod_class, | |
a5322c6f | 1504 | .clkdm_name = "ivahd_clkdm", |
8f25bdc5 BC |
1505 | .rst_lines = omap44xx_iva_resets, |
1506 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), | |
17b7e7d3 | 1507 | .main_clk = "dpll_iva_m5x2_ck", |
8f25bdc5 BC |
1508 | .prcm = { |
1509 | .omap4 = { | |
d0f0631d | 1510 | .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, |
eaac329d | 1511 | .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, |
27bb00b5 | 1512 | .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET, |
03fdefe5 | 1513 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
1514 | }, |
1515 | }, | |
8f25bdc5 BC |
1516 | }; |
1517 | ||
407a6888 BC |
1518 | /* |
1519 | * 'kbd' class | |
1520 | * keyboard controller | |
1521 | */ | |
1522 | ||
1523 | static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = { | |
1524 | .rev_offs = 0x0000, | |
1525 | .sysc_offs = 0x0010, | |
1526 | .syss_offs = 0x0014, | |
1527 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1528 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
1529 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1530 | SYSS_HAS_RESET_STATUS), | |
1531 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1532 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1533 | }; | |
1534 | ||
1535 | static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { | |
1536 | .name = "kbd", | |
1537 | .sysc = &omap44xx_kbd_sysc, | |
1538 | }; | |
1539 | ||
1540 | /* kbd */ | |
407a6888 BC |
1541 | static struct omap_hwmod omap44xx_kbd_hwmod = { |
1542 | .name = "kbd", | |
1543 | .class = &omap44xx_kbd_hwmod_class, | |
a5322c6f | 1544 | .clkdm_name = "l4_wkup_clkdm", |
17b7e7d3 | 1545 | .main_clk = "sys_32k_ck", |
00fe610b | 1546 | .prcm = { |
407a6888 | 1547 | .omap4 = { |
d0f0631d | 1548 | .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, |
27bb00b5 | 1549 | .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET, |
03fdefe5 | 1550 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1551 | }, |
1552 | }, | |
407a6888 BC |
1553 | }; |
1554 | ||
ec5df927 BC |
1555 | /* |
1556 | * 'mailbox' class | |
1557 | * mailbox module allowing communication between the on-chip processors using a | |
1558 | * queued mailbox-interrupt mechanism. | |
1559 | */ | |
1560 | ||
1561 | static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = { | |
1562 | .rev_offs = 0x0000, | |
1563 | .sysc_offs = 0x0010, | |
1564 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1565 | SYSC_HAS_SOFTRESET), | |
1566 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1567 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1568 | }; | |
1569 | ||
1570 | static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { | |
1571 | .name = "mailbox", | |
1572 | .sysc = &omap44xx_mailbox_sysc, | |
1573 | }; | |
1574 | ||
1575 | /* mailbox */ | |
ec5df927 BC |
1576 | static struct omap_hwmod omap44xx_mailbox_hwmod = { |
1577 | .name = "mailbox", | |
1578 | .class = &omap44xx_mailbox_hwmod_class, | |
a5322c6f | 1579 | .clkdm_name = "l4_cfg_clkdm", |
00fe610b | 1580 | .prcm = { |
ec5df927 | 1581 | .omap4 = { |
d0f0631d | 1582 | .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, |
27bb00b5 | 1583 | .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, |
ec5df927 BC |
1584 | }, |
1585 | }, | |
ec5df927 BC |
1586 | }; |
1587 | ||
896d4e98 BC |
1588 | /* |
1589 | * 'mcasp' class | |
1590 | * multi-channel audio serial port controller | |
1591 | */ | |
1592 | ||
1593 | /* The IP is not compliant to type1 / type2 scheme */ | |
1594 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = { | |
1595 | .sidle_shift = 0, | |
1596 | }; | |
1597 | ||
1598 | static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = { | |
1599 | .sysc_offs = 0x0004, | |
1600 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
1601 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1602 | SIDLE_SMART_WKUP), | |
1603 | .sysc_fields = &omap_hwmod_sysc_type_mcasp, | |
1604 | }; | |
1605 | ||
1606 | static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = { | |
1607 | .name = "mcasp", | |
1608 | .sysc = &omap44xx_mcasp_sysc, | |
1609 | }; | |
1610 | ||
1611 | /* mcasp */ | |
896d4e98 BC |
1612 | static struct omap_hwmod omap44xx_mcasp_hwmod = { |
1613 | .name = "mcasp", | |
1614 | .class = &omap44xx_mcasp_hwmod_class, | |
1615 | .clkdm_name = "abe_clkdm", | |
ee877acd | 1616 | .main_clk = "func_mcasp_abe_gfclk", |
896d4e98 BC |
1617 | .prcm = { |
1618 | .omap4 = { | |
1619 | .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET, | |
1620 | .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET, | |
1621 | .modulemode = MODULEMODE_SWCTRL, | |
1622 | }, | |
1623 | }, | |
1624 | }; | |
1625 | ||
4ddff493 BC |
1626 | /* |
1627 | * 'mcbsp' class | |
1628 | * multi channel buffered serial port controller | |
1629 | */ | |
1630 | ||
1631 | static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { | |
1632 | .sysc_offs = 0x008c, | |
1633 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
1634 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1635 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1636 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1637 | }; | |
1638 | ||
1639 | static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { | |
1640 | .name = "mcbsp", | |
1641 | .sysc = &omap44xx_mcbsp_sysc, | |
cb7e9ded | 1642 | .rev = MCBSP_CONFIG_TYPE4, |
4ddff493 BC |
1643 | }; |
1644 | ||
1645 | /* mcbsp1 */ | |
503d0ea2 PW |
1646 | static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { |
1647 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 1648 | { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" }, |
503d0ea2 PW |
1649 | }; |
1650 | ||
4ddff493 BC |
1651 | static struct omap_hwmod omap44xx_mcbsp1_hwmod = { |
1652 | .name = "mcbsp1", | |
1653 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1654 | .clkdm_name = "abe_clkdm", |
ee877acd | 1655 | .main_clk = "func_mcbsp1_gfclk", |
4ddff493 BC |
1656 | .prcm = { |
1657 | .omap4 = { | |
d0f0631d | 1658 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, |
27bb00b5 | 1659 | .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET, |
03fdefe5 | 1660 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1661 | }, |
1662 | }, | |
503d0ea2 PW |
1663 | .opt_clks = mcbsp1_opt_clks, |
1664 | .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks), | |
4ddff493 BC |
1665 | }; |
1666 | ||
1667 | /* mcbsp2 */ | |
844a3b63 PW |
1668 | static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { |
1669 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 1670 | { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" }, |
503d0ea2 PW |
1671 | }; |
1672 | ||
4ddff493 BC |
1673 | static struct omap_hwmod omap44xx_mcbsp2_hwmod = { |
1674 | .name = "mcbsp2", | |
1675 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1676 | .clkdm_name = "abe_clkdm", |
ee877acd | 1677 | .main_clk = "func_mcbsp2_gfclk", |
4ddff493 BC |
1678 | .prcm = { |
1679 | .omap4 = { | |
d0f0631d | 1680 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, |
27bb00b5 | 1681 | .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET, |
03fdefe5 | 1682 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1683 | }, |
1684 | }, | |
503d0ea2 PW |
1685 | .opt_clks = mcbsp2_opt_clks, |
1686 | .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks), | |
4ddff493 BC |
1687 | }; |
1688 | ||
1689 | /* mcbsp3 */ | |
503d0ea2 PW |
1690 | static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { |
1691 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 1692 | { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" }, |
503d0ea2 PW |
1693 | }; |
1694 | ||
4ddff493 BC |
1695 | static struct omap_hwmod omap44xx_mcbsp3_hwmod = { |
1696 | .name = "mcbsp3", | |
1697 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1698 | .clkdm_name = "abe_clkdm", |
ee877acd | 1699 | .main_clk = "func_mcbsp3_gfclk", |
4ddff493 BC |
1700 | .prcm = { |
1701 | .omap4 = { | |
d0f0631d | 1702 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, |
27bb00b5 | 1703 | .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET, |
03fdefe5 | 1704 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1705 | }, |
1706 | }, | |
503d0ea2 PW |
1707 | .opt_clks = mcbsp3_opt_clks, |
1708 | .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks), | |
4ddff493 BC |
1709 | }; |
1710 | ||
1711 | /* mcbsp4 */ | |
503d0ea2 PW |
1712 | static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { |
1713 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 1714 | { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" }, |
503d0ea2 PW |
1715 | }; |
1716 | ||
4ddff493 BC |
1717 | static struct omap_hwmod omap44xx_mcbsp4_hwmod = { |
1718 | .name = "mcbsp4", | |
1719 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1720 | .clkdm_name = "l4_per_clkdm", |
ee877acd | 1721 | .main_clk = "per_mcbsp4_gfclk", |
4ddff493 BC |
1722 | .prcm = { |
1723 | .omap4 = { | |
d0f0631d | 1724 | .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, |
27bb00b5 | 1725 | .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET, |
03fdefe5 | 1726 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1727 | }, |
1728 | }, | |
503d0ea2 PW |
1729 | .opt_clks = mcbsp4_opt_clks, |
1730 | .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks), | |
4ddff493 BC |
1731 | }; |
1732 | ||
407a6888 BC |
1733 | /* |
1734 | * 'mcpdm' class | |
1735 | * multi channel pdm controller (proprietary interface with phoenix power | |
1736 | * ic) | |
1737 | */ | |
1738 | ||
1739 | static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = { | |
1740 | .rev_offs = 0x0000, | |
1741 | .sysc_offs = 0x0010, | |
1742 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
1743 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1744 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1745 | SIDLE_SMART_WKUP), | |
1746 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1747 | }; | |
1748 | ||
1749 | static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { | |
1750 | .name = "mcpdm", | |
1751 | .sysc = &omap44xx_mcpdm_sysc, | |
1752 | }; | |
1753 | ||
1754 | /* mcpdm */ | |
407a6888 BC |
1755 | static struct omap_hwmod omap44xx_mcpdm_hwmod = { |
1756 | .name = "mcpdm", | |
1757 | .class = &omap44xx_mcpdm_hwmod_class, | |
a5322c6f | 1758 | .clkdm_name = "abe_clkdm", |
bc05244e PW |
1759 | /* |
1760 | * It's suspected that the McPDM requires an off-chip main | |
1761 | * functional clock, controlled via I2C. This IP block is | |
1762 | * currently reset very early during boot, before I2C is | |
1763 | * available, so it doesn't seem that we have any choice in | |
1764 | * the kernel other than to avoid resetting it. | |
12d82e4b PU |
1765 | * |
1766 | * Also, McPDM needs to be configured to NO_IDLE mode when it | |
1767 | * is in used otherwise vital clocks will be gated which | |
1768 | * results 'slow motion' audio playback. | |
bc05244e | 1769 | */ |
12d82e4b | 1770 | .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE, |
17b7e7d3 | 1771 | .main_clk = "pad_clks_ck", |
00fe610b | 1772 | .prcm = { |
407a6888 | 1773 | .omap4 = { |
d0f0631d | 1774 | .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, |
27bb00b5 | 1775 | .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET, |
03fdefe5 | 1776 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1777 | }, |
1778 | }, | |
407a6888 BC |
1779 | }; |
1780 | ||
9bcbd7f0 BC |
1781 | /* |
1782 | * 'mcspi' class | |
1783 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
1784 | * bus | |
1785 | */ | |
1786 | ||
1787 | static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = { | |
1788 | .rev_offs = 0x0000, | |
1789 | .sysc_offs = 0x0010, | |
1790 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
1791 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1792 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1793 | SIDLE_SMART_WKUP), | |
1794 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1795 | }; | |
1796 | ||
1797 | static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { | |
1798 | .name = "mcspi", | |
1799 | .sysc = &omap44xx_mcspi_sysc, | |
905a74d9 | 1800 | .rev = OMAP4_MCSPI_REV, |
9bcbd7f0 BC |
1801 | }; |
1802 | ||
1803 | /* mcspi1 */ | |
9bcbd7f0 BC |
1804 | static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { |
1805 | { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, | |
1806 | { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, | |
1807 | { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START }, | |
1808 | { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START }, | |
1809 | { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START }, | |
1810 | { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, | |
1811 | { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, | |
1812 | { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1813 | { .dma_req = -1 } |
9bcbd7f0 BC |
1814 | }; |
1815 | ||
905a74d9 BC |
1816 | /* mcspi1 dev_attr */ |
1817 | static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { | |
1818 | .num_chipselect = 4, | |
1819 | }; | |
1820 | ||
9bcbd7f0 BC |
1821 | static struct omap_hwmod omap44xx_mcspi1_hwmod = { |
1822 | .name = "mcspi1", | |
1823 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 1824 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 1825 | .sdma_reqs = omap44xx_mcspi1_sdma_reqs, |
17b7e7d3 | 1826 | .main_clk = "func_48m_fclk", |
9bcbd7f0 BC |
1827 | .prcm = { |
1828 | .omap4 = { | |
d0f0631d | 1829 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, |
27bb00b5 | 1830 | .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET, |
03fdefe5 | 1831 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
1832 | }, |
1833 | }, | |
905a74d9 | 1834 | .dev_attr = &mcspi1_dev_attr, |
9bcbd7f0 BC |
1835 | }; |
1836 | ||
1837 | /* mcspi2 */ | |
9bcbd7f0 BC |
1838 | static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { |
1839 | { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, | |
1840 | { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, | |
1841 | { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, | |
1842 | { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1843 | { .dma_req = -1 } |
9bcbd7f0 BC |
1844 | }; |
1845 | ||
905a74d9 BC |
1846 | /* mcspi2 dev_attr */ |
1847 | static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { | |
1848 | .num_chipselect = 2, | |
1849 | }; | |
1850 | ||
9bcbd7f0 BC |
1851 | static struct omap_hwmod omap44xx_mcspi2_hwmod = { |
1852 | .name = "mcspi2", | |
1853 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 1854 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 1855 | .sdma_reqs = omap44xx_mcspi2_sdma_reqs, |
17b7e7d3 | 1856 | .main_clk = "func_48m_fclk", |
9bcbd7f0 BC |
1857 | .prcm = { |
1858 | .omap4 = { | |
d0f0631d | 1859 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, |
27bb00b5 | 1860 | .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET, |
03fdefe5 | 1861 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
1862 | }, |
1863 | }, | |
905a74d9 | 1864 | .dev_attr = &mcspi2_dev_attr, |
9bcbd7f0 BC |
1865 | }; |
1866 | ||
1867 | /* mcspi3 */ | |
9bcbd7f0 BC |
1868 | static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { |
1869 | { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, | |
1870 | { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, | |
1871 | { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, | |
1872 | { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1873 | { .dma_req = -1 } |
9bcbd7f0 BC |
1874 | }; |
1875 | ||
905a74d9 BC |
1876 | /* mcspi3 dev_attr */ |
1877 | static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { | |
1878 | .num_chipselect = 2, | |
1879 | }; | |
1880 | ||
9bcbd7f0 BC |
1881 | static struct omap_hwmod omap44xx_mcspi3_hwmod = { |
1882 | .name = "mcspi3", | |
1883 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 1884 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 1885 | .sdma_reqs = omap44xx_mcspi3_sdma_reqs, |
17b7e7d3 | 1886 | .main_clk = "func_48m_fclk", |
9bcbd7f0 BC |
1887 | .prcm = { |
1888 | .omap4 = { | |
d0f0631d | 1889 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, |
27bb00b5 | 1890 | .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET, |
03fdefe5 | 1891 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
1892 | }, |
1893 | }, | |
905a74d9 | 1894 | .dev_attr = &mcspi3_dev_attr, |
9bcbd7f0 BC |
1895 | }; |
1896 | ||
1897 | /* mcspi4 */ | |
9bcbd7f0 BC |
1898 | static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { |
1899 | { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, | |
1900 | { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1901 | { .dma_req = -1 } |
9bcbd7f0 BC |
1902 | }; |
1903 | ||
905a74d9 BC |
1904 | /* mcspi4 dev_attr */ |
1905 | static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { | |
1906 | .num_chipselect = 1, | |
1907 | }; | |
1908 | ||
9bcbd7f0 BC |
1909 | static struct omap_hwmod omap44xx_mcspi4_hwmod = { |
1910 | .name = "mcspi4", | |
1911 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 1912 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 1913 | .sdma_reqs = omap44xx_mcspi4_sdma_reqs, |
17b7e7d3 | 1914 | .main_clk = "func_48m_fclk", |
9bcbd7f0 BC |
1915 | .prcm = { |
1916 | .omap4 = { | |
d0f0631d | 1917 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, |
27bb00b5 | 1918 | .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET, |
03fdefe5 | 1919 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
1920 | }, |
1921 | }, | |
905a74d9 | 1922 | .dev_attr = &mcspi4_dev_attr, |
9bcbd7f0 BC |
1923 | }; |
1924 | ||
407a6888 BC |
1925 | /* |
1926 | * 'mmc' class | |
1927 | * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller | |
1928 | */ | |
1929 | ||
1930 | static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = { | |
1931 | .rev_offs = 0x0000, | |
1932 | .sysc_offs = 0x0010, | |
1933 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
1934 | SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1935 | SYSC_HAS_SOFTRESET), | |
1936 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1937 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1938 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1939 | .sysc_fields = &omap_hwmod_sysc_type2, |
1940 | }; | |
1941 | ||
1942 | static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { | |
1943 | .name = "mmc", | |
1944 | .sysc = &omap44xx_mmc_sysc, | |
1945 | }; | |
1946 | ||
1947 | /* mmc1 */ | |
407a6888 BC |
1948 | static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { |
1949 | { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, | |
1950 | { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1951 | { .dma_req = -1 } |
407a6888 BC |
1952 | }; |
1953 | ||
6ab8946f KK |
1954 | /* mmc1 dev_attr */ |
1955 | static struct omap_mmc_dev_attr mmc1_dev_attr = { | |
1956 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
1957 | }; | |
1958 | ||
407a6888 BC |
1959 | static struct omap_hwmod omap44xx_mmc1_hwmod = { |
1960 | .name = "mmc1", | |
1961 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 1962 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 1963 | .sdma_reqs = omap44xx_mmc1_sdma_reqs, |
ee877acd | 1964 | .main_clk = "hsmmc1_fclk", |
00fe610b | 1965 | .prcm = { |
407a6888 | 1966 | .omap4 = { |
d0f0631d | 1967 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET, |
27bb00b5 | 1968 | .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET, |
03fdefe5 | 1969 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1970 | }, |
1971 | }, | |
6ab8946f | 1972 | .dev_attr = &mmc1_dev_attr, |
407a6888 BC |
1973 | }; |
1974 | ||
1975 | /* mmc2 */ | |
407a6888 BC |
1976 | static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { |
1977 | { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, | |
1978 | { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1979 | { .dma_req = -1 } |
407a6888 BC |
1980 | }; |
1981 | ||
407a6888 BC |
1982 | static struct omap_hwmod omap44xx_mmc2_hwmod = { |
1983 | .name = "mmc2", | |
1984 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 1985 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 1986 | .sdma_reqs = omap44xx_mmc2_sdma_reqs, |
ee877acd | 1987 | .main_clk = "hsmmc2_fclk", |
00fe610b | 1988 | .prcm = { |
407a6888 | 1989 | .omap4 = { |
d0f0631d | 1990 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET, |
27bb00b5 | 1991 | .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET, |
03fdefe5 | 1992 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1993 | }, |
1994 | }, | |
407a6888 BC |
1995 | }; |
1996 | ||
1997 | /* mmc3 */ | |
407a6888 BC |
1998 | static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { |
1999 | { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, | |
2000 | { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2001 | { .dma_req = -1 } |
407a6888 BC |
2002 | }; |
2003 | ||
407a6888 BC |
2004 | static struct omap_hwmod omap44xx_mmc3_hwmod = { |
2005 | .name = "mmc3", | |
2006 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2007 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2008 | .sdma_reqs = omap44xx_mmc3_sdma_reqs, |
17b7e7d3 | 2009 | .main_clk = "func_48m_fclk", |
00fe610b | 2010 | .prcm = { |
407a6888 | 2011 | .omap4 = { |
d0f0631d | 2012 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET, |
27bb00b5 | 2013 | .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET, |
03fdefe5 | 2014 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2015 | }, |
2016 | }, | |
407a6888 BC |
2017 | }; |
2018 | ||
2019 | /* mmc4 */ | |
407a6888 BC |
2020 | static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { |
2021 | { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, | |
2022 | { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2023 | { .dma_req = -1 } |
407a6888 BC |
2024 | }; |
2025 | ||
407a6888 BC |
2026 | static struct omap_hwmod omap44xx_mmc4_hwmod = { |
2027 | .name = "mmc4", | |
2028 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2029 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2030 | .sdma_reqs = omap44xx_mmc4_sdma_reqs, |
17b7e7d3 | 2031 | .main_clk = "func_48m_fclk", |
00fe610b | 2032 | .prcm = { |
407a6888 | 2033 | .omap4 = { |
d0f0631d | 2034 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET, |
27bb00b5 | 2035 | .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET, |
03fdefe5 | 2036 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2037 | }, |
2038 | }, | |
407a6888 BC |
2039 | }; |
2040 | ||
2041 | /* mmc5 */ | |
407a6888 BC |
2042 | static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { |
2043 | { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, | |
2044 | { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2045 | { .dma_req = -1 } |
407a6888 BC |
2046 | }; |
2047 | ||
407a6888 BC |
2048 | static struct omap_hwmod omap44xx_mmc5_hwmod = { |
2049 | .name = "mmc5", | |
2050 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2051 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2052 | .sdma_reqs = omap44xx_mmc5_sdma_reqs, |
17b7e7d3 | 2053 | .main_clk = "func_48m_fclk", |
00fe610b | 2054 | .prcm = { |
407a6888 | 2055 | .omap4 = { |
d0f0631d | 2056 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET, |
27bb00b5 | 2057 | .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET, |
03fdefe5 | 2058 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2059 | }, |
2060 | }, | |
407a6888 BC |
2061 | }; |
2062 | ||
230844db ORL |
2063 | /* |
2064 | * 'mmu' class | |
2065 | * The memory management unit performs virtual to physical address translation | |
2066 | * for its requestors. | |
2067 | */ | |
2068 | ||
2069 | static struct omap_hwmod_class_sysconfig mmu_sysc = { | |
2070 | .rev_offs = 0x000, | |
2071 | .sysc_offs = 0x010, | |
2072 | .syss_offs = 0x014, | |
2073 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
2074 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
2075 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2076 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2077 | }; | |
2078 | ||
2079 | static struct omap_hwmod_class omap44xx_mmu_hwmod_class = { | |
2080 | .name = "mmu", | |
2081 | .sysc = &mmu_sysc, | |
2082 | }; | |
2083 | ||
2084 | /* mmu ipu */ | |
2085 | ||
2086 | static struct omap_mmu_dev_attr mmu_ipu_dev_attr = { | |
230844db ORL |
2087 | .nr_tlb_entries = 32, |
2088 | }; | |
2089 | ||
2090 | static struct omap_hwmod omap44xx_mmu_ipu_hwmod; | |
230844db ORL |
2091 | static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = { |
2092 | { .name = "mmu_cache", .rst_shift = 2 }, | |
2093 | }; | |
2094 | ||
2095 | static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = { | |
2096 | { | |
2097 | .pa_start = 0x55082000, | |
2098 | .pa_end = 0x550820ff, | |
2099 | .flags = ADDR_TYPE_RT, | |
2100 | }, | |
2101 | { } | |
2102 | }; | |
2103 | ||
2104 | /* l3_main_2 -> mmu_ipu */ | |
2105 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = { | |
2106 | .master = &omap44xx_l3_main_2_hwmod, | |
2107 | .slave = &omap44xx_mmu_ipu_hwmod, | |
2108 | .clk = "l3_div_ck", | |
2109 | .addr = omap44xx_mmu_ipu_addrs, | |
2110 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2111 | }; | |
2112 | ||
2113 | static struct omap_hwmod omap44xx_mmu_ipu_hwmod = { | |
2114 | .name = "mmu_ipu", | |
2115 | .class = &omap44xx_mmu_hwmod_class, | |
2116 | .clkdm_name = "ducati_clkdm", | |
230844db ORL |
2117 | .rst_lines = omap44xx_mmu_ipu_resets, |
2118 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets), | |
2119 | .main_clk = "ducati_clk_mux_ck", | |
2120 | .prcm = { | |
2121 | .omap4 = { | |
2122 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, | |
2123 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, | |
2124 | .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, | |
2125 | .modulemode = MODULEMODE_HWCTRL, | |
2126 | }, | |
2127 | }, | |
2128 | .dev_attr = &mmu_ipu_dev_attr, | |
2129 | }; | |
2130 | ||
2131 | /* mmu dsp */ | |
2132 | ||
2133 | static struct omap_mmu_dev_attr mmu_dsp_dev_attr = { | |
230844db ORL |
2134 | .nr_tlb_entries = 32, |
2135 | }; | |
2136 | ||
2137 | static struct omap_hwmod omap44xx_mmu_dsp_hwmod; | |
230844db ORL |
2138 | static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = { |
2139 | { .name = "mmu_cache", .rst_shift = 1 }, | |
2140 | }; | |
2141 | ||
2142 | static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = { | |
2143 | { | |
2144 | .pa_start = 0x4a066000, | |
2145 | .pa_end = 0x4a0660ff, | |
2146 | .flags = ADDR_TYPE_RT, | |
2147 | }, | |
2148 | { } | |
2149 | }; | |
2150 | ||
2151 | /* l4_cfg -> dsp */ | |
2152 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = { | |
2153 | .master = &omap44xx_l4_cfg_hwmod, | |
2154 | .slave = &omap44xx_mmu_dsp_hwmod, | |
2155 | .clk = "l4_div_ck", | |
2156 | .addr = omap44xx_mmu_dsp_addrs, | |
2157 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2158 | }; | |
2159 | ||
2160 | static struct omap_hwmod omap44xx_mmu_dsp_hwmod = { | |
2161 | .name = "mmu_dsp", | |
2162 | .class = &omap44xx_mmu_hwmod_class, | |
2163 | .clkdm_name = "tesla_clkdm", | |
230844db ORL |
2164 | .rst_lines = omap44xx_mmu_dsp_resets, |
2165 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets), | |
2166 | .main_clk = "dpll_iva_m4x2_ck", | |
2167 | .prcm = { | |
2168 | .omap4 = { | |
2169 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, | |
2170 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, | |
2171 | .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, | |
2172 | .modulemode = MODULEMODE_HWCTRL, | |
2173 | }, | |
2174 | }, | |
2175 | .dev_attr = &mmu_dsp_dev_attr, | |
2176 | }; | |
2177 | ||
3b54baad BC |
2178 | /* |
2179 | * 'mpu' class | |
2180 | * mpu sub-system | |
2181 | */ | |
2182 | ||
2183 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { | |
fe13471c | 2184 | .name = "mpu", |
db12ba53 BC |
2185 | }; |
2186 | ||
3b54baad | 2187 | /* mpu */ |
3b54baad BC |
2188 | static struct omap_hwmod omap44xx_mpu_hwmod = { |
2189 | .name = "mpu", | |
2190 | .class = &omap44xx_mpu_hwmod_class, | |
a5322c6f | 2191 | .clkdm_name = "mpuss_clkdm", |
b2eb0002 | 2192 | .flags = HWMOD_INIT_NO_IDLE, |
3b54baad | 2193 | .main_clk = "dpll_mpu_m2_ck", |
db12ba53 BC |
2194 | .prcm = { |
2195 | .omap4 = { | |
d0f0631d | 2196 | .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 2197 | .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, |
db12ba53 BC |
2198 | }, |
2199 | }, | |
db12ba53 BC |
2200 | }; |
2201 | ||
e17f18c0 PW |
2202 | /* |
2203 | * 'ocmc_ram' class | |
2204 | * top-level core on-chip ram | |
2205 | */ | |
2206 | ||
2207 | static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = { | |
2208 | .name = "ocmc_ram", | |
2209 | }; | |
2210 | ||
2211 | /* ocmc_ram */ | |
2212 | static struct omap_hwmod omap44xx_ocmc_ram_hwmod = { | |
2213 | .name = "ocmc_ram", | |
2214 | .class = &omap44xx_ocmc_ram_hwmod_class, | |
2215 | .clkdm_name = "l3_2_clkdm", | |
2216 | .prcm = { | |
2217 | .omap4 = { | |
2218 | .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET, | |
2219 | .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET, | |
2220 | }, | |
2221 | }, | |
2222 | }; | |
2223 | ||
0c668875 BC |
2224 | /* |
2225 | * 'ocp2scp' class | |
2226 | * bridge to transform ocp interface protocol to scp (serial control port) | |
2227 | * protocol | |
2228 | */ | |
2229 | ||
33c976ec BC |
2230 | static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = { |
2231 | .rev_offs = 0x0000, | |
2232 | .sysc_offs = 0x0010, | |
2233 | .syss_offs = 0x0014, | |
2234 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
2235 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
2236 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2237 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2238 | }; | |
2239 | ||
0c668875 BC |
2240 | static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = { |
2241 | .name = "ocp2scp", | |
33c976ec | 2242 | .sysc = &omap44xx_ocp2scp_sysc, |
0c668875 BC |
2243 | }; |
2244 | ||
2245 | /* ocp2scp_usb_phy */ | |
0c668875 BC |
2246 | static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { |
2247 | .name = "ocp2scp_usb_phy", | |
2248 | .class = &omap44xx_ocp2scp_hwmod_class, | |
2249 | .clkdm_name = "l3_init_clkdm", | |
f4d7a536 KVA |
2250 | /* |
2251 | * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP | |
2252 | * block as an "optional clock," and normally should never be | |
2253 | * specified as the main_clk for an OMAP IP block. However it | |
2254 | * turns out that this clock is actually the main clock for | |
2255 | * the ocp2scp_usb_phy IP block: | |
2256 | * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html | |
2257 | * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems | |
2258 | * to be the best workaround. | |
2259 | */ | |
2260 | .main_clk = "ocp2scp_usb_phy_phy_48m", | |
0c668875 BC |
2261 | .prcm = { |
2262 | .omap4 = { | |
2263 | .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, | |
2264 | .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET, | |
2265 | .modulemode = MODULEMODE_HWCTRL, | |
2266 | }, | |
2267 | }, | |
0c668875 BC |
2268 | }; |
2269 | ||
794b480a PW |
2270 | /* |
2271 | * 'prcm' class | |
2272 | * power and reset manager (part of the prcm infrastructure) + clock manager 2 | |
2273 | * + clock manager 1 (in always on power domain) + local prm in mpu | |
2274 | */ | |
2275 | ||
2276 | static struct omap_hwmod_class omap44xx_prcm_hwmod_class = { | |
2277 | .name = "prcm", | |
2278 | }; | |
2279 | ||
2280 | /* prcm_mpu */ | |
2281 | static struct omap_hwmod omap44xx_prcm_mpu_hwmod = { | |
2282 | .name = "prcm_mpu", | |
2283 | .class = &omap44xx_prcm_hwmod_class, | |
2284 | .clkdm_name = "l4_wkup_clkdm", | |
53cce97c | 2285 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
2286 | .prcm = { |
2287 | .omap4 = { | |
2288 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2289 | }, | |
2290 | }, | |
794b480a PW |
2291 | }; |
2292 | ||
2293 | /* cm_core_aon */ | |
2294 | static struct omap_hwmod omap44xx_cm_core_aon_hwmod = { | |
2295 | .name = "cm_core_aon", | |
2296 | .class = &omap44xx_prcm_hwmod_class, | |
53cce97c | 2297 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
2298 | .prcm = { |
2299 | .omap4 = { | |
2300 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2301 | }, | |
2302 | }, | |
794b480a PW |
2303 | }; |
2304 | ||
2305 | /* cm_core */ | |
2306 | static struct omap_hwmod omap44xx_cm_core_hwmod = { | |
2307 | .name = "cm_core", | |
2308 | .class = &omap44xx_prcm_hwmod_class, | |
53cce97c | 2309 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
2310 | .prcm = { |
2311 | .omap4 = { | |
2312 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2313 | }, | |
2314 | }, | |
794b480a PW |
2315 | }; |
2316 | ||
2317 | /* prm */ | |
794b480a PW |
2318 | static struct omap_hwmod_rst_info omap44xx_prm_resets[] = { |
2319 | { .name = "rst_global_warm_sw", .rst_shift = 0 }, | |
2320 | { .name = "rst_global_cold_sw", .rst_shift = 1 }, | |
2321 | }; | |
2322 | ||
2323 | static struct omap_hwmod omap44xx_prm_hwmod = { | |
2324 | .name = "prm", | |
2325 | .class = &omap44xx_prcm_hwmod_class, | |
794b480a PW |
2326 | .rst_lines = omap44xx_prm_resets, |
2327 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets), | |
2328 | }; | |
2329 | ||
2330 | /* | |
2331 | * 'scrm' class | |
2332 | * system clock and reset manager | |
2333 | */ | |
2334 | ||
2335 | static struct omap_hwmod_class omap44xx_scrm_hwmod_class = { | |
2336 | .name = "scrm", | |
2337 | }; | |
2338 | ||
2339 | /* scrm */ | |
2340 | static struct omap_hwmod omap44xx_scrm_hwmod = { | |
2341 | .name = "scrm", | |
2342 | .class = &omap44xx_scrm_hwmod_class, | |
2343 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
2344 | .prcm = { |
2345 | .omap4 = { | |
2346 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2347 | }, | |
2348 | }, | |
794b480a PW |
2349 | }; |
2350 | ||
42b9e387 PW |
2351 | /* |
2352 | * 'sl2if' class | |
2353 | * shared level 2 memory interface | |
2354 | */ | |
2355 | ||
2356 | static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = { | |
2357 | .name = "sl2if", | |
2358 | }; | |
2359 | ||
2360 | /* sl2if */ | |
2361 | static struct omap_hwmod omap44xx_sl2if_hwmod = { | |
2362 | .name = "sl2if", | |
2363 | .class = &omap44xx_sl2if_hwmod_class, | |
2364 | .clkdm_name = "ivahd_clkdm", | |
2365 | .prcm = { | |
2366 | .omap4 = { | |
2367 | .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET, | |
2368 | .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET, | |
2369 | .modulemode = MODULEMODE_HWCTRL, | |
2370 | }, | |
2371 | }, | |
2372 | }; | |
2373 | ||
1e3b5e59 BC |
2374 | /* |
2375 | * 'slimbus' class | |
2376 | * bidirectional, multi-drop, multi-channel two-line serial interface between | |
2377 | * the device and external components | |
2378 | */ | |
2379 | ||
2380 | static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = { | |
2381 | .rev_offs = 0x0000, | |
2382 | .sysc_offs = 0x0010, | |
2383 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
2384 | SYSC_HAS_SOFTRESET), | |
2385 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2386 | SIDLE_SMART_WKUP), | |
2387 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2388 | }; | |
2389 | ||
2390 | static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = { | |
2391 | .name = "slimbus", | |
2392 | .sysc = &omap44xx_slimbus_sysc, | |
2393 | }; | |
2394 | ||
2395 | /* slimbus1 */ | |
1e3b5e59 BC |
2396 | static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = { |
2397 | { .role = "fclk_1", .clk = "slimbus1_fclk_1" }, | |
2398 | { .role = "fclk_0", .clk = "slimbus1_fclk_0" }, | |
2399 | { .role = "fclk_2", .clk = "slimbus1_fclk_2" }, | |
2400 | { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" }, | |
2401 | }; | |
2402 | ||
2403 | static struct omap_hwmod omap44xx_slimbus1_hwmod = { | |
2404 | .name = "slimbus1", | |
2405 | .class = &omap44xx_slimbus_hwmod_class, | |
2406 | .clkdm_name = "abe_clkdm", | |
1e3b5e59 BC |
2407 | .prcm = { |
2408 | .omap4 = { | |
2409 | .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET, | |
2410 | .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET, | |
2411 | .modulemode = MODULEMODE_SWCTRL, | |
2412 | }, | |
2413 | }, | |
2414 | .opt_clks = slimbus1_opt_clks, | |
2415 | .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks), | |
2416 | }; | |
2417 | ||
2418 | /* slimbus2 */ | |
1e3b5e59 BC |
2419 | static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = { |
2420 | { .role = "fclk_1", .clk = "slimbus2_fclk_1" }, | |
2421 | { .role = "fclk_0", .clk = "slimbus2_fclk_0" }, | |
2422 | { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" }, | |
2423 | }; | |
2424 | ||
2425 | static struct omap_hwmod omap44xx_slimbus2_hwmod = { | |
2426 | .name = "slimbus2", | |
2427 | .class = &omap44xx_slimbus_hwmod_class, | |
2428 | .clkdm_name = "l4_per_clkdm", | |
1e3b5e59 BC |
2429 | .prcm = { |
2430 | .omap4 = { | |
2431 | .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET, | |
2432 | .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET, | |
2433 | .modulemode = MODULEMODE_SWCTRL, | |
2434 | }, | |
2435 | }, | |
2436 | .opt_clks = slimbus2_opt_clks, | |
2437 | .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks), | |
2438 | }; | |
2439 | ||
1f6a717f BC |
2440 | /* |
2441 | * 'smartreflex' class | |
2442 | * smartreflex module (monitor silicon performance and outputs a measure of | |
2443 | * performance error) | |
2444 | */ | |
2445 | ||
2446 | /* The IP is not compliant to type1 / type2 scheme */ | |
2447 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { | |
2448 | .sidle_shift = 24, | |
2449 | .enwkup_shift = 26, | |
2450 | }; | |
2451 | ||
2452 | static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { | |
2453 | .sysc_offs = 0x0038, | |
2454 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), | |
2455 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2456 | SIDLE_SMART_WKUP), | |
2457 | .sysc_fields = &omap_hwmod_sysc_type_smartreflex, | |
2458 | }; | |
2459 | ||
2460 | static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { | |
fe13471c BC |
2461 | .name = "smartreflex", |
2462 | .sysc = &omap44xx_smartreflex_sysc, | |
2463 | .rev = 2, | |
1f6a717f BC |
2464 | }; |
2465 | ||
2466 | /* smartreflex_core */ | |
cea6b942 SG |
2467 | static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { |
2468 | .sensor_voltdm_name = "core", | |
2469 | }; | |
2470 | ||
1f6a717f BC |
2471 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { |
2472 | .name = "smartreflex_core", | |
2473 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2474 | .clkdm_name = "l4_ao_clkdm", |
212738a4 | 2475 | |
1f6a717f | 2476 | .main_clk = "smartreflex_core_fck", |
1f6a717f BC |
2477 | .prcm = { |
2478 | .omap4 = { | |
d0f0631d | 2479 | .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET, |
27bb00b5 | 2480 | .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET, |
03fdefe5 | 2481 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2482 | }, |
2483 | }, | |
cea6b942 | 2484 | .dev_attr = &smartreflex_core_dev_attr, |
1f6a717f BC |
2485 | }; |
2486 | ||
2487 | /* smartreflex_iva */ | |
cea6b942 SG |
2488 | static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { |
2489 | .sensor_voltdm_name = "iva", | |
2490 | }; | |
2491 | ||
1f6a717f BC |
2492 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { |
2493 | .name = "smartreflex_iva", | |
2494 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2495 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2496 | .main_clk = "smartreflex_iva_fck", |
1f6a717f BC |
2497 | .prcm = { |
2498 | .omap4 = { | |
d0f0631d | 2499 | .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET, |
27bb00b5 | 2500 | .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET, |
03fdefe5 | 2501 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2502 | }, |
2503 | }, | |
cea6b942 | 2504 | .dev_attr = &smartreflex_iva_dev_attr, |
1f6a717f BC |
2505 | }; |
2506 | ||
2507 | /* smartreflex_mpu */ | |
cea6b942 SG |
2508 | static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { |
2509 | .sensor_voltdm_name = "mpu", | |
2510 | }; | |
2511 | ||
1f6a717f BC |
2512 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { |
2513 | .name = "smartreflex_mpu", | |
2514 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2515 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2516 | .main_clk = "smartreflex_mpu_fck", |
1f6a717f BC |
2517 | .prcm = { |
2518 | .omap4 = { | |
d0f0631d | 2519 | .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 2520 | .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET, |
03fdefe5 | 2521 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2522 | }, |
2523 | }, | |
cea6b942 | 2524 | .dev_attr = &smartreflex_mpu_dev_attr, |
1f6a717f BC |
2525 | }; |
2526 | ||
d11c217f BC |
2527 | /* |
2528 | * 'spinlock' class | |
2529 | * spinlock provides hardware assistance for synchronizing the processes | |
2530 | * running on multiple processors | |
2531 | */ | |
2532 | ||
2533 | static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = { | |
2534 | .rev_offs = 0x0000, | |
2535 | .sysc_offs = 0x0010, | |
2536 | .syss_offs = 0x0014, | |
2537 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2538 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
2539 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
77319669 | 2540 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
d11c217f BC |
2541 | .sysc_fields = &omap_hwmod_sysc_type1, |
2542 | }; | |
2543 | ||
2544 | static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { | |
2545 | .name = "spinlock", | |
2546 | .sysc = &omap44xx_spinlock_sysc, | |
2547 | }; | |
2548 | ||
2549 | /* spinlock */ | |
d11c217f BC |
2550 | static struct omap_hwmod omap44xx_spinlock_hwmod = { |
2551 | .name = "spinlock", | |
2552 | .class = &omap44xx_spinlock_hwmod_class, | |
a5322c6f | 2553 | .clkdm_name = "l4_cfg_clkdm", |
d11c217f BC |
2554 | .prcm = { |
2555 | .omap4 = { | |
d0f0631d | 2556 | .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET, |
27bb00b5 | 2557 | .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, |
d11c217f BC |
2558 | }, |
2559 | }, | |
d11c217f BC |
2560 | }; |
2561 | ||
35d1a66a BC |
2562 | /* |
2563 | * 'timer' class | |
2564 | * general purpose timer module with accurate 1ms tick | |
2565 | * This class contains several variants: ['timer_1ms', 'timer'] | |
2566 | */ | |
2567 | ||
2568 | static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = { | |
2569 | .rev_offs = 0x0000, | |
2570 | .sysc_offs = 0x0010, | |
2571 | .syss_offs = 0x0014, | |
2572 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2573 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
2574 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
2575 | SYSS_HAS_RESET_STATUS), | |
2576 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
10759e82 | 2577 | .clockact = CLOCKACT_TEST_ICLK, |
35d1a66a BC |
2578 | .sysc_fields = &omap_hwmod_sysc_type1, |
2579 | }; | |
2580 | ||
2581 | static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = { | |
2582 | .name = "timer", | |
2583 | .sysc = &omap44xx_timer_1ms_sysc, | |
2584 | }; | |
2585 | ||
2586 | static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = { | |
2587 | .rev_offs = 0x0000, | |
2588 | .sysc_offs = 0x0010, | |
2589 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2590 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2591 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2592 | SIDLE_SMART_WKUP), | |
2593 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2594 | }; | |
2595 | ||
2596 | static struct omap_hwmod_class omap44xx_timer_hwmod_class = { | |
2597 | .name = "timer", | |
2598 | .sysc = &omap44xx_timer_sysc, | |
2599 | }; | |
2600 | ||
c345c8b0 TKD |
2601 | /* always-on timers dev attribute */ |
2602 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
2603 | .timer_capability = OMAP_TIMER_ALWON, | |
2604 | }; | |
2605 | ||
2606 | /* pwm timers dev attribute */ | |
2607 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
2608 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
2609 | }; | |
2610 | ||
5c3e4ec4 JH |
2611 | /* timers with DSP interrupt dev attribute */ |
2612 | static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = { | |
2613 | .timer_capability = OMAP_TIMER_HAS_DSP_IRQ, | |
2614 | }; | |
2615 | ||
2616 | /* pwm timers with DSP interrupt dev attribute */ | |
2617 | static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = { | |
2618 | .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM, | |
2619 | }; | |
2620 | ||
35d1a66a | 2621 | /* timer1 */ |
35d1a66a BC |
2622 | static struct omap_hwmod omap44xx_timer1_hwmod = { |
2623 | .name = "timer1", | |
2624 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2625 | .clkdm_name = "l4_wkup_clkdm", |
10759e82 | 2626 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
ee877acd | 2627 | .main_clk = "dmt1_clk_mux", |
35d1a66a BC |
2628 | .prcm = { |
2629 | .omap4 = { | |
d0f0631d | 2630 | .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, |
27bb00b5 | 2631 | .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET, |
03fdefe5 | 2632 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2633 | }, |
2634 | }, | |
c345c8b0 | 2635 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2636 | }; |
2637 | ||
2638 | /* timer2 */ | |
35d1a66a BC |
2639 | static struct omap_hwmod omap44xx_timer2_hwmod = { |
2640 | .name = "timer2", | |
2641 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2642 | .clkdm_name = "l4_per_clkdm", |
10759e82 | 2643 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
ee877acd | 2644 | .main_clk = "cm2_dm2_mux", |
35d1a66a BC |
2645 | .prcm = { |
2646 | .omap4 = { | |
d0f0631d | 2647 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, |
27bb00b5 | 2648 | .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET, |
03fdefe5 | 2649 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2650 | }, |
2651 | }, | |
35d1a66a BC |
2652 | }; |
2653 | ||
2654 | /* timer3 */ | |
35d1a66a BC |
2655 | static struct omap_hwmod omap44xx_timer3_hwmod = { |
2656 | .name = "timer3", | |
2657 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2658 | .clkdm_name = "l4_per_clkdm", |
ee877acd | 2659 | .main_clk = "cm2_dm3_mux", |
35d1a66a BC |
2660 | .prcm = { |
2661 | .omap4 = { | |
d0f0631d | 2662 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, |
27bb00b5 | 2663 | .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET, |
03fdefe5 | 2664 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2665 | }, |
2666 | }, | |
35d1a66a BC |
2667 | }; |
2668 | ||
2669 | /* timer4 */ | |
35d1a66a BC |
2670 | static struct omap_hwmod omap44xx_timer4_hwmod = { |
2671 | .name = "timer4", | |
2672 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2673 | .clkdm_name = "l4_per_clkdm", |
ee877acd | 2674 | .main_clk = "cm2_dm4_mux", |
35d1a66a BC |
2675 | .prcm = { |
2676 | .omap4 = { | |
d0f0631d | 2677 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, |
27bb00b5 | 2678 | .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET, |
03fdefe5 | 2679 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2680 | }, |
2681 | }, | |
35d1a66a BC |
2682 | }; |
2683 | ||
2684 | /* timer5 */ | |
35d1a66a BC |
2685 | static struct omap_hwmod omap44xx_timer5_hwmod = { |
2686 | .name = "timer5", | |
2687 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2688 | .clkdm_name = "abe_clkdm", |
ee877acd | 2689 | .main_clk = "timer5_sync_mux", |
35d1a66a BC |
2690 | .prcm = { |
2691 | .omap4 = { | |
d0f0631d | 2692 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, |
27bb00b5 | 2693 | .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET, |
03fdefe5 | 2694 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2695 | }, |
2696 | }, | |
5c3e4ec4 | 2697 | .dev_attr = &capability_dsp_dev_attr, |
35d1a66a BC |
2698 | }; |
2699 | ||
2700 | /* timer6 */ | |
35d1a66a BC |
2701 | static struct omap_hwmod omap44xx_timer6_hwmod = { |
2702 | .name = "timer6", | |
2703 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2704 | .clkdm_name = "abe_clkdm", |
ee877acd | 2705 | .main_clk = "timer6_sync_mux", |
35d1a66a BC |
2706 | .prcm = { |
2707 | .omap4 = { | |
d0f0631d | 2708 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, |
27bb00b5 | 2709 | .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET, |
03fdefe5 | 2710 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2711 | }, |
2712 | }, | |
5c3e4ec4 | 2713 | .dev_attr = &capability_dsp_dev_attr, |
35d1a66a BC |
2714 | }; |
2715 | ||
2716 | /* timer7 */ | |
35d1a66a BC |
2717 | static struct omap_hwmod omap44xx_timer7_hwmod = { |
2718 | .name = "timer7", | |
2719 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2720 | .clkdm_name = "abe_clkdm", |
ee877acd | 2721 | .main_clk = "timer7_sync_mux", |
35d1a66a BC |
2722 | .prcm = { |
2723 | .omap4 = { | |
d0f0631d | 2724 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, |
27bb00b5 | 2725 | .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET, |
03fdefe5 | 2726 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2727 | }, |
2728 | }, | |
5c3e4ec4 | 2729 | .dev_attr = &capability_dsp_dev_attr, |
35d1a66a BC |
2730 | }; |
2731 | ||
2732 | /* timer8 */ | |
35d1a66a BC |
2733 | static struct omap_hwmod omap44xx_timer8_hwmod = { |
2734 | .name = "timer8", | |
2735 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2736 | .clkdm_name = "abe_clkdm", |
ee877acd | 2737 | .main_clk = "timer8_sync_mux", |
35d1a66a BC |
2738 | .prcm = { |
2739 | .omap4 = { | |
d0f0631d | 2740 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, |
27bb00b5 | 2741 | .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET, |
03fdefe5 | 2742 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2743 | }, |
2744 | }, | |
5c3e4ec4 | 2745 | .dev_attr = &capability_dsp_pwm_dev_attr, |
35d1a66a BC |
2746 | }; |
2747 | ||
2748 | /* timer9 */ | |
35d1a66a BC |
2749 | static struct omap_hwmod omap44xx_timer9_hwmod = { |
2750 | .name = "timer9", | |
2751 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2752 | .clkdm_name = "l4_per_clkdm", |
ee877acd | 2753 | .main_clk = "cm2_dm9_mux", |
35d1a66a BC |
2754 | .prcm = { |
2755 | .omap4 = { | |
d0f0631d | 2756 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, |
27bb00b5 | 2757 | .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET, |
03fdefe5 | 2758 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2759 | }, |
2760 | }, | |
c345c8b0 | 2761 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
2762 | }; |
2763 | ||
2764 | /* timer10 */ | |
35d1a66a BC |
2765 | static struct omap_hwmod omap44xx_timer10_hwmod = { |
2766 | .name = "timer10", | |
2767 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2768 | .clkdm_name = "l4_per_clkdm", |
10759e82 | 2769 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
ee877acd | 2770 | .main_clk = "cm2_dm10_mux", |
35d1a66a BC |
2771 | .prcm = { |
2772 | .omap4 = { | |
d0f0631d | 2773 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, |
27bb00b5 | 2774 | .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET, |
03fdefe5 | 2775 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2776 | }, |
2777 | }, | |
c345c8b0 | 2778 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
2779 | }; |
2780 | ||
2781 | /* timer11 */ | |
35d1a66a BC |
2782 | static struct omap_hwmod omap44xx_timer11_hwmod = { |
2783 | .name = "timer11", | |
2784 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2785 | .clkdm_name = "l4_per_clkdm", |
ee877acd | 2786 | .main_clk = "cm2_dm11_mux", |
35d1a66a BC |
2787 | .prcm = { |
2788 | .omap4 = { | |
d0f0631d | 2789 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, |
27bb00b5 | 2790 | .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET, |
03fdefe5 | 2791 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2792 | }, |
2793 | }, | |
c345c8b0 | 2794 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
2795 | }; |
2796 | ||
9780a9cf | 2797 | /* |
3b54baad BC |
2798 | * 'uart' class |
2799 | * universal asynchronous receiver/transmitter (uart) | |
9780a9cf BC |
2800 | */ |
2801 | ||
3b54baad BC |
2802 | static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { |
2803 | .rev_offs = 0x0050, | |
2804 | .sysc_offs = 0x0054, | |
2805 | .syss_offs = 0x0058, | |
2806 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
0cfe8751 BC |
2807 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
2808 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
2809 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
2810 | SIDLE_SMART_WKUP), | |
9780a9cf BC |
2811 | .sysc_fields = &omap_hwmod_sysc_type1, |
2812 | }; | |
2813 | ||
3b54baad | 2814 | static struct omap_hwmod_class omap44xx_uart_hwmod_class = { |
fe13471c BC |
2815 | .name = "uart", |
2816 | .sysc = &omap44xx_uart_sysc, | |
9780a9cf BC |
2817 | }; |
2818 | ||
3b54baad | 2819 | /* uart1 */ |
3b54baad BC |
2820 | static struct omap_hwmod omap44xx_uart1_hwmod = { |
2821 | .name = "uart1", | |
2822 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 2823 | .clkdm_name = "l4_per_clkdm", |
66dde54e | 2824 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
17b7e7d3 | 2825 | .main_clk = "func_48m_fclk", |
9780a9cf BC |
2826 | .prcm = { |
2827 | .omap4 = { | |
d0f0631d | 2828 | .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET, |
27bb00b5 | 2829 | .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET, |
03fdefe5 | 2830 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
2831 | }, |
2832 | }, | |
9780a9cf BC |
2833 | }; |
2834 | ||
3b54baad | 2835 | /* uart2 */ |
3b54baad BC |
2836 | static struct omap_hwmod omap44xx_uart2_hwmod = { |
2837 | .name = "uart2", | |
2838 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 2839 | .clkdm_name = "l4_per_clkdm", |
66dde54e | 2840 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
17b7e7d3 | 2841 | .main_clk = "func_48m_fclk", |
9780a9cf BC |
2842 | .prcm = { |
2843 | .omap4 = { | |
d0f0631d | 2844 | .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET, |
27bb00b5 | 2845 | .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET, |
03fdefe5 | 2846 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
2847 | }, |
2848 | }, | |
9780a9cf BC |
2849 | }; |
2850 | ||
3b54baad | 2851 | /* uart3 */ |
3b54baad BC |
2852 | static struct omap_hwmod omap44xx_uart3_hwmod = { |
2853 | .name = "uart3", | |
2854 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 2855 | .clkdm_name = "l4_per_clkdm", |
7dedd346 | 2856 | .flags = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT, |
17b7e7d3 | 2857 | .main_clk = "func_48m_fclk", |
9780a9cf BC |
2858 | .prcm = { |
2859 | .omap4 = { | |
d0f0631d | 2860 | .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET, |
27bb00b5 | 2861 | .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET, |
03fdefe5 | 2862 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
2863 | }, |
2864 | }, | |
9780a9cf BC |
2865 | }; |
2866 | ||
3b54baad | 2867 | /* uart4 */ |
3b54baad BC |
2868 | static struct omap_hwmod omap44xx_uart4_hwmod = { |
2869 | .name = "uart4", | |
2870 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 2871 | .clkdm_name = "l4_per_clkdm", |
7dedd346 | 2872 | .flags = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT, |
17b7e7d3 | 2873 | .main_clk = "func_48m_fclk", |
9780a9cf BC |
2874 | .prcm = { |
2875 | .omap4 = { | |
d0f0631d | 2876 | .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET, |
27bb00b5 | 2877 | .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET, |
03fdefe5 | 2878 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
2879 | }, |
2880 | }, | |
9780a9cf BC |
2881 | }; |
2882 | ||
0c668875 BC |
2883 | /* |
2884 | * 'usb_host_fs' class | |
2885 | * full-speed usb host controller | |
2886 | */ | |
2887 | ||
2888 | /* The IP is not compliant to type1 / type2 scheme */ | |
2889 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = { | |
2890 | .midle_shift = 4, | |
2891 | .sidle_shift = 2, | |
2892 | .srst_shift = 1, | |
2893 | }; | |
2894 | ||
2895 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = { | |
2896 | .rev_offs = 0x0000, | |
2897 | .sysc_offs = 0x0210, | |
2898 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
2899 | SYSC_HAS_SOFTRESET), | |
2900 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2901 | SIDLE_SMART_WKUP), | |
2902 | .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs, | |
2903 | }; | |
2904 | ||
2905 | static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = { | |
2906 | .name = "usb_host_fs", | |
2907 | .sysc = &omap44xx_usb_host_fs_sysc, | |
2908 | }; | |
2909 | ||
2910 | /* usb_host_fs */ | |
0c668875 BC |
2911 | static struct omap_hwmod omap44xx_usb_host_fs_hwmod = { |
2912 | .name = "usb_host_fs", | |
2913 | .class = &omap44xx_usb_host_fs_hwmod_class, | |
2914 | .clkdm_name = "l3_init_clkdm", | |
0c668875 BC |
2915 | .main_clk = "usb_host_fs_fck", |
2916 | .prcm = { | |
2917 | .omap4 = { | |
2918 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET, | |
2919 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET, | |
2920 | .modulemode = MODULEMODE_SWCTRL, | |
2921 | }, | |
2922 | }, | |
2923 | }; | |
2924 | ||
5844c4ea | 2925 | /* |
844a3b63 PW |
2926 | * 'usb_host_hs' class |
2927 | * high-speed multi-port usb host controller | |
5844c4ea BC |
2928 | */ |
2929 | ||
844a3b63 PW |
2930 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { |
2931 | .rev_offs = 0x0000, | |
2932 | .sysc_offs = 0x0010, | |
2933 | .syss_offs = 0x0014, | |
2934 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
b483a4a5 | 2935 | SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS), |
5844c4ea BC |
2936 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
2937 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
844a3b63 PW |
2938 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
2939 | .sysc_fields = &omap_hwmod_sysc_type2, | |
5844c4ea BC |
2940 | }; |
2941 | ||
844a3b63 PW |
2942 | static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { |
2943 | .name = "usb_host_hs", | |
2944 | .sysc = &omap44xx_usb_host_hs_sysc, | |
5844c4ea BC |
2945 | }; |
2946 | ||
844a3b63 | 2947 | /* usb_host_hs */ |
844a3b63 PW |
2948 | static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { |
2949 | .name = "usb_host_hs", | |
2950 | .class = &omap44xx_usb_host_hs_hwmod_class, | |
a5322c6f | 2951 | .clkdm_name = "l3_init_clkdm", |
844a3b63 | 2952 | .main_clk = "usb_host_hs_fck", |
5844c4ea BC |
2953 | .prcm = { |
2954 | .omap4 = { | |
844a3b63 PW |
2955 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, |
2956 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, | |
2957 | .modulemode = MODULEMODE_SWCTRL, | |
2958 | }, | |
2959 | }, | |
844a3b63 PW |
2960 | |
2961 | /* | |
2962 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
2963 | * id: i660 | |
2964 | * | |
2965 | * Description: | |
2966 | * In the following configuration : | |
2967 | * - USBHOST module is set to smart-idle mode | |
2968 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
2969 | * happens when the system is going to a low power mode : all ports | |
2970 | * have been suspended, the master part of the USBHOST module has | |
2971 | * entered the standby state, and SW has cut the functional clocks) | |
2972 | * - an USBHOST interrupt occurs before the module is able to answer | |
2973 | * idle_ack, typically a remote wakeup IRQ. | |
2974 | * Then the USB HOST module will enter a deadlock situation where it | |
2975 | * is no more accessible nor functional. | |
2976 | * | |
2977 | * Workaround: | |
2978 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
2979 | */ | |
2980 | ||
2981 | /* | |
2982 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
2983 | * Id: i571 | |
2984 | * | |
2985 | * Description: | |
2986 | * When the USBHOST module is set to smart-standby mode, and when it is | |
2987 | * ready to enter the standby state (i.e. all ports are suspended and | |
2988 | * all attached devices are in suspend mode), then it can wrongly assert | |
2989 | * the Mstandby signal too early while there are still some residual OCP | |
2990 | * transactions ongoing. If this condition occurs, the internal state | |
2991 | * machine may go to an undefined state and the USB link may be stuck | |
2992 | * upon the next resume. | |
2993 | * | |
2994 | * Workaround: | |
2995 | * Don't use smart standby; use only force standby, | |
2996 | * hence HWMOD_SWSUP_MSTANDBY | |
2997 | */ | |
2998 | ||
b483a4a5 | 2999 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
844a3b63 PW |
3000 | }; |
3001 | ||
3002 | /* | |
3003 | * 'usb_otg_hs' class | |
3004 | * high-speed on-the-go universal serial bus (usb_otg_hs) controller | |
3005 | */ | |
3006 | ||
3007 | static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { | |
3008 | .rev_offs = 0x0400, | |
3009 | .sysc_offs = 0x0404, | |
3010 | .syss_offs = 0x0408, | |
3011 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
3012 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
3013 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
3014 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3015 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
3016 | MSTANDBY_SMART), | |
3017 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3018 | }; | |
3019 | ||
3020 | static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { | |
3021 | .name = "usb_otg_hs", | |
3022 | .sysc = &omap44xx_usb_otg_hs_sysc, | |
3023 | }; | |
3024 | ||
3025 | /* usb_otg_hs */ | |
844a3b63 PW |
3026 | static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { |
3027 | { .role = "xclk", .clk = "usb_otg_hs_xclk" }, | |
3028 | }; | |
3029 | ||
3030 | static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { | |
3031 | .name = "usb_otg_hs", | |
3032 | .class = &omap44xx_usb_otg_hs_hwmod_class, | |
3033 | .clkdm_name = "l3_init_clkdm", | |
3034 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | |
844a3b63 PW |
3035 | .main_clk = "usb_otg_hs_ick", |
3036 | .prcm = { | |
3037 | .omap4 = { | |
3038 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET, | |
3039 | .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET, | |
3040 | .modulemode = MODULEMODE_HWCTRL, | |
3041 | }, | |
3042 | }, | |
3043 | .opt_clks = usb_otg_hs_opt_clks, | |
3044 | .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), | |
3045 | }; | |
3046 | ||
3047 | /* | |
3048 | * 'usb_tll_hs' class | |
3049 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
3050 | */ | |
3051 | ||
3052 | static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { | |
3053 | .rev_offs = 0x0000, | |
3054 | .sysc_offs = 0x0010, | |
3055 | .syss_offs = 0x0014, | |
3056 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
3057 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
3058 | SYSC_HAS_AUTOIDLE), | |
3059 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
3060 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3061 | }; | |
3062 | ||
3063 | static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { | |
3064 | .name = "usb_tll_hs", | |
3065 | .sysc = &omap44xx_usb_tll_hs_sysc, | |
3066 | }; | |
3067 | ||
844a3b63 PW |
3068 | static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { |
3069 | .name = "usb_tll_hs", | |
3070 | .class = &omap44xx_usb_tll_hs_hwmod_class, | |
3071 | .clkdm_name = "l3_init_clkdm", | |
844a3b63 PW |
3072 | .main_clk = "usb_tll_hs_ick", |
3073 | .prcm = { | |
3074 | .omap4 = { | |
3075 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, | |
3076 | .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, | |
3077 | .modulemode = MODULEMODE_HWCTRL, | |
5844c4ea BC |
3078 | }, |
3079 | }, | |
5844c4ea BC |
3080 | }; |
3081 | ||
3b54baad BC |
3082 | /* |
3083 | * 'wd_timer' class | |
3084 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
3085 | * overflow condition | |
3086 | */ | |
3087 | ||
3088 | static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { | |
3089 | .rev_offs = 0x0000, | |
3090 | .sysc_offs = 0x0010, | |
3091 | .syss_offs = 0x0014, | |
3092 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 3093 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
3094 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3095 | SIDLE_SMART_WKUP), | |
3b54baad | 3096 | .sysc_fields = &omap_hwmod_sysc_type1, |
9780a9cf BC |
3097 | }; |
3098 | ||
3b54baad BC |
3099 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { |
3100 | .name = "wd_timer", | |
3101 | .sysc = &omap44xx_wd_timer_sysc, | |
fe13471c | 3102 | .pre_shutdown = &omap2_wd_timer_disable, |
414e4128 | 3103 | .reset = &omap2_wd_timer_reset, |
3b54baad BC |
3104 | }; |
3105 | ||
3106 | /* wd_timer2 */ | |
3b54baad BC |
3107 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { |
3108 | .name = "wd_timer2", | |
3109 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 3110 | .clkdm_name = "l4_wkup_clkdm", |
17b7e7d3 | 3111 | .main_clk = "sys_32k_ck", |
9780a9cf BC |
3112 | .prcm = { |
3113 | .omap4 = { | |
d0f0631d | 3114 | .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, |
27bb00b5 | 3115 | .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET, |
03fdefe5 | 3116 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3117 | }, |
3118 | }, | |
9780a9cf BC |
3119 | }; |
3120 | ||
3b54baad | 3121 | /* wd_timer3 */ |
3b54baad BC |
3122 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { |
3123 | .name = "wd_timer3", | |
3124 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 3125 | .clkdm_name = "abe_clkdm", |
17b7e7d3 | 3126 | .main_clk = "sys_32k_ck", |
9780a9cf BC |
3127 | .prcm = { |
3128 | .omap4 = { | |
d0f0631d | 3129 | .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, |
27bb00b5 | 3130 | .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET, |
03fdefe5 | 3131 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3132 | }, |
3133 | }, | |
9780a9cf | 3134 | }; |
531ce0d5 | 3135 | |
844a3b63 | 3136 | |
af88fa9a | 3137 | /* |
844a3b63 | 3138 | * interfaces |
af88fa9a | 3139 | */ |
af88fa9a | 3140 | |
844a3b63 PW |
3141 | /* l3_main_1 -> dmm */ |
3142 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { | |
3143 | .master = &omap44xx_l3_main_1_hwmod, | |
3144 | .slave = &omap44xx_dmm_hwmod, | |
3145 | .clk = "l3_div_ck", | |
3146 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
3147 | }; |
3148 | ||
844a3b63 PW |
3149 | /* mpu -> dmm */ |
3150 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { | |
3151 | .master = &omap44xx_mpu_hwmod, | |
3152 | .slave = &omap44xx_dmm_hwmod, | |
3153 | .clk = "l3_div_ck", | |
844a3b63 PW |
3154 | .user = OCP_USER_MPU, |
3155 | }; | |
3156 | ||
3157 | /* iva -> l3_instr */ | |
3158 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { | |
3159 | .master = &omap44xx_iva_hwmod, | |
3160 | .slave = &omap44xx_l3_instr_hwmod, | |
3161 | .clk = "l3_div_ck", | |
3162 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3163 | }; | |
3164 | ||
3165 | /* l3_main_3 -> l3_instr */ | |
3166 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { | |
3167 | .master = &omap44xx_l3_main_3_hwmod, | |
3168 | .slave = &omap44xx_l3_instr_hwmod, | |
3169 | .clk = "l3_div_ck", | |
3170 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3171 | }; | |
3172 | ||
9a817bc8 BC |
3173 | /* ocp_wp_noc -> l3_instr */ |
3174 | static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = { | |
3175 | .master = &omap44xx_ocp_wp_noc_hwmod, | |
3176 | .slave = &omap44xx_l3_instr_hwmod, | |
3177 | .clk = "l3_div_ck", | |
3178 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3179 | }; | |
3180 | ||
844a3b63 PW |
3181 | /* dsp -> l3_main_1 */ |
3182 | static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { | |
3183 | .master = &omap44xx_dsp_hwmod, | |
3184 | .slave = &omap44xx_l3_main_1_hwmod, | |
3185 | .clk = "l3_div_ck", | |
3186 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3187 | }; | |
3188 | ||
3189 | /* dss -> l3_main_1 */ | |
3190 | static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { | |
3191 | .master = &omap44xx_dss_hwmod, | |
3192 | .slave = &omap44xx_l3_main_1_hwmod, | |
3193 | .clk = "l3_div_ck", | |
3194 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3195 | }; | |
3196 | ||
3197 | /* l3_main_2 -> l3_main_1 */ | |
3198 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { | |
3199 | .master = &omap44xx_l3_main_2_hwmod, | |
3200 | .slave = &omap44xx_l3_main_1_hwmod, | |
3201 | .clk = "l3_div_ck", | |
3202 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3203 | }; | |
3204 | ||
3205 | /* l4_cfg -> l3_main_1 */ | |
3206 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { | |
3207 | .master = &omap44xx_l4_cfg_hwmod, | |
3208 | .slave = &omap44xx_l3_main_1_hwmod, | |
3209 | .clk = "l4_div_ck", | |
3210 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3211 | }; | |
3212 | ||
3213 | /* mmc1 -> l3_main_1 */ | |
3214 | static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { | |
3215 | .master = &omap44xx_mmc1_hwmod, | |
3216 | .slave = &omap44xx_l3_main_1_hwmod, | |
3217 | .clk = "l3_div_ck", | |
3218 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3219 | }; | |
3220 | ||
3221 | /* mmc2 -> l3_main_1 */ | |
3222 | static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { | |
3223 | .master = &omap44xx_mmc2_hwmod, | |
3224 | .slave = &omap44xx_l3_main_1_hwmod, | |
3225 | .clk = "l3_div_ck", | |
3226 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3227 | }; | |
3228 | ||
844a3b63 PW |
3229 | /* mpu -> l3_main_1 */ |
3230 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { | |
3231 | .master = &omap44xx_mpu_hwmod, | |
3232 | .slave = &omap44xx_l3_main_1_hwmod, | |
3233 | .clk = "l3_div_ck", | |
844a3b63 PW |
3234 | .user = OCP_USER_MPU, |
3235 | }; | |
3236 | ||
96566043 BC |
3237 | /* debugss -> l3_main_2 */ |
3238 | static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = { | |
3239 | .master = &omap44xx_debugss_hwmod, | |
3240 | .slave = &omap44xx_l3_main_2_hwmod, | |
3241 | .clk = "dbgclk_mux_ck", | |
3242 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3243 | }; | |
3244 | ||
844a3b63 PW |
3245 | /* dma_system -> l3_main_2 */ |
3246 | static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { | |
3247 | .master = &omap44xx_dma_system_hwmod, | |
3248 | .slave = &omap44xx_l3_main_2_hwmod, | |
3249 | .clk = "l3_div_ck", | |
3250 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3251 | }; | |
3252 | ||
b050f688 ML |
3253 | /* fdif -> l3_main_2 */ |
3254 | static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = { | |
3255 | .master = &omap44xx_fdif_hwmod, | |
3256 | .slave = &omap44xx_l3_main_2_hwmod, | |
3257 | .clk = "l3_div_ck", | |
3258 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3259 | }; | |
3260 | ||
9def390e PW |
3261 | /* gpu -> l3_main_2 */ |
3262 | static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = { | |
3263 | .master = &omap44xx_gpu_hwmod, | |
3264 | .slave = &omap44xx_l3_main_2_hwmod, | |
3265 | .clk = "l3_div_ck", | |
3266 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3267 | }; | |
3268 | ||
844a3b63 PW |
3269 | /* hsi -> l3_main_2 */ |
3270 | static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { | |
3271 | .master = &omap44xx_hsi_hwmod, | |
3272 | .slave = &omap44xx_l3_main_2_hwmod, | |
3273 | .clk = "l3_div_ck", | |
3274 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3275 | }; | |
3276 | ||
3277 | /* ipu -> l3_main_2 */ | |
3278 | static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { | |
3279 | .master = &omap44xx_ipu_hwmod, | |
3280 | .slave = &omap44xx_l3_main_2_hwmod, | |
3281 | .clk = "l3_div_ck", | |
3282 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3283 | }; | |
3284 | ||
3285 | /* iss -> l3_main_2 */ | |
3286 | static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { | |
3287 | .master = &omap44xx_iss_hwmod, | |
3288 | .slave = &omap44xx_l3_main_2_hwmod, | |
3289 | .clk = "l3_div_ck", | |
3290 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3291 | }; | |
3292 | ||
3293 | /* iva -> l3_main_2 */ | |
3294 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { | |
3295 | .master = &omap44xx_iva_hwmod, | |
3296 | .slave = &omap44xx_l3_main_2_hwmod, | |
3297 | .clk = "l3_div_ck", | |
3298 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3299 | }; | |
3300 | ||
844a3b63 PW |
3301 | /* l3_main_1 -> l3_main_2 */ |
3302 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { | |
3303 | .master = &omap44xx_l3_main_1_hwmod, | |
3304 | .slave = &omap44xx_l3_main_2_hwmod, | |
3305 | .clk = "l3_div_ck", | |
844a3b63 PW |
3306 | .user = OCP_USER_MPU, |
3307 | }; | |
3308 | ||
3309 | /* l4_cfg -> l3_main_2 */ | |
3310 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { | |
3311 | .master = &omap44xx_l4_cfg_hwmod, | |
3312 | .slave = &omap44xx_l3_main_2_hwmod, | |
3313 | .clk = "l4_div_ck", | |
3314 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3315 | }; | |
3316 | ||
0c668875 | 3317 | /* usb_host_fs -> l3_main_2 */ |
b0a70cc8 | 3318 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = { |
0c668875 BC |
3319 | .master = &omap44xx_usb_host_fs_hwmod, |
3320 | .slave = &omap44xx_l3_main_2_hwmod, | |
3321 | .clk = "l3_div_ck", | |
3322 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3323 | }; | |
3324 | ||
844a3b63 PW |
3325 | /* usb_host_hs -> l3_main_2 */ |
3326 | static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { | |
3327 | .master = &omap44xx_usb_host_hs_hwmod, | |
3328 | .slave = &omap44xx_l3_main_2_hwmod, | |
3329 | .clk = "l3_div_ck", | |
3330 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3331 | }; | |
3332 | ||
3333 | /* usb_otg_hs -> l3_main_2 */ | |
3334 | static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { | |
3335 | .master = &omap44xx_usb_otg_hs_hwmod, | |
3336 | .slave = &omap44xx_l3_main_2_hwmod, | |
3337 | .clk = "l3_div_ck", | |
3338 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3339 | }; | |
3340 | ||
844a3b63 PW |
3341 | /* l3_main_1 -> l3_main_3 */ |
3342 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { | |
3343 | .master = &omap44xx_l3_main_1_hwmod, | |
3344 | .slave = &omap44xx_l3_main_3_hwmod, | |
3345 | .clk = "l3_div_ck", | |
844a3b63 PW |
3346 | .user = OCP_USER_MPU, |
3347 | }; | |
3348 | ||
3349 | /* l3_main_2 -> l3_main_3 */ | |
3350 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { | |
3351 | .master = &omap44xx_l3_main_2_hwmod, | |
3352 | .slave = &omap44xx_l3_main_3_hwmod, | |
3353 | .clk = "l3_div_ck", | |
3354 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3355 | }; | |
3356 | ||
3357 | /* l4_cfg -> l3_main_3 */ | |
3358 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { | |
3359 | .master = &omap44xx_l4_cfg_hwmod, | |
3360 | .slave = &omap44xx_l3_main_3_hwmod, | |
3361 | .clk = "l4_div_ck", | |
3362 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3363 | }; | |
3364 | ||
3365 | /* aess -> l4_abe */ | |
b0a70cc8 | 3366 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = { |
844a3b63 PW |
3367 | .master = &omap44xx_aess_hwmod, |
3368 | .slave = &omap44xx_l4_abe_hwmod, | |
3369 | .clk = "ocp_abe_iclk", | |
3370 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3371 | }; | |
3372 | ||
3373 | /* dsp -> l4_abe */ | |
3374 | static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { | |
3375 | .master = &omap44xx_dsp_hwmod, | |
3376 | .slave = &omap44xx_l4_abe_hwmod, | |
3377 | .clk = "ocp_abe_iclk", | |
3378 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3379 | }; | |
3380 | ||
3381 | /* l3_main_1 -> l4_abe */ | |
3382 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { | |
3383 | .master = &omap44xx_l3_main_1_hwmod, | |
3384 | .slave = &omap44xx_l4_abe_hwmod, | |
3385 | .clk = "l3_div_ck", | |
3386 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3387 | }; | |
3388 | ||
3389 | /* mpu -> l4_abe */ | |
3390 | static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { | |
3391 | .master = &omap44xx_mpu_hwmod, | |
3392 | .slave = &omap44xx_l4_abe_hwmod, | |
3393 | .clk = "ocp_abe_iclk", | |
3394 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3395 | }; | |
3396 | ||
3397 | /* l3_main_1 -> l4_cfg */ | |
3398 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { | |
3399 | .master = &omap44xx_l3_main_1_hwmod, | |
3400 | .slave = &omap44xx_l4_cfg_hwmod, | |
3401 | .clk = "l3_div_ck", | |
3402 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3403 | }; | |
3404 | ||
3405 | /* l3_main_2 -> l4_per */ | |
3406 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { | |
3407 | .master = &omap44xx_l3_main_2_hwmod, | |
3408 | .slave = &omap44xx_l4_per_hwmod, | |
3409 | .clk = "l3_div_ck", | |
3410 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3411 | }; | |
3412 | ||
3413 | /* l4_cfg -> l4_wkup */ | |
3414 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { | |
3415 | .master = &omap44xx_l4_cfg_hwmod, | |
3416 | .slave = &omap44xx_l4_wkup_hwmod, | |
3417 | .clk = "l4_div_ck", | |
3418 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3419 | }; | |
3420 | ||
3421 | /* mpu -> mpu_private */ | |
3422 | static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { | |
3423 | .master = &omap44xx_mpu_hwmod, | |
3424 | .slave = &omap44xx_mpu_private_hwmod, | |
3425 | .clk = "l3_div_ck", | |
3426 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3427 | }; | |
3428 | ||
9a817bc8 BC |
3429 | /* l4_cfg -> ocp_wp_noc */ |
3430 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = { | |
3431 | .master = &omap44xx_l4_cfg_hwmod, | |
3432 | .slave = &omap44xx_ocp_wp_noc_hwmod, | |
3433 | .clk = "l4_div_ck", | |
9a817bc8 BC |
3434 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3435 | }; | |
3436 | ||
844a3b63 PW |
3437 | static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { |
3438 | { | |
9f0c5996 SG |
3439 | .name = "dmem", |
3440 | .pa_start = 0x40180000, | |
3441 | .pa_end = 0x4018ffff | |
3442 | }, | |
3443 | { | |
3444 | .name = "cmem", | |
3445 | .pa_start = 0x401a0000, | |
3446 | .pa_end = 0x401a1fff | |
3447 | }, | |
3448 | { | |
3449 | .name = "smem", | |
3450 | .pa_start = 0x401c0000, | |
3451 | .pa_end = 0x401c5fff | |
3452 | }, | |
3453 | { | |
3454 | .name = "pmem", | |
3455 | .pa_start = 0x401e0000, | |
3456 | .pa_end = 0x401e1fff | |
3457 | }, | |
3458 | { | |
3459 | .name = "mpu", | |
844a3b63 PW |
3460 | .pa_start = 0x401f1000, |
3461 | .pa_end = 0x401f13ff, | |
3462 | .flags = ADDR_TYPE_RT | |
3463 | }, | |
3464 | { } | |
3465 | }; | |
3466 | ||
3467 | /* l4_abe -> aess */ | |
b0a70cc8 | 3468 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = { |
844a3b63 PW |
3469 | .master = &omap44xx_l4_abe_hwmod, |
3470 | .slave = &omap44xx_aess_hwmod, | |
3471 | .clk = "ocp_abe_iclk", | |
3472 | .addr = omap44xx_aess_addrs, | |
3473 | .user = OCP_USER_MPU, | |
3474 | }; | |
3475 | ||
3476 | static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { | |
3477 | { | |
9f0c5996 SG |
3478 | .name = "dmem_dma", |
3479 | .pa_start = 0x49080000, | |
3480 | .pa_end = 0x4908ffff | |
3481 | }, | |
3482 | { | |
3483 | .name = "cmem_dma", | |
3484 | .pa_start = 0x490a0000, | |
3485 | .pa_end = 0x490a1fff | |
3486 | }, | |
3487 | { | |
3488 | .name = "smem_dma", | |
3489 | .pa_start = 0x490c0000, | |
3490 | .pa_end = 0x490c5fff | |
3491 | }, | |
3492 | { | |
3493 | .name = "pmem_dma", | |
3494 | .pa_start = 0x490e0000, | |
3495 | .pa_end = 0x490e1fff | |
3496 | }, | |
3497 | { | |
3498 | .name = "dma", | |
844a3b63 PW |
3499 | .pa_start = 0x490f1000, |
3500 | .pa_end = 0x490f13ff, | |
3501 | .flags = ADDR_TYPE_RT | |
3502 | }, | |
3503 | { } | |
3504 | }; | |
3505 | ||
3506 | /* l4_abe -> aess (dma) */ | |
b0a70cc8 | 3507 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = { |
844a3b63 PW |
3508 | .master = &omap44xx_l4_abe_hwmod, |
3509 | .slave = &omap44xx_aess_hwmod, | |
3510 | .clk = "ocp_abe_iclk", | |
3511 | .addr = omap44xx_aess_dma_addrs, | |
3512 | .user = OCP_USER_SDMA, | |
3513 | }; | |
3514 | ||
42b9e387 PW |
3515 | /* l3_main_2 -> c2c */ |
3516 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = { | |
3517 | .master = &omap44xx_l3_main_2_hwmod, | |
3518 | .slave = &omap44xx_c2c_hwmod, | |
3519 | .clk = "l3_div_ck", | |
3520 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3521 | }; | |
3522 | ||
844a3b63 PW |
3523 | /* l4_wkup -> counter_32k */ |
3524 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { | |
3525 | .master = &omap44xx_l4_wkup_hwmod, | |
3526 | .slave = &omap44xx_counter_32k_hwmod, | |
3527 | .clk = "l4_wkup_clk_mux_ck", | |
844a3b63 PW |
3528 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3529 | }; | |
3530 | ||
a0b5d813 PW |
3531 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = { |
3532 | { | |
3533 | .pa_start = 0x4a002000, | |
3534 | .pa_end = 0x4a0027ff, | |
3535 | .flags = ADDR_TYPE_RT | |
3536 | }, | |
3537 | { } | |
3538 | }; | |
3539 | ||
3540 | /* l4_cfg -> ctrl_module_core */ | |
3541 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = { | |
3542 | .master = &omap44xx_l4_cfg_hwmod, | |
3543 | .slave = &omap44xx_ctrl_module_core_hwmod, | |
3544 | .clk = "l4_div_ck", | |
3545 | .addr = omap44xx_ctrl_module_core_addrs, | |
3546 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3547 | }; | |
3548 | ||
3549 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = { | |
3550 | { | |
3551 | .pa_start = 0x4a100000, | |
3552 | .pa_end = 0x4a1007ff, | |
3553 | .flags = ADDR_TYPE_RT | |
3554 | }, | |
3555 | { } | |
3556 | }; | |
3557 | ||
3558 | /* l4_cfg -> ctrl_module_pad_core */ | |
3559 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = { | |
3560 | .master = &omap44xx_l4_cfg_hwmod, | |
3561 | .slave = &omap44xx_ctrl_module_pad_core_hwmod, | |
3562 | .clk = "l4_div_ck", | |
3563 | .addr = omap44xx_ctrl_module_pad_core_addrs, | |
3564 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3565 | }; | |
3566 | ||
3567 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = { | |
3568 | { | |
3569 | .pa_start = 0x4a30c000, | |
3570 | .pa_end = 0x4a30c7ff, | |
3571 | .flags = ADDR_TYPE_RT | |
3572 | }, | |
3573 | { } | |
3574 | }; | |
3575 | ||
3576 | /* l4_wkup -> ctrl_module_wkup */ | |
3577 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = { | |
3578 | .master = &omap44xx_l4_wkup_hwmod, | |
3579 | .slave = &omap44xx_ctrl_module_wkup_hwmod, | |
3580 | .clk = "l4_wkup_clk_mux_ck", | |
3581 | .addr = omap44xx_ctrl_module_wkup_addrs, | |
3582 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3583 | }; | |
3584 | ||
3585 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = { | |
3586 | { | |
3587 | .pa_start = 0x4a31e000, | |
3588 | .pa_end = 0x4a31e7ff, | |
3589 | .flags = ADDR_TYPE_RT | |
3590 | }, | |
3591 | { } | |
3592 | }; | |
3593 | ||
3594 | /* l4_wkup -> ctrl_module_pad_wkup */ | |
3595 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = { | |
3596 | .master = &omap44xx_l4_wkup_hwmod, | |
3597 | .slave = &omap44xx_ctrl_module_pad_wkup_hwmod, | |
3598 | .clk = "l4_wkup_clk_mux_ck", | |
3599 | .addr = omap44xx_ctrl_module_pad_wkup_addrs, | |
3600 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3601 | }; | |
3602 | ||
96566043 BC |
3603 | /* l3_instr -> debugss */ |
3604 | static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = { | |
3605 | .master = &omap44xx_l3_instr_hwmod, | |
3606 | .slave = &omap44xx_debugss_hwmod, | |
3607 | .clk = "l3_div_ck", | |
96566043 BC |
3608 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3609 | }; | |
3610 | ||
844a3b63 PW |
3611 | static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { |
3612 | { | |
3613 | .pa_start = 0x4a056000, | |
3614 | .pa_end = 0x4a056fff, | |
3615 | .flags = ADDR_TYPE_RT | |
3616 | }, | |
3617 | { } | |
3618 | }; | |
3619 | ||
3620 | /* l4_cfg -> dma_system */ | |
3621 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { | |
3622 | .master = &omap44xx_l4_cfg_hwmod, | |
3623 | .slave = &omap44xx_dma_system_hwmod, | |
3624 | .clk = "l4_div_ck", | |
3625 | .addr = omap44xx_dma_system_addrs, | |
3626 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3627 | }; | |
3628 | ||
844a3b63 PW |
3629 | /* l4_abe -> dmic */ |
3630 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { | |
3631 | .master = &omap44xx_l4_abe_hwmod, | |
3632 | .slave = &omap44xx_dmic_hwmod, | |
3633 | .clk = "ocp_abe_iclk", | |
e3491795 | 3634 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
3635 | }; |
3636 | ||
3637 | /* dsp -> iva */ | |
3638 | static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { | |
3639 | .master = &omap44xx_dsp_hwmod, | |
3640 | .slave = &omap44xx_iva_hwmod, | |
3641 | .clk = "dpll_iva_m5x2_ck", | |
3642 | .user = OCP_USER_DSP, | |
3643 | }; | |
3644 | ||
42b9e387 | 3645 | /* dsp -> sl2if */ |
b360124e | 3646 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = { |
42b9e387 PW |
3647 | .master = &omap44xx_dsp_hwmod, |
3648 | .slave = &omap44xx_sl2if_hwmod, | |
3649 | .clk = "dpll_iva_m5x2_ck", | |
3650 | .user = OCP_USER_DSP, | |
3651 | }; | |
3652 | ||
844a3b63 PW |
3653 | /* l4_cfg -> dsp */ |
3654 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { | |
3655 | .master = &omap44xx_l4_cfg_hwmod, | |
3656 | .slave = &omap44xx_dsp_hwmod, | |
3657 | .clk = "l4_div_ck", | |
3658 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3659 | }; | |
3660 | ||
3661 | static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { | |
3662 | { | |
3663 | .pa_start = 0x58000000, | |
3664 | .pa_end = 0x5800007f, | |
3665 | .flags = ADDR_TYPE_RT | |
3666 | }, | |
3667 | { } | |
3668 | }; | |
3669 | ||
3670 | /* l3_main_2 -> dss */ | |
3671 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { | |
3672 | .master = &omap44xx_l3_main_2_hwmod, | |
3673 | .slave = &omap44xx_dss_hwmod, | |
3674 | .clk = "dss_fck", | |
3675 | .addr = omap44xx_dss_dma_addrs, | |
3676 | .user = OCP_USER_SDMA, | |
3677 | }; | |
3678 | ||
3679 | static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { | |
3680 | { | |
3681 | .pa_start = 0x48040000, | |
3682 | .pa_end = 0x4804007f, | |
3683 | .flags = ADDR_TYPE_RT | |
3684 | }, | |
3685 | { } | |
3686 | }; | |
3687 | ||
3688 | /* l4_per -> dss */ | |
3689 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { | |
3690 | .master = &omap44xx_l4_per_hwmod, | |
3691 | .slave = &omap44xx_dss_hwmod, | |
3692 | .clk = "l4_div_ck", | |
3693 | .addr = omap44xx_dss_addrs, | |
3694 | .user = OCP_USER_MPU, | |
3695 | }; | |
3696 | ||
3697 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { | |
3698 | { | |
3699 | .pa_start = 0x58001000, | |
3700 | .pa_end = 0x58001fff, | |
3701 | .flags = ADDR_TYPE_RT | |
3702 | }, | |
3703 | { } | |
3704 | }; | |
3705 | ||
3706 | /* l3_main_2 -> dss_dispc */ | |
3707 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { | |
3708 | .master = &omap44xx_l3_main_2_hwmod, | |
3709 | .slave = &omap44xx_dss_dispc_hwmod, | |
3710 | .clk = "dss_fck", | |
3711 | .addr = omap44xx_dss_dispc_dma_addrs, | |
3712 | .user = OCP_USER_SDMA, | |
3713 | }; | |
3714 | ||
3715 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { | |
3716 | { | |
3717 | .pa_start = 0x48041000, | |
3718 | .pa_end = 0x48041fff, | |
3719 | .flags = ADDR_TYPE_RT | |
3720 | }, | |
3721 | { } | |
3722 | }; | |
3723 | ||
3724 | /* l4_per -> dss_dispc */ | |
3725 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { | |
3726 | .master = &omap44xx_l4_per_hwmod, | |
3727 | .slave = &omap44xx_dss_dispc_hwmod, | |
3728 | .clk = "l4_div_ck", | |
3729 | .addr = omap44xx_dss_dispc_addrs, | |
3730 | .user = OCP_USER_MPU, | |
3731 | }; | |
3732 | ||
3733 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { | |
3734 | { | |
3735 | .pa_start = 0x58004000, | |
3736 | .pa_end = 0x580041ff, | |
3737 | .flags = ADDR_TYPE_RT | |
3738 | }, | |
3739 | { } | |
3740 | }; | |
3741 | ||
3742 | /* l3_main_2 -> dss_dsi1 */ | |
3743 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { | |
3744 | .master = &omap44xx_l3_main_2_hwmod, | |
3745 | .slave = &omap44xx_dss_dsi1_hwmod, | |
3746 | .clk = "dss_fck", | |
3747 | .addr = omap44xx_dss_dsi1_dma_addrs, | |
3748 | .user = OCP_USER_SDMA, | |
3749 | }; | |
3750 | ||
3751 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { | |
3752 | { | |
3753 | .pa_start = 0x48044000, | |
3754 | .pa_end = 0x480441ff, | |
3755 | .flags = ADDR_TYPE_RT | |
3756 | }, | |
3757 | { } | |
3758 | }; | |
3759 | ||
3760 | /* l4_per -> dss_dsi1 */ | |
3761 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { | |
3762 | .master = &omap44xx_l4_per_hwmod, | |
3763 | .slave = &omap44xx_dss_dsi1_hwmod, | |
3764 | .clk = "l4_div_ck", | |
3765 | .addr = omap44xx_dss_dsi1_addrs, | |
3766 | .user = OCP_USER_MPU, | |
3767 | }; | |
3768 | ||
3769 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { | |
3770 | { | |
3771 | .pa_start = 0x58005000, | |
3772 | .pa_end = 0x580051ff, | |
3773 | .flags = ADDR_TYPE_RT | |
3774 | }, | |
3775 | { } | |
3776 | }; | |
3777 | ||
3778 | /* l3_main_2 -> dss_dsi2 */ | |
3779 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { | |
3780 | .master = &omap44xx_l3_main_2_hwmod, | |
3781 | .slave = &omap44xx_dss_dsi2_hwmod, | |
3782 | .clk = "dss_fck", | |
3783 | .addr = omap44xx_dss_dsi2_dma_addrs, | |
3784 | .user = OCP_USER_SDMA, | |
3785 | }; | |
3786 | ||
3787 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { | |
3788 | { | |
3789 | .pa_start = 0x48045000, | |
3790 | .pa_end = 0x480451ff, | |
3791 | .flags = ADDR_TYPE_RT | |
3792 | }, | |
3793 | { } | |
3794 | }; | |
3795 | ||
3796 | /* l4_per -> dss_dsi2 */ | |
3797 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { | |
3798 | .master = &omap44xx_l4_per_hwmod, | |
3799 | .slave = &omap44xx_dss_dsi2_hwmod, | |
3800 | .clk = "l4_div_ck", | |
3801 | .addr = omap44xx_dss_dsi2_addrs, | |
3802 | .user = OCP_USER_MPU, | |
3803 | }; | |
3804 | ||
3805 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { | |
3806 | { | |
3807 | .pa_start = 0x58006000, | |
3808 | .pa_end = 0x58006fff, | |
3809 | .flags = ADDR_TYPE_RT | |
3810 | }, | |
3811 | { } | |
3812 | }; | |
3813 | ||
3814 | /* l3_main_2 -> dss_hdmi */ | |
3815 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { | |
3816 | .master = &omap44xx_l3_main_2_hwmod, | |
3817 | .slave = &omap44xx_dss_hdmi_hwmod, | |
3818 | .clk = "dss_fck", | |
3819 | .addr = omap44xx_dss_hdmi_dma_addrs, | |
3820 | .user = OCP_USER_SDMA, | |
3821 | }; | |
3822 | ||
3823 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { | |
3824 | { | |
3825 | .pa_start = 0x48046000, | |
3826 | .pa_end = 0x48046fff, | |
3827 | .flags = ADDR_TYPE_RT | |
3828 | }, | |
3829 | { } | |
3830 | }; | |
3831 | ||
3832 | /* l4_per -> dss_hdmi */ | |
3833 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { | |
3834 | .master = &omap44xx_l4_per_hwmod, | |
3835 | .slave = &omap44xx_dss_hdmi_hwmod, | |
3836 | .clk = "l4_div_ck", | |
3837 | .addr = omap44xx_dss_hdmi_addrs, | |
3838 | .user = OCP_USER_MPU, | |
3839 | }; | |
3840 | ||
3841 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { | |
3842 | { | |
3843 | .pa_start = 0x58002000, | |
3844 | .pa_end = 0x580020ff, | |
3845 | .flags = ADDR_TYPE_RT | |
3846 | }, | |
3847 | { } | |
3848 | }; | |
3849 | ||
3850 | /* l3_main_2 -> dss_rfbi */ | |
3851 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { | |
3852 | .master = &omap44xx_l3_main_2_hwmod, | |
3853 | .slave = &omap44xx_dss_rfbi_hwmod, | |
3854 | .clk = "dss_fck", | |
3855 | .addr = omap44xx_dss_rfbi_dma_addrs, | |
3856 | .user = OCP_USER_SDMA, | |
3857 | }; | |
3858 | ||
3859 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { | |
3860 | { | |
3861 | .pa_start = 0x48042000, | |
3862 | .pa_end = 0x480420ff, | |
3863 | .flags = ADDR_TYPE_RT | |
3864 | }, | |
3865 | { } | |
3866 | }; | |
3867 | ||
3868 | /* l4_per -> dss_rfbi */ | |
3869 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { | |
3870 | .master = &omap44xx_l4_per_hwmod, | |
3871 | .slave = &omap44xx_dss_rfbi_hwmod, | |
3872 | .clk = "l4_div_ck", | |
3873 | .addr = omap44xx_dss_rfbi_addrs, | |
3874 | .user = OCP_USER_MPU, | |
3875 | }; | |
3876 | ||
3877 | static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { | |
3878 | { | |
3879 | .pa_start = 0x58003000, | |
3880 | .pa_end = 0x580030ff, | |
3881 | .flags = ADDR_TYPE_RT | |
3882 | }, | |
3883 | { } | |
3884 | }; | |
3885 | ||
3886 | /* l3_main_2 -> dss_venc */ | |
3887 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { | |
3888 | .master = &omap44xx_l3_main_2_hwmod, | |
3889 | .slave = &omap44xx_dss_venc_hwmod, | |
3890 | .clk = "dss_fck", | |
3891 | .addr = omap44xx_dss_venc_dma_addrs, | |
3892 | .user = OCP_USER_SDMA, | |
3893 | }; | |
3894 | ||
3895 | static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { | |
3896 | { | |
3897 | .pa_start = 0x48043000, | |
3898 | .pa_end = 0x480430ff, | |
3899 | .flags = ADDR_TYPE_RT | |
3900 | }, | |
3901 | { } | |
3902 | }; | |
3903 | ||
3904 | /* l4_per -> dss_venc */ | |
3905 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { | |
3906 | .master = &omap44xx_l4_per_hwmod, | |
3907 | .slave = &omap44xx_dss_venc_hwmod, | |
3908 | .clk = "l4_div_ck", | |
3909 | .addr = omap44xx_dss_venc_addrs, | |
3910 | .user = OCP_USER_MPU, | |
3911 | }; | |
3912 | ||
42b9e387 PW |
3913 | static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = { |
3914 | { | |
3915 | .pa_start = 0x48078000, | |
3916 | .pa_end = 0x48078fff, | |
3917 | .flags = ADDR_TYPE_RT | |
3918 | }, | |
3919 | { } | |
3920 | }; | |
3921 | ||
3922 | /* l4_per -> elm */ | |
3923 | static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = { | |
3924 | .master = &omap44xx_l4_per_hwmod, | |
3925 | .slave = &omap44xx_elm_hwmod, | |
3926 | .clk = "l4_div_ck", | |
3927 | .addr = omap44xx_elm_addrs, | |
3928 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3929 | }; | |
3930 | ||
b050f688 ML |
3931 | static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = { |
3932 | { | |
3933 | .pa_start = 0x4a10a000, | |
3934 | .pa_end = 0x4a10a1ff, | |
3935 | .flags = ADDR_TYPE_RT | |
3936 | }, | |
3937 | { } | |
3938 | }; | |
3939 | ||
3940 | /* l4_cfg -> fdif */ | |
3941 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = { | |
3942 | .master = &omap44xx_l4_cfg_hwmod, | |
3943 | .slave = &omap44xx_fdif_hwmod, | |
3944 | .clk = "l4_div_ck", | |
3945 | .addr = omap44xx_fdif_addrs, | |
3946 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3947 | }; | |
3948 | ||
844a3b63 PW |
3949 | /* l4_wkup -> gpio1 */ |
3950 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { | |
3951 | .master = &omap44xx_l4_wkup_hwmod, | |
3952 | .slave = &omap44xx_gpio1_hwmod, | |
3953 | .clk = "l4_wkup_clk_mux_ck", | |
844a3b63 PW |
3954 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3955 | }; | |
3956 | ||
844a3b63 PW |
3957 | /* l4_per -> gpio2 */ |
3958 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { | |
3959 | .master = &omap44xx_l4_per_hwmod, | |
3960 | .slave = &omap44xx_gpio2_hwmod, | |
3961 | .clk = "l4_div_ck", | |
844a3b63 PW |
3962 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3963 | }; | |
3964 | ||
844a3b63 PW |
3965 | /* l4_per -> gpio3 */ |
3966 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { | |
3967 | .master = &omap44xx_l4_per_hwmod, | |
3968 | .slave = &omap44xx_gpio3_hwmod, | |
3969 | .clk = "l4_div_ck", | |
844a3b63 PW |
3970 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3971 | }; | |
3972 | ||
844a3b63 PW |
3973 | /* l4_per -> gpio4 */ |
3974 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { | |
3975 | .master = &omap44xx_l4_per_hwmod, | |
3976 | .slave = &omap44xx_gpio4_hwmod, | |
3977 | .clk = "l4_div_ck", | |
844a3b63 PW |
3978 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3979 | }; | |
3980 | ||
844a3b63 PW |
3981 | /* l4_per -> gpio5 */ |
3982 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { | |
3983 | .master = &omap44xx_l4_per_hwmod, | |
3984 | .slave = &omap44xx_gpio5_hwmod, | |
3985 | .clk = "l4_div_ck", | |
844a3b63 PW |
3986 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3987 | }; | |
3988 | ||
844a3b63 PW |
3989 | /* l4_per -> gpio6 */ |
3990 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { | |
3991 | .master = &omap44xx_l4_per_hwmod, | |
3992 | .slave = &omap44xx_gpio6_hwmod, | |
3993 | .clk = "l4_div_ck", | |
844a3b63 PW |
3994 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3995 | }; | |
3996 | ||
eb42b5d3 BC |
3997 | /* l3_main_2 -> gpmc */ |
3998 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { | |
3999 | .master = &omap44xx_l3_main_2_hwmod, | |
4000 | .slave = &omap44xx_gpmc_hwmod, | |
4001 | .clk = "l3_div_ck", | |
eb42b5d3 BC |
4002 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4003 | }; | |
4004 | ||
9def390e PW |
4005 | static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = { |
4006 | { | |
4007 | .pa_start = 0x56000000, | |
4008 | .pa_end = 0x5600ffff, | |
4009 | .flags = ADDR_TYPE_RT | |
4010 | }, | |
4011 | { } | |
4012 | }; | |
4013 | ||
4014 | /* l3_main_2 -> gpu */ | |
4015 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = { | |
4016 | .master = &omap44xx_l3_main_2_hwmod, | |
4017 | .slave = &omap44xx_gpu_hwmod, | |
4018 | .clk = "l3_div_ck", | |
4019 | .addr = omap44xx_gpu_addrs, | |
4020 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4021 | }; | |
4022 | ||
a091c08e PW |
4023 | static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = { |
4024 | { | |
4025 | .pa_start = 0x480b2000, | |
4026 | .pa_end = 0x480b201f, | |
4027 | .flags = ADDR_TYPE_RT | |
4028 | }, | |
4029 | { } | |
4030 | }; | |
4031 | ||
4032 | /* l4_per -> hdq1w */ | |
4033 | static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = { | |
4034 | .master = &omap44xx_l4_per_hwmod, | |
4035 | .slave = &omap44xx_hdq1w_hwmod, | |
4036 | .clk = "l4_div_ck", | |
4037 | .addr = omap44xx_hdq1w_addrs, | |
4038 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4039 | }; | |
4040 | ||
844a3b63 PW |
4041 | static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { |
4042 | { | |
4043 | .pa_start = 0x4a058000, | |
4044 | .pa_end = 0x4a05bfff, | |
4045 | .flags = ADDR_TYPE_RT | |
4046 | }, | |
4047 | { } | |
4048 | }; | |
4049 | ||
4050 | /* l4_cfg -> hsi */ | |
4051 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { | |
4052 | .master = &omap44xx_l4_cfg_hwmod, | |
4053 | .slave = &omap44xx_hsi_hwmod, | |
4054 | .clk = "l4_div_ck", | |
4055 | .addr = omap44xx_hsi_addrs, | |
4056 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4057 | }; | |
4058 | ||
844a3b63 PW |
4059 | /* l4_per -> i2c1 */ |
4060 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { | |
4061 | .master = &omap44xx_l4_per_hwmod, | |
4062 | .slave = &omap44xx_i2c1_hwmod, | |
4063 | .clk = "l4_div_ck", | |
844a3b63 PW |
4064 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4065 | }; | |
4066 | ||
844a3b63 PW |
4067 | /* l4_per -> i2c2 */ |
4068 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { | |
4069 | .master = &omap44xx_l4_per_hwmod, | |
4070 | .slave = &omap44xx_i2c2_hwmod, | |
4071 | .clk = "l4_div_ck", | |
844a3b63 PW |
4072 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4073 | }; | |
4074 | ||
844a3b63 PW |
4075 | /* l4_per -> i2c3 */ |
4076 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { | |
4077 | .master = &omap44xx_l4_per_hwmod, | |
4078 | .slave = &omap44xx_i2c3_hwmod, | |
4079 | .clk = "l4_div_ck", | |
844a3b63 PW |
4080 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4081 | }; | |
4082 | ||
844a3b63 PW |
4083 | /* l4_per -> i2c4 */ |
4084 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { | |
4085 | .master = &omap44xx_l4_per_hwmod, | |
4086 | .slave = &omap44xx_i2c4_hwmod, | |
4087 | .clk = "l4_div_ck", | |
844a3b63 PW |
4088 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4089 | }; | |
4090 | ||
4091 | /* l3_main_2 -> ipu */ | |
4092 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { | |
4093 | .master = &omap44xx_l3_main_2_hwmod, | |
4094 | .slave = &omap44xx_ipu_hwmod, | |
4095 | .clk = "l3_div_ck", | |
4096 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4097 | }; | |
4098 | ||
4099 | static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { | |
4100 | { | |
4101 | .pa_start = 0x52000000, | |
4102 | .pa_end = 0x520000ff, | |
4103 | .flags = ADDR_TYPE_RT | |
4104 | }, | |
4105 | { } | |
4106 | }; | |
4107 | ||
4108 | /* l3_main_2 -> iss */ | |
4109 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { | |
4110 | .master = &omap44xx_l3_main_2_hwmod, | |
4111 | .slave = &omap44xx_iss_hwmod, | |
4112 | .clk = "l3_div_ck", | |
4113 | .addr = omap44xx_iss_addrs, | |
4114 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4115 | }; | |
4116 | ||
42b9e387 | 4117 | /* iva -> sl2if */ |
b360124e | 4118 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = { |
42b9e387 PW |
4119 | .master = &omap44xx_iva_hwmod, |
4120 | .slave = &omap44xx_sl2if_hwmod, | |
4121 | .clk = "dpll_iva_m5x2_ck", | |
4122 | .user = OCP_USER_IVA, | |
4123 | }; | |
4124 | ||
844a3b63 PW |
4125 | /* l3_main_2 -> iva */ |
4126 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { | |
4127 | .master = &omap44xx_l3_main_2_hwmod, | |
4128 | .slave = &omap44xx_iva_hwmod, | |
4129 | .clk = "l3_div_ck", | |
844a3b63 PW |
4130 | .user = OCP_USER_MPU, |
4131 | }; | |
4132 | ||
844a3b63 PW |
4133 | /* l4_wkup -> kbd */ |
4134 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { | |
4135 | .master = &omap44xx_l4_wkup_hwmod, | |
4136 | .slave = &omap44xx_kbd_hwmod, | |
4137 | .clk = "l4_wkup_clk_mux_ck", | |
844a3b63 PW |
4138 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4139 | }; | |
4140 | ||
4141 | static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { | |
4142 | { | |
4143 | .pa_start = 0x4a0f4000, | |
4144 | .pa_end = 0x4a0f41ff, | |
4145 | .flags = ADDR_TYPE_RT | |
4146 | }, | |
4147 | { } | |
4148 | }; | |
4149 | ||
4150 | /* l4_cfg -> mailbox */ | |
4151 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { | |
4152 | .master = &omap44xx_l4_cfg_hwmod, | |
4153 | .slave = &omap44xx_mailbox_hwmod, | |
4154 | .clk = "l4_div_ck", | |
4155 | .addr = omap44xx_mailbox_addrs, | |
4156 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4157 | }; | |
4158 | ||
896d4e98 BC |
4159 | static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = { |
4160 | { | |
4161 | .pa_start = 0x40128000, | |
4162 | .pa_end = 0x401283ff, | |
4163 | .flags = ADDR_TYPE_RT | |
4164 | }, | |
4165 | { } | |
4166 | }; | |
4167 | ||
4168 | /* l4_abe -> mcasp */ | |
4169 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = { | |
4170 | .master = &omap44xx_l4_abe_hwmod, | |
4171 | .slave = &omap44xx_mcasp_hwmod, | |
4172 | .clk = "ocp_abe_iclk", | |
4173 | .addr = omap44xx_mcasp_addrs, | |
4174 | .user = OCP_USER_MPU, | |
4175 | }; | |
4176 | ||
4177 | static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = { | |
4178 | { | |
4179 | .pa_start = 0x49028000, | |
4180 | .pa_end = 0x490283ff, | |
4181 | .flags = ADDR_TYPE_RT | |
4182 | }, | |
4183 | { } | |
4184 | }; | |
4185 | ||
4186 | /* l4_abe -> mcasp (dma) */ | |
4187 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = { | |
4188 | .master = &omap44xx_l4_abe_hwmod, | |
4189 | .slave = &omap44xx_mcasp_hwmod, | |
4190 | .clk = "ocp_abe_iclk", | |
4191 | .addr = omap44xx_mcasp_dma_addrs, | |
4192 | .user = OCP_USER_SDMA, | |
4193 | }; | |
4194 | ||
844a3b63 PW |
4195 | /* l4_abe -> mcbsp1 */ |
4196 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { | |
4197 | .master = &omap44xx_l4_abe_hwmod, | |
4198 | .slave = &omap44xx_mcbsp1_hwmod, | |
4199 | .clk = "ocp_abe_iclk", | |
e3491795 | 4200 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4201 | }; |
4202 | ||
844a3b63 PW |
4203 | /* l4_abe -> mcbsp2 */ |
4204 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { | |
4205 | .master = &omap44xx_l4_abe_hwmod, | |
4206 | .slave = &omap44xx_mcbsp2_hwmod, | |
4207 | .clk = "ocp_abe_iclk", | |
e3491795 | 4208 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4209 | }; |
4210 | ||
844a3b63 PW |
4211 | /* l4_abe -> mcbsp3 */ |
4212 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { | |
4213 | .master = &omap44xx_l4_abe_hwmod, | |
4214 | .slave = &omap44xx_mcbsp3_hwmod, | |
4215 | .clk = "ocp_abe_iclk", | |
e3491795 | 4216 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4217 | }; |
4218 | ||
844a3b63 PW |
4219 | /* l4_per -> mcbsp4 */ |
4220 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { | |
4221 | .master = &omap44xx_l4_per_hwmod, | |
4222 | .slave = &omap44xx_mcbsp4_hwmod, | |
4223 | .clk = "l4_div_ck", | |
844a3b63 PW |
4224 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4225 | }; | |
4226 | ||
844a3b63 PW |
4227 | /* l4_abe -> mcpdm */ |
4228 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { | |
4229 | .master = &omap44xx_l4_abe_hwmod, | |
4230 | .slave = &omap44xx_mcpdm_hwmod, | |
4231 | .clk = "ocp_abe_iclk", | |
e3491795 | 4232 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4233 | }; |
4234 | ||
844a3b63 PW |
4235 | /* l4_per -> mcspi1 */ |
4236 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { | |
4237 | .master = &omap44xx_l4_per_hwmod, | |
4238 | .slave = &omap44xx_mcspi1_hwmod, | |
4239 | .clk = "l4_div_ck", | |
844a3b63 PW |
4240 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4241 | }; | |
4242 | ||
844a3b63 PW |
4243 | /* l4_per -> mcspi2 */ |
4244 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { | |
4245 | .master = &omap44xx_l4_per_hwmod, | |
4246 | .slave = &omap44xx_mcspi2_hwmod, | |
4247 | .clk = "l4_div_ck", | |
844a3b63 PW |
4248 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4249 | }; | |
4250 | ||
844a3b63 PW |
4251 | /* l4_per -> mcspi3 */ |
4252 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { | |
4253 | .master = &omap44xx_l4_per_hwmod, | |
4254 | .slave = &omap44xx_mcspi3_hwmod, | |
4255 | .clk = "l4_div_ck", | |
844a3b63 PW |
4256 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4257 | }; | |
4258 | ||
844a3b63 PW |
4259 | /* l4_per -> mcspi4 */ |
4260 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { | |
4261 | .master = &omap44xx_l4_per_hwmod, | |
4262 | .slave = &omap44xx_mcspi4_hwmod, | |
4263 | .clk = "l4_div_ck", | |
844a3b63 PW |
4264 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4265 | }; | |
4266 | ||
844a3b63 PW |
4267 | /* l4_per -> mmc1 */ |
4268 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { | |
4269 | .master = &omap44xx_l4_per_hwmod, | |
4270 | .slave = &omap44xx_mmc1_hwmod, | |
4271 | .clk = "l4_div_ck", | |
844a3b63 PW |
4272 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4273 | }; | |
4274 | ||
844a3b63 PW |
4275 | /* l4_per -> mmc2 */ |
4276 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { | |
4277 | .master = &omap44xx_l4_per_hwmod, | |
4278 | .slave = &omap44xx_mmc2_hwmod, | |
4279 | .clk = "l4_div_ck", | |
844a3b63 PW |
4280 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4281 | }; | |
4282 | ||
844a3b63 PW |
4283 | /* l4_per -> mmc3 */ |
4284 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { | |
4285 | .master = &omap44xx_l4_per_hwmod, | |
4286 | .slave = &omap44xx_mmc3_hwmod, | |
4287 | .clk = "l4_div_ck", | |
844a3b63 PW |
4288 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4289 | }; | |
4290 | ||
844a3b63 PW |
4291 | /* l4_per -> mmc4 */ |
4292 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { | |
4293 | .master = &omap44xx_l4_per_hwmod, | |
4294 | .slave = &omap44xx_mmc4_hwmod, | |
4295 | .clk = "l4_div_ck", | |
844a3b63 PW |
4296 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4297 | }; | |
4298 | ||
844a3b63 PW |
4299 | /* l4_per -> mmc5 */ |
4300 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { | |
4301 | .master = &omap44xx_l4_per_hwmod, | |
4302 | .slave = &omap44xx_mmc5_hwmod, | |
4303 | .clk = "l4_div_ck", | |
844a3b63 PW |
4304 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4305 | }; | |
4306 | ||
e17f18c0 PW |
4307 | /* l3_main_2 -> ocmc_ram */ |
4308 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = { | |
4309 | .master = &omap44xx_l3_main_2_hwmod, | |
4310 | .slave = &omap44xx_ocmc_ram_hwmod, | |
4311 | .clk = "l3_div_ck", | |
4312 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4313 | }; | |
4314 | ||
0c668875 BC |
4315 | /* l4_cfg -> ocp2scp_usb_phy */ |
4316 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = { | |
4317 | .master = &omap44xx_l4_cfg_hwmod, | |
4318 | .slave = &omap44xx_ocp2scp_usb_phy_hwmod, | |
4319 | .clk = "l4_div_ck", | |
4320 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4321 | }; | |
4322 | ||
794b480a PW |
4323 | /* mpu_private -> prcm_mpu */ |
4324 | static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = { | |
4325 | .master = &omap44xx_mpu_private_hwmod, | |
4326 | .slave = &omap44xx_prcm_mpu_hwmod, | |
4327 | .clk = "l3_div_ck", | |
794b480a PW |
4328 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4329 | }; | |
4330 | ||
794b480a PW |
4331 | /* l4_wkup -> cm_core_aon */ |
4332 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = { | |
4333 | .master = &omap44xx_l4_wkup_hwmod, | |
4334 | .slave = &omap44xx_cm_core_aon_hwmod, | |
4335 | .clk = "l4_wkup_clk_mux_ck", | |
794b480a PW |
4336 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4337 | }; | |
4338 | ||
794b480a PW |
4339 | /* l4_cfg -> cm_core */ |
4340 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = { | |
4341 | .master = &omap44xx_l4_cfg_hwmod, | |
4342 | .slave = &omap44xx_cm_core_hwmod, | |
4343 | .clk = "l4_div_ck", | |
794b480a PW |
4344 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4345 | }; | |
4346 | ||
794b480a PW |
4347 | /* l4_wkup -> prm */ |
4348 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = { | |
4349 | .master = &omap44xx_l4_wkup_hwmod, | |
4350 | .slave = &omap44xx_prm_hwmod, | |
4351 | .clk = "l4_wkup_clk_mux_ck", | |
794b480a PW |
4352 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4353 | }; | |
4354 | ||
794b480a PW |
4355 | /* l4_wkup -> scrm */ |
4356 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = { | |
4357 | .master = &omap44xx_l4_wkup_hwmod, | |
4358 | .slave = &omap44xx_scrm_hwmod, | |
4359 | .clk = "l4_wkup_clk_mux_ck", | |
794b480a PW |
4360 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4361 | }; | |
4362 | ||
42b9e387 | 4363 | /* l3_main_2 -> sl2if */ |
b360124e | 4364 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = { |
42b9e387 PW |
4365 | .master = &omap44xx_l3_main_2_hwmod, |
4366 | .slave = &omap44xx_sl2if_hwmod, | |
4367 | .clk = "l3_div_ck", | |
4368 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4369 | }; | |
4370 | ||
1e3b5e59 BC |
4371 | static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = { |
4372 | { | |
4373 | .pa_start = 0x4012c000, | |
4374 | .pa_end = 0x4012c3ff, | |
4375 | .flags = ADDR_TYPE_RT | |
4376 | }, | |
4377 | { } | |
4378 | }; | |
4379 | ||
4380 | /* l4_abe -> slimbus1 */ | |
4381 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = { | |
4382 | .master = &omap44xx_l4_abe_hwmod, | |
4383 | .slave = &omap44xx_slimbus1_hwmod, | |
4384 | .clk = "ocp_abe_iclk", | |
4385 | .addr = omap44xx_slimbus1_addrs, | |
4386 | .user = OCP_USER_MPU, | |
4387 | }; | |
4388 | ||
4389 | static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = { | |
4390 | { | |
4391 | .pa_start = 0x4902c000, | |
4392 | .pa_end = 0x4902c3ff, | |
4393 | .flags = ADDR_TYPE_RT | |
4394 | }, | |
4395 | { } | |
4396 | }; | |
4397 | ||
4398 | /* l4_abe -> slimbus1 (dma) */ | |
4399 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = { | |
4400 | .master = &omap44xx_l4_abe_hwmod, | |
4401 | .slave = &omap44xx_slimbus1_hwmod, | |
4402 | .clk = "ocp_abe_iclk", | |
4403 | .addr = omap44xx_slimbus1_dma_addrs, | |
4404 | .user = OCP_USER_SDMA, | |
4405 | }; | |
4406 | ||
4407 | static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = { | |
4408 | { | |
4409 | .pa_start = 0x48076000, | |
4410 | .pa_end = 0x480763ff, | |
4411 | .flags = ADDR_TYPE_RT | |
4412 | }, | |
4413 | { } | |
4414 | }; | |
4415 | ||
4416 | /* l4_per -> slimbus2 */ | |
4417 | static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = { | |
4418 | .master = &omap44xx_l4_per_hwmod, | |
4419 | .slave = &omap44xx_slimbus2_hwmod, | |
4420 | .clk = "l4_div_ck", | |
4421 | .addr = omap44xx_slimbus2_addrs, | |
4422 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4423 | }; | |
4424 | ||
844a3b63 PW |
4425 | static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { |
4426 | { | |
4427 | .pa_start = 0x4a0dd000, | |
4428 | .pa_end = 0x4a0dd03f, | |
4429 | .flags = ADDR_TYPE_RT | |
4430 | }, | |
4431 | { } | |
4432 | }; | |
4433 | ||
4434 | /* l4_cfg -> smartreflex_core */ | |
4435 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { | |
4436 | .master = &omap44xx_l4_cfg_hwmod, | |
4437 | .slave = &omap44xx_smartreflex_core_hwmod, | |
4438 | .clk = "l4_div_ck", | |
4439 | .addr = omap44xx_smartreflex_core_addrs, | |
4440 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4441 | }; | |
4442 | ||
4443 | static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { | |
4444 | { | |
4445 | .pa_start = 0x4a0db000, | |
4446 | .pa_end = 0x4a0db03f, | |
4447 | .flags = ADDR_TYPE_RT | |
4448 | }, | |
4449 | { } | |
4450 | }; | |
4451 | ||
4452 | /* l4_cfg -> smartreflex_iva */ | |
4453 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { | |
4454 | .master = &omap44xx_l4_cfg_hwmod, | |
4455 | .slave = &omap44xx_smartreflex_iva_hwmod, | |
4456 | .clk = "l4_div_ck", | |
4457 | .addr = omap44xx_smartreflex_iva_addrs, | |
4458 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4459 | }; | |
4460 | ||
4461 | static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { | |
4462 | { | |
4463 | .pa_start = 0x4a0d9000, | |
4464 | .pa_end = 0x4a0d903f, | |
4465 | .flags = ADDR_TYPE_RT | |
4466 | }, | |
4467 | { } | |
4468 | }; | |
4469 | ||
4470 | /* l4_cfg -> smartreflex_mpu */ | |
4471 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { | |
4472 | .master = &omap44xx_l4_cfg_hwmod, | |
4473 | .slave = &omap44xx_smartreflex_mpu_hwmod, | |
4474 | .clk = "l4_div_ck", | |
4475 | .addr = omap44xx_smartreflex_mpu_addrs, | |
4476 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4477 | }; | |
4478 | ||
4479 | static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { | |
4480 | { | |
4481 | .pa_start = 0x4a0f6000, | |
4482 | .pa_end = 0x4a0f6fff, | |
4483 | .flags = ADDR_TYPE_RT | |
4484 | }, | |
4485 | { } | |
4486 | }; | |
4487 | ||
4488 | /* l4_cfg -> spinlock */ | |
4489 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { | |
4490 | .master = &omap44xx_l4_cfg_hwmod, | |
4491 | .slave = &omap44xx_spinlock_hwmod, | |
4492 | .clk = "l4_div_ck", | |
4493 | .addr = omap44xx_spinlock_addrs, | |
4494 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4495 | }; | |
4496 | ||
844a3b63 PW |
4497 | /* l4_wkup -> timer1 */ |
4498 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { | |
4499 | .master = &omap44xx_l4_wkup_hwmod, | |
4500 | .slave = &omap44xx_timer1_hwmod, | |
4501 | .clk = "l4_wkup_clk_mux_ck", | |
844a3b63 PW |
4502 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4503 | }; | |
4504 | ||
844a3b63 PW |
4505 | /* l4_per -> timer2 */ |
4506 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { | |
4507 | .master = &omap44xx_l4_per_hwmod, | |
4508 | .slave = &omap44xx_timer2_hwmod, | |
4509 | .clk = "l4_div_ck", | |
844a3b63 PW |
4510 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4511 | }; | |
4512 | ||
844a3b63 PW |
4513 | /* l4_per -> timer3 */ |
4514 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { | |
4515 | .master = &omap44xx_l4_per_hwmod, | |
4516 | .slave = &omap44xx_timer3_hwmod, | |
4517 | .clk = "l4_div_ck", | |
844a3b63 PW |
4518 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4519 | }; | |
4520 | ||
844a3b63 PW |
4521 | /* l4_per -> timer4 */ |
4522 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { | |
4523 | .master = &omap44xx_l4_per_hwmod, | |
4524 | .slave = &omap44xx_timer4_hwmod, | |
4525 | .clk = "l4_div_ck", | |
844a3b63 PW |
4526 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4527 | }; | |
4528 | ||
844a3b63 PW |
4529 | /* l4_abe -> timer5 */ |
4530 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { | |
4531 | .master = &omap44xx_l4_abe_hwmod, | |
4532 | .slave = &omap44xx_timer5_hwmod, | |
4533 | .clk = "ocp_abe_iclk", | |
e3491795 | 4534 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4535 | }; |
4536 | ||
844a3b63 PW |
4537 | /* l4_abe -> timer6 */ |
4538 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { | |
4539 | .master = &omap44xx_l4_abe_hwmod, | |
4540 | .slave = &omap44xx_timer6_hwmod, | |
4541 | .clk = "ocp_abe_iclk", | |
e3491795 | 4542 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4543 | }; |
4544 | ||
844a3b63 PW |
4545 | /* l4_abe -> timer7 */ |
4546 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { | |
4547 | .master = &omap44xx_l4_abe_hwmod, | |
4548 | .slave = &omap44xx_timer7_hwmod, | |
4549 | .clk = "ocp_abe_iclk", | |
e3491795 | 4550 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4551 | }; |
4552 | ||
844a3b63 PW |
4553 | /* l4_abe -> timer8 */ |
4554 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { | |
4555 | .master = &omap44xx_l4_abe_hwmod, | |
4556 | .slave = &omap44xx_timer8_hwmod, | |
4557 | .clk = "ocp_abe_iclk", | |
e3491795 | 4558 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 PW |
4559 | }; |
4560 | ||
844a3b63 PW |
4561 | /* l4_per -> timer9 */ |
4562 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { | |
4563 | .master = &omap44xx_l4_per_hwmod, | |
4564 | .slave = &omap44xx_timer9_hwmod, | |
4565 | .clk = "l4_div_ck", | |
844a3b63 PW |
4566 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4567 | }; | |
4568 | ||
844a3b63 PW |
4569 | /* l4_per -> timer10 */ |
4570 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { | |
4571 | .master = &omap44xx_l4_per_hwmod, | |
4572 | .slave = &omap44xx_timer10_hwmod, | |
4573 | .clk = "l4_div_ck", | |
844a3b63 PW |
4574 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4575 | }; | |
4576 | ||
844a3b63 PW |
4577 | /* l4_per -> timer11 */ |
4578 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { | |
4579 | .master = &omap44xx_l4_per_hwmod, | |
4580 | .slave = &omap44xx_timer11_hwmod, | |
4581 | .clk = "l4_div_ck", | |
af88fa9a BC |
4582 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4583 | }; | |
4584 | ||
844a3b63 PW |
4585 | /* l4_per -> uart1 */ |
4586 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { | |
4587 | .master = &omap44xx_l4_per_hwmod, | |
4588 | .slave = &omap44xx_uart1_hwmod, | |
4589 | .clk = "l4_div_ck", | |
844a3b63 PW |
4590 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4591 | }; | |
af88fa9a | 4592 | |
844a3b63 PW |
4593 | /* l4_per -> uart2 */ |
4594 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { | |
4595 | .master = &omap44xx_l4_per_hwmod, | |
4596 | .slave = &omap44xx_uart2_hwmod, | |
4597 | .clk = "l4_div_ck", | |
844a3b63 PW |
4598 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4599 | }; | |
af88fa9a | 4600 | |
844a3b63 PW |
4601 | /* l4_per -> uart3 */ |
4602 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { | |
4603 | .master = &omap44xx_l4_per_hwmod, | |
4604 | .slave = &omap44xx_uart3_hwmod, | |
4605 | .clk = "l4_div_ck", | |
844a3b63 | 4606 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
af88fa9a BC |
4607 | }; |
4608 | ||
844a3b63 PW |
4609 | /* l4_per -> uart4 */ |
4610 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { | |
4611 | .master = &omap44xx_l4_per_hwmod, | |
4612 | .slave = &omap44xx_uart4_hwmod, | |
4613 | .clk = "l4_div_ck", | |
844a3b63 PW |
4614 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4615 | }; | |
4616 | ||
0c668875 | 4617 | /* l4_cfg -> usb_host_fs */ |
b0a70cc8 | 4618 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = { |
0c668875 BC |
4619 | .master = &omap44xx_l4_cfg_hwmod, |
4620 | .slave = &omap44xx_usb_host_fs_hwmod, | |
4621 | .clk = "l4_div_ck", | |
0c668875 BC |
4622 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4623 | }; | |
4624 | ||
844a3b63 PW |
4625 | /* l4_cfg -> usb_host_hs */ |
4626 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { | |
4627 | .master = &omap44xx_l4_cfg_hwmod, | |
4628 | .slave = &omap44xx_usb_host_hs_hwmod, | |
4629 | .clk = "l4_div_ck", | |
844a3b63 PW |
4630 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4631 | }; | |
4632 | ||
844a3b63 PW |
4633 | /* l4_cfg -> usb_otg_hs */ |
4634 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { | |
4635 | .master = &omap44xx_l4_cfg_hwmod, | |
4636 | .slave = &omap44xx_usb_otg_hs_hwmod, | |
4637 | .clk = "l4_div_ck", | |
844a3b63 | 4638 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
af88fa9a BC |
4639 | }; |
4640 | ||
844a3b63 | 4641 | /* l4_cfg -> usb_tll_hs */ |
af88fa9a BC |
4642 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { |
4643 | .master = &omap44xx_l4_cfg_hwmod, | |
4644 | .slave = &omap44xx_usb_tll_hs_hwmod, | |
4645 | .clk = "l4_div_ck", | |
af88fa9a BC |
4646 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4647 | }; | |
4648 | ||
844a3b63 PW |
4649 | /* l4_wkup -> wd_timer2 */ |
4650 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { | |
4651 | .master = &omap44xx_l4_wkup_hwmod, | |
4652 | .slave = &omap44xx_wd_timer2_hwmod, | |
4653 | .clk = "l4_wkup_clk_mux_ck", | |
844a3b63 PW |
4654 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4655 | }; | |
4656 | ||
4657 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { | |
4658 | { | |
4659 | .pa_start = 0x40130000, | |
4660 | .pa_end = 0x4013007f, | |
4661 | .flags = ADDR_TYPE_RT | |
4662 | }, | |
4663 | { } | |
4664 | }; | |
4665 | ||
4666 | /* l4_abe -> wd_timer3 */ | |
4667 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { | |
4668 | .master = &omap44xx_l4_abe_hwmod, | |
4669 | .slave = &omap44xx_wd_timer3_hwmod, | |
4670 | .clk = "ocp_abe_iclk", | |
4671 | .addr = omap44xx_wd_timer3_addrs, | |
4672 | .user = OCP_USER_MPU, | |
4673 | }; | |
4674 | ||
4675 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { | |
4676 | { | |
4677 | .pa_start = 0x49030000, | |
4678 | .pa_end = 0x4903007f, | |
4679 | .flags = ADDR_TYPE_RT | |
4680 | }, | |
4681 | { } | |
4682 | }; | |
4683 | ||
4684 | /* l4_abe -> wd_timer3 (dma) */ | |
4685 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { | |
4686 | .master = &omap44xx_l4_abe_hwmod, | |
4687 | .slave = &omap44xx_wd_timer3_hwmod, | |
4688 | .clk = "ocp_abe_iclk", | |
4689 | .addr = omap44xx_wd_timer3_dma_addrs, | |
4690 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
4691 | }; |
4692 | ||
3b9b1015 S |
4693 | /* mpu -> emif1 */ |
4694 | static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = { | |
4695 | .master = &omap44xx_mpu_hwmod, | |
4696 | .slave = &omap44xx_emif1_hwmod, | |
4697 | .clk = "l3_div_ck", | |
4698 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4699 | }; | |
4700 | ||
4701 | /* mpu -> emif2 */ | |
4702 | static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = { | |
4703 | .master = &omap44xx_mpu_hwmod, | |
4704 | .slave = &omap44xx_emif2_hwmod, | |
4705 | .clk = "l3_div_ck", | |
4706 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4707 | }; | |
4708 | ||
0a78c5c5 PW |
4709 | static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { |
4710 | &omap44xx_l3_main_1__dmm, | |
4711 | &omap44xx_mpu__dmm, | |
0a78c5c5 PW |
4712 | &omap44xx_iva__l3_instr, |
4713 | &omap44xx_l3_main_3__l3_instr, | |
9a817bc8 | 4714 | &omap44xx_ocp_wp_noc__l3_instr, |
0a78c5c5 PW |
4715 | &omap44xx_dsp__l3_main_1, |
4716 | &omap44xx_dss__l3_main_1, | |
4717 | &omap44xx_l3_main_2__l3_main_1, | |
4718 | &omap44xx_l4_cfg__l3_main_1, | |
4719 | &omap44xx_mmc1__l3_main_1, | |
4720 | &omap44xx_mmc2__l3_main_1, | |
4721 | &omap44xx_mpu__l3_main_1, | |
96566043 | 4722 | &omap44xx_debugss__l3_main_2, |
0a78c5c5 | 4723 | &omap44xx_dma_system__l3_main_2, |
b050f688 | 4724 | &omap44xx_fdif__l3_main_2, |
9def390e | 4725 | &omap44xx_gpu__l3_main_2, |
0a78c5c5 PW |
4726 | &omap44xx_hsi__l3_main_2, |
4727 | &omap44xx_ipu__l3_main_2, | |
4728 | &omap44xx_iss__l3_main_2, | |
4729 | &omap44xx_iva__l3_main_2, | |
4730 | &omap44xx_l3_main_1__l3_main_2, | |
4731 | &omap44xx_l4_cfg__l3_main_2, | |
b0a70cc8 | 4732 | /* &omap44xx_usb_host_fs__l3_main_2, */ |
0a78c5c5 PW |
4733 | &omap44xx_usb_host_hs__l3_main_2, |
4734 | &omap44xx_usb_otg_hs__l3_main_2, | |
4735 | &omap44xx_l3_main_1__l3_main_3, | |
4736 | &omap44xx_l3_main_2__l3_main_3, | |
4737 | &omap44xx_l4_cfg__l3_main_3, | |
5cebb23c | 4738 | &omap44xx_aess__l4_abe, |
0a78c5c5 PW |
4739 | &omap44xx_dsp__l4_abe, |
4740 | &omap44xx_l3_main_1__l4_abe, | |
4741 | &omap44xx_mpu__l4_abe, | |
4742 | &omap44xx_l3_main_1__l4_cfg, | |
4743 | &omap44xx_l3_main_2__l4_per, | |
4744 | &omap44xx_l4_cfg__l4_wkup, | |
4745 | &omap44xx_mpu__mpu_private, | |
9a817bc8 | 4746 | &omap44xx_l4_cfg__ocp_wp_noc, |
5cebb23c SG |
4747 | &omap44xx_l4_abe__aess, |
4748 | &omap44xx_l4_abe__aess_dma, | |
42b9e387 | 4749 | &omap44xx_l3_main_2__c2c, |
0a78c5c5 | 4750 | &omap44xx_l4_wkup__counter_32k, |
a0b5d813 PW |
4751 | &omap44xx_l4_cfg__ctrl_module_core, |
4752 | &omap44xx_l4_cfg__ctrl_module_pad_core, | |
4753 | &omap44xx_l4_wkup__ctrl_module_wkup, | |
4754 | &omap44xx_l4_wkup__ctrl_module_pad_wkup, | |
96566043 | 4755 | &omap44xx_l3_instr__debugss, |
0a78c5c5 PW |
4756 | &omap44xx_l4_cfg__dma_system, |
4757 | &omap44xx_l4_abe__dmic, | |
0a78c5c5 | 4758 | &omap44xx_dsp__iva, |
b360124e | 4759 | /* &omap44xx_dsp__sl2if, */ |
0a78c5c5 PW |
4760 | &omap44xx_l4_cfg__dsp, |
4761 | &omap44xx_l3_main_2__dss, | |
4762 | &omap44xx_l4_per__dss, | |
4763 | &omap44xx_l3_main_2__dss_dispc, | |
4764 | &omap44xx_l4_per__dss_dispc, | |
4765 | &omap44xx_l3_main_2__dss_dsi1, | |
4766 | &omap44xx_l4_per__dss_dsi1, | |
4767 | &omap44xx_l3_main_2__dss_dsi2, | |
4768 | &omap44xx_l4_per__dss_dsi2, | |
4769 | &omap44xx_l3_main_2__dss_hdmi, | |
4770 | &omap44xx_l4_per__dss_hdmi, | |
4771 | &omap44xx_l3_main_2__dss_rfbi, | |
4772 | &omap44xx_l4_per__dss_rfbi, | |
4773 | &omap44xx_l3_main_2__dss_venc, | |
4774 | &omap44xx_l4_per__dss_venc, | |
42b9e387 | 4775 | &omap44xx_l4_per__elm, |
b050f688 | 4776 | &omap44xx_l4_cfg__fdif, |
0a78c5c5 PW |
4777 | &omap44xx_l4_wkup__gpio1, |
4778 | &omap44xx_l4_per__gpio2, | |
4779 | &omap44xx_l4_per__gpio3, | |
4780 | &omap44xx_l4_per__gpio4, | |
4781 | &omap44xx_l4_per__gpio5, | |
4782 | &omap44xx_l4_per__gpio6, | |
eb42b5d3 | 4783 | &omap44xx_l3_main_2__gpmc, |
9def390e | 4784 | &omap44xx_l3_main_2__gpu, |
a091c08e | 4785 | &omap44xx_l4_per__hdq1w, |
0a78c5c5 PW |
4786 | &omap44xx_l4_cfg__hsi, |
4787 | &omap44xx_l4_per__i2c1, | |
4788 | &omap44xx_l4_per__i2c2, | |
4789 | &omap44xx_l4_per__i2c3, | |
4790 | &omap44xx_l4_per__i2c4, | |
4791 | &omap44xx_l3_main_2__ipu, | |
4792 | &omap44xx_l3_main_2__iss, | |
b360124e | 4793 | /* &omap44xx_iva__sl2if, */ |
0a78c5c5 PW |
4794 | &omap44xx_l3_main_2__iva, |
4795 | &omap44xx_l4_wkup__kbd, | |
4796 | &omap44xx_l4_cfg__mailbox, | |
896d4e98 BC |
4797 | &omap44xx_l4_abe__mcasp, |
4798 | &omap44xx_l4_abe__mcasp_dma, | |
0a78c5c5 | 4799 | &omap44xx_l4_abe__mcbsp1, |
0a78c5c5 | 4800 | &omap44xx_l4_abe__mcbsp2, |
0a78c5c5 | 4801 | &omap44xx_l4_abe__mcbsp3, |
0a78c5c5 PW |
4802 | &omap44xx_l4_per__mcbsp4, |
4803 | &omap44xx_l4_abe__mcpdm, | |
0a78c5c5 PW |
4804 | &omap44xx_l4_per__mcspi1, |
4805 | &omap44xx_l4_per__mcspi2, | |
4806 | &omap44xx_l4_per__mcspi3, | |
4807 | &omap44xx_l4_per__mcspi4, | |
4808 | &omap44xx_l4_per__mmc1, | |
4809 | &omap44xx_l4_per__mmc2, | |
4810 | &omap44xx_l4_per__mmc3, | |
4811 | &omap44xx_l4_per__mmc4, | |
4812 | &omap44xx_l4_per__mmc5, | |
230844db ORL |
4813 | &omap44xx_l3_main_2__mmu_ipu, |
4814 | &omap44xx_l4_cfg__mmu_dsp, | |
e17f18c0 | 4815 | &omap44xx_l3_main_2__ocmc_ram, |
0c668875 | 4816 | &omap44xx_l4_cfg__ocp2scp_usb_phy, |
794b480a PW |
4817 | &omap44xx_mpu_private__prcm_mpu, |
4818 | &omap44xx_l4_wkup__cm_core_aon, | |
4819 | &omap44xx_l4_cfg__cm_core, | |
4820 | &omap44xx_l4_wkup__prm, | |
4821 | &omap44xx_l4_wkup__scrm, | |
b360124e | 4822 | /* &omap44xx_l3_main_2__sl2if, */ |
1e3b5e59 BC |
4823 | &omap44xx_l4_abe__slimbus1, |
4824 | &omap44xx_l4_abe__slimbus1_dma, | |
4825 | &omap44xx_l4_per__slimbus2, | |
0a78c5c5 PW |
4826 | &omap44xx_l4_cfg__smartreflex_core, |
4827 | &omap44xx_l4_cfg__smartreflex_iva, | |
4828 | &omap44xx_l4_cfg__smartreflex_mpu, | |
4829 | &omap44xx_l4_cfg__spinlock, | |
4830 | &omap44xx_l4_wkup__timer1, | |
4831 | &omap44xx_l4_per__timer2, | |
4832 | &omap44xx_l4_per__timer3, | |
4833 | &omap44xx_l4_per__timer4, | |
4834 | &omap44xx_l4_abe__timer5, | |
0a78c5c5 | 4835 | &omap44xx_l4_abe__timer6, |
0a78c5c5 | 4836 | &omap44xx_l4_abe__timer7, |
0a78c5c5 | 4837 | &omap44xx_l4_abe__timer8, |
0a78c5c5 PW |
4838 | &omap44xx_l4_per__timer9, |
4839 | &omap44xx_l4_per__timer10, | |
4840 | &omap44xx_l4_per__timer11, | |
4841 | &omap44xx_l4_per__uart1, | |
4842 | &omap44xx_l4_per__uart2, | |
4843 | &omap44xx_l4_per__uart3, | |
4844 | &omap44xx_l4_per__uart4, | |
b0a70cc8 | 4845 | /* &omap44xx_l4_cfg__usb_host_fs, */ |
0a78c5c5 PW |
4846 | &omap44xx_l4_cfg__usb_host_hs, |
4847 | &omap44xx_l4_cfg__usb_otg_hs, | |
4848 | &omap44xx_l4_cfg__usb_tll_hs, | |
4849 | &omap44xx_l4_wkup__wd_timer2, | |
4850 | &omap44xx_l4_abe__wd_timer3, | |
4851 | &omap44xx_l4_abe__wd_timer3_dma, | |
3b9b1015 S |
4852 | &omap44xx_mpu__emif1, |
4853 | &omap44xx_mpu__emif2, | |
55d2cb08 BC |
4854 | NULL, |
4855 | }; | |
4856 | ||
4857 | int __init omap44xx_hwmod_init(void) | |
4858 | { | |
9ebfd285 | 4859 | omap_hwmod_init(); |
0a78c5c5 | 4860 | return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); |
55d2cb08 BC |
4861 | } |
4862 |