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55d2cb08 BC |
1 | /* |
2 | * Hardware modules present on the OMAP44xx chips | |
3 | * | |
0a78c5c5 | 4 | * Copyright (C) 2009-2012 Texas Instruments, Inc. |
55d2cb08 BC |
5 | * Copyright (C) 2009-2010 Nokia Corporation |
6 | * | |
7 | * Paul Walmsley | |
8 | * Benoit Cousson | |
9 | * | |
10 | * This file is automatically generated from the OMAP hardware databases. | |
11 | * We respectfully ask that any modifications to this file be coordinated | |
12 | * with the public linux-omap@vger.kernel.org mailing list and the | |
13 | * authors above to ensure that the autogeneration scripts are kept | |
14 | * up-to-date with the file contents. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/io.h> | |
4b25408f | 22 | #include <linux/platform_data/gpio-omap.h> |
b86aeafc | 23 | #include <linux/power/smartreflex.h> |
637874dd | 24 | #include <linux/platform_data/omap_ocp2scp.h> |
3a8761c0 | 25 | #include <linux/i2c-omap.h> |
55d2cb08 | 26 | |
45c3eb7d | 27 | #include <linux/omap-dma.h> |
2a296c8f | 28 | |
0f9cb211 | 29 | #include <linux/platform_data/omap_ocp2scp.h> |
2203747c AB |
30 | #include <linux/platform_data/spi-omap2-mcspi.h> |
31 | #include <linux/platform_data/asoc-ti-mcbsp.h> | |
2ab7c848 | 32 | #include <linux/platform_data/iommu-omap.h> |
c345c8b0 | 33 | #include <plat/dmtimer.h> |
55d2cb08 | 34 | |
2a296c8f | 35 | #include "omap_hwmod.h" |
55d2cb08 | 36 | #include "omap_hwmod_common_data.h" |
d198b514 PW |
37 | #include "cm1_44xx.h" |
38 | #include "cm2_44xx.h" | |
39 | #include "prm44xx.h" | |
55d2cb08 | 40 | #include "prm-regbits-44xx.h" |
3a8761c0 | 41 | #include "i2c.h" |
68f39e74 | 42 | #include "mmc.h" |
ff2516fb | 43 | #include "wd_timer.h" |
55d2cb08 BC |
44 | |
45 | /* Base offset for all OMAP4 interrupts external to MPUSS */ | |
46 | #define OMAP44XX_IRQ_GIC_START 32 | |
47 | ||
48 | /* Base offset for all OMAP4 dma requests */ | |
844a3b63 | 49 | #define OMAP44XX_DMA_REQ_START 1 |
55d2cb08 BC |
50 | |
51 | /* | |
844a3b63 | 52 | * IP blocks |
55d2cb08 BC |
53 | */ |
54 | ||
42b9e387 PW |
55 | /* |
56 | * 'c2c_target_fw' class | |
57 | * instance(s): c2c_target_fw | |
58 | */ | |
59 | static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = { | |
60 | .name = "c2c_target_fw", | |
61 | }; | |
62 | ||
63 | /* c2c_target_fw */ | |
64 | static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = { | |
65 | .name = "c2c_target_fw", | |
66 | .class = &omap44xx_c2c_target_fw_hwmod_class, | |
67 | .clkdm_name = "d2d_clkdm", | |
68 | .prcm = { | |
69 | .omap4 = { | |
70 | .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET, | |
71 | .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET, | |
72 | }, | |
73 | }, | |
74 | }; | |
75 | ||
55d2cb08 BC |
76 | /* |
77 | * 'dmm' class | |
78 | * instance(s): dmm | |
79 | */ | |
80 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { | |
fe13471c | 81 | .name = "dmm", |
55d2cb08 BC |
82 | }; |
83 | ||
7e69ed97 BC |
84 | /* dmm */ |
85 | static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { | |
86 | { .irq = 113 + OMAP44XX_IRQ_GIC_START }, | |
87 | { .irq = -1 } | |
88 | }; | |
89 | ||
55d2cb08 BC |
90 | static struct omap_hwmod omap44xx_dmm_hwmod = { |
91 | .name = "dmm", | |
92 | .class = &omap44xx_dmm_hwmod_class, | |
a5322c6f | 93 | .clkdm_name = "l3_emif_clkdm", |
844a3b63 | 94 | .mpu_irqs = omap44xx_dmm_irqs, |
d0f0631d BC |
95 | .prcm = { |
96 | .omap4 = { | |
97 | .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, | |
27bb00b5 | 98 | .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, |
d0f0631d BC |
99 | }, |
100 | }, | |
55d2cb08 BC |
101 | }; |
102 | ||
103 | /* | |
104 | * 'emif_fw' class | |
105 | * instance(s): emif_fw | |
106 | */ | |
107 | static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { | |
fe13471c | 108 | .name = "emif_fw", |
55d2cb08 BC |
109 | }; |
110 | ||
7e69ed97 | 111 | /* emif_fw */ |
55d2cb08 BC |
112 | static struct omap_hwmod omap44xx_emif_fw_hwmod = { |
113 | .name = "emif_fw", | |
114 | .class = &omap44xx_emif_fw_hwmod_class, | |
a5322c6f | 115 | .clkdm_name = "l3_emif_clkdm", |
d0f0631d BC |
116 | .prcm = { |
117 | .omap4 = { | |
118 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET, | |
27bb00b5 | 119 | .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET, |
d0f0631d BC |
120 | }, |
121 | }, | |
55d2cb08 BC |
122 | }; |
123 | ||
124 | /* | |
125 | * 'l3' class | |
126 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 | |
127 | */ | |
128 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { | |
fe13471c | 129 | .name = "l3", |
55d2cb08 BC |
130 | }; |
131 | ||
7e69ed97 | 132 | /* l3_instr */ |
55d2cb08 BC |
133 | static struct omap_hwmod omap44xx_l3_instr_hwmod = { |
134 | .name = "l3_instr", | |
135 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 136 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
137 | .prcm = { |
138 | .omap4 = { | |
139 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, | |
27bb00b5 | 140 | .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, |
03fdefe5 | 141 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
142 | }, |
143 | }, | |
55d2cb08 BC |
144 | }; |
145 | ||
7e69ed97 | 146 | /* l3_main_1 */ |
9b4021be BC |
147 | static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = { |
148 | { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START }, | |
149 | { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START }, | |
150 | { .irq = -1 } | |
151 | }; | |
152 | ||
55d2cb08 BC |
153 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { |
154 | .name = "l3_main_1", | |
155 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 156 | .clkdm_name = "l3_1_clkdm", |
7e69ed97 | 157 | .mpu_irqs = omap44xx_l3_main_1_irqs, |
d0f0631d BC |
158 | .prcm = { |
159 | .omap4 = { | |
160 | .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, | |
27bb00b5 | 161 | .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, |
d0f0631d BC |
162 | }, |
163 | }, | |
55d2cb08 BC |
164 | }; |
165 | ||
7e69ed97 | 166 | /* l3_main_2 */ |
55d2cb08 BC |
167 | static struct omap_hwmod omap44xx_l3_main_2_hwmod = { |
168 | .name = "l3_main_2", | |
169 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 170 | .clkdm_name = "l3_2_clkdm", |
d0f0631d BC |
171 | .prcm = { |
172 | .omap4 = { | |
173 | .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET, | |
27bb00b5 | 174 | .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, |
d0f0631d BC |
175 | }, |
176 | }, | |
55d2cb08 BC |
177 | }; |
178 | ||
7e69ed97 | 179 | /* l3_main_3 */ |
55d2cb08 BC |
180 | static struct omap_hwmod omap44xx_l3_main_3_hwmod = { |
181 | .name = "l3_main_3", | |
182 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 183 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
184 | .prcm = { |
185 | .omap4 = { | |
186 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET, | |
27bb00b5 | 187 | .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET, |
03fdefe5 | 188 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
189 | }, |
190 | }, | |
55d2cb08 BC |
191 | }; |
192 | ||
193 | /* | |
194 | * 'l4' class | |
195 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup | |
196 | */ | |
197 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { | |
fe13471c | 198 | .name = "l4", |
55d2cb08 BC |
199 | }; |
200 | ||
7e69ed97 | 201 | /* l4_abe */ |
55d2cb08 BC |
202 | static struct omap_hwmod omap44xx_l4_abe_hwmod = { |
203 | .name = "l4_abe", | |
204 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 205 | .clkdm_name = "abe_clkdm", |
d0f0631d BC |
206 | .prcm = { |
207 | .omap4 = { | |
208 | .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, | |
ce80979a TK |
209 | .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, |
210 | .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK, | |
46b3af27 | 211 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, |
d0f0631d BC |
212 | }, |
213 | }, | |
55d2cb08 BC |
214 | }; |
215 | ||
7e69ed97 | 216 | /* l4_cfg */ |
55d2cb08 BC |
217 | static struct omap_hwmod omap44xx_l4_cfg_hwmod = { |
218 | .name = "l4_cfg", | |
219 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 220 | .clkdm_name = "l4_cfg_clkdm", |
d0f0631d BC |
221 | .prcm = { |
222 | .omap4 = { | |
223 | .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, | |
27bb00b5 | 224 | .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, |
d0f0631d BC |
225 | }, |
226 | }, | |
55d2cb08 BC |
227 | }; |
228 | ||
7e69ed97 | 229 | /* l4_per */ |
55d2cb08 BC |
230 | static struct omap_hwmod omap44xx_l4_per_hwmod = { |
231 | .name = "l4_per", | |
232 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 233 | .clkdm_name = "l4_per_clkdm", |
d0f0631d BC |
234 | .prcm = { |
235 | .omap4 = { | |
236 | .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET, | |
27bb00b5 | 237 | .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, |
d0f0631d BC |
238 | }, |
239 | }, | |
55d2cb08 BC |
240 | }; |
241 | ||
7e69ed97 | 242 | /* l4_wkup */ |
55d2cb08 BC |
243 | static struct omap_hwmod omap44xx_l4_wkup_hwmod = { |
244 | .name = "l4_wkup", | |
245 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 246 | .clkdm_name = "l4_wkup_clkdm", |
d0f0631d BC |
247 | .prcm = { |
248 | .omap4 = { | |
249 | .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, | |
27bb00b5 | 250 | .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, |
d0f0631d BC |
251 | }, |
252 | }, | |
55d2cb08 BC |
253 | }; |
254 | ||
f776471f | 255 | /* |
3b54baad BC |
256 | * 'mpu_bus' class |
257 | * instance(s): mpu_private | |
f776471f | 258 | */ |
3b54baad | 259 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { |
fe13471c | 260 | .name = "mpu_bus", |
3b54baad | 261 | }; |
f776471f | 262 | |
7e69ed97 | 263 | /* mpu_private */ |
3b54baad BC |
264 | static struct omap_hwmod omap44xx_mpu_private_hwmod = { |
265 | .name = "mpu_private", | |
266 | .class = &omap44xx_mpu_bus_hwmod_class, | |
a5322c6f | 267 | .clkdm_name = "mpuss_clkdm", |
46b3af27 TK |
268 | .prcm = { |
269 | .omap4 = { | |
270 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
271 | }, | |
272 | }, | |
3b54baad BC |
273 | }; |
274 | ||
9a817bc8 BC |
275 | /* |
276 | * 'ocp_wp_noc' class | |
277 | * instance(s): ocp_wp_noc | |
278 | */ | |
279 | static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = { | |
280 | .name = "ocp_wp_noc", | |
281 | }; | |
282 | ||
283 | /* ocp_wp_noc */ | |
284 | static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = { | |
285 | .name = "ocp_wp_noc", | |
286 | .class = &omap44xx_ocp_wp_noc_hwmod_class, | |
287 | .clkdm_name = "l3_instr_clkdm", | |
288 | .prcm = { | |
289 | .omap4 = { | |
290 | .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET, | |
291 | .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET, | |
292 | .modulemode = MODULEMODE_HWCTRL, | |
293 | }, | |
294 | }, | |
295 | }; | |
296 | ||
3b54baad BC |
297 | /* |
298 | * Modules omap_hwmod structures | |
299 | * | |
300 | * The following IPs are excluded for the moment because: | |
301 | * - They do not need an explicit SW control using omap_hwmod API. | |
302 | * - They still need to be validated with the driver | |
303 | * properly adapted to omap_hwmod / omap_device | |
304 | * | |
96566043 | 305 | * usim |
3b54baad BC |
306 | */ |
307 | ||
407a6888 BC |
308 | /* |
309 | * 'aess' class | |
310 | * audio engine sub system | |
311 | */ | |
312 | ||
313 | static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = { | |
314 | .rev_offs = 0x0000, | |
315 | .sysc_offs = 0x0010, | |
316 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
317 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
c614ebf6 BC |
318 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART | |
319 | MSTANDBY_SMART_WKUP), | |
407a6888 BC |
320 | .sysc_fields = &omap_hwmod_sysc_type2, |
321 | }; | |
322 | ||
323 | static struct omap_hwmod_class omap44xx_aess_hwmod_class = { | |
324 | .name = "aess", | |
325 | .sysc = &omap44xx_aess_sysc, | |
326 | }; | |
327 | ||
328 | /* aess */ | |
329 | static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { | |
330 | { .irq = 99 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 331 | { .irq = -1 } |
407a6888 BC |
332 | }; |
333 | ||
334 | static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { | |
335 | { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START }, | |
336 | { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START }, | |
337 | { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START }, | |
338 | { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START }, | |
339 | { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START }, | |
340 | { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START }, | |
341 | { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START }, | |
342 | { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 343 | { .dma_req = -1 } |
407a6888 BC |
344 | }; |
345 | ||
407a6888 BC |
346 | static struct omap_hwmod omap44xx_aess_hwmod = { |
347 | .name = "aess", | |
348 | .class = &omap44xx_aess_hwmod_class, | |
a5322c6f | 349 | .clkdm_name = "abe_clkdm", |
407a6888 | 350 | .mpu_irqs = omap44xx_aess_irqs, |
407a6888 | 351 | .sdma_reqs = omap44xx_aess_sdma_reqs, |
407a6888 | 352 | .main_clk = "aess_fck", |
00fe610b | 353 | .prcm = { |
407a6888 | 354 | .omap4 = { |
d0f0631d | 355 | .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, |
27bb00b5 | 356 | .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, |
ce80979a | 357 | .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK, |
03fdefe5 | 358 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
359 | }, |
360 | }, | |
407a6888 BC |
361 | }; |
362 | ||
42b9e387 PW |
363 | /* |
364 | * 'c2c' class | |
365 | * chip 2 chip interface used to plug the ape soc (omap) with an external modem | |
366 | * soc | |
367 | */ | |
368 | ||
369 | static struct omap_hwmod_class omap44xx_c2c_hwmod_class = { | |
370 | .name = "c2c", | |
371 | }; | |
372 | ||
373 | /* c2c */ | |
374 | static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = { | |
375 | { .irq = 88 + OMAP44XX_IRQ_GIC_START }, | |
376 | { .irq = -1 } | |
377 | }; | |
378 | ||
379 | static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = { | |
380 | { .dma_req = 68 + OMAP44XX_DMA_REQ_START }, | |
381 | { .dma_req = -1 } | |
382 | }; | |
383 | ||
384 | static struct omap_hwmod omap44xx_c2c_hwmod = { | |
385 | .name = "c2c", | |
386 | .class = &omap44xx_c2c_hwmod_class, | |
387 | .clkdm_name = "d2d_clkdm", | |
388 | .mpu_irqs = omap44xx_c2c_irqs, | |
389 | .sdma_reqs = omap44xx_c2c_sdma_reqs, | |
390 | .prcm = { | |
391 | .omap4 = { | |
392 | .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET, | |
393 | .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET, | |
394 | }, | |
395 | }, | |
396 | }; | |
397 | ||
407a6888 BC |
398 | /* |
399 | * 'counter' class | |
400 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock | |
401 | */ | |
402 | ||
403 | static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = { | |
404 | .rev_offs = 0x0000, | |
405 | .sysc_offs = 0x0004, | |
406 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
252a4c54 | 407 | .idlemodes = (SIDLE_FORCE | SIDLE_NO), |
407a6888 BC |
408 | .sysc_fields = &omap_hwmod_sysc_type1, |
409 | }; | |
410 | ||
411 | static struct omap_hwmod_class omap44xx_counter_hwmod_class = { | |
412 | .name = "counter", | |
413 | .sysc = &omap44xx_counter_sysc, | |
414 | }; | |
415 | ||
416 | /* counter_32k */ | |
407a6888 BC |
417 | static struct omap_hwmod omap44xx_counter_32k_hwmod = { |
418 | .name = "counter_32k", | |
419 | .class = &omap44xx_counter_hwmod_class, | |
a5322c6f | 420 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 BC |
421 | .flags = HWMOD_SWSUP_SIDLE, |
422 | .main_clk = "sys_32k_ck", | |
00fe610b | 423 | .prcm = { |
407a6888 | 424 | .omap4 = { |
d0f0631d | 425 | .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, |
27bb00b5 | 426 | .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, |
407a6888 BC |
427 | }, |
428 | }, | |
407a6888 BC |
429 | }; |
430 | ||
a0b5d813 PW |
431 | /* |
432 | * 'ctrl_module' class | |
433 | * attila core control module + core pad control module + wkup pad control | |
434 | * module + attila wkup control module | |
435 | */ | |
436 | ||
437 | static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = { | |
438 | .rev_offs = 0x0000, | |
439 | .sysc_offs = 0x0010, | |
440 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
441 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
442 | SIDLE_SMART_WKUP), | |
443 | .sysc_fields = &omap_hwmod_sysc_type2, | |
444 | }; | |
445 | ||
446 | static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = { | |
447 | .name = "ctrl_module", | |
448 | .sysc = &omap44xx_ctrl_module_sysc, | |
449 | }; | |
450 | ||
451 | /* ctrl_module_core */ | |
452 | static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = { | |
453 | { .irq = 8 + OMAP44XX_IRQ_GIC_START }, | |
454 | { .irq = -1 } | |
455 | }; | |
456 | ||
457 | static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = { | |
458 | .name = "ctrl_module_core", | |
459 | .class = &omap44xx_ctrl_module_hwmod_class, | |
460 | .clkdm_name = "l4_cfg_clkdm", | |
461 | .mpu_irqs = omap44xx_ctrl_module_core_irqs, | |
46b3af27 TK |
462 | .prcm = { |
463 | .omap4 = { | |
464 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
465 | }, | |
466 | }, | |
a0b5d813 PW |
467 | }; |
468 | ||
469 | /* ctrl_module_pad_core */ | |
470 | static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = { | |
471 | .name = "ctrl_module_pad_core", | |
472 | .class = &omap44xx_ctrl_module_hwmod_class, | |
473 | .clkdm_name = "l4_cfg_clkdm", | |
46b3af27 TK |
474 | .prcm = { |
475 | .omap4 = { | |
476 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
477 | }, | |
478 | }, | |
a0b5d813 PW |
479 | }; |
480 | ||
481 | /* ctrl_module_wkup */ | |
482 | static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = { | |
483 | .name = "ctrl_module_wkup", | |
484 | .class = &omap44xx_ctrl_module_hwmod_class, | |
485 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
486 | .prcm = { |
487 | .omap4 = { | |
488 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
489 | }, | |
490 | }, | |
a0b5d813 PW |
491 | }; |
492 | ||
493 | /* ctrl_module_pad_wkup */ | |
494 | static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = { | |
495 | .name = "ctrl_module_pad_wkup", | |
496 | .class = &omap44xx_ctrl_module_hwmod_class, | |
497 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
498 | .prcm = { |
499 | .omap4 = { | |
500 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
501 | }, | |
502 | }, | |
a0b5d813 PW |
503 | }; |
504 | ||
96566043 BC |
505 | /* |
506 | * 'debugss' class | |
507 | * debug and emulation sub system | |
508 | */ | |
509 | ||
510 | static struct omap_hwmod_class omap44xx_debugss_hwmod_class = { | |
511 | .name = "debugss", | |
512 | }; | |
513 | ||
514 | /* debugss */ | |
515 | static struct omap_hwmod omap44xx_debugss_hwmod = { | |
516 | .name = "debugss", | |
517 | .class = &omap44xx_debugss_hwmod_class, | |
518 | .clkdm_name = "emu_sys_clkdm", | |
519 | .main_clk = "trace_clk_div_ck", | |
520 | .prcm = { | |
521 | .omap4 = { | |
522 | .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET, | |
523 | .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET, | |
524 | }, | |
525 | }, | |
526 | }; | |
527 | ||
d7cf5f33 BC |
528 | /* |
529 | * 'dma' class | |
530 | * dma controller for data exchange between memory to memory (i.e. internal or | |
531 | * external memory) and gp peripherals to memory or memory to gp peripherals | |
532 | */ | |
533 | ||
534 | static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { | |
535 | .rev_offs = 0x0000, | |
536 | .sysc_offs = 0x002c, | |
537 | .syss_offs = 0x0028, | |
538 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
539 | SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
540 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
541 | SYSS_HAS_RESET_STATUS), | |
542 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
543 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
544 | .sysc_fields = &omap_hwmod_sysc_type1, | |
545 | }; | |
546 | ||
547 | static struct omap_hwmod_class omap44xx_dma_hwmod_class = { | |
548 | .name = "dma", | |
549 | .sysc = &omap44xx_dma_sysc, | |
550 | }; | |
551 | ||
552 | /* dma dev_attr */ | |
553 | static struct omap_dma_dev_attr dma_dev_attr = { | |
554 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
555 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
556 | .lch_count = 32, | |
557 | }; | |
558 | ||
559 | /* dma_system */ | |
560 | static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { | |
561 | { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, | |
562 | { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, | |
563 | { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, | |
564 | { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 565 | { .irq = -1 } |
d7cf5f33 BC |
566 | }; |
567 | ||
d7cf5f33 BC |
568 | static struct omap_hwmod omap44xx_dma_system_hwmod = { |
569 | .name = "dma_system", | |
570 | .class = &omap44xx_dma_hwmod_class, | |
a5322c6f | 571 | .clkdm_name = "l3_dma_clkdm", |
d7cf5f33 | 572 | .mpu_irqs = omap44xx_dma_system_irqs, |
d7cf5f33 BC |
573 | .main_clk = "l3_div_ck", |
574 | .prcm = { | |
575 | .omap4 = { | |
d0f0631d | 576 | .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET, |
27bb00b5 | 577 | .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET, |
d7cf5f33 BC |
578 | }, |
579 | }, | |
580 | .dev_attr = &dma_dev_attr, | |
d7cf5f33 BC |
581 | }; |
582 | ||
8ca476da BC |
583 | /* |
584 | * 'dmic' class | |
585 | * digital microphone controller | |
586 | */ | |
587 | ||
588 | static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = { | |
589 | .rev_offs = 0x0000, | |
590 | .sysc_offs = 0x0010, | |
591 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
592 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
593 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
594 | SIDLE_SMART_WKUP), | |
595 | .sysc_fields = &omap_hwmod_sysc_type2, | |
596 | }; | |
597 | ||
598 | static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { | |
599 | .name = "dmic", | |
600 | .sysc = &omap44xx_dmic_sysc, | |
601 | }; | |
602 | ||
603 | /* dmic */ | |
8ca476da BC |
604 | static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { |
605 | { .irq = 114 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 606 | { .irq = -1 } |
8ca476da BC |
607 | }; |
608 | ||
609 | static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { | |
610 | { .dma_req = 66 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 611 | { .dma_req = -1 } |
8ca476da BC |
612 | }; |
613 | ||
8ca476da BC |
614 | static struct omap_hwmod omap44xx_dmic_hwmod = { |
615 | .name = "dmic", | |
616 | .class = &omap44xx_dmic_hwmod_class, | |
a5322c6f | 617 | .clkdm_name = "abe_clkdm", |
8ca476da | 618 | .mpu_irqs = omap44xx_dmic_irqs, |
8ca476da | 619 | .sdma_reqs = omap44xx_dmic_sdma_reqs, |
8ca476da | 620 | .main_clk = "dmic_fck", |
00fe610b | 621 | .prcm = { |
8ca476da | 622 | .omap4 = { |
d0f0631d | 623 | .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, |
27bb00b5 | 624 | .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET, |
03fdefe5 | 625 | .modulemode = MODULEMODE_SWCTRL, |
8ca476da BC |
626 | }, |
627 | }, | |
8ca476da BC |
628 | }; |
629 | ||
8f25bdc5 BC |
630 | /* |
631 | * 'dsp' class | |
632 | * dsp sub-system | |
633 | */ | |
634 | ||
635 | static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { | |
fe13471c | 636 | .name = "dsp", |
8f25bdc5 BC |
637 | }; |
638 | ||
639 | /* dsp */ | |
640 | static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { | |
641 | { .irq = 28 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 642 | { .irq = -1 } |
8f25bdc5 BC |
643 | }; |
644 | ||
645 | static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { | |
8f25bdc5 BC |
646 | { .name = "dsp", .rst_shift = 0 }, |
647 | }; | |
648 | ||
8f25bdc5 BC |
649 | static struct omap_hwmod omap44xx_dsp_hwmod = { |
650 | .name = "dsp", | |
651 | .class = &omap44xx_dsp_hwmod_class, | |
a5322c6f | 652 | .clkdm_name = "tesla_clkdm", |
8f25bdc5 | 653 | .mpu_irqs = omap44xx_dsp_irqs, |
8f25bdc5 BC |
654 | .rst_lines = omap44xx_dsp_resets, |
655 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), | |
298ea44f | 656 | .main_clk = "dpll_iva_m4x2_ck", |
8f25bdc5 BC |
657 | .prcm = { |
658 | .omap4 = { | |
d0f0631d | 659 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, |
eaac329d | 660 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, |
27bb00b5 | 661 | .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, |
03fdefe5 | 662 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
663 | }, |
664 | }, | |
8f25bdc5 BC |
665 | }; |
666 | ||
d63bd74f BC |
667 | /* |
668 | * 'dss' class | |
669 | * display sub-system | |
670 | */ | |
671 | ||
672 | static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = { | |
673 | .rev_offs = 0x0000, | |
674 | .syss_offs = 0x0014, | |
675 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
676 | }; | |
677 | ||
678 | static struct omap_hwmod_class omap44xx_dss_hwmod_class = { | |
679 | .name = "dss", | |
680 | .sysc = &omap44xx_dss_sysc, | |
13662dc5 | 681 | .reset = omap_dss_reset, |
d63bd74f BC |
682 | }; |
683 | ||
684 | /* dss */ | |
d63bd74f BC |
685 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { |
686 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
687 | { .role = "tv_clk", .clk = "dss_tv_clk" }, | |
4d0698d9 | 688 | { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, |
d63bd74f BC |
689 | }; |
690 | ||
691 | static struct omap_hwmod omap44xx_dss_hwmod = { | |
692 | .name = "dss_core", | |
37ad0855 | 693 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
d63bd74f | 694 | .class = &omap44xx_dss_hwmod_class, |
a5322c6f | 695 | .clkdm_name = "l3_dss_clkdm", |
da7cdfac | 696 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
697 | .prcm = { |
698 | .omap4 = { | |
d0f0631d | 699 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 700 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
701 | }, |
702 | }, | |
703 | .opt_clks = dss_opt_clks, | |
704 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
d63bd74f BC |
705 | }; |
706 | ||
707 | /* | |
708 | * 'dispc' class | |
709 | * display controller | |
710 | */ | |
711 | ||
712 | static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = { | |
713 | .rev_offs = 0x0000, | |
714 | .sysc_offs = 0x0010, | |
715 | .syss_offs = 0x0014, | |
716 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
717 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | | |
718 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
719 | SYSS_HAS_RESET_STATUS), | |
720 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
721 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
722 | .sysc_fields = &omap_hwmod_sysc_type1, | |
723 | }; | |
724 | ||
725 | static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { | |
726 | .name = "dispc", | |
727 | .sysc = &omap44xx_dispc_sysc, | |
728 | }; | |
729 | ||
730 | /* dss_dispc */ | |
d63bd74f BC |
731 | static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { |
732 | { .irq = 25 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 733 | { .irq = -1 } |
d63bd74f BC |
734 | }; |
735 | ||
736 | static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { | |
737 | { .dma_req = 5 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 738 | { .dma_req = -1 } |
d63bd74f BC |
739 | }; |
740 | ||
b923d40d AT |
741 | static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { |
742 | .manager_count = 3, | |
743 | .has_framedonetv_irq = 1 | |
744 | }; | |
745 | ||
d63bd74f BC |
746 | static struct omap_hwmod omap44xx_dss_dispc_hwmod = { |
747 | .name = "dss_dispc", | |
748 | .class = &omap44xx_dispc_hwmod_class, | |
a5322c6f | 749 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 750 | .mpu_irqs = omap44xx_dss_dispc_irqs, |
d63bd74f | 751 | .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, |
da7cdfac | 752 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
753 | .prcm = { |
754 | .omap4 = { | |
d0f0631d | 755 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 756 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
757 | }, |
758 | }, | |
b923d40d | 759 | .dev_attr = &omap44xx_dss_dispc_dev_attr |
d63bd74f BC |
760 | }; |
761 | ||
762 | /* | |
763 | * 'dsi' class | |
764 | * display serial interface controller | |
765 | */ | |
766 | ||
767 | static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = { | |
768 | .rev_offs = 0x0000, | |
769 | .sysc_offs = 0x0010, | |
770 | .syss_offs = 0x0014, | |
771 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
772 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
773 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
774 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
775 | .sysc_fields = &omap_hwmod_sysc_type1, | |
776 | }; | |
777 | ||
778 | static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { | |
779 | .name = "dsi", | |
780 | .sysc = &omap44xx_dsi_sysc, | |
781 | }; | |
782 | ||
783 | /* dss_dsi1 */ | |
d63bd74f BC |
784 | static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { |
785 | { .irq = 53 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 786 | { .irq = -1 } |
d63bd74f BC |
787 | }; |
788 | ||
789 | static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { | |
790 | { .dma_req = 74 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 791 | { .dma_req = -1 } |
d63bd74f BC |
792 | }; |
793 | ||
3a23aafc TV |
794 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { |
795 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
796 | }; | |
797 | ||
d63bd74f BC |
798 | static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { |
799 | .name = "dss_dsi1", | |
800 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 801 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 802 | .mpu_irqs = omap44xx_dss_dsi1_irqs, |
d63bd74f | 803 | .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, |
da7cdfac | 804 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
805 | .prcm = { |
806 | .omap4 = { | |
d0f0631d | 807 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 808 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
809 | }, |
810 | }, | |
3a23aafc TV |
811 | .opt_clks = dss_dsi1_opt_clks, |
812 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
d63bd74f BC |
813 | }; |
814 | ||
815 | /* dss_dsi2 */ | |
d63bd74f BC |
816 | static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { |
817 | { .irq = 84 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 818 | { .irq = -1 } |
d63bd74f BC |
819 | }; |
820 | ||
821 | static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { | |
822 | { .dma_req = 83 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 823 | { .dma_req = -1 } |
d63bd74f BC |
824 | }; |
825 | ||
3a23aafc TV |
826 | static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { |
827 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
828 | }; | |
829 | ||
d63bd74f BC |
830 | static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { |
831 | .name = "dss_dsi2", | |
832 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 833 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 834 | .mpu_irqs = omap44xx_dss_dsi2_irqs, |
d63bd74f | 835 | .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, |
da7cdfac | 836 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
837 | .prcm = { |
838 | .omap4 = { | |
d0f0631d | 839 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 840 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
841 | }, |
842 | }, | |
3a23aafc TV |
843 | .opt_clks = dss_dsi2_opt_clks, |
844 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), | |
d63bd74f BC |
845 | }; |
846 | ||
847 | /* | |
848 | * 'hdmi' class | |
849 | * hdmi controller | |
850 | */ | |
851 | ||
852 | static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = { | |
853 | .rev_offs = 0x0000, | |
854 | .sysc_offs = 0x0010, | |
855 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
856 | SYSC_HAS_SOFTRESET), | |
857 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
858 | SIDLE_SMART_WKUP), | |
859 | .sysc_fields = &omap_hwmod_sysc_type2, | |
860 | }; | |
861 | ||
862 | static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { | |
863 | .name = "hdmi", | |
864 | .sysc = &omap44xx_hdmi_sysc, | |
865 | }; | |
866 | ||
867 | /* dss_hdmi */ | |
d63bd74f BC |
868 | static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { |
869 | { .irq = 101 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 870 | { .irq = -1 } |
d63bd74f BC |
871 | }; |
872 | ||
873 | static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { | |
874 | { .dma_req = 75 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 875 | { .dma_req = -1 } |
d63bd74f BC |
876 | }; |
877 | ||
3a23aafc TV |
878 | static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { |
879 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
880 | }; | |
881 | ||
d63bd74f BC |
882 | static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { |
883 | .name = "dss_hdmi", | |
884 | .class = &omap44xx_hdmi_hwmod_class, | |
a5322c6f | 885 | .clkdm_name = "l3_dss_clkdm", |
dc57aef5 RN |
886 | /* |
887 | * HDMI audio requires to use no-idle mode. Hence, | |
888 | * set idle mode by software. | |
889 | */ | |
890 | .flags = HWMOD_SWSUP_SIDLE, | |
d63bd74f | 891 | .mpu_irqs = omap44xx_dss_hdmi_irqs, |
d63bd74f | 892 | .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, |
4d0698d9 | 893 | .main_clk = "dss_48mhz_clk", |
d63bd74f BC |
894 | .prcm = { |
895 | .omap4 = { | |
d0f0631d | 896 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 897 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
898 | }, |
899 | }, | |
3a23aafc TV |
900 | .opt_clks = dss_hdmi_opt_clks, |
901 | .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), | |
d63bd74f BC |
902 | }; |
903 | ||
904 | /* | |
905 | * 'rfbi' class | |
906 | * remote frame buffer interface | |
907 | */ | |
908 | ||
909 | static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = { | |
910 | .rev_offs = 0x0000, | |
911 | .sysc_offs = 0x0010, | |
912 | .syss_offs = 0x0014, | |
913 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
914 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
915 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
916 | .sysc_fields = &omap_hwmod_sysc_type1, | |
917 | }; | |
918 | ||
919 | static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { | |
920 | .name = "rfbi", | |
921 | .sysc = &omap44xx_rfbi_sysc, | |
922 | }; | |
923 | ||
924 | /* dss_rfbi */ | |
d63bd74f BC |
925 | static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { |
926 | { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 927 | { .dma_req = -1 } |
d63bd74f BC |
928 | }; |
929 | ||
3a23aafc TV |
930 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
931 | { .role = "ick", .clk = "dss_fck" }, | |
932 | }; | |
933 | ||
d63bd74f BC |
934 | static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { |
935 | .name = "dss_rfbi", | |
936 | .class = &omap44xx_rfbi_hwmod_class, | |
a5322c6f | 937 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 938 | .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, |
da7cdfac | 939 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
940 | .prcm = { |
941 | .omap4 = { | |
d0f0631d | 942 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 943 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
944 | }, |
945 | }, | |
3a23aafc TV |
946 | .opt_clks = dss_rfbi_opt_clks, |
947 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
d63bd74f BC |
948 | }; |
949 | ||
950 | /* | |
951 | * 'venc' class | |
952 | * video encoder | |
953 | */ | |
954 | ||
955 | static struct omap_hwmod_class omap44xx_venc_hwmod_class = { | |
956 | .name = "venc", | |
957 | }; | |
958 | ||
959 | /* dss_venc */ | |
d63bd74f BC |
960 | static struct omap_hwmod omap44xx_dss_venc_hwmod = { |
961 | .name = "dss_venc", | |
962 | .class = &omap44xx_venc_hwmod_class, | |
a5322c6f | 963 | .clkdm_name = "l3_dss_clkdm", |
4d0698d9 | 964 | .main_clk = "dss_tv_clk", |
d63bd74f BC |
965 | .prcm = { |
966 | .omap4 = { | |
d0f0631d | 967 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 968 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
969 | }, |
970 | }, | |
d63bd74f BC |
971 | }; |
972 | ||
42b9e387 PW |
973 | /* |
974 | * 'elm' class | |
975 | * bch error location module | |
976 | */ | |
977 | ||
978 | static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = { | |
979 | .rev_offs = 0x0000, | |
980 | .sysc_offs = 0x0010, | |
981 | .syss_offs = 0x0014, | |
982 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
983 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
984 | SYSS_HAS_RESET_STATUS), | |
985 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
986 | .sysc_fields = &omap_hwmod_sysc_type1, | |
987 | }; | |
988 | ||
989 | static struct omap_hwmod_class omap44xx_elm_hwmod_class = { | |
990 | .name = "elm", | |
991 | .sysc = &omap44xx_elm_sysc, | |
992 | }; | |
993 | ||
994 | /* elm */ | |
995 | static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = { | |
996 | { .irq = 4 + OMAP44XX_IRQ_GIC_START }, | |
997 | { .irq = -1 } | |
998 | }; | |
999 | ||
1000 | static struct omap_hwmod omap44xx_elm_hwmod = { | |
1001 | .name = "elm", | |
1002 | .class = &omap44xx_elm_hwmod_class, | |
1003 | .clkdm_name = "l4_per_clkdm", | |
1004 | .mpu_irqs = omap44xx_elm_irqs, | |
1005 | .prcm = { | |
1006 | .omap4 = { | |
1007 | .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET, | |
1008 | .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET, | |
1009 | }, | |
1010 | }, | |
1011 | }; | |
1012 | ||
bf30f950 PW |
1013 | /* |
1014 | * 'emif' class | |
1015 | * external memory interface no1 | |
1016 | */ | |
1017 | ||
1018 | static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = { | |
1019 | .rev_offs = 0x0000, | |
1020 | }; | |
1021 | ||
1022 | static struct omap_hwmod_class omap44xx_emif_hwmod_class = { | |
1023 | .name = "emif", | |
1024 | .sysc = &omap44xx_emif_sysc, | |
1025 | }; | |
1026 | ||
1027 | /* emif1 */ | |
1028 | static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = { | |
1029 | { .irq = 110 + OMAP44XX_IRQ_GIC_START }, | |
1030 | { .irq = -1 } | |
1031 | }; | |
1032 | ||
1033 | static struct omap_hwmod omap44xx_emif1_hwmod = { | |
1034 | .name = "emif1", | |
1035 | .class = &omap44xx_emif_hwmod_class, | |
1036 | .clkdm_name = "l3_emif_clkdm", | |
1037 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | |
1038 | .mpu_irqs = omap44xx_emif1_irqs, | |
1039 | .main_clk = "ddrphy_ck", | |
1040 | .prcm = { | |
1041 | .omap4 = { | |
1042 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET, | |
1043 | .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET, | |
1044 | .modulemode = MODULEMODE_HWCTRL, | |
1045 | }, | |
1046 | }, | |
1047 | }; | |
1048 | ||
1049 | /* emif2 */ | |
1050 | static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = { | |
1051 | { .irq = 111 + OMAP44XX_IRQ_GIC_START }, | |
1052 | { .irq = -1 } | |
1053 | }; | |
1054 | ||
1055 | static struct omap_hwmod omap44xx_emif2_hwmod = { | |
1056 | .name = "emif2", | |
1057 | .class = &omap44xx_emif_hwmod_class, | |
1058 | .clkdm_name = "l3_emif_clkdm", | |
1059 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | |
1060 | .mpu_irqs = omap44xx_emif2_irqs, | |
1061 | .main_clk = "ddrphy_ck", | |
1062 | .prcm = { | |
1063 | .omap4 = { | |
1064 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET, | |
1065 | .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET, | |
1066 | .modulemode = MODULEMODE_HWCTRL, | |
1067 | }, | |
1068 | }, | |
1069 | }; | |
1070 | ||
b050f688 ML |
1071 | /* |
1072 | * 'fdif' class | |
1073 | * face detection hw accelerator module | |
1074 | */ | |
1075 | ||
1076 | static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = { | |
1077 | .rev_offs = 0x0000, | |
1078 | .sysc_offs = 0x0010, | |
1079 | /* | |
1080 | * FDIF needs 100 OCP clk cycles delay after a softreset before | |
1081 | * accessing sysconfig again. | |
1082 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
1083 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
1084 | * | |
1085 | * TODO: Indicate errata when available. | |
1086 | */ | |
1087 | .srst_udelay = 2, | |
1088 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | | |
1089 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1090 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1091 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1092 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1093 | }; | |
1094 | ||
1095 | static struct omap_hwmod_class omap44xx_fdif_hwmod_class = { | |
1096 | .name = "fdif", | |
1097 | .sysc = &omap44xx_fdif_sysc, | |
1098 | }; | |
1099 | ||
1100 | /* fdif */ | |
1101 | static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = { | |
1102 | { .irq = 69 + OMAP44XX_IRQ_GIC_START }, | |
1103 | { .irq = -1 } | |
1104 | }; | |
1105 | ||
1106 | static struct omap_hwmod omap44xx_fdif_hwmod = { | |
1107 | .name = "fdif", | |
1108 | .class = &omap44xx_fdif_hwmod_class, | |
1109 | .clkdm_name = "iss_clkdm", | |
1110 | .mpu_irqs = omap44xx_fdif_irqs, | |
1111 | .main_clk = "fdif_fck", | |
1112 | .prcm = { | |
1113 | .omap4 = { | |
1114 | .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET, | |
1115 | .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET, | |
1116 | .modulemode = MODULEMODE_SWCTRL, | |
1117 | }, | |
1118 | }, | |
1119 | }; | |
1120 | ||
3b54baad BC |
1121 | /* |
1122 | * 'gpio' class | |
1123 | * general purpose io module | |
1124 | */ | |
1125 | ||
1126 | static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { | |
1127 | .rev_offs = 0x0000, | |
f776471f | 1128 | .sysc_offs = 0x0010, |
3b54baad | 1129 | .syss_offs = 0x0114, |
0cfe8751 BC |
1130 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
1131 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1132 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
1133 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1134 | SIDLE_SMART_WKUP), | |
f776471f BC |
1135 | .sysc_fields = &omap_hwmod_sysc_type1, |
1136 | }; | |
1137 | ||
3b54baad | 1138 | static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { |
fe13471c BC |
1139 | .name = "gpio", |
1140 | .sysc = &omap44xx_gpio_sysc, | |
1141 | .rev = 2, | |
f776471f BC |
1142 | }; |
1143 | ||
3b54baad BC |
1144 | /* gpio dev_attr */ |
1145 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
fe13471c BC |
1146 | .bank_width = 32, |
1147 | .dbck_flag = true, | |
f776471f BC |
1148 | }; |
1149 | ||
3b54baad | 1150 | /* gpio1 */ |
3b54baad BC |
1151 | static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { |
1152 | { .irq = 29 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1153 | { .irq = -1 } |
f776471f BC |
1154 | }; |
1155 | ||
3b54baad | 1156 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
b399bca8 | 1157 | { .role = "dbclk", .clk = "gpio1_dbclk" }, |
3b54baad BC |
1158 | }; |
1159 | ||
1160 | static struct omap_hwmod omap44xx_gpio1_hwmod = { | |
1161 | .name = "gpio1", | |
1162 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1163 | .clkdm_name = "l4_wkup_clkdm", |
3b54baad | 1164 | .mpu_irqs = omap44xx_gpio1_irqs, |
3b54baad | 1165 | .main_clk = "gpio1_ick", |
f776471f BC |
1166 | .prcm = { |
1167 | .omap4 = { | |
d0f0631d | 1168 | .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, |
27bb00b5 | 1169 | .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET, |
03fdefe5 | 1170 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1171 | }, |
1172 | }, | |
3b54baad BC |
1173 | .opt_clks = gpio1_opt_clks, |
1174 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
1175 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1176 | }; |
1177 | ||
3b54baad | 1178 | /* gpio2 */ |
3b54baad BC |
1179 | static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { |
1180 | { .irq = 30 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1181 | { .irq = -1 } |
f776471f BC |
1182 | }; |
1183 | ||
3b54baad | 1184 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
b399bca8 | 1185 | { .role = "dbclk", .clk = "gpio2_dbclk" }, |
3b54baad BC |
1186 | }; |
1187 | ||
1188 | static struct omap_hwmod omap44xx_gpio2_hwmod = { | |
1189 | .name = "gpio2", | |
1190 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1191 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1192 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1193 | .mpu_irqs = omap44xx_gpio2_irqs, |
3b54baad | 1194 | .main_clk = "gpio2_ick", |
f776471f BC |
1195 | .prcm = { |
1196 | .omap4 = { | |
d0f0631d | 1197 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET, |
27bb00b5 | 1198 | .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET, |
03fdefe5 | 1199 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1200 | }, |
1201 | }, | |
3b54baad BC |
1202 | .opt_clks = gpio2_opt_clks, |
1203 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
1204 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1205 | }; |
1206 | ||
3b54baad | 1207 | /* gpio3 */ |
3b54baad BC |
1208 | static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { |
1209 | { .irq = 31 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1210 | { .irq = -1 } |
f776471f BC |
1211 | }; |
1212 | ||
3b54baad | 1213 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
b399bca8 | 1214 | { .role = "dbclk", .clk = "gpio3_dbclk" }, |
3b54baad BC |
1215 | }; |
1216 | ||
1217 | static struct omap_hwmod omap44xx_gpio3_hwmod = { | |
1218 | .name = "gpio3", | |
1219 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1220 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1221 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1222 | .mpu_irqs = omap44xx_gpio3_irqs, |
3b54baad | 1223 | .main_clk = "gpio3_ick", |
f776471f BC |
1224 | .prcm = { |
1225 | .omap4 = { | |
d0f0631d | 1226 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET, |
27bb00b5 | 1227 | .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET, |
03fdefe5 | 1228 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1229 | }, |
1230 | }, | |
3b54baad BC |
1231 | .opt_clks = gpio3_opt_clks, |
1232 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
1233 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1234 | }; |
1235 | ||
3b54baad | 1236 | /* gpio4 */ |
3b54baad BC |
1237 | static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { |
1238 | { .irq = 32 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1239 | { .irq = -1 } |
f776471f BC |
1240 | }; |
1241 | ||
3b54baad | 1242 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { |
b399bca8 | 1243 | { .role = "dbclk", .clk = "gpio4_dbclk" }, |
3b54baad BC |
1244 | }; |
1245 | ||
1246 | static struct omap_hwmod omap44xx_gpio4_hwmod = { | |
1247 | .name = "gpio4", | |
1248 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1249 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1250 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1251 | .mpu_irqs = omap44xx_gpio4_irqs, |
3b54baad | 1252 | .main_clk = "gpio4_ick", |
f776471f BC |
1253 | .prcm = { |
1254 | .omap4 = { | |
d0f0631d | 1255 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET, |
27bb00b5 | 1256 | .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET, |
03fdefe5 | 1257 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1258 | }, |
1259 | }, | |
3b54baad BC |
1260 | .opt_clks = gpio4_opt_clks, |
1261 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
1262 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1263 | }; |
1264 | ||
3b54baad | 1265 | /* gpio5 */ |
3b54baad BC |
1266 | static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { |
1267 | { .irq = 33 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1268 | { .irq = -1 } |
55d2cb08 BC |
1269 | }; |
1270 | ||
844a3b63 PW |
1271 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
1272 | { .role = "dbclk", .clk = "gpio5_dbclk" }, | |
55d2cb08 BC |
1273 | }; |
1274 | ||
3b54baad BC |
1275 | static struct omap_hwmod omap44xx_gpio5_hwmod = { |
1276 | .name = "gpio5", | |
1277 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1278 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1279 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1280 | .mpu_irqs = omap44xx_gpio5_irqs, |
3b54baad | 1281 | .main_clk = "gpio5_ick", |
55d2cb08 BC |
1282 | .prcm = { |
1283 | .omap4 = { | |
d0f0631d | 1284 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET, |
27bb00b5 | 1285 | .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET, |
03fdefe5 | 1286 | .modulemode = MODULEMODE_HWCTRL, |
55d2cb08 BC |
1287 | }, |
1288 | }, | |
3b54baad BC |
1289 | .opt_clks = gpio5_opt_clks, |
1290 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
1291 | .dev_attr = &gpio_dev_attr, | |
55d2cb08 BC |
1292 | }; |
1293 | ||
3b54baad | 1294 | /* gpio6 */ |
3b54baad BC |
1295 | static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { |
1296 | { .irq = 34 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1297 | { .irq = -1 } |
92b18d1c BC |
1298 | }; |
1299 | ||
3b54baad | 1300 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
b399bca8 | 1301 | { .role = "dbclk", .clk = "gpio6_dbclk" }, |
db12ba53 BC |
1302 | }; |
1303 | ||
3b54baad BC |
1304 | static struct omap_hwmod omap44xx_gpio6_hwmod = { |
1305 | .name = "gpio6", | |
1306 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1307 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1308 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1309 | .mpu_irqs = omap44xx_gpio6_irqs, |
3b54baad BC |
1310 | .main_clk = "gpio6_ick", |
1311 | .prcm = { | |
1312 | .omap4 = { | |
d0f0631d | 1313 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET, |
27bb00b5 | 1314 | .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET, |
03fdefe5 | 1315 | .modulemode = MODULEMODE_HWCTRL, |
3b54baad | 1316 | }, |
db12ba53 | 1317 | }, |
3b54baad BC |
1318 | .opt_clks = gpio6_opt_clks, |
1319 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
1320 | .dev_attr = &gpio_dev_attr, | |
db12ba53 BC |
1321 | }; |
1322 | ||
eb42b5d3 BC |
1323 | /* |
1324 | * 'gpmc' class | |
1325 | * general purpose memory controller | |
1326 | */ | |
1327 | ||
1328 | static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = { | |
1329 | .rev_offs = 0x0000, | |
1330 | .sysc_offs = 0x0010, | |
1331 | .syss_offs = 0x0014, | |
1332 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
1333 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1334 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1335 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1336 | }; | |
1337 | ||
1338 | static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = { | |
1339 | .name = "gpmc", | |
1340 | .sysc = &omap44xx_gpmc_sysc, | |
1341 | }; | |
1342 | ||
1343 | /* gpmc */ | |
1344 | static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = { | |
1345 | { .irq = 20 + OMAP44XX_IRQ_GIC_START }, | |
1346 | { .irq = -1 } | |
1347 | }; | |
1348 | ||
1349 | static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = { | |
1350 | { .dma_req = 3 + OMAP44XX_DMA_REQ_START }, | |
1351 | { .dma_req = -1 } | |
1352 | }; | |
1353 | ||
1354 | static struct omap_hwmod omap44xx_gpmc_hwmod = { | |
1355 | .name = "gpmc", | |
1356 | .class = &omap44xx_gpmc_hwmod_class, | |
1357 | .clkdm_name = "l3_2_clkdm", | |
49484a60 AM |
1358 | /* |
1359 | * XXX HWMOD_INIT_NO_RESET should not be needed for this IP | |
1360 | * block. It is not being added due to any known bugs with | |
1361 | * resetting the GPMC IP block, but rather because any timings | |
1362 | * set by the bootloader are not being correctly programmed by | |
1363 | * the kernel from the board file or DT data. | |
1364 | * HWMOD_INIT_NO_RESET should be removed ASAP. | |
1365 | */ | |
eb42b5d3 BC |
1366 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
1367 | .mpu_irqs = omap44xx_gpmc_irqs, | |
1368 | .sdma_reqs = omap44xx_gpmc_sdma_reqs, | |
1369 | .prcm = { | |
1370 | .omap4 = { | |
1371 | .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET, | |
1372 | .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET, | |
1373 | .modulemode = MODULEMODE_HWCTRL, | |
1374 | }, | |
1375 | }, | |
1376 | }; | |
1377 | ||
9def390e PW |
1378 | /* |
1379 | * 'gpu' class | |
1380 | * 2d/3d graphics accelerator | |
1381 | */ | |
1382 | ||
1383 | static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = { | |
1384 | .rev_offs = 0x1fc00, | |
1385 | .sysc_offs = 0x1fc10, | |
1386 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
1387 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1388 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
1389 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
1390 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1391 | }; | |
1392 | ||
1393 | static struct omap_hwmod_class omap44xx_gpu_hwmod_class = { | |
1394 | .name = "gpu", | |
1395 | .sysc = &omap44xx_gpu_sysc, | |
1396 | }; | |
1397 | ||
1398 | /* gpu */ | |
1399 | static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = { | |
1400 | { .irq = 21 + OMAP44XX_IRQ_GIC_START }, | |
1401 | { .irq = -1 } | |
1402 | }; | |
1403 | ||
1404 | static struct omap_hwmod omap44xx_gpu_hwmod = { | |
1405 | .name = "gpu", | |
1406 | .class = &omap44xx_gpu_hwmod_class, | |
1407 | .clkdm_name = "l3_gfx_clkdm", | |
1408 | .mpu_irqs = omap44xx_gpu_irqs, | |
1409 | .main_clk = "gpu_fck", | |
1410 | .prcm = { | |
1411 | .omap4 = { | |
1412 | .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET, | |
1413 | .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET, | |
1414 | .modulemode = MODULEMODE_SWCTRL, | |
1415 | }, | |
1416 | }, | |
1417 | }; | |
1418 | ||
a091c08e PW |
1419 | /* |
1420 | * 'hdq1w' class | |
1421 | * hdq / 1-wire serial interface controller | |
1422 | */ | |
1423 | ||
1424 | static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = { | |
1425 | .rev_offs = 0x0000, | |
1426 | .sysc_offs = 0x0014, | |
1427 | .syss_offs = 0x0018, | |
1428 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET | | |
1429 | SYSS_HAS_RESET_STATUS), | |
1430 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1431 | }; | |
1432 | ||
1433 | static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = { | |
1434 | .name = "hdq1w", | |
1435 | .sysc = &omap44xx_hdq1w_sysc, | |
1436 | }; | |
1437 | ||
1438 | /* hdq1w */ | |
1439 | static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = { | |
1440 | { .irq = 58 + OMAP44XX_IRQ_GIC_START }, | |
1441 | { .irq = -1 } | |
1442 | }; | |
1443 | ||
1444 | static struct omap_hwmod omap44xx_hdq1w_hwmod = { | |
1445 | .name = "hdq1w", | |
1446 | .class = &omap44xx_hdq1w_hwmod_class, | |
1447 | .clkdm_name = "l4_per_clkdm", | |
1448 | .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ | |
1449 | .mpu_irqs = omap44xx_hdq1w_irqs, | |
1450 | .main_clk = "hdq1w_fck", | |
1451 | .prcm = { | |
1452 | .omap4 = { | |
1453 | .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, | |
1454 | .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET, | |
1455 | .modulemode = MODULEMODE_SWCTRL, | |
1456 | }, | |
1457 | }, | |
1458 | }; | |
1459 | ||
407a6888 BC |
1460 | /* |
1461 | * 'hsi' class | |
1462 | * mipi high-speed synchronous serial interface (multichannel and full-duplex | |
1463 | * serial if) | |
1464 | */ | |
1465 | ||
1466 | static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = { | |
1467 | .rev_offs = 0x0000, | |
1468 | .sysc_offs = 0x0010, | |
1469 | .syss_offs = 0x0014, | |
1470 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | | |
1471 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
1472 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1473 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1474 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1475 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1476 | .sysc_fields = &omap_hwmod_sysc_type1, |
1477 | }; | |
1478 | ||
1479 | static struct omap_hwmod_class omap44xx_hsi_hwmod_class = { | |
1480 | .name = "hsi", | |
1481 | .sysc = &omap44xx_hsi_sysc, | |
1482 | }; | |
1483 | ||
1484 | /* hsi */ | |
1485 | static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { | |
1486 | { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START }, | |
1487 | { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START }, | |
1488 | { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1489 | { .irq = -1 } |
407a6888 BC |
1490 | }; |
1491 | ||
407a6888 BC |
1492 | static struct omap_hwmod omap44xx_hsi_hwmod = { |
1493 | .name = "hsi", | |
1494 | .class = &omap44xx_hsi_hwmod_class, | |
a5322c6f | 1495 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 1496 | .mpu_irqs = omap44xx_hsi_irqs, |
407a6888 | 1497 | .main_clk = "hsi_fck", |
00fe610b | 1498 | .prcm = { |
407a6888 | 1499 | .omap4 = { |
d0f0631d | 1500 | .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET, |
27bb00b5 | 1501 | .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET, |
03fdefe5 | 1502 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1503 | }, |
1504 | }, | |
407a6888 BC |
1505 | }; |
1506 | ||
3b54baad BC |
1507 | /* |
1508 | * 'i2c' class | |
1509 | * multimaster high-speed i2c controller | |
1510 | */ | |
db12ba53 | 1511 | |
3b54baad BC |
1512 | static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { |
1513 | .sysc_offs = 0x0010, | |
1514 | .syss_offs = 0x0090, | |
1515 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1516 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 1517 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
1518 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1519 | SIDLE_SMART_WKUP), | |
3e47dc6a | 1520 | .clockact = CLOCKACT_TEST_ICLK, |
3b54baad | 1521 | .sysc_fields = &omap_hwmod_sysc_type1, |
db12ba53 BC |
1522 | }; |
1523 | ||
3b54baad | 1524 | static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { |
fe13471c BC |
1525 | .name = "i2c", |
1526 | .sysc = &omap44xx_i2c_sysc, | |
db791a75 | 1527 | .rev = OMAP_I2C_IP_VERSION_2, |
6d3c55fd | 1528 | .reset = &omap_i2c_reset, |
db12ba53 BC |
1529 | }; |
1530 | ||
4d4441a6 | 1531 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
972deb4f | 1532 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, |
4d4441a6 AG |
1533 | }; |
1534 | ||
3b54baad | 1535 | /* i2c1 */ |
3b54baad BC |
1536 | static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { |
1537 | { .irq = 56 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1538 | { .irq = -1 } |
db12ba53 BC |
1539 | }; |
1540 | ||
3b54baad BC |
1541 | static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { |
1542 | { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, | |
1543 | { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1544 | { .dma_req = -1 } |
db12ba53 BC |
1545 | }; |
1546 | ||
3b54baad BC |
1547 | static struct omap_hwmod omap44xx_i2c1_hwmod = { |
1548 | .name = "i2c1", | |
1549 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1550 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1551 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1552 | .mpu_irqs = omap44xx_i2c1_irqs, |
3b54baad | 1553 | .sdma_reqs = omap44xx_i2c1_sdma_reqs, |
3b54baad | 1554 | .main_clk = "i2c1_fck", |
92b18d1c BC |
1555 | .prcm = { |
1556 | .omap4 = { | |
d0f0631d | 1557 | .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET, |
27bb00b5 | 1558 | .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET, |
03fdefe5 | 1559 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
1560 | }, |
1561 | }, | |
4d4441a6 | 1562 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
1563 | }; |
1564 | ||
3b54baad | 1565 | /* i2c2 */ |
3b54baad BC |
1566 | static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { |
1567 | { .irq = 57 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1568 | { .irq = -1 } |
92b18d1c BC |
1569 | }; |
1570 | ||
3b54baad BC |
1571 | static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { |
1572 | { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, | |
1573 | { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1574 | { .dma_req = -1 } |
3b54baad BC |
1575 | }; |
1576 | ||
3b54baad BC |
1577 | static struct omap_hwmod omap44xx_i2c2_hwmod = { |
1578 | .name = "i2c2", | |
1579 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1580 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1581 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1582 | .mpu_irqs = omap44xx_i2c2_irqs, |
3b54baad | 1583 | .sdma_reqs = omap44xx_i2c2_sdma_reqs, |
3b54baad | 1584 | .main_clk = "i2c2_fck", |
db12ba53 BC |
1585 | .prcm = { |
1586 | .omap4 = { | |
d0f0631d | 1587 | .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, |
27bb00b5 | 1588 | .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET, |
03fdefe5 | 1589 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
1590 | }, |
1591 | }, | |
4d4441a6 | 1592 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
1593 | }; |
1594 | ||
3b54baad | 1595 | /* i2c3 */ |
3b54baad BC |
1596 | static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { |
1597 | { .irq = 61 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1598 | { .irq = -1 } |
db12ba53 BC |
1599 | }; |
1600 | ||
3b54baad BC |
1601 | static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { |
1602 | { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, | |
1603 | { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1604 | { .dma_req = -1 } |
92b18d1c BC |
1605 | }; |
1606 | ||
3b54baad BC |
1607 | static struct omap_hwmod omap44xx_i2c3_hwmod = { |
1608 | .name = "i2c3", | |
1609 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1610 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1611 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1612 | .mpu_irqs = omap44xx_i2c3_irqs, |
3b54baad | 1613 | .sdma_reqs = omap44xx_i2c3_sdma_reqs, |
3b54baad | 1614 | .main_clk = "i2c3_fck", |
db12ba53 BC |
1615 | .prcm = { |
1616 | .omap4 = { | |
d0f0631d | 1617 | .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET, |
27bb00b5 | 1618 | .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET, |
03fdefe5 | 1619 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
1620 | }, |
1621 | }, | |
4d4441a6 | 1622 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
1623 | }; |
1624 | ||
3b54baad | 1625 | /* i2c4 */ |
3b54baad BC |
1626 | static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { |
1627 | { .irq = 62 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1628 | { .irq = -1 } |
db12ba53 BC |
1629 | }; |
1630 | ||
3b54baad BC |
1631 | static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { |
1632 | { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, | |
1633 | { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1634 | { .dma_req = -1 } |
db12ba53 BC |
1635 | }; |
1636 | ||
3b54baad BC |
1637 | static struct omap_hwmod omap44xx_i2c4_hwmod = { |
1638 | .name = "i2c4", | |
1639 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1640 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1641 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1642 | .mpu_irqs = omap44xx_i2c4_irqs, |
3b54baad | 1643 | .sdma_reqs = omap44xx_i2c4_sdma_reqs, |
3b54baad | 1644 | .main_clk = "i2c4_fck", |
92b18d1c BC |
1645 | .prcm = { |
1646 | .omap4 = { | |
d0f0631d | 1647 | .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET, |
27bb00b5 | 1648 | .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET, |
03fdefe5 | 1649 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
1650 | }, |
1651 | }, | |
4d4441a6 | 1652 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
1653 | }; |
1654 | ||
407a6888 BC |
1655 | /* |
1656 | * 'ipu' class | |
1657 | * imaging processor unit | |
1658 | */ | |
1659 | ||
1660 | static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { | |
1661 | .name = "ipu", | |
1662 | }; | |
1663 | ||
1664 | /* ipu */ | |
1665 | static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { | |
1666 | { .irq = 100 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1667 | { .irq = -1 } |
407a6888 BC |
1668 | }; |
1669 | ||
f2f5736c | 1670 | static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { |
407a6888 | 1671 | { .name = "cpu0", .rst_shift = 0 }, |
407a6888 | 1672 | { .name = "cpu1", .rst_shift = 1 }, |
407a6888 BC |
1673 | }; |
1674 | ||
407a6888 BC |
1675 | static struct omap_hwmod omap44xx_ipu_hwmod = { |
1676 | .name = "ipu", | |
1677 | .class = &omap44xx_ipu_hwmod_class, | |
a5322c6f | 1678 | .clkdm_name = "ducati_clkdm", |
407a6888 | 1679 | .mpu_irqs = omap44xx_ipu_irqs, |
407a6888 BC |
1680 | .rst_lines = omap44xx_ipu_resets, |
1681 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), | |
298ea44f | 1682 | .main_clk = "ducati_clk_mux_ck", |
00fe610b | 1683 | .prcm = { |
407a6888 | 1684 | .omap4 = { |
d0f0631d | 1685 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, |
eaac329d | 1686 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, |
27bb00b5 | 1687 | .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, |
03fdefe5 | 1688 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1689 | }, |
1690 | }, | |
407a6888 BC |
1691 | }; |
1692 | ||
1693 | /* | |
1694 | * 'iss' class | |
1695 | * external images sensor pixel data processor | |
1696 | */ | |
1697 | ||
1698 | static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { | |
1699 | .rev_offs = 0x0000, | |
1700 | .sysc_offs = 0x0010, | |
d99de7f5 FGL |
1701 | /* |
1702 | * ISS needs 100 OCP clk cycles delay after a softreset before | |
1703 | * accessing sysconfig again. | |
1704 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
1705 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
1706 | * | |
1707 | * TODO: Indicate errata when available. | |
1708 | */ | |
1709 | .srst_udelay = 2, | |
407a6888 BC |
1710 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | |
1711 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1712 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1713 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1714 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1715 | .sysc_fields = &omap_hwmod_sysc_type2, |
1716 | }; | |
1717 | ||
1718 | static struct omap_hwmod_class omap44xx_iss_hwmod_class = { | |
1719 | .name = "iss", | |
1720 | .sysc = &omap44xx_iss_sysc, | |
1721 | }; | |
1722 | ||
1723 | /* iss */ | |
1724 | static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = { | |
1725 | { .irq = 24 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1726 | { .irq = -1 } |
407a6888 BC |
1727 | }; |
1728 | ||
1729 | static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { | |
1730 | { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START }, | |
1731 | { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START }, | |
1732 | { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START }, | |
1733 | { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1734 | { .dma_req = -1 } |
407a6888 BC |
1735 | }; |
1736 | ||
407a6888 BC |
1737 | static struct omap_hwmod_opt_clk iss_opt_clks[] = { |
1738 | { .role = "ctrlclk", .clk = "iss_ctrlclk" }, | |
1739 | }; | |
1740 | ||
1741 | static struct omap_hwmod omap44xx_iss_hwmod = { | |
1742 | .name = "iss", | |
1743 | .class = &omap44xx_iss_hwmod_class, | |
a5322c6f | 1744 | .clkdm_name = "iss_clkdm", |
407a6888 | 1745 | .mpu_irqs = omap44xx_iss_irqs, |
407a6888 | 1746 | .sdma_reqs = omap44xx_iss_sdma_reqs, |
407a6888 | 1747 | .main_clk = "iss_fck", |
00fe610b | 1748 | .prcm = { |
407a6888 | 1749 | .omap4 = { |
d0f0631d | 1750 | .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, |
27bb00b5 | 1751 | .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET, |
03fdefe5 | 1752 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1753 | }, |
1754 | }, | |
1755 | .opt_clks = iss_opt_clks, | |
1756 | .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), | |
407a6888 BC |
1757 | }; |
1758 | ||
8f25bdc5 BC |
1759 | /* |
1760 | * 'iva' class | |
1761 | * multi-standard video encoder/decoder hardware accelerator | |
1762 | */ | |
1763 | ||
1764 | static struct omap_hwmod_class omap44xx_iva_hwmod_class = { | |
fe13471c | 1765 | .name = "iva", |
8f25bdc5 BC |
1766 | }; |
1767 | ||
1768 | /* iva */ | |
1769 | static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { | |
1770 | { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, | |
1771 | { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, | |
1772 | { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1773 | { .irq = -1 } |
8f25bdc5 BC |
1774 | }; |
1775 | ||
1776 | static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { | |
8f25bdc5 | 1777 | { .name = "seq0", .rst_shift = 0 }, |
8f25bdc5 | 1778 | { .name = "seq1", .rst_shift = 1 }, |
f2f5736c | 1779 | { .name = "logic", .rst_shift = 2 }, |
8f25bdc5 BC |
1780 | }; |
1781 | ||
8f25bdc5 BC |
1782 | static struct omap_hwmod omap44xx_iva_hwmod = { |
1783 | .name = "iva", | |
1784 | .class = &omap44xx_iva_hwmod_class, | |
a5322c6f | 1785 | .clkdm_name = "ivahd_clkdm", |
8f25bdc5 | 1786 | .mpu_irqs = omap44xx_iva_irqs, |
8f25bdc5 BC |
1787 | .rst_lines = omap44xx_iva_resets, |
1788 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), | |
1789 | .main_clk = "iva_fck", | |
1790 | .prcm = { | |
1791 | .omap4 = { | |
d0f0631d | 1792 | .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, |
eaac329d | 1793 | .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, |
27bb00b5 | 1794 | .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET, |
03fdefe5 | 1795 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
1796 | }, |
1797 | }, | |
8f25bdc5 BC |
1798 | }; |
1799 | ||
407a6888 BC |
1800 | /* |
1801 | * 'kbd' class | |
1802 | * keyboard controller | |
1803 | */ | |
1804 | ||
1805 | static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = { | |
1806 | .rev_offs = 0x0000, | |
1807 | .sysc_offs = 0x0010, | |
1808 | .syss_offs = 0x0014, | |
1809 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1810 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
1811 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1812 | SYSS_HAS_RESET_STATUS), | |
1813 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1814 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1815 | }; | |
1816 | ||
1817 | static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { | |
1818 | .name = "kbd", | |
1819 | .sysc = &omap44xx_kbd_sysc, | |
1820 | }; | |
1821 | ||
1822 | /* kbd */ | |
407a6888 BC |
1823 | static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { |
1824 | { .irq = 120 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1825 | { .irq = -1 } |
407a6888 BC |
1826 | }; |
1827 | ||
407a6888 BC |
1828 | static struct omap_hwmod omap44xx_kbd_hwmod = { |
1829 | .name = "kbd", | |
1830 | .class = &omap44xx_kbd_hwmod_class, | |
a5322c6f | 1831 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 | 1832 | .mpu_irqs = omap44xx_kbd_irqs, |
407a6888 | 1833 | .main_clk = "kbd_fck", |
00fe610b | 1834 | .prcm = { |
407a6888 | 1835 | .omap4 = { |
d0f0631d | 1836 | .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, |
27bb00b5 | 1837 | .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET, |
03fdefe5 | 1838 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1839 | }, |
1840 | }, | |
407a6888 BC |
1841 | }; |
1842 | ||
ec5df927 BC |
1843 | /* |
1844 | * 'mailbox' class | |
1845 | * mailbox module allowing communication between the on-chip processors using a | |
1846 | * queued mailbox-interrupt mechanism. | |
1847 | */ | |
1848 | ||
1849 | static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = { | |
1850 | .rev_offs = 0x0000, | |
1851 | .sysc_offs = 0x0010, | |
1852 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1853 | SYSC_HAS_SOFTRESET), | |
1854 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1855 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1856 | }; | |
1857 | ||
1858 | static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { | |
1859 | .name = "mailbox", | |
1860 | .sysc = &omap44xx_mailbox_sysc, | |
1861 | }; | |
1862 | ||
1863 | /* mailbox */ | |
ec5df927 BC |
1864 | static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { |
1865 | { .irq = 26 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1866 | { .irq = -1 } |
ec5df927 BC |
1867 | }; |
1868 | ||
ec5df927 BC |
1869 | static struct omap_hwmod omap44xx_mailbox_hwmod = { |
1870 | .name = "mailbox", | |
1871 | .class = &omap44xx_mailbox_hwmod_class, | |
a5322c6f | 1872 | .clkdm_name = "l4_cfg_clkdm", |
ec5df927 | 1873 | .mpu_irqs = omap44xx_mailbox_irqs, |
00fe610b | 1874 | .prcm = { |
ec5df927 | 1875 | .omap4 = { |
d0f0631d | 1876 | .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, |
27bb00b5 | 1877 | .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, |
ec5df927 BC |
1878 | }, |
1879 | }, | |
ec5df927 BC |
1880 | }; |
1881 | ||
896d4e98 BC |
1882 | /* |
1883 | * 'mcasp' class | |
1884 | * multi-channel audio serial port controller | |
1885 | */ | |
1886 | ||
1887 | /* The IP is not compliant to type1 / type2 scheme */ | |
1888 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = { | |
1889 | .sidle_shift = 0, | |
1890 | }; | |
1891 | ||
1892 | static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = { | |
1893 | .sysc_offs = 0x0004, | |
1894 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
1895 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1896 | SIDLE_SMART_WKUP), | |
1897 | .sysc_fields = &omap_hwmod_sysc_type_mcasp, | |
1898 | }; | |
1899 | ||
1900 | static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = { | |
1901 | .name = "mcasp", | |
1902 | .sysc = &omap44xx_mcasp_sysc, | |
1903 | }; | |
1904 | ||
1905 | /* mcasp */ | |
1906 | static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = { | |
1907 | { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START }, | |
1908 | { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START }, | |
1909 | { .irq = -1 } | |
1910 | }; | |
1911 | ||
1912 | static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = { | |
1913 | { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START }, | |
1914 | { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START }, | |
1915 | { .dma_req = -1 } | |
1916 | }; | |
1917 | ||
1918 | static struct omap_hwmod omap44xx_mcasp_hwmod = { | |
1919 | .name = "mcasp", | |
1920 | .class = &omap44xx_mcasp_hwmod_class, | |
1921 | .clkdm_name = "abe_clkdm", | |
1922 | .mpu_irqs = omap44xx_mcasp_irqs, | |
1923 | .sdma_reqs = omap44xx_mcasp_sdma_reqs, | |
1924 | .main_clk = "mcasp_fck", | |
1925 | .prcm = { | |
1926 | .omap4 = { | |
1927 | .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET, | |
1928 | .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET, | |
1929 | .modulemode = MODULEMODE_SWCTRL, | |
1930 | }, | |
1931 | }, | |
1932 | }; | |
1933 | ||
4ddff493 BC |
1934 | /* |
1935 | * 'mcbsp' class | |
1936 | * multi channel buffered serial port controller | |
1937 | */ | |
1938 | ||
1939 | static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { | |
1940 | .sysc_offs = 0x008c, | |
1941 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
1942 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1943 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1944 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1945 | }; | |
1946 | ||
1947 | static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { | |
1948 | .name = "mcbsp", | |
1949 | .sysc = &omap44xx_mcbsp_sysc, | |
cb7e9ded | 1950 | .rev = MCBSP_CONFIG_TYPE4, |
4ddff493 BC |
1951 | }; |
1952 | ||
1953 | /* mcbsp1 */ | |
4ddff493 | 1954 | static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { |
437e8970 | 1955 | { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START }, |
212738a4 | 1956 | { .irq = -1 } |
4ddff493 BC |
1957 | }; |
1958 | ||
1959 | static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { | |
1960 | { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, | |
1961 | { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1962 | { .dma_req = -1 } |
4ddff493 BC |
1963 | }; |
1964 | ||
503d0ea2 PW |
1965 | static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { |
1966 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 1967 | { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" }, |
503d0ea2 PW |
1968 | }; |
1969 | ||
4ddff493 BC |
1970 | static struct omap_hwmod omap44xx_mcbsp1_hwmod = { |
1971 | .name = "mcbsp1", | |
1972 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1973 | .clkdm_name = "abe_clkdm", |
4ddff493 | 1974 | .mpu_irqs = omap44xx_mcbsp1_irqs, |
4ddff493 | 1975 | .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, |
4ddff493 BC |
1976 | .main_clk = "mcbsp1_fck", |
1977 | .prcm = { | |
1978 | .omap4 = { | |
d0f0631d | 1979 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, |
27bb00b5 | 1980 | .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET, |
03fdefe5 | 1981 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1982 | }, |
1983 | }, | |
503d0ea2 PW |
1984 | .opt_clks = mcbsp1_opt_clks, |
1985 | .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks), | |
4ddff493 BC |
1986 | }; |
1987 | ||
1988 | /* mcbsp2 */ | |
4ddff493 | 1989 | static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { |
437e8970 | 1990 | { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START }, |
212738a4 | 1991 | { .irq = -1 } |
4ddff493 BC |
1992 | }; |
1993 | ||
1994 | static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { | |
1995 | { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START }, | |
1996 | { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1997 | { .dma_req = -1 } |
4ddff493 BC |
1998 | }; |
1999 | ||
844a3b63 PW |
2000 | static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { |
2001 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 2002 | { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" }, |
503d0ea2 PW |
2003 | }; |
2004 | ||
4ddff493 BC |
2005 | static struct omap_hwmod omap44xx_mcbsp2_hwmod = { |
2006 | .name = "mcbsp2", | |
2007 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 2008 | .clkdm_name = "abe_clkdm", |
4ddff493 | 2009 | .mpu_irqs = omap44xx_mcbsp2_irqs, |
4ddff493 | 2010 | .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, |
4ddff493 BC |
2011 | .main_clk = "mcbsp2_fck", |
2012 | .prcm = { | |
2013 | .omap4 = { | |
d0f0631d | 2014 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, |
27bb00b5 | 2015 | .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET, |
03fdefe5 | 2016 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
2017 | }, |
2018 | }, | |
503d0ea2 PW |
2019 | .opt_clks = mcbsp2_opt_clks, |
2020 | .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks), | |
4ddff493 BC |
2021 | }; |
2022 | ||
2023 | /* mcbsp3 */ | |
4ddff493 | 2024 | static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { |
437e8970 | 2025 | { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START }, |
212738a4 | 2026 | { .irq = -1 } |
4ddff493 BC |
2027 | }; |
2028 | ||
2029 | static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { | |
2030 | { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START }, | |
2031 | { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2032 | { .dma_req = -1 } |
4ddff493 BC |
2033 | }; |
2034 | ||
503d0ea2 PW |
2035 | static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { |
2036 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 2037 | { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" }, |
503d0ea2 PW |
2038 | }; |
2039 | ||
4ddff493 BC |
2040 | static struct omap_hwmod omap44xx_mcbsp3_hwmod = { |
2041 | .name = "mcbsp3", | |
2042 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 2043 | .clkdm_name = "abe_clkdm", |
4ddff493 | 2044 | .mpu_irqs = omap44xx_mcbsp3_irqs, |
4ddff493 | 2045 | .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, |
4ddff493 BC |
2046 | .main_clk = "mcbsp3_fck", |
2047 | .prcm = { | |
2048 | .omap4 = { | |
d0f0631d | 2049 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, |
27bb00b5 | 2050 | .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET, |
03fdefe5 | 2051 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
2052 | }, |
2053 | }, | |
503d0ea2 PW |
2054 | .opt_clks = mcbsp3_opt_clks, |
2055 | .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks), | |
4ddff493 BC |
2056 | }; |
2057 | ||
2058 | /* mcbsp4 */ | |
4ddff493 | 2059 | static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { |
437e8970 | 2060 | { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START }, |
212738a4 | 2061 | { .irq = -1 } |
4ddff493 BC |
2062 | }; |
2063 | ||
2064 | static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { | |
2065 | { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START }, | |
2066 | { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2067 | { .dma_req = -1 } |
4ddff493 BC |
2068 | }; |
2069 | ||
503d0ea2 PW |
2070 | static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { |
2071 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 2072 | { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" }, |
503d0ea2 PW |
2073 | }; |
2074 | ||
4ddff493 BC |
2075 | static struct omap_hwmod omap44xx_mcbsp4_hwmod = { |
2076 | .name = "mcbsp4", | |
2077 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 2078 | .clkdm_name = "l4_per_clkdm", |
4ddff493 | 2079 | .mpu_irqs = omap44xx_mcbsp4_irqs, |
4ddff493 | 2080 | .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, |
4ddff493 BC |
2081 | .main_clk = "mcbsp4_fck", |
2082 | .prcm = { | |
2083 | .omap4 = { | |
d0f0631d | 2084 | .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, |
27bb00b5 | 2085 | .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET, |
03fdefe5 | 2086 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
2087 | }, |
2088 | }, | |
503d0ea2 PW |
2089 | .opt_clks = mcbsp4_opt_clks, |
2090 | .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks), | |
4ddff493 BC |
2091 | }; |
2092 | ||
407a6888 BC |
2093 | /* |
2094 | * 'mcpdm' class | |
2095 | * multi channel pdm controller (proprietary interface with phoenix power | |
2096 | * ic) | |
2097 | */ | |
2098 | ||
2099 | static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = { | |
2100 | .rev_offs = 0x0000, | |
2101 | .sysc_offs = 0x0010, | |
2102 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2103 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2104 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2105 | SIDLE_SMART_WKUP), | |
2106 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2107 | }; | |
2108 | ||
2109 | static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { | |
2110 | .name = "mcpdm", | |
2111 | .sysc = &omap44xx_mcpdm_sysc, | |
2112 | }; | |
2113 | ||
2114 | /* mcpdm */ | |
407a6888 BC |
2115 | static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { |
2116 | { .irq = 112 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2117 | { .irq = -1 } |
407a6888 BC |
2118 | }; |
2119 | ||
2120 | static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { | |
2121 | { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START }, | |
2122 | { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2123 | { .dma_req = -1 } |
407a6888 BC |
2124 | }; |
2125 | ||
407a6888 BC |
2126 | static struct omap_hwmod omap44xx_mcpdm_hwmod = { |
2127 | .name = "mcpdm", | |
2128 | .class = &omap44xx_mcpdm_hwmod_class, | |
a5322c6f | 2129 | .clkdm_name = "abe_clkdm", |
bc05244e PW |
2130 | /* |
2131 | * It's suspected that the McPDM requires an off-chip main | |
2132 | * functional clock, controlled via I2C. This IP block is | |
2133 | * currently reset very early during boot, before I2C is | |
2134 | * available, so it doesn't seem that we have any choice in | |
2135 | * the kernel other than to avoid resetting it. | |
2136 | */ | |
2137 | .flags = HWMOD_EXT_OPT_MAIN_CLK, | |
407a6888 | 2138 | .mpu_irqs = omap44xx_mcpdm_irqs, |
407a6888 | 2139 | .sdma_reqs = omap44xx_mcpdm_sdma_reqs, |
407a6888 | 2140 | .main_clk = "mcpdm_fck", |
00fe610b | 2141 | .prcm = { |
407a6888 | 2142 | .omap4 = { |
d0f0631d | 2143 | .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, |
27bb00b5 | 2144 | .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET, |
03fdefe5 | 2145 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2146 | }, |
2147 | }, | |
407a6888 BC |
2148 | }; |
2149 | ||
9bcbd7f0 BC |
2150 | /* |
2151 | * 'mcspi' class | |
2152 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
2153 | * bus | |
2154 | */ | |
2155 | ||
2156 | static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = { | |
2157 | .rev_offs = 0x0000, | |
2158 | .sysc_offs = 0x0010, | |
2159 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2160 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2161 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2162 | SIDLE_SMART_WKUP), | |
2163 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2164 | }; | |
2165 | ||
2166 | static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { | |
2167 | .name = "mcspi", | |
2168 | .sysc = &omap44xx_mcspi_sysc, | |
905a74d9 | 2169 | .rev = OMAP4_MCSPI_REV, |
9bcbd7f0 BC |
2170 | }; |
2171 | ||
2172 | /* mcspi1 */ | |
9bcbd7f0 BC |
2173 | static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { |
2174 | { .irq = 65 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2175 | { .irq = -1 } |
9bcbd7f0 BC |
2176 | }; |
2177 | ||
2178 | static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { | |
2179 | { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, | |
2180 | { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, | |
2181 | { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START }, | |
2182 | { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START }, | |
2183 | { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START }, | |
2184 | { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, | |
2185 | { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, | |
2186 | { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2187 | { .dma_req = -1 } |
9bcbd7f0 BC |
2188 | }; |
2189 | ||
905a74d9 BC |
2190 | /* mcspi1 dev_attr */ |
2191 | static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { | |
2192 | .num_chipselect = 4, | |
2193 | }; | |
2194 | ||
9bcbd7f0 BC |
2195 | static struct omap_hwmod omap44xx_mcspi1_hwmod = { |
2196 | .name = "mcspi1", | |
2197 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2198 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2199 | .mpu_irqs = omap44xx_mcspi1_irqs, |
9bcbd7f0 | 2200 | .sdma_reqs = omap44xx_mcspi1_sdma_reqs, |
9bcbd7f0 BC |
2201 | .main_clk = "mcspi1_fck", |
2202 | .prcm = { | |
2203 | .omap4 = { | |
d0f0631d | 2204 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, |
27bb00b5 | 2205 | .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET, |
03fdefe5 | 2206 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2207 | }, |
2208 | }, | |
905a74d9 | 2209 | .dev_attr = &mcspi1_dev_attr, |
9bcbd7f0 BC |
2210 | }; |
2211 | ||
2212 | /* mcspi2 */ | |
9bcbd7f0 BC |
2213 | static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { |
2214 | { .irq = 66 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2215 | { .irq = -1 } |
9bcbd7f0 BC |
2216 | }; |
2217 | ||
2218 | static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { | |
2219 | { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, | |
2220 | { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, | |
2221 | { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, | |
2222 | { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2223 | { .dma_req = -1 } |
9bcbd7f0 BC |
2224 | }; |
2225 | ||
905a74d9 BC |
2226 | /* mcspi2 dev_attr */ |
2227 | static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { | |
2228 | .num_chipselect = 2, | |
2229 | }; | |
2230 | ||
9bcbd7f0 BC |
2231 | static struct omap_hwmod omap44xx_mcspi2_hwmod = { |
2232 | .name = "mcspi2", | |
2233 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2234 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2235 | .mpu_irqs = omap44xx_mcspi2_irqs, |
9bcbd7f0 | 2236 | .sdma_reqs = omap44xx_mcspi2_sdma_reqs, |
9bcbd7f0 BC |
2237 | .main_clk = "mcspi2_fck", |
2238 | .prcm = { | |
2239 | .omap4 = { | |
d0f0631d | 2240 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, |
27bb00b5 | 2241 | .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET, |
03fdefe5 | 2242 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2243 | }, |
2244 | }, | |
905a74d9 | 2245 | .dev_attr = &mcspi2_dev_attr, |
9bcbd7f0 BC |
2246 | }; |
2247 | ||
2248 | /* mcspi3 */ | |
9bcbd7f0 BC |
2249 | static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { |
2250 | { .irq = 91 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2251 | { .irq = -1 } |
9bcbd7f0 BC |
2252 | }; |
2253 | ||
2254 | static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { | |
2255 | { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, | |
2256 | { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, | |
2257 | { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, | |
2258 | { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2259 | { .dma_req = -1 } |
9bcbd7f0 BC |
2260 | }; |
2261 | ||
905a74d9 BC |
2262 | /* mcspi3 dev_attr */ |
2263 | static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { | |
2264 | .num_chipselect = 2, | |
2265 | }; | |
2266 | ||
9bcbd7f0 BC |
2267 | static struct omap_hwmod omap44xx_mcspi3_hwmod = { |
2268 | .name = "mcspi3", | |
2269 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2270 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2271 | .mpu_irqs = omap44xx_mcspi3_irqs, |
9bcbd7f0 | 2272 | .sdma_reqs = omap44xx_mcspi3_sdma_reqs, |
9bcbd7f0 BC |
2273 | .main_clk = "mcspi3_fck", |
2274 | .prcm = { | |
2275 | .omap4 = { | |
d0f0631d | 2276 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, |
27bb00b5 | 2277 | .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET, |
03fdefe5 | 2278 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2279 | }, |
2280 | }, | |
905a74d9 | 2281 | .dev_attr = &mcspi3_dev_attr, |
9bcbd7f0 BC |
2282 | }; |
2283 | ||
2284 | /* mcspi4 */ | |
9bcbd7f0 BC |
2285 | static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { |
2286 | { .irq = 48 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2287 | { .irq = -1 } |
9bcbd7f0 BC |
2288 | }; |
2289 | ||
2290 | static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { | |
2291 | { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, | |
2292 | { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2293 | { .dma_req = -1 } |
9bcbd7f0 BC |
2294 | }; |
2295 | ||
905a74d9 BC |
2296 | /* mcspi4 dev_attr */ |
2297 | static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { | |
2298 | .num_chipselect = 1, | |
2299 | }; | |
2300 | ||
9bcbd7f0 BC |
2301 | static struct omap_hwmod omap44xx_mcspi4_hwmod = { |
2302 | .name = "mcspi4", | |
2303 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2304 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2305 | .mpu_irqs = omap44xx_mcspi4_irqs, |
9bcbd7f0 | 2306 | .sdma_reqs = omap44xx_mcspi4_sdma_reqs, |
9bcbd7f0 BC |
2307 | .main_clk = "mcspi4_fck", |
2308 | .prcm = { | |
2309 | .omap4 = { | |
d0f0631d | 2310 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, |
27bb00b5 | 2311 | .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET, |
03fdefe5 | 2312 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2313 | }, |
2314 | }, | |
905a74d9 | 2315 | .dev_attr = &mcspi4_dev_attr, |
9bcbd7f0 BC |
2316 | }; |
2317 | ||
407a6888 BC |
2318 | /* |
2319 | * 'mmc' class | |
2320 | * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller | |
2321 | */ | |
2322 | ||
2323 | static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = { | |
2324 | .rev_offs = 0x0000, | |
2325 | .sysc_offs = 0x0010, | |
2326 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
2327 | SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
2328 | SYSC_HAS_SOFTRESET), | |
2329 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2330 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 2331 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
2332 | .sysc_fields = &omap_hwmod_sysc_type2, |
2333 | }; | |
2334 | ||
2335 | static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { | |
2336 | .name = "mmc", | |
2337 | .sysc = &omap44xx_mmc_sysc, | |
2338 | }; | |
2339 | ||
2340 | /* mmc1 */ | |
2341 | static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { | |
2342 | { .irq = 83 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2343 | { .irq = -1 } |
407a6888 BC |
2344 | }; |
2345 | ||
2346 | static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { | |
2347 | { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, | |
2348 | { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2349 | { .dma_req = -1 } |
407a6888 BC |
2350 | }; |
2351 | ||
6ab8946f KK |
2352 | /* mmc1 dev_attr */ |
2353 | static struct omap_mmc_dev_attr mmc1_dev_attr = { | |
2354 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
2355 | }; | |
2356 | ||
407a6888 BC |
2357 | static struct omap_hwmod omap44xx_mmc1_hwmod = { |
2358 | .name = "mmc1", | |
2359 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2360 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 2361 | .mpu_irqs = omap44xx_mmc1_irqs, |
407a6888 | 2362 | .sdma_reqs = omap44xx_mmc1_sdma_reqs, |
407a6888 | 2363 | .main_clk = "mmc1_fck", |
00fe610b | 2364 | .prcm = { |
407a6888 | 2365 | .omap4 = { |
d0f0631d | 2366 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET, |
27bb00b5 | 2367 | .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET, |
03fdefe5 | 2368 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2369 | }, |
2370 | }, | |
6ab8946f | 2371 | .dev_attr = &mmc1_dev_attr, |
407a6888 BC |
2372 | }; |
2373 | ||
2374 | /* mmc2 */ | |
2375 | static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = { | |
2376 | { .irq = 86 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2377 | { .irq = -1 } |
407a6888 BC |
2378 | }; |
2379 | ||
2380 | static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { | |
2381 | { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, | |
2382 | { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2383 | { .dma_req = -1 } |
407a6888 BC |
2384 | }; |
2385 | ||
407a6888 BC |
2386 | static struct omap_hwmod omap44xx_mmc2_hwmod = { |
2387 | .name = "mmc2", | |
2388 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2389 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 2390 | .mpu_irqs = omap44xx_mmc2_irqs, |
407a6888 | 2391 | .sdma_reqs = omap44xx_mmc2_sdma_reqs, |
407a6888 | 2392 | .main_clk = "mmc2_fck", |
00fe610b | 2393 | .prcm = { |
407a6888 | 2394 | .omap4 = { |
d0f0631d | 2395 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET, |
27bb00b5 | 2396 | .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET, |
03fdefe5 | 2397 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2398 | }, |
2399 | }, | |
407a6888 BC |
2400 | }; |
2401 | ||
2402 | /* mmc3 */ | |
407a6888 BC |
2403 | static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { |
2404 | { .irq = 94 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2405 | { .irq = -1 } |
407a6888 BC |
2406 | }; |
2407 | ||
2408 | static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { | |
2409 | { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, | |
2410 | { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2411 | { .dma_req = -1 } |
407a6888 BC |
2412 | }; |
2413 | ||
407a6888 BC |
2414 | static struct omap_hwmod omap44xx_mmc3_hwmod = { |
2415 | .name = "mmc3", | |
2416 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2417 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2418 | .mpu_irqs = omap44xx_mmc3_irqs, |
407a6888 | 2419 | .sdma_reqs = omap44xx_mmc3_sdma_reqs, |
407a6888 | 2420 | .main_clk = "mmc3_fck", |
00fe610b | 2421 | .prcm = { |
407a6888 | 2422 | .omap4 = { |
d0f0631d | 2423 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET, |
27bb00b5 | 2424 | .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET, |
03fdefe5 | 2425 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2426 | }, |
2427 | }, | |
407a6888 BC |
2428 | }; |
2429 | ||
2430 | /* mmc4 */ | |
407a6888 BC |
2431 | static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { |
2432 | { .irq = 96 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2433 | { .irq = -1 } |
407a6888 BC |
2434 | }; |
2435 | ||
2436 | static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { | |
2437 | { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, | |
2438 | { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2439 | { .dma_req = -1 } |
407a6888 BC |
2440 | }; |
2441 | ||
407a6888 BC |
2442 | static struct omap_hwmod omap44xx_mmc4_hwmod = { |
2443 | .name = "mmc4", | |
2444 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2445 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2446 | .mpu_irqs = omap44xx_mmc4_irqs, |
407a6888 | 2447 | .sdma_reqs = omap44xx_mmc4_sdma_reqs, |
407a6888 | 2448 | .main_clk = "mmc4_fck", |
00fe610b | 2449 | .prcm = { |
407a6888 | 2450 | .omap4 = { |
d0f0631d | 2451 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET, |
27bb00b5 | 2452 | .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET, |
03fdefe5 | 2453 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2454 | }, |
2455 | }, | |
407a6888 BC |
2456 | }; |
2457 | ||
2458 | /* mmc5 */ | |
407a6888 BC |
2459 | static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { |
2460 | { .irq = 59 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2461 | { .irq = -1 } |
407a6888 BC |
2462 | }; |
2463 | ||
2464 | static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { | |
2465 | { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, | |
2466 | { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2467 | { .dma_req = -1 } |
407a6888 BC |
2468 | }; |
2469 | ||
407a6888 BC |
2470 | static struct omap_hwmod omap44xx_mmc5_hwmod = { |
2471 | .name = "mmc5", | |
2472 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2473 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2474 | .mpu_irqs = omap44xx_mmc5_irqs, |
407a6888 | 2475 | .sdma_reqs = omap44xx_mmc5_sdma_reqs, |
407a6888 | 2476 | .main_clk = "mmc5_fck", |
00fe610b | 2477 | .prcm = { |
407a6888 | 2478 | .omap4 = { |
d0f0631d | 2479 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET, |
27bb00b5 | 2480 | .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET, |
03fdefe5 | 2481 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2482 | }, |
2483 | }, | |
407a6888 BC |
2484 | }; |
2485 | ||
230844db ORL |
2486 | /* |
2487 | * 'mmu' class | |
2488 | * The memory management unit performs virtual to physical address translation | |
2489 | * for its requestors. | |
2490 | */ | |
2491 | ||
2492 | static struct omap_hwmod_class_sysconfig mmu_sysc = { | |
2493 | .rev_offs = 0x000, | |
2494 | .sysc_offs = 0x010, | |
2495 | .syss_offs = 0x014, | |
2496 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
2497 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
2498 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2499 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2500 | }; | |
2501 | ||
2502 | static struct omap_hwmod_class omap44xx_mmu_hwmod_class = { | |
2503 | .name = "mmu", | |
2504 | .sysc = &mmu_sysc, | |
2505 | }; | |
2506 | ||
2507 | /* mmu ipu */ | |
2508 | ||
2509 | static struct omap_mmu_dev_attr mmu_ipu_dev_attr = { | |
2510 | .da_start = 0x0, | |
2511 | .da_end = 0xfffff000, | |
2512 | .nr_tlb_entries = 32, | |
2513 | }; | |
2514 | ||
2515 | static struct omap_hwmod omap44xx_mmu_ipu_hwmod; | |
2516 | static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = { | |
2517 | { .irq = 100 + OMAP44XX_IRQ_GIC_START, }, | |
2518 | { .irq = -1 } | |
2519 | }; | |
2520 | ||
2521 | static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = { | |
2522 | { .name = "mmu_cache", .rst_shift = 2 }, | |
2523 | }; | |
2524 | ||
2525 | static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = { | |
2526 | { | |
2527 | .pa_start = 0x55082000, | |
2528 | .pa_end = 0x550820ff, | |
2529 | .flags = ADDR_TYPE_RT, | |
2530 | }, | |
2531 | { } | |
2532 | }; | |
2533 | ||
2534 | /* l3_main_2 -> mmu_ipu */ | |
2535 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = { | |
2536 | .master = &omap44xx_l3_main_2_hwmod, | |
2537 | .slave = &omap44xx_mmu_ipu_hwmod, | |
2538 | .clk = "l3_div_ck", | |
2539 | .addr = omap44xx_mmu_ipu_addrs, | |
2540 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2541 | }; | |
2542 | ||
2543 | static struct omap_hwmod omap44xx_mmu_ipu_hwmod = { | |
2544 | .name = "mmu_ipu", | |
2545 | .class = &omap44xx_mmu_hwmod_class, | |
2546 | .clkdm_name = "ducati_clkdm", | |
2547 | .mpu_irqs = omap44xx_mmu_ipu_irqs, | |
2548 | .rst_lines = omap44xx_mmu_ipu_resets, | |
2549 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets), | |
2550 | .main_clk = "ducati_clk_mux_ck", | |
2551 | .prcm = { | |
2552 | .omap4 = { | |
2553 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, | |
2554 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, | |
2555 | .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, | |
2556 | .modulemode = MODULEMODE_HWCTRL, | |
2557 | }, | |
2558 | }, | |
2559 | .dev_attr = &mmu_ipu_dev_attr, | |
2560 | }; | |
2561 | ||
2562 | /* mmu dsp */ | |
2563 | ||
2564 | static struct omap_mmu_dev_attr mmu_dsp_dev_attr = { | |
2565 | .da_start = 0x0, | |
2566 | .da_end = 0xfffff000, | |
2567 | .nr_tlb_entries = 32, | |
2568 | }; | |
2569 | ||
2570 | static struct omap_hwmod omap44xx_mmu_dsp_hwmod; | |
2571 | static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = { | |
2572 | { .irq = 28 + OMAP44XX_IRQ_GIC_START }, | |
2573 | { .irq = -1 } | |
2574 | }; | |
2575 | ||
2576 | static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = { | |
2577 | { .name = "mmu_cache", .rst_shift = 1 }, | |
2578 | }; | |
2579 | ||
2580 | static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = { | |
2581 | { | |
2582 | .pa_start = 0x4a066000, | |
2583 | .pa_end = 0x4a0660ff, | |
2584 | .flags = ADDR_TYPE_RT, | |
2585 | }, | |
2586 | { } | |
2587 | }; | |
2588 | ||
2589 | /* l4_cfg -> dsp */ | |
2590 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = { | |
2591 | .master = &omap44xx_l4_cfg_hwmod, | |
2592 | .slave = &omap44xx_mmu_dsp_hwmod, | |
2593 | .clk = "l4_div_ck", | |
2594 | .addr = omap44xx_mmu_dsp_addrs, | |
2595 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2596 | }; | |
2597 | ||
2598 | static struct omap_hwmod omap44xx_mmu_dsp_hwmod = { | |
2599 | .name = "mmu_dsp", | |
2600 | .class = &omap44xx_mmu_hwmod_class, | |
2601 | .clkdm_name = "tesla_clkdm", | |
2602 | .mpu_irqs = omap44xx_mmu_dsp_irqs, | |
2603 | .rst_lines = omap44xx_mmu_dsp_resets, | |
2604 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets), | |
2605 | .main_clk = "dpll_iva_m4x2_ck", | |
2606 | .prcm = { | |
2607 | .omap4 = { | |
2608 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, | |
2609 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, | |
2610 | .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, | |
2611 | .modulemode = MODULEMODE_HWCTRL, | |
2612 | }, | |
2613 | }, | |
2614 | .dev_attr = &mmu_dsp_dev_attr, | |
2615 | }; | |
2616 | ||
3b54baad BC |
2617 | /* |
2618 | * 'mpu' class | |
2619 | * mpu sub-system | |
2620 | */ | |
2621 | ||
2622 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { | |
fe13471c | 2623 | .name = "mpu", |
db12ba53 BC |
2624 | }; |
2625 | ||
3b54baad BC |
2626 | /* mpu */ |
2627 | static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { | |
76a5d9bf JH |
2628 | { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START }, |
2629 | { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START }, | |
3b54baad BC |
2630 | { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, |
2631 | { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, | |
2632 | { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2633 | { .irq = -1 } |
db12ba53 BC |
2634 | }; |
2635 | ||
3b54baad BC |
2636 | static struct omap_hwmod omap44xx_mpu_hwmod = { |
2637 | .name = "mpu", | |
2638 | .class = &omap44xx_mpu_hwmod_class, | |
a5322c6f | 2639 | .clkdm_name = "mpuss_clkdm", |
7ecc5373 | 2640 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
3b54baad | 2641 | .mpu_irqs = omap44xx_mpu_irqs, |
3b54baad | 2642 | .main_clk = "dpll_mpu_m2_ck", |
db12ba53 BC |
2643 | .prcm = { |
2644 | .omap4 = { | |
d0f0631d | 2645 | .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 2646 | .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, |
db12ba53 BC |
2647 | }, |
2648 | }, | |
db12ba53 BC |
2649 | }; |
2650 | ||
e17f18c0 PW |
2651 | /* |
2652 | * 'ocmc_ram' class | |
2653 | * top-level core on-chip ram | |
2654 | */ | |
2655 | ||
2656 | static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = { | |
2657 | .name = "ocmc_ram", | |
2658 | }; | |
2659 | ||
2660 | /* ocmc_ram */ | |
2661 | static struct omap_hwmod omap44xx_ocmc_ram_hwmod = { | |
2662 | .name = "ocmc_ram", | |
2663 | .class = &omap44xx_ocmc_ram_hwmod_class, | |
2664 | .clkdm_name = "l3_2_clkdm", | |
2665 | .prcm = { | |
2666 | .omap4 = { | |
2667 | .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET, | |
2668 | .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET, | |
2669 | }, | |
2670 | }, | |
2671 | }; | |
2672 | ||
0c668875 BC |
2673 | /* |
2674 | * 'ocp2scp' class | |
2675 | * bridge to transform ocp interface protocol to scp (serial control port) | |
2676 | * protocol | |
2677 | */ | |
2678 | ||
33c976ec BC |
2679 | static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = { |
2680 | .rev_offs = 0x0000, | |
2681 | .sysc_offs = 0x0010, | |
2682 | .syss_offs = 0x0014, | |
2683 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
2684 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
2685 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2686 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2687 | }; | |
2688 | ||
0c668875 BC |
2689 | static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = { |
2690 | .name = "ocp2scp", | |
33c976ec | 2691 | .sysc = &omap44xx_ocp2scp_sysc, |
0c668875 BC |
2692 | }; |
2693 | ||
637874dd KVA |
2694 | /* ocp2scp dev_attr */ |
2695 | static struct resource omap44xx_usb_phy_and_pll_addrs[] = { | |
2696 | { | |
2697 | .name = "usb_phy", | |
2698 | .start = 0x4a0ad080, | |
2699 | .end = 0x4a0ae000, | |
2700 | .flags = IORESOURCE_MEM, | |
2701 | }, | |
2702 | { | |
2703 | /* XXX: Remove this once control module driver is in place */ | |
2704 | .name = "ctrl_dev", | |
2705 | .start = 0x4a002300, | |
2706 | .end = 0x4a002303, | |
2707 | .flags = IORESOURCE_MEM, | |
2708 | }, | |
2709 | { } | |
2710 | }; | |
2711 | ||
2712 | static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = { | |
2713 | { | |
2714 | .drv_name = "omap-usb2", | |
2715 | .res = omap44xx_usb_phy_and_pll_addrs, | |
2716 | }, | |
2717 | { } | |
2718 | }; | |
2719 | ||
0c668875 | 2720 | /* ocp2scp_usb_phy */ |
0c668875 BC |
2721 | static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { |
2722 | .name = "ocp2scp_usb_phy", | |
2723 | .class = &omap44xx_ocp2scp_hwmod_class, | |
2724 | .clkdm_name = "l3_init_clkdm", | |
1b024d2f | 2725 | .main_clk = "ocp2scp_usb_phy_phy_48m", |
0c668875 BC |
2726 | .prcm = { |
2727 | .omap4 = { | |
2728 | .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, | |
2729 | .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET, | |
2730 | .modulemode = MODULEMODE_HWCTRL, | |
2731 | }, | |
2732 | }, | |
637874dd | 2733 | .dev_attr = ocp2scp_dev_attr, |
0c668875 BC |
2734 | }; |
2735 | ||
794b480a PW |
2736 | /* |
2737 | * 'prcm' class | |
2738 | * power and reset manager (part of the prcm infrastructure) + clock manager 2 | |
2739 | * + clock manager 1 (in always on power domain) + local prm in mpu | |
2740 | */ | |
2741 | ||
2742 | static struct omap_hwmod_class omap44xx_prcm_hwmod_class = { | |
2743 | .name = "prcm", | |
2744 | }; | |
2745 | ||
2746 | /* prcm_mpu */ | |
2747 | static struct omap_hwmod omap44xx_prcm_mpu_hwmod = { | |
2748 | .name = "prcm_mpu", | |
2749 | .class = &omap44xx_prcm_hwmod_class, | |
2750 | .clkdm_name = "l4_wkup_clkdm", | |
53cce97c | 2751 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
2752 | .prcm = { |
2753 | .omap4 = { | |
2754 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2755 | }, | |
2756 | }, | |
794b480a PW |
2757 | }; |
2758 | ||
2759 | /* cm_core_aon */ | |
2760 | static struct omap_hwmod omap44xx_cm_core_aon_hwmod = { | |
2761 | .name = "cm_core_aon", | |
2762 | .class = &omap44xx_prcm_hwmod_class, | |
53cce97c | 2763 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
2764 | .prcm = { |
2765 | .omap4 = { | |
2766 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2767 | }, | |
2768 | }, | |
794b480a PW |
2769 | }; |
2770 | ||
2771 | /* cm_core */ | |
2772 | static struct omap_hwmod omap44xx_cm_core_hwmod = { | |
2773 | .name = "cm_core", | |
2774 | .class = &omap44xx_prcm_hwmod_class, | |
53cce97c | 2775 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
2776 | .prcm = { |
2777 | .omap4 = { | |
2778 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2779 | }, | |
2780 | }, | |
794b480a PW |
2781 | }; |
2782 | ||
2783 | /* prm */ | |
2784 | static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = { | |
2785 | { .irq = 11 + OMAP44XX_IRQ_GIC_START }, | |
2786 | { .irq = -1 } | |
2787 | }; | |
2788 | ||
2789 | static struct omap_hwmod_rst_info omap44xx_prm_resets[] = { | |
2790 | { .name = "rst_global_warm_sw", .rst_shift = 0 }, | |
2791 | { .name = "rst_global_cold_sw", .rst_shift = 1 }, | |
2792 | }; | |
2793 | ||
2794 | static struct omap_hwmod omap44xx_prm_hwmod = { | |
2795 | .name = "prm", | |
2796 | .class = &omap44xx_prcm_hwmod_class, | |
794b480a PW |
2797 | .mpu_irqs = omap44xx_prm_irqs, |
2798 | .rst_lines = omap44xx_prm_resets, | |
2799 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets), | |
2800 | }; | |
2801 | ||
2802 | /* | |
2803 | * 'scrm' class | |
2804 | * system clock and reset manager | |
2805 | */ | |
2806 | ||
2807 | static struct omap_hwmod_class omap44xx_scrm_hwmod_class = { | |
2808 | .name = "scrm", | |
2809 | }; | |
2810 | ||
2811 | /* scrm */ | |
2812 | static struct omap_hwmod omap44xx_scrm_hwmod = { | |
2813 | .name = "scrm", | |
2814 | .class = &omap44xx_scrm_hwmod_class, | |
2815 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
2816 | .prcm = { |
2817 | .omap4 = { | |
2818 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2819 | }, | |
2820 | }, | |
794b480a PW |
2821 | }; |
2822 | ||
42b9e387 PW |
2823 | /* |
2824 | * 'sl2if' class | |
2825 | * shared level 2 memory interface | |
2826 | */ | |
2827 | ||
2828 | static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = { | |
2829 | .name = "sl2if", | |
2830 | }; | |
2831 | ||
2832 | /* sl2if */ | |
2833 | static struct omap_hwmod omap44xx_sl2if_hwmod = { | |
2834 | .name = "sl2if", | |
2835 | .class = &omap44xx_sl2if_hwmod_class, | |
2836 | .clkdm_name = "ivahd_clkdm", | |
2837 | .prcm = { | |
2838 | .omap4 = { | |
2839 | .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET, | |
2840 | .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET, | |
2841 | .modulemode = MODULEMODE_HWCTRL, | |
2842 | }, | |
2843 | }, | |
2844 | }; | |
2845 | ||
1e3b5e59 BC |
2846 | /* |
2847 | * 'slimbus' class | |
2848 | * bidirectional, multi-drop, multi-channel two-line serial interface between | |
2849 | * the device and external components | |
2850 | */ | |
2851 | ||
2852 | static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = { | |
2853 | .rev_offs = 0x0000, | |
2854 | .sysc_offs = 0x0010, | |
2855 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
2856 | SYSC_HAS_SOFTRESET), | |
2857 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2858 | SIDLE_SMART_WKUP), | |
2859 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2860 | }; | |
2861 | ||
2862 | static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = { | |
2863 | .name = "slimbus", | |
2864 | .sysc = &omap44xx_slimbus_sysc, | |
2865 | }; | |
2866 | ||
2867 | /* slimbus1 */ | |
2868 | static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = { | |
2869 | { .irq = 97 + OMAP44XX_IRQ_GIC_START }, | |
2870 | { .irq = -1 } | |
2871 | }; | |
2872 | ||
2873 | static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = { | |
2874 | { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START }, | |
2875 | { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START }, | |
2876 | { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START }, | |
2877 | { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START }, | |
2878 | { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START }, | |
2879 | { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START }, | |
2880 | { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START }, | |
2881 | { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START }, | |
2882 | { .dma_req = -1 } | |
2883 | }; | |
2884 | ||
2885 | static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = { | |
2886 | { .role = "fclk_1", .clk = "slimbus1_fclk_1" }, | |
2887 | { .role = "fclk_0", .clk = "slimbus1_fclk_0" }, | |
2888 | { .role = "fclk_2", .clk = "slimbus1_fclk_2" }, | |
2889 | { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" }, | |
2890 | }; | |
2891 | ||
2892 | static struct omap_hwmod omap44xx_slimbus1_hwmod = { | |
2893 | .name = "slimbus1", | |
2894 | .class = &omap44xx_slimbus_hwmod_class, | |
2895 | .clkdm_name = "abe_clkdm", | |
2896 | .mpu_irqs = omap44xx_slimbus1_irqs, | |
2897 | .sdma_reqs = omap44xx_slimbus1_sdma_reqs, | |
2898 | .prcm = { | |
2899 | .omap4 = { | |
2900 | .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET, | |
2901 | .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET, | |
2902 | .modulemode = MODULEMODE_SWCTRL, | |
2903 | }, | |
2904 | }, | |
2905 | .opt_clks = slimbus1_opt_clks, | |
2906 | .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks), | |
2907 | }; | |
2908 | ||
2909 | /* slimbus2 */ | |
2910 | static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = { | |
2911 | { .irq = 98 + OMAP44XX_IRQ_GIC_START }, | |
2912 | { .irq = -1 } | |
2913 | }; | |
2914 | ||
2915 | static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = { | |
2916 | { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START }, | |
2917 | { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START }, | |
2918 | { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START }, | |
2919 | { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START }, | |
2920 | { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START }, | |
2921 | { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START }, | |
2922 | { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START }, | |
2923 | { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START }, | |
2924 | { .dma_req = -1 } | |
2925 | }; | |
2926 | ||
2927 | static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = { | |
2928 | { .role = "fclk_1", .clk = "slimbus2_fclk_1" }, | |
2929 | { .role = "fclk_0", .clk = "slimbus2_fclk_0" }, | |
2930 | { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" }, | |
2931 | }; | |
2932 | ||
2933 | static struct omap_hwmod omap44xx_slimbus2_hwmod = { | |
2934 | .name = "slimbus2", | |
2935 | .class = &omap44xx_slimbus_hwmod_class, | |
2936 | .clkdm_name = "l4_per_clkdm", | |
2937 | .mpu_irqs = omap44xx_slimbus2_irqs, | |
2938 | .sdma_reqs = omap44xx_slimbus2_sdma_reqs, | |
2939 | .prcm = { | |
2940 | .omap4 = { | |
2941 | .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET, | |
2942 | .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET, | |
2943 | .modulemode = MODULEMODE_SWCTRL, | |
2944 | }, | |
2945 | }, | |
2946 | .opt_clks = slimbus2_opt_clks, | |
2947 | .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks), | |
2948 | }; | |
2949 | ||
1f6a717f BC |
2950 | /* |
2951 | * 'smartreflex' class | |
2952 | * smartreflex module (monitor silicon performance and outputs a measure of | |
2953 | * performance error) | |
2954 | */ | |
2955 | ||
2956 | /* The IP is not compliant to type1 / type2 scheme */ | |
2957 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { | |
2958 | .sidle_shift = 24, | |
2959 | .enwkup_shift = 26, | |
2960 | }; | |
2961 | ||
2962 | static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { | |
2963 | .sysc_offs = 0x0038, | |
2964 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), | |
2965 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2966 | SIDLE_SMART_WKUP), | |
2967 | .sysc_fields = &omap_hwmod_sysc_type_smartreflex, | |
2968 | }; | |
2969 | ||
2970 | static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { | |
fe13471c BC |
2971 | .name = "smartreflex", |
2972 | .sysc = &omap44xx_smartreflex_sysc, | |
2973 | .rev = 2, | |
1f6a717f BC |
2974 | }; |
2975 | ||
2976 | /* smartreflex_core */ | |
cea6b942 SG |
2977 | static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { |
2978 | .sensor_voltdm_name = "core", | |
2979 | }; | |
2980 | ||
1f6a717f BC |
2981 | static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { |
2982 | { .irq = 19 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2983 | { .irq = -1 } |
1f6a717f BC |
2984 | }; |
2985 | ||
1f6a717f BC |
2986 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { |
2987 | .name = "smartreflex_core", | |
2988 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2989 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2990 | .mpu_irqs = omap44xx_smartreflex_core_irqs, |
212738a4 | 2991 | |
1f6a717f | 2992 | .main_clk = "smartreflex_core_fck", |
1f6a717f BC |
2993 | .prcm = { |
2994 | .omap4 = { | |
d0f0631d | 2995 | .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET, |
27bb00b5 | 2996 | .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET, |
03fdefe5 | 2997 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2998 | }, |
2999 | }, | |
cea6b942 | 3000 | .dev_attr = &smartreflex_core_dev_attr, |
1f6a717f BC |
3001 | }; |
3002 | ||
3003 | /* smartreflex_iva */ | |
cea6b942 SG |
3004 | static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { |
3005 | .sensor_voltdm_name = "iva", | |
3006 | }; | |
3007 | ||
1f6a717f BC |
3008 | static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { |
3009 | { .irq = 102 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3010 | { .irq = -1 } |
1f6a717f BC |
3011 | }; |
3012 | ||
1f6a717f BC |
3013 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { |
3014 | .name = "smartreflex_iva", | |
3015 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 3016 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 3017 | .mpu_irqs = omap44xx_smartreflex_iva_irqs, |
1f6a717f | 3018 | .main_clk = "smartreflex_iva_fck", |
1f6a717f BC |
3019 | .prcm = { |
3020 | .omap4 = { | |
d0f0631d | 3021 | .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET, |
27bb00b5 | 3022 | .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET, |
03fdefe5 | 3023 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
3024 | }, |
3025 | }, | |
cea6b942 | 3026 | .dev_attr = &smartreflex_iva_dev_attr, |
1f6a717f BC |
3027 | }; |
3028 | ||
3029 | /* smartreflex_mpu */ | |
cea6b942 SG |
3030 | static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { |
3031 | .sensor_voltdm_name = "mpu", | |
3032 | }; | |
3033 | ||
1f6a717f BC |
3034 | static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { |
3035 | { .irq = 18 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3036 | { .irq = -1 } |
1f6a717f BC |
3037 | }; |
3038 | ||
1f6a717f BC |
3039 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { |
3040 | .name = "smartreflex_mpu", | |
3041 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 3042 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 3043 | .mpu_irqs = omap44xx_smartreflex_mpu_irqs, |
1f6a717f | 3044 | .main_clk = "smartreflex_mpu_fck", |
1f6a717f BC |
3045 | .prcm = { |
3046 | .omap4 = { | |
d0f0631d | 3047 | .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 3048 | .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET, |
03fdefe5 | 3049 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
3050 | }, |
3051 | }, | |
cea6b942 | 3052 | .dev_attr = &smartreflex_mpu_dev_attr, |
1f6a717f BC |
3053 | }; |
3054 | ||
d11c217f BC |
3055 | /* |
3056 | * 'spinlock' class | |
3057 | * spinlock provides hardware assistance for synchronizing the processes | |
3058 | * running on multiple processors | |
3059 | */ | |
3060 | ||
3061 | static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = { | |
3062 | .rev_offs = 0x0000, | |
3063 | .sysc_offs = 0x0010, | |
3064 | .syss_offs = 0x0014, | |
3065 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
3066 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
3067 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
3068 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3069 | SIDLE_SMART_WKUP), | |
3070 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3071 | }; | |
3072 | ||
3073 | static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { | |
3074 | .name = "spinlock", | |
3075 | .sysc = &omap44xx_spinlock_sysc, | |
3076 | }; | |
3077 | ||
3078 | /* spinlock */ | |
d11c217f BC |
3079 | static struct omap_hwmod omap44xx_spinlock_hwmod = { |
3080 | .name = "spinlock", | |
3081 | .class = &omap44xx_spinlock_hwmod_class, | |
a5322c6f | 3082 | .clkdm_name = "l4_cfg_clkdm", |
d11c217f BC |
3083 | .prcm = { |
3084 | .omap4 = { | |
d0f0631d | 3085 | .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET, |
27bb00b5 | 3086 | .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, |
d11c217f BC |
3087 | }, |
3088 | }, | |
d11c217f BC |
3089 | }; |
3090 | ||
35d1a66a BC |
3091 | /* |
3092 | * 'timer' class | |
3093 | * general purpose timer module with accurate 1ms tick | |
3094 | * This class contains several variants: ['timer_1ms', 'timer'] | |
3095 | */ | |
3096 | ||
3097 | static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = { | |
3098 | .rev_offs = 0x0000, | |
3099 | .sysc_offs = 0x0010, | |
3100 | .syss_offs = 0x0014, | |
3101 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
3102 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
3103 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
3104 | SYSS_HAS_RESET_STATUS), | |
3105 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
10759e82 | 3106 | .clockact = CLOCKACT_TEST_ICLK, |
35d1a66a BC |
3107 | .sysc_fields = &omap_hwmod_sysc_type1, |
3108 | }; | |
3109 | ||
3110 | static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = { | |
3111 | .name = "timer", | |
3112 | .sysc = &omap44xx_timer_1ms_sysc, | |
3113 | }; | |
3114 | ||
3115 | static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = { | |
3116 | .rev_offs = 0x0000, | |
3117 | .sysc_offs = 0x0010, | |
3118 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
3119 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
3120 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3121 | SIDLE_SMART_WKUP), | |
3122 | .sysc_fields = &omap_hwmod_sysc_type2, | |
3123 | }; | |
3124 | ||
3125 | static struct omap_hwmod_class omap44xx_timer_hwmod_class = { | |
3126 | .name = "timer", | |
3127 | .sysc = &omap44xx_timer_sysc, | |
3128 | }; | |
3129 | ||
c345c8b0 TKD |
3130 | /* always-on timers dev attribute */ |
3131 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
3132 | .timer_capability = OMAP_TIMER_ALWON, | |
3133 | }; | |
3134 | ||
3135 | /* pwm timers dev attribute */ | |
3136 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
3137 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
3138 | }; | |
3139 | ||
5c3e4ec4 JH |
3140 | /* timers with DSP interrupt dev attribute */ |
3141 | static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = { | |
3142 | .timer_capability = OMAP_TIMER_HAS_DSP_IRQ, | |
3143 | }; | |
3144 | ||
3145 | /* pwm timers with DSP interrupt dev attribute */ | |
3146 | static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = { | |
3147 | .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM, | |
3148 | }; | |
3149 | ||
35d1a66a | 3150 | /* timer1 */ |
35d1a66a BC |
3151 | static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { |
3152 | { .irq = 37 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3153 | { .irq = -1 } |
35d1a66a BC |
3154 | }; |
3155 | ||
35d1a66a BC |
3156 | static struct omap_hwmod omap44xx_timer1_hwmod = { |
3157 | .name = "timer1", | |
3158 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 3159 | .clkdm_name = "l4_wkup_clkdm", |
10759e82 | 3160 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
35d1a66a | 3161 | .mpu_irqs = omap44xx_timer1_irqs, |
35d1a66a BC |
3162 | .main_clk = "timer1_fck", |
3163 | .prcm = { | |
3164 | .omap4 = { | |
d0f0631d | 3165 | .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, |
27bb00b5 | 3166 | .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET, |
03fdefe5 | 3167 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3168 | }, |
3169 | }, | |
c345c8b0 | 3170 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
3171 | }; |
3172 | ||
3173 | /* timer2 */ | |
35d1a66a BC |
3174 | static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { |
3175 | { .irq = 38 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3176 | { .irq = -1 } |
35d1a66a BC |
3177 | }; |
3178 | ||
35d1a66a BC |
3179 | static struct omap_hwmod omap44xx_timer2_hwmod = { |
3180 | .name = "timer2", | |
3181 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 3182 | .clkdm_name = "l4_per_clkdm", |
10759e82 | 3183 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
35d1a66a | 3184 | .mpu_irqs = omap44xx_timer2_irqs, |
35d1a66a BC |
3185 | .main_clk = "timer2_fck", |
3186 | .prcm = { | |
3187 | .omap4 = { | |
d0f0631d | 3188 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, |
27bb00b5 | 3189 | .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET, |
03fdefe5 | 3190 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3191 | }, |
3192 | }, | |
35d1a66a BC |
3193 | }; |
3194 | ||
3195 | /* timer3 */ | |
35d1a66a BC |
3196 | static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { |
3197 | { .irq = 39 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3198 | { .irq = -1 } |
35d1a66a BC |
3199 | }; |
3200 | ||
35d1a66a BC |
3201 | static struct omap_hwmod omap44xx_timer3_hwmod = { |
3202 | .name = "timer3", | |
3203 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3204 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 3205 | .mpu_irqs = omap44xx_timer3_irqs, |
35d1a66a BC |
3206 | .main_clk = "timer3_fck", |
3207 | .prcm = { | |
3208 | .omap4 = { | |
d0f0631d | 3209 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, |
27bb00b5 | 3210 | .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET, |
03fdefe5 | 3211 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3212 | }, |
3213 | }, | |
35d1a66a BC |
3214 | }; |
3215 | ||
3216 | /* timer4 */ | |
35d1a66a BC |
3217 | static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { |
3218 | { .irq = 40 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3219 | { .irq = -1 } |
35d1a66a BC |
3220 | }; |
3221 | ||
35d1a66a BC |
3222 | static struct omap_hwmod omap44xx_timer4_hwmod = { |
3223 | .name = "timer4", | |
3224 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3225 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 3226 | .mpu_irqs = omap44xx_timer4_irqs, |
35d1a66a BC |
3227 | .main_clk = "timer4_fck", |
3228 | .prcm = { | |
3229 | .omap4 = { | |
d0f0631d | 3230 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, |
27bb00b5 | 3231 | .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET, |
03fdefe5 | 3232 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3233 | }, |
3234 | }, | |
35d1a66a BC |
3235 | }; |
3236 | ||
3237 | /* timer5 */ | |
35d1a66a BC |
3238 | static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { |
3239 | { .irq = 41 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3240 | { .irq = -1 } |
35d1a66a BC |
3241 | }; |
3242 | ||
35d1a66a BC |
3243 | static struct omap_hwmod omap44xx_timer5_hwmod = { |
3244 | .name = "timer5", | |
3245 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3246 | .clkdm_name = "abe_clkdm", |
35d1a66a | 3247 | .mpu_irqs = omap44xx_timer5_irqs, |
35d1a66a BC |
3248 | .main_clk = "timer5_fck", |
3249 | .prcm = { | |
3250 | .omap4 = { | |
d0f0631d | 3251 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, |
27bb00b5 | 3252 | .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET, |
03fdefe5 | 3253 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3254 | }, |
3255 | }, | |
5c3e4ec4 | 3256 | .dev_attr = &capability_dsp_dev_attr, |
35d1a66a BC |
3257 | }; |
3258 | ||
3259 | /* timer6 */ | |
35d1a66a BC |
3260 | static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { |
3261 | { .irq = 42 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3262 | { .irq = -1 } |
35d1a66a BC |
3263 | }; |
3264 | ||
35d1a66a BC |
3265 | static struct omap_hwmod omap44xx_timer6_hwmod = { |
3266 | .name = "timer6", | |
3267 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3268 | .clkdm_name = "abe_clkdm", |
35d1a66a | 3269 | .mpu_irqs = omap44xx_timer6_irqs, |
212738a4 | 3270 | |
35d1a66a BC |
3271 | .main_clk = "timer6_fck", |
3272 | .prcm = { | |
3273 | .omap4 = { | |
d0f0631d | 3274 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, |
27bb00b5 | 3275 | .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET, |
03fdefe5 | 3276 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3277 | }, |
3278 | }, | |
5c3e4ec4 | 3279 | .dev_attr = &capability_dsp_dev_attr, |
35d1a66a BC |
3280 | }; |
3281 | ||
3282 | /* timer7 */ | |
35d1a66a BC |
3283 | static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { |
3284 | { .irq = 43 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3285 | { .irq = -1 } |
35d1a66a BC |
3286 | }; |
3287 | ||
35d1a66a BC |
3288 | static struct omap_hwmod omap44xx_timer7_hwmod = { |
3289 | .name = "timer7", | |
3290 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3291 | .clkdm_name = "abe_clkdm", |
35d1a66a | 3292 | .mpu_irqs = omap44xx_timer7_irqs, |
35d1a66a BC |
3293 | .main_clk = "timer7_fck", |
3294 | .prcm = { | |
3295 | .omap4 = { | |
d0f0631d | 3296 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, |
27bb00b5 | 3297 | .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET, |
03fdefe5 | 3298 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3299 | }, |
3300 | }, | |
5c3e4ec4 | 3301 | .dev_attr = &capability_dsp_dev_attr, |
35d1a66a BC |
3302 | }; |
3303 | ||
3304 | /* timer8 */ | |
35d1a66a BC |
3305 | static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { |
3306 | { .irq = 44 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3307 | { .irq = -1 } |
35d1a66a BC |
3308 | }; |
3309 | ||
35d1a66a BC |
3310 | static struct omap_hwmod omap44xx_timer8_hwmod = { |
3311 | .name = "timer8", | |
3312 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3313 | .clkdm_name = "abe_clkdm", |
35d1a66a | 3314 | .mpu_irqs = omap44xx_timer8_irqs, |
35d1a66a BC |
3315 | .main_clk = "timer8_fck", |
3316 | .prcm = { | |
3317 | .omap4 = { | |
d0f0631d | 3318 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, |
27bb00b5 | 3319 | .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET, |
03fdefe5 | 3320 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3321 | }, |
3322 | }, | |
5c3e4ec4 | 3323 | .dev_attr = &capability_dsp_pwm_dev_attr, |
35d1a66a BC |
3324 | }; |
3325 | ||
3326 | /* timer9 */ | |
35d1a66a BC |
3327 | static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { |
3328 | { .irq = 45 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3329 | { .irq = -1 } |
35d1a66a BC |
3330 | }; |
3331 | ||
35d1a66a BC |
3332 | static struct omap_hwmod omap44xx_timer9_hwmod = { |
3333 | .name = "timer9", | |
3334 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3335 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 3336 | .mpu_irqs = omap44xx_timer9_irqs, |
35d1a66a BC |
3337 | .main_clk = "timer9_fck", |
3338 | .prcm = { | |
3339 | .omap4 = { | |
d0f0631d | 3340 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, |
27bb00b5 | 3341 | .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET, |
03fdefe5 | 3342 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3343 | }, |
3344 | }, | |
c345c8b0 | 3345 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
3346 | }; |
3347 | ||
3348 | /* timer10 */ | |
35d1a66a BC |
3349 | static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { |
3350 | { .irq = 46 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3351 | { .irq = -1 } |
35d1a66a BC |
3352 | }; |
3353 | ||
35d1a66a BC |
3354 | static struct omap_hwmod omap44xx_timer10_hwmod = { |
3355 | .name = "timer10", | |
3356 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 3357 | .clkdm_name = "l4_per_clkdm", |
10759e82 | 3358 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
35d1a66a | 3359 | .mpu_irqs = omap44xx_timer10_irqs, |
35d1a66a BC |
3360 | .main_clk = "timer10_fck", |
3361 | .prcm = { | |
3362 | .omap4 = { | |
d0f0631d | 3363 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, |
27bb00b5 | 3364 | .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET, |
03fdefe5 | 3365 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3366 | }, |
3367 | }, | |
c345c8b0 | 3368 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
3369 | }; |
3370 | ||
3371 | /* timer11 */ | |
35d1a66a BC |
3372 | static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { |
3373 | { .irq = 47 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3374 | { .irq = -1 } |
35d1a66a BC |
3375 | }; |
3376 | ||
35d1a66a BC |
3377 | static struct omap_hwmod omap44xx_timer11_hwmod = { |
3378 | .name = "timer11", | |
3379 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3380 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 3381 | .mpu_irqs = omap44xx_timer11_irqs, |
35d1a66a BC |
3382 | .main_clk = "timer11_fck", |
3383 | .prcm = { | |
3384 | .omap4 = { | |
d0f0631d | 3385 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, |
27bb00b5 | 3386 | .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET, |
03fdefe5 | 3387 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3388 | }, |
3389 | }, | |
c345c8b0 | 3390 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
3391 | }; |
3392 | ||
9780a9cf | 3393 | /* |
3b54baad BC |
3394 | * 'uart' class |
3395 | * universal asynchronous receiver/transmitter (uart) | |
9780a9cf BC |
3396 | */ |
3397 | ||
3b54baad BC |
3398 | static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { |
3399 | .rev_offs = 0x0050, | |
3400 | .sysc_offs = 0x0054, | |
3401 | .syss_offs = 0x0058, | |
3402 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
0cfe8751 BC |
3403 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
3404 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
3405 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3406 | SIDLE_SMART_WKUP), | |
9780a9cf BC |
3407 | .sysc_fields = &omap_hwmod_sysc_type1, |
3408 | }; | |
3409 | ||
3b54baad | 3410 | static struct omap_hwmod_class omap44xx_uart_hwmod_class = { |
fe13471c BC |
3411 | .name = "uart", |
3412 | .sysc = &omap44xx_uart_sysc, | |
9780a9cf BC |
3413 | }; |
3414 | ||
3b54baad | 3415 | /* uart1 */ |
3b54baad BC |
3416 | static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { |
3417 | { .irq = 72 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3418 | { .irq = -1 } |
9780a9cf BC |
3419 | }; |
3420 | ||
3b54baad BC |
3421 | static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { |
3422 | { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, | |
3423 | { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3424 | { .dma_req = -1 } |
9780a9cf BC |
3425 | }; |
3426 | ||
3b54baad BC |
3427 | static struct omap_hwmod omap44xx_uart1_hwmod = { |
3428 | .name = "uart1", | |
3429 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3430 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 3431 | .mpu_irqs = omap44xx_uart1_irqs, |
3b54baad | 3432 | .sdma_reqs = omap44xx_uart1_sdma_reqs, |
3b54baad | 3433 | .main_clk = "uart1_fck", |
9780a9cf BC |
3434 | .prcm = { |
3435 | .omap4 = { | |
d0f0631d | 3436 | .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET, |
27bb00b5 | 3437 | .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET, |
03fdefe5 | 3438 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3439 | }, |
3440 | }, | |
9780a9cf BC |
3441 | }; |
3442 | ||
3b54baad | 3443 | /* uart2 */ |
3b54baad BC |
3444 | static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { |
3445 | { .irq = 73 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3446 | { .irq = -1 } |
9780a9cf BC |
3447 | }; |
3448 | ||
3b54baad BC |
3449 | static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { |
3450 | { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, | |
3451 | { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3452 | { .dma_req = -1 } |
3b54baad BC |
3453 | }; |
3454 | ||
3b54baad BC |
3455 | static struct omap_hwmod omap44xx_uart2_hwmod = { |
3456 | .name = "uart2", | |
3457 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3458 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 3459 | .mpu_irqs = omap44xx_uart2_irqs, |
3b54baad | 3460 | .sdma_reqs = omap44xx_uart2_sdma_reqs, |
3b54baad | 3461 | .main_clk = "uart2_fck", |
9780a9cf BC |
3462 | .prcm = { |
3463 | .omap4 = { | |
d0f0631d | 3464 | .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET, |
27bb00b5 | 3465 | .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET, |
03fdefe5 | 3466 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3467 | }, |
3468 | }, | |
9780a9cf BC |
3469 | }; |
3470 | ||
3b54baad | 3471 | /* uart3 */ |
3b54baad BC |
3472 | static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { |
3473 | { .irq = 74 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3474 | { .irq = -1 } |
9780a9cf BC |
3475 | }; |
3476 | ||
3b54baad BC |
3477 | static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { |
3478 | { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, | |
3479 | { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3480 | { .dma_req = -1 } |
3b54baad BC |
3481 | }; |
3482 | ||
3b54baad BC |
3483 | static struct omap_hwmod omap44xx_uart3_hwmod = { |
3484 | .name = "uart3", | |
3485 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3486 | .clkdm_name = "l4_per_clkdm", |
7ecc5373 | 3487 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
3b54baad | 3488 | .mpu_irqs = omap44xx_uart3_irqs, |
3b54baad | 3489 | .sdma_reqs = omap44xx_uart3_sdma_reqs, |
3b54baad | 3490 | .main_clk = "uart3_fck", |
9780a9cf BC |
3491 | .prcm = { |
3492 | .omap4 = { | |
d0f0631d | 3493 | .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET, |
27bb00b5 | 3494 | .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET, |
03fdefe5 | 3495 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3496 | }, |
3497 | }, | |
9780a9cf BC |
3498 | }; |
3499 | ||
3b54baad | 3500 | /* uart4 */ |
3b54baad BC |
3501 | static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { |
3502 | { .irq = 70 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3503 | { .irq = -1 } |
9780a9cf BC |
3504 | }; |
3505 | ||
3b54baad BC |
3506 | static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { |
3507 | { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, | |
3508 | { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3509 | { .dma_req = -1 } |
3b54baad BC |
3510 | }; |
3511 | ||
3b54baad BC |
3512 | static struct omap_hwmod omap44xx_uart4_hwmod = { |
3513 | .name = "uart4", | |
3514 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3515 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 3516 | .mpu_irqs = omap44xx_uart4_irqs, |
3b54baad | 3517 | .sdma_reqs = omap44xx_uart4_sdma_reqs, |
3b54baad | 3518 | .main_clk = "uart4_fck", |
9780a9cf BC |
3519 | .prcm = { |
3520 | .omap4 = { | |
d0f0631d | 3521 | .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET, |
27bb00b5 | 3522 | .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET, |
03fdefe5 | 3523 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3524 | }, |
3525 | }, | |
9780a9cf BC |
3526 | }; |
3527 | ||
0c668875 BC |
3528 | /* |
3529 | * 'usb_host_fs' class | |
3530 | * full-speed usb host controller | |
3531 | */ | |
3532 | ||
3533 | /* The IP is not compliant to type1 / type2 scheme */ | |
3534 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = { | |
3535 | .midle_shift = 4, | |
3536 | .sidle_shift = 2, | |
3537 | .srst_shift = 1, | |
3538 | }; | |
3539 | ||
3540 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = { | |
3541 | .rev_offs = 0x0000, | |
3542 | .sysc_offs = 0x0210, | |
3543 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
3544 | SYSC_HAS_SOFTRESET), | |
3545 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3546 | SIDLE_SMART_WKUP), | |
3547 | .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs, | |
3548 | }; | |
3549 | ||
3550 | static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = { | |
3551 | .name = "usb_host_fs", | |
3552 | .sysc = &omap44xx_usb_host_fs_sysc, | |
3553 | }; | |
3554 | ||
3555 | /* usb_host_fs */ | |
3556 | static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = { | |
3557 | { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START }, | |
3558 | { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START }, | |
3559 | { .irq = -1 } | |
3560 | }; | |
3561 | ||
3562 | static struct omap_hwmod omap44xx_usb_host_fs_hwmod = { | |
3563 | .name = "usb_host_fs", | |
3564 | .class = &omap44xx_usb_host_fs_hwmod_class, | |
3565 | .clkdm_name = "l3_init_clkdm", | |
3566 | .mpu_irqs = omap44xx_usb_host_fs_irqs, | |
3567 | .main_clk = "usb_host_fs_fck", | |
3568 | .prcm = { | |
3569 | .omap4 = { | |
3570 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET, | |
3571 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET, | |
3572 | .modulemode = MODULEMODE_SWCTRL, | |
3573 | }, | |
3574 | }, | |
3575 | }; | |
3576 | ||
5844c4ea | 3577 | /* |
844a3b63 PW |
3578 | * 'usb_host_hs' class |
3579 | * high-speed multi-port usb host controller | |
5844c4ea BC |
3580 | */ |
3581 | ||
844a3b63 PW |
3582 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { |
3583 | .rev_offs = 0x0000, | |
3584 | .sysc_offs = 0x0010, | |
3585 | .syss_offs = 0x0014, | |
3586 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
3587 | SYSC_HAS_SOFTRESET), | |
5844c4ea BC |
3588 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3589 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
844a3b63 PW |
3590 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
3591 | .sysc_fields = &omap_hwmod_sysc_type2, | |
5844c4ea BC |
3592 | }; |
3593 | ||
844a3b63 PW |
3594 | static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { |
3595 | .name = "usb_host_hs", | |
3596 | .sysc = &omap44xx_usb_host_hs_sysc, | |
5844c4ea BC |
3597 | }; |
3598 | ||
844a3b63 PW |
3599 | /* usb_host_hs */ |
3600 | static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { | |
3601 | { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, | |
3602 | { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3603 | { .irq = -1 } |
5844c4ea BC |
3604 | }; |
3605 | ||
844a3b63 PW |
3606 | static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { |
3607 | .name = "usb_host_hs", | |
3608 | .class = &omap44xx_usb_host_hs_hwmod_class, | |
a5322c6f | 3609 | .clkdm_name = "l3_init_clkdm", |
844a3b63 | 3610 | .main_clk = "usb_host_hs_fck", |
5844c4ea BC |
3611 | .prcm = { |
3612 | .omap4 = { | |
844a3b63 PW |
3613 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, |
3614 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, | |
3615 | .modulemode = MODULEMODE_SWCTRL, | |
3616 | }, | |
3617 | }, | |
3618 | .mpu_irqs = omap44xx_usb_host_hs_irqs, | |
3619 | ||
3620 | /* | |
3621 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
3622 | * id: i660 | |
3623 | * | |
3624 | * Description: | |
3625 | * In the following configuration : | |
3626 | * - USBHOST module is set to smart-idle mode | |
3627 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
3628 | * happens when the system is going to a low power mode : all ports | |
3629 | * have been suspended, the master part of the USBHOST module has | |
3630 | * entered the standby state, and SW has cut the functional clocks) | |
3631 | * - an USBHOST interrupt occurs before the module is able to answer | |
3632 | * idle_ack, typically a remote wakeup IRQ. | |
3633 | * Then the USB HOST module will enter a deadlock situation where it | |
3634 | * is no more accessible nor functional. | |
3635 | * | |
3636 | * Workaround: | |
3637 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
3638 | */ | |
3639 | ||
3640 | /* | |
3641 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
3642 | * Id: i571 | |
3643 | * | |
3644 | * Description: | |
3645 | * When the USBHOST module is set to smart-standby mode, and when it is | |
3646 | * ready to enter the standby state (i.e. all ports are suspended and | |
3647 | * all attached devices are in suspend mode), then it can wrongly assert | |
3648 | * the Mstandby signal too early while there are still some residual OCP | |
3649 | * transactions ongoing. If this condition occurs, the internal state | |
3650 | * machine may go to an undefined state and the USB link may be stuck | |
3651 | * upon the next resume. | |
3652 | * | |
3653 | * Workaround: | |
3654 | * Don't use smart standby; use only force standby, | |
3655 | * hence HWMOD_SWSUP_MSTANDBY | |
3656 | */ | |
3657 | ||
3658 | /* | |
3659 | * During system boot; If the hwmod framework resets the module | |
3660 | * the module will have smart idle settings; which can lead to deadlock | |
3661 | * (above Errata Id:i660); so, dont reset the module during boot; | |
3662 | * Use HWMOD_INIT_NO_RESET. | |
3663 | */ | |
3664 | ||
3665 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | | |
3666 | HWMOD_INIT_NO_RESET, | |
3667 | }; | |
3668 | ||
3669 | /* | |
3670 | * 'usb_otg_hs' class | |
3671 | * high-speed on-the-go universal serial bus (usb_otg_hs) controller | |
3672 | */ | |
3673 | ||
3674 | static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { | |
3675 | .rev_offs = 0x0400, | |
3676 | .sysc_offs = 0x0404, | |
3677 | .syss_offs = 0x0408, | |
3678 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
3679 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
3680 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
3681 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3682 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
3683 | MSTANDBY_SMART), | |
3684 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3685 | }; | |
3686 | ||
3687 | static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { | |
3688 | .name = "usb_otg_hs", | |
3689 | .sysc = &omap44xx_usb_otg_hs_sysc, | |
3690 | }; | |
3691 | ||
3692 | /* usb_otg_hs */ | |
3693 | static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { | |
3694 | { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, | |
3695 | { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, | |
3696 | { .irq = -1 } | |
3697 | }; | |
3698 | ||
3699 | static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { | |
3700 | { .role = "xclk", .clk = "usb_otg_hs_xclk" }, | |
3701 | }; | |
3702 | ||
3703 | static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { | |
3704 | .name = "usb_otg_hs", | |
3705 | .class = &omap44xx_usb_otg_hs_hwmod_class, | |
3706 | .clkdm_name = "l3_init_clkdm", | |
3707 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | |
3708 | .mpu_irqs = omap44xx_usb_otg_hs_irqs, | |
3709 | .main_clk = "usb_otg_hs_ick", | |
3710 | .prcm = { | |
3711 | .omap4 = { | |
3712 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET, | |
3713 | .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET, | |
3714 | .modulemode = MODULEMODE_HWCTRL, | |
3715 | }, | |
3716 | }, | |
3717 | .opt_clks = usb_otg_hs_opt_clks, | |
3718 | .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), | |
3719 | }; | |
3720 | ||
3721 | /* | |
3722 | * 'usb_tll_hs' class | |
3723 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
3724 | */ | |
3725 | ||
3726 | static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { | |
3727 | .rev_offs = 0x0000, | |
3728 | .sysc_offs = 0x0010, | |
3729 | .syss_offs = 0x0014, | |
3730 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
3731 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
3732 | SYSC_HAS_AUTOIDLE), | |
3733 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
3734 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3735 | }; | |
3736 | ||
3737 | static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { | |
3738 | .name = "usb_tll_hs", | |
3739 | .sysc = &omap44xx_usb_tll_hs_sysc, | |
3740 | }; | |
3741 | ||
3742 | static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { | |
3743 | { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, | |
3744 | { .irq = -1 } | |
3745 | }; | |
3746 | ||
3747 | static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { | |
3748 | .name = "usb_tll_hs", | |
3749 | .class = &omap44xx_usb_tll_hs_hwmod_class, | |
3750 | .clkdm_name = "l3_init_clkdm", | |
3751 | .mpu_irqs = omap44xx_usb_tll_hs_irqs, | |
3752 | .main_clk = "usb_tll_hs_ick", | |
3753 | .prcm = { | |
3754 | .omap4 = { | |
3755 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, | |
3756 | .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, | |
3757 | .modulemode = MODULEMODE_HWCTRL, | |
5844c4ea BC |
3758 | }, |
3759 | }, | |
5844c4ea BC |
3760 | }; |
3761 | ||
3b54baad BC |
3762 | /* |
3763 | * 'wd_timer' class | |
3764 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
3765 | * overflow condition | |
3766 | */ | |
3767 | ||
3768 | static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { | |
3769 | .rev_offs = 0x0000, | |
3770 | .sysc_offs = 0x0010, | |
3771 | .syss_offs = 0x0014, | |
3772 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 3773 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
3774 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3775 | SIDLE_SMART_WKUP), | |
3b54baad | 3776 | .sysc_fields = &omap_hwmod_sysc_type1, |
9780a9cf BC |
3777 | }; |
3778 | ||
3b54baad BC |
3779 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { |
3780 | .name = "wd_timer", | |
3781 | .sysc = &omap44xx_wd_timer_sysc, | |
fe13471c | 3782 | .pre_shutdown = &omap2_wd_timer_disable, |
414e4128 | 3783 | .reset = &omap2_wd_timer_reset, |
3b54baad BC |
3784 | }; |
3785 | ||
3786 | /* wd_timer2 */ | |
3b54baad BC |
3787 | static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { |
3788 | { .irq = 80 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3789 | { .irq = -1 } |
3b54baad BC |
3790 | }; |
3791 | ||
3b54baad BC |
3792 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { |
3793 | .name = "wd_timer2", | |
3794 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 3795 | .clkdm_name = "l4_wkup_clkdm", |
3b54baad | 3796 | .mpu_irqs = omap44xx_wd_timer2_irqs, |
3b54baad | 3797 | .main_clk = "wd_timer2_fck", |
9780a9cf BC |
3798 | .prcm = { |
3799 | .omap4 = { | |
d0f0631d | 3800 | .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, |
27bb00b5 | 3801 | .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET, |
03fdefe5 | 3802 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3803 | }, |
3804 | }, | |
9780a9cf BC |
3805 | }; |
3806 | ||
3b54baad | 3807 | /* wd_timer3 */ |
3b54baad BC |
3808 | static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { |
3809 | { .irq = 36 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3810 | { .irq = -1 } |
9780a9cf BC |
3811 | }; |
3812 | ||
3b54baad BC |
3813 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { |
3814 | .name = "wd_timer3", | |
3815 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 3816 | .clkdm_name = "abe_clkdm", |
3b54baad | 3817 | .mpu_irqs = omap44xx_wd_timer3_irqs, |
3b54baad | 3818 | .main_clk = "wd_timer3_fck", |
9780a9cf BC |
3819 | .prcm = { |
3820 | .omap4 = { | |
d0f0631d | 3821 | .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, |
27bb00b5 | 3822 | .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET, |
03fdefe5 | 3823 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3824 | }, |
3825 | }, | |
9780a9cf | 3826 | }; |
531ce0d5 | 3827 | |
844a3b63 | 3828 | |
af88fa9a | 3829 | /* |
844a3b63 | 3830 | * interfaces |
af88fa9a | 3831 | */ |
af88fa9a | 3832 | |
42b9e387 PW |
3833 | static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = { |
3834 | { | |
3835 | .pa_start = 0x4a204000, | |
3836 | .pa_end = 0x4a2040ff, | |
3837 | .flags = ADDR_TYPE_RT | |
3838 | }, | |
3839 | { } | |
3840 | }; | |
3841 | ||
3842 | /* c2c -> c2c_target_fw */ | |
3843 | static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = { | |
3844 | .master = &omap44xx_c2c_hwmod, | |
3845 | .slave = &omap44xx_c2c_target_fw_hwmod, | |
3846 | .clk = "div_core_ck", | |
3847 | .addr = omap44xx_c2c_target_fw_addrs, | |
3848 | .user = OCP_USER_MPU, | |
3849 | }; | |
3850 | ||
3851 | /* l4_cfg -> c2c_target_fw */ | |
3852 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = { | |
3853 | .master = &omap44xx_l4_cfg_hwmod, | |
3854 | .slave = &omap44xx_c2c_target_fw_hwmod, | |
3855 | .clk = "l4_div_ck", | |
3856 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3857 | }; | |
3858 | ||
844a3b63 PW |
3859 | /* l3_main_1 -> dmm */ |
3860 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { | |
3861 | .master = &omap44xx_l3_main_1_hwmod, | |
3862 | .slave = &omap44xx_dmm_hwmod, | |
3863 | .clk = "l3_div_ck", | |
3864 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
3865 | }; |
3866 | ||
844a3b63 | 3867 | static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { |
af88fa9a | 3868 | { |
844a3b63 PW |
3869 | .pa_start = 0x4e000000, |
3870 | .pa_end = 0x4e0007ff, | |
af88fa9a BC |
3871 | .flags = ADDR_TYPE_RT |
3872 | }, | |
844a3b63 | 3873 | { } |
af88fa9a BC |
3874 | }; |
3875 | ||
844a3b63 PW |
3876 | /* mpu -> dmm */ |
3877 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { | |
3878 | .master = &omap44xx_mpu_hwmod, | |
3879 | .slave = &omap44xx_dmm_hwmod, | |
3880 | .clk = "l3_div_ck", | |
3881 | .addr = omap44xx_dmm_addrs, | |
3882 | .user = OCP_USER_MPU, | |
af88fa9a BC |
3883 | }; |
3884 | ||
42b9e387 PW |
3885 | /* c2c -> emif_fw */ |
3886 | static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = { | |
3887 | .master = &omap44xx_c2c_hwmod, | |
3888 | .slave = &omap44xx_emif_fw_hwmod, | |
3889 | .clk = "div_core_ck", | |
3890 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3891 | }; | |
3892 | ||
844a3b63 PW |
3893 | /* dmm -> emif_fw */ |
3894 | static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { | |
3895 | .master = &omap44xx_dmm_hwmod, | |
3896 | .slave = &omap44xx_emif_fw_hwmod, | |
3897 | .clk = "l3_div_ck", | |
3898 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3899 | }; | |
3900 | ||
3901 | static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { | |
3902 | { | |
3903 | .pa_start = 0x4a20c000, | |
3904 | .pa_end = 0x4a20c0ff, | |
3905 | .flags = ADDR_TYPE_RT | |
3906 | }, | |
3907 | { } | |
3908 | }; | |
3909 | ||
3910 | /* l4_cfg -> emif_fw */ | |
3911 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { | |
3912 | .master = &omap44xx_l4_cfg_hwmod, | |
3913 | .slave = &omap44xx_emif_fw_hwmod, | |
3914 | .clk = "l4_div_ck", | |
3915 | .addr = omap44xx_emif_fw_addrs, | |
3916 | .user = OCP_USER_MPU, | |
3917 | }; | |
3918 | ||
3919 | /* iva -> l3_instr */ | |
3920 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { | |
3921 | .master = &omap44xx_iva_hwmod, | |
3922 | .slave = &omap44xx_l3_instr_hwmod, | |
3923 | .clk = "l3_div_ck", | |
3924 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3925 | }; | |
3926 | ||
3927 | /* l3_main_3 -> l3_instr */ | |
3928 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { | |
3929 | .master = &omap44xx_l3_main_3_hwmod, | |
3930 | .slave = &omap44xx_l3_instr_hwmod, | |
3931 | .clk = "l3_div_ck", | |
3932 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3933 | }; | |
3934 | ||
9a817bc8 BC |
3935 | /* ocp_wp_noc -> l3_instr */ |
3936 | static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = { | |
3937 | .master = &omap44xx_ocp_wp_noc_hwmod, | |
3938 | .slave = &omap44xx_l3_instr_hwmod, | |
3939 | .clk = "l3_div_ck", | |
3940 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3941 | }; | |
3942 | ||
844a3b63 PW |
3943 | /* dsp -> l3_main_1 */ |
3944 | static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { | |
3945 | .master = &omap44xx_dsp_hwmod, | |
3946 | .slave = &omap44xx_l3_main_1_hwmod, | |
3947 | .clk = "l3_div_ck", | |
3948 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3949 | }; | |
3950 | ||
3951 | /* dss -> l3_main_1 */ | |
3952 | static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { | |
3953 | .master = &omap44xx_dss_hwmod, | |
3954 | .slave = &omap44xx_l3_main_1_hwmod, | |
3955 | .clk = "l3_div_ck", | |
3956 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3957 | }; | |
3958 | ||
3959 | /* l3_main_2 -> l3_main_1 */ | |
3960 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { | |
3961 | .master = &omap44xx_l3_main_2_hwmod, | |
3962 | .slave = &omap44xx_l3_main_1_hwmod, | |
3963 | .clk = "l3_div_ck", | |
3964 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3965 | }; | |
3966 | ||
3967 | /* l4_cfg -> l3_main_1 */ | |
3968 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { | |
3969 | .master = &omap44xx_l4_cfg_hwmod, | |
3970 | .slave = &omap44xx_l3_main_1_hwmod, | |
3971 | .clk = "l4_div_ck", | |
3972 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3973 | }; | |
3974 | ||
3975 | /* mmc1 -> l3_main_1 */ | |
3976 | static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { | |
3977 | .master = &omap44xx_mmc1_hwmod, | |
3978 | .slave = &omap44xx_l3_main_1_hwmod, | |
3979 | .clk = "l3_div_ck", | |
3980 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3981 | }; | |
3982 | ||
3983 | /* mmc2 -> l3_main_1 */ | |
3984 | static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { | |
3985 | .master = &omap44xx_mmc2_hwmod, | |
3986 | .slave = &omap44xx_l3_main_1_hwmod, | |
3987 | .clk = "l3_div_ck", | |
3988 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3989 | }; | |
3990 | ||
3991 | static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { | |
3992 | { | |
3993 | .pa_start = 0x44000000, | |
3994 | .pa_end = 0x44000fff, | |
3995 | .flags = ADDR_TYPE_RT | |
3996 | }, | |
3997 | { } | |
3998 | }; | |
3999 | ||
4000 | /* mpu -> l3_main_1 */ | |
4001 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { | |
4002 | .master = &omap44xx_mpu_hwmod, | |
4003 | .slave = &omap44xx_l3_main_1_hwmod, | |
4004 | .clk = "l3_div_ck", | |
4005 | .addr = omap44xx_l3_main_1_addrs, | |
4006 | .user = OCP_USER_MPU, | |
4007 | }; | |
4008 | ||
42b9e387 PW |
4009 | /* c2c_target_fw -> l3_main_2 */ |
4010 | static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = { | |
4011 | .master = &omap44xx_c2c_target_fw_hwmod, | |
4012 | .slave = &omap44xx_l3_main_2_hwmod, | |
4013 | .clk = "l3_div_ck", | |
4014 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4015 | }; | |
4016 | ||
96566043 BC |
4017 | /* debugss -> l3_main_2 */ |
4018 | static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = { | |
4019 | .master = &omap44xx_debugss_hwmod, | |
4020 | .slave = &omap44xx_l3_main_2_hwmod, | |
4021 | .clk = "dbgclk_mux_ck", | |
4022 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4023 | }; | |
4024 | ||
844a3b63 PW |
4025 | /* dma_system -> l3_main_2 */ |
4026 | static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { | |
4027 | .master = &omap44xx_dma_system_hwmod, | |
4028 | .slave = &omap44xx_l3_main_2_hwmod, | |
4029 | .clk = "l3_div_ck", | |
4030 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4031 | }; | |
4032 | ||
b050f688 ML |
4033 | /* fdif -> l3_main_2 */ |
4034 | static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = { | |
4035 | .master = &omap44xx_fdif_hwmod, | |
4036 | .slave = &omap44xx_l3_main_2_hwmod, | |
4037 | .clk = "l3_div_ck", | |
4038 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4039 | }; | |
4040 | ||
9def390e PW |
4041 | /* gpu -> l3_main_2 */ |
4042 | static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = { | |
4043 | .master = &omap44xx_gpu_hwmod, | |
4044 | .slave = &omap44xx_l3_main_2_hwmod, | |
4045 | .clk = "l3_div_ck", | |
4046 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4047 | }; | |
4048 | ||
844a3b63 PW |
4049 | /* hsi -> l3_main_2 */ |
4050 | static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { | |
4051 | .master = &omap44xx_hsi_hwmod, | |
4052 | .slave = &omap44xx_l3_main_2_hwmod, | |
4053 | .clk = "l3_div_ck", | |
4054 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4055 | }; | |
4056 | ||
4057 | /* ipu -> l3_main_2 */ | |
4058 | static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { | |
4059 | .master = &omap44xx_ipu_hwmod, | |
4060 | .slave = &omap44xx_l3_main_2_hwmod, | |
4061 | .clk = "l3_div_ck", | |
4062 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4063 | }; | |
4064 | ||
4065 | /* iss -> l3_main_2 */ | |
4066 | static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { | |
4067 | .master = &omap44xx_iss_hwmod, | |
4068 | .slave = &omap44xx_l3_main_2_hwmod, | |
4069 | .clk = "l3_div_ck", | |
4070 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4071 | }; | |
4072 | ||
4073 | /* iva -> l3_main_2 */ | |
4074 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { | |
4075 | .master = &omap44xx_iva_hwmod, | |
4076 | .slave = &omap44xx_l3_main_2_hwmod, | |
4077 | .clk = "l3_div_ck", | |
4078 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4079 | }; | |
4080 | ||
4081 | static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { | |
4082 | { | |
4083 | .pa_start = 0x44800000, | |
4084 | .pa_end = 0x44801fff, | |
4085 | .flags = ADDR_TYPE_RT | |
4086 | }, | |
4087 | { } | |
4088 | }; | |
4089 | ||
4090 | /* l3_main_1 -> l3_main_2 */ | |
4091 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { | |
4092 | .master = &omap44xx_l3_main_1_hwmod, | |
4093 | .slave = &omap44xx_l3_main_2_hwmod, | |
4094 | .clk = "l3_div_ck", | |
4095 | .addr = omap44xx_l3_main_2_addrs, | |
4096 | .user = OCP_USER_MPU, | |
4097 | }; | |
4098 | ||
4099 | /* l4_cfg -> l3_main_2 */ | |
4100 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { | |
4101 | .master = &omap44xx_l4_cfg_hwmod, | |
4102 | .slave = &omap44xx_l3_main_2_hwmod, | |
4103 | .clk = "l4_div_ck", | |
4104 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4105 | }; | |
4106 | ||
0c668875 | 4107 | /* usb_host_fs -> l3_main_2 */ |
b0a70cc8 | 4108 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = { |
0c668875 BC |
4109 | .master = &omap44xx_usb_host_fs_hwmod, |
4110 | .slave = &omap44xx_l3_main_2_hwmod, | |
4111 | .clk = "l3_div_ck", | |
4112 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4113 | }; | |
4114 | ||
844a3b63 PW |
4115 | /* usb_host_hs -> l3_main_2 */ |
4116 | static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { | |
4117 | .master = &omap44xx_usb_host_hs_hwmod, | |
4118 | .slave = &omap44xx_l3_main_2_hwmod, | |
4119 | .clk = "l3_div_ck", | |
4120 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4121 | }; | |
4122 | ||
4123 | /* usb_otg_hs -> l3_main_2 */ | |
4124 | static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { | |
4125 | .master = &omap44xx_usb_otg_hs_hwmod, | |
4126 | .slave = &omap44xx_l3_main_2_hwmod, | |
4127 | .clk = "l3_div_ck", | |
4128 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4129 | }; | |
4130 | ||
4131 | static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { | |
4132 | { | |
4133 | .pa_start = 0x45000000, | |
4134 | .pa_end = 0x45000fff, | |
4135 | .flags = ADDR_TYPE_RT | |
4136 | }, | |
4137 | { } | |
4138 | }; | |
4139 | ||
4140 | /* l3_main_1 -> l3_main_3 */ | |
4141 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { | |
4142 | .master = &omap44xx_l3_main_1_hwmod, | |
4143 | .slave = &omap44xx_l3_main_3_hwmod, | |
4144 | .clk = "l3_div_ck", | |
4145 | .addr = omap44xx_l3_main_3_addrs, | |
4146 | .user = OCP_USER_MPU, | |
4147 | }; | |
4148 | ||
4149 | /* l3_main_2 -> l3_main_3 */ | |
4150 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { | |
4151 | .master = &omap44xx_l3_main_2_hwmod, | |
4152 | .slave = &omap44xx_l3_main_3_hwmod, | |
4153 | .clk = "l3_div_ck", | |
4154 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4155 | }; | |
4156 | ||
4157 | /* l4_cfg -> l3_main_3 */ | |
4158 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { | |
4159 | .master = &omap44xx_l4_cfg_hwmod, | |
4160 | .slave = &omap44xx_l3_main_3_hwmod, | |
4161 | .clk = "l4_div_ck", | |
4162 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4163 | }; | |
4164 | ||
4165 | /* aess -> l4_abe */ | |
b0a70cc8 | 4166 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = { |
844a3b63 PW |
4167 | .master = &omap44xx_aess_hwmod, |
4168 | .slave = &omap44xx_l4_abe_hwmod, | |
4169 | .clk = "ocp_abe_iclk", | |
4170 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4171 | }; | |
4172 | ||
4173 | /* dsp -> l4_abe */ | |
4174 | static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { | |
4175 | .master = &omap44xx_dsp_hwmod, | |
4176 | .slave = &omap44xx_l4_abe_hwmod, | |
4177 | .clk = "ocp_abe_iclk", | |
4178 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4179 | }; | |
4180 | ||
4181 | /* l3_main_1 -> l4_abe */ | |
4182 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { | |
4183 | .master = &omap44xx_l3_main_1_hwmod, | |
4184 | .slave = &omap44xx_l4_abe_hwmod, | |
4185 | .clk = "l3_div_ck", | |
4186 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4187 | }; | |
4188 | ||
4189 | /* mpu -> l4_abe */ | |
4190 | static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { | |
4191 | .master = &omap44xx_mpu_hwmod, | |
4192 | .slave = &omap44xx_l4_abe_hwmod, | |
4193 | .clk = "ocp_abe_iclk", | |
4194 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4195 | }; | |
4196 | ||
4197 | /* l3_main_1 -> l4_cfg */ | |
4198 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { | |
4199 | .master = &omap44xx_l3_main_1_hwmod, | |
4200 | .slave = &omap44xx_l4_cfg_hwmod, | |
4201 | .clk = "l3_div_ck", | |
4202 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4203 | }; | |
4204 | ||
4205 | /* l3_main_2 -> l4_per */ | |
4206 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { | |
4207 | .master = &omap44xx_l3_main_2_hwmod, | |
4208 | .slave = &omap44xx_l4_per_hwmod, | |
4209 | .clk = "l3_div_ck", | |
4210 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4211 | }; | |
4212 | ||
4213 | /* l4_cfg -> l4_wkup */ | |
4214 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { | |
4215 | .master = &omap44xx_l4_cfg_hwmod, | |
4216 | .slave = &omap44xx_l4_wkup_hwmod, | |
4217 | .clk = "l4_div_ck", | |
4218 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4219 | }; | |
4220 | ||
4221 | /* mpu -> mpu_private */ | |
4222 | static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { | |
4223 | .master = &omap44xx_mpu_hwmod, | |
4224 | .slave = &omap44xx_mpu_private_hwmod, | |
4225 | .clk = "l3_div_ck", | |
4226 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4227 | }; | |
4228 | ||
9a817bc8 BC |
4229 | static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = { |
4230 | { | |
4231 | .pa_start = 0x4a102000, | |
4232 | .pa_end = 0x4a10207f, | |
4233 | .flags = ADDR_TYPE_RT | |
4234 | }, | |
4235 | { } | |
4236 | }; | |
4237 | ||
4238 | /* l4_cfg -> ocp_wp_noc */ | |
4239 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = { | |
4240 | .master = &omap44xx_l4_cfg_hwmod, | |
4241 | .slave = &omap44xx_ocp_wp_noc_hwmod, | |
4242 | .clk = "l4_div_ck", | |
4243 | .addr = omap44xx_ocp_wp_noc_addrs, | |
4244 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4245 | }; | |
4246 | ||
844a3b63 PW |
4247 | static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { |
4248 | { | |
4249 | .pa_start = 0x401f1000, | |
4250 | .pa_end = 0x401f13ff, | |
4251 | .flags = ADDR_TYPE_RT | |
4252 | }, | |
4253 | { } | |
4254 | }; | |
4255 | ||
4256 | /* l4_abe -> aess */ | |
b0a70cc8 | 4257 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = { |
844a3b63 PW |
4258 | .master = &omap44xx_l4_abe_hwmod, |
4259 | .slave = &omap44xx_aess_hwmod, | |
4260 | .clk = "ocp_abe_iclk", | |
4261 | .addr = omap44xx_aess_addrs, | |
4262 | .user = OCP_USER_MPU, | |
4263 | }; | |
4264 | ||
4265 | static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { | |
4266 | { | |
4267 | .pa_start = 0x490f1000, | |
4268 | .pa_end = 0x490f13ff, | |
4269 | .flags = ADDR_TYPE_RT | |
4270 | }, | |
4271 | { } | |
4272 | }; | |
4273 | ||
4274 | /* l4_abe -> aess (dma) */ | |
b0a70cc8 | 4275 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = { |
844a3b63 PW |
4276 | .master = &omap44xx_l4_abe_hwmod, |
4277 | .slave = &omap44xx_aess_hwmod, | |
4278 | .clk = "ocp_abe_iclk", | |
4279 | .addr = omap44xx_aess_dma_addrs, | |
4280 | .user = OCP_USER_SDMA, | |
4281 | }; | |
4282 | ||
42b9e387 PW |
4283 | /* l3_main_2 -> c2c */ |
4284 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = { | |
4285 | .master = &omap44xx_l3_main_2_hwmod, | |
4286 | .slave = &omap44xx_c2c_hwmod, | |
4287 | .clk = "l3_div_ck", | |
4288 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4289 | }; | |
4290 | ||
844a3b63 PW |
4291 | static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { |
4292 | { | |
4293 | .pa_start = 0x4a304000, | |
4294 | .pa_end = 0x4a30401f, | |
4295 | .flags = ADDR_TYPE_RT | |
4296 | }, | |
4297 | { } | |
4298 | }; | |
4299 | ||
4300 | /* l4_wkup -> counter_32k */ | |
4301 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { | |
4302 | .master = &omap44xx_l4_wkup_hwmod, | |
4303 | .slave = &omap44xx_counter_32k_hwmod, | |
4304 | .clk = "l4_wkup_clk_mux_ck", | |
4305 | .addr = omap44xx_counter_32k_addrs, | |
4306 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4307 | }; | |
4308 | ||
a0b5d813 PW |
4309 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = { |
4310 | { | |
4311 | .pa_start = 0x4a002000, | |
4312 | .pa_end = 0x4a0027ff, | |
4313 | .flags = ADDR_TYPE_RT | |
4314 | }, | |
4315 | { } | |
4316 | }; | |
4317 | ||
4318 | /* l4_cfg -> ctrl_module_core */ | |
4319 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = { | |
4320 | .master = &omap44xx_l4_cfg_hwmod, | |
4321 | .slave = &omap44xx_ctrl_module_core_hwmod, | |
4322 | .clk = "l4_div_ck", | |
4323 | .addr = omap44xx_ctrl_module_core_addrs, | |
4324 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4325 | }; | |
4326 | ||
4327 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = { | |
4328 | { | |
4329 | .pa_start = 0x4a100000, | |
4330 | .pa_end = 0x4a1007ff, | |
4331 | .flags = ADDR_TYPE_RT | |
4332 | }, | |
4333 | { } | |
4334 | }; | |
4335 | ||
4336 | /* l4_cfg -> ctrl_module_pad_core */ | |
4337 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = { | |
4338 | .master = &omap44xx_l4_cfg_hwmod, | |
4339 | .slave = &omap44xx_ctrl_module_pad_core_hwmod, | |
4340 | .clk = "l4_div_ck", | |
4341 | .addr = omap44xx_ctrl_module_pad_core_addrs, | |
4342 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4343 | }; | |
4344 | ||
4345 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = { | |
4346 | { | |
4347 | .pa_start = 0x4a30c000, | |
4348 | .pa_end = 0x4a30c7ff, | |
4349 | .flags = ADDR_TYPE_RT | |
4350 | }, | |
4351 | { } | |
4352 | }; | |
4353 | ||
4354 | /* l4_wkup -> ctrl_module_wkup */ | |
4355 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = { | |
4356 | .master = &omap44xx_l4_wkup_hwmod, | |
4357 | .slave = &omap44xx_ctrl_module_wkup_hwmod, | |
4358 | .clk = "l4_wkup_clk_mux_ck", | |
4359 | .addr = omap44xx_ctrl_module_wkup_addrs, | |
4360 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4361 | }; | |
4362 | ||
4363 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = { | |
4364 | { | |
4365 | .pa_start = 0x4a31e000, | |
4366 | .pa_end = 0x4a31e7ff, | |
4367 | .flags = ADDR_TYPE_RT | |
4368 | }, | |
4369 | { } | |
4370 | }; | |
4371 | ||
4372 | /* l4_wkup -> ctrl_module_pad_wkup */ | |
4373 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = { | |
4374 | .master = &omap44xx_l4_wkup_hwmod, | |
4375 | .slave = &omap44xx_ctrl_module_pad_wkup_hwmod, | |
4376 | .clk = "l4_wkup_clk_mux_ck", | |
4377 | .addr = omap44xx_ctrl_module_pad_wkup_addrs, | |
4378 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4379 | }; | |
4380 | ||
96566043 BC |
4381 | static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = { |
4382 | { | |
4383 | .pa_start = 0x54160000, | |
4384 | .pa_end = 0x54167fff, | |
4385 | .flags = ADDR_TYPE_RT | |
4386 | }, | |
4387 | { } | |
4388 | }; | |
4389 | ||
4390 | /* l3_instr -> debugss */ | |
4391 | static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = { | |
4392 | .master = &omap44xx_l3_instr_hwmod, | |
4393 | .slave = &omap44xx_debugss_hwmod, | |
4394 | .clk = "l3_div_ck", | |
4395 | .addr = omap44xx_debugss_addrs, | |
4396 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4397 | }; | |
4398 | ||
844a3b63 PW |
4399 | static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { |
4400 | { | |
4401 | .pa_start = 0x4a056000, | |
4402 | .pa_end = 0x4a056fff, | |
4403 | .flags = ADDR_TYPE_RT | |
4404 | }, | |
4405 | { } | |
4406 | }; | |
4407 | ||
4408 | /* l4_cfg -> dma_system */ | |
4409 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { | |
4410 | .master = &omap44xx_l4_cfg_hwmod, | |
4411 | .slave = &omap44xx_dma_system_hwmod, | |
4412 | .clk = "l4_div_ck", | |
4413 | .addr = omap44xx_dma_system_addrs, | |
4414 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4415 | }; | |
4416 | ||
4417 | static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { | |
4418 | { | |
4419 | .name = "mpu", | |
4420 | .pa_start = 0x4012e000, | |
4421 | .pa_end = 0x4012e07f, | |
4422 | .flags = ADDR_TYPE_RT | |
4423 | }, | |
4424 | { } | |
4425 | }; | |
4426 | ||
4427 | /* l4_abe -> dmic */ | |
4428 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { | |
4429 | .master = &omap44xx_l4_abe_hwmod, | |
4430 | .slave = &omap44xx_dmic_hwmod, | |
4431 | .clk = "ocp_abe_iclk", | |
4432 | .addr = omap44xx_dmic_addrs, | |
4433 | .user = OCP_USER_MPU, | |
4434 | }; | |
4435 | ||
4436 | static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { | |
4437 | { | |
4438 | .name = "dma", | |
4439 | .pa_start = 0x4902e000, | |
4440 | .pa_end = 0x4902e07f, | |
4441 | .flags = ADDR_TYPE_RT | |
4442 | }, | |
4443 | { } | |
4444 | }; | |
4445 | ||
4446 | /* l4_abe -> dmic (dma) */ | |
4447 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { | |
4448 | .master = &omap44xx_l4_abe_hwmod, | |
4449 | .slave = &omap44xx_dmic_hwmod, | |
4450 | .clk = "ocp_abe_iclk", | |
4451 | .addr = omap44xx_dmic_dma_addrs, | |
4452 | .user = OCP_USER_SDMA, | |
4453 | }; | |
4454 | ||
4455 | /* dsp -> iva */ | |
4456 | static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { | |
4457 | .master = &omap44xx_dsp_hwmod, | |
4458 | .slave = &omap44xx_iva_hwmod, | |
4459 | .clk = "dpll_iva_m5x2_ck", | |
4460 | .user = OCP_USER_DSP, | |
4461 | }; | |
4462 | ||
42b9e387 | 4463 | /* dsp -> sl2if */ |
b360124e | 4464 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = { |
42b9e387 PW |
4465 | .master = &omap44xx_dsp_hwmod, |
4466 | .slave = &omap44xx_sl2if_hwmod, | |
4467 | .clk = "dpll_iva_m5x2_ck", | |
4468 | .user = OCP_USER_DSP, | |
4469 | }; | |
4470 | ||
844a3b63 PW |
4471 | /* l4_cfg -> dsp */ |
4472 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { | |
4473 | .master = &omap44xx_l4_cfg_hwmod, | |
4474 | .slave = &omap44xx_dsp_hwmod, | |
4475 | .clk = "l4_div_ck", | |
4476 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4477 | }; | |
4478 | ||
4479 | static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { | |
4480 | { | |
4481 | .pa_start = 0x58000000, | |
4482 | .pa_end = 0x5800007f, | |
4483 | .flags = ADDR_TYPE_RT | |
4484 | }, | |
4485 | { } | |
4486 | }; | |
4487 | ||
4488 | /* l3_main_2 -> dss */ | |
4489 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { | |
4490 | .master = &omap44xx_l3_main_2_hwmod, | |
4491 | .slave = &omap44xx_dss_hwmod, | |
4492 | .clk = "dss_fck", | |
4493 | .addr = omap44xx_dss_dma_addrs, | |
4494 | .user = OCP_USER_SDMA, | |
4495 | }; | |
4496 | ||
4497 | static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { | |
4498 | { | |
4499 | .pa_start = 0x48040000, | |
4500 | .pa_end = 0x4804007f, | |
4501 | .flags = ADDR_TYPE_RT | |
4502 | }, | |
4503 | { } | |
4504 | }; | |
4505 | ||
4506 | /* l4_per -> dss */ | |
4507 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { | |
4508 | .master = &omap44xx_l4_per_hwmod, | |
4509 | .slave = &omap44xx_dss_hwmod, | |
4510 | .clk = "l4_div_ck", | |
4511 | .addr = omap44xx_dss_addrs, | |
4512 | .user = OCP_USER_MPU, | |
4513 | }; | |
4514 | ||
4515 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { | |
4516 | { | |
4517 | .pa_start = 0x58001000, | |
4518 | .pa_end = 0x58001fff, | |
4519 | .flags = ADDR_TYPE_RT | |
4520 | }, | |
4521 | { } | |
4522 | }; | |
4523 | ||
4524 | /* l3_main_2 -> dss_dispc */ | |
4525 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { | |
4526 | .master = &omap44xx_l3_main_2_hwmod, | |
4527 | .slave = &omap44xx_dss_dispc_hwmod, | |
4528 | .clk = "dss_fck", | |
4529 | .addr = omap44xx_dss_dispc_dma_addrs, | |
4530 | .user = OCP_USER_SDMA, | |
4531 | }; | |
4532 | ||
4533 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { | |
4534 | { | |
4535 | .pa_start = 0x48041000, | |
4536 | .pa_end = 0x48041fff, | |
4537 | .flags = ADDR_TYPE_RT | |
4538 | }, | |
4539 | { } | |
4540 | }; | |
4541 | ||
4542 | /* l4_per -> dss_dispc */ | |
4543 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { | |
4544 | .master = &omap44xx_l4_per_hwmod, | |
4545 | .slave = &omap44xx_dss_dispc_hwmod, | |
4546 | .clk = "l4_div_ck", | |
4547 | .addr = omap44xx_dss_dispc_addrs, | |
4548 | .user = OCP_USER_MPU, | |
4549 | }; | |
4550 | ||
4551 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { | |
4552 | { | |
4553 | .pa_start = 0x58004000, | |
4554 | .pa_end = 0x580041ff, | |
4555 | .flags = ADDR_TYPE_RT | |
4556 | }, | |
4557 | { } | |
4558 | }; | |
4559 | ||
4560 | /* l3_main_2 -> dss_dsi1 */ | |
4561 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { | |
4562 | .master = &omap44xx_l3_main_2_hwmod, | |
4563 | .slave = &omap44xx_dss_dsi1_hwmod, | |
4564 | .clk = "dss_fck", | |
4565 | .addr = omap44xx_dss_dsi1_dma_addrs, | |
4566 | .user = OCP_USER_SDMA, | |
4567 | }; | |
4568 | ||
4569 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { | |
4570 | { | |
4571 | .pa_start = 0x48044000, | |
4572 | .pa_end = 0x480441ff, | |
4573 | .flags = ADDR_TYPE_RT | |
4574 | }, | |
4575 | { } | |
4576 | }; | |
4577 | ||
4578 | /* l4_per -> dss_dsi1 */ | |
4579 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { | |
4580 | .master = &omap44xx_l4_per_hwmod, | |
4581 | .slave = &omap44xx_dss_dsi1_hwmod, | |
4582 | .clk = "l4_div_ck", | |
4583 | .addr = omap44xx_dss_dsi1_addrs, | |
4584 | .user = OCP_USER_MPU, | |
4585 | }; | |
4586 | ||
4587 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { | |
4588 | { | |
4589 | .pa_start = 0x58005000, | |
4590 | .pa_end = 0x580051ff, | |
4591 | .flags = ADDR_TYPE_RT | |
4592 | }, | |
4593 | { } | |
4594 | }; | |
4595 | ||
4596 | /* l3_main_2 -> dss_dsi2 */ | |
4597 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { | |
4598 | .master = &omap44xx_l3_main_2_hwmod, | |
4599 | .slave = &omap44xx_dss_dsi2_hwmod, | |
4600 | .clk = "dss_fck", | |
4601 | .addr = omap44xx_dss_dsi2_dma_addrs, | |
4602 | .user = OCP_USER_SDMA, | |
4603 | }; | |
4604 | ||
4605 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { | |
4606 | { | |
4607 | .pa_start = 0x48045000, | |
4608 | .pa_end = 0x480451ff, | |
4609 | .flags = ADDR_TYPE_RT | |
4610 | }, | |
4611 | { } | |
4612 | }; | |
4613 | ||
4614 | /* l4_per -> dss_dsi2 */ | |
4615 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { | |
4616 | .master = &omap44xx_l4_per_hwmod, | |
4617 | .slave = &omap44xx_dss_dsi2_hwmod, | |
4618 | .clk = "l4_div_ck", | |
4619 | .addr = omap44xx_dss_dsi2_addrs, | |
4620 | .user = OCP_USER_MPU, | |
4621 | }; | |
4622 | ||
4623 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { | |
4624 | { | |
4625 | .pa_start = 0x58006000, | |
4626 | .pa_end = 0x58006fff, | |
4627 | .flags = ADDR_TYPE_RT | |
4628 | }, | |
4629 | { } | |
4630 | }; | |
4631 | ||
4632 | /* l3_main_2 -> dss_hdmi */ | |
4633 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { | |
4634 | .master = &omap44xx_l3_main_2_hwmod, | |
4635 | .slave = &omap44xx_dss_hdmi_hwmod, | |
4636 | .clk = "dss_fck", | |
4637 | .addr = omap44xx_dss_hdmi_dma_addrs, | |
4638 | .user = OCP_USER_SDMA, | |
4639 | }; | |
4640 | ||
4641 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { | |
4642 | { | |
4643 | .pa_start = 0x48046000, | |
4644 | .pa_end = 0x48046fff, | |
4645 | .flags = ADDR_TYPE_RT | |
4646 | }, | |
4647 | { } | |
4648 | }; | |
4649 | ||
4650 | /* l4_per -> dss_hdmi */ | |
4651 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { | |
4652 | .master = &omap44xx_l4_per_hwmod, | |
4653 | .slave = &omap44xx_dss_hdmi_hwmod, | |
4654 | .clk = "l4_div_ck", | |
4655 | .addr = omap44xx_dss_hdmi_addrs, | |
4656 | .user = OCP_USER_MPU, | |
4657 | }; | |
4658 | ||
4659 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { | |
4660 | { | |
4661 | .pa_start = 0x58002000, | |
4662 | .pa_end = 0x580020ff, | |
4663 | .flags = ADDR_TYPE_RT | |
4664 | }, | |
4665 | { } | |
4666 | }; | |
4667 | ||
4668 | /* l3_main_2 -> dss_rfbi */ | |
4669 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { | |
4670 | .master = &omap44xx_l3_main_2_hwmod, | |
4671 | .slave = &omap44xx_dss_rfbi_hwmod, | |
4672 | .clk = "dss_fck", | |
4673 | .addr = omap44xx_dss_rfbi_dma_addrs, | |
4674 | .user = OCP_USER_SDMA, | |
4675 | }; | |
4676 | ||
4677 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { | |
4678 | { | |
4679 | .pa_start = 0x48042000, | |
4680 | .pa_end = 0x480420ff, | |
4681 | .flags = ADDR_TYPE_RT | |
4682 | }, | |
4683 | { } | |
4684 | }; | |
4685 | ||
4686 | /* l4_per -> dss_rfbi */ | |
4687 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { | |
4688 | .master = &omap44xx_l4_per_hwmod, | |
4689 | .slave = &omap44xx_dss_rfbi_hwmod, | |
4690 | .clk = "l4_div_ck", | |
4691 | .addr = omap44xx_dss_rfbi_addrs, | |
4692 | .user = OCP_USER_MPU, | |
4693 | }; | |
4694 | ||
4695 | static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { | |
4696 | { | |
4697 | .pa_start = 0x58003000, | |
4698 | .pa_end = 0x580030ff, | |
4699 | .flags = ADDR_TYPE_RT | |
4700 | }, | |
4701 | { } | |
4702 | }; | |
4703 | ||
4704 | /* l3_main_2 -> dss_venc */ | |
4705 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { | |
4706 | .master = &omap44xx_l3_main_2_hwmod, | |
4707 | .slave = &omap44xx_dss_venc_hwmod, | |
4708 | .clk = "dss_fck", | |
4709 | .addr = omap44xx_dss_venc_dma_addrs, | |
4710 | .user = OCP_USER_SDMA, | |
4711 | }; | |
4712 | ||
4713 | static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { | |
4714 | { | |
4715 | .pa_start = 0x48043000, | |
4716 | .pa_end = 0x480430ff, | |
4717 | .flags = ADDR_TYPE_RT | |
4718 | }, | |
4719 | { } | |
4720 | }; | |
4721 | ||
4722 | /* l4_per -> dss_venc */ | |
4723 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { | |
4724 | .master = &omap44xx_l4_per_hwmod, | |
4725 | .slave = &omap44xx_dss_venc_hwmod, | |
4726 | .clk = "l4_div_ck", | |
4727 | .addr = omap44xx_dss_venc_addrs, | |
4728 | .user = OCP_USER_MPU, | |
4729 | }; | |
4730 | ||
42b9e387 PW |
4731 | static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = { |
4732 | { | |
4733 | .pa_start = 0x48078000, | |
4734 | .pa_end = 0x48078fff, | |
4735 | .flags = ADDR_TYPE_RT | |
4736 | }, | |
4737 | { } | |
4738 | }; | |
4739 | ||
4740 | /* l4_per -> elm */ | |
4741 | static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = { | |
4742 | .master = &omap44xx_l4_per_hwmod, | |
4743 | .slave = &omap44xx_elm_hwmod, | |
4744 | .clk = "l4_div_ck", | |
4745 | .addr = omap44xx_elm_addrs, | |
4746 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4747 | }; | |
4748 | ||
bf30f950 PW |
4749 | static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = { |
4750 | { | |
4751 | .pa_start = 0x4c000000, | |
4752 | .pa_end = 0x4c0000ff, | |
4753 | .flags = ADDR_TYPE_RT | |
4754 | }, | |
4755 | { } | |
4756 | }; | |
4757 | ||
4758 | /* emif_fw -> emif1 */ | |
4759 | static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = { | |
4760 | .master = &omap44xx_emif_fw_hwmod, | |
4761 | .slave = &omap44xx_emif1_hwmod, | |
4762 | .clk = "l3_div_ck", | |
4763 | .addr = omap44xx_emif1_addrs, | |
4764 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4765 | }; | |
4766 | ||
4767 | static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = { | |
4768 | { | |
4769 | .pa_start = 0x4d000000, | |
4770 | .pa_end = 0x4d0000ff, | |
4771 | .flags = ADDR_TYPE_RT | |
4772 | }, | |
4773 | { } | |
4774 | }; | |
4775 | ||
4776 | /* emif_fw -> emif2 */ | |
4777 | static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = { | |
4778 | .master = &omap44xx_emif_fw_hwmod, | |
4779 | .slave = &omap44xx_emif2_hwmod, | |
4780 | .clk = "l3_div_ck", | |
4781 | .addr = omap44xx_emif2_addrs, | |
4782 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4783 | }; | |
4784 | ||
b050f688 ML |
4785 | static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = { |
4786 | { | |
4787 | .pa_start = 0x4a10a000, | |
4788 | .pa_end = 0x4a10a1ff, | |
4789 | .flags = ADDR_TYPE_RT | |
4790 | }, | |
4791 | { } | |
4792 | }; | |
4793 | ||
4794 | /* l4_cfg -> fdif */ | |
4795 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = { | |
4796 | .master = &omap44xx_l4_cfg_hwmod, | |
4797 | .slave = &omap44xx_fdif_hwmod, | |
4798 | .clk = "l4_div_ck", | |
4799 | .addr = omap44xx_fdif_addrs, | |
4800 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4801 | }; | |
4802 | ||
844a3b63 PW |
4803 | static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { |
4804 | { | |
4805 | .pa_start = 0x4a310000, | |
4806 | .pa_end = 0x4a3101ff, | |
4807 | .flags = ADDR_TYPE_RT | |
4808 | }, | |
4809 | { } | |
4810 | }; | |
4811 | ||
4812 | /* l4_wkup -> gpio1 */ | |
4813 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { | |
4814 | .master = &omap44xx_l4_wkup_hwmod, | |
4815 | .slave = &omap44xx_gpio1_hwmod, | |
4816 | .clk = "l4_wkup_clk_mux_ck", | |
4817 | .addr = omap44xx_gpio1_addrs, | |
4818 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4819 | }; | |
4820 | ||
4821 | static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { | |
4822 | { | |
4823 | .pa_start = 0x48055000, | |
4824 | .pa_end = 0x480551ff, | |
4825 | .flags = ADDR_TYPE_RT | |
4826 | }, | |
4827 | { } | |
4828 | }; | |
4829 | ||
4830 | /* l4_per -> gpio2 */ | |
4831 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { | |
4832 | .master = &omap44xx_l4_per_hwmod, | |
4833 | .slave = &omap44xx_gpio2_hwmod, | |
4834 | .clk = "l4_div_ck", | |
4835 | .addr = omap44xx_gpio2_addrs, | |
4836 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4837 | }; | |
4838 | ||
4839 | static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { | |
4840 | { | |
4841 | .pa_start = 0x48057000, | |
4842 | .pa_end = 0x480571ff, | |
4843 | .flags = ADDR_TYPE_RT | |
4844 | }, | |
4845 | { } | |
4846 | }; | |
4847 | ||
4848 | /* l4_per -> gpio3 */ | |
4849 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { | |
4850 | .master = &omap44xx_l4_per_hwmod, | |
4851 | .slave = &omap44xx_gpio3_hwmod, | |
4852 | .clk = "l4_div_ck", | |
4853 | .addr = omap44xx_gpio3_addrs, | |
4854 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4855 | }; | |
4856 | ||
4857 | static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { | |
4858 | { | |
4859 | .pa_start = 0x48059000, | |
4860 | .pa_end = 0x480591ff, | |
4861 | .flags = ADDR_TYPE_RT | |
4862 | }, | |
4863 | { } | |
4864 | }; | |
4865 | ||
4866 | /* l4_per -> gpio4 */ | |
4867 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { | |
4868 | .master = &omap44xx_l4_per_hwmod, | |
4869 | .slave = &omap44xx_gpio4_hwmod, | |
4870 | .clk = "l4_div_ck", | |
4871 | .addr = omap44xx_gpio4_addrs, | |
4872 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4873 | }; | |
4874 | ||
4875 | static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { | |
4876 | { | |
4877 | .pa_start = 0x4805b000, | |
4878 | .pa_end = 0x4805b1ff, | |
4879 | .flags = ADDR_TYPE_RT | |
4880 | }, | |
4881 | { } | |
4882 | }; | |
4883 | ||
4884 | /* l4_per -> gpio5 */ | |
4885 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { | |
4886 | .master = &omap44xx_l4_per_hwmod, | |
4887 | .slave = &omap44xx_gpio5_hwmod, | |
4888 | .clk = "l4_div_ck", | |
4889 | .addr = omap44xx_gpio5_addrs, | |
4890 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4891 | }; | |
4892 | ||
4893 | static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { | |
4894 | { | |
4895 | .pa_start = 0x4805d000, | |
4896 | .pa_end = 0x4805d1ff, | |
4897 | .flags = ADDR_TYPE_RT | |
4898 | }, | |
4899 | { } | |
4900 | }; | |
4901 | ||
4902 | /* l4_per -> gpio6 */ | |
4903 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { | |
4904 | .master = &omap44xx_l4_per_hwmod, | |
4905 | .slave = &omap44xx_gpio6_hwmod, | |
4906 | .clk = "l4_div_ck", | |
4907 | .addr = omap44xx_gpio6_addrs, | |
4908 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4909 | }; | |
4910 | ||
eb42b5d3 BC |
4911 | static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = { |
4912 | { | |
4913 | .pa_start = 0x50000000, | |
4914 | .pa_end = 0x500003ff, | |
4915 | .flags = ADDR_TYPE_RT | |
4916 | }, | |
4917 | { } | |
4918 | }; | |
4919 | ||
4920 | /* l3_main_2 -> gpmc */ | |
4921 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { | |
4922 | .master = &omap44xx_l3_main_2_hwmod, | |
4923 | .slave = &omap44xx_gpmc_hwmod, | |
4924 | .clk = "l3_div_ck", | |
4925 | .addr = omap44xx_gpmc_addrs, | |
4926 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4927 | }; | |
4928 | ||
9def390e PW |
4929 | static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = { |
4930 | { | |
4931 | .pa_start = 0x56000000, | |
4932 | .pa_end = 0x5600ffff, | |
4933 | .flags = ADDR_TYPE_RT | |
4934 | }, | |
4935 | { } | |
4936 | }; | |
4937 | ||
4938 | /* l3_main_2 -> gpu */ | |
4939 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = { | |
4940 | .master = &omap44xx_l3_main_2_hwmod, | |
4941 | .slave = &omap44xx_gpu_hwmod, | |
4942 | .clk = "l3_div_ck", | |
4943 | .addr = omap44xx_gpu_addrs, | |
4944 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4945 | }; | |
4946 | ||
a091c08e PW |
4947 | static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = { |
4948 | { | |
4949 | .pa_start = 0x480b2000, | |
4950 | .pa_end = 0x480b201f, | |
4951 | .flags = ADDR_TYPE_RT | |
4952 | }, | |
4953 | { } | |
4954 | }; | |
4955 | ||
4956 | /* l4_per -> hdq1w */ | |
4957 | static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = { | |
4958 | .master = &omap44xx_l4_per_hwmod, | |
4959 | .slave = &omap44xx_hdq1w_hwmod, | |
4960 | .clk = "l4_div_ck", | |
4961 | .addr = omap44xx_hdq1w_addrs, | |
4962 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4963 | }; | |
4964 | ||
844a3b63 PW |
4965 | static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { |
4966 | { | |
4967 | .pa_start = 0x4a058000, | |
4968 | .pa_end = 0x4a05bfff, | |
4969 | .flags = ADDR_TYPE_RT | |
4970 | }, | |
4971 | { } | |
4972 | }; | |
4973 | ||
4974 | /* l4_cfg -> hsi */ | |
4975 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { | |
4976 | .master = &omap44xx_l4_cfg_hwmod, | |
4977 | .slave = &omap44xx_hsi_hwmod, | |
4978 | .clk = "l4_div_ck", | |
4979 | .addr = omap44xx_hsi_addrs, | |
4980 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4981 | }; | |
4982 | ||
4983 | static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { | |
4984 | { | |
4985 | .pa_start = 0x48070000, | |
4986 | .pa_end = 0x480700ff, | |
4987 | .flags = ADDR_TYPE_RT | |
4988 | }, | |
4989 | { } | |
4990 | }; | |
4991 | ||
4992 | /* l4_per -> i2c1 */ | |
4993 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { | |
4994 | .master = &omap44xx_l4_per_hwmod, | |
4995 | .slave = &omap44xx_i2c1_hwmod, | |
4996 | .clk = "l4_div_ck", | |
4997 | .addr = omap44xx_i2c1_addrs, | |
4998 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4999 | }; | |
5000 | ||
5001 | static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { | |
5002 | { | |
5003 | .pa_start = 0x48072000, | |
5004 | .pa_end = 0x480720ff, | |
5005 | .flags = ADDR_TYPE_RT | |
5006 | }, | |
5007 | { } | |
5008 | }; | |
5009 | ||
5010 | /* l4_per -> i2c2 */ | |
5011 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { | |
5012 | .master = &omap44xx_l4_per_hwmod, | |
5013 | .slave = &omap44xx_i2c2_hwmod, | |
5014 | .clk = "l4_div_ck", | |
5015 | .addr = omap44xx_i2c2_addrs, | |
5016 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5017 | }; | |
5018 | ||
5019 | static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { | |
5020 | { | |
5021 | .pa_start = 0x48060000, | |
5022 | .pa_end = 0x480600ff, | |
5023 | .flags = ADDR_TYPE_RT | |
5024 | }, | |
5025 | { } | |
5026 | }; | |
5027 | ||
5028 | /* l4_per -> i2c3 */ | |
5029 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { | |
5030 | .master = &omap44xx_l4_per_hwmod, | |
5031 | .slave = &omap44xx_i2c3_hwmod, | |
5032 | .clk = "l4_div_ck", | |
5033 | .addr = omap44xx_i2c3_addrs, | |
5034 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5035 | }; | |
5036 | ||
5037 | static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { | |
5038 | { | |
5039 | .pa_start = 0x48350000, | |
5040 | .pa_end = 0x483500ff, | |
5041 | .flags = ADDR_TYPE_RT | |
5042 | }, | |
5043 | { } | |
5044 | }; | |
5045 | ||
5046 | /* l4_per -> i2c4 */ | |
5047 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { | |
5048 | .master = &omap44xx_l4_per_hwmod, | |
5049 | .slave = &omap44xx_i2c4_hwmod, | |
5050 | .clk = "l4_div_ck", | |
5051 | .addr = omap44xx_i2c4_addrs, | |
5052 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5053 | }; | |
5054 | ||
5055 | /* l3_main_2 -> ipu */ | |
5056 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { | |
5057 | .master = &omap44xx_l3_main_2_hwmod, | |
5058 | .slave = &omap44xx_ipu_hwmod, | |
5059 | .clk = "l3_div_ck", | |
5060 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5061 | }; | |
5062 | ||
5063 | static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { | |
5064 | { | |
5065 | .pa_start = 0x52000000, | |
5066 | .pa_end = 0x520000ff, | |
5067 | .flags = ADDR_TYPE_RT | |
5068 | }, | |
5069 | { } | |
5070 | }; | |
5071 | ||
5072 | /* l3_main_2 -> iss */ | |
5073 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { | |
5074 | .master = &omap44xx_l3_main_2_hwmod, | |
5075 | .slave = &omap44xx_iss_hwmod, | |
5076 | .clk = "l3_div_ck", | |
5077 | .addr = omap44xx_iss_addrs, | |
5078 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5079 | }; | |
5080 | ||
42b9e387 | 5081 | /* iva -> sl2if */ |
b360124e | 5082 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = { |
42b9e387 PW |
5083 | .master = &omap44xx_iva_hwmod, |
5084 | .slave = &omap44xx_sl2if_hwmod, | |
5085 | .clk = "dpll_iva_m5x2_ck", | |
5086 | .user = OCP_USER_IVA, | |
5087 | }; | |
5088 | ||
844a3b63 PW |
5089 | static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { |
5090 | { | |
5091 | .pa_start = 0x5a000000, | |
5092 | .pa_end = 0x5a07ffff, | |
5093 | .flags = ADDR_TYPE_RT | |
5094 | }, | |
5095 | { } | |
5096 | }; | |
5097 | ||
5098 | /* l3_main_2 -> iva */ | |
5099 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { | |
5100 | .master = &omap44xx_l3_main_2_hwmod, | |
5101 | .slave = &omap44xx_iva_hwmod, | |
5102 | .clk = "l3_div_ck", | |
5103 | .addr = omap44xx_iva_addrs, | |
5104 | .user = OCP_USER_MPU, | |
5105 | }; | |
5106 | ||
5107 | static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { | |
5108 | { | |
5109 | .pa_start = 0x4a31c000, | |
5110 | .pa_end = 0x4a31c07f, | |
5111 | .flags = ADDR_TYPE_RT | |
5112 | }, | |
5113 | { } | |
5114 | }; | |
5115 | ||
5116 | /* l4_wkup -> kbd */ | |
5117 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { | |
5118 | .master = &omap44xx_l4_wkup_hwmod, | |
5119 | .slave = &omap44xx_kbd_hwmod, | |
5120 | .clk = "l4_wkup_clk_mux_ck", | |
5121 | .addr = omap44xx_kbd_addrs, | |
5122 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5123 | }; | |
5124 | ||
5125 | static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { | |
5126 | { | |
5127 | .pa_start = 0x4a0f4000, | |
5128 | .pa_end = 0x4a0f41ff, | |
5129 | .flags = ADDR_TYPE_RT | |
5130 | }, | |
5131 | { } | |
5132 | }; | |
5133 | ||
5134 | /* l4_cfg -> mailbox */ | |
5135 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { | |
5136 | .master = &omap44xx_l4_cfg_hwmod, | |
5137 | .slave = &omap44xx_mailbox_hwmod, | |
5138 | .clk = "l4_div_ck", | |
5139 | .addr = omap44xx_mailbox_addrs, | |
5140 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5141 | }; | |
5142 | ||
896d4e98 BC |
5143 | static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = { |
5144 | { | |
5145 | .pa_start = 0x40128000, | |
5146 | .pa_end = 0x401283ff, | |
5147 | .flags = ADDR_TYPE_RT | |
5148 | }, | |
5149 | { } | |
5150 | }; | |
5151 | ||
5152 | /* l4_abe -> mcasp */ | |
5153 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = { | |
5154 | .master = &omap44xx_l4_abe_hwmod, | |
5155 | .slave = &omap44xx_mcasp_hwmod, | |
5156 | .clk = "ocp_abe_iclk", | |
5157 | .addr = omap44xx_mcasp_addrs, | |
5158 | .user = OCP_USER_MPU, | |
5159 | }; | |
5160 | ||
5161 | static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = { | |
5162 | { | |
5163 | .pa_start = 0x49028000, | |
5164 | .pa_end = 0x490283ff, | |
5165 | .flags = ADDR_TYPE_RT | |
5166 | }, | |
5167 | { } | |
5168 | }; | |
5169 | ||
5170 | /* l4_abe -> mcasp (dma) */ | |
5171 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = { | |
5172 | .master = &omap44xx_l4_abe_hwmod, | |
5173 | .slave = &omap44xx_mcasp_hwmod, | |
5174 | .clk = "ocp_abe_iclk", | |
5175 | .addr = omap44xx_mcasp_dma_addrs, | |
5176 | .user = OCP_USER_SDMA, | |
5177 | }; | |
5178 | ||
844a3b63 PW |
5179 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { |
5180 | { | |
5181 | .name = "mpu", | |
5182 | .pa_start = 0x40122000, | |
5183 | .pa_end = 0x401220ff, | |
5184 | .flags = ADDR_TYPE_RT | |
5185 | }, | |
5186 | { } | |
5187 | }; | |
5188 | ||
5189 | /* l4_abe -> mcbsp1 */ | |
5190 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { | |
5191 | .master = &omap44xx_l4_abe_hwmod, | |
5192 | .slave = &omap44xx_mcbsp1_hwmod, | |
5193 | .clk = "ocp_abe_iclk", | |
5194 | .addr = omap44xx_mcbsp1_addrs, | |
5195 | .user = OCP_USER_MPU, | |
5196 | }; | |
5197 | ||
5198 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { | |
5199 | { | |
5200 | .name = "dma", | |
5201 | .pa_start = 0x49022000, | |
5202 | .pa_end = 0x490220ff, | |
5203 | .flags = ADDR_TYPE_RT | |
5204 | }, | |
5205 | { } | |
5206 | }; | |
5207 | ||
5208 | /* l4_abe -> mcbsp1 (dma) */ | |
5209 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { | |
5210 | .master = &omap44xx_l4_abe_hwmod, | |
5211 | .slave = &omap44xx_mcbsp1_hwmod, | |
5212 | .clk = "ocp_abe_iclk", | |
5213 | .addr = omap44xx_mcbsp1_dma_addrs, | |
5214 | .user = OCP_USER_SDMA, | |
5215 | }; | |
5216 | ||
5217 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { | |
5218 | { | |
5219 | .name = "mpu", | |
5220 | .pa_start = 0x40124000, | |
5221 | .pa_end = 0x401240ff, | |
5222 | .flags = ADDR_TYPE_RT | |
5223 | }, | |
5224 | { } | |
5225 | }; | |
5226 | ||
5227 | /* l4_abe -> mcbsp2 */ | |
5228 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { | |
5229 | .master = &omap44xx_l4_abe_hwmod, | |
5230 | .slave = &omap44xx_mcbsp2_hwmod, | |
5231 | .clk = "ocp_abe_iclk", | |
5232 | .addr = omap44xx_mcbsp2_addrs, | |
5233 | .user = OCP_USER_MPU, | |
5234 | }; | |
5235 | ||
5236 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { | |
5237 | { | |
5238 | .name = "dma", | |
5239 | .pa_start = 0x49024000, | |
5240 | .pa_end = 0x490240ff, | |
5241 | .flags = ADDR_TYPE_RT | |
5242 | }, | |
5243 | { } | |
5244 | }; | |
5245 | ||
5246 | /* l4_abe -> mcbsp2 (dma) */ | |
5247 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { | |
5248 | .master = &omap44xx_l4_abe_hwmod, | |
5249 | .slave = &omap44xx_mcbsp2_hwmod, | |
5250 | .clk = "ocp_abe_iclk", | |
5251 | .addr = omap44xx_mcbsp2_dma_addrs, | |
5252 | .user = OCP_USER_SDMA, | |
5253 | }; | |
5254 | ||
5255 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { | |
5256 | { | |
5257 | .name = "mpu", | |
5258 | .pa_start = 0x40126000, | |
5259 | .pa_end = 0x401260ff, | |
5260 | .flags = ADDR_TYPE_RT | |
5261 | }, | |
5262 | { } | |
5263 | }; | |
5264 | ||
5265 | /* l4_abe -> mcbsp3 */ | |
5266 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { | |
5267 | .master = &omap44xx_l4_abe_hwmod, | |
5268 | .slave = &omap44xx_mcbsp3_hwmod, | |
5269 | .clk = "ocp_abe_iclk", | |
5270 | .addr = omap44xx_mcbsp3_addrs, | |
5271 | .user = OCP_USER_MPU, | |
5272 | }; | |
5273 | ||
5274 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { | |
5275 | { | |
5276 | .name = "dma", | |
5277 | .pa_start = 0x49026000, | |
5278 | .pa_end = 0x490260ff, | |
5279 | .flags = ADDR_TYPE_RT | |
5280 | }, | |
5281 | { } | |
5282 | }; | |
5283 | ||
5284 | /* l4_abe -> mcbsp3 (dma) */ | |
5285 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { | |
5286 | .master = &omap44xx_l4_abe_hwmod, | |
5287 | .slave = &omap44xx_mcbsp3_hwmod, | |
5288 | .clk = "ocp_abe_iclk", | |
5289 | .addr = omap44xx_mcbsp3_dma_addrs, | |
5290 | .user = OCP_USER_SDMA, | |
5291 | }; | |
5292 | ||
5293 | static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { | |
5294 | { | |
5295 | .pa_start = 0x48096000, | |
5296 | .pa_end = 0x480960ff, | |
5297 | .flags = ADDR_TYPE_RT | |
5298 | }, | |
5299 | { } | |
5300 | }; | |
5301 | ||
5302 | /* l4_per -> mcbsp4 */ | |
5303 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { | |
5304 | .master = &omap44xx_l4_per_hwmod, | |
5305 | .slave = &omap44xx_mcbsp4_hwmod, | |
5306 | .clk = "l4_div_ck", | |
5307 | .addr = omap44xx_mcbsp4_addrs, | |
5308 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5309 | }; | |
5310 | ||
5311 | static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { | |
5312 | { | |
acd08ecd | 5313 | .name = "mpu", |
844a3b63 PW |
5314 | .pa_start = 0x40132000, |
5315 | .pa_end = 0x4013207f, | |
5316 | .flags = ADDR_TYPE_RT | |
5317 | }, | |
5318 | { } | |
5319 | }; | |
5320 | ||
5321 | /* l4_abe -> mcpdm */ | |
5322 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { | |
5323 | .master = &omap44xx_l4_abe_hwmod, | |
5324 | .slave = &omap44xx_mcpdm_hwmod, | |
5325 | .clk = "ocp_abe_iclk", | |
5326 | .addr = omap44xx_mcpdm_addrs, | |
5327 | .user = OCP_USER_MPU, | |
5328 | }; | |
5329 | ||
5330 | static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { | |
5331 | { | |
acd08ecd | 5332 | .name = "dma", |
844a3b63 PW |
5333 | .pa_start = 0x49032000, |
5334 | .pa_end = 0x4903207f, | |
5335 | .flags = ADDR_TYPE_RT | |
5336 | }, | |
5337 | { } | |
5338 | }; | |
5339 | ||
5340 | /* l4_abe -> mcpdm (dma) */ | |
5341 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { | |
5342 | .master = &omap44xx_l4_abe_hwmod, | |
5343 | .slave = &omap44xx_mcpdm_hwmod, | |
5344 | .clk = "ocp_abe_iclk", | |
5345 | .addr = omap44xx_mcpdm_dma_addrs, | |
5346 | .user = OCP_USER_SDMA, | |
5347 | }; | |
5348 | ||
5349 | static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { | |
5350 | { | |
5351 | .pa_start = 0x48098000, | |
5352 | .pa_end = 0x480981ff, | |
5353 | .flags = ADDR_TYPE_RT | |
5354 | }, | |
5355 | { } | |
5356 | }; | |
5357 | ||
5358 | /* l4_per -> mcspi1 */ | |
5359 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { | |
5360 | .master = &omap44xx_l4_per_hwmod, | |
5361 | .slave = &omap44xx_mcspi1_hwmod, | |
5362 | .clk = "l4_div_ck", | |
5363 | .addr = omap44xx_mcspi1_addrs, | |
5364 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5365 | }; | |
5366 | ||
5367 | static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { | |
5368 | { | |
5369 | .pa_start = 0x4809a000, | |
5370 | .pa_end = 0x4809a1ff, | |
5371 | .flags = ADDR_TYPE_RT | |
5372 | }, | |
5373 | { } | |
5374 | }; | |
5375 | ||
5376 | /* l4_per -> mcspi2 */ | |
5377 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { | |
5378 | .master = &omap44xx_l4_per_hwmod, | |
5379 | .slave = &omap44xx_mcspi2_hwmod, | |
5380 | .clk = "l4_div_ck", | |
5381 | .addr = omap44xx_mcspi2_addrs, | |
5382 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5383 | }; | |
5384 | ||
5385 | static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { | |
5386 | { | |
5387 | .pa_start = 0x480b8000, | |
5388 | .pa_end = 0x480b81ff, | |
5389 | .flags = ADDR_TYPE_RT | |
5390 | }, | |
5391 | { } | |
5392 | }; | |
5393 | ||
5394 | /* l4_per -> mcspi3 */ | |
5395 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { | |
5396 | .master = &omap44xx_l4_per_hwmod, | |
5397 | .slave = &omap44xx_mcspi3_hwmod, | |
5398 | .clk = "l4_div_ck", | |
5399 | .addr = omap44xx_mcspi3_addrs, | |
5400 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5401 | }; | |
5402 | ||
5403 | static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { | |
5404 | { | |
5405 | .pa_start = 0x480ba000, | |
5406 | .pa_end = 0x480ba1ff, | |
5407 | .flags = ADDR_TYPE_RT | |
5408 | }, | |
5409 | { } | |
5410 | }; | |
5411 | ||
5412 | /* l4_per -> mcspi4 */ | |
5413 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { | |
5414 | .master = &omap44xx_l4_per_hwmod, | |
5415 | .slave = &omap44xx_mcspi4_hwmod, | |
5416 | .clk = "l4_div_ck", | |
5417 | .addr = omap44xx_mcspi4_addrs, | |
5418 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5419 | }; | |
5420 | ||
5421 | static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { | |
5422 | { | |
5423 | .pa_start = 0x4809c000, | |
5424 | .pa_end = 0x4809c3ff, | |
5425 | .flags = ADDR_TYPE_RT | |
5426 | }, | |
5427 | { } | |
5428 | }; | |
5429 | ||
5430 | /* l4_per -> mmc1 */ | |
5431 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { | |
5432 | .master = &omap44xx_l4_per_hwmod, | |
5433 | .slave = &omap44xx_mmc1_hwmod, | |
5434 | .clk = "l4_div_ck", | |
5435 | .addr = omap44xx_mmc1_addrs, | |
5436 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5437 | }; | |
5438 | ||
5439 | static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { | |
5440 | { | |
5441 | .pa_start = 0x480b4000, | |
5442 | .pa_end = 0x480b43ff, | |
5443 | .flags = ADDR_TYPE_RT | |
5444 | }, | |
5445 | { } | |
5446 | }; | |
5447 | ||
5448 | /* l4_per -> mmc2 */ | |
5449 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { | |
5450 | .master = &omap44xx_l4_per_hwmod, | |
5451 | .slave = &omap44xx_mmc2_hwmod, | |
5452 | .clk = "l4_div_ck", | |
5453 | .addr = omap44xx_mmc2_addrs, | |
5454 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5455 | }; | |
5456 | ||
5457 | static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { | |
5458 | { | |
5459 | .pa_start = 0x480ad000, | |
5460 | .pa_end = 0x480ad3ff, | |
5461 | .flags = ADDR_TYPE_RT | |
5462 | }, | |
5463 | { } | |
5464 | }; | |
5465 | ||
5466 | /* l4_per -> mmc3 */ | |
5467 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { | |
5468 | .master = &omap44xx_l4_per_hwmod, | |
5469 | .slave = &omap44xx_mmc3_hwmod, | |
5470 | .clk = "l4_div_ck", | |
5471 | .addr = omap44xx_mmc3_addrs, | |
5472 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5473 | }; | |
5474 | ||
5475 | static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { | |
5476 | { | |
5477 | .pa_start = 0x480d1000, | |
5478 | .pa_end = 0x480d13ff, | |
5479 | .flags = ADDR_TYPE_RT | |
5480 | }, | |
5481 | { } | |
5482 | }; | |
5483 | ||
5484 | /* l4_per -> mmc4 */ | |
5485 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { | |
5486 | .master = &omap44xx_l4_per_hwmod, | |
5487 | .slave = &omap44xx_mmc4_hwmod, | |
5488 | .clk = "l4_div_ck", | |
5489 | .addr = omap44xx_mmc4_addrs, | |
5490 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5491 | }; | |
5492 | ||
5493 | static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { | |
5494 | { | |
5495 | .pa_start = 0x480d5000, | |
5496 | .pa_end = 0x480d53ff, | |
5497 | .flags = ADDR_TYPE_RT | |
5498 | }, | |
5499 | { } | |
5500 | }; | |
5501 | ||
5502 | /* l4_per -> mmc5 */ | |
5503 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { | |
5504 | .master = &omap44xx_l4_per_hwmod, | |
5505 | .slave = &omap44xx_mmc5_hwmod, | |
5506 | .clk = "l4_div_ck", | |
5507 | .addr = omap44xx_mmc5_addrs, | |
5508 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5509 | }; | |
5510 | ||
e17f18c0 PW |
5511 | /* l3_main_2 -> ocmc_ram */ |
5512 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = { | |
5513 | .master = &omap44xx_l3_main_2_hwmod, | |
5514 | .slave = &omap44xx_ocmc_ram_hwmod, | |
5515 | .clk = "l3_div_ck", | |
5516 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5517 | }; | |
5518 | ||
33c976ec BC |
5519 | static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = { |
5520 | { | |
5521 | .pa_start = 0x4a0ad000, | |
5522 | .pa_end = 0x4a0ad01f, | |
5523 | .flags = ADDR_TYPE_RT | |
5524 | }, | |
5525 | { } | |
5526 | }; | |
5527 | ||
0c668875 BC |
5528 | /* l4_cfg -> ocp2scp_usb_phy */ |
5529 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = { | |
5530 | .master = &omap44xx_l4_cfg_hwmod, | |
5531 | .slave = &omap44xx_ocp2scp_usb_phy_hwmod, | |
5532 | .clk = "l4_div_ck", | |
33c976ec | 5533 | .addr = omap44xx_ocp2scp_usb_phy_addrs, |
0c668875 BC |
5534 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
5535 | }; | |
5536 | ||
794b480a PW |
5537 | static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = { |
5538 | { | |
5539 | .pa_start = 0x48243000, | |
5540 | .pa_end = 0x48243fff, | |
5541 | .flags = ADDR_TYPE_RT | |
5542 | }, | |
5543 | { } | |
5544 | }; | |
5545 | ||
5546 | /* mpu_private -> prcm_mpu */ | |
5547 | static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = { | |
5548 | .master = &omap44xx_mpu_private_hwmod, | |
5549 | .slave = &omap44xx_prcm_mpu_hwmod, | |
5550 | .clk = "l3_div_ck", | |
5551 | .addr = omap44xx_prcm_mpu_addrs, | |
5552 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5553 | }; | |
5554 | ||
5555 | static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = { | |
5556 | { | |
5557 | .pa_start = 0x4a004000, | |
5558 | .pa_end = 0x4a004fff, | |
5559 | .flags = ADDR_TYPE_RT | |
5560 | }, | |
5561 | { } | |
5562 | }; | |
5563 | ||
5564 | /* l4_wkup -> cm_core_aon */ | |
5565 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = { | |
5566 | .master = &omap44xx_l4_wkup_hwmod, | |
5567 | .slave = &omap44xx_cm_core_aon_hwmod, | |
5568 | .clk = "l4_wkup_clk_mux_ck", | |
5569 | .addr = omap44xx_cm_core_aon_addrs, | |
5570 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5571 | }; | |
5572 | ||
5573 | static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = { | |
5574 | { | |
5575 | .pa_start = 0x4a008000, | |
5576 | .pa_end = 0x4a009fff, | |
5577 | .flags = ADDR_TYPE_RT | |
5578 | }, | |
5579 | { } | |
5580 | }; | |
5581 | ||
5582 | /* l4_cfg -> cm_core */ | |
5583 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = { | |
5584 | .master = &omap44xx_l4_cfg_hwmod, | |
5585 | .slave = &omap44xx_cm_core_hwmod, | |
5586 | .clk = "l4_div_ck", | |
5587 | .addr = omap44xx_cm_core_addrs, | |
5588 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5589 | }; | |
5590 | ||
5591 | static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = { | |
5592 | { | |
5593 | .pa_start = 0x4a306000, | |
5594 | .pa_end = 0x4a307fff, | |
5595 | .flags = ADDR_TYPE_RT | |
5596 | }, | |
5597 | { } | |
5598 | }; | |
5599 | ||
5600 | /* l4_wkup -> prm */ | |
5601 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = { | |
5602 | .master = &omap44xx_l4_wkup_hwmod, | |
5603 | .slave = &omap44xx_prm_hwmod, | |
5604 | .clk = "l4_wkup_clk_mux_ck", | |
5605 | .addr = omap44xx_prm_addrs, | |
5606 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5607 | }; | |
5608 | ||
5609 | static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = { | |
5610 | { | |
5611 | .pa_start = 0x4a30a000, | |
5612 | .pa_end = 0x4a30a7ff, | |
5613 | .flags = ADDR_TYPE_RT | |
5614 | }, | |
5615 | { } | |
5616 | }; | |
5617 | ||
5618 | /* l4_wkup -> scrm */ | |
5619 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = { | |
5620 | .master = &omap44xx_l4_wkup_hwmod, | |
5621 | .slave = &omap44xx_scrm_hwmod, | |
5622 | .clk = "l4_wkup_clk_mux_ck", | |
5623 | .addr = omap44xx_scrm_addrs, | |
5624 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5625 | }; | |
5626 | ||
42b9e387 | 5627 | /* l3_main_2 -> sl2if */ |
b360124e | 5628 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = { |
42b9e387 PW |
5629 | .master = &omap44xx_l3_main_2_hwmod, |
5630 | .slave = &omap44xx_sl2if_hwmod, | |
5631 | .clk = "l3_div_ck", | |
5632 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5633 | }; | |
5634 | ||
1e3b5e59 BC |
5635 | static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = { |
5636 | { | |
5637 | .pa_start = 0x4012c000, | |
5638 | .pa_end = 0x4012c3ff, | |
5639 | .flags = ADDR_TYPE_RT | |
5640 | }, | |
5641 | { } | |
5642 | }; | |
5643 | ||
5644 | /* l4_abe -> slimbus1 */ | |
5645 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = { | |
5646 | .master = &omap44xx_l4_abe_hwmod, | |
5647 | .slave = &omap44xx_slimbus1_hwmod, | |
5648 | .clk = "ocp_abe_iclk", | |
5649 | .addr = omap44xx_slimbus1_addrs, | |
5650 | .user = OCP_USER_MPU, | |
5651 | }; | |
5652 | ||
5653 | static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = { | |
5654 | { | |
5655 | .pa_start = 0x4902c000, | |
5656 | .pa_end = 0x4902c3ff, | |
5657 | .flags = ADDR_TYPE_RT | |
5658 | }, | |
5659 | { } | |
5660 | }; | |
5661 | ||
5662 | /* l4_abe -> slimbus1 (dma) */ | |
5663 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = { | |
5664 | .master = &omap44xx_l4_abe_hwmod, | |
5665 | .slave = &omap44xx_slimbus1_hwmod, | |
5666 | .clk = "ocp_abe_iclk", | |
5667 | .addr = omap44xx_slimbus1_dma_addrs, | |
5668 | .user = OCP_USER_SDMA, | |
5669 | }; | |
5670 | ||
5671 | static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = { | |
5672 | { | |
5673 | .pa_start = 0x48076000, | |
5674 | .pa_end = 0x480763ff, | |
5675 | .flags = ADDR_TYPE_RT | |
5676 | }, | |
5677 | { } | |
5678 | }; | |
5679 | ||
5680 | /* l4_per -> slimbus2 */ | |
5681 | static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = { | |
5682 | .master = &omap44xx_l4_per_hwmod, | |
5683 | .slave = &omap44xx_slimbus2_hwmod, | |
5684 | .clk = "l4_div_ck", | |
5685 | .addr = omap44xx_slimbus2_addrs, | |
5686 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5687 | }; | |
5688 | ||
844a3b63 PW |
5689 | static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { |
5690 | { | |
5691 | .pa_start = 0x4a0dd000, | |
5692 | .pa_end = 0x4a0dd03f, | |
5693 | .flags = ADDR_TYPE_RT | |
5694 | }, | |
5695 | { } | |
5696 | }; | |
5697 | ||
5698 | /* l4_cfg -> smartreflex_core */ | |
5699 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { | |
5700 | .master = &omap44xx_l4_cfg_hwmod, | |
5701 | .slave = &omap44xx_smartreflex_core_hwmod, | |
5702 | .clk = "l4_div_ck", | |
5703 | .addr = omap44xx_smartreflex_core_addrs, | |
5704 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5705 | }; | |
5706 | ||
5707 | static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { | |
5708 | { | |
5709 | .pa_start = 0x4a0db000, | |
5710 | .pa_end = 0x4a0db03f, | |
5711 | .flags = ADDR_TYPE_RT | |
5712 | }, | |
5713 | { } | |
5714 | }; | |
5715 | ||
5716 | /* l4_cfg -> smartreflex_iva */ | |
5717 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { | |
5718 | .master = &omap44xx_l4_cfg_hwmod, | |
5719 | .slave = &omap44xx_smartreflex_iva_hwmod, | |
5720 | .clk = "l4_div_ck", | |
5721 | .addr = omap44xx_smartreflex_iva_addrs, | |
5722 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5723 | }; | |
5724 | ||
5725 | static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { | |
5726 | { | |
5727 | .pa_start = 0x4a0d9000, | |
5728 | .pa_end = 0x4a0d903f, | |
5729 | .flags = ADDR_TYPE_RT | |
5730 | }, | |
5731 | { } | |
5732 | }; | |
5733 | ||
5734 | /* l4_cfg -> smartreflex_mpu */ | |
5735 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { | |
5736 | .master = &omap44xx_l4_cfg_hwmod, | |
5737 | .slave = &omap44xx_smartreflex_mpu_hwmod, | |
5738 | .clk = "l4_div_ck", | |
5739 | .addr = omap44xx_smartreflex_mpu_addrs, | |
5740 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5741 | }; | |
5742 | ||
5743 | static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { | |
5744 | { | |
5745 | .pa_start = 0x4a0f6000, | |
5746 | .pa_end = 0x4a0f6fff, | |
5747 | .flags = ADDR_TYPE_RT | |
5748 | }, | |
5749 | { } | |
5750 | }; | |
5751 | ||
5752 | /* l4_cfg -> spinlock */ | |
5753 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { | |
5754 | .master = &omap44xx_l4_cfg_hwmod, | |
5755 | .slave = &omap44xx_spinlock_hwmod, | |
5756 | .clk = "l4_div_ck", | |
5757 | .addr = omap44xx_spinlock_addrs, | |
5758 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5759 | }; | |
5760 | ||
5761 | static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { | |
5762 | { | |
5763 | .pa_start = 0x4a318000, | |
5764 | .pa_end = 0x4a31807f, | |
5765 | .flags = ADDR_TYPE_RT | |
5766 | }, | |
5767 | { } | |
5768 | }; | |
5769 | ||
5770 | /* l4_wkup -> timer1 */ | |
5771 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { | |
5772 | .master = &omap44xx_l4_wkup_hwmod, | |
5773 | .slave = &omap44xx_timer1_hwmod, | |
5774 | .clk = "l4_wkup_clk_mux_ck", | |
5775 | .addr = omap44xx_timer1_addrs, | |
5776 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5777 | }; | |
5778 | ||
5779 | static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { | |
5780 | { | |
5781 | .pa_start = 0x48032000, | |
5782 | .pa_end = 0x4803207f, | |
5783 | .flags = ADDR_TYPE_RT | |
5784 | }, | |
5785 | { } | |
5786 | }; | |
5787 | ||
5788 | /* l4_per -> timer2 */ | |
5789 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { | |
5790 | .master = &omap44xx_l4_per_hwmod, | |
5791 | .slave = &omap44xx_timer2_hwmod, | |
5792 | .clk = "l4_div_ck", | |
5793 | .addr = omap44xx_timer2_addrs, | |
5794 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5795 | }; | |
5796 | ||
5797 | static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { | |
5798 | { | |
5799 | .pa_start = 0x48034000, | |
5800 | .pa_end = 0x4803407f, | |
5801 | .flags = ADDR_TYPE_RT | |
5802 | }, | |
5803 | { } | |
5804 | }; | |
5805 | ||
5806 | /* l4_per -> timer3 */ | |
5807 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { | |
5808 | .master = &omap44xx_l4_per_hwmod, | |
5809 | .slave = &omap44xx_timer3_hwmod, | |
5810 | .clk = "l4_div_ck", | |
5811 | .addr = omap44xx_timer3_addrs, | |
5812 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5813 | }; | |
5814 | ||
5815 | static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { | |
5816 | { | |
5817 | .pa_start = 0x48036000, | |
5818 | .pa_end = 0x4803607f, | |
5819 | .flags = ADDR_TYPE_RT | |
5820 | }, | |
5821 | { } | |
5822 | }; | |
5823 | ||
5824 | /* l4_per -> timer4 */ | |
5825 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { | |
5826 | .master = &omap44xx_l4_per_hwmod, | |
5827 | .slave = &omap44xx_timer4_hwmod, | |
5828 | .clk = "l4_div_ck", | |
5829 | .addr = omap44xx_timer4_addrs, | |
5830 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5831 | }; | |
5832 | ||
5833 | static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { | |
5834 | { | |
5835 | .pa_start = 0x40138000, | |
5836 | .pa_end = 0x4013807f, | |
5837 | .flags = ADDR_TYPE_RT | |
5838 | }, | |
5839 | { } | |
5840 | }; | |
5841 | ||
5842 | /* l4_abe -> timer5 */ | |
5843 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { | |
5844 | .master = &omap44xx_l4_abe_hwmod, | |
5845 | .slave = &omap44xx_timer5_hwmod, | |
5846 | .clk = "ocp_abe_iclk", | |
5847 | .addr = omap44xx_timer5_addrs, | |
5848 | .user = OCP_USER_MPU, | |
5849 | }; | |
5850 | ||
5851 | static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { | |
5852 | { | |
5853 | .pa_start = 0x49038000, | |
5854 | .pa_end = 0x4903807f, | |
5855 | .flags = ADDR_TYPE_RT | |
5856 | }, | |
5857 | { } | |
5858 | }; | |
5859 | ||
5860 | /* l4_abe -> timer5 (dma) */ | |
5861 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { | |
5862 | .master = &omap44xx_l4_abe_hwmod, | |
5863 | .slave = &omap44xx_timer5_hwmod, | |
5864 | .clk = "ocp_abe_iclk", | |
5865 | .addr = omap44xx_timer5_dma_addrs, | |
5866 | .user = OCP_USER_SDMA, | |
5867 | }; | |
5868 | ||
5869 | static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { | |
5870 | { | |
5871 | .pa_start = 0x4013a000, | |
5872 | .pa_end = 0x4013a07f, | |
5873 | .flags = ADDR_TYPE_RT | |
5874 | }, | |
5875 | { } | |
5876 | }; | |
5877 | ||
5878 | /* l4_abe -> timer6 */ | |
5879 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { | |
5880 | .master = &omap44xx_l4_abe_hwmod, | |
5881 | .slave = &omap44xx_timer6_hwmod, | |
5882 | .clk = "ocp_abe_iclk", | |
5883 | .addr = omap44xx_timer6_addrs, | |
5884 | .user = OCP_USER_MPU, | |
5885 | }; | |
5886 | ||
5887 | static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { | |
5888 | { | |
5889 | .pa_start = 0x4903a000, | |
5890 | .pa_end = 0x4903a07f, | |
5891 | .flags = ADDR_TYPE_RT | |
5892 | }, | |
5893 | { } | |
5894 | }; | |
5895 | ||
5896 | /* l4_abe -> timer6 (dma) */ | |
5897 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { | |
5898 | .master = &omap44xx_l4_abe_hwmod, | |
5899 | .slave = &omap44xx_timer6_hwmod, | |
5900 | .clk = "ocp_abe_iclk", | |
5901 | .addr = omap44xx_timer6_dma_addrs, | |
5902 | .user = OCP_USER_SDMA, | |
5903 | }; | |
5904 | ||
5905 | static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { | |
5906 | { | |
5907 | .pa_start = 0x4013c000, | |
5908 | .pa_end = 0x4013c07f, | |
5909 | .flags = ADDR_TYPE_RT | |
5910 | }, | |
5911 | { } | |
5912 | }; | |
5913 | ||
5914 | /* l4_abe -> timer7 */ | |
5915 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { | |
5916 | .master = &omap44xx_l4_abe_hwmod, | |
5917 | .slave = &omap44xx_timer7_hwmod, | |
5918 | .clk = "ocp_abe_iclk", | |
5919 | .addr = omap44xx_timer7_addrs, | |
5920 | .user = OCP_USER_MPU, | |
5921 | }; | |
5922 | ||
5923 | static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { | |
5924 | { | |
5925 | .pa_start = 0x4903c000, | |
5926 | .pa_end = 0x4903c07f, | |
5927 | .flags = ADDR_TYPE_RT | |
5928 | }, | |
5929 | { } | |
5930 | }; | |
5931 | ||
5932 | /* l4_abe -> timer7 (dma) */ | |
5933 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { | |
5934 | .master = &omap44xx_l4_abe_hwmod, | |
5935 | .slave = &omap44xx_timer7_hwmod, | |
5936 | .clk = "ocp_abe_iclk", | |
5937 | .addr = omap44xx_timer7_dma_addrs, | |
5938 | .user = OCP_USER_SDMA, | |
5939 | }; | |
5940 | ||
5941 | static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { | |
5942 | { | |
5943 | .pa_start = 0x4013e000, | |
5944 | .pa_end = 0x4013e07f, | |
5945 | .flags = ADDR_TYPE_RT | |
5946 | }, | |
5947 | { } | |
5948 | }; | |
5949 | ||
5950 | /* l4_abe -> timer8 */ | |
5951 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { | |
5952 | .master = &omap44xx_l4_abe_hwmod, | |
5953 | .slave = &omap44xx_timer8_hwmod, | |
5954 | .clk = "ocp_abe_iclk", | |
5955 | .addr = omap44xx_timer8_addrs, | |
5956 | .user = OCP_USER_MPU, | |
5957 | }; | |
5958 | ||
5959 | static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { | |
5960 | { | |
5961 | .pa_start = 0x4903e000, | |
5962 | .pa_end = 0x4903e07f, | |
5963 | .flags = ADDR_TYPE_RT | |
5964 | }, | |
5965 | { } | |
5966 | }; | |
5967 | ||
5968 | /* l4_abe -> timer8 (dma) */ | |
5969 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { | |
5970 | .master = &omap44xx_l4_abe_hwmod, | |
5971 | .slave = &omap44xx_timer8_hwmod, | |
5972 | .clk = "ocp_abe_iclk", | |
5973 | .addr = omap44xx_timer8_dma_addrs, | |
5974 | .user = OCP_USER_SDMA, | |
5975 | }; | |
5976 | ||
5977 | static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { | |
5978 | { | |
5979 | .pa_start = 0x4803e000, | |
5980 | .pa_end = 0x4803e07f, | |
5981 | .flags = ADDR_TYPE_RT | |
5982 | }, | |
5983 | { } | |
5984 | }; | |
5985 | ||
5986 | /* l4_per -> timer9 */ | |
5987 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { | |
5988 | .master = &omap44xx_l4_per_hwmod, | |
5989 | .slave = &omap44xx_timer9_hwmod, | |
5990 | .clk = "l4_div_ck", | |
5991 | .addr = omap44xx_timer9_addrs, | |
5992 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5993 | }; | |
5994 | ||
5995 | static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { | |
5996 | { | |
5997 | .pa_start = 0x48086000, | |
5998 | .pa_end = 0x4808607f, | |
5999 | .flags = ADDR_TYPE_RT | |
6000 | }, | |
6001 | { } | |
6002 | }; | |
6003 | ||
6004 | /* l4_per -> timer10 */ | |
6005 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { | |
6006 | .master = &omap44xx_l4_per_hwmod, | |
6007 | .slave = &omap44xx_timer10_hwmod, | |
6008 | .clk = "l4_div_ck", | |
6009 | .addr = omap44xx_timer10_addrs, | |
6010 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
6011 | }; | |
6012 | ||
6013 | static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { | |
6014 | { | |
6015 | .pa_start = 0x48088000, | |
6016 | .pa_end = 0x4808807f, | |
6017 | .flags = ADDR_TYPE_RT | |
6018 | }, | |
6019 | { } | |
6020 | }; | |
6021 | ||
6022 | /* l4_per -> timer11 */ | |
6023 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { | |
6024 | .master = &omap44xx_l4_per_hwmod, | |
6025 | .slave = &omap44xx_timer11_hwmod, | |
6026 | .clk = "l4_div_ck", | |
6027 | .addr = omap44xx_timer11_addrs, | |
af88fa9a BC |
6028 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
6029 | }; | |
6030 | ||
844a3b63 PW |
6031 | static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { |
6032 | { | |
6033 | .pa_start = 0x4806a000, | |
6034 | .pa_end = 0x4806a0ff, | |
6035 | .flags = ADDR_TYPE_RT | |
af88fa9a | 6036 | }, |
844a3b63 PW |
6037 | { } |
6038 | }; | |
af88fa9a | 6039 | |
844a3b63 PW |
6040 | /* l4_per -> uart1 */ |
6041 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { | |
6042 | .master = &omap44xx_l4_per_hwmod, | |
6043 | .slave = &omap44xx_uart1_hwmod, | |
6044 | .clk = "l4_div_ck", | |
6045 | .addr = omap44xx_uart1_addrs, | |
6046 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
6047 | }; | |
af88fa9a | 6048 | |
844a3b63 PW |
6049 | static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { |
6050 | { | |
6051 | .pa_start = 0x4806c000, | |
6052 | .pa_end = 0x4806c0ff, | |
6053 | .flags = ADDR_TYPE_RT | |
6054 | }, | |
6055 | { } | |
6056 | }; | |
af88fa9a | 6057 | |
844a3b63 PW |
6058 | /* l4_per -> uart2 */ |
6059 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { | |
6060 | .master = &omap44xx_l4_per_hwmod, | |
6061 | .slave = &omap44xx_uart2_hwmod, | |
6062 | .clk = "l4_div_ck", | |
6063 | .addr = omap44xx_uart2_addrs, | |
6064 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
6065 | }; | |
af88fa9a | 6066 | |
844a3b63 PW |
6067 | static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { |
6068 | { | |
6069 | .pa_start = 0x48020000, | |
6070 | .pa_end = 0x480200ff, | |
6071 | .flags = ADDR_TYPE_RT | |
6072 | }, | |
6073 | { } | |
af88fa9a BC |
6074 | }; |
6075 | ||
844a3b63 PW |
6076 | /* l4_per -> uart3 */ |
6077 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { | |
6078 | .master = &omap44xx_l4_per_hwmod, | |
6079 | .slave = &omap44xx_uart3_hwmod, | |
6080 | .clk = "l4_div_ck", | |
6081 | .addr = omap44xx_uart3_addrs, | |
6082 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
af88fa9a BC |
6083 | }; |
6084 | ||
844a3b63 PW |
6085 | static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { |
6086 | { | |
6087 | .pa_start = 0x4806e000, | |
6088 | .pa_end = 0x4806e0ff, | |
6089 | .flags = ADDR_TYPE_RT | |
6090 | }, | |
6091 | { } | |
af88fa9a BC |
6092 | }; |
6093 | ||
844a3b63 PW |
6094 | /* l4_per -> uart4 */ |
6095 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { | |
6096 | .master = &omap44xx_l4_per_hwmod, | |
6097 | .slave = &omap44xx_uart4_hwmod, | |
6098 | .clk = "l4_div_ck", | |
6099 | .addr = omap44xx_uart4_addrs, | |
6100 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
6101 | }; | |
6102 | ||
0c668875 BC |
6103 | static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = { |
6104 | { | |
6105 | .pa_start = 0x4a0a9000, | |
6106 | .pa_end = 0x4a0a93ff, | |
6107 | .flags = ADDR_TYPE_RT | |
6108 | }, | |
6109 | { } | |
6110 | }; | |
6111 | ||
6112 | /* l4_cfg -> usb_host_fs */ | |
b0a70cc8 | 6113 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = { |
0c668875 BC |
6114 | .master = &omap44xx_l4_cfg_hwmod, |
6115 | .slave = &omap44xx_usb_host_fs_hwmod, | |
6116 | .clk = "l4_div_ck", | |
6117 | .addr = omap44xx_usb_host_fs_addrs, | |
6118 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
6119 | }; | |
6120 | ||
844a3b63 PW |
6121 | static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { |
6122 | { | |
6123 | .name = "uhh", | |
6124 | .pa_start = 0x4a064000, | |
6125 | .pa_end = 0x4a0647ff, | |
6126 | .flags = ADDR_TYPE_RT | |
6127 | }, | |
6128 | { | |
6129 | .name = "ohci", | |
6130 | .pa_start = 0x4a064800, | |
6131 | .pa_end = 0x4a064bff, | |
6132 | }, | |
6133 | { | |
6134 | .name = "ehci", | |
6135 | .pa_start = 0x4a064c00, | |
6136 | .pa_end = 0x4a064fff, | |
6137 | }, | |
6138 | {} | |
6139 | }; | |
6140 | ||
6141 | /* l4_cfg -> usb_host_hs */ | |
6142 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { | |
6143 | .master = &omap44xx_l4_cfg_hwmod, | |
6144 | .slave = &omap44xx_usb_host_hs_hwmod, | |
6145 | .clk = "l4_div_ck", | |
6146 | .addr = omap44xx_usb_host_hs_addrs, | |
6147 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
6148 | }; | |
6149 | ||
6150 | static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { | |
6151 | { | |
6152 | .pa_start = 0x4a0ab000, | |
33c976ec | 6153 | .pa_end = 0x4a0ab7ff, |
844a3b63 PW |
6154 | .flags = ADDR_TYPE_RT |
6155 | }, | |
94715d59 KVA |
6156 | { |
6157 | /* XXX: Remove this once control module driver is in place */ | |
6158 | .pa_start = 0x4a00233c, | |
6159 | .pa_end = 0x4a00233f, | |
6160 | .flags = ADDR_TYPE_RT | |
6161 | }, | |
844a3b63 PW |
6162 | { } |
6163 | }; | |
6164 | ||
6165 | /* l4_cfg -> usb_otg_hs */ | |
6166 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { | |
6167 | .master = &omap44xx_l4_cfg_hwmod, | |
6168 | .slave = &omap44xx_usb_otg_hs_hwmod, | |
6169 | .clk = "l4_div_ck", | |
6170 | .addr = omap44xx_usb_otg_hs_addrs, | |
6171 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
af88fa9a BC |
6172 | }; |
6173 | ||
6174 | static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { | |
6175 | { | |
6176 | .name = "tll", | |
6177 | .pa_start = 0x4a062000, | |
6178 | .pa_end = 0x4a063fff, | |
6179 | .flags = ADDR_TYPE_RT | |
6180 | }, | |
6181 | {} | |
6182 | }; | |
6183 | ||
844a3b63 | 6184 | /* l4_cfg -> usb_tll_hs */ |
af88fa9a BC |
6185 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { |
6186 | .master = &omap44xx_l4_cfg_hwmod, | |
6187 | .slave = &omap44xx_usb_tll_hs_hwmod, | |
6188 | .clk = "l4_div_ck", | |
6189 | .addr = omap44xx_usb_tll_hs_addrs, | |
6190 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
6191 | }; | |
6192 | ||
844a3b63 PW |
6193 | static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { |
6194 | { | |
6195 | .pa_start = 0x4a314000, | |
6196 | .pa_end = 0x4a31407f, | |
6197 | .flags = ADDR_TYPE_RT | |
af88fa9a | 6198 | }, |
844a3b63 PW |
6199 | { } |
6200 | }; | |
6201 | ||
6202 | /* l4_wkup -> wd_timer2 */ | |
6203 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { | |
6204 | .master = &omap44xx_l4_wkup_hwmod, | |
6205 | .slave = &omap44xx_wd_timer2_hwmod, | |
6206 | .clk = "l4_wkup_clk_mux_ck", | |
6207 | .addr = omap44xx_wd_timer2_addrs, | |
6208 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
6209 | }; | |
6210 | ||
6211 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { | |
6212 | { | |
6213 | .pa_start = 0x40130000, | |
6214 | .pa_end = 0x4013007f, | |
6215 | .flags = ADDR_TYPE_RT | |
6216 | }, | |
6217 | { } | |
6218 | }; | |
6219 | ||
6220 | /* l4_abe -> wd_timer3 */ | |
6221 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { | |
6222 | .master = &omap44xx_l4_abe_hwmod, | |
6223 | .slave = &omap44xx_wd_timer3_hwmod, | |
6224 | .clk = "ocp_abe_iclk", | |
6225 | .addr = omap44xx_wd_timer3_addrs, | |
6226 | .user = OCP_USER_MPU, | |
6227 | }; | |
6228 | ||
6229 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { | |
6230 | { | |
6231 | .pa_start = 0x49030000, | |
6232 | .pa_end = 0x4903007f, | |
6233 | .flags = ADDR_TYPE_RT | |
6234 | }, | |
6235 | { } | |
6236 | }; | |
6237 | ||
6238 | /* l4_abe -> wd_timer3 (dma) */ | |
6239 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { | |
6240 | .master = &omap44xx_l4_abe_hwmod, | |
6241 | .slave = &omap44xx_wd_timer3_hwmod, | |
6242 | .clk = "ocp_abe_iclk", | |
6243 | .addr = omap44xx_wd_timer3_dma_addrs, | |
6244 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
6245 | }; |
6246 | ||
0a78c5c5 | 6247 | static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { |
42b9e387 PW |
6248 | &omap44xx_c2c__c2c_target_fw, |
6249 | &omap44xx_l4_cfg__c2c_target_fw, | |
0a78c5c5 PW |
6250 | &omap44xx_l3_main_1__dmm, |
6251 | &omap44xx_mpu__dmm, | |
42b9e387 | 6252 | &omap44xx_c2c__emif_fw, |
0a78c5c5 PW |
6253 | &omap44xx_dmm__emif_fw, |
6254 | &omap44xx_l4_cfg__emif_fw, | |
6255 | &omap44xx_iva__l3_instr, | |
6256 | &omap44xx_l3_main_3__l3_instr, | |
9a817bc8 | 6257 | &omap44xx_ocp_wp_noc__l3_instr, |
0a78c5c5 PW |
6258 | &omap44xx_dsp__l3_main_1, |
6259 | &omap44xx_dss__l3_main_1, | |
6260 | &omap44xx_l3_main_2__l3_main_1, | |
6261 | &omap44xx_l4_cfg__l3_main_1, | |
6262 | &omap44xx_mmc1__l3_main_1, | |
6263 | &omap44xx_mmc2__l3_main_1, | |
6264 | &omap44xx_mpu__l3_main_1, | |
42b9e387 | 6265 | &omap44xx_c2c_target_fw__l3_main_2, |
96566043 | 6266 | &omap44xx_debugss__l3_main_2, |
0a78c5c5 | 6267 | &omap44xx_dma_system__l3_main_2, |
b050f688 | 6268 | &omap44xx_fdif__l3_main_2, |
9def390e | 6269 | &omap44xx_gpu__l3_main_2, |
0a78c5c5 PW |
6270 | &omap44xx_hsi__l3_main_2, |
6271 | &omap44xx_ipu__l3_main_2, | |
6272 | &omap44xx_iss__l3_main_2, | |
6273 | &omap44xx_iva__l3_main_2, | |
6274 | &omap44xx_l3_main_1__l3_main_2, | |
6275 | &omap44xx_l4_cfg__l3_main_2, | |
b0a70cc8 | 6276 | /* &omap44xx_usb_host_fs__l3_main_2, */ |
0a78c5c5 PW |
6277 | &omap44xx_usb_host_hs__l3_main_2, |
6278 | &omap44xx_usb_otg_hs__l3_main_2, | |
6279 | &omap44xx_l3_main_1__l3_main_3, | |
6280 | &omap44xx_l3_main_2__l3_main_3, | |
6281 | &omap44xx_l4_cfg__l3_main_3, | |
b0a70cc8 | 6282 | /* &omap44xx_aess__l4_abe, */ |
0a78c5c5 PW |
6283 | &omap44xx_dsp__l4_abe, |
6284 | &omap44xx_l3_main_1__l4_abe, | |
6285 | &omap44xx_mpu__l4_abe, | |
6286 | &omap44xx_l3_main_1__l4_cfg, | |
6287 | &omap44xx_l3_main_2__l4_per, | |
6288 | &omap44xx_l4_cfg__l4_wkup, | |
6289 | &omap44xx_mpu__mpu_private, | |
9a817bc8 | 6290 | &omap44xx_l4_cfg__ocp_wp_noc, |
b0a70cc8 PW |
6291 | /* &omap44xx_l4_abe__aess, */ |
6292 | /* &omap44xx_l4_abe__aess_dma, */ | |
42b9e387 | 6293 | &omap44xx_l3_main_2__c2c, |
0a78c5c5 | 6294 | &omap44xx_l4_wkup__counter_32k, |
a0b5d813 PW |
6295 | &omap44xx_l4_cfg__ctrl_module_core, |
6296 | &omap44xx_l4_cfg__ctrl_module_pad_core, | |
6297 | &omap44xx_l4_wkup__ctrl_module_wkup, | |
6298 | &omap44xx_l4_wkup__ctrl_module_pad_wkup, | |
96566043 | 6299 | &omap44xx_l3_instr__debugss, |
0a78c5c5 PW |
6300 | &omap44xx_l4_cfg__dma_system, |
6301 | &omap44xx_l4_abe__dmic, | |
6302 | &omap44xx_l4_abe__dmic_dma, | |
6303 | &omap44xx_dsp__iva, | |
b360124e | 6304 | /* &omap44xx_dsp__sl2if, */ |
0a78c5c5 PW |
6305 | &omap44xx_l4_cfg__dsp, |
6306 | &omap44xx_l3_main_2__dss, | |
6307 | &omap44xx_l4_per__dss, | |
6308 | &omap44xx_l3_main_2__dss_dispc, | |
6309 | &omap44xx_l4_per__dss_dispc, | |
6310 | &omap44xx_l3_main_2__dss_dsi1, | |
6311 | &omap44xx_l4_per__dss_dsi1, | |
6312 | &omap44xx_l3_main_2__dss_dsi2, | |
6313 | &omap44xx_l4_per__dss_dsi2, | |
6314 | &omap44xx_l3_main_2__dss_hdmi, | |
6315 | &omap44xx_l4_per__dss_hdmi, | |
6316 | &omap44xx_l3_main_2__dss_rfbi, | |
6317 | &omap44xx_l4_per__dss_rfbi, | |
6318 | &omap44xx_l3_main_2__dss_venc, | |
6319 | &omap44xx_l4_per__dss_venc, | |
42b9e387 | 6320 | &omap44xx_l4_per__elm, |
bf30f950 PW |
6321 | &omap44xx_emif_fw__emif1, |
6322 | &omap44xx_emif_fw__emif2, | |
b050f688 | 6323 | &omap44xx_l4_cfg__fdif, |
0a78c5c5 PW |
6324 | &omap44xx_l4_wkup__gpio1, |
6325 | &omap44xx_l4_per__gpio2, | |
6326 | &omap44xx_l4_per__gpio3, | |
6327 | &omap44xx_l4_per__gpio4, | |
6328 | &omap44xx_l4_per__gpio5, | |
6329 | &omap44xx_l4_per__gpio6, | |
eb42b5d3 | 6330 | &omap44xx_l3_main_2__gpmc, |
9def390e | 6331 | &omap44xx_l3_main_2__gpu, |
a091c08e | 6332 | &omap44xx_l4_per__hdq1w, |
0a78c5c5 PW |
6333 | &omap44xx_l4_cfg__hsi, |
6334 | &omap44xx_l4_per__i2c1, | |
6335 | &omap44xx_l4_per__i2c2, | |
6336 | &omap44xx_l4_per__i2c3, | |
6337 | &omap44xx_l4_per__i2c4, | |
6338 | &omap44xx_l3_main_2__ipu, | |
6339 | &omap44xx_l3_main_2__iss, | |
b360124e | 6340 | /* &omap44xx_iva__sl2if, */ |
0a78c5c5 PW |
6341 | &omap44xx_l3_main_2__iva, |
6342 | &omap44xx_l4_wkup__kbd, | |
6343 | &omap44xx_l4_cfg__mailbox, | |
896d4e98 BC |
6344 | &omap44xx_l4_abe__mcasp, |
6345 | &omap44xx_l4_abe__mcasp_dma, | |
0a78c5c5 PW |
6346 | &omap44xx_l4_abe__mcbsp1, |
6347 | &omap44xx_l4_abe__mcbsp1_dma, | |
6348 | &omap44xx_l4_abe__mcbsp2, | |
6349 | &omap44xx_l4_abe__mcbsp2_dma, | |
6350 | &omap44xx_l4_abe__mcbsp3, | |
6351 | &omap44xx_l4_abe__mcbsp3_dma, | |
6352 | &omap44xx_l4_per__mcbsp4, | |
6353 | &omap44xx_l4_abe__mcpdm, | |
6354 | &omap44xx_l4_abe__mcpdm_dma, | |
6355 | &omap44xx_l4_per__mcspi1, | |
6356 | &omap44xx_l4_per__mcspi2, | |
6357 | &omap44xx_l4_per__mcspi3, | |
6358 | &omap44xx_l4_per__mcspi4, | |
6359 | &omap44xx_l4_per__mmc1, | |
6360 | &omap44xx_l4_per__mmc2, | |
6361 | &omap44xx_l4_per__mmc3, | |
6362 | &omap44xx_l4_per__mmc4, | |
6363 | &omap44xx_l4_per__mmc5, | |
230844db ORL |
6364 | &omap44xx_l3_main_2__mmu_ipu, |
6365 | &omap44xx_l4_cfg__mmu_dsp, | |
e17f18c0 | 6366 | &omap44xx_l3_main_2__ocmc_ram, |
0c668875 | 6367 | &omap44xx_l4_cfg__ocp2scp_usb_phy, |
794b480a PW |
6368 | &omap44xx_mpu_private__prcm_mpu, |
6369 | &omap44xx_l4_wkup__cm_core_aon, | |
6370 | &omap44xx_l4_cfg__cm_core, | |
6371 | &omap44xx_l4_wkup__prm, | |
6372 | &omap44xx_l4_wkup__scrm, | |
b360124e | 6373 | /* &omap44xx_l3_main_2__sl2if, */ |
1e3b5e59 BC |
6374 | &omap44xx_l4_abe__slimbus1, |
6375 | &omap44xx_l4_abe__slimbus1_dma, | |
6376 | &omap44xx_l4_per__slimbus2, | |
0a78c5c5 PW |
6377 | &omap44xx_l4_cfg__smartreflex_core, |
6378 | &omap44xx_l4_cfg__smartreflex_iva, | |
6379 | &omap44xx_l4_cfg__smartreflex_mpu, | |
6380 | &omap44xx_l4_cfg__spinlock, | |
6381 | &omap44xx_l4_wkup__timer1, | |
6382 | &omap44xx_l4_per__timer2, | |
6383 | &omap44xx_l4_per__timer3, | |
6384 | &omap44xx_l4_per__timer4, | |
6385 | &omap44xx_l4_abe__timer5, | |
6386 | &omap44xx_l4_abe__timer5_dma, | |
6387 | &omap44xx_l4_abe__timer6, | |
6388 | &omap44xx_l4_abe__timer6_dma, | |
6389 | &omap44xx_l4_abe__timer7, | |
6390 | &omap44xx_l4_abe__timer7_dma, | |
6391 | &omap44xx_l4_abe__timer8, | |
6392 | &omap44xx_l4_abe__timer8_dma, | |
6393 | &omap44xx_l4_per__timer9, | |
6394 | &omap44xx_l4_per__timer10, | |
6395 | &omap44xx_l4_per__timer11, | |
6396 | &omap44xx_l4_per__uart1, | |
6397 | &omap44xx_l4_per__uart2, | |
6398 | &omap44xx_l4_per__uart3, | |
6399 | &omap44xx_l4_per__uart4, | |
b0a70cc8 | 6400 | /* &omap44xx_l4_cfg__usb_host_fs, */ |
0a78c5c5 PW |
6401 | &omap44xx_l4_cfg__usb_host_hs, |
6402 | &omap44xx_l4_cfg__usb_otg_hs, | |
6403 | &omap44xx_l4_cfg__usb_tll_hs, | |
6404 | &omap44xx_l4_wkup__wd_timer2, | |
6405 | &omap44xx_l4_abe__wd_timer3, | |
6406 | &omap44xx_l4_abe__wd_timer3_dma, | |
55d2cb08 BC |
6407 | NULL, |
6408 | }; | |
6409 | ||
6410 | int __init omap44xx_hwmod_init(void) | |
6411 | { | |
9ebfd285 | 6412 | omap_hwmod_init(); |
0a78c5c5 | 6413 | return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); |
55d2cb08 BC |
6414 | } |
6415 |