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55d2cb08 BC |
1 | /* |
2 | * Hardware modules present on the OMAP44xx chips | |
3 | * | |
0a78c5c5 | 4 | * Copyright (C) 2009-2012 Texas Instruments, Inc. |
55d2cb08 BC |
5 | * Copyright (C) 2009-2010 Nokia Corporation |
6 | * | |
7 | * Paul Walmsley | |
8 | * Benoit Cousson | |
9 | * | |
10 | * This file is automatically generated from the OMAP hardware databases. | |
11 | * We respectfully ask that any modifications to this file be coordinated | |
12 | * with the public linux-omap@vger.kernel.org mailing list and the | |
13 | * authors above to ensure that the autogeneration scripts are kept | |
14 | * up-to-date with the file contents. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/io.h> | |
4b25408f | 22 | #include <linux/platform_data/gpio-omap.h> |
b86aeafc | 23 | #include <linux/power/smartreflex.h> |
55d2cb08 BC |
24 | |
25 | #include <plat/omap_hwmod.h> | |
6d3c55fd | 26 | #include <plat/i2c.h> |
531ce0d5 | 27 | #include <plat/dma.h> |
905a74d9 | 28 | #include <plat/mcspi.h> |
cb7e9ded | 29 | #include <plat/mcbsp.h> |
6ab8946f | 30 | #include <plat/mmc.h> |
c345c8b0 | 31 | #include <plat/dmtimer.h> |
13662dc5 | 32 | #include <plat/common.h> |
230844db | 33 | #include <plat/iommu.h> |
55d2cb08 BC |
34 | |
35 | #include "omap_hwmod_common_data.h" | |
d198b514 PW |
36 | #include "cm1_44xx.h" |
37 | #include "cm2_44xx.h" | |
38 | #include "prm44xx.h" | |
55d2cb08 | 39 | #include "prm-regbits-44xx.h" |
ff2516fb | 40 | #include "wd_timer.h" |
55d2cb08 BC |
41 | |
42 | /* Base offset for all OMAP4 interrupts external to MPUSS */ | |
43 | #define OMAP44XX_IRQ_GIC_START 32 | |
44 | ||
45 | /* Base offset for all OMAP4 dma requests */ | |
844a3b63 | 46 | #define OMAP44XX_DMA_REQ_START 1 |
55d2cb08 BC |
47 | |
48 | /* | |
844a3b63 | 49 | * IP blocks |
55d2cb08 BC |
50 | */ |
51 | ||
42b9e387 PW |
52 | /* |
53 | * 'c2c_target_fw' class | |
54 | * instance(s): c2c_target_fw | |
55 | */ | |
56 | static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = { | |
57 | .name = "c2c_target_fw", | |
58 | }; | |
59 | ||
60 | /* c2c_target_fw */ | |
61 | static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = { | |
62 | .name = "c2c_target_fw", | |
63 | .class = &omap44xx_c2c_target_fw_hwmod_class, | |
64 | .clkdm_name = "d2d_clkdm", | |
65 | .prcm = { | |
66 | .omap4 = { | |
67 | .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET, | |
68 | .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET, | |
69 | }, | |
70 | }, | |
71 | }; | |
72 | ||
55d2cb08 BC |
73 | /* |
74 | * 'dmm' class | |
75 | * instance(s): dmm | |
76 | */ | |
77 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { | |
fe13471c | 78 | .name = "dmm", |
55d2cb08 BC |
79 | }; |
80 | ||
7e69ed97 BC |
81 | /* dmm */ |
82 | static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { | |
83 | { .irq = 113 + OMAP44XX_IRQ_GIC_START }, | |
84 | { .irq = -1 } | |
85 | }; | |
86 | ||
55d2cb08 BC |
87 | static struct omap_hwmod omap44xx_dmm_hwmod = { |
88 | .name = "dmm", | |
89 | .class = &omap44xx_dmm_hwmod_class, | |
a5322c6f | 90 | .clkdm_name = "l3_emif_clkdm", |
844a3b63 | 91 | .mpu_irqs = omap44xx_dmm_irqs, |
d0f0631d BC |
92 | .prcm = { |
93 | .omap4 = { | |
94 | .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, | |
27bb00b5 | 95 | .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, |
d0f0631d BC |
96 | }, |
97 | }, | |
55d2cb08 BC |
98 | }; |
99 | ||
100 | /* | |
101 | * 'emif_fw' class | |
102 | * instance(s): emif_fw | |
103 | */ | |
104 | static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { | |
fe13471c | 105 | .name = "emif_fw", |
55d2cb08 BC |
106 | }; |
107 | ||
7e69ed97 | 108 | /* emif_fw */ |
55d2cb08 BC |
109 | static struct omap_hwmod omap44xx_emif_fw_hwmod = { |
110 | .name = "emif_fw", | |
111 | .class = &omap44xx_emif_fw_hwmod_class, | |
a5322c6f | 112 | .clkdm_name = "l3_emif_clkdm", |
d0f0631d BC |
113 | .prcm = { |
114 | .omap4 = { | |
115 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET, | |
27bb00b5 | 116 | .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET, |
d0f0631d BC |
117 | }, |
118 | }, | |
55d2cb08 BC |
119 | }; |
120 | ||
121 | /* | |
122 | * 'l3' class | |
123 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 | |
124 | */ | |
125 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { | |
fe13471c | 126 | .name = "l3", |
55d2cb08 BC |
127 | }; |
128 | ||
7e69ed97 | 129 | /* l3_instr */ |
55d2cb08 BC |
130 | static struct omap_hwmod omap44xx_l3_instr_hwmod = { |
131 | .name = "l3_instr", | |
132 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 133 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
134 | .prcm = { |
135 | .omap4 = { | |
136 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, | |
27bb00b5 | 137 | .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, |
03fdefe5 | 138 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
139 | }, |
140 | }, | |
55d2cb08 BC |
141 | }; |
142 | ||
7e69ed97 | 143 | /* l3_main_1 */ |
9b4021be BC |
144 | static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = { |
145 | { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START }, | |
146 | { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START }, | |
147 | { .irq = -1 } | |
148 | }; | |
149 | ||
55d2cb08 BC |
150 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { |
151 | .name = "l3_main_1", | |
152 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 153 | .clkdm_name = "l3_1_clkdm", |
7e69ed97 | 154 | .mpu_irqs = omap44xx_l3_main_1_irqs, |
d0f0631d BC |
155 | .prcm = { |
156 | .omap4 = { | |
157 | .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, | |
27bb00b5 | 158 | .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, |
d0f0631d BC |
159 | }, |
160 | }, | |
55d2cb08 BC |
161 | }; |
162 | ||
7e69ed97 | 163 | /* l3_main_2 */ |
55d2cb08 BC |
164 | static struct omap_hwmod omap44xx_l3_main_2_hwmod = { |
165 | .name = "l3_main_2", | |
166 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 167 | .clkdm_name = "l3_2_clkdm", |
d0f0631d BC |
168 | .prcm = { |
169 | .omap4 = { | |
170 | .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET, | |
27bb00b5 | 171 | .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, |
d0f0631d BC |
172 | }, |
173 | }, | |
55d2cb08 BC |
174 | }; |
175 | ||
7e69ed97 | 176 | /* l3_main_3 */ |
55d2cb08 BC |
177 | static struct omap_hwmod omap44xx_l3_main_3_hwmod = { |
178 | .name = "l3_main_3", | |
179 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 180 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
181 | .prcm = { |
182 | .omap4 = { | |
183 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET, | |
27bb00b5 | 184 | .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET, |
03fdefe5 | 185 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
186 | }, |
187 | }, | |
55d2cb08 BC |
188 | }; |
189 | ||
190 | /* | |
191 | * 'l4' class | |
192 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup | |
193 | */ | |
194 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { | |
fe13471c | 195 | .name = "l4", |
55d2cb08 BC |
196 | }; |
197 | ||
7e69ed97 | 198 | /* l4_abe */ |
55d2cb08 BC |
199 | static struct omap_hwmod omap44xx_l4_abe_hwmod = { |
200 | .name = "l4_abe", | |
201 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 202 | .clkdm_name = "abe_clkdm", |
d0f0631d BC |
203 | .prcm = { |
204 | .omap4 = { | |
205 | .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, | |
ce80979a TK |
206 | .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, |
207 | .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK, | |
46b3af27 | 208 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, |
d0f0631d BC |
209 | }, |
210 | }, | |
55d2cb08 BC |
211 | }; |
212 | ||
7e69ed97 | 213 | /* l4_cfg */ |
55d2cb08 BC |
214 | static struct omap_hwmod omap44xx_l4_cfg_hwmod = { |
215 | .name = "l4_cfg", | |
216 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 217 | .clkdm_name = "l4_cfg_clkdm", |
d0f0631d BC |
218 | .prcm = { |
219 | .omap4 = { | |
220 | .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, | |
27bb00b5 | 221 | .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, |
d0f0631d BC |
222 | }, |
223 | }, | |
55d2cb08 BC |
224 | }; |
225 | ||
7e69ed97 | 226 | /* l4_per */ |
55d2cb08 BC |
227 | static struct omap_hwmod omap44xx_l4_per_hwmod = { |
228 | .name = "l4_per", | |
229 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 230 | .clkdm_name = "l4_per_clkdm", |
d0f0631d BC |
231 | .prcm = { |
232 | .omap4 = { | |
233 | .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET, | |
27bb00b5 | 234 | .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, |
d0f0631d BC |
235 | }, |
236 | }, | |
55d2cb08 BC |
237 | }; |
238 | ||
7e69ed97 | 239 | /* l4_wkup */ |
55d2cb08 BC |
240 | static struct omap_hwmod omap44xx_l4_wkup_hwmod = { |
241 | .name = "l4_wkup", | |
242 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 243 | .clkdm_name = "l4_wkup_clkdm", |
d0f0631d BC |
244 | .prcm = { |
245 | .omap4 = { | |
246 | .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, | |
27bb00b5 | 247 | .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, |
d0f0631d BC |
248 | }, |
249 | }, | |
55d2cb08 BC |
250 | }; |
251 | ||
f776471f | 252 | /* |
3b54baad BC |
253 | * 'mpu_bus' class |
254 | * instance(s): mpu_private | |
f776471f | 255 | */ |
3b54baad | 256 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { |
fe13471c | 257 | .name = "mpu_bus", |
3b54baad | 258 | }; |
f776471f | 259 | |
7e69ed97 | 260 | /* mpu_private */ |
3b54baad BC |
261 | static struct omap_hwmod omap44xx_mpu_private_hwmod = { |
262 | .name = "mpu_private", | |
263 | .class = &omap44xx_mpu_bus_hwmod_class, | |
a5322c6f | 264 | .clkdm_name = "mpuss_clkdm", |
46b3af27 TK |
265 | .prcm = { |
266 | .omap4 = { | |
267 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
268 | }, | |
269 | }, | |
3b54baad BC |
270 | }; |
271 | ||
9a817bc8 BC |
272 | /* |
273 | * 'ocp_wp_noc' class | |
274 | * instance(s): ocp_wp_noc | |
275 | */ | |
276 | static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = { | |
277 | .name = "ocp_wp_noc", | |
278 | }; | |
279 | ||
280 | /* ocp_wp_noc */ | |
281 | static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = { | |
282 | .name = "ocp_wp_noc", | |
283 | .class = &omap44xx_ocp_wp_noc_hwmod_class, | |
284 | .clkdm_name = "l3_instr_clkdm", | |
285 | .prcm = { | |
286 | .omap4 = { | |
287 | .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET, | |
288 | .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET, | |
289 | .modulemode = MODULEMODE_HWCTRL, | |
290 | }, | |
291 | }, | |
292 | }; | |
293 | ||
3b54baad BC |
294 | /* |
295 | * Modules omap_hwmod structures | |
296 | * | |
297 | * The following IPs are excluded for the moment because: | |
298 | * - They do not need an explicit SW control using omap_hwmod API. | |
299 | * - They still need to be validated with the driver | |
300 | * properly adapted to omap_hwmod / omap_device | |
301 | * | |
96566043 | 302 | * usim |
3b54baad BC |
303 | */ |
304 | ||
407a6888 BC |
305 | /* |
306 | * 'aess' class | |
307 | * audio engine sub system | |
308 | */ | |
309 | ||
310 | static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = { | |
311 | .rev_offs = 0x0000, | |
312 | .sysc_offs = 0x0010, | |
313 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
314 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
c614ebf6 BC |
315 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART | |
316 | MSTANDBY_SMART_WKUP), | |
407a6888 BC |
317 | .sysc_fields = &omap_hwmod_sysc_type2, |
318 | }; | |
319 | ||
320 | static struct omap_hwmod_class omap44xx_aess_hwmod_class = { | |
321 | .name = "aess", | |
322 | .sysc = &omap44xx_aess_sysc, | |
323 | }; | |
324 | ||
325 | /* aess */ | |
326 | static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { | |
327 | { .irq = 99 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 328 | { .irq = -1 } |
407a6888 BC |
329 | }; |
330 | ||
331 | static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { | |
332 | { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START }, | |
333 | { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START }, | |
334 | { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START }, | |
335 | { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START }, | |
336 | { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START }, | |
337 | { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START }, | |
338 | { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START }, | |
339 | { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 340 | { .dma_req = -1 } |
407a6888 BC |
341 | }; |
342 | ||
407a6888 BC |
343 | static struct omap_hwmod omap44xx_aess_hwmod = { |
344 | .name = "aess", | |
345 | .class = &omap44xx_aess_hwmod_class, | |
a5322c6f | 346 | .clkdm_name = "abe_clkdm", |
407a6888 | 347 | .mpu_irqs = omap44xx_aess_irqs, |
407a6888 | 348 | .sdma_reqs = omap44xx_aess_sdma_reqs, |
407a6888 | 349 | .main_clk = "aess_fck", |
00fe610b | 350 | .prcm = { |
407a6888 | 351 | .omap4 = { |
d0f0631d | 352 | .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, |
27bb00b5 | 353 | .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, |
ce80979a | 354 | .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK, |
03fdefe5 | 355 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
356 | }, |
357 | }, | |
407a6888 BC |
358 | }; |
359 | ||
42b9e387 PW |
360 | /* |
361 | * 'c2c' class | |
362 | * chip 2 chip interface used to plug the ape soc (omap) with an external modem | |
363 | * soc | |
364 | */ | |
365 | ||
366 | static struct omap_hwmod_class omap44xx_c2c_hwmod_class = { | |
367 | .name = "c2c", | |
368 | }; | |
369 | ||
370 | /* c2c */ | |
371 | static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = { | |
372 | { .irq = 88 + OMAP44XX_IRQ_GIC_START }, | |
373 | { .irq = -1 } | |
374 | }; | |
375 | ||
376 | static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = { | |
377 | { .dma_req = 68 + OMAP44XX_DMA_REQ_START }, | |
378 | { .dma_req = -1 } | |
379 | }; | |
380 | ||
381 | static struct omap_hwmod omap44xx_c2c_hwmod = { | |
382 | .name = "c2c", | |
383 | .class = &omap44xx_c2c_hwmod_class, | |
384 | .clkdm_name = "d2d_clkdm", | |
385 | .mpu_irqs = omap44xx_c2c_irqs, | |
386 | .sdma_reqs = omap44xx_c2c_sdma_reqs, | |
387 | .prcm = { | |
388 | .omap4 = { | |
389 | .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET, | |
390 | .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET, | |
391 | }, | |
392 | }, | |
393 | }; | |
394 | ||
407a6888 BC |
395 | /* |
396 | * 'counter' class | |
397 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock | |
398 | */ | |
399 | ||
400 | static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = { | |
401 | .rev_offs = 0x0000, | |
402 | .sysc_offs = 0x0004, | |
403 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
252a4c54 | 404 | .idlemodes = (SIDLE_FORCE | SIDLE_NO), |
407a6888 BC |
405 | .sysc_fields = &omap_hwmod_sysc_type1, |
406 | }; | |
407 | ||
408 | static struct omap_hwmod_class omap44xx_counter_hwmod_class = { | |
409 | .name = "counter", | |
410 | .sysc = &omap44xx_counter_sysc, | |
411 | }; | |
412 | ||
413 | /* counter_32k */ | |
407a6888 BC |
414 | static struct omap_hwmod omap44xx_counter_32k_hwmod = { |
415 | .name = "counter_32k", | |
416 | .class = &omap44xx_counter_hwmod_class, | |
a5322c6f | 417 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 BC |
418 | .flags = HWMOD_SWSUP_SIDLE, |
419 | .main_clk = "sys_32k_ck", | |
00fe610b | 420 | .prcm = { |
407a6888 | 421 | .omap4 = { |
d0f0631d | 422 | .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, |
27bb00b5 | 423 | .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, |
407a6888 BC |
424 | }, |
425 | }, | |
407a6888 BC |
426 | }; |
427 | ||
a0b5d813 PW |
428 | /* |
429 | * 'ctrl_module' class | |
430 | * attila core control module + core pad control module + wkup pad control | |
431 | * module + attila wkup control module | |
432 | */ | |
433 | ||
434 | static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = { | |
435 | .rev_offs = 0x0000, | |
436 | .sysc_offs = 0x0010, | |
437 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
438 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
439 | SIDLE_SMART_WKUP), | |
440 | .sysc_fields = &omap_hwmod_sysc_type2, | |
441 | }; | |
442 | ||
443 | static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = { | |
444 | .name = "ctrl_module", | |
445 | .sysc = &omap44xx_ctrl_module_sysc, | |
446 | }; | |
447 | ||
448 | /* ctrl_module_core */ | |
449 | static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = { | |
450 | { .irq = 8 + OMAP44XX_IRQ_GIC_START }, | |
451 | { .irq = -1 } | |
452 | }; | |
453 | ||
454 | static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = { | |
455 | .name = "ctrl_module_core", | |
456 | .class = &omap44xx_ctrl_module_hwmod_class, | |
457 | .clkdm_name = "l4_cfg_clkdm", | |
458 | .mpu_irqs = omap44xx_ctrl_module_core_irqs, | |
46b3af27 TK |
459 | .prcm = { |
460 | .omap4 = { | |
461 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
462 | }, | |
463 | }, | |
a0b5d813 PW |
464 | }; |
465 | ||
466 | /* ctrl_module_pad_core */ | |
467 | static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = { | |
468 | .name = "ctrl_module_pad_core", | |
469 | .class = &omap44xx_ctrl_module_hwmod_class, | |
470 | .clkdm_name = "l4_cfg_clkdm", | |
46b3af27 TK |
471 | .prcm = { |
472 | .omap4 = { | |
473 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
474 | }, | |
475 | }, | |
a0b5d813 PW |
476 | }; |
477 | ||
478 | /* ctrl_module_wkup */ | |
479 | static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = { | |
480 | .name = "ctrl_module_wkup", | |
481 | .class = &omap44xx_ctrl_module_hwmod_class, | |
482 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
483 | .prcm = { |
484 | .omap4 = { | |
485 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
486 | }, | |
487 | }, | |
a0b5d813 PW |
488 | }; |
489 | ||
490 | /* ctrl_module_pad_wkup */ | |
491 | static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = { | |
492 | .name = "ctrl_module_pad_wkup", | |
493 | .class = &omap44xx_ctrl_module_hwmod_class, | |
494 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
495 | .prcm = { |
496 | .omap4 = { | |
497 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
498 | }, | |
499 | }, | |
a0b5d813 PW |
500 | }; |
501 | ||
96566043 BC |
502 | /* |
503 | * 'debugss' class | |
504 | * debug and emulation sub system | |
505 | */ | |
506 | ||
507 | static struct omap_hwmod_class omap44xx_debugss_hwmod_class = { | |
508 | .name = "debugss", | |
509 | }; | |
510 | ||
511 | /* debugss */ | |
512 | static struct omap_hwmod omap44xx_debugss_hwmod = { | |
513 | .name = "debugss", | |
514 | .class = &omap44xx_debugss_hwmod_class, | |
515 | .clkdm_name = "emu_sys_clkdm", | |
516 | .main_clk = "trace_clk_div_ck", | |
517 | .prcm = { | |
518 | .omap4 = { | |
519 | .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET, | |
520 | .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET, | |
521 | }, | |
522 | }, | |
523 | }; | |
524 | ||
d7cf5f33 BC |
525 | /* |
526 | * 'dma' class | |
527 | * dma controller for data exchange between memory to memory (i.e. internal or | |
528 | * external memory) and gp peripherals to memory or memory to gp peripherals | |
529 | */ | |
530 | ||
531 | static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { | |
532 | .rev_offs = 0x0000, | |
533 | .sysc_offs = 0x002c, | |
534 | .syss_offs = 0x0028, | |
535 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
536 | SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
537 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
538 | SYSS_HAS_RESET_STATUS), | |
539 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
540 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
541 | .sysc_fields = &omap_hwmod_sysc_type1, | |
542 | }; | |
543 | ||
544 | static struct omap_hwmod_class omap44xx_dma_hwmod_class = { | |
545 | .name = "dma", | |
546 | .sysc = &omap44xx_dma_sysc, | |
547 | }; | |
548 | ||
549 | /* dma dev_attr */ | |
550 | static struct omap_dma_dev_attr dma_dev_attr = { | |
551 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
552 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
553 | .lch_count = 32, | |
554 | }; | |
555 | ||
556 | /* dma_system */ | |
557 | static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { | |
558 | { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, | |
559 | { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, | |
560 | { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, | |
561 | { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 562 | { .irq = -1 } |
d7cf5f33 BC |
563 | }; |
564 | ||
d7cf5f33 BC |
565 | static struct omap_hwmod omap44xx_dma_system_hwmod = { |
566 | .name = "dma_system", | |
567 | .class = &omap44xx_dma_hwmod_class, | |
a5322c6f | 568 | .clkdm_name = "l3_dma_clkdm", |
d7cf5f33 | 569 | .mpu_irqs = omap44xx_dma_system_irqs, |
d7cf5f33 BC |
570 | .main_clk = "l3_div_ck", |
571 | .prcm = { | |
572 | .omap4 = { | |
d0f0631d | 573 | .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET, |
27bb00b5 | 574 | .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET, |
d7cf5f33 BC |
575 | }, |
576 | }, | |
577 | .dev_attr = &dma_dev_attr, | |
d7cf5f33 BC |
578 | }; |
579 | ||
8ca476da BC |
580 | /* |
581 | * 'dmic' class | |
582 | * digital microphone controller | |
583 | */ | |
584 | ||
585 | static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = { | |
586 | .rev_offs = 0x0000, | |
587 | .sysc_offs = 0x0010, | |
588 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
589 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
590 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
591 | SIDLE_SMART_WKUP), | |
592 | .sysc_fields = &omap_hwmod_sysc_type2, | |
593 | }; | |
594 | ||
595 | static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { | |
596 | .name = "dmic", | |
597 | .sysc = &omap44xx_dmic_sysc, | |
598 | }; | |
599 | ||
600 | /* dmic */ | |
8ca476da BC |
601 | static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { |
602 | { .irq = 114 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 603 | { .irq = -1 } |
8ca476da BC |
604 | }; |
605 | ||
606 | static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { | |
607 | { .dma_req = 66 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 608 | { .dma_req = -1 } |
8ca476da BC |
609 | }; |
610 | ||
8ca476da BC |
611 | static struct omap_hwmod omap44xx_dmic_hwmod = { |
612 | .name = "dmic", | |
613 | .class = &omap44xx_dmic_hwmod_class, | |
a5322c6f | 614 | .clkdm_name = "abe_clkdm", |
8ca476da | 615 | .mpu_irqs = omap44xx_dmic_irqs, |
8ca476da | 616 | .sdma_reqs = omap44xx_dmic_sdma_reqs, |
8ca476da | 617 | .main_clk = "dmic_fck", |
00fe610b | 618 | .prcm = { |
8ca476da | 619 | .omap4 = { |
d0f0631d | 620 | .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, |
27bb00b5 | 621 | .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET, |
03fdefe5 | 622 | .modulemode = MODULEMODE_SWCTRL, |
8ca476da BC |
623 | }, |
624 | }, | |
8ca476da BC |
625 | }; |
626 | ||
8f25bdc5 BC |
627 | /* |
628 | * 'dsp' class | |
629 | * dsp sub-system | |
630 | */ | |
631 | ||
632 | static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { | |
fe13471c | 633 | .name = "dsp", |
8f25bdc5 BC |
634 | }; |
635 | ||
636 | /* dsp */ | |
637 | static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { | |
638 | { .irq = 28 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 639 | { .irq = -1 } |
8f25bdc5 BC |
640 | }; |
641 | ||
642 | static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { | |
8f25bdc5 BC |
643 | { .name = "dsp", .rst_shift = 0 }, |
644 | }; | |
645 | ||
8f25bdc5 BC |
646 | static struct omap_hwmod omap44xx_dsp_hwmod = { |
647 | .name = "dsp", | |
648 | .class = &omap44xx_dsp_hwmod_class, | |
a5322c6f | 649 | .clkdm_name = "tesla_clkdm", |
8f25bdc5 | 650 | .mpu_irqs = omap44xx_dsp_irqs, |
8f25bdc5 BC |
651 | .rst_lines = omap44xx_dsp_resets, |
652 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), | |
653 | .main_clk = "dsp_fck", | |
654 | .prcm = { | |
655 | .omap4 = { | |
d0f0631d | 656 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, |
eaac329d | 657 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, |
27bb00b5 | 658 | .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, |
03fdefe5 | 659 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
660 | }, |
661 | }, | |
8f25bdc5 BC |
662 | }; |
663 | ||
d63bd74f BC |
664 | /* |
665 | * 'dss' class | |
666 | * display sub-system | |
667 | */ | |
668 | ||
669 | static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = { | |
670 | .rev_offs = 0x0000, | |
671 | .syss_offs = 0x0014, | |
672 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
673 | }; | |
674 | ||
675 | static struct omap_hwmod_class omap44xx_dss_hwmod_class = { | |
676 | .name = "dss", | |
677 | .sysc = &omap44xx_dss_sysc, | |
13662dc5 | 678 | .reset = omap_dss_reset, |
d63bd74f BC |
679 | }; |
680 | ||
681 | /* dss */ | |
d63bd74f BC |
682 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { |
683 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
684 | { .role = "tv_clk", .clk = "dss_tv_clk" }, | |
4d0698d9 | 685 | { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, |
d63bd74f BC |
686 | }; |
687 | ||
688 | static struct omap_hwmod omap44xx_dss_hwmod = { | |
689 | .name = "dss_core", | |
37ad0855 | 690 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
d63bd74f | 691 | .class = &omap44xx_dss_hwmod_class, |
a5322c6f | 692 | .clkdm_name = "l3_dss_clkdm", |
da7cdfac | 693 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
694 | .prcm = { |
695 | .omap4 = { | |
d0f0631d | 696 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 697 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
698 | }, |
699 | }, | |
700 | .opt_clks = dss_opt_clks, | |
701 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
d63bd74f BC |
702 | }; |
703 | ||
704 | /* | |
705 | * 'dispc' class | |
706 | * display controller | |
707 | */ | |
708 | ||
709 | static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = { | |
710 | .rev_offs = 0x0000, | |
711 | .sysc_offs = 0x0010, | |
712 | .syss_offs = 0x0014, | |
713 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
714 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | | |
715 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
716 | SYSS_HAS_RESET_STATUS), | |
717 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
718 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
719 | .sysc_fields = &omap_hwmod_sysc_type1, | |
720 | }; | |
721 | ||
722 | static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { | |
723 | .name = "dispc", | |
724 | .sysc = &omap44xx_dispc_sysc, | |
725 | }; | |
726 | ||
727 | /* dss_dispc */ | |
d63bd74f BC |
728 | static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { |
729 | { .irq = 25 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 730 | { .irq = -1 } |
d63bd74f BC |
731 | }; |
732 | ||
733 | static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { | |
734 | { .dma_req = 5 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 735 | { .dma_req = -1 } |
d63bd74f BC |
736 | }; |
737 | ||
b923d40d AT |
738 | static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { |
739 | .manager_count = 3, | |
740 | .has_framedonetv_irq = 1 | |
741 | }; | |
742 | ||
d63bd74f BC |
743 | static struct omap_hwmod omap44xx_dss_dispc_hwmod = { |
744 | .name = "dss_dispc", | |
745 | .class = &omap44xx_dispc_hwmod_class, | |
a5322c6f | 746 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 747 | .mpu_irqs = omap44xx_dss_dispc_irqs, |
d63bd74f | 748 | .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, |
da7cdfac | 749 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
750 | .prcm = { |
751 | .omap4 = { | |
d0f0631d | 752 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 753 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
754 | }, |
755 | }, | |
b923d40d | 756 | .dev_attr = &omap44xx_dss_dispc_dev_attr |
d63bd74f BC |
757 | }; |
758 | ||
759 | /* | |
760 | * 'dsi' class | |
761 | * display serial interface controller | |
762 | */ | |
763 | ||
764 | static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = { | |
765 | .rev_offs = 0x0000, | |
766 | .sysc_offs = 0x0010, | |
767 | .syss_offs = 0x0014, | |
768 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
769 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
770 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
771 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
772 | .sysc_fields = &omap_hwmod_sysc_type1, | |
773 | }; | |
774 | ||
775 | static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { | |
776 | .name = "dsi", | |
777 | .sysc = &omap44xx_dsi_sysc, | |
778 | }; | |
779 | ||
780 | /* dss_dsi1 */ | |
d63bd74f BC |
781 | static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { |
782 | { .irq = 53 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 783 | { .irq = -1 } |
d63bd74f BC |
784 | }; |
785 | ||
786 | static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { | |
787 | { .dma_req = 74 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 788 | { .dma_req = -1 } |
d63bd74f BC |
789 | }; |
790 | ||
3a23aafc TV |
791 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { |
792 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
793 | }; | |
794 | ||
d63bd74f BC |
795 | static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { |
796 | .name = "dss_dsi1", | |
797 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 798 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 799 | .mpu_irqs = omap44xx_dss_dsi1_irqs, |
d63bd74f | 800 | .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, |
da7cdfac | 801 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
802 | .prcm = { |
803 | .omap4 = { | |
d0f0631d | 804 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 805 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
806 | }, |
807 | }, | |
3a23aafc TV |
808 | .opt_clks = dss_dsi1_opt_clks, |
809 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
d63bd74f BC |
810 | }; |
811 | ||
812 | /* dss_dsi2 */ | |
d63bd74f BC |
813 | static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { |
814 | { .irq = 84 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 815 | { .irq = -1 } |
d63bd74f BC |
816 | }; |
817 | ||
818 | static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { | |
819 | { .dma_req = 83 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 820 | { .dma_req = -1 } |
d63bd74f BC |
821 | }; |
822 | ||
3a23aafc TV |
823 | static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { |
824 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
825 | }; | |
826 | ||
d63bd74f BC |
827 | static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { |
828 | .name = "dss_dsi2", | |
829 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 830 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 831 | .mpu_irqs = omap44xx_dss_dsi2_irqs, |
d63bd74f | 832 | .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, |
da7cdfac | 833 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
834 | .prcm = { |
835 | .omap4 = { | |
d0f0631d | 836 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 837 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
838 | }, |
839 | }, | |
3a23aafc TV |
840 | .opt_clks = dss_dsi2_opt_clks, |
841 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), | |
d63bd74f BC |
842 | }; |
843 | ||
844 | /* | |
845 | * 'hdmi' class | |
846 | * hdmi controller | |
847 | */ | |
848 | ||
849 | static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = { | |
850 | .rev_offs = 0x0000, | |
851 | .sysc_offs = 0x0010, | |
852 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
853 | SYSC_HAS_SOFTRESET), | |
854 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
855 | SIDLE_SMART_WKUP), | |
856 | .sysc_fields = &omap_hwmod_sysc_type2, | |
857 | }; | |
858 | ||
859 | static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { | |
860 | .name = "hdmi", | |
861 | .sysc = &omap44xx_hdmi_sysc, | |
862 | }; | |
863 | ||
864 | /* dss_hdmi */ | |
d63bd74f BC |
865 | static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { |
866 | { .irq = 101 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 867 | { .irq = -1 } |
d63bd74f BC |
868 | }; |
869 | ||
870 | static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { | |
871 | { .dma_req = 75 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 872 | { .dma_req = -1 } |
d63bd74f BC |
873 | }; |
874 | ||
3a23aafc TV |
875 | static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { |
876 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
877 | }; | |
878 | ||
d63bd74f BC |
879 | static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { |
880 | .name = "dss_hdmi", | |
881 | .class = &omap44xx_hdmi_hwmod_class, | |
a5322c6f | 882 | .clkdm_name = "l3_dss_clkdm", |
dc57aef5 RN |
883 | /* |
884 | * HDMI audio requires to use no-idle mode. Hence, | |
885 | * set idle mode by software. | |
886 | */ | |
887 | .flags = HWMOD_SWSUP_SIDLE, | |
d63bd74f | 888 | .mpu_irqs = omap44xx_dss_hdmi_irqs, |
d63bd74f | 889 | .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, |
4d0698d9 | 890 | .main_clk = "dss_48mhz_clk", |
d63bd74f BC |
891 | .prcm = { |
892 | .omap4 = { | |
d0f0631d | 893 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 894 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
895 | }, |
896 | }, | |
3a23aafc TV |
897 | .opt_clks = dss_hdmi_opt_clks, |
898 | .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), | |
d63bd74f BC |
899 | }; |
900 | ||
901 | /* | |
902 | * 'rfbi' class | |
903 | * remote frame buffer interface | |
904 | */ | |
905 | ||
906 | static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = { | |
907 | .rev_offs = 0x0000, | |
908 | .sysc_offs = 0x0010, | |
909 | .syss_offs = 0x0014, | |
910 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
911 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
912 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
913 | .sysc_fields = &omap_hwmod_sysc_type1, | |
914 | }; | |
915 | ||
916 | static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { | |
917 | .name = "rfbi", | |
918 | .sysc = &omap44xx_rfbi_sysc, | |
919 | }; | |
920 | ||
921 | /* dss_rfbi */ | |
d63bd74f BC |
922 | static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { |
923 | { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 924 | { .dma_req = -1 } |
d63bd74f BC |
925 | }; |
926 | ||
3a23aafc TV |
927 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
928 | { .role = "ick", .clk = "dss_fck" }, | |
929 | }; | |
930 | ||
d63bd74f BC |
931 | static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { |
932 | .name = "dss_rfbi", | |
933 | .class = &omap44xx_rfbi_hwmod_class, | |
a5322c6f | 934 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 935 | .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, |
da7cdfac | 936 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
937 | .prcm = { |
938 | .omap4 = { | |
d0f0631d | 939 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 940 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
941 | }, |
942 | }, | |
3a23aafc TV |
943 | .opt_clks = dss_rfbi_opt_clks, |
944 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
d63bd74f BC |
945 | }; |
946 | ||
947 | /* | |
948 | * 'venc' class | |
949 | * video encoder | |
950 | */ | |
951 | ||
952 | static struct omap_hwmod_class omap44xx_venc_hwmod_class = { | |
953 | .name = "venc", | |
954 | }; | |
955 | ||
956 | /* dss_venc */ | |
d63bd74f BC |
957 | static struct omap_hwmod omap44xx_dss_venc_hwmod = { |
958 | .name = "dss_venc", | |
959 | .class = &omap44xx_venc_hwmod_class, | |
a5322c6f | 960 | .clkdm_name = "l3_dss_clkdm", |
4d0698d9 | 961 | .main_clk = "dss_tv_clk", |
d63bd74f BC |
962 | .prcm = { |
963 | .omap4 = { | |
d0f0631d | 964 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 965 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
966 | }, |
967 | }, | |
d63bd74f BC |
968 | }; |
969 | ||
42b9e387 PW |
970 | /* |
971 | * 'elm' class | |
972 | * bch error location module | |
973 | */ | |
974 | ||
975 | static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = { | |
976 | .rev_offs = 0x0000, | |
977 | .sysc_offs = 0x0010, | |
978 | .syss_offs = 0x0014, | |
979 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
980 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
981 | SYSS_HAS_RESET_STATUS), | |
982 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
983 | .sysc_fields = &omap_hwmod_sysc_type1, | |
984 | }; | |
985 | ||
986 | static struct omap_hwmod_class omap44xx_elm_hwmod_class = { | |
987 | .name = "elm", | |
988 | .sysc = &omap44xx_elm_sysc, | |
989 | }; | |
990 | ||
991 | /* elm */ | |
992 | static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = { | |
993 | { .irq = 4 + OMAP44XX_IRQ_GIC_START }, | |
994 | { .irq = -1 } | |
995 | }; | |
996 | ||
997 | static struct omap_hwmod omap44xx_elm_hwmod = { | |
998 | .name = "elm", | |
999 | .class = &omap44xx_elm_hwmod_class, | |
1000 | .clkdm_name = "l4_per_clkdm", | |
1001 | .mpu_irqs = omap44xx_elm_irqs, | |
1002 | .prcm = { | |
1003 | .omap4 = { | |
1004 | .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET, | |
1005 | .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET, | |
1006 | }, | |
1007 | }, | |
1008 | }; | |
1009 | ||
bf30f950 PW |
1010 | /* |
1011 | * 'emif' class | |
1012 | * external memory interface no1 | |
1013 | */ | |
1014 | ||
1015 | static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = { | |
1016 | .rev_offs = 0x0000, | |
1017 | }; | |
1018 | ||
1019 | static struct omap_hwmod_class omap44xx_emif_hwmod_class = { | |
1020 | .name = "emif", | |
1021 | .sysc = &omap44xx_emif_sysc, | |
1022 | }; | |
1023 | ||
1024 | /* emif1 */ | |
1025 | static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = { | |
1026 | { .irq = 110 + OMAP44XX_IRQ_GIC_START }, | |
1027 | { .irq = -1 } | |
1028 | }; | |
1029 | ||
1030 | static struct omap_hwmod omap44xx_emif1_hwmod = { | |
1031 | .name = "emif1", | |
1032 | .class = &omap44xx_emif_hwmod_class, | |
1033 | .clkdm_name = "l3_emif_clkdm", | |
1034 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | |
1035 | .mpu_irqs = omap44xx_emif1_irqs, | |
1036 | .main_clk = "ddrphy_ck", | |
1037 | .prcm = { | |
1038 | .omap4 = { | |
1039 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET, | |
1040 | .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET, | |
1041 | .modulemode = MODULEMODE_HWCTRL, | |
1042 | }, | |
1043 | }, | |
1044 | }; | |
1045 | ||
1046 | /* emif2 */ | |
1047 | static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = { | |
1048 | { .irq = 111 + OMAP44XX_IRQ_GIC_START }, | |
1049 | { .irq = -1 } | |
1050 | }; | |
1051 | ||
1052 | static struct omap_hwmod omap44xx_emif2_hwmod = { | |
1053 | .name = "emif2", | |
1054 | .class = &omap44xx_emif_hwmod_class, | |
1055 | .clkdm_name = "l3_emif_clkdm", | |
1056 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | |
1057 | .mpu_irqs = omap44xx_emif2_irqs, | |
1058 | .main_clk = "ddrphy_ck", | |
1059 | .prcm = { | |
1060 | .omap4 = { | |
1061 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET, | |
1062 | .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET, | |
1063 | .modulemode = MODULEMODE_HWCTRL, | |
1064 | }, | |
1065 | }, | |
1066 | }; | |
1067 | ||
b050f688 ML |
1068 | /* |
1069 | * 'fdif' class | |
1070 | * face detection hw accelerator module | |
1071 | */ | |
1072 | ||
1073 | static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = { | |
1074 | .rev_offs = 0x0000, | |
1075 | .sysc_offs = 0x0010, | |
1076 | /* | |
1077 | * FDIF needs 100 OCP clk cycles delay after a softreset before | |
1078 | * accessing sysconfig again. | |
1079 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
1080 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
1081 | * | |
1082 | * TODO: Indicate errata when available. | |
1083 | */ | |
1084 | .srst_udelay = 2, | |
1085 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | | |
1086 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1087 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1088 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1089 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1090 | }; | |
1091 | ||
1092 | static struct omap_hwmod_class omap44xx_fdif_hwmod_class = { | |
1093 | .name = "fdif", | |
1094 | .sysc = &omap44xx_fdif_sysc, | |
1095 | }; | |
1096 | ||
1097 | /* fdif */ | |
1098 | static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = { | |
1099 | { .irq = 69 + OMAP44XX_IRQ_GIC_START }, | |
1100 | { .irq = -1 } | |
1101 | }; | |
1102 | ||
1103 | static struct omap_hwmod omap44xx_fdif_hwmod = { | |
1104 | .name = "fdif", | |
1105 | .class = &omap44xx_fdif_hwmod_class, | |
1106 | .clkdm_name = "iss_clkdm", | |
1107 | .mpu_irqs = omap44xx_fdif_irqs, | |
1108 | .main_clk = "fdif_fck", | |
1109 | .prcm = { | |
1110 | .omap4 = { | |
1111 | .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET, | |
1112 | .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET, | |
1113 | .modulemode = MODULEMODE_SWCTRL, | |
1114 | }, | |
1115 | }, | |
1116 | }; | |
1117 | ||
3b54baad BC |
1118 | /* |
1119 | * 'gpio' class | |
1120 | * general purpose io module | |
1121 | */ | |
1122 | ||
1123 | static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { | |
1124 | .rev_offs = 0x0000, | |
f776471f | 1125 | .sysc_offs = 0x0010, |
3b54baad | 1126 | .syss_offs = 0x0114, |
0cfe8751 BC |
1127 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
1128 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1129 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
1130 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1131 | SIDLE_SMART_WKUP), | |
f776471f BC |
1132 | .sysc_fields = &omap_hwmod_sysc_type1, |
1133 | }; | |
1134 | ||
3b54baad | 1135 | static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { |
fe13471c BC |
1136 | .name = "gpio", |
1137 | .sysc = &omap44xx_gpio_sysc, | |
1138 | .rev = 2, | |
f776471f BC |
1139 | }; |
1140 | ||
3b54baad BC |
1141 | /* gpio dev_attr */ |
1142 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
fe13471c BC |
1143 | .bank_width = 32, |
1144 | .dbck_flag = true, | |
f776471f BC |
1145 | }; |
1146 | ||
3b54baad | 1147 | /* gpio1 */ |
3b54baad BC |
1148 | static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { |
1149 | { .irq = 29 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1150 | { .irq = -1 } |
f776471f BC |
1151 | }; |
1152 | ||
3b54baad | 1153 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
b399bca8 | 1154 | { .role = "dbclk", .clk = "gpio1_dbclk" }, |
3b54baad BC |
1155 | }; |
1156 | ||
1157 | static struct omap_hwmod omap44xx_gpio1_hwmod = { | |
1158 | .name = "gpio1", | |
1159 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1160 | .clkdm_name = "l4_wkup_clkdm", |
3b54baad | 1161 | .mpu_irqs = omap44xx_gpio1_irqs, |
3b54baad | 1162 | .main_clk = "gpio1_ick", |
f776471f BC |
1163 | .prcm = { |
1164 | .omap4 = { | |
d0f0631d | 1165 | .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, |
27bb00b5 | 1166 | .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET, |
03fdefe5 | 1167 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1168 | }, |
1169 | }, | |
3b54baad BC |
1170 | .opt_clks = gpio1_opt_clks, |
1171 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
1172 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1173 | }; |
1174 | ||
3b54baad | 1175 | /* gpio2 */ |
3b54baad BC |
1176 | static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { |
1177 | { .irq = 30 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1178 | { .irq = -1 } |
f776471f BC |
1179 | }; |
1180 | ||
3b54baad | 1181 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
b399bca8 | 1182 | { .role = "dbclk", .clk = "gpio2_dbclk" }, |
3b54baad BC |
1183 | }; |
1184 | ||
1185 | static struct omap_hwmod omap44xx_gpio2_hwmod = { | |
1186 | .name = "gpio2", | |
1187 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1188 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1189 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1190 | .mpu_irqs = omap44xx_gpio2_irqs, |
3b54baad | 1191 | .main_clk = "gpio2_ick", |
f776471f BC |
1192 | .prcm = { |
1193 | .omap4 = { | |
d0f0631d | 1194 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET, |
27bb00b5 | 1195 | .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET, |
03fdefe5 | 1196 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1197 | }, |
1198 | }, | |
3b54baad BC |
1199 | .opt_clks = gpio2_opt_clks, |
1200 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
1201 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1202 | }; |
1203 | ||
3b54baad | 1204 | /* gpio3 */ |
3b54baad BC |
1205 | static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { |
1206 | { .irq = 31 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1207 | { .irq = -1 } |
f776471f BC |
1208 | }; |
1209 | ||
3b54baad | 1210 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
b399bca8 | 1211 | { .role = "dbclk", .clk = "gpio3_dbclk" }, |
3b54baad BC |
1212 | }; |
1213 | ||
1214 | static struct omap_hwmod omap44xx_gpio3_hwmod = { | |
1215 | .name = "gpio3", | |
1216 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1217 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1218 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1219 | .mpu_irqs = omap44xx_gpio3_irqs, |
3b54baad | 1220 | .main_clk = "gpio3_ick", |
f776471f BC |
1221 | .prcm = { |
1222 | .omap4 = { | |
d0f0631d | 1223 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET, |
27bb00b5 | 1224 | .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET, |
03fdefe5 | 1225 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1226 | }, |
1227 | }, | |
3b54baad BC |
1228 | .opt_clks = gpio3_opt_clks, |
1229 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
1230 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1231 | }; |
1232 | ||
3b54baad | 1233 | /* gpio4 */ |
3b54baad BC |
1234 | static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { |
1235 | { .irq = 32 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1236 | { .irq = -1 } |
f776471f BC |
1237 | }; |
1238 | ||
3b54baad | 1239 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { |
b399bca8 | 1240 | { .role = "dbclk", .clk = "gpio4_dbclk" }, |
3b54baad BC |
1241 | }; |
1242 | ||
1243 | static struct omap_hwmod omap44xx_gpio4_hwmod = { | |
1244 | .name = "gpio4", | |
1245 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1246 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1247 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1248 | .mpu_irqs = omap44xx_gpio4_irqs, |
3b54baad | 1249 | .main_clk = "gpio4_ick", |
f776471f BC |
1250 | .prcm = { |
1251 | .omap4 = { | |
d0f0631d | 1252 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET, |
27bb00b5 | 1253 | .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET, |
03fdefe5 | 1254 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1255 | }, |
1256 | }, | |
3b54baad BC |
1257 | .opt_clks = gpio4_opt_clks, |
1258 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
1259 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1260 | }; |
1261 | ||
3b54baad | 1262 | /* gpio5 */ |
3b54baad BC |
1263 | static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { |
1264 | { .irq = 33 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1265 | { .irq = -1 } |
55d2cb08 BC |
1266 | }; |
1267 | ||
844a3b63 PW |
1268 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
1269 | { .role = "dbclk", .clk = "gpio5_dbclk" }, | |
55d2cb08 BC |
1270 | }; |
1271 | ||
3b54baad BC |
1272 | static struct omap_hwmod omap44xx_gpio5_hwmod = { |
1273 | .name = "gpio5", | |
1274 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1275 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1276 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1277 | .mpu_irqs = omap44xx_gpio5_irqs, |
3b54baad | 1278 | .main_clk = "gpio5_ick", |
55d2cb08 BC |
1279 | .prcm = { |
1280 | .omap4 = { | |
d0f0631d | 1281 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET, |
27bb00b5 | 1282 | .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET, |
03fdefe5 | 1283 | .modulemode = MODULEMODE_HWCTRL, |
55d2cb08 BC |
1284 | }, |
1285 | }, | |
3b54baad BC |
1286 | .opt_clks = gpio5_opt_clks, |
1287 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
1288 | .dev_attr = &gpio_dev_attr, | |
55d2cb08 BC |
1289 | }; |
1290 | ||
3b54baad | 1291 | /* gpio6 */ |
3b54baad BC |
1292 | static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { |
1293 | { .irq = 34 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1294 | { .irq = -1 } |
92b18d1c BC |
1295 | }; |
1296 | ||
3b54baad | 1297 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
b399bca8 | 1298 | { .role = "dbclk", .clk = "gpio6_dbclk" }, |
db12ba53 BC |
1299 | }; |
1300 | ||
3b54baad BC |
1301 | static struct omap_hwmod omap44xx_gpio6_hwmod = { |
1302 | .name = "gpio6", | |
1303 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1304 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1305 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1306 | .mpu_irqs = omap44xx_gpio6_irqs, |
3b54baad BC |
1307 | .main_clk = "gpio6_ick", |
1308 | .prcm = { | |
1309 | .omap4 = { | |
d0f0631d | 1310 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET, |
27bb00b5 | 1311 | .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET, |
03fdefe5 | 1312 | .modulemode = MODULEMODE_HWCTRL, |
3b54baad | 1313 | }, |
db12ba53 | 1314 | }, |
3b54baad BC |
1315 | .opt_clks = gpio6_opt_clks, |
1316 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
1317 | .dev_attr = &gpio_dev_attr, | |
db12ba53 BC |
1318 | }; |
1319 | ||
eb42b5d3 BC |
1320 | /* |
1321 | * 'gpmc' class | |
1322 | * general purpose memory controller | |
1323 | */ | |
1324 | ||
1325 | static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = { | |
1326 | .rev_offs = 0x0000, | |
1327 | .sysc_offs = 0x0010, | |
1328 | .syss_offs = 0x0014, | |
1329 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
1330 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1331 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1332 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1333 | }; | |
1334 | ||
1335 | static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = { | |
1336 | .name = "gpmc", | |
1337 | .sysc = &omap44xx_gpmc_sysc, | |
1338 | }; | |
1339 | ||
1340 | /* gpmc */ | |
1341 | static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = { | |
1342 | { .irq = 20 + OMAP44XX_IRQ_GIC_START }, | |
1343 | { .irq = -1 } | |
1344 | }; | |
1345 | ||
1346 | static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = { | |
1347 | { .dma_req = 3 + OMAP44XX_DMA_REQ_START }, | |
1348 | { .dma_req = -1 } | |
1349 | }; | |
1350 | ||
1351 | static struct omap_hwmod omap44xx_gpmc_hwmod = { | |
1352 | .name = "gpmc", | |
1353 | .class = &omap44xx_gpmc_hwmod_class, | |
1354 | .clkdm_name = "l3_2_clkdm", | |
1355 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | |
1356 | .mpu_irqs = omap44xx_gpmc_irqs, | |
1357 | .sdma_reqs = omap44xx_gpmc_sdma_reqs, | |
1358 | .prcm = { | |
1359 | .omap4 = { | |
1360 | .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET, | |
1361 | .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET, | |
1362 | .modulemode = MODULEMODE_HWCTRL, | |
1363 | }, | |
1364 | }, | |
1365 | }; | |
1366 | ||
9def390e PW |
1367 | /* |
1368 | * 'gpu' class | |
1369 | * 2d/3d graphics accelerator | |
1370 | */ | |
1371 | ||
1372 | static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = { | |
1373 | .rev_offs = 0x1fc00, | |
1374 | .sysc_offs = 0x1fc10, | |
1375 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
1376 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1377 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
1378 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
1379 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1380 | }; | |
1381 | ||
1382 | static struct omap_hwmod_class omap44xx_gpu_hwmod_class = { | |
1383 | .name = "gpu", | |
1384 | .sysc = &omap44xx_gpu_sysc, | |
1385 | }; | |
1386 | ||
1387 | /* gpu */ | |
1388 | static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = { | |
1389 | { .irq = 21 + OMAP44XX_IRQ_GIC_START }, | |
1390 | { .irq = -1 } | |
1391 | }; | |
1392 | ||
1393 | static struct omap_hwmod omap44xx_gpu_hwmod = { | |
1394 | .name = "gpu", | |
1395 | .class = &omap44xx_gpu_hwmod_class, | |
1396 | .clkdm_name = "l3_gfx_clkdm", | |
1397 | .mpu_irqs = omap44xx_gpu_irqs, | |
1398 | .main_clk = "gpu_fck", | |
1399 | .prcm = { | |
1400 | .omap4 = { | |
1401 | .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET, | |
1402 | .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET, | |
1403 | .modulemode = MODULEMODE_SWCTRL, | |
1404 | }, | |
1405 | }, | |
1406 | }; | |
1407 | ||
a091c08e PW |
1408 | /* |
1409 | * 'hdq1w' class | |
1410 | * hdq / 1-wire serial interface controller | |
1411 | */ | |
1412 | ||
1413 | static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = { | |
1414 | .rev_offs = 0x0000, | |
1415 | .sysc_offs = 0x0014, | |
1416 | .syss_offs = 0x0018, | |
1417 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET | | |
1418 | SYSS_HAS_RESET_STATUS), | |
1419 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1420 | }; | |
1421 | ||
1422 | static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = { | |
1423 | .name = "hdq1w", | |
1424 | .sysc = &omap44xx_hdq1w_sysc, | |
1425 | }; | |
1426 | ||
1427 | /* hdq1w */ | |
1428 | static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = { | |
1429 | { .irq = 58 + OMAP44XX_IRQ_GIC_START }, | |
1430 | { .irq = -1 } | |
1431 | }; | |
1432 | ||
1433 | static struct omap_hwmod omap44xx_hdq1w_hwmod = { | |
1434 | .name = "hdq1w", | |
1435 | .class = &omap44xx_hdq1w_hwmod_class, | |
1436 | .clkdm_name = "l4_per_clkdm", | |
1437 | .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ | |
1438 | .mpu_irqs = omap44xx_hdq1w_irqs, | |
1439 | .main_clk = "hdq1w_fck", | |
1440 | .prcm = { | |
1441 | .omap4 = { | |
1442 | .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, | |
1443 | .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET, | |
1444 | .modulemode = MODULEMODE_SWCTRL, | |
1445 | }, | |
1446 | }, | |
1447 | }; | |
1448 | ||
407a6888 BC |
1449 | /* |
1450 | * 'hsi' class | |
1451 | * mipi high-speed synchronous serial interface (multichannel and full-duplex | |
1452 | * serial if) | |
1453 | */ | |
1454 | ||
1455 | static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = { | |
1456 | .rev_offs = 0x0000, | |
1457 | .sysc_offs = 0x0010, | |
1458 | .syss_offs = 0x0014, | |
1459 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | | |
1460 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
1461 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1462 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1463 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1464 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1465 | .sysc_fields = &omap_hwmod_sysc_type1, |
1466 | }; | |
1467 | ||
1468 | static struct omap_hwmod_class omap44xx_hsi_hwmod_class = { | |
1469 | .name = "hsi", | |
1470 | .sysc = &omap44xx_hsi_sysc, | |
1471 | }; | |
1472 | ||
1473 | /* hsi */ | |
1474 | static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { | |
1475 | { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START }, | |
1476 | { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START }, | |
1477 | { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1478 | { .irq = -1 } |
407a6888 BC |
1479 | }; |
1480 | ||
407a6888 BC |
1481 | static struct omap_hwmod omap44xx_hsi_hwmod = { |
1482 | .name = "hsi", | |
1483 | .class = &omap44xx_hsi_hwmod_class, | |
a5322c6f | 1484 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 1485 | .mpu_irqs = omap44xx_hsi_irqs, |
407a6888 | 1486 | .main_clk = "hsi_fck", |
00fe610b | 1487 | .prcm = { |
407a6888 | 1488 | .omap4 = { |
d0f0631d | 1489 | .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET, |
27bb00b5 | 1490 | .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET, |
03fdefe5 | 1491 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1492 | }, |
1493 | }, | |
407a6888 BC |
1494 | }; |
1495 | ||
3b54baad BC |
1496 | /* |
1497 | * 'i2c' class | |
1498 | * multimaster high-speed i2c controller | |
1499 | */ | |
db12ba53 | 1500 | |
3b54baad BC |
1501 | static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { |
1502 | .sysc_offs = 0x0010, | |
1503 | .syss_offs = 0x0090, | |
1504 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1505 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 1506 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
1507 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1508 | SIDLE_SMART_WKUP), | |
3e47dc6a | 1509 | .clockact = CLOCKACT_TEST_ICLK, |
3b54baad | 1510 | .sysc_fields = &omap_hwmod_sysc_type1, |
db12ba53 BC |
1511 | }; |
1512 | ||
3b54baad | 1513 | static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { |
fe13471c BC |
1514 | .name = "i2c", |
1515 | .sysc = &omap44xx_i2c_sysc, | |
db791a75 | 1516 | .rev = OMAP_I2C_IP_VERSION_2, |
6d3c55fd | 1517 | .reset = &omap_i2c_reset, |
db12ba53 BC |
1518 | }; |
1519 | ||
4d4441a6 | 1520 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
aa8f6cef S |
1521 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE | |
1522 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE, | |
4d4441a6 AG |
1523 | }; |
1524 | ||
3b54baad | 1525 | /* i2c1 */ |
3b54baad BC |
1526 | static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { |
1527 | { .irq = 56 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1528 | { .irq = -1 } |
db12ba53 BC |
1529 | }; |
1530 | ||
3b54baad BC |
1531 | static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { |
1532 | { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, | |
1533 | { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1534 | { .dma_req = -1 } |
db12ba53 BC |
1535 | }; |
1536 | ||
3b54baad BC |
1537 | static struct omap_hwmod omap44xx_i2c1_hwmod = { |
1538 | .name = "i2c1", | |
1539 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1540 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1541 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1542 | .mpu_irqs = omap44xx_i2c1_irqs, |
3b54baad | 1543 | .sdma_reqs = omap44xx_i2c1_sdma_reqs, |
3b54baad | 1544 | .main_clk = "i2c1_fck", |
92b18d1c BC |
1545 | .prcm = { |
1546 | .omap4 = { | |
d0f0631d | 1547 | .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET, |
27bb00b5 | 1548 | .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET, |
03fdefe5 | 1549 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
1550 | }, |
1551 | }, | |
4d4441a6 | 1552 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
1553 | }; |
1554 | ||
3b54baad | 1555 | /* i2c2 */ |
3b54baad BC |
1556 | static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { |
1557 | { .irq = 57 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1558 | { .irq = -1 } |
92b18d1c BC |
1559 | }; |
1560 | ||
3b54baad BC |
1561 | static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { |
1562 | { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, | |
1563 | { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1564 | { .dma_req = -1 } |
3b54baad BC |
1565 | }; |
1566 | ||
3b54baad BC |
1567 | static struct omap_hwmod omap44xx_i2c2_hwmod = { |
1568 | .name = "i2c2", | |
1569 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1570 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1571 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1572 | .mpu_irqs = omap44xx_i2c2_irqs, |
3b54baad | 1573 | .sdma_reqs = omap44xx_i2c2_sdma_reqs, |
3b54baad | 1574 | .main_clk = "i2c2_fck", |
db12ba53 BC |
1575 | .prcm = { |
1576 | .omap4 = { | |
d0f0631d | 1577 | .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, |
27bb00b5 | 1578 | .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET, |
03fdefe5 | 1579 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
1580 | }, |
1581 | }, | |
4d4441a6 | 1582 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
1583 | }; |
1584 | ||
3b54baad | 1585 | /* i2c3 */ |
3b54baad BC |
1586 | static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { |
1587 | { .irq = 61 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1588 | { .irq = -1 } |
db12ba53 BC |
1589 | }; |
1590 | ||
3b54baad BC |
1591 | static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { |
1592 | { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, | |
1593 | { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1594 | { .dma_req = -1 } |
92b18d1c BC |
1595 | }; |
1596 | ||
3b54baad BC |
1597 | static struct omap_hwmod omap44xx_i2c3_hwmod = { |
1598 | .name = "i2c3", | |
1599 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1600 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1601 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1602 | .mpu_irqs = omap44xx_i2c3_irqs, |
3b54baad | 1603 | .sdma_reqs = omap44xx_i2c3_sdma_reqs, |
3b54baad | 1604 | .main_clk = "i2c3_fck", |
db12ba53 BC |
1605 | .prcm = { |
1606 | .omap4 = { | |
d0f0631d | 1607 | .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET, |
27bb00b5 | 1608 | .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET, |
03fdefe5 | 1609 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
1610 | }, |
1611 | }, | |
4d4441a6 | 1612 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
1613 | }; |
1614 | ||
3b54baad | 1615 | /* i2c4 */ |
3b54baad BC |
1616 | static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { |
1617 | { .irq = 62 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1618 | { .irq = -1 } |
db12ba53 BC |
1619 | }; |
1620 | ||
3b54baad BC |
1621 | static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { |
1622 | { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, | |
1623 | { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1624 | { .dma_req = -1 } |
db12ba53 BC |
1625 | }; |
1626 | ||
3b54baad BC |
1627 | static struct omap_hwmod omap44xx_i2c4_hwmod = { |
1628 | .name = "i2c4", | |
1629 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1630 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1631 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1632 | .mpu_irqs = omap44xx_i2c4_irqs, |
3b54baad | 1633 | .sdma_reqs = omap44xx_i2c4_sdma_reqs, |
3b54baad | 1634 | .main_clk = "i2c4_fck", |
92b18d1c BC |
1635 | .prcm = { |
1636 | .omap4 = { | |
d0f0631d | 1637 | .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET, |
27bb00b5 | 1638 | .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET, |
03fdefe5 | 1639 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
1640 | }, |
1641 | }, | |
4d4441a6 | 1642 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
1643 | }; |
1644 | ||
407a6888 BC |
1645 | /* |
1646 | * 'ipu' class | |
1647 | * imaging processor unit | |
1648 | */ | |
1649 | ||
1650 | static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { | |
1651 | .name = "ipu", | |
1652 | }; | |
1653 | ||
1654 | /* ipu */ | |
1655 | static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { | |
1656 | { .irq = 100 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1657 | { .irq = -1 } |
407a6888 BC |
1658 | }; |
1659 | ||
f2f5736c | 1660 | static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { |
407a6888 | 1661 | { .name = "cpu0", .rst_shift = 0 }, |
407a6888 | 1662 | { .name = "cpu1", .rst_shift = 1 }, |
407a6888 BC |
1663 | }; |
1664 | ||
407a6888 BC |
1665 | static struct omap_hwmod omap44xx_ipu_hwmod = { |
1666 | .name = "ipu", | |
1667 | .class = &omap44xx_ipu_hwmod_class, | |
a5322c6f | 1668 | .clkdm_name = "ducati_clkdm", |
407a6888 | 1669 | .mpu_irqs = omap44xx_ipu_irqs, |
407a6888 BC |
1670 | .rst_lines = omap44xx_ipu_resets, |
1671 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), | |
1672 | .main_clk = "ipu_fck", | |
00fe610b | 1673 | .prcm = { |
407a6888 | 1674 | .omap4 = { |
d0f0631d | 1675 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, |
eaac329d | 1676 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, |
27bb00b5 | 1677 | .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, |
03fdefe5 | 1678 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1679 | }, |
1680 | }, | |
407a6888 BC |
1681 | }; |
1682 | ||
1683 | /* | |
1684 | * 'iss' class | |
1685 | * external images sensor pixel data processor | |
1686 | */ | |
1687 | ||
1688 | static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { | |
1689 | .rev_offs = 0x0000, | |
1690 | .sysc_offs = 0x0010, | |
d99de7f5 FGL |
1691 | /* |
1692 | * ISS needs 100 OCP clk cycles delay after a softreset before | |
1693 | * accessing sysconfig again. | |
1694 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
1695 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
1696 | * | |
1697 | * TODO: Indicate errata when available. | |
1698 | */ | |
1699 | .srst_udelay = 2, | |
407a6888 BC |
1700 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | |
1701 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1702 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1703 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1704 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1705 | .sysc_fields = &omap_hwmod_sysc_type2, |
1706 | }; | |
1707 | ||
1708 | static struct omap_hwmod_class omap44xx_iss_hwmod_class = { | |
1709 | .name = "iss", | |
1710 | .sysc = &omap44xx_iss_sysc, | |
1711 | }; | |
1712 | ||
1713 | /* iss */ | |
1714 | static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = { | |
1715 | { .irq = 24 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1716 | { .irq = -1 } |
407a6888 BC |
1717 | }; |
1718 | ||
1719 | static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { | |
1720 | { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START }, | |
1721 | { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START }, | |
1722 | { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START }, | |
1723 | { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1724 | { .dma_req = -1 } |
407a6888 BC |
1725 | }; |
1726 | ||
407a6888 BC |
1727 | static struct omap_hwmod_opt_clk iss_opt_clks[] = { |
1728 | { .role = "ctrlclk", .clk = "iss_ctrlclk" }, | |
1729 | }; | |
1730 | ||
1731 | static struct omap_hwmod omap44xx_iss_hwmod = { | |
1732 | .name = "iss", | |
1733 | .class = &omap44xx_iss_hwmod_class, | |
a5322c6f | 1734 | .clkdm_name = "iss_clkdm", |
407a6888 | 1735 | .mpu_irqs = omap44xx_iss_irqs, |
407a6888 | 1736 | .sdma_reqs = omap44xx_iss_sdma_reqs, |
407a6888 | 1737 | .main_clk = "iss_fck", |
00fe610b | 1738 | .prcm = { |
407a6888 | 1739 | .omap4 = { |
d0f0631d | 1740 | .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, |
27bb00b5 | 1741 | .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET, |
03fdefe5 | 1742 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1743 | }, |
1744 | }, | |
1745 | .opt_clks = iss_opt_clks, | |
1746 | .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), | |
407a6888 BC |
1747 | }; |
1748 | ||
8f25bdc5 BC |
1749 | /* |
1750 | * 'iva' class | |
1751 | * multi-standard video encoder/decoder hardware accelerator | |
1752 | */ | |
1753 | ||
1754 | static struct omap_hwmod_class omap44xx_iva_hwmod_class = { | |
fe13471c | 1755 | .name = "iva", |
8f25bdc5 BC |
1756 | }; |
1757 | ||
1758 | /* iva */ | |
1759 | static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { | |
1760 | { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, | |
1761 | { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, | |
1762 | { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1763 | { .irq = -1 } |
8f25bdc5 BC |
1764 | }; |
1765 | ||
1766 | static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { | |
8f25bdc5 | 1767 | { .name = "seq0", .rst_shift = 0 }, |
8f25bdc5 | 1768 | { .name = "seq1", .rst_shift = 1 }, |
f2f5736c | 1769 | { .name = "logic", .rst_shift = 2 }, |
8f25bdc5 BC |
1770 | }; |
1771 | ||
8f25bdc5 BC |
1772 | static struct omap_hwmod omap44xx_iva_hwmod = { |
1773 | .name = "iva", | |
1774 | .class = &omap44xx_iva_hwmod_class, | |
a5322c6f | 1775 | .clkdm_name = "ivahd_clkdm", |
8f25bdc5 | 1776 | .mpu_irqs = omap44xx_iva_irqs, |
8f25bdc5 BC |
1777 | .rst_lines = omap44xx_iva_resets, |
1778 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), | |
1779 | .main_clk = "iva_fck", | |
1780 | .prcm = { | |
1781 | .omap4 = { | |
d0f0631d | 1782 | .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, |
eaac329d | 1783 | .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, |
27bb00b5 | 1784 | .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET, |
03fdefe5 | 1785 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
1786 | }, |
1787 | }, | |
8f25bdc5 BC |
1788 | }; |
1789 | ||
407a6888 BC |
1790 | /* |
1791 | * 'kbd' class | |
1792 | * keyboard controller | |
1793 | */ | |
1794 | ||
1795 | static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = { | |
1796 | .rev_offs = 0x0000, | |
1797 | .sysc_offs = 0x0010, | |
1798 | .syss_offs = 0x0014, | |
1799 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1800 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
1801 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1802 | SYSS_HAS_RESET_STATUS), | |
1803 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1804 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1805 | }; | |
1806 | ||
1807 | static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { | |
1808 | .name = "kbd", | |
1809 | .sysc = &omap44xx_kbd_sysc, | |
1810 | }; | |
1811 | ||
1812 | /* kbd */ | |
407a6888 BC |
1813 | static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { |
1814 | { .irq = 120 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1815 | { .irq = -1 } |
407a6888 BC |
1816 | }; |
1817 | ||
407a6888 BC |
1818 | static struct omap_hwmod omap44xx_kbd_hwmod = { |
1819 | .name = "kbd", | |
1820 | .class = &omap44xx_kbd_hwmod_class, | |
a5322c6f | 1821 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 | 1822 | .mpu_irqs = omap44xx_kbd_irqs, |
407a6888 | 1823 | .main_clk = "kbd_fck", |
00fe610b | 1824 | .prcm = { |
407a6888 | 1825 | .omap4 = { |
d0f0631d | 1826 | .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, |
27bb00b5 | 1827 | .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET, |
03fdefe5 | 1828 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1829 | }, |
1830 | }, | |
407a6888 BC |
1831 | }; |
1832 | ||
ec5df927 BC |
1833 | /* |
1834 | * 'mailbox' class | |
1835 | * mailbox module allowing communication between the on-chip processors using a | |
1836 | * queued mailbox-interrupt mechanism. | |
1837 | */ | |
1838 | ||
1839 | static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = { | |
1840 | .rev_offs = 0x0000, | |
1841 | .sysc_offs = 0x0010, | |
1842 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1843 | SYSC_HAS_SOFTRESET), | |
1844 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1845 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1846 | }; | |
1847 | ||
1848 | static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { | |
1849 | .name = "mailbox", | |
1850 | .sysc = &omap44xx_mailbox_sysc, | |
1851 | }; | |
1852 | ||
1853 | /* mailbox */ | |
ec5df927 BC |
1854 | static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { |
1855 | { .irq = 26 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1856 | { .irq = -1 } |
ec5df927 BC |
1857 | }; |
1858 | ||
ec5df927 BC |
1859 | static struct omap_hwmod omap44xx_mailbox_hwmod = { |
1860 | .name = "mailbox", | |
1861 | .class = &omap44xx_mailbox_hwmod_class, | |
a5322c6f | 1862 | .clkdm_name = "l4_cfg_clkdm", |
ec5df927 | 1863 | .mpu_irqs = omap44xx_mailbox_irqs, |
00fe610b | 1864 | .prcm = { |
ec5df927 | 1865 | .omap4 = { |
d0f0631d | 1866 | .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, |
27bb00b5 | 1867 | .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, |
ec5df927 BC |
1868 | }, |
1869 | }, | |
ec5df927 BC |
1870 | }; |
1871 | ||
896d4e98 BC |
1872 | /* |
1873 | * 'mcasp' class | |
1874 | * multi-channel audio serial port controller | |
1875 | */ | |
1876 | ||
1877 | /* The IP is not compliant to type1 / type2 scheme */ | |
1878 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = { | |
1879 | .sidle_shift = 0, | |
1880 | }; | |
1881 | ||
1882 | static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = { | |
1883 | .sysc_offs = 0x0004, | |
1884 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
1885 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1886 | SIDLE_SMART_WKUP), | |
1887 | .sysc_fields = &omap_hwmod_sysc_type_mcasp, | |
1888 | }; | |
1889 | ||
1890 | static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = { | |
1891 | .name = "mcasp", | |
1892 | .sysc = &omap44xx_mcasp_sysc, | |
1893 | }; | |
1894 | ||
1895 | /* mcasp */ | |
1896 | static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = { | |
1897 | { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START }, | |
1898 | { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START }, | |
1899 | { .irq = -1 } | |
1900 | }; | |
1901 | ||
1902 | static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = { | |
1903 | { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START }, | |
1904 | { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START }, | |
1905 | { .dma_req = -1 } | |
1906 | }; | |
1907 | ||
1908 | static struct omap_hwmod omap44xx_mcasp_hwmod = { | |
1909 | .name = "mcasp", | |
1910 | .class = &omap44xx_mcasp_hwmod_class, | |
1911 | .clkdm_name = "abe_clkdm", | |
1912 | .mpu_irqs = omap44xx_mcasp_irqs, | |
1913 | .sdma_reqs = omap44xx_mcasp_sdma_reqs, | |
1914 | .main_clk = "mcasp_fck", | |
1915 | .prcm = { | |
1916 | .omap4 = { | |
1917 | .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET, | |
1918 | .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET, | |
1919 | .modulemode = MODULEMODE_SWCTRL, | |
1920 | }, | |
1921 | }, | |
1922 | }; | |
1923 | ||
4ddff493 BC |
1924 | /* |
1925 | * 'mcbsp' class | |
1926 | * multi channel buffered serial port controller | |
1927 | */ | |
1928 | ||
1929 | static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { | |
1930 | .sysc_offs = 0x008c, | |
1931 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
1932 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1933 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1934 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1935 | }; | |
1936 | ||
1937 | static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { | |
1938 | .name = "mcbsp", | |
1939 | .sysc = &omap44xx_mcbsp_sysc, | |
cb7e9ded | 1940 | .rev = MCBSP_CONFIG_TYPE4, |
4ddff493 BC |
1941 | }; |
1942 | ||
1943 | /* mcbsp1 */ | |
4ddff493 | 1944 | static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { |
437e8970 | 1945 | { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START }, |
212738a4 | 1946 | { .irq = -1 } |
4ddff493 BC |
1947 | }; |
1948 | ||
1949 | static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { | |
1950 | { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, | |
1951 | { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1952 | { .dma_req = -1 } |
4ddff493 BC |
1953 | }; |
1954 | ||
503d0ea2 PW |
1955 | static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { |
1956 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 1957 | { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" }, |
503d0ea2 PW |
1958 | }; |
1959 | ||
4ddff493 BC |
1960 | static struct omap_hwmod omap44xx_mcbsp1_hwmod = { |
1961 | .name = "mcbsp1", | |
1962 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1963 | .clkdm_name = "abe_clkdm", |
4ddff493 | 1964 | .mpu_irqs = omap44xx_mcbsp1_irqs, |
4ddff493 | 1965 | .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, |
4ddff493 BC |
1966 | .main_clk = "mcbsp1_fck", |
1967 | .prcm = { | |
1968 | .omap4 = { | |
d0f0631d | 1969 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, |
27bb00b5 | 1970 | .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET, |
03fdefe5 | 1971 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1972 | }, |
1973 | }, | |
503d0ea2 PW |
1974 | .opt_clks = mcbsp1_opt_clks, |
1975 | .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks), | |
4ddff493 BC |
1976 | }; |
1977 | ||
1978 | /* mcbsp2 */ | |
4ddff493 | 1979 | static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { |
437e8970 | 1980 | { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START }, |
212738a4 | 1981 | { .irq = -1 } |
4ddff493 BC |
1982 | }; |
1983 | ||
1984 | static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { | |
1985 | { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START }, | |
1986 | { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1987 | { .dma_req = -1 } |
4ddff493 BC |
1988 | }; |
1989 | ||
844a3b63 PW |
1990 | static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { |
1991 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 1992 | { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" }, |
503d0ea2 PW |
1993 | }; |
1994 | ||
4ddff493 BC |
1995 | static struct omap_hwmod omap44xx_mcbsp2_hwmod = { |
1996 | .name = "mcbsp2", | |
1997 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1998 | .clkdm_name = "abe_clkdm", |
4ddff493 | 1999 | .mpu_irqs = omap44xx_mcbsp2_irqs, |
4ddff493 | 2000 | .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, |
4ddff493 BC |
2001 | .main_clk = "mcbsp2_fck", |
2002 | .prcm = { | |
2003 | .omap4 = { | |
d0f0631d | 2004 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, |
27bb00b5 | 2005 | .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET, |
03fdefe5 | 2006 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
2007 | }, |
2008 | }, | |
503d0ea2 PW |
2009 | .opt_clks = mcbsp2_opt_clks, |
2010 | .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks), | |
4ddff493 BC |
2011 | }; |
2012 | ||
2013 | /* mcbsp3 */ | |
4ddff493 | 2014 | static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { |
437e8970 | 2015 | { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START }, |
212738a4 | 2016 | { .irq = -1 } |
4ddff493 BC |
2017 | }; |
2018 | ||
2019 | static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { | |
2020 | { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START }, | |
2021 | { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2022 | { .dma_req = -1 } |
4ddff493 BC |
2023 | }; |
2024 | ||
503d0ea2 PW |
2025 | static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { |
2026 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 2027 | { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" }, |
503d0ea2 PW |
2028 | }; |
2029 | ||
4ddff493 BC |
2030 | static struct omap_hwmod omap44xx_mcbsp3_hwmod = { |
2031 | .name = "mcbsp3", | |
2032 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 2033 | .clkdm_name = "abe_clkdm", |
4ddff493 | 2034 | .mpu_irqs = omap44xx_mcbsp3_irqs, |
4ddff493 | 2035 | .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, |
4ddff493 BC |
2036 | .main_clk = "mcbsp3_fck", |
2037 | .prcm = { | |
2038 | .omap4 = { | |
d0f0631d | 2039 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, |
27bb00b5 | 2040 | .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET, |
03fdefe5 | 2041 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
2042 | }, |
2043 | }, | |
503d0ea2 PW |
2044 | .opt_clks = mcbsp3_opt_clks, |
2045 | .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks), | |
4ddff493 BC |
2046 | }; |
2047 | ||
2048 | /* mcbsp4 */ | |
4ddff493 | 2049 | static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { |
437e8970 | 2050 | { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START }, |
212738a4 | 2051 | { .irq = -1 } |
4ddff493 BC |
2052 | }; |
2053 | ||
2054 | static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { | |
2055 | { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START }, | |
2056 | { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2057 | { .dma_req = -1 } |
4ddff493 BC |
2058 | }; |
2059 | ||
503d0ea2 PW |
2060 | static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { |
2061 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 2062 | { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" }, |
503d0ea2 PW |
2063 | }; |
2064 | ||
4ddff493 BC |
2065 | static struct omap_hwmod omap44xx_mcbsp4_hwmod = { |
2066 | .name = "mcbsp4", | |
2067 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 2068 | .clkdm_name = "l4_per_clkdm", |
4ddff493 | 2069 | .mpu_irqs = omap44xx_mcbsp4_irqs, |
4ddff493 | 2070 | .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, |
4ddff493 BC |
2071 | .main_clk = "mcbsp4_fck", |
2072 | .prcm = { | |
2073 | .omap4 = { | |
d0f0631d | 2074 | .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, |
27bb00b5 | 2075 | .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET, |
03fdefe5 | 2076 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
2077 | }, |
2078 | }, | |
503d0ea2 PW |
2079 | .opt_clks = mcbsp4_opt_clks, |
2080 | .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks), | |
4ddff493 BC |
2081 | }; |
2082 | ||
407a6888 BC |
2083 | /* |
2084 | * 'mcpdm' class | |
2085 | * multi channel pdm controller (proprietary interface with phoenix power | |
2086 | * ic) | |
2087 | */ | |
2088 | ||
2089 | static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = { | |
2090 | .rev_offs = 0x0000, | |
2091 | .sysc_offs = 0x0010, | |
2092 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2093 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2094 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2095 | SIDLE_SMART_WKUP), | |
2096 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2097 | }; | |
2098 | ||
2099 | static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { | |
2100 | .name = "mcpdm", | |
2101 | .sysc = &omap44xx_mcpdm_sysc, | |
2102 | }; | |
2103 | ||
2104 | /* mcpdm */ | |
407a6888 BC |
2105 | static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { |
2106 | { .irq = 112 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2107 | { .irq = -1 } |
407a6888 BC |
2108 | }; |
2109 | ||
2110 | static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { | |
2111 | { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START }, | |
2112 | { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2113 | { .dma_req = -1 } |
407a6888 BC |
2114 | }; |
2115 | ||
407a6888 BC |
2116 | static struct omap_hwmod omap44xx_mcpdm_hwmod = { |
2117 | .name = "mcpdm", | |
2118 | .class = &omap44xx_mcpdm_hwmod_class, | |
a5322c6f | 2119 | .clkdm_name = "abe_clkdm", |
407a6888 | 2120 | .mpu_irqs = omap44xx_mcpdm_irqs, |
407a6888 | 2121 | .sdma_reqs = omap44xx_mcpdm_sdma_reqs, |
407a6888 | 2122 | .main_clk = "mcpdm_fck", |
00fe610b | 2123 | .prcm = { |
407a6888 | 2124 | .omap4 = { |
d0f0631d | 2125 | .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, |
27bb00b5 | 2126 | .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET, |
03fdefe5 | 2127 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2128 | }, |
2129 | }, | |
407a6888 BC |
2130 | }; |
2131 | ||
9bcbd7f0 BC |
2132 | /* |
2133 | * 'mcspi' class | |
2134 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
2135 | * bus | |
2136 | */ | |
2137 | ||
2138 | static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = { | |
2139 | .rev_offs = 0x0000, | |
2140 | .sysc_offs = 0x0010, | |
2141 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2142 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2143 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2144 | SIDLE_SMART_WKUP), | |
2145 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2146 | }; | |
2147 | ||
2148 | static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { | |
2149 | .name = "mcspi", | |
2150 | .sysc = &omap44xx_mcspi_sysc, | |
905a74d9 | 2151 | .rev = OMAP4_MCSPI_REV, |
9bcbd7f0 BC |
2152 | }; |
2153 | ||
2154 | /* mcspi1 */ | |
9bcbd7f0 BC |
2155 | static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { |
2156 | { .irq = 65 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2157 | { .irq = -1 } |
9bcbd7f0 BC |
2158 | }; |
2159 | ||
2160 | static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { | |
2161 | { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, | |
2162 | { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, | |
2163 | { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START }, | |
2164 | { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START }, | |
2165 | { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START }, | |
2166 | { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, | |
2167 | { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, | |
2168 | { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2169 | { .dma_req = -1 } |
9bcbd7f0 BC |
2170 | }; |
2171 | ||
905a74d9 BC |
2172 | /* mcspi1 dev_attr */ |
2173 | static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { | |
2174 | .num_chipselect = 4, | |
2175 | }; | |
2176 | ||
9bcbd7f0 BC |
2177 | static struct omap_hwmod omap44xx_mcspi1_hwmod = { |
2178 | .name = "mcspi1", | |
2179 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2180 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2181 | .mpu_irqs = omap44xx_mcspi1_irqs, |
9bcbd7f0 | 2182 | .sdma_reqs = omap44xx_mcspi1_sdma_reqs, |
9bcbd7f0 BC |
2183 | .main_clk = "mcspi1_fck", |
2184 | .prcm = { | |
2185 | .omap4 = { | |
d0f0631d | 2186 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, |
27bb00b5 | 2187 | .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET, |
03fdefe5 | 2188 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2189 | }, |
2190 | }, | |
905a74d9 | 2191 | .dev_attr = &mcspi1_dev_attr, |
9bcbd7f0 BC |
2192 | }; |
2193 | ||
2194 | /* mcspi2 */ | |
9bcbd7f0 BC |
2195 | static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { |
2196 | { .irq = 66 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2197 | { .irq = -1 } |
9bcbd7f0 BC |
2198 | }; |
2199 | ||
2200 | static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { | |
2201 | { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, | |
2202 | { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, | |
2203 | { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, | |
2204 | { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2205 | { .dma_req = -1 } |
9bcbd7f0 BC |
2206 | }; |
2207 | ||
905a74d9 BC |
2208 | /* mcspi2 dev_attr */ |
2209 | static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { | |
2210 | .num_chipselect = 2, | |
2211 | }; | |
2212 | ||
9bcbd7f0 BC |
2213 | static struct omap_hwmod omap44xx_mcspi2_hwmod = { |
2214 | .name = "mcspi2", | |
2215 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2216 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2217 | .mpu_irqs = omap44xx_mcspi2_irqs, |
9bcbd7f0 | 2218 | .sdma_reqs = omap44xx_mcspi2_sdma_reqs, |
9bcbd7f0 BC |
2219 | .main_clk = "mcspi2_fck", |
2220 | .prcm = { | |
2221 | .omap4 = { | |
d0f0631d | 2222 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, |
27bb00b5 | 2223 | .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET, |
03fdefe5 | 2224 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2225 | }, |
2226 | }, | |
905a74d9 | 2227 | .dev_attr = &mcspi2_dev_attr, |
9bcbd7f0 BC |
2228 | }; |
2229 | ||
2230 | /* mcspi3 */ | |
9bcbd7f0 BC |
2231 | static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { |
2232 | { .irq = 91 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2233 | { .irq = -1 } |
9bcbd7f0 BC |
2234 | }; |
2235 | ||
2236 | static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { | |
2237 | { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, | |
2238 | { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, | |
2239 | { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, | |
2240 | { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2241 | { .dma_req = -1 } |
9bcbd7f0 BC |
2242 | }; |
2243 | ||
905a74d9 BC |
2244 | /* mcspi3 dev_attr */ |
2245 | static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { | |
2246 | .num_chipselect = 2, | |
2247 | }; | |
2248 | ||
9bcbd7f0 BC |
2249 | static struct omap_hwmod omap44xx_mcspi3_hwmod = { |
2250 | .name = "mcspi3", | |
2251 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2252 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2253 | .mpu_irqs = omap44xx_mcspi3_irqs, |
9bcbd7f0 | 2254 | .sdma_reqs = omap44xx_mcspi3_sdma_reqs, |
9bcbd7f0 BC |
2255 | .main_clk = "mcspi3_fck", |
2256 | .prcm = { | |
2257 | .omap4 = { | |
d0f0631d | 2258 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, |
27bb00b5 | 2259 | .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET, |
03fdefe5 | 2260 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2261 | }, |
2262 | }, | |
905a74d9 | 2263 | .dev_attr = &mcspi3_dev_attr, |
9bcbd7f0 BC |
2264 | }; |
2265 | ||
2266 | /* mcspi4 */ | |
9bcbd7f0 BC |
2267 | static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { |
2268 | { .irq = 48 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2269 | { .irq = -1 } |
9bcbd7f0 BC |
2270 | }; |
2271 | ||
2272 | static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { | |
2273 | { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, | |
2274 | { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2275 | { .dma_req = -1 } |
9bcbd7f0 BC |
2276 | }; |
2277 | ||
905a74d9 BC |
2278 | /* mcspi4 dev_attr */ |
2279 | static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { | |
2280 | .num_chipselect = 1, | |
2281 | }; | |
2282 | ||
9bcbd7f0 BC |
2283 | static struct omap_hwmod omap44xx_mcspi4_hwmod = { |
2284 | .name = "mcspi4", | |
2285 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2286 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2287 | .mpu_irqs = omap44xx_mcspi4_irqs, |
9bcbd7f0 | 2288 | .sdma_reqs = omap44xx_mcspi4_sdma_reqs, |
9bcbd7f0 BC |
2289 | .main_clk = "mcspi4_fck", |
2290 | .prcm = { | |
2291 | .omap4 = { | |
d0f0631d | 2292 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, |
27bb00b5 | 2293 | .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET, |
03fdefe5 | 2294 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2295 | }, |
2296 | }, | |
905a74d9 | 2297 | .dev_attr = &mcspi4_dev_attr, |
9bcbd7f0 BC |
2298 | }; |
2299 | ||
407a6888 BC |
2300 | /* |
2301 | * 'mmc' class | |
2302 | * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller | |
2303 | */ | |
2304 | ||
2305 | static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = { | |
2306 | .rev_offs = 0x0000, | |
2307 | .sysc_offs = 0x0010, | |
2308 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
2309 | SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
2310 | SYSC_HAS_SOFTRESET), | |
2311 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2312 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 2313 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
2314 | .sysc_fields = &omap_hwmod_sysc_type2, |
2315 | }; | |
2316 | ||
2317 | static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { | |
2318 | .name = "mmc", | |
2319 | .sysc = &omap44xx_mmc_sysc, | |
2320 | }; | |
2321 | ||
2322 | /* mmc1 */ | |
2323 | static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { | |
2324 | { .irq = 83 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2325 | { .irq = -1 } |
407a6888 BC |
2326 | }; |
2327 | ||
2328 | static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { | |
2329 | { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, | |
2330 | { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2331 | { .dma_req = -1 } |
407a6888 BC |
2332 | }; |
2333 | ||
6ab8946f KK |
2334 | /* mmc1 dev_attr */ |
2335 | static struct omap_mmc_dev_attr mmc1_dev_attr = { | |
2336 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
2337 | }; | |
2338 | ||
407a6888 BC |
2339 | static struct omap_hwmod omap44xx_mmc1_hwmod = { |
2340 | .name = "mmc1", | |
2341 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2342 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 2343 | .mpu_irqs = omap44xx_mmc1_irqs, |
407a6888 | 2344 | .sdma_reqs = omap44xx_mmc1_sdma_reqs, |
407a6888 | 2345 | .main_clk = "mmc1_fck", |
00fe610b | 2346 | .prcm = { |
407a6888 | 2347 | .omap4 = { |
d0f0631d | 2348 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET, |
27bb00b5 | 2349 | .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET, |
03fdefe5 | 2350 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2351 | }, |
2352 | }, | |
6ab8946f | 2353 | .dev_attr = &mmc1_dev_attr, |
407a6888 BC |
2354 | }; |
2355 | ||
2356 | /* mmc2 */ | |
2357 | static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = { | |
2358 | { .irq = 86 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2359 | { .irq = -1 } |
407a6888 BC |
2360 | }; |
2361 | ||
2362 | static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { | |
2363 | { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, | |
2364 | { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2365 | { .dma_req = -1 } |
407a6888 BC |
2366 | }; |
2367 | ||
407a6888 BC |
2368 | static struct omap_hwmod omap44xx_mmc2_hwmod = { |
2369 | .name = "mmc2", | |
2370 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2371 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 2372 | .mpu_irqs = omap44xx_mmc2_irqs, |
407a6888 | 2373 | .sdma_reqs = omap44xx_mmc2_sdma_reqs, |
407a6888 | 2374 | .main_clk = "mmc2_fck", |
00fe610b | 2375 | .prcm = { |
407a6888 | 2376 | .omap4 = { |
d0f0631d | 2377 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET, |
27bb00b5 | 2378 | .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET, |
03fdefe5 | 2379 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2380 | }, |
2381 | }, | |
407a6888 BC |
2382 | }; |
2383 | ||
2384 | /* mmc3 */ | |
407a6888 BC |
2385 | static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { |
2386 | { .irq = 94 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2387 | { .irq = -1 } |
407a6888 BC |
2388 | }; |
2389 | ||
2390 | static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { | |
2391 | { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, | |
2392 | { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2393 | { .dma_req = -1 } |
407a6888 BC |
2394 | }; |
2395 | ||
407a6888 BC |
2396 | static struct omap_hwmod omap44xx_mmc3_hwmod = { |
2397 | .name = "mmc3", | |
2398 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2399 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2400 | .mpu_irqs = omap44xx_mmc3_irqs, |
407a6888 | 2401 | .sdma_reqs = omap44xx_mmc3_sdma_reqs, |
407a6888 | 2402 | .main_clk = "mmc3_fck", |
00fe610b | 2403 | .prcm = { |
407a6888 | 2404 | .omap4 = { |
d0f0631d | 2405 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET, |
27bb00b5 | 2406 | .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET, |
03fdefe5 | 2407 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2408 | }, |
2409 | }, | |
407a6888 BC |
2410 | }; |
2411 | ||
2412 | /* mmc4 */ | |
407a6888 BC |
2413 | static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { |
2414 | { .irq = 96 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2415 | { .irq = -1 } |
407a6888 BC |
2416 | }; |
2417 | ||
2418 | static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { | |
2419 | { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, | |
2420 | { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2421 | { .dma_req = -1 } |
407a6888 BC |
2422 | }; |
2423 | ||
407a6888 BC |
2424 | static struct omap_hwmod omap44xx_mmc4_hwmod = { |
2425 | .name = "mmc4", | |
2426 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2427 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2428 | .mpu_irqs = omap44xx_mmc4_irqs, |
407a6888 | 2429 | .sdma_reqs = omap44xx_mmc4_sdma_reqs, |
407a6888 | 2430 | .main_clk = "mmc4_fck", |
00fe610b | 2431 | .prcm = { |
407a6888 | 2432 | .omap4 = { |
d0f0631d | 2433 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET, |
27bb00b5 | 2434 | .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET, |
03fdefe5 | 2435 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2436 | }, |
2437 | }, | |
407a6888 BC |
2438 | }; |
2439 | ||
2440 | /* mmc5 */ | |
407a6888 BC |
2441 | static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { |
2442 | { .irq = 59 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2443 | { .irq = -1 } |
407a6888 BC |
2444 | }; |
2445 | ||
2446 | static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { | |
2447 | { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, | |
2448 | { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2449 | { .dma_req = -1 } |
407a6888 BC |
2450 | }; |
2451 | ||
407a6888 BC |
2452 | static struct omap_hwmod omap44xx_mmc5_hwmod = { |
2453 | .name = "mmc5", | |
2454 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2455 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2456 | .mpu_irqs = omap44xx_mmc5_irqs, |
407a6888 | 2457 | .sdma_reqs = omap44xx_mmc5_sdma_reqs, |
407a6888 | 2458 | .main_clk = "mmc5_fck", |
00fe610b | 2459 | .prcm = { |
407a6888 | 2460 | .omap4 = { |
d0f0631d | 2461 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET, |
27bb00b5 | 2462 | .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET, |
03fdefe5 | 2463 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2464 | }, |
2465 | }, | |
407a6888 BC |
2466 | }; |
2467 | ||
230844db ORL |
2468 | /* |
2469 | * 'mmu' class | |
2470 | * The memory management unit performs virtual to physical address translation | |
2471 | * for its requestors. | |
2472 | */ | |
2473 | ||
2474 | static struct omap_hwmod_class_sysconfig mmu_sysc = { | |
2475 | .rev_offs = 0x000, | |
2476 | .sysc_offs = 0x010, | |
2477 | .syss_offs = 0x014, | |
2478 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
2479 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
2480 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2481 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2482 | }; | |
2483 | ||
2484 | static struct omap_hwmod_class omap44xx_mmu_hwmod_class = { | |
2485 | .name = "mmu", | |
2486 | .sysc = &mmu_sysc, | |
2487 | }; | |
2488 | ||
2489 | /* mmu ipu */ | |
2490 | ||
2491 | static struct omap_mmu_dev_attr mmu_ipu_dev_attr = { | |
2492 | .da_start = 0x0, | |
2493 | .da_end = 0xfffff000, | |
2494 | .nr_tlb_entries = 32, | |
2495 | }; | |
2496 | ||
2497 | static struct omap_hwmod omap44xx_mmu_ipu_hwmod; | |
2498 | static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = { | |
2499 | { .irq = 100 + OMAP44XX_IRQ_GIC_START, }, | |
2500 | { .irq = -1 } | |
2501 | }; | |
2502 | ||
2503 | static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = { | |
2504 | { .name = "mmu_cache", .rst_shift = 2 }, | |
2505 | }; | |
2506 | ||
2507 | static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = { | |
2508 | { | |
2509 | .pa_start = 0x55082000, | |
2510 | .pa_end = 0x550820ff, | |
2511 | .flags = ADDR_TYPE_RT, | |
2512 | }, | |
2513 | { } | |
2514 | }; | |
2515 | ||
2516 | /* l3_main_2 -> mmu_ipu */ | |
2517 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = { | |
2518 | .master = &omap44xx_l3_main_2_hwmod, | |
2519 | .slave = &omap44xx_mmu_ipu_hwmod, | |
2520 | .clk = "l3_div_ck", | |
2521 | .addr = omap44xx_mmu_ipu_addrs, | |
2522 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2523 | }; | |
2524 | ||
2525 | static struct omap_hwmod omap44xx_mmu_ipu_hwmod = { | |
2526 | .name = "mmu_ipu", | |
2527 | .class = &omap44xx_mmu_hwmod_class, | |
2528 | .clkdm_name = "ducati_clkdm", | |
2529 | .mpu_irqs = omap44xx_mmu_ipu_irqs, | |
2530 | .rst_lines = omap44xx_mmu_ipu_resets, | |
2531 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets), | |
2532 | .main_clk = "ducati_clk_mux_ck", | |
2533 | .prcm = { | |
2534 | .omap4 = { | |
2535 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, | |
2536 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, | |
2537 | .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, | |
2538 | .modulemode = MODULEMODE_HWCTRL, | |
2539 | }, | |
2540 | }, | |
2541 | .dev_attr = &mmu_ipu_dev_attr, | |
2542 | }; | |
2543 | ||
2544 | /* mmu dsp */ | |
2545 | ||
2546 | static struct omap_mmu_dev_attr mmu_dsp_dev_attr = { | |
2547 | .da_start = 0x0, | |
2548 | .da_end = 0xfffff000, | |
2549 | .nr_tlb_entries = 32, | |
2550 | }; | |
2551 | ||
2552 | static struct omap_hwmod omap44xx_mmu_dsp_hwmod; | |
2553 | static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = { | |
2554 | { .irq = 28 + OMAP44XX_IRQ_GIC_START }, | |
2555 | { .irq = -1 } | |
2556 | }; | |
2557 | ||
2558 | static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = { | |
2559 | { .name = "mmu_cache", .rst_shift = 1 }, | |
2560 | }; | |
2561 | ||
2562 | static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = { | |
2563 | { | |
2564 | .pa_start = 0x4a066000, | |
2565 | .pa_end = 0x4a0660ff, | |
2566 | .flags = ADDR_TYPE_RT, | |
2567 | }, | |
2568 | { } | |
2569 | }; | |
2570 | ||
2571 | /* l4_cfg -> dsp */ | |
2572 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = { | |
2573 | .master = &omap44xx_l4_cfg_hwmod, | |
2574 | .slave = &omap44xx_mmu_dsp_hwmod, | |
2575 | .clk = "l4_div_ck", | |
2576 | .addr = omap44xx_mmu_dsp_addrs, | |
2577 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2578 | }; | |
2579 | ||
2580 | static struct omap_hwmod omap44xx_mmu_dsp_hwmod = { | |
2581 | .name = "mmu_dsp", | |
2582 | .class = &omap44xx_mmu_hwmod_class, | |
2583 | .clkdm_name = "tesla_clkdm", | |
2584 | .mpu_irqs = omap44xx_mmu_dsp_irqs, | |
2585 | .rst_lines = omap44xx_mmu_dsp_resets, | |
2586 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets), | |
2587 | .main_clk = "dpll_iva_m4x2_ck", | |
2588 | .prcm = { | |
2589 | .omap4 = { | |
2590 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, | |
2591 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, | |
2592 | .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, | |
2593 | .modulemode = MODULEMODE_HWCTRL, | |
2594 | }, | |
2595 | }, | |
2596 | .dev_attr = &mmu_dsp_dev_attr, | |
2597 | }; | |
2598 | ||
3b54baad BC |
2599 | /* |
2600 | * 'mpu' class | |
2601 | * mpu sub-system | |
2602 | */ | |
2603 | ||
2604 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { | |
fe13471c | 2605 | .name = "mpu", |
db12ba53 BC |
2606 | }; |
2607 | ||
3b54baad BC |
2608 | /* mpu */ |
2609 | static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { | |
2610 | { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, | |
2611 | { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, | |
2612 | { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2613 | { .irq = -1 } |
db12ba53 BC |
2614 | }; |
2615 | ||
3b54baad BC |
2616 | static struct omap_hwmod omap44xx_mpu_hwmod = { |
2617 | .name = "mpu", | |
2618 | .class = &omap44xx_mpu_hwmod_class, | |
a5322c6f | 2619 | .clkdm_name = "mpuss_clkdm", |
7ecc5373 | 2620 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
3b54baad | 2621 | .mpu_irqs = omap44xx_mpu_irqs, |
3b54baad | 2622 | .main_clk = "dpll_mpu_m2_ck", |
db12ba53 BC |
2623 | .prcm = { |
2624 | .omap4 = { | |
d0f0631d | 2625 | .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 2626 | .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, |
db12ba53 BC |
2627 | }, |
2628 | }, | |
db12ba53 BC |
2629 | }; |
2630 | ||
e17f18c0 PW |
2631 | /* |
2632 | * 'ocmc_ram' class | |
2633 | * top-level core on-chip ram | |
2634 | */ | |
2635 | ||
2636 | static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = { | |
2637 | .name = "ocmc_ram", | |
2638 | }; | |
2639 | ||
2640 | /* ocmc_ram */ | |
2641 | static struct omap_hwmod omap44xx_ocmc_ram_hwmod = { | |
2642 | .name = "ocmc_ram", | |
2643 | .class = &omap44xx_ocmc_ram_hwmod_class, | |
2644 | .clkdm_name = "l3_2_clkdm", | |
2645 | .prcm = { | |
2646 | .omap4 = { | |
2647 | .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET, | |
2648 | .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET, | |
2649 | }, | |
2650 | }, | |
2651 | }; | |
2652 | ||
0c668875 BC |
2653 | /* |
2654 | * 'ocp2scp' class | |
2655 | * bridge to transform ocp interface protocol to scp (serial control port) | |
2656 | * protocol | |
2657 | */ | |
2658 | ||
33c976ec BC |
2659 | static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = { |
2660 | .rev_offs = 0x0000, | |
2661 | .sysc_offs = 0x0010, | |
2662 | .syss_offs = 0x0014, | |
2663 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
2664 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
2665 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2666 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2667 | }; | |
2668 | ||
0c668875 BC |
2669 | static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = { |
2670 | .name = "ocp2scp", | |
33c976ec | 2671 | .sysc = &omap44xx_ocp2scp_sysc, |
0c668875 BC |
2672 | }; |
2673 | ||
2674 | /* ocp2scp_usb_phy */ | |
0c668875 BC |
2675 | static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { |
2676 | .name = "ocp2scp_usb_phy", | |
2677 | .class = &omap44xx_ocp2scp_hwmod_class, | |
2678 | .clkdm_name = "l3_init_clkdm", | |
1b024d2f | 2679 | .main_clk = "ocp2scp_usb_phy_phy_48m", |
0c668875 BC |
2680 | .prcm = { |
2681 | .omap4 = { | |
2682 | .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, | |
2683 | .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET, | |
2684 | .modulemode = MODULEMODE_HWCTRL, | |
2685 | }, | |
2686 | }, | |
0c668875 BC |
2687 | }; |
2688 | ||
794b480a PW |
2689 | /* |
2690 | * 'prcm' class | |
2691 | * power and reset manager (part of the prcm infrastructure) + clock manager 2 | |
2692 | * + clock manager 1 (in always on power domain) + local prm in mpu | |
2693 | */ | |
2694 | ||
2695 | static struct omap_hwmod_class omap44xx_prcm_hwmod_class = { | |
2696 | .name = "prcm", | |
2697 | }; | |
2698 | ||
2699 | /* prcm_mpu */ | |
2700 | static struct omap_hwmod omap44xx_prcm_mpu_hwmod = { | |
2701 | .name = "prcm_mpu", | |
2702 | .class = &omap44xx_prcm_hwmod_class, | |
2703 | .clkdm_name = "l4_wkup_clkdm", | |
53cce97c | 2704 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
2705 | .prcm = { |
2706 | .omap4 = { | |
2707 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2708 | }, | |
2709 | }, | |
794b480a PW |
2710 | }; |
2711 | ||
2712 | /* cm_core_aon */ | |
2713 | static struct omap_hwmod omap44xx_cm_core_aon_hwmod = { | |
2714 | .name = "cm_core_aon", | |
2715 | .class = &omap44xx_prcm_hwmod_class, | |
53cce97c | 2716 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
2717 | .prcm = { |
2718 | .omap4 = { | |
2719 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2720 | }, | |
2721 | }, | |
794b480a PW |
2722 | }; |
2723 | ||
2724 | /* cm_core */ | |
2725 | static struct omap_hwmod omap44xx_cm_core_hwmod = { | |
2726 | .name = "cm_core", | |
2727 | .class = &omap44xx_prcm_hwmod_class, | |
53cce97c | 2728 | .flags = HWMOD_NO_IDLEST, |
46b3af27 TK |
2729 | .prcm = { |
2730 | .omap4 = { | |
2731 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2732 | }, | |
2733 | }, | |
794b480a PW |
2734 | }; |
2735 | ||
2736 | /* prm */ | |
2737 | static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = { | |
2738 | { .irq = 11 + OMAP44XX_IRQ_GIC_START }, | |
2739 | { .irq = -1 } | |
2740 | }; | |
2741 | ||
2742 | static struct omap_hwmod_rst_info omap44xx_prm_resets[] = { | |
2743 | { .name = "rst_global_warm_sw", .rst_shift = 0 }, | |
2744 | { .name = "rst_global_cold_sw", .rst_shift = 1 }, | |
2745 | }; | |
2746 | ||
2747 | static struct omap_hwmod omap44xx_prm_hwmod = { | |
2748 | .name = "prm", | |
2749 | .class = &omap44xx_prcm_hwmod_class, | |
794b480a PW |
2750 | .mpu_irqs = omap44xx_prm_irqs, |
2751 | .rst_lines = omap44xx_prm_resets, | |
2752 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets), | |
2753 | }; | |
2754 | ||
2755 | /* | |
2756 | * 'scrm' class | |
2757 | * system clock and reset manager | |
2758 | */ | |
2759 | ||
2760 | static struct omap_hwmod_class omap44xx_scrm_hwmod_class = { | |
2761 | .name = "scrm", | |
2762 | }; | |
2763 | ||
2764 | /* scrm */ | |
2765 | static struct omap_hwmod omap44xx_scrm_hwmod = { | |
2766 | .name = "scrm", | |
2767 | .class = &omap44xx_scrm_hwmod_class, | |
2768 | .clkdm_name = "l4_wkup_clkdm", | |
46b3af27 TK |
2769 | .prcm = { |
2770 | .omap4 = { | |
2771 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
2772 | }, | |
2773 | }, | |
794b480a PW |
2774 | }; |
2775 | ||
42b9e387 PW |
2776 | /* |
2777 | * 'sl2if' class | |
2778 | * shared level 2 memory interface | |
2779 | */ | |
2780 | ||
2781 | static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = { | |
2782 | .name = "sl2if", | |
2783 | }; | |
2784 | ||
2785 | /* sl2if */ | |
2786 | static struct omap_hwmod omap44xx_sl2if_hwmod = { | |
2787 | .name = "sl2if", | |
2788 | .class = &omap44xx_sl2if_hwmod_class, | |
2789 | .clkdm_name = "ivahd_clkdm", | |
2790 | .prcm = { | |
2791 | .omap4 = { | |
2792 | .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET, | |
2793 | .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET, | |
2794 | .modulemode = MODULEMODE_HWCTRL, | |
2795 | }, | |
2796 | }, | |
2797 | }; | |
2798 | ||
1e3b5e59 BC |
2799 | /* |
2800 | * 'slimbus' class | |
2801 | * bidirectional, multi-drop, multi-channel two-line serial interface between | |
2802 | * the device and external components | |
2803 | */ | |
2804 | ||
2805 | static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = { | |
2806 | .rev_offs = 0x0000, | |
2807 | .sysc_offs = 0x0010, | |
2808 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
2809 | SYSC_HAS_SOFTRESET), | |
2810 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2811 | SIDLE_SMART_WKUP), | |
2812 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2813 | }; | |
2814 | ||
2815 | static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = { | |
2816 | .name = "slimbus", | |
2817 | .sysc = &omap44xx_slimbus_sysc, | |
2818 | }; | |
2819 | ||
2820 | /* slimbus1 */ | |
2821 | static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = { | |
2822 | { .irq = 97 + OMAP44XX_IRQ_GIC_START }, | |
2823 | { .irq = -1 } | |
2824 | }; | |
2825 | ||
2826 | static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = { | |
2827 | { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START }, | |
2828 | { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START }, | |
2829 | { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START }, | |
2830 | { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START }, | |
2831 | { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START }, | |
2832 | { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START }, | |
2833 | { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START }, | |
2834 | { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START }, | |
2835 | { .dma_req = -1 } | |
2836 | }; | |
2837 | ||
2838 | static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = { | |
2839 | { .role = "fclk_1", .clk = "slimbus1_fclk_1" }, | |
2840 | { .role = "fclk_0", .clk = "slimbus1_fclk_0" }, | |
2841 | { .role = "fclk_2", .clk = "slimbus1_fclk_2" }, | |
2842 | { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" }, | |
2843 | }; | |
2844 | ||
2845 | static struct omap_hwmod omap44xx_slimbus1_hwmod = { | |
2846 | .name = "slimbus1", | |
2847 | .class = &omap44xx_slimbus_hwmod_class, | |
2848 | .clkdm_name = "abe_clkdm", | |
2849 | .mpu_irqs = omap44xx_slimbus1_irqs, | |
2850 | .sdma_reqs = omap44xx_slimbus1_sdma_reqs, | |
2851 | .prcm = { | |
2852 | .omap4 = { | |
2853 | .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET, | |
2854 | .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET, | |
2855 | .modulemode = MODULEMODE_SWCTRL, | |
2856 | }, | |
2857 | }, | |
2858 | .opt_clks = slimbus1_opt_clks, | |
2859 | .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks), | |
2860 | }; | |
2861 | ||
2862 | /* slimbus2 */ | |
2863 | static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = { | |
2864 | { .irq = 98 + OMAP44XX_IRQ_GIC_START }, | |
2865 | { .irq = -1 } | |
2866 | }; | |
2867 | ||
2868 | static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = { | |
2869 | { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START }, | |
2870 | { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START }, | |
2871 | { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START }, | |
2872 | { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START }, | |
2873 | { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START }, | |
2874 | { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START }, | |
2875 | { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START }, | |
2876 | { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START }, | |
2877 | { .dma_req = -1 } | |
2878 | }; | |
2879 | ||
2880 | static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = { | |
2881 | { .role = "fclk_1", .clk = "slimbus2_fclk_1" }, | |
2882 | { .role = "fclk_0", .clk = "slimbus2_fclk_0" }, | |
2883 | { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" }, | |
2884 | }; | |
2885 | ||
2886 | static struct omap_hwmod omap44xx_slimbus2_hwmod = { | |
2887 | .name = "slimbus2", | |
2888 | .class = &omap44xx_slimbus_hwmod_class, | |
2889 | .clkdm_name = "l4_per_clkdm", | |
2890 | .mpu_irqs = omap44xx_slimbus2_irqs, | |
2891 | .sdma_reqs = omap44xx_slimbus2_sdma_reqs, | |
2892 | .prcm = { | |
2893 | .omap4 = { | |
2894 | .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET, | |
2895 | .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET, | |
2896 | .modulemode = MODULEMODE_SWCTRL, | |
2897 | }, | |
2898 | }, | |
2899 | .opt_clks = slimbus2_opt_clks, | |
2900 | .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks), | |
2901 | }; | |
2902 | ||
1f6a717f BC |
2903 | /* |
2904 | * 'smartreflex' class | |
2905 | * smartreflex module (monitor silicon performance and outputs a measure of | |
2906 | * performance error) | |
2907 | */ | |
2908 | ||
2909 | /* The IP is not compliant to type1 / type2 scheme */ | |
2910 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { | |
2911 | .sidle_shift = 24, | |
2912 | .enwkup_shift = 26, | |
2913 | }; | |
2914 | ||
2915 | static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { | |
2916 | .sysc_offs = 0x0038, | |
2917 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), | |
2918 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2919 | SIDLE_SMART_WKUP), | |
2920 | .sysc_fields = &omap_hwmod_sysc_type_smartreflex, | |
2921 | }; | |
2922 | ||
2923 | static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { | |
fe13471c BC |
2924 | .name = "smartreflex", |
2925 | .sysc = &omap44xx_smartreflex_sysc, | |
2926 | .rev = 2, | |
1f6a717f BC |
2927 | }; |
2928 | ||
2929 | /* smartreflex_core */ | |
cea6b942 SG |
2930 | static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { |
2931 | .sensor_voltdm_name = "core", | |
2932 | }; | |
2933 | ||
1f6a717f BC |
2934 | static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { |
2935 | { .irq = 19 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2936 | { .irq = -1 } |
1f6a717f BC |
2937 | }; |
2938 | ||
1f6a717f BC |
2939 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { |
2940 | .name = "smartreflex_core", | |
2941 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2942 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2943 | .mpu_irqs = omap44xx_smartreflex_core_irqs, |
212738a4 | 2944 | |
1f6a717f | 2945 | .main_clk = "smartreflex_core_fck", |
1f6a717f BC |
2946 | .prcm = { |
2947 | .omap4 = { | |
d0f0631d | 2948 | .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET, |
27bb00b5 | 2949 | .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET, |
03fdefe5 | 2950 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2951 | }, |
2952 | }, | |
cea6b942 | 2953 | .dev_attr = &smartreflex_core_dev_attr, |
1f6a717f BC |
2954 | }; |
2955 | ||
2956 | /* smartreflex_iva */ | |
cea6b942 SG |
2957 | static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { |
2958 | .sensor_voltdm_name = "iva", | |
2959 | }; | |
2960 | ||
1f6a717f BC |
2961 | static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { |
2962 | { .irq = 102 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2963 | { .irq = -1 } |
1f6a717f BC |
2964 | }; |
2965 | ||
1f6a717f BC |
2966 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { |
2967 | .name = "smartreflex_iva", | |
2968 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2969 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2970 | .mpu_irqs = omap44xx_smartreflex_iva_irqs, |
1f6a717f | 2971 | .main_clk = "smartreflex_iva_fck", |
1f6a717f BC |
2972 | .prcm = { |
2973 | .omap4 = { | |
d0f0631d | 2974 | .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET, |
27bb00b5 | 2975 | .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET, |
03fdefe5 | 2976 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2977 | }, |
2978 | }, | |
cea6b942 | 2979 | .dev_attr = &smartreflex_iva_dev_attr, |
1f6a717f BC |
2980 | }; |
2981 | ||
2982 | /* smartreflex_mpu */ | |
cea6b942 SG |
2983 | static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { |
2984 | .sensor_voltdm_name = "mpu", | |
2985 | }; | |
2986 | ||
1f6a717f BC |
2987 | static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { |
2988 | { .irq = 18 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2989 | { .irq = -1 } |
1f6a717f BC |
2990 | }; |
2991 | ||
1f6a717f BC |
2992 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { |
2993 | .name = "smartreflex_mpu", | |
2994 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2995 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2996 | .mpu_irqs = omap44xx_smartreflex_mpu_irqs, |
1f6a717f | 2997 | .main_clk = "smartreflex_mpu_fck", |
1f6a717f BC |
2998 | .prcm = { |
2999 | .omap4 = { | |
d0f0631d | 3000 | .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 3001 | .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET, |
03fdefe5 | 3002 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
3003 | }, |
3004 | }, | |
cea6b942 | 3005 | .dev_attr = &smartreflex_mpu_dev_attr, |
1f6a717f BC |
3006 | }; |
3007 | ||
d11c217f BC |
3008 | /* |
3009 | * 'spinlock' class | |
3010 | * spinlock provides hardware assistance for synchronizing the processes | |
3011 | * running on multiple processors | |
3012 | */ | |
3013 | ||
3014 | static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = { | |
3015 | .rev_offs = 0x0000, | |
3016 | .sysc_offs = 0x0010, | |
3017 | .syss_offs = 0x0014, | |
3018 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
3019 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
3020 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
3021 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3022 | SIDLE_SMART_WKUP), | |
3023 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3024 | }; | |
3025 | ||
3026 | static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { | |
3027 | .name = "spinlock", | |
3028 | .sysc = &omap44xx_spinlock_sysc, | |
3029 | }; | |
3030 | ||
3031 | /* spinlock */ | |
d11c217f BC |
3032 | static struct omap_hwmod omap44xx_spinlock_hwmod = { |
3033 | .name = "spinlock", | |
3034 | .class = &omap44xx_spinlock_hwmod_class, | |
a5322c6f | 3035 | .clkdm_name = "l4_cfg_clkdm", |
d11c217f BC |
3036 | .prcm = { |
3037 | .omap4 = { | |
d0f0631d | 3038 | .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET, |
27bb00b5 | 3039 | .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, |
d11c217f BC |
3040 | }, |
3041 | }, | |
d11c217f BC |
3042 | }; |
3043 | ||
35d1a66a BC |
3044 | /* |
3045 | * 'timer' class | |
3046 | * general purpose timer module with accurate 1ms tick | |
3047 | * This class contains several variants: ['timer_1ms', 'timer'] | |
3048 | */ | |
3049 | ||
3050 | static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = { | |
3051 | .rev_offs = 0x0000, | |
3052 | .sysc_offs = 0x0010, | |
3053 | .syss_offs = 0x0014, | |
3054 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
3055 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
3056 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
3057 | SYSS_HAS_RESET_STATUS), | |
3058 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
3059 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3060 | }; | |
3061 | ||
3062 | static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = { | |
3063 | .name = "timer", | |
3064 | .sysc = &omap44xx_timer_1ms_sysc, | |
3065 | }; | |
3066 | ||
3067 | static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = { | |
3068 | .rev_offs = 0x0000, | |
3069 | .sysc_offs = 0x0010, | |
3070 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
3071 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
3072 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3073 | SIDLE_SMART_WKUP), | |
3074 | .sysc_fields = &omap_hwmod_sysc_type2, | |
3075 | }; | |
3076 | ||
3077 | static struct omap_hwmod_class omap44xx_timer_hwmod_class = { | |
3078 | .name = "timer", | |
3079 | .sysc = &omap44xx_timer_sysc, | |
3080 | }; | |
3081 | ||
c345c8b0 TKD |
3082 | /* always-on timers dev attribute */ |
3083 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
3084 | .timer_capability = OMAP_TIMER_ALWON, | |
3085 | }; | |
3086 | ||
3087 | /* pwm timers dev attribute */ | |
3088 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
3089 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
3090 | }; | |
3091 | ||
35d1a66a | 3092 | /* timer1 */ |
35d1a66a BC |
3093 | static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { |
3094 | { .irq = 37 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3095 | { .irq = -1 } |
35d1a66a BC |
3096 | }; |
3097 | ||
35d1a66a BC |
3098 | static struct omap_hwmod omap44xx_timer1_hwmod = { |
3099 | .name = "timer1", | |
3100 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 3101 | .clkdm_name = "l4_wkup_clkdm", |
35d1a66a | 3102 | .mpu_irqs = omap44xx_timer1_irqs, |
35d1a66a BC |
3103 | .main_clk = "timer1_fck", |
3104 | .prcm = { | |
3105 | .omap4 = { | |
d0f0631d | 3106 | .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, |
27bb00b5 | 3107 | .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET, |
03fdefe5 | 3108 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3109 | }, |
3110 | }, | |
c345c8b0 | 3111 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
3112 | }; |
3113 | ||
3114 | /* timer2 */ | |
35d1a66a BC |
3115 | static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { |
3116 | { .irq = 38 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3117 | { .irq = -1 } |
35d1a66a BC |
3118 | }; |
3119 | ||
35d1a66a BC |
3120 | static struct omap_hwmod omap44xx_timer2_hwmod = { |
3121 | .name = "timer2", | |
3122 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 3123 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 3124 | .mpu_irqs = omap44xx_timer2_irqs, |
35d1a66a BC |
3125 | .main_clk = "timer2_fck", |
3126 | .prcm = { | |
3127 | .omap4 = { | |
d0f0631d | 3128 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, |
27bb00b5 | 3129 | .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET, |
03fdefe5 | 3130 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3131 | }, |
3132 | }, | |
35d1a66a BC |
3133 | }; |
3134 | ||
3135 | /* timer3 */ | |
35d1a66a BC |
3136 | static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { |
3137 | { .irq = 39 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3138 | { .irq = -1 } |
35d1a66a BC |
3139 | }; |
3140 | ||
35d1a66a BC |
3141 | static struct omap_hwmod omap44xx_timer3_hwmod = { |
3142 | .name = "timer3", | |
3143 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3144 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 3145 | .mpu_irqs = omap44xx_timer3_irqs, |
35d1a66a BC |
3146 | .main_clk = "timer3_fck", |
3147 | .prcm = { | |
3148 | .omap4 = { | |
d0f0631d | 3149 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, |
27bb00b5 | 3150 | .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET, |
03fdefe5 | 3151 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3152 | }, |
3153 | }, | |
35d1a66a BC |
3154 | }; |
3155 | ||
3156 | /* timer4 */ | |
35d1a66a BC |
3157 | static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { |
3158 | { .irq = 40 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3159 | { .irq = -1 } |
35d1a66a BC |
3160 | }; |
3161 | ||
35d1a66a BC |
3162 | static struct omap_hwmod omap44xx_timer4_hwmod = { |
3163 | .name = "timer4", | |
3164 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3165 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 3166 | .mpu_irqs = omap44xx_timer4_irqs, |
35d1a66a BC |
3167 | .main_clk = "timer4_fck", |
3168 | .prcm = { | |
3169 | .omap4 = { | |
d0f0631d | 3170 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, |
27bb00b5 | 3171 | .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET, |
03fdefe5 | 3172 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3173 | }, |
3174 | }, | |
35d1a66a BC |
3175 | }; |
3176 | ||
3177 | /* timer5 */ | |
35d1a66a BC |
3178 | static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { |
3179 | { .irq = 41 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3180 | { .irq = -1 } |
35d1a66a BC |
3181 | }; |
3182 | ||
35d1a66a BC |
3183 | static struct omap_hwmod omap44xx_timer5_hwmod = { |
3184 | .name = "timer5", | |
3185 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3186 | .clkdm_name = "abe_clkdm", |
35d1a66a | 3187 | .mpu_irqs = omap44xx_timer5_irqs, |
35d1a66a BC |
3188 | .main_clk = "timer5_fck", |
3189 | .prcm = { | |
3190 | .omap4 = { | |
d0f0631d | 3191 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, |
27bb00b5 | 3192 | .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET, |
03fdefe5 | 3193 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3194 | }, |
3195 | }, | |
35d1a66a BC |
3196 | }; |
3197 | ||
3198 | /* timer6 */ | |
35d1a66a BC |
3199 | static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { |
3200 | { .irq = 42 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3201 | { .irq = -1 } |
35d1a66a BC |
3202 | }; |
3203 | ||
35d1a66a BC |
3204 | static struct omap_hwmod omap44xx_timer6_hwmod = { |
3205 | .name = "timer6", | |
3206 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3207 | .clkdm_name = "abe_clkdm", |
35d1a66a | 3208 | .mpu_irqs = omap44xx_timer6_irqs, |
212738a4 | 3209 | |
35d1a66a BC |
3210 | .main_clk = "timer6_fck", |
3211 | .prcm = { | |
3212 | .omap4 = { | |
d0f0631d | 3213 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, |
27bb00b5 | 3214 | .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET, |
03fdefe5 | 3215 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3216 | }, |
3217 | }, | |
35d1a66a BC |
3218 | }; |
3219 | ||
3220 | /* timer7 */ | |
35d1a66a BC |
3221 | static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { |
3222 | { .irq = 43 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3223 | { .irq = -1 } |
35d1a66a BC |
3224 | }; |
3225 | ||
35d1a66a BC |
3226 | static struct omap_hwmod omap44xx_timer7_hwmod = { |
3227 | .name = "timer7", | |
3228 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3229 | .clkdm_name = "abe_clkdm", |
35d1a66a | 3230 | .mpu_irqs = omap44xx_timer7_irqs, |
35d1a66a BC |
3231 | .main_clk = "timer7_fck", |
3232 | .prcm = { | |
3233 | .omap4 = { | |
d0f0631d | 3234 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, |
27bb00b5 | 3235 | .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET, |
03fdefe5 | 3236 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3237 | }, |
3238 | }, | |
35d1a66a BC |
3239 | }; |
3240 | ||
3241 | /* timer8 */ | |
35d1a66a BC |
3242 | static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { |
3243 | { .irq = 44 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3244 | { .irq = -1 } |
35d1a66a BC |
3245 | }; |
3246 | ||
35d1a66a BC |
3247 | static struct omap_hwmod omap44xx_timer8_hwmod = { |
3248 | .name = "timer8", | |
3249 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3250 | .clkdm_name = "abe_clkdm", |
35d1a66a | 3251 | .mpu_irqs = omap44xx_timer8_irqs, |
35d1a66a BC |
3252 | .main_clk = "timer8_fck", |
3253 | .prcm = { | |
3254 | .omap4 = { | |
d0f0631d | 3255 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, |
27bb00b5 | 3256 | .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET, |
03fdefe5 | 3257 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3258 | }, |
3259 | }, | |
c345c8b0 | 3260 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
3261 | }; |
3262 | ||
3263 | /* timer9 */ | |
35d1a66a BC |
3264 | static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { |
3265 | { .irq = 45 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3266 | { .irq = -1 } |
35d1a66a BC |
3267 | }; |
3268 | ||
35d1a66a BC |
3269 | static struct omap_hwmod omap44xx_timer9_hwmod = { |
3270 | .name = "timer9", | |
3271 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3272 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 3273 | .mpu_irqs = omap44xx_timer9_irqs, |
35d1a66a BC |
3274 | .main_clk = "timer9_fck", |
3275 | .prcm = { | |
3276 | .omap4 = { | |
d0f0631d | 3277 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, |
27bb00b5 | 3278 | .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET, |
03fdefe5 | 3279 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3280 | }, |
3281 | }, | |
c345c8b0 | 3282 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
3283 | }; |
3284 | ||
3285 | /* timer10 */ | |
35d1a66a BC |
3286 | static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { |
3287 | { .irq = 46 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3288 | { .irq = -1 } |
35d1a66a BC |
3289 | }; |
3290 | ||
35d1a66a BC |
3291 | static struct omap_hwmod omap44xx_timer10_hwmod = { |
3292 | .name = "timer10", | |
3293 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 3294 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 3295 | .mpu_irqs = omap44xx_timer10_irqs, |
35d1a66a BC |
3296 | .main_clk = "timer10_fck", |
3297 | .prcm = { | |
3298 | .omap4 = { | |
d0f0631d | 3299 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, |
27bb00b5 | 3300 | .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET, |
03fdefe5 | 3301 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3302 | }, |
3303 | }, | |
c345c8b0 | 3304 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
3305 | }; |
3306 | ||
3307 | /* timer11 */ | |
35d1a66a BC |
3308 | static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { |
3309 | { .irq = 47 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3310 | { .irq = -1 } |
35d1a66a BC |
3311 | }; |
3312 | ||
35d1a66a BC |
3313 | static struct omap_hwmod omap44xx_timer11_hwmod = { |
3314 | .name = "timer11", | |
3315 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3316 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 3317 | .mpu_irqs = omap44xx_timer11_irqs, |
35d1a66a BC |
3318 | .main_clk = "timer11_fck", |
3319 | .prcm = { | |
3320 | .omap4 = { | |
d0f0631d | 3321 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, |
27bb00b5 | 3322 | .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET, |
03fdefe5 | 3323 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3324 | }, |
3325 | }, | |
c345c8b0 | 3326 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
3327 | }; |
3328 | ||
9780a9cf | 3329 | /* |
3b54baad BC |
3330 | * 'uart' class |
3331 | * universal asynchronous receiver/transmitter (uart) | |
9780a9cf BC |
3332 | */ |
3333 | ||
3b54baad BC |
3334 | static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { |
3335 | .rev_offs = 0x0050, | |
3336 | .sysc_offs = 0x0054, | |
3337 | .syss_offs = 0x0058, | |
3338 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
0cfe8751 BC |
3339 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
3340 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
3341 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3342 | SIDLE_SMART_WKUP), | |
9780a9cf BC |
3343 | .sysc_fields = &omap_hwmod_sysc_type1, |
3344 | }; | |
3345 | ||
3b54baad | 3346 | static struct omap_hwmod_class omap44xx_uart_hwmod_class = { |
fe13471c BC |
3347 | .name = "uart", |
3348 | .sysc = &omap44xx_uart_sysc, | |
9780a9cf BC |
3349 | }; |
3350 | ||
3b54baad | 3351 | /* uart1 */ |
3b54baad BC |
3352 | static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { |
3353 | { .irq = 72 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3354 | { .irq = -1 } |
9780a9cf BC |
3355 | }; |
3356 | ||
3b54baad BC |
3357 | static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { |
3358 | { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, | |
3359 | { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3360 | { .dma_req = -1 } |
9780a9cf BC |
3361 | }; |
3362 | ||
3b54baad BC |
3363 | static struct omap_hwmod omap44xx_uart1_hwmod = { |
3364 | .name = "uart1", | |
3365 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3366 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 3367 | .mpu_irqs = omap44xx_uart1_irqs, |
3b54baad | 3368 | .sdma_reqs = omap44xx_uart1_sdma_reqs, |
3b54baad | 3369 | .main_clk = "uart1_fck", |
9780a9cf BC |
3370 | .prcm = { |
3371 | .omap4 = { | |
d0f0631d | 3372 | .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET, |
27bb00b5 | 3373 | .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET, |
03fdefe5 | 3374 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3375 | }, |
3376 | }, | |
9780a9cf BC |
3377 | }; |
3378 | ||
3b54baad | 3379 | /* uart2 */ |
3b54baad BC |
3380 | static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { |
3381 | { .irq = 73 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3382 | { .irq = -1 } |
9780a9cf BC |
3383 | }; |
3384 | ||
3b54baad BC |
3385 | static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { |
3386 | { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, | |
3387 | { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3388 | { .dma_req = -1 } |
3b54baad BC |
3389 | }; |
3390 | ||
3b54baad BC |
3391 | static struct omap_hwmod omap44xx_uart2_hwmod = { |
3392 | .name = "uart2", | |
3393 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3394 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 3395 | .mpu_irqs = omap44xx_uart2_irqs, |
3b54baad | 3396 | .sdma_reqs = omap44xx_uart2_sdma_reqs, |
3b54baad | 3397 | .main_clk = "uart2_fck", |
9780a9cf BC |
3398 | .prcm = { |
3399 | .omap4 = { | |
d0f0631d | 3400 | .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET, |
27bb00b5 | 3401 | .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET, |
03fdefe5 | 3402 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3403 | }, |
3404 | }, | |
9780a9cf BC |
3405 | }; |
3406 | ||
3b54baad | 3407 | /* uart3 */ |
3b54baad BC |
3408 | static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { |
3409 | { .irq = 74 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3410 | { .irq = -1 } |
9780a9cf BC |
3411 | }; |
3412 | ||
3b54baad BC |
3413 | static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { |
3414 | { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, | |
3415 | { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3416 | { .dma_req = -1 } |
3b54baad BC |
3417 | }; |
3418 | ||
3b54baad BC |
3419 | static struct omap_hwmod omap44xx_uart3_hwmod = { |
3420 | .name = "uart3", | |
3421 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3422 | .clkdm_name = "l4_per_clkdm", |
7ecc5373 | 3423 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
3b54baad | 3424 | .mpu_irqs = omap44xx_uart3_irqs, |
3b54baad | 3425 | .sdma_reqs = omap44xx_uart3_sdma_reqs, |
3b54baad | 3426 | .main_clk = "uart3_fck", |
9780a9cf BC |
3427 | .prcm = { |
3428 | .omap4 = { | |
d0f0631d | 3429 | .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET, |
27bb00b5 | 3430 | .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET, |
03fdefe5 | 3431 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3432 | }, |
3433 | }, | |
9780a9cf BC |
3434 | }; |
3435 | ||
3b54baad | 3436 | /* uart4 */ |
3b54baad BC |
3437 | static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { |
3438 | { .irq = 70 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3439 | { .irq = -1 } |
9780a9cf BC |
3440 | }; |
3441 | ||
3b54baad BC |
3442 | static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { |
3443 | { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, | |
3444 | { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3445 | { .dma_req = -1 } |
3b54baad BC |
3446 | }; |
3447 | ||
3b54baad BC |
3448 | static struct omap_hwmod omap44xx_uart4_hwmod = { |
3449 | .name = "uart4", | |
3450 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3451 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 3452 | .mpu_irqs = omap44xx_uart4_irqs, |
3b54baad | 3453 | .sdma_reqs = omap44xx_uart4_sdma_reqs, |
3b54baad | 3454 | .main_clk = "uart4_fck", |
9780a9cf BC |
3455 | .prcm = { |
3456 | .omap4 = { | |
d0f0631d | 3457 | .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET, |
27bb00b5 | 3458 | .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET, |
03fdefe5 | 3459 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3460 | }, |
3461 | }, | |
9780a9cf BC |
3462 | }; |
3463 | ||
0c668875 BC |
3464 | /* |
3465 | * 'usb_host_fs' class | |
3466 | * full-speed usb host controller | |
3467 | */ | |
3468 | ||
3469 | /* The IP is not compliant to type1 / type2 scheme */ | |
3470 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = { | |
3471 | .midle_shift = 4, | |
3472 | .sidle_shift = 2, | |
3473 | .srst_shift = 1, | |
3474 | }; | |
3475 | ||
3476 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = { | |
3477 | .rev_offs = 0x0000, | |
3478 | .sysc_offs = 0x0210, | |
3479 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
3480 | SYSC_HAS_SOFTRESET), | |
3481 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3482 | SIDLE_SMART_WKUP), | |
3483 | .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs, | |
3484 | }; | |
3485 | ||
3486 | static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = { | |
3487 | .name = "usb_host_fs", | |
3488 | .sysc = &omap44xx_usb_host_fs_sysc, | |
3489 | }; | |
3490 | ||
3491 | /* usb_host_fs */ | |
3492 | static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = { | |
3493 | { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START }, | |
3494 | { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START }, | |
3495 | { .irq = -1 } | |
3496 | }; | |
3497 | ||
3498 | static struct omap_hwmod omap44xx_usb_host_fs_hwmod = { | |
3499 | .name = "usb_host_fs", | |
3500 | .class = &omap44xx_usb_host_fs_hwmod_class, | |
3501 | .clkdm_name = "l3_init_clkdm", | |
3502 | .mpu_irqs = omap44xx_usb_host_fs_irqs, | |
3503 | .main_clk = "usb_host_fs_fck", | |
3504 | .prcm = { | |
3505 | .omap4 = { | |
3506 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET, | |
3507 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET, | |
3508 | .modulemode = MODULEMODE_SWCTRL, | |
3509 | }, | |
3510 | }, | |
3511 | }; | |
3512 | ||
5844c4ea | 3513 | /* |
844a3b63 PW |
3514 | * 'usb_host_hs' class |
3515 | * high-speed multi-port usb host controller | |
5844c4ea BC |
3516 | */ |
3517 | ||
844a3b63 PW |
3518 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { |
3519 | .rev_offs = 0x0000, | |
3520 | .sysc_offs = 0x0010, | |
3521 | .syss_offs = 0x0014, | |
3522 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
3523 | SYSC_HAS_SOFTRESET), | |
5844c4ea BC |
3524 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3525 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
844a3b63 PW |
3526 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
3527 | .sysc_fields = &omap_hwmod_sysc_type2, | |
5844c4ea BC |
3528 | }; |
3529 | ||
844a3b63 PW |
3530 | static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { |
3531 | .name = "usb_host_hs", | |
3532 | .sysc = &omap44xx_usb_host_hs_sysc, | |
5844c4ea BC |
3533 | }; |
3534 | ||
844a3b63 PW |
3535 | /* usb_host_hs */ |
3536 | static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { | |
3537 | { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, | |
3538 | { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3539 | { .irq = -1 } |
5844c4ea BC |
3540 | }; |
3541 | ||
844a3b63 PW |
3542 | static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { |
3543 | .name = "usb_host_hs", | |
3544 | .class = &omap44xx_usb_host_hs_hwmod_class, | |
a5322c6f | 3545 | .clkdm_name = "l3_init_clkdm", |
844a3b63 | 3546 | .main_clk = "usb_host_hs_fck", |
5844c4ea BC |
3547 | .prcm = { |
3548 | .omap4 = { | |
844a3b63 PW |
3549 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, |
3550 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, | |
3551 | .modulemode = MODULEMODE_SWCTRL, | |
3552 | }, | |
3553 | }, | |
3554 | .mpu_irqs = omap44xx_usb_host_hs_irqs, | |
3555 | ||
3556 | /* | |
3557 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
3558 | * id: i660 | |
3559 | * | |
3560 | * Description: | |
3561 | * In the following configuration : | |
3562 | * - USBHOST module is set to smart-idle mode | |
3563 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
3564 | * happens when the system is going to a low power mode : all ports | |
3565 | * have been suspended, the master part of the USBHOST module has | |
3566 | * entered the standby state, and SW has cut the functional clocks) | |
3567 | * - an USBHOST interrupt occurs before the module is able to answer | |
3568 | * idle_ack, typically a remote wakeup IRQ. | |
3569 | * Then the USB HOST module will enter a deadlock situation where it | |
3570 | * is no more accessible nor functional. | |
3571 | * | |
3572 | * Workaround: | |
3573 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
3574 | */ | |
3575 | ||
3576 | /* | |
3577 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
3578 | * Id: i571 | |
3579 | * | |
3580 | * Description: | |
3581 | * When the USBHOST module is set to smart-standby mode, and when it is | |
3582 | * ready to enter the standby state (i.e. all ports are suspended and | |
3583 | * all attached devices are in suspend mode), then it can wrongly assert | |
3584 | * the Mstandby signal too early while there are still some residual OCP | |
3585 | * transactions ongoing. If this condition occurs, the internal state | |
3586 | * machine may go to an undefined state and the USB link may be stuck | |
3587 | * upon the next resume. | |
3588 | * | |
3589 | * Workaround: | |
3590 | * Don't use smart standby; use only force standby, | |
3591 | * hence HWMOD_SWSUP_MSTANDBY | |
3592 | */ | |
3593 | ||
3594 | /* | |
3595 | * During system boot; If the hwmod framework resets the module | |
3596 | * the module will have smart idle settings; which can lead to deadlock | |
3597 | * (above Errata Id:i660); so, dont reset the module during boot; | |
3598 | * Use HWMOD_INIT_NO_RESET. | |
3599 | */ | |
3600 | ||
3601 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | | |
3602 | HWMOD_INIT_NO_RESET, | |
3603 | }; | |
3604 | ||
3605 | /* | |
3606 | * 'usb_otg_hs' class | |
3607 | * high-speed on-the-go universal serial bus (usb_otg_hs) controller | |
3608 | */ | |
3609 | ||
3610 | static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { | |
3611 | .rev_offs = 0x0400, | |
3612 | .sysc_offs = 0x0404, | |
3613 | .syss_offs = 0x0408, | |
3614 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
3615 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
3616 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
3617 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3618 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
3619 | MSTANDBY_SMART), | |
3620 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3621 | }; | |
3622 | ||
3623 | static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { | |
3624 | .name = "usb_otg_hs", | |
3625 | .sysc = &omap44xx_usb_otg_hs_sysc, | |
3626 | }; | |
3627 | ||
3628 | /* usb_otg_hs */ | |
3629 | static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { | |
3630 | { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, | |
3631 | { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, | |
3632 | { .irq = -1 } | |
3633 | }; | |
3634 | ||
3635 | static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { | |
3636 | { .role = "xclk", .clk = "usb_otg_hs_xclk" }, | |
3637 | }; | |
3638 | ||
3639 | static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { | |
3640 | .name = "usb_otg_hs", | |
3641 | .class = &omap44xx_usb_otg_hs_hwmod_class, | |
3642 | .clkdm_name = "l3_init_clkdm", | |
3643 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | |
3644 | .mpu_irqs = omap44xx_usb_otg_hs_irqs, | |
3645 | .main_clk = "usb_otg_hs_ick", | |
3646 | .prcm = { | |
3647 | .omap4 = { | |
3648 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET, | |
3649 | .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET, | |
3650 | .modulemode = MODULEMODE_HWCTRL, | |
3651 | }, | |
3652 | }, | |
3653 | .opt_clks = usb_otg_hs_opt_clks, | |
3654 | .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), | |
3655 | }; | |
3656 | ||
3657 | /* | |
3658 | * 'usb_tll_hs' class | |
3659 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
3660 | */ | |
3661 | ||
3662 | static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { | |
3663 | .rev_offs = 0x0000, | |
3664 | .sysc_offs = 0x0010, | |
3665 | .syss_offs = 0x0014, | |
3666 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
3667 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
3668 | SYSC_HAS_AUTOIDLE), | |
3669 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
3670 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3671 | }; | |
3672 | ||
3673 | static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { | |
3674 | .name = "usb_tll_hs", | |
3675 | .sysc = &omap44xx_usb_tll_hs_sysc, | |
3676 | }; | |
3677 | ||
3678 | static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { | |
3679 | { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, | |
3680 | { .irq = -1 } | |
3681 | }; | |
3682 | ||
3683 | static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { | |
3684 | .name = "usb_tll_hs", | |
3685 | .class = &omap44xx_usb_tll_hs_hwmod_class, | |
3686 | .clkdm_name = "l3_init_clkdm", | |
3687 | .mpu_irqs = omap44xx_usb_tll_hs_irqs, | |
3688 | .main_clk = "usb_tll_hs_ick", | |
3689 | .prcm = { | |
3690 | .omap4 = { | |
3691 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, | |
3692 | .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, | |
3693 | .modulemode = MODULEMODE_HWCTRL, | |
5844c4ea BC |
3694 | }, |
3695 | }, | |
5844c4ea BC |
3696 | }; |
3697 | ||
3b54baad BC |
3698 | /* |
3699 | * 'wd_timer' class | |
3700 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
3701 | * overflow condition | |
3702 | */ | |
3703 | ||
3704 | static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { | |
3705 | .rev_offs = 0x0000, | |
3706 | .sysc_offs = 0x0010, | |
3707 | .syss_offs = 0x0014, | |
3708 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 3709 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
3710 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3711 | SIDLE_SMART_WKUP), | |
3b54baad | 3712 | .sysc_fields = &omap_hwmod_sysc_type1, |
9780a9cf BC |
3713 | }; |
3714 | ||
3b54baad BC |
3715 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { |
3716 | .name = "wd_timer", | |
3717 | .sysc = &omap44xx_wd_timer_sysc, | |
fe13471c | 3718 | .pre_shutdown = &omap2_wd_timer_disable, |
414e4128 | 3719 | .reset = &omap2_wd_timer_reset, |
3b54baad BC |
3720 | }; |
3721 | ||
3722 | /* wd_timer2 */ | |
3b54baad BC |
3723 | static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { |
3724 | { .irq = 80 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3725 | { .irq = -1 } |
3b54baad BC |
3726 | }; |
3727 | ||
3b54baad BC |
3728 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { |
3729 | .name = "wd_timer2", | |
3730 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 3731 | .clkdm_name = "l4_wkup_clkdm", |
3b54baad | 3732 | .mpu_irqs = omap44xx_wd_timer2_irqs, |
3b54baad | 3733 | .main_clk = "wd_timer2_fck", |
9780a9cf BC |
3734 | .prcm = { |
3735 | .omap4 = { | |
d0f0631d | 3736 | .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, |
27bb00b5 | 3737 | .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET, |
03fdefe5 | 3738 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3739 | }, |
3740 | }, | |
9780a9cf BC |
3741 | }; |
3742 | ||
3b54baad | 3743 | /* wd_timer3 */ |
3b54baad BC |
3744 | static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { |
3745 | { .irq = 36 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3746 | { .irq = -1 } |
9780a9cf BC |
3747 | }; |
3748 | ||
3b54baad BC |
3749 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { |
3750 | .name = "wd_timer3", | |
3751 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 3752 | .clkdm_name = "abe_clkdm", |
3b54baad | 3753 | .mpu_irqs = omap44xx_wd_timer3_irqs, |
3b54baad | 3754 | .main_clk = "wd_timer3_fck", |
9780a9cf BC |
3755 | .prcm = { |
3756 | .omap4 = { | |
d0f0631d | 3757 | .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, |
27bb00b5 | 3758 | .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET, |
03fdefe5 | 3759 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3760 | }, |
3761 | }, | |
9780a9cf | 3762 | }; |
531ce0d5 | 3763 | |
844a3b63 | 3764 | |
af88fa9a | 3765 | /* |
844a3b63 | 3766 | * interfaces |
af88fa9a | 3767 | */ |
af88fa9a | 3768 | |
42b9e387 PW |
3769 | static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = { |
3770 | { | |
3771 | .pa_start = 0x4a204000, | |
3772 | .pa_end = 0x4a2040ff, | |
3773 | .flags = ADDR_TYPE_RT | |
3774 | }, | |
3775 | { } | |
3776 | }; | |
3777 | ||
3778 | /* c2c -> c2c_target_fw */ | |
3779 | static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = { | |
3780 | .master = &omap44xx_c2c_hwmod, | |
3781 | .slave = &omap44xx_c2c_target_fw_hwmod, | |
3782 | .clk = "div_core_ck", | |
3783 | .addr = omap44xx_c2c_target_fw_addrs, | |
3784 | .user = OCP_USER_MPU, | |
3785 | }; | |
3786 | ||
3787 | /* l4_cfg -> c2c_target_fw */ | |
3788 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = { | |
3789 | .master = &omap44xx_l4_cfg_hwmod, | |
3790 | .slave = &omap44xx_c2c_target_fw_hwmod, | |
3791 | .clk = "l4_div_ck", | |
3792 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3793 | }; | |
3794 | ||
844a3b63 PW |
3795 | /* l3_main_1 -> dmm */ |
3796 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { | |
3797 | .master = &omap44xx_l3_main_1_hwmod, | |
3798 | .slave = &omap44xx_dmm_hwmod, | |
3799 | .clk = "l3_div_ck", | |
3800 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
3801 | }; |
3802 | ||
844a3b63 | 3803 | static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { |
af88fa9a | 3804 | { |
844a3b63 PW |
3805 | .pa_start = 0x4e000000, |
3806 | .pa_end = 0x4e0007ff, | |
af88fa9a BC |
3807 | .flags = ADDR_TYPE_RT |
3808 | }, | |
844a3b63 | 3809 | { } |
af88fa9a BC |
3810 | }; |
3811 | ||
844a3b63 PW |
3812 | /* mpu -> dmm */ |
3813 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { | |
3814 | .master = &omap44xx_mpu_hwmod, | |
3815 | .slave = &omap44xx_dmm_hwmod, | |
3816 | .clk = "l3_div_ck", | |
3817 | .addr = omap44xx_dmm_addrs, | |
3818 | .user = OCP_USER_MPU, | |
af88fa9a BC |
3819 | }; |
3820 | ||
42b9e387 PW |
3821 | /* c2c -> emif_fw */ |
3822 | static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = { | |
3823 | .master = &omap44xx_c2c_hwmod, | |
3824 | .slave = &omap44xx_emif_fw_hwmod, | |
3825 | .clk = "div_core_ck", | |
3826 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3827 | }; | |
3828 | ||
844a3b63 PW |
3829 | /* dmm -> emif_fw */ |
3830 | static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { | |
3831 | .master = &omap44xx_dmm_hwmod, | |
3832 | .slave = &omap44xx_emif_fw_hwmod, | |
3833 | .clk = "l3_div_ck", | |
3834 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3835 | }; | |
3836 | ||
3837 | static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { | |
3838 | { | |
3839 | .pa_start = 0x4a20c000, | |
3840 | .pa_end = 0x4a20c0ff, | |
3841 | .flags = ADDR_TYPE_RT | |
3842 | }, | |
3843 | { } | |
3844 | }; | |
3845 | ||
3846 | /* l4_cfg -> emif_fw */ | |
3847 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { | |
3848 | .master = &omap44xx_l4_cfg_hwmod, | |
3849 | .slave = &omap44xx_emif_fw_hwmod, | |
3850 | .clk = "l4_div_ck", | |
3851 | .addr = omap44xx_emif_fw_addrs, | |
3852 | .user = OCP_USER_MPU, | |
3853 | }; | |
3854 | ||
3855 | /* iva -> l3_instr */ | |
3856 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { | |
3857 | .master = &omap44xx_iva_hwmod, | |
3858 | .slave = &omap44xx_l3_instr_hwmod, | |
3859 | .clk = "l3_div_ck", | |
3860 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3861 | }; | |
3862 | ||
3863 | /* l3_main_3 -> l3_instr */ | |
3864 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { | |
3865 | .master = &omap44xx_l3_main_3_hwmod, | |
3866 | .slave = &omap44xx_l3_instr_hwmod, | |
3867 | .clk = "l3_div_ck", | |
3868 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3869 | }; | |
3870 | ||
9a817bc8 BC |
3871 | /* ocp_wp_noc -> l3_instr */ |
3872 | static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = { | |
3873 | .master = &omap44xx_ocp_wp_noc_hwmod, | |
3874 | .slave = &omap44xx_l3_instr_hwmod, | |
3875 | .clk = "l3_div_ck", | |
3876 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3877 | }; | |
3878 | ||
844a3b63 PW |
3879 | /* dsp -> l3_main_1 */ |
3880 | static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { | |
3881 | .master = &omap44xx_dsp_hwmod, | |
3882 | .slave = &omap44xx_l3_main_1_hwmod, | |
3883 | .clk = "l3_div_ck", | |
3884 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3885 | }; | |
3886 | ||
3887 | /* dss -> l3_main_1 */ | |
3888 | static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { | |
3889 | .master = &omap44xx_dss_hwmod, | |
3890 | .slave = &omap44xx_l3_main_1_hwmod, | |
3891 | .clk = "l3_div_ck", | |
3892 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3893 | }; | |
3894 | ||
3895 | /* l3_main_2 -> l3_main_1 */ | |
3896 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { | |
3897 | .master = &omap44xx_l3_main_2_hwmod, | |
3898 | .slave = &omap44xx_l3_main_1_hwmod, | |
3899 | .clk = "l3_div_ck", | |
3900 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3901 | }; | |
3902 | ||
3903 | /* l4_cfg -> l3_main_1 */ | |
3904 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { | |
3905 | .master = &omap44xx_l4_cfg_hwmod, | |
3906 | .slave = &omap44xx_l3_main_1_hwmod, | |
3907 | .clk = "l4_div_ck", | |
3908 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3909 | }; | |
3910 | ||
3911 | /* mmc1 -> l3_main_1 */ | |
3912 | static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { | |
3913 | .master = &omap44xx_mmc1_hwmod, | |
3914 | .slave = &omap44xx_l3_main_1_hwmod, | |
3915 | .clk = "l3_div_ck", | |
3916 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3917 | }; | |
3918 | ||
3919 | /* mmc2 -> l3_main_1 */ | |
3920 | static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { | |
3921 | .master = &omap44xx_mmc2_hwmod, | |
3922 | .slave = &omap44xx_l3_main_1_hwmod, | |
3923 | .clk = "l3_div_ck", | |
3924 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3925 | }; | |
3926 | ||
3927 | static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { | |
3928 | { | |
3929 | .pa_start = 0x44000000, | |
3930 | .pa_end = 0x44000fff, | |
3931 | .flags = ADDR_TYPE_RT | |
3932 | }, | |
3933 | { } | |
3934 | }; | |
3935 | ||
3936 | /* mpu -> l3_main_1 */ | |
3937 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { | |
3938 | .master = &omap44xx_mpu_hwmod, | |
3939 | .slave = &omap44xx_l3_main_1_hwmod, | |
3940 | .clk = "l3_div_ck", | |
3941 | .addr = omap44xx_l3_main_1_addrs, | |
3942 | .user = OCP_USER_MPU, | |
3943 | }; | |
3944 | ||
42b9e387 PW |
3945 | /* c2c_target_fw -> l3_main_2 */ |
3946 | static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = { | |
3947 | .master = &omap44xx_c2c_target_fw_hwmod, | |
3948 | .slave = &omap44xx_l3_main_2_hwmod, | |
3949 | .clk = "l3_div_ck", | |
3950 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3951 | }; | |
3952 | ||
96566043 BC |
3953 | /* debugss -> l3_main_2 */ |
3954 | static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = { | |
3955 | .master = &omap44xx_debugss_hwmod, | |
3956 | .slave = &omap44xx_l3_main_2_hwmod, | |
3957 | .clk = "dbgclk_mux_ck", | |
3958 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3959 | }; | |
3960 | ||
844a3b63 PW |
3961 | /* dma_system -> l3_main_2 */ |
3962 | static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { | |
3963 | .master = &omap44xx_dma_system_hwmod, | |
3964 | .slave = &omap44xx_l3_main_2_hwmod, | |
3965 | .clk = "l3_div_ck", | |
3966 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3967 | }; | |
3968 | ||
b050f688 ML |
3969 | /* fdif -> l3_main_2 */ |
3970 | static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = { | |
3971 | .master = &omap44xx_fdif_hwmod, | |
3972 | .slave = &omap44xx_l3_main_2_hwmod, | |
3973 | .clk = "l3_div_ck", | |
3974 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3975 | }; | |
3976 | ||
9def390e PW |
3977 | /* gpu -> l3_main_2 */ |
3978 | static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = { | |
3979 | .master = &omap44xx_gpu_hwmod, | |
3980 | .slave = &omap44xx_l3_main_2_hwmod, | |
3981 | .clk = "l3_div_ck", | |
3982 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3983 | }; | |
3984 | ||
844a3b63 PW |
3985 | /* hsi -> l3_main_2 */ |
3986 | static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { | |
3987 | .master = &omap44xx_hsi_hwmod, | |
3988 | .slave = &omap44xx_l3_main_2_hwmod, | |
3989 | .clk = "l3_div_ck", | |
3990 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3991 | }; | |
3992 | ||
3993 | /* ipu -> l3_main_2 */ | |
3994 | static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { | |
3995 | .master = &omap44xx_ipu_hwmod, | |
3996 | .slave = &omap44xx_l3_main_2_hwmod, | |
3997 | .clk = "l3_div_ck", | |
3998 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3999 | }; | |
4000 | ||
4001 | /* iss -> l3_main_2 */ | |
4002 | static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { | |
4003 | .master = &omap44xx_iss_hwmod, | |
4004 | .slave = &omap44xx_l3_main_2_hwmod, | |
4005 | .clk = "l3_div_ck", | |
4006 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4007 | }; | |
4008 | ||
4009 | /* iva -> l3_main_2 */ | |
4010 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { | |
4011 | .master = &omap44xx_iva_hwmod, | |
4012 | .slave = &omap44xx_l3_main_2_hwmod, | |
4013 | .clk = "l3_div_ck", | |
4014 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4015 | }; | |
4016 | ||
4017 | static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { | |
4018 | { | |
4019 | .pa_start = 0x44800000, | |
4020 | .pa_end = 0x44801fff, | |
4021 | .flags = ADDR_TYPE_RT | |
4022 | }, | |
4023 | { } | |
4024 | }; | |
4025 | ||
4026 | /* l3_main_1 -> l3_main_2 */ | |
4027 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { | |
4028 | .master = &omap44xx_l3_main_1_hwmod, | |
4029 | .slave = &omap44xx_l3_main_2_hwmod, | |
4030 | .clk = "l3_div_ck", | |
4031 | .addr = omap44xx_l3_main_2_addrs, | |
4032 | .user = OCP_USER_MPU, | |
4033 | }; | |
4034 | ||
4035 | /* l4_cfg -> l3_main_2 */ | |
4036 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { | |
4037 | .master = &omap44xx_l4_cfg_hwmod, | |
4038 | .slave = &omap44xx_l3_main_2_hwmod, | |
4039 | .clk = "l4_div_ck", | |
4040 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4041 | }; | |
4042 | ||
0c668875 | 4043 | /* usb_host_fs -> l3_main_2 */ |
b0a70cc8 | 4044 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = { |
0c668875 BC |
4045 | .master = &omap44xx_usb_host_fs_hwmod, |
4046 | .slave = &omap44xx_l3_main_2_hwmod, | |
4047 | .clk = "l3_div_ck", | |
4048 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4049 | }; | |
4050 | ||
844a3b63 PW |
4051 | /* usb_host_hs -> l3_main_2 */ |
4052 | static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { | |
4053 | .master = &omap44xx_usb_host_hs_hwmod, | |
4054 | .slave = &omap44xx_l3_main_2_hwmod, | |
4055 | .clk = "l3_div_ck", | |
4056 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4057 | }; | |
4058 | ||
4059 | /* usb_otg_hs -> l3_main_2 */ | |
4060 | static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { | |
4061 | .master = &omap44xx_usb_otg_hs_hwmod, | |
4062 | .slave = &omap44xx_l3_main_2_hwmod, | |
4063 | .clk = "l3_div_ck", | |
4064 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4065 | }; | |
4066 | ||
4067 | static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { | |
4068 | { | |
4069 | .pa_start = 0x45000000, | |
4070 | .pa_end = 0x45000fff, | |
4071 | .flags = ADDR_TYPE_RT | |
4072 | }, | |
4073 | { } | |
4074 | }; | |
4075 | ||
4076 | /* l3_main_1 -> l3_main_3 */ | |
4077 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { | |
4078 | .master = &omap44xx_l3_main_1_hwmod, | |
4079 | .slave = &omap44xx_l3_main_3_hwmod, | |
4080 | .clk = "l3_div_ck", | |
4081 | .addr = omap44xx_l3_main_3_addrs, | |
4082 | .user = OCP_USER_MPU, | |
4083 | }; | |
4084 | ||
4085 | /* l3_main_2 -> l3_main_3 */ | |
4086 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { | |
4087 | .master = &omap44xx_l3_main_2_hwmod, | |
4088 | .slave = &omap44xx_l3_main_3_hwmod, | |
4089 | .clk = "l3_div_ck", | |
4090 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4091 | }; | |
4092 | ||
4093 | /* l4_cfg -> l3_main_3 */ | |
4094 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { | |
4095 | .master = &omap44xx_l4_cfg_hwmod, | |
4096 | .slave = &omap44xx_l3_main_3_hwmod, | |
4097 | .clk = "l4_div_ck", | |
4098 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4099 | }; | |
4100 | ||
4101 | /* aess -> l4_abe */ | |
b0a70cc8 | 4102 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = { |
844a3b63 PW |
4103 | .master = &omap44xx_aess_hwmod, |
4104 | .slave = &omap44xx_l4_abe_hwmod, | |
4105 | .clk = "ocp_abe_iclk", | |
4106 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4107 | }; | |
4108 | ||
4109 | /* dsp -> l4_abe */ | |
4110 | static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { | |
4111 | .master = &omap44xx_dsp_hwmod, | |
4112 | .slave = &omap44xx_l4_abe_hwmod, | |
4113 | .clk = "ocp_abe_iclk", | |
4114 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4115 | }; | |
4116 | ||
4117 | /* l3_main_1 -> l4_abe */ | |
4118 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { | |
4119 | .master = &omap44xx_l3_main_1_hwmod, | |
4120 | .slave = &omap44xx_l4_abe_hwmod, | |
4121 | .clk = "l3_div_ck", | |
4122 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4123 | }; | |
4124 | ||
4125 | /* mpu -> l4_abe */ | |
4126 | static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { | |
4127 | .master = &omap44xx_mpu_hwmod, | |
4128 | .slave = &omap44xx_l4_abe_hwmod, | |
4129 | .clk = "ocp_abe_iclk", | |
4130 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4131 | }; | |
4132 | ||
4133 | /* l3_main_1 -> l4_cfg */ | |
4134 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { | |
4135 | .master = &omap44xx_l3_main_1_hwmod, | |
4136 | .slave = &omap44xx_l4_cfg_hwmod, | |
4137 | .clk = "l3_div_ck", | |
4138 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4139 | }; | |
4140 | ||
4141 | /* l3_main_2 -> l4_per */ | |
4142 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { | |
4143 | .master = &omap44xx_l3_main_2_hwmod, | |
4144 | .slave = &omap44xx_l4_per_hwmod, | |
4145 | .clk = "l3_div_ck", | |
4146 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4147 | }; | |
4148 | ||
4149 | /* l4_cfg -> l4_wkup */ | |
4150 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { | |
4151 | .master = &omap44xx_l4_cfg_hwmod, | |
4152 | .slave = &omap44xx_l4_wkup_hwmod, | |
4153 | .clk = "l4_div_ck", | |
4154 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4155 | }; | |
4156 | ||
4157 | /* mpu -> mpu_private */ | |
4158 | static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { | |
4159 | .master = &omap44xx_mpu_hwmod, | |
4160 | .slave = &omap44xx_mpu_private_hwmod, | |
4161 | .clk = "l3_div_ck", | |
4162 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4163 | }; | |
4164 | ||
9a817bc8 BC |
4165 | static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = { |
4166 | { | |
4167 | .pa_start = 0x4a102000, | |
4168 | .pa_end = 0x4a10207f, | |
4169 | .flags = ADDR_TYPE_RT | |
4170 | }, | |
4171 | { } | |
4172 | }; | |
4173 | ||
4174 | /* l4_cfg -> ocp_wp_noc */ | |
4175 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = { | |
4176 | .master = &omap44xx_l4_cfg_hwmod, | |
4177 | .slave = &omap44xx_ocp_wp_noc_hwmod, | |
4178 | .clk = "l4_div_ck", | |
4179 | .addr = omap44xx_ocp_wp_noc_addrs, | |
4180 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4181 | }; | |
4182 | ||
844a3b63 PW |
4183 | static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { |
4184 | { | |
4185 | .pa_start = 0x401f1000, | |
4186 | .pa_end = 0x401f13ff, | |
4187 | .flags = ADDR_TYPE_RT | |
4188 | }, | |
4189 | { } | |
4190 | }; | |
4191 | ||
4192 | /* l4_abe -> aess */ | |
b0a70cc8 | 4193 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = { |
844a3b63 PW |
4194 | .master = &omap44xx_l4_abe_hwmod, |
4195 | .slave = &omap44xx_aess_hwmod, | |
4196 | .clk = "ocp_abe_iclk", | |
4197 | .addr = omap44xx_aess_addrs, | |
4198 | .user = OCP_USER_MPU, | |
4199 | }; | |
4200 | ||
4201 | static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { | |
4202 | { | |
4203 | .pa_start = 0x490f1000, | |
4204 | .pa_end = 0x490f13ff, | |
4205 | .flags = ADDR_TYPE_RT | |
4206 | }, | |
4207 | { } | |
4208 | }; | |
4209 | ||
4210 | /* l4_abe -> aess (dma) */ | |
b0a70cc8 | 4211 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = { |
844a3b63 PW |
4212 | .master = &omap44xx_l4_abe_hwmod, |
4213 | .slave = &omap44xx_aess_hwmod, | |
4214 | .clk = "ocp_abe_iclk", | |
4215 | .addr = omap44xx_aess_dma_addrs, | |
4216 | .user = OCP_USER_SDMA, | |
4217 | }; | |
4218 | ||
42b9e387 PW |
4219 | /* l3_main_2 -> c2c */ |
4220 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = { | |
4221 | .master = &omap44xx_l3_main_2_hwmod, | |
4222 | .slave = &omap44xx_c2c_hwmod, | |
4223 | .clk = "l3_div_ck", | |
4224 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4225 | }; | |
4226 | ||
844a3b63 PW |
4227 | static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { |
4228 | { | |
4229 | .pa_start = 0x4a304000, | |
4230 | .pa_end = 0x4a30401f, | |
4231 | .flags = ADDR_TYPE_RT | |
4232 | }, | |
4233 | { } | |
4234 | }; | |
4235 | ||
4236 | /* l4_wkup -> counter_32k */ | |
4237 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { | |
4238 | .master = &omap44xx_l4_wkup_hwmod, | |
4239 | .slave = &omap44xx_counter_32k_hwmod, | |
4240 | .clk = "l4_wkup_clk_mux_ck", | |
4241 | .addr = omap44xx_counter_32k_addrs, | |
4242 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4243 | }; | |
4244 | ||
a0b5d813 PW |
4245 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = { |
4246 | { | |
4247 | .pa_start = 0x4a002000, | |
4248 | .pa_end = 0x4a0027ff, | |
4249 | .flags = ADDR_TYPE_RT | |
4250 | }, | |
4251 | { } | |
4252 | }; | |
4253 | ||
4254 | /* l4_cfg -> ctrl_module_core */ | |
4255 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = { | |
4256 | .master = &omap44xx_l4_cfg_hwmod, | |
4257 | .slave = &omap44xx_ctrl_module_core_hwmod, | |
4258 | .clk = "l4_div_ck", | |
4259 | .addr = omap44xx_ctrl_module_core_addrs, | |
4260 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4261 | }; | |
4262 | ||
4263 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = { | |
4264 | { | |
4265 | .pa_start = 0x4a100000, | |
4266 | .pa_end = 0x4a1007ff, | |
4267 | .flags = ADDR_TYPE_RT | |
4268 | }, | |
4269 | { } | |
4270 | }; | |
4271 | ||
4272 | /* l4_cfg -> ctrl_module_pad_core */ | |
4273 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = { | |
4274 | .master = &omap44xx_l4_cfg_hwmod, | |
4275 | .slave = &omap44xx_ctrl_module_pad_core_hwmod, | |
4276 | .clk = "l4_div_ck", | |
4277 | .addr = omap44xx_ctrl_module_pad_core_addrs, | |
4278 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4279 | }; | |
4280 | ||
4281 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = { | |
4282 | { | |
4283 | .pa_start = 0x4a30c000, | |
4284 | .pa_end = 0x4a30c7ff, | |
4285 | .flags = ADDR_TYPE_RT | |
4286 | }, | |
4287 | { } | |
4288 | }; | |
4289 | ||
4290 | /* l4_wkup -> ctrl_module_wkup */ | |
4291 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = { | |
4292 | .master = &omap44xx_l4_wkup_hwmod, | |
4293 | .slave = &omap44xx_ctrl_module_wkup_hwmod, | |
4294 | .clk = "l4_wkup_clk_mux_ck", | |
4295 | .addr = omap44xx_ctrl_module_wkup_addrs, | |
4296 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4297 | }; | |
4298 | ||
4299 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = { | |
4300 | { | |
4301 | .pa_start = 0x4a31e000, | |
4302 | .pa_end = 0x4a31e7ff, | |
4303 | .flags = ADDR_TYPE_RT | |
4304 | }, | |
4305 | { } | |
4306 | }; | |
4307 | ||
4308 | /* l4_wkup -> ctrl_module_pad_wkup */ | |
4309 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = { | |
4310 | .master = &omap44xx_l4_wkup_hwmod, | |
4311 | .slave = &omap44xx_ctrl_module_pad_wkup_hwmod, | |
4312 | .clk = "l4_wkup_clk_mux_ck", | |
4313 | .addr = omap44xx_ctrl_module_pad_wkup_addrs, | |
4314 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4315 | }; | |
4316 | ||
96566043 BC |
4317 | static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = { |
4318 | { | |
4319 | .pa_start = 0x54160000, | |
4320 | .pa_end = 0x54167fff, | |
4321 | .flags = ADDR_TYPE_RT | |
4322 | }, | |
4323 | { } | |
4324 | }; | |
4325 | ||
4326 | /* l3_instr -> debugss */ | |
4327 | static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = { | |
4328 | .master = &omap44xx_l3_instr_hwmod, | |
4329 | .slave = &omap44xx_debugss_hwmod, | |
4330 | .clk = "l3_div_ck", | |
4331 | .addr = omap44xx_debugss_addrs, | |
4332 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4333 | }; | |
4334 | ||
844a3b63 PW |
4335 | static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { |
4336 | { | |
4337 | .pa_start = 0x4a056000, | |
4338 | .pa_end = 0x4a056fff, | |
4339 | .flags = ADDR_TYPE_RT | |
4340 | }, | |
4341 | { } | |
4342 | }; | |
4343 | ||
4344 | /* l4_cfg -> dma_system */ | |
4345 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { | |
4346 | .master = &omap44xx_l4_cfg_hwmod, | |
4347 | .slave = &omap44xx_dma_system_hwmod, | |
4348 | .clk = "l4_div_ck", | |
4349 | .addr = omap44xx_dma_system_addrs, | |
4350 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4351 | }; | |
4352 | ||
4353 | static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { | |
4354 | { | |
4355 | .name = "mpu", | |
4356 | .pa_start = 0x4012e000, | |
4357 | .pa_end = 0x4012e07f, | |
4358 | .flags = ADDR_TYPE_RT | |
4359 | }, | |
4360 | { } | |
4361 | }; | |
4362 | ||
4363 | /* l4_abe -> dmic */ | |
4364 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { | |
4365 | .master = &omap44xx_l4_abe_hwmod, | |
4366 | .slave = &omap44xx_dmic_hwmod, | |
4367 | .clk = "ocp_abe_iclk", | |
4368 | .addr = omap44xx_dmic_addrs, | |
4369 | .user = OCP_USER_MPU, | |
4370 | }; | |
4371 | ||
4372 | static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { | |
4373 | { | |
4374 | .name = "dma", | |
4375 | .pa_start = 0x4902e000, | |
4376 | .pa_end = 0x4902e07f, | |
4377 | .flags = ADDR_TYPE_RT | |
4378 | }, | |
4379 | { } | |
4380 | }; | |
4381 | ||
4382 | /* l4_abe -> dmic (dma) */ | |
4383 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { | |
4384 | .master = &omap44xx_l4_abe_hwmod, | |
4385 | .slave = &omap44xx_dmic_hwmod, | |
4386 | .clk = "ocp_abe_iclk", | |
4387 | .addr = omap44xx_dmic_dma_addrs, | |
4388 | .user = OCP_USER_SDMA, | |
4389 | }; | |
4390 | ||
4391 | /* dsp -> iva */ | |
4392 | static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { | |
4393 | .master = &omap44xx_dsp_hwmod, | |
4394 | .slave = &omap44xx_iva_hwmod, | |
4395 | .clk = "dpll_iva_m5x2_ck", | |
4396 | .user = OCP_USER_DSP, | |
4397 | }; | |
4398 | ||
42b9e387 | 4399 | /* dsp -> sl2if */ |
b360124e | 4400 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = { |
42b9e387 PW |
4401 | .master = &omap44xx_dsp_hwmod, |
4402 | .slave = &omap44xx_sl2if_hwmod, | |
4403 | .clk = "dpll_iva_m5x2_ck", | |
4404 | .user = OCP_USER_DSP, | |
4405 | }; | |
4406 | ||
844a3b63 PW |
4407 | /* l4_cfg -> dsp */ |
4408 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { | |
4409 | .master = &omap44xx_l4_cfg_hwmod, | |
4410 | .slave = &omap44xx_dsp_hwmod, | |
4411 | .clk = "l4_div_ck", | |
4412 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4413 | }; | |
4414 | ||
4415 | static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { | |
4416 | { | |
4417 | .pa_start = 0x58000000, | |
4418 | .pa_end = 0x5800007f, | |
4419 | .flags = ADDR_TYPE_RT | |
4420 | }, | |
4421 | { } | |
4422 | }; | |
4423 | ||
4424 | /* l3_main_2 -> dss */ | |
4425 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { | |
4426 | .master = &omap44xx_l3_main_2_hwmod, | |
4427 | .slave = &omap44xx_dss_hwmod, | |
4428 | .clk = "dss_fck", | |
4429 | .addr = omap44xx_dss_dma_addrs, | |
4430 | .user = OCP_USER_SDMA, | |
4431 | }; | |
4432 | ||
4433 | static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { | |
4434 | { | |
4435 | .pa_start = 0x48040000, | |
4436 | .pa_end = 0x4804007f, | |
4437 | .flags = ADDR_TYPE_RT | |
4438 | }, | |
4439 | { } | |
4440 | }; | |
4441 | ||
4442 | /* l4_per -> dss */ | |
4443 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { | |
4444 | .master = &omap44xx_l4_per_hwmod, | |
4445 | .slave = &omap44xx_dss_hwmod, | |
4446 | .clk = "l4_div_ck", | |
4447 | .addr = omap44xx_dss_addrs, | |
4448 | .user = OCP_USER_MPU, | |
4449 | }; | |
4450 | ||
4451 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { | |
4452 | { | |
4453 | .pa_start = 0x58001000, | |
4454 | .pa_end = 0x58001fff, | |
4455 | .flags = ADDR_TYPE_RT | |
4456 | }, | |
4457 | { } | |
4458 | }; | |
4459 | ||
4460 | /* l3_main_2 -> dss_dispc */ | |
4461 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { | |
4462 | .master = &omap44xx_l3_main_2_hwmod, | |
4463 | .slave = &omap44xx_dss_dispc_hwmod, | |
4464 | .clk = "dss_fck", | |
4465 | .addr = omap44xx_dss_dispc_dma_addrs, | |
4466 | .user = OCP_USER_SDMA, | |
4467 | }; | |
4468 | ||
4469 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { | |
4470 | { | |
4471 | .pa_start = 0x48041000, | |
4472 | .pa_end = 0x48041fff, | |
4473 | .flags = ADDR_TYPE_RT | |
4474 | }, | |
4475 | { } | |
4476 | }; | |
4477 | ||
4478 | /* l4_per -> dss_dispc */ | |
4479 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { | |
4480 | .master = &omap44xx_l4_per_hwmod, | |
4481 | .slave = &omap44xx_dss_dispc_hwmod, | |
4482 | .clk = "l4_div_ck", | |
4483 | .addr = omap44xx_dss_dispc_addrs, | |
4484 | .user = OCP_USER_MPU, | |
4485 | }; | |
4486 | ||
4487 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { | |
4488 | { | |
4489 | .pa_start = 0x58004000, | |
4490 | .pa_end = 0x580041ff, | |
4491 | .flags = ADDR_TYPE_RT | |
4492 | }, | |
4493 | { } | |
4494 | }; | |
4495 | ||
4496 | /* l3_main_2 -> dss_dsi1 */ | |
4497 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { | |
4498 | .master = &omap44xx_l3_main_2_hwmod, | |
4499 | .slave = &omap44xx_dss_dsi1_hwmod, | |
4500 | .clk = "dss_fck", | |
4501 | .addr = omap44xx_dss_dsi1_dma_addrs, | |
4502 | .user = OCP_USER_SDMA, | |
4503 | }; | |
4504 | ||
4505 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { | |
4506 | { | |
4507 | .pa_start = 0x48044000, | |
4508 | .pa_end = 0x480441ff, | |
4509 | .flags = ADDR_TYPE_RT | |
4510 | }, | |
4511 | { } | |
4512 | }; | |
4513 | ||
4514 | /* l4_per -> dss_dsi1 */ | |
4515 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { | |
4516 | .master = &omap44xx_l4_per_hwmod, | |
4517 | .slave = &omap44xx_dss_dsi1_hwmod, | |
4518 | .clk = "l4_div_ck", | |
4519 | .addr = omap44xx_dss_dsi1_addrs, | |
4520 | .user = OCP_USER_MPU, | |
4521 | }; | |
4522 | ||
4523 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { | |
4524 | { | |
4525 | .pa_start = 0x58005000, | |
4526 | .pa_end = 0x580051ff, | |
4527 | .flags = ADDR_TYPE_RT | |
4528 | }, | |
4529 | { } | |
4530 | }; | |
4531 | ||
4532 | /* l3_main_2 -> dss_dsi2 */ | |
4533 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { | |
4534 | .master = &omap44xx_l3_main_2_hwmod, | |
4535 | .slave = &omap44xx_dss_dsi2_hwmod, | |
4536 | .clk = "dss_fck", | |
4537 | .addr = omap44xx_dss_dsi2_dma_addrs, | |
4538 | .user = OCP_USER_SDMA, | |
4539 | }; | |
4540 | ||
4541 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { | |
4542 | { | |
4543 | .pa_start = 0x48045000, | |
4544 | .pa_end = 0x480451ff, | |
4545 | .flags = ADDR_TYPE_RT | |
4546 | }, | |
4547 | { } | |
4548 | }; | |
4549 | ||
4550 | /* l4_per -> dss_dsi2 */ | |
4551 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { | |
4552 | .master = &omap44xx_l4_per_hwmod, | |
4553 | .slave = &omap44xx_dss_dsi2_hwmod, | |
4554 | .clk = "l4_div_ck", | |
4555 | .addr = omap44xx_dss_dsi2_addrs, | |
4556 | .user = OCP_USER_MPU, | |
4557 | }; | |
4558 | ||
4559 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { | |
4560 | { | |
4561 | .pa_start = 0x58006000, | |
4562 | .pa_end = 0x58006fff, | |
4563 | .flags = ADDR_TYPE_RT | |
4564 | }, | |
4565 | { } | |
4566 | }; | |
4567 | ||
4568 | /* l3_main_2 -> dss_hdmi */ | |
4569 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { | |
4570 | .master = &omap44xx_l3_main_2_hwmod, | |
4571 | .slave = &omap44xx_dss_hdmi_hwmod, | |
4572 | .clk = "dss_fck", | |
4573 | .addr = omap44xx_dss_hdmi_dma_addrs, | |
4574 | .user = OCP_USER_SDMA, | |
4575 | }; | |
4576 | ||
4577 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { | |
4578 | { | |
4579 | .pa_start = 0x48046000, | |
4580 | .pa_end = 0x48046fff, | |
4581 | .flags = ADDR_TYPE_RT | |
4582 | }, | |
4583 | { } | |
4584 | }; | |
4585 | ||
4586 | /* l4_per -> dss_hdmi */ | |
4587 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { | |
4588 | .master = &omap44xx_l4_per_hwmod, | |
4589 | .slave = &omap44xx_dss_hdmi_hwmod, | |
4590 | .clk = "l4_div_ck", | |
4591 | .addr = omap44xx_dss_hdmi_addrs, | |
4592 | .user = OCP_USER_MPU, | |
4593 | }; | |
4594 | ||
4595 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { | |
4596 | { | |
4597 | .pa_start = 0x58002000, | |
4598 | .pa_end = 0x580020ff, | |
4599 | .flags = ADDR_TYPE_RT | |
4600 | }, | |
4601 | { } | |
4602 | }; | |
4603 | ||
4604 | /* l3_main_2 -> dss_rfbi */ | |
4605 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { | |
4606 | .master = &omap44xx_l3_main_2_hwmod, | |
4607 | .slave = &omap44xx_dss_rfbi_hwmod, | |
4608 | .clk = "dss_fck", | |
4609 | .addr = omap44xx_dss_rfbi_dma_addrs, | |
4610 | .user = OCP_USER_SDMA, | |
4611 | }; | |
4612 | ||
4613 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { | |
4614 | { | |
4615 | .pa_start = 0x48042000, | |
4616 | .pa_end = 0x480420ff, | |
4617 | .flags = ADDR_TYPE_RT | |
4618 | }, | |
4619 | { } | |
4620 | }; | |
4621 | ||
4622 | /* l4_per -> dss_rfbi */ | |
4623 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { | |
4624 | .master = &omap44xx_l4_per_hwmod, | |
4625 | .slave = &omap44xx_dss_rfbi_hwmod, | |
4626 | .clk = "l4_div_ck", | |
4627 | .addr = omap44xx_dss_rfbi_addrs, | |
4628 | .user = OCP_USER_MPU, | |
4629 | }; | |
4630 | ||
4631 | static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { | |
4632 | { | |
4633 | .pa_start = 0x58003000, | |
4634 | .pa_end = 0x580030ff, | |
4635 | .flags = ADDR_TYPE_RT | |
4636 | }, | |
4637 | { } | |
4638 | }; | |
4639 | ||
4640 | /* l3_main_2 -> dss_venc */ | |
4641 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { | |
4642 | .master = &omap44xx_l3_main_2_hwmod, | |
4643 | .slave = &omap44xx_dss_venc_hwmod, | |
4644 | .clk = "dss_fck", | |
4645 | .addr = omap44xx_dss_venc_dma_addrs, | |
4646 | .user = OCP_USER_SDMA, | |
4647 | }; | |
4648 | ||
4649 | static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { | |
4650 | { | |
4651 | .pa_start = 0x48043000, | |
4652 | .pa_end = 0x480430ff, | |
4653 | .flags = ADDR_TYPE_RT | |
4654 | }, | |
4655 | { } | |
4656 | }; | |
4657 | ||
4658 | /* l4_per -> dss_venc */ | |
4659 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { | |
4660 | .master = &omap44xx_l4_per_hwmod, | |
4661 | .slave = &omap44xx_dss_venc_hwmod, | |
4662 | .clk = "l4_div_ck", | |
4663 | .addr = omap44xx_dss_venc_addrs, | |
4664 | .user = OCP_USER_MPU, | |
4665 | }; | |
4666 | ||
42b9e387 PW |
4667 | static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = { |
4668 | { | |
4669 | .pa_start = 0x48078000, | |
4670 | .pa_end = 0x48078fff, | |
4671 | .flags = ADDR_TYPE_RT | |
4672 | }, | |
4673 | { } | |
4674 | }; | |
4675 | ||
4676 | /* l4_per -> elm */ | |
4677 | static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = { | |
4678 | .master = &omap44xx_l4_per_hwmod, | |
4679 | .slave = &omap44xx_elm_hwmod, | |
4680 | .clk = "l4_div_ck", | |
4681 | .addr = omap44xx_elm_addrs, | |
4682 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4683 | }; | |
4684 | ||
bf30f950 PW |
4685 | static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = { |
4686 | { | |
4687 | .pa_start = 0x4c000000, | |
4688 | .pa_end = 0x4c0000ff, | |
4689 | .flags = ADDR_TYPE_RT | |
4690 | }, | |
4691 | { } | |
4692 | }; | |
4693 | ||
4694 | /* emif_fw -> emif1 */ | |
4695 | static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = { | |
4696 | .master = &omap44xx_emif_fw_hwmod, | |
4697 | .slave = &omap44xx_emif1_hwmod, | |
4698 | .clk = "l3_div_ck", | |
4699 | .addr = omap44xx_emif1_addrs, | |
4700 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4701 | }; | |
4702 | ||
4703 | static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = { | |
4704 | { | |
4705 | .pa_start = 0x4d000000, | |
4706 | .pa_end = 0x4d0000ff, | |
4707 | .flags = ADDR_TYPE_RT | |
4708 | }, | |
4709 | { } | |
4710 | }; | |
4711 | ||
4712 | /* emif_fw -> emif2 */ | |
4713 | static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = { | |
4714 | .master = &omap44xx_emif_fw_hwmod, | |
4715 | .slave = &omap44xx_emif2_hwmod, | |
4716 | .clk = "l3_div_ck", | |
4717 | .addr = omap44xx_emif2_addrs, | |
4718 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4719 | }; | |
4720 | ||
b050f688 ML |
4721 | static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = { |
4722 | { | |
4723 | .pa_start = 0x4a10a000, | |
4724 | .pa_end = 0x4a10a1ff, | |
4725 | .flags = ADDR_TYPE_RT | |
4726 | }, | |
4727 | { } | |
4728 | }; | |
4729 | ||
4730 | /* l4_cfg -> fdif */ | |
4731 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = { | |
4732 | .master = &omap44xx_l4_cfg_hwmod, | |
4733 | .slave = &omap44xx_fdif_hwmod, | |
4734 | .clk = "l4_div_ck", | |
4735 | .addr = omap44xx_fdif_addrs, | |
4736 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4737 | }; | |
4738 | ||
844a3b63 PW |
4739 | static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { |
4740 | { | |
4741 | .pa_start = 0x4a310000, | |
4742 | .pa_end = 0x4a3101ff, | |
4743 | .flags = ADDR_TYPE_RT | |
4744 | }, | |
4745 | { } | |
4746 | }; | |
4747 | ||
4748 | /* l4_wkup -> gpio1 */ | |
4749 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { | |
4750 | .master = &omap44xx_l4_wkup_hwmod, | |
4751 | .slave = &omap44xx_gpio1_hwmod, | |
4752 | .clk = "l4_wkup_clk_mux_ck", | |
4753 | .addr = omap44xx_gpio1_addrs, | |
4754 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4755 | }; | |
4756 | ||
4757 | static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { | |
4758 | { | |
4759 | .pa_start = 0x48055000, | |
4760 | .pa_end = 0x480551ff, | |
4761 | .flags = ADDR_TYPE_RT | |
4762 | }, | |
4763 | { } | |
4764 | }; | |
4765 | ||
4766 | /* l4_per -> gpio2 */ | |
4767 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { | |
4768 | .master = &omap44xx_l4_per_hwmod, | |
4769 | .slave = &omap44xx_gpio2_hwmod, | |
4770 | .clk = "l4_div_ck", | |
4771 | .addr = omap44xx_gpio2_addrs, | |
4772 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4773 | }; | |
4774 | ||
4775 | static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { | |
4776 | { | |
4777 | .pa_start = 0x48057000, | |
4778 | .pa_end = 0x480571ff, | |
4779 | .flags = ADDR_TYPE_RT | |
4780 | }, | |
4781 | { } | |
4782 | }; | |
4783 | ||
4784 | /* l4_per -> gpio3 */ | |
4785 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { | |
4786 | .master = &omap44xx_l4_per_hwmod, | |
4787 | .slave = &omap44xx_gpio3_hwmod, | |
4788 | .clk = "l4_div_ck", | |
4789 | .addr = omap44xx_gpio3_addrs, | |
4790 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4791 | }; | |
4792 | ||
4793 | static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { | |
4794 | { | |
4795 | .pa_start = 0x48059000, | |
4796 | .pa_end = 0x480591ff, | |
4797 | .flags = ADDR_TYPE_RT | |
4798 | }, | |
4799 | { } | |
4800 | }; | |
4801 | ||
4802 | /* l4_per -> gpio4 */ | |
4803 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { | |
4804 | .master = &omap44xx_l4_per_hwmod, | |
4805 | .slave = &omap44xx_gpio4_hwmod, | |
4806 | .clk = "l4_div_ck", | |
4807 | .addr = omap44xx_gpio4_addrs, | |
4808 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4809 | }; | |
4810 | ||
4811 | static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { | |
4812 | { | |
4813 | .pa_start = 0x4805b000, | |
4814 | .pa_end = 0x4805b1ff, | |
4815 | .flags = ADDR_TYPE_RT | |
4816 | }, | |
4817 | { } | |
4818 | }; | |
4819 | ||
4820 | /* l4_per -> gpio5 */ | |
4821 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { | |
4822 | .master = &omap44xx_l4_per_hwmod, | |
4823 | .slave = &omap44xx_gpio5_hwmod, | |
4824 | .clk = "l4_div_ck", | |
4825 | .addr = omap44xx_gpio5_addrs, | |
4826 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4827 | }; | |
4828 | ||
4829 | static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { | |
4830 | { | |
4831 | .pa_start = 0x4805d000, | |
4832 | .pa_end = 0x4805d1ff, | |
4833 | .flags = ADDR_TYPE_RT | |
4834 | }, | |
4835 | { } | |
4836 | }; | |
4837 | ||
4838 | /* l4_per -> gpio6 */ | |
4839 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { | |
4840 | .master = &omap44xx_l4_per_hwmod, | |
4841 | .slave = &omap44xx_gpio6_hwmod, | |
4842 | .clk = "l4_div_ck", | |
4843 | .addr = omap44xx_gpio6_addrs, | |
4844 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4845 | }; | |
4846 | ||
eb42b5d3 BC |
4847 | static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = { |
4848 | { | |
4849 | .pa_start = 0x50000000, | |
4850 | .pa_end = 0x500003ff, | |
4851 | .flags = ADDR_TYPE_RT | |
4852 | }, | |
4853 | { } | |
4854 | }; | |
4855 | ||
4856 | /* l3_main_2 -> gpmc */ | |
4857 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { | |
4858 | .master = &omap44xx_l3_main_2_hwmod, | |
4859 | .slave = &omap44xx_gpmc_hwmod, | |
4860 | .clk = "l3_div_ck", | |
4861 | .addr = omap44xx_gpmc_addrs, | |
4862 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4863 | }; | |
4864 | ||
9def390e PW |
4865 | static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = { |
4866 | { | |
4867 | .pa_start = 0x56000000, | |
4868 | .pa_end = 0x5600ffff, | |
4869 | .flags = ADDR_TYPE_RT | |
4870 | }, | |
4871 | { } | |
4872 | }; | |
4873 | ||
4874 | /* l3_main_2 -> gpu */ | |
4875 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = { | |
4876 | .master = &omap44xx_l3_main_2_hwmod, | |
4877 | .slave = &omap44xx_gpu_hwmod, | |
4878 | .clk = "l3_div_ck", | |
4879 | .addr = omap44xx_gpu_addrs, | |
4880 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4881 | }; | |
4882 | ||
a091c08e PW |
4883 | static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = { |
4884 | { | |
4885 | .pa_start = 0x480b2000, | |
4886 | .pa_end = 0x480b201f, | |
4887 | .flags = ADDR_TYPE_RT | |
4888 | }, | |
4889 | { } | |
4890 | }; | |
4891 | ||
4892 | /* l4_per -> hdq1w */ | |
4893 | static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = { | |
4894 | .master = &omap44xx_l4_per_hwmod, | |
4895 | .slave = &omap44xx_hdq1w_hwmod, | |
4896 | .clk = "l4_div_ck", | |
4897 | .addr = omap44xx_hdq1w_addrs, | |
4898 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4899 | }; | |
4900 | ||
844a3b63 PW |
4901 | static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { |
4902 | { | |
4903 | .pa_start = 0x4a058000, | |
4904 | .pa_end = 0x4a05bfff, | |
4905 | .flags = ADDR_TYPE_RT | |
4906 | }, | |
4907 | { } | |
4908 | }; | |
4909 | ||
4910 | /* l4_cfg -> hsi */ | |
4911 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { | |
4912 | .master = &omap44xx_l4_cfg_hwmod, | |
4913 | .slave = &omap44xx_hsi_hwmod, | |
4914 | .clk = "l4_div_ck", | |
4915 | .addr = omap44xx_hsi_addrs, | |
4916 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4917 | }; | |
4918 | ||
4919 | static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { | |
4920 | { | |
4921 | .pa_start = 0x48070000, | |
4922 | .pa_end = 0x480700ff, | |
4923 | .flags = ADDR_TYPE_RT | |
4924 | }, | |
4925 | { } | |
4926 | }; | |
4927 | ||
4928 | /* l4_per -> i2c1 */ | |
4929 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { | |
4930 | .master = &omap44xx_l4_per_hwmod, | |
4931 | .slave = &omap44xx_i2c1_hwmod, | |
4932 | .clk = "l4_div_ck", | |
4933 | .addr = omap44xx_i2c1_addrs, | |
4934 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4935 | }; | |
4936 | ||
4937 | static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { | |
4938 | { | |
4939 | .pa_start = 0x48072000, | |
4940 | .pa_end = 0x480720ff, | |
4941 | .flags = ADDR_TYPE_RT | |
4942 | }, | |
4943 | { } | |
4944 | }; | |
4945 | ||
4946 | /* l4_per -> i2c2 */ | |
4947 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { | |
4948 | .master = &omap44xx_l4_per_hwmod, | |
4949 | .slave = &omap44xx_i2c2_hwmod, | |
4950 | .clk = "l4_div_ck", | |
4951 | .addr = omap44xx_i2c2_addrs, | |
4952 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4953 | }; | |
4954 | ||
4955 | static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { | |
4956 | { | |
4957 | .pa_start = 0x48060000, | |
4958 | .pa_end = 0x480600ff, | |
4959 | .flags = ADDR_TYPE_RT | |
4960 | }, | |
4961 | { } | |
4962 | }; | |
4963 | ||
4964 | /* l4_per -> i2c3 */ | |
4965 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { | |
4966 | .master = &omap44xx_l4_per_hwmod, | |
4967 | .slave = &omap44xx_i2c3_hwmod, | |
4968 | .clk = "l4_div_ck", | |
4969 | .addr = omap44xx_i2c3_addrs, | |
4970 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4971 | }; | |
4972 | ||
4973 | static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { | |
4974 | { | |
4975 | .pa_start = 0x48350000, | |
4976 | .pa_end = 0x483500ff, | |
4977 | .flags = ADDR_TYPE_RT | |
4978 | }, | |
4979 | { } | |
4980 | }; | |
4981 | ||
4982 | /* l4_per -> i2c4 */ | |
4983 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { | |
4984 | .master = &omap44xx_l4_per_hwmod, | |
4985 | .slave = &omap44xx_i2c4_hwmod, | |
4986 | .clk = "l4_div_ck", | |
4987 | .addr = omap44xx_i2c4_addrs, | |
4988 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4989 | }; | |
4990 | ||
4991 | /* l3_main_2 -> ipu */ | |
4992 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { | |
4993 | .master = &omap44xx_l3_main_2_hwmod, | |
4994 | .slave = &omap44xx_ipu_hwmod, | |
4995 | .clk = "l3_div_ck", | |
4996 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4997 | }; | |
4998 | ||
4999 | static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { | |
5000 | { | |
5001 | .pa_start = 0x52000000, | |
5002 | .pa_end = 0x520000ff, | |
5003 | .flags = ADDR_TYPE_RT | |
5004 | }, | |
5005 | { } | |
5006 | }; | |
5007 | ||
5008 | /* l3_main_2 -> iss */ | |
5009 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { | |
5010 | .master = &omap44xx_l3_main_2_hwmod, | |
5011 | .slave = &omap44xx_iss_hwmod, | |
5012 | .clk = "l3_div_ck", | |
5013 | .addr = omap44xx_iss_addrs, | |
5014 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5015 | }; | |
5016 | ||
42b9e387 | 5017 | /* iva -> sl2if */ |
b360124e | 5018 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = { |
42b9e387 PW |
5019 | .master = &omap44xx_iva_hwmod, |
5020 | .slave = &omap44xx_sl2if_hwmod, | |
5021 | .clk = "dpll_iva_m5x2_ck", | |
5022 | .user = OCP_USER_IVA, | |
5023 | }; | |
5024 | ||
844a3b63 PW |
5025 | static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { |
5026 | { | |
5027 | .pa_start = 0x5a000000, | |
5028 | .pa_end = 0x5a07ffff, | |
5029 | .flags = ADDR_TYPE_RT | |
5030 | }, | |
5031 | { } | |
5032 | }; | |
5033 | ||
5034 | /* l3_main_2 -> iva */ | |
5035 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { | |
5036 | .master = &omap44xx_l3_main_2_hwmod, | |
5037 | .slave = &omap44xx_iva_hwmod, | |
5038 | .clk = "l3_div_ck", | |
5039 | .addr = omap44xx_iva_addrs, | |
5040 | .user = OCP_USER_MPU, | |
5041 | }; | |
5042 | ||
5043 | static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { | |
5044 | { | |
5045 | .pa_start = 0x4a31c000, | |
5046 | .pa_end = 0x4a31c07f, | |
5047 | .flags = ADDR_TYPE_RT | |
5048 | }, | |
5049 | { } | |
5050 | }; | |
5051 | ||
5052 | /* l4_wkup -> kbd */ | |
5053 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { | |
5054 | .master = &omap44xx_l4_wkup_hwmod, | |
5055 | .slave = &omap44xx_kbd_hwmod, | |
5056 | .clk = "l4_wkup_clk_mux_ck", | |
5057 | .addr = omap44xx_kbd_addrs, | |
5058 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5059 | }; | |
5060 | ||
5061 | static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { | |
5062 | { | |
5063 | .pa_start = 0x4a0f4000, | |
5064 | .pa_end = 0x4a0f41ff, | |
5065 | .flags = ADDR_TYPE_RT | |
5066 | }, | |
5067 | { } | |
5068 | }; | |
5069 | ||
5070 | /* l4_cfg -> mailbox */ | |
5071 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { | |
5072 | .master = &omap44xx_l4_cfg_hwmod, | |
5073 | .slave = &omap44xx_mailbox_hwmod, | |
5074 | .clk = "l4_div_ck", | |
5075 | .addr = omap44xx_mailbox_addrs, | |
5076 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5077 | }; | |
5078 | ||
896d4e98 BC |
5079 | static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = { |
5080 | { | |
5081 | .pa_start = 0x40128000, | |
5082 | .pa_end = 0x401283ff, | |
5083 | .flags = ADDR_TYPE_RT | |
5084 | }, | |
5085 | { } | |
5086 | }; | |
5087 | ||
5088 | /* l4_abe -> mcasp */ | |
5089 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = { | |
5090 | .master = &omap44xx_l4_abe_hwmod, | |
5091 | .slave = &omap44xx_mcasp_hwmod, | |
5092 | .clk = "ocp_abe_iclk", | |
5093 | .addr = omap44xx_mcasp_addrs, | |
5094 | .user = OCP_USER_MPU, | |
5095 | }; | |
5096 | ||
5097 | static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = { | |
5098 | { | |
5099 | .pa_start = 0x49028000, | |
5100 | .pa_end = 0x490283ff, | |
5101 | .flags = ADDR_TYPE_RT | |
5102 | }, | |
5103 | { } | |
5104 | }; | |
5105 | ||
5106 | /* l4_abe -> mcasp (dma) */ | |
5107 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = { | |
5108 | .master = &omap44xx_l4_abe_hwmod, | |
5109 | .slave = &omap44xx_mcasp_hwmod, | |
5110 | .clk = "ocp_abe_iclk", | |
5111 | .addr = omap44xx_mcasp_dma_addrs, | |
5112 | .user = OCP_USER_SDMA, | |
5113 | }; | |
5114 | ||
844a3b63 PW |
5115 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { |
5116 | { | |
5117 | .name = "mpu", | |
5118 | .pa_start = 0x40122000, | |
5119 | .pa_end = 0x401220ff, | |
5120 | .flags = ADDR_TYPE_RT | |
5121 | }, | |
5122 | { } | |
5123 | }; | |
5124 | ||
5125 | /* l4_abe -> mcbsp1 */ | |
5126 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { | |
5127 | .master = &omap44xx_l4_abe_hwmod, | |
5128 | .slave = &omap44xx_mcbsp1_hwmod, | |
5129 | .clk = "ocp_abe_iclk", | |
5130 | .addr = omap44xx_mcbsp1_addrs, | |
5131 | .user = OCP_USER_MPU, | |
5132 | }; | |
5133 | ||
5134 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { | |
5135 | { | |
5136 | .name = "dma", | |
5137 | .pa_start = 0x49022000, | |
5138 | .pa_end = 0x490220ff, | |
5139 | .flags = ADDR_TYPE_RT | |
5140 | }, | |
5141 | { } | |
5142 | }; | |
5143 | ||
5144 | /* l4_abe -> mcbsp1 (dma) */ | |
5145 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { | |
5146 | .master = &omap44xx_l4_abe_hwmod, | |
5147 | .slave = &omap44xx_mcbsp1_hwmod, | |
5148 | .clk = "ocp_abe_iclk", | |
5149 | .addr = omap44xx_mcbsp1_dma_addrs, | |
5150 | .user = OCP_USER_SDMA, | |
5151 | }; | |
5152 | ||
5153 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { | |
5154 | { | |
5155 | .name = "mpu", | |
5156 | .pa_start = 0x40124000, | |
5157 | .pa_end = 0x401240ff, | |
5158 | .flags = ADDR_TYPE_RT | |
5159 | }, | |
5160 | { } | |
5161 | }; | |
5162 | ||
5163 | /* l4_abe -> mcbsp2 */ | |
5164 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { | |
5165 | .master = &omap44xx_l4_abe_hwmod, | |
5166 | .slave = &omap44xx_mcbsp2_hwmod, | |
5167 | .clk = "ocp_abe_iclk", | |
5168 | .addr = omap44xx_mcbsp2_addrs, | |
5169 | .user = OCP_USER_MPU, | |
5170 | }; | |
5171 | ||
5172 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { | |
5173 | { | |
5174 | .name = "dma", | |
5175 | .pa_start = 0x49024000, | |
5176 | .pa_end = 0x490240ff, | |
5177 | .flags = ADDR_TYPE_RT | |
5178 | }, | |
5179 | { } | |
5180 | }; | |
5181 | ||
5182 | /* l4_abe -> mcbsp2 (dma) */ | |
5183 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { | |
5184 | .master = &omap44xx_l4_abe_hwmod, | |
5185 | .slave = &omap44xx_mcbsp2_hwmod, | |
5186 | .clk = "ocp_abe_iclk", | |
5187 | .addr = omap44xx_mcbsp2_dma_addrs, | |
5188 | .user = OCP_USER_SDMA, | |
5189 | }; | |
5190 | ||
5191 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { | |
5192 | { | |
5193 | .name = "mpu", | |
5194 | .pa_start = 0x40126000, | |
5195 | .pa_end = 0x401260ff, | |
5196 | .flags = ADDR_TYPE_RT | |
5197 | }, | |
5198 | { } | |
5199 | }; | |
5200 | ||
5201 | /* l4_abe -> mcbsp3 */ | |
5202 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { | |
5203 | .master = &omap44xx_l4_abe_hwmod, | |
5204 | .slave = &omap44xx_mcbsp3_hwmod, | |
5205 | .clk = "ocp_abe_iclk", | |
5206 | .addr = omap44xx_mcbsp3_addrs, | |
5207 | .user = OCP_USER_MPU, | |
5208 | }; | |
5209 | ||
5210 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { | |
5211 | { | |
5212 | .name = "dma", | |
5213 | .pa_start = 0x49026000, | |
5214 | .pa_end = 0x490260ff, | |
5215 | .flags = ADDR_TYPE_RT | |
5216 | }, | |
5217 | { } | |
5218 | }; | |
5219 | ||
5220 | /* l4_abe -> mcbsp3 (dma) */ | |
5221 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { | |
5222 | .master = &omap44xx_l4_abe_hwmod, | |
5223 | .slave = &omap44xx_mcbsp3_hwmod, | |
5224 | .clk = "ocp_abe_iclk", | |
5225 | .addr = omap44xx_mcbsp3_dma_addrs, | |
5226 | .user = OCP_USER_SDMA, | |
5227 | }; | |
5228 | ||
5229 | static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { | |
5230 | { | |
5231 | .pa_start = 0x48096000, | |
5232 | .pa_end = 0x480960ff, | |
5233 | .flags = ADDR_TYPE_RT | |
5234 | }, | |
5235 | { } | |
5236 | }; | |
5237 | ||
5238 | /* l4_per -> mcbsp4 */ | |
5239 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { | |
5240 | .master = &omap44xx_l4_per_hwmod, | |
5241 | .slave = &omap44xx_mcbsp4_hwmod, | |
5242 | .clk = "l4_div_ck", | |
5243 | .addr = omap44xx_mcbsp4_addrs, | |
5244 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5245 | }; | |
5246 | ||
5247 | static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { | |
5248 | { | |
5249 | .pa_start = 0x40132000, | |
5250 | .pa_end = 0x4013207f, | |
5251 | .flags = ADDR_TYPE_RT | |
5252 | }, | |
5253 | { } | |
5254 | }; | |
5255 | ||
5256 | /* l4_abe -> mcpdm */ | |
5257 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { | |
5258 | .master = &omap44xx_l4_abe_hwmod, | |
5259 | .slave = &omap44xx_mcpdm_hwmod, | |
5260 | .clk = "ocp_abe_iclk", | |
5261 | .addr = omap44xx_mcpdm_addrs, | |
5262 | .user = OCP_USER_MPU, | |
5263 | }; | |
5264 | ||
5265 | static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { | |
5266 | { | |
5267 | .pa_start = 0x49032000, | |
5268 | .pa_end = 0x4903207f, | |
5269 | .flags = ADDR_TYPE_RT | |
5270 | }, | |
5271 | { } | |
5272 | }; | |
5273 | ||
5274 | /* l4_abe -> mcpdm (dma) */ | |
5275 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { | |
5276 | .master = &omap44xx_l4_abe_hwmod, | |
5277 | .slave = &omap44xx_mcpdm_hwmod, | |
5278 | .clk = "ocp_abe_iclk", | |
5279 | .addr = omap44xx_mcpdm_dma_addrs, | |
5280 | .user = OCP_USER_SDMA, | |
5281 | }; | |
5282 | ||
5283 | static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { | |
5284 | { | |
5285 | .pa_start = 0x48098000, | |
5286 | .pa_end = 0x480981ff, | |
5287 | .flags = ADDR_TYPE_RT | |
5288 | }, | |
5289 | { } | |
5290 | }; | |
5291 | ||
5292 | /* l4_per -> mcspi1 */ | |
5293 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { | |
5294 | .master = &omap44xx_l4_per_hwmod, | |
5295 | .slave = &omap44xx_mcspi1_hwmod, | |
5296 | .clk = "l4_div_ck", | |
5297 | .addr = omap44xx_mcspi1_addrs, | |
5298 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5299 | }; | |
5300 | ||
5301 | static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { | |
5302 | { | |
5303 | .pa_start = 0x4809a000, | |
5304 | .pa_end = 0x4809a1ff, | |
5305 | .flags = ADDR_TYPE_RT | |
5306 | }, | |
5307 | { } | |
5308 | }; | |
5309 | ||
5310 | /* l4_per -> mcspi2 */ | |
5311 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { | |
5312 | .master = &omap44xx_l4_per_hwmod, | |
5313 | .slave = &omap44xx_mcspi2_hwmod, | |
5314 | .clk = "l4_div_ck", | |
5315 | .addr = omap44xx_mcspi2_addrs, | |
5316 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5317 | }; | |
5318 | ||
5319 | static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { | |
5320 | { | |
5321 | .pa_start = 0x480b8000, | |
5322 | .pa_end = 0x480b81ff, | |
5323 | .flags = ADDR_TYPE_RT | |
5324 | }, | |
5325 | { } | |
5326 | }; | |
5327 | ||
5328 | /* l4_per -> mcspi3 */ | |
5329 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { | |
5330 | .master = &omap44xx_l4_per_hwmod, | |
5331 | .slave = &omap44xx_mcspi3_hwmod, | |
5332 | .clk = "l4_div_ck", | |
5333 | .addr = omap44xx_mcspi3_addrs, | |
5334 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5335 | }; | |
5336 | ||
5337 | static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { | |
5338 | { | |
5339 | .pa_start = 0x480ba000, | |
5340 | .pa_end = 0x480ba1ff, | |
5341 | .flags = ADDR_TYPE_RT | |
5342 | }, | |
5343 | { } | |
5344 | }; | |
5345 | ||
5346 | /* l4_per -> mcspi4 */ | |
5347 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { | |
5348 | .master = &omap44xx_l4_per_hwmod, | |
5349 | .slave = &omap44xx_mcspi4_hwmod, | |
5350 | .clk = "l4_div_ck", | |
5351 | .addr = omap44xx_mcspi4_addrs, | |
5352 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5353 | }; | |
5354 | ||
5355 | static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { | |
5356 | { | |
5357 | .pa_start = 0x4809c000, | |
5358 | .pa_end = 0x4809c3ff, | |
5359 | .flags = ADDR_TYPE_RT | |
5360 | }, | |
5361 | { } | |
5362 | }; | |
5363 | ||
5364 | /* l4_per -> mmc1 */ | |
5365 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { | |
5366 | .master = &omap44xx_l4_per_hwmod, | |
5367 | .slave = &omap44xx_mmc1_hwmod, | |
5368 | .clk = "l4_div_ck", | |
5369 | .addr = omap44xx_mmc1_addrs, | |
5370 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5371 | }; | |
5372 | ||
5373 | static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { | |
5374 | { | |
5375 | .pa_start = 0x480b4000, | |
5376 | .pa_end = 0x480b43ff, | |
5377 | .flags = ADDR_TYPE_RT | |
5378 | }, | |
5379 | { } | |
5380 | }; | |
5381 | ||
5382 | /* l4_per -> mmc2 */ | |
5383 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { | |
5384 | .master = &omap44xx_l4_per_hwmod, | |
5385 | .slave = &omap44xx_mmc2_hwmod, | |
5386 | .clk = "l4_div_ck", | |
5387 | .addr = omap44xx_mmc2_addrs, | |
5388 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5389 | }; | |
5390 | ||
5391 | static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { | |
5392 | { | |
5393 | .pa_start = 0x480ad000, | |
5394 | .pa_end = 0x480ad3ff, | |
5395 | .flags = ADDR_TYPE_RT | |
5396 | }, | |
5397 | { } | |
5398 | }; | |
5399 | ||
5400 | /* l4_per -> mmc3 */ | |
5401 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { | |
5402 | .master = &omap44xx_l4_per_hwmod, | |
5403 | .slave = &omap44xx_mmc3_hwmod, | |
5404 | .clk = "l4_div_ck", | |
5405 | .addr = omap44xx_mmc3_addrs, | |
5406 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5407 | }; | |
5408 | ||
5409 | static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { | |
5410 | { | |
5411 | .pa_start = 0x480d1000, | |
5412 | .pa_end = 0x480d13ff, | |
5413 | .flags = ADDR_TYPE_RT | |
5414 | }, | |
5415 | { } | |
5416 | }; | |
5417 | ||
5418 | /* l4_per -> mmc4 */ | |
5419 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { | |
5420 | .master = &omap44xx_l4_per_hwmod, | |
5421 | .slave = &omap44xx_mmc4_hwmod, | |
5422 | .clk = "l4_div_ck", | |
5423 | .addr = omap44xx_mmc4_addrs, | |
5424 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5425 | }; | |
5426 | ||
5427 | static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { | |
5428 | { | |
5429 | .pa_start = 0x480d5000, | |
5430 | .pa_end = 0x480d53ff, | |
5431 | .flags = ADDR_TYPE_RT | |
5432 | }, | |
5433 | { } | |
5434 | }; | |
5435 | ||
5436 | /* l4_per -> mmc5 */ | |
5437 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { | |
5438 | .master = &omap44xx_l4_per_hwmod, | |
5439 | .slave = &omap44xx_mmc5_hwmod, | |
5440 | .clk = "l4_div_ck", | |
5441 | .addr = omap44xx_mmc5_addrs, | |
5442 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5443 | }; | |
5444 | ||
e17f18c0 PW |
5445 | /* l3_main_2 -> ocmc_ram */ |
5446 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = { | |
5447 | .master = &omap44xx_l3_main_2_hwmod, | |
5448 | .slave = &omap44xx_ocmc_ram_hwmod, | |
5449 | .clk = "l3_div_ck", | |
5450 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5451 | }; | |
5452 | ||
33c976ec BC |
5453 | static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = { |
5454 | { | |
5455 | .pa_start = 0x4a0ad000, | |
5456 | .pa_end = 0x4a0ad01f, | |
5457 | .flags = ADDR_TYPE_RT | |
5458 | }, | |
5459 | { } | |
5460 | }; | |
5461 | ||
0c668875 BC |
5462 | /* l4_cfg -> ocp2scp_usb_phy */ |
5463 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = { | |
5464 | .master = &omap44xx_l4_cfg_hwmod, | |
5465 | .slave = &omap44xx_ocp2scp_usb_phy_hwmod, | |
5466 | .clk = "l4_div_ck", | |
33c976ec | 5467 | .addr = omap44xx_ocp2scp_usb_phy_addrs, |
0c668875 BC |
5468 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
5469 | }; | |
5470 | ||
794b480a PW |
5471 | static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = { |
5472 | { | |
5473 | .pa_start = 0x48243000, | |
5474 | .pa_end = 0x48243fff, | |
5475 | .flags = ADDR_TYPE_RT | |
5476 | }, | |
5477 | { } | |
5478 | }; | |
5479 | ||
5480 | /* mpu_private -> prcm_mpu */ | |
5481 | static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = { | |
5482 | .master = &omap44xx_mpu_private_hwmod, | |
5483 | .slave = &omap44xx_prcm_mpu_hwmod, | |
5484 | .clk = "l3_div_ck", | |
5485 | .addr = omap44xx_prcm_mpu_addrs, | |
5486 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5487 | }; | |
5488 | ||
5489 | static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = { | |
5490 | { | |
5491 | .pa_start = 0x4a004000, | |
5492 | .pa_end = 0x4a004fff, | |
5493 | .flags = ADDR_TYPE_RT | |
5494 | }, | |
5495 | { } | |
5496 | }; | |
5497 | ||
5498 | /* l4_wkup -> cm_core_aon */ | |
5499 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = { | |
5500 | .master = &omap44xx_l4_wkup_hwmod, | |
5501 | .slave = &omap44xx_cm_core_aon_hwmod, | |
5502 | .clk = "l4_wkup_clk_mux_ck", | |
5503 | .addr = omap44xx_cm_core_aon_addrs, | |
5504 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5505 | }; | |
5506 | ||
5507 | static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = { | |
5508 | { | |
5509 | .pa_start = 0x4a008000, | |
5510 | .pa_end = 0x4a009fff, | |
5511 | .flags = ADDR_TYPE_RT | |
5512 | }, | |
5513 | { } | |
5514 | }; | |
5515 | ||
5516 | /* l4_cfg -> cm_core */ | |
5517 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = { | |
5518 | .master = &omap44xx_l4_cfg_hwmod, | |
5519 | .slave = &omap44xx_cm_core_hwmod, | |
5520 | .clk = "l4_div_ck", | |
5521 | .addr = omap44xx_cm_core_addrs, | |
5522 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5523 | }; | |
5524 | ||
5525 | static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = { | |
5526 | { | |
5527 | .pa_start = 0x4a306000, | |
5528 | .pa_end = 0x4a307fff, | |
5529 | .flags = ADDR_TYPE_RT | |
5530 | }, | |
5531 | { } | |
5532 | }; | |
5533 | ||
5534 | /* l4_wkup -> prm */ | |
5535 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = { | |
5536 | .master = &omap44xx_l4_wkup_hwmod, | |
5537 | .slave = &omap44xx_prm_hwmod, | |
5538 | .clk = "l4_wkup_clk_mux_ck", | |
5539 | .addr = omap44xx_prm_addrs, | |
5540 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5541 | }; | |
5542 | ||
5543 | static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = { | |
5544 | { | |
5545 | .pa_start = 0x4a30a000, | |
5546 | .pa_end = 0x4a30a7ff, | |
5547 | .flags = ADDR_TYPE_RT | |
5548 | }, | |
5549 | { } | |
5550 | }; | |
5551 | ||
5552 | /* l4_wkup -> scrm */ | |
5553 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = { | |
5554 | .master = &omap44xx_l4_wkup_hwmod, | |
5555 | .slave = &omap44xx_scrm_hwmod, | |
5556 | .clk = "l4_wkup_clk_mux_ck", | |
5557 | .addr = omap44xx_scrm_addrs, | |
5558 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5559 | }; | |
5560 | ||
42b9e387 | 5561 | /* l3_main_2 -> sl2if */ |
b360124e | 5562 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = { |
42b9e387 PW |
5563 | .master = &omap44xx_l3_main_2_hwmod, |
5564 | .slave = &omap44xx_sl2if_hwmod, | |
5565 | .clk = "l3_div_ck", | |
5566 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5567 | }; | |
5568 | ||
1e3b5e59 BC |
5569 | static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = { |
5570 | { | |
5571 | .pa_start = 0x4012c000, | |
5572 | .pa_end = 0x4012c3ff, | |
5573 | .flags = ADDR_TYPE_RT | |
5574 | }, | |
5575 | { } | |
5576 | }; | |
5577 | ||
5578 | /* l4_abe -> slimbus1 */ | |
5579 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = { | |
5580 | .master = &omap44xx_l4_abe_hwmod, | |
5581 | .slave = &omap44xx_slimbus1_hwmod, | |
5582 | .clk = "ocp_abe_iclk", | |
5583 | .addr = omap44xx_slimbus1_addrs, | |
5584 | .user = OCP_USER_MPU, | |
5585 | }; | |
5586 | ||
5587 | static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = { | |
5588 | { | |
5589 | .pa_start = 0x4902c000, | |
5590 | .pa_end = 0x4902c3ff, | |
5591 | .flags = ADDR_TYPE_RT | |
5592 | }, | |
5593 | { } | |
5594 | }; | |
5595 | ||
5596 | /* l4_abe -> slimbus1 (dma) */ | |
5597 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = { | |
5598 | .master = &omap44xx_l4_abe_hwmod, | |
5599 | .slave = &omap44xx_slimbus1_hwmod, | |
5600 | .clk = "ocp_abe_iclk", | |
5601 | .addr = omap44xx_slimbus1_dma_addrs, | |
5602 | .user = OCP_USER_SDMA, | |
5603 | }; | |
5604 | ||
5605 | static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = { | |
5606 | { | |
5607 | .pa_start = 0x48076000, | |
5608 | .pa_end = 0x480763ff, | |
5609 | .flags = ADDR_TYPE_RT | |
5610 | }, | |
5611 | { } | |
5612 | }; | |
5613 | ||
5614 | /* l4_per -> slimbus2 */ | |
5615 | static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = { | |
5616 | .master = &omap44xx_l4_per_hwmod, | |
5617 | .slave = &omap44xx_slimbus2_hwmod, | |
5618 | .clk = "l4_div_ck", | |
5619 | .addr = omap44xx_slimbus2_addrs, | |
5620 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5621 | }; | |
5622 | ||
844a3b63 PW |
5623 | static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { |
5624 | { | |
5625 | .pa_start = 0x4a0dd000, | |
5626 | .pa_end = 0x4a0dd03f, | |
5627 | .flags = ADDR_TYPE_RT | |
5628 | }, | |
5629 | { } | |
5630 | }; | |
5631 | ||
5632 | /* l4_cfg -> smartreflex_core */ | |
5633 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { | |
5634 | .master = &omap44xx_l4_cfg_hwmod, | |
5635 | .slave = &omap44xx_smartreflex_core_hwmod, | |
5636 | .clk = "l4_div_ck", | |
5637 | .addr = omap44xx_smartreflex_core_addrs, | |
5638 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5639 | }; | |
5640 | ||
5641 | static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { | |
5642 | { | |
5643 | .pa_start = 0x4a0db000, | |
5644 | .pa_end = 0x4a0db03f, | |
5645 | .flags = ADDR_TYPE_RT | |
5646 | }, | |
5647 | { } | |
5648 | }; | |
5649 | ||
5650 | /* l4_cfg -> smartreflex_iva */ | |
5651 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { | |
5652 | .master = &omap44xx_l4_cfg_hwmod, | |
5653 | .slave = &omap44xx_smartreflex_iva_hwmod, | |
5654 | .clk = "l4_div_ck", | |
5655 | .addr = omap44xx_smartreflex_iva_addrs, | |
5656 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5657 | }; | |
5658 | ||
5659 | static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { | |
5660 | { | |
5661 | .pa_start = 0x4a0d9000, | |
5662 | .pa_end = 0x4a0d903f, | |
5663 | .flags = ADDR_TYPE_RT | |
5664 | }, | |
5665 | { } | |
5666 | }; | |
5667 | ||
5668 | /* l4_cfg -> smartreflex_mpu */ | |
5669 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { | |
5670 | .master = &omap44xx_l4_cfg_hwmod, | |
5671 | .slave = &omap44xx_smartreflex_mpu_hwmod, | |
5672 | .clk = "l4_div_ck", | |
5673 | .addr = omap44xx_smartreflex_mpu_addrs, | |
5674 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5675 | }; | |
5676 | ||
5677 | static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { | |
5678 | { | |
5679 | .pa_start = 0x4a0f6000, | |
5680 | .pa_end = 0x4a0f6fff, | |
5681 | .flags = ADDR_TYPE_RT | |
5682 | }, | |
5683 | { } | |
5684 | }; | |
5685 | ||
5686 | /* l4_cfg -> spinlock */ | |
5687 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { | |
5688 | .master = &omap44xx_l4_cfg_hwmod, | |
5689 | .slave = &omap44xx_spinlock_hwmod, | |
5690 | .clk = "l4_div_ck", | |
5691 | .addr = omap44xx_spinlock_addrs, | |
5692 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5693 | }; | |
5694 | ||
5695 | static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { | |
5696 | { | |
5697 | .pa_start = 0x4a318000, | |
5698 | .pa_end = 0x4a31807f, | |
5699 | .flags = ADDR_TYPE_RT | |
5700 | }, | |
5701 | { } | |
5702 | }; | |
5703 | ||
5704 | /* l4_wkup -> timer1 */ | |
5705 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { | |
5706 | .master = &omap44xx_l4_wkup_hwmod, | |
5707 | .slave = &omap44xx_timer1_hwmod, | |
5708 | .clk = "l4_wkup_clk_mux_ck", | |
5709 | .addr = omap44xx_timer1_addrs, | |
5710 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5711 | }; | |
5712 | ||
5713 | static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { | |
5714 | { | |
5715 | .pa_start = 0x48032000, | |
5716 | .pa_end = 0x4803207f, | |
5717 | .flags = ADDR_TYPE_RT | |
5718 | }, | |
5719 | { } | |
5720 | }; | |
5721 | ||
5722 | /* l4_per -> timer2 */ | |
5723 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { | |
5724 | .master = &omap44xx_l4_per_hwmod, | |
5725 | .slave = &omap44xx_timer2_hwmod, | |
5726 | .clk = "l4_div_ck", | |
5727 | .addr = omap44xx_timer2_addrs, | |
5728 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5729 | }; | |
5730 | ||
5731 | static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { | |
5732 | { | |
5733 | .pa_start = 0x48034000, | |
5734 | .pa_end = 0x4803407f, | |
5735 | .flags = ADDR_TYPE_RT | |
5736 | }, | |
5737 | { } | |
5738 | }; | |
5739 | ||
5740 | /* l4_per -> timer3 */ | |
5741 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { | |
5742 | .master = &omap44xx_l4_per_hwmod, | |
5743 | .slave = &omap44xx_timer3_hwmod, | |
5744 | .clk = "l4_div_ck", | |
5745 | .addr = omap44xx_timer3_addrs, | |
5746 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5747 | }; | |
5748 | ||
5749 | static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { | |
5750 | { | |
5751 | .pa_start = 0x48036000, | |
5752 | .pa_end = 0x4803607f, | |
5753 | .flags = ADDR_TYPE_RT | |
5754 | }, | |
5755 | { } | |
5756 | }; | |
5757 | ||
5758 | /* l4_per -> timer4 */ | |
5759 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { | |
5760 | .master = &omap44xx_l4_per_hwmod, | |
5761 | .slave = &omap44xx_timer4_hwmod, | |
5762 | .clk = "l4_div_ck", | |
5763 | .addr = omap44xx_timer4_addrs, | |
5764 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5765 | }; | |
5766 | ||
5767 | static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { | |
5768 | { | |
5769 | .pa_start = 0x40138000, | |
5770 | .pa_end = 0x4013807f, | |
5771 | .flags = ADDR_TYPE_RT | |
5772 | }, | |
5773 | { } | |
5774 | }; | |
5775 | ||
5776 | /* l4_abe -> timer5 */ | |
5777 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { | |
5778 | .master = &omap44xx_l4_abe_hwmod, | |
5779 | .slave = &omap44xx_timer5_hwmod, | |
5780 | .clk = "ocp_abe_iclk", | |
5781 | .addr = omap44xx_timer5_addrs, | |
5782 | .user = OCP_USER_MPU, | |
5783 | }; | |
5784 | ||
5785 | static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { | |
5786 | { | |
5787 | .pa_start = 0x49038000, | |
5788 | .pa_end = 0x4903807f, | |
5789 | .flags = ADDR_TYPE_RT | |
5790 | }, | |
5791 | { } | |
5792 | }; | |
5793 | ||
5794 | /* l4_abe -> timer5 (dma) */ | |
5795 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { | |
5796 | .master = &omap44xx_l4_abe_hwmod, | |
5797 | .slave = &omap44xx_timer5_hwmod, | |
5798 | .clk = "ocp_abe_iclk", | |
5799 | .addr = omap44xx_timer5_dma_addrs, | |
5800 | .user = OCP_USER_SDMA, | |
5801 | }; | |
5802 | ||
5803 | static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { | |
5804 | { | |
5805 | .pa_start = 0x4013a000, | |
5806 | .pa_end = 0x4013a07f, | |
5807 | .flags = ADDR_TYPE_RT | |
5808 | }, | |
5809 | { } | |
5810 | }; | |
5811 | ||
5812 | /* l4_abe -> timer6 */ | |
5813 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { | |
5814 | .master = &omap44xx_l4_abe_hwmod, | |
5815 | .slave = &omap44xx_timer6_hwmod, | |
5816 | .clk = "ocp_abe_iclk", | |
5817 | .addr = omap44xx_timer6_addrs, | |
5818 | .user = OCP_USER_MPU, | |
5819 | }; | |
5820 | ||
5821 | static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { | |
5822 | { | |
5823 | .pa_start = 0x4903a000, | |
5824 | .pa_end = 0x4903a07f, | |
5825 | .flags = ADDR_TYPE_RT | |
5826 | }, | |
5827 | { } | |
5828 | }; | |
5829 | ||
5830 | /* l4_abe -> timer6 (dma) */ | |
5831 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { | |
5832 | .master = &omap44xx_l4_abe_hwmod, | |
5833 | .slave = &omap44xx_timer6_hwmod, | |
5834 | .clk = "ocp_abe_iclk", | |
5835 | .addr = omap44xx_timer6_dma_addrs, | |
5836 | .user = OCP_USER_SDMA, | |
5837 | }; | |
5838 | ||
5839 | static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { | |
5840 | { | |
5841 | .pa_start = 0x4013c000, | |
5842 | .pa_end = 0x4013c07f, | |
5843 | .flags = ADDR_TYPE_RT | |
5844 | }, | |
5845 | { } | |
5846 | }; | |
5847 | ||
5848 | /* l4_abe -> timer7 */ | |
5849 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { | |
5850 | .master = &omap44xx_l4_abe_hwmod, | |
5851 | .slave = &omap44xx_timer7_hwmod, | |
5852 | .clk = "ocp_abe_iclk", | |
5853 | .addr = omap44xx_timer7_addrs, | |
5854 | .user = OCP_USER_MPU, | |
5855 | }; | |
5856 | ||
5857 | static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { | |
5858 | { | |
5859 | .pa_start = 0x4903c000, | |
5860 | .pa_end = 0x4903c07f, | |
5861 | .flags = ADDR_TYPE_RT | |
5862 | }, | |
5863 | { } | |
5864 | }; | |
5865 | ||
5866 | /* l4_abe -> timer7 (dma) */ | |
5867 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { | |
5868 | .master = &omap44xx_l4_abe_hwmod, | |
5869 | .slave = &omap44xx_timer7_hwmod, | |
5870 | .clk = "ocp_abe_iclk", | |
5871 | .addr = omap44xx_timer7_dma_addrs, | |
5872 | .user = OCP_USER_SDMA, | |
5873 | }; | |
5874 | ||
5875 | static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { | |
5876 | { | |
5877 | .pa_start = 0x4013e000, | |
5878 | .pa_end = 0x4013e07f, | |
5879 | .flags = ADDR_TYPE_RT | |
5880 | }, | |
5881 | { } | |
5882 | }; | |
5883 | ||
5884 | /* l4_abe -> timer8 */ | |
5885 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { | |
5886 | .master = &omap44xx_l4_abe_hwmod, | |
5887 | .slave = &omap44xx_timer8_hwmod, | |
5888 | .clk = "ocp_abe_iclk", | |
5889 | .addr = omap44xx_timer8_addrs, | |
5890 | .user = OCP_USER_MPU, | |
5891 | }; | |
5892 | ||
5893 | static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { | |
5894 | { | |
5895 | .pa_start = 0x4903e000, | |
5896 | .pa_end = 0x4903e07f, | |
5897 | .flags = ADDR_TYPE_RT | |
5898 | }, | |
5899 | { } | |
5900 | }; | |
5901 | ||
5902 | /* l4_abe -> timer8 (dma) */ | |
5903 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { | |
5904 | .master = &omap44xx_l4_abe_hwmod, | |
5905 | .slave = &omap44xx_timer8_hwmod, | |
5906 | .clk = "ocp_abe_iclk", | |
5907 | .addr = omap44xx_timer8_dma_addrs, | |
5908 | .user = OCP_USER_SDMA, | |
5909 | }; | |
5910 | ||
5911 | static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { | |
5912 | { | |
5913 | .pa_start = 0x4803e000, | |
5914 | .pa_end = 0x4803e07f, | |
5915 | .flags = ADDR_TYPE_RT | |
5916 | }, | |
5917 | { } | |
5918 | }; | |
5919 | ||
5920 | /* l4_per -> timer9 */ | |
5921 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { | |
5922 | .master = &omap44xx_l4_per_hwmod, | |
5923 | .slave = &omap44xx_timer9_hwmod, | |
5924 | .clk = "l4_div_ck", | |
5925 | .addr = omap44xx_timer9_addrs, | |
5926 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5927 | }; | |
5928 | ||
5929 | static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { | |
5930 | { | |
5931 | .pa_start = 0x48086000, | |
5932 | .pa_end = 0x4808607f, | |
5933 | .flags = ADDR_TYPE_RT | |
5934 | }, | |
5935 | { } | |
5936 | }; | |
5937 | ||
5938 | /* l4_per -> timer10 */ | |
5939 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { | |
5940 | .master = &omap44xx_l4_per_hwmod, | |
5941 | .slave = &omap44xx_timer10_hwmod, | |
5942 | .clk = "l4_div_ck", | |
5943 | .addr = omap44xx_timer10_addrs, | |
5944 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5945 | }; | |
5946 | ||
5947 | static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { | |
5948 | { | |
5949 | .pa_start = 0x48088000, | |
5950 | .pa_end = 0x4808807f, | |
5951 | .flags = ADDR_TYPE_RT | |
5952 | }, | |
5953 | { } | |
5954 | }; | |
5955 | ||
5956 | /* l4_per -> timer11 */ | |
5957 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { | |
5958 | .master = &omap44xx_l4_per_hwmod, | |
5959 | .slave = &omap44xx_timer11_hwmod, | |
5960 | .clk = "l4_div_ck", | |
5961 | .addr = omap44xx_timer11_addrs, | |
af88fa9a BC |
5962 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
5963 | }; | |
5964 | ||
844a3b63 PW |
5965 | static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { |
5966 | { | |
5967 | .pa_start = 0x4806a000, | |
5968 | .pa_end = 0x4806a0ff, | |
5969 | .flags = ADDR_TYPE_RT | |
af88fa9a | 5970 | }, |
844a3b63 PW |
5971 | { } |
5972 | }; | |
af88fa9a | 5973 | |
844a3b63 PW |
5974 | /* l4_per -> uart1 */ |
5975 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { | |
5976 | .master = &omap44xx_l4_per_hwmod, | |
5977 | .slave = &omap44xx_uart1_hwmod, | |
5978 | .clk = "l4_div_ck", | |
5979 | .addr = omap44xx_uart1_addrs, | |
5980 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5981 | }; | |
af88fa9a | 5982 | |
844a3b63 PW |
5983 | static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { |
5984 | { | |
5985 | .pa_start = 0x4806c000, | |
5986 | .pa_end = 0x4806c0ff, | |
5987 | .flags = ADDR_TYPE_RT | |
5988 | }, | |
5989 | { } | |
5990 | }; | |
af88fa9a | 5991 | |
844a3b63 PW |
5992 | /* l4_per -> uart2 */ |
5993 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { | |
5994 | .master = &omap44xx_l4_per_hwmod, | |
5995 | .slave = &omap44xx_uart2_hwmod, | |
5996 | .clk = "l4_div_ck", | |
5997 | .addr = omap44xx_uart2_addrs, | |
5998 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5999 | }; | |
af88fa9a | 6000 | |
844a3b63 PW |
6001 | static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { |
6002 | { | |
6003 | .pa_start = 0x48020000, | |
6004 | .pa_end = 0x480200ff, | |
6005 | .flags = ADDR_TYPE_RT | |
6006 | }, | |
6007 | { } | |
af88fa9a BC |
6008 | }; |
6009 | ||
844a3b63 PW |
6010 | /* l4_per -> uart3 */ |
6011 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { | |
6012 | .master = &omap44xx_l4_per_hwmod, | |
6013 | .slave = &omap44xx_uart3_hwmod, | |
6014 | .clk = "l4_div_ck", | |
6015 | .addr = omap44xx_uart3_addrs, | |
6016 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
af88fa9a BC |
6017 | }; |
6018 | ||
844a3b63 PW |
6019 | static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { |
6020 | { | |
6021 | .pa_start = 0x4806e000, | |
6022 | .pa_end = 0x4806e0ff, | |
6023 | .flags = ADDR_TYPE_RT | |
6024 | }, | |
6025 | { } | |
af88fa9a BC |
6026 | }; |
6027 | ||
844a3b63 PW |
6028 | /* l4_per -> uart4 */ |
6029 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { | |
6030 | .master = &omap44xx_l4_per_hwmod, | |
6031 | .slave = &omap44xx_uart4_hwmod, | |
6032 | .clk = "l4_div_ck", | |
6033 | .addr = omap44xx_uart4_addrs, | |
6034 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
6035 | }; | |
6036 | ||
0c668875 BC |
6037 | static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = { |
6038 | { | |
6039 | .pa_start = 0x4a0a9000, | |
6040 | .pa_end = 0x4a0a93ff, | |
6041 | .flags = ADDR_TYPE_RT | |
6042 | }, | |
6043 | { } | |
6044 | }; | |
6045 | ||
6046 | /* l4_cfg -> usb_host_fs */ | |
b0a70cc8 | 6047 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = { |
0c668875 BC |
6048 | .master = &omap44xx_l4_cfg_hwmod, |
6049 | .slave = &omap44xx_usb_host_fs_hwmod, | |
6050 | .clk = "l4_div_ck", | |
6051 | .addr = omap44xx_usb_host_fs_addrs, | |
6052 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
6053 | }; | |
6054 | ||
844a3b63 PW |
6055 | static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { |
6056 | { | |
6057 | .name = "uhh", | |
6058 | .pa_start = 0x4a064000, | |
6059 | .pa_end = 0x4a0647ff, | |
6060 | .flags = ADDR_TYPE_RT | |
6061 | }, | |
6062 | { | |
6063 | .name = "ohci", | |
6064 | .pa_start = 0x4a064800, | |
6065 | .pa_end = 0x4a064bff, | |
6066 | }, | |
6067 | { | |
6068 | .name = "ehci", | |
6069 | .pa_start = 0x4a064c00, | |
6070 | .pa_end = 0x4a064fff, | |
6071 | }, | |
6072 | {} | |
6073 | }; | |
6074 | ||
6075 | /* l4_cfg -> usb_host_hs */ | |
6076 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { | |
6077 | .master = &omap44xx_l4_cfg_hwmod, | |
6078 | .slave = &omap44xx_usb_host_hs_hwmod, | |
6079 | .clk = "l4_div_ck", | |
6080 | .addr = omap44xx_usb_host_hs_addrs, | |
6081 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
6082 | }; | |
6083 | ||
6084 | static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { | |
6085 | { | |
6086 | .pa_start = 0x4a0ab000, | |
33c976ec | 6087 | .pa_end = 0x4a0ab7ff, |
844a3b63 PW |
6088 | .flags = ADDR_TYPE_RT |
6089 | }, | |
6090 | { } | |
6091 | }; | |
6092 | ||
6093 | /* l4_cfg -> usb_otg_hs */ | |
6094 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { | |
6095 | .master = &omap44xx_l4_cfg_hwmod, | |
6096 | .slave = &omap44xx_usb_otg_hs_hwmod, | |
6097 | .clk = "l4_div_ck", | |
6098 | .addr = omap44xx_usb_otg_hs_addrs, | |
6099 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
af88fa9a BC |
6100 | }; |
6101 | ||
6102 | static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { | |
6103 | { | |
6104 | .name = "tll", | |
6105 | .pa_start = 0x4a062000, | |
6106 | .pa_end = 0x4a063fff, | |
6107 | .flags = ADDR_TYPE_RT | |
6108 | }, | |
6109 | {} | |
6110 | }; | |
6111 | ||
844a3b63 | 6112 | /* l4_cfg -> usb_tll_hs */ |
af88fa9a BC |
6113 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { |
6114 | .master = &omap44xx_l4_cfg_hwmod, | |
6115 | .slave = &omap44xx_usb_tll_hs_hwmod, | |
6116 | .clk = "l4_div_ck", | |
6117 | .addr = omap44xx_usb_tll_hs_addrs, | |
6118 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
6119 | }; | |
6120 | ||
844a3b63 PW |
6121 | static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { |
6122 | { | |
6123 | .pa_start = 0x4a314000, | |
6124 | .pa_end = 0x4a31407f, | |
6125 | .flags = ADDR_TYPE_RT | |
af88fa9a | 6126 | }, |
844a3b63 PW |
6127 | { } |
6128 | }; | |
6129 | ||
6130 | /* l4_wkup -> wd_timer2 */ | |
6131 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { | |
6132 | .master = &omap44xx_l4_wkup_hwmod, | |
6133 | .slave = &omap44xx_wd_timer2_hwmod, | |
6134 | .clk = "l4_wkup_clk_mux_ck", | |
6135 | .addr = omap44xx_wd_timer2_addrs, | |
6136 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
6137 | }; | |
6138 | ||
6139 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { | |
6140 | { | |
6141 | .pa_start = 0x40130000, | |
6142 | .pa_end = 0x4013007f, | |
6143 | .flags = ADDR_TYPE_RT | |
6144 | }, | |
6145 | { } | |
6146 | }; | |
6147 | ||
6148 | /* l4_abe -> wd_timer3 */ | |
6149 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { | |
6150 | .master = &omap44xx_l4_abe_hwmod, | |
6151 | .slave = &omap44xx_wd_timer3_hwmod, | |
6152 | .clk = "ocp_abe_iclk", | |
6153 | .addr = omap44xx_wd_timer3_addrs, | |
6154 | .user = OCP_USER_MPU, | |
6155 | }; | |
6156 | ||
6157 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { | |
6158 | { | |
6159 | .pa_start = 0x49030000, | |
6160 | .pa_end = 0x4903007f, | |
6161 | .flags = ADDR_TYPE_RT | |
6162 | }, | |
6163 | { } | |
6164 | }; | |
6165 | ||
6166 | /* l4_abe -> wd_timer3 (dma) */ | |
6167 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { | |
6168 | .master = &omap44xx_l4_abe_hwmod, | |
6169 | .slave = &omap44xx_wd_timer3_hwmod, | |
6170 | .clk = "ocp_abe_iclk", | |
6171 | .addr = omap44xx_wd_timer3_dma_addrs, | |
6172 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
6173 | }; |
6174 | ||
0a78c5c5 | 6175 | static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { |
42b9e387 PW |
6176 | &omap44xx_c2c__c2c_target_fw, |
6177 | &omap44xx_l4_cfg__c2c_target_fw, | |
0a78c5c5 PW |
6178 | &omap44xx_l3_main_1__dmm, |
6179 | &omap44xx_mpu__dmm, | |
42b9e387 | 6180 | &omap44xx_c2c__emif_fw, |
0a78c5c5 PW |
6181 | &omap44xx_dmm__emif_fw, |
6182 | &omap44xx_l4_cfg__emif_fw, | |
6183 | &omap44xx_iva__l3_instr, | |
6184 | &omap44xx_l3_main_3__l3_instr, | |
9a817bc8 | 6185 | &omap44xx_ocp_wp_noc__l3_instr, |
0a78c5c5 PW |
6186 | &omap44xx_dsp__l3_main_1, |
6187 | &omap44xx_dss__l3_main_1, | |
6188 | &omap44xx_l3_main_2__l3_main_1, | |
6189 | &omap44xx_l4_cfg__l3_main_1, | |
6190 | &omap44xx_mmc1__l3_main_1, | |
6191 | &omap44xx_mmc2__l3_main_1, | |
6192 | &omap44xx_mpu__l3_main_1, | |
42b9e387 | 6193 | &omap44xx_c2c_target_fw__l3_main_2, |
96566043 | 6194 | &omap44xx_debugss__l3_main_2, |
0a78c5c5 | 6195 | &omap44xx_dma_system__l3_main_2, |
b050f688 | 6196 | &omap44xx_fdif__l3_main_2, |
9def390e | 6197 | &omap44xx_gpu__l3_main_2, |
0a78c5c5 PW |
6198 | &omap44xx_hsi__l3_main_2, |
6199 | &omap44xx_ipu__l3_main_2, | |
6200 | &omap44xx_iss__l3_main_2, | |
6201 | &omap44xx_iva__l3_main_2, | |
6202 | &omap44xx_l3_main_1__l3_main_2, | |
6203 | &omap44xx_l4_cfg__l3_main_2, | |
b0a70cc8 | 6204 | /* &omap44xx_usb_host_fs__l3_main_2, */ |
0a78c5c5 PW |
6205 | &omap44xx_usb_host_hs__l3_main_2, |
6206 | &omap44xx_usb_otg_hs__l3_main_2, | |
6207 | &omap44xx_l3_main_1__l3_main_3, | |
6208 | &omap44xx_l3_main_2__l3_main_3, | |
6209 | &omap44xx_l4_cfg__l3_main_3, | |
b0a70cc8 | 6210 | /* &omap44xx_aess__l4_abe, */ |
0a78c5c5 PW |
6211 | &omap44xx_dsp__l4_abe, |
6212 | &omap44xx_l3_main_1__l4_abe, | |
6213 | &omap44xx_mpu__l4_abe, | |
6214 | &omap44xx_l3_main_1__l4_cfg, | |
6215 | &omap44xx_l3_main_2__l4_per, | |
6216 | &omap44xx_l4_cfg__l4_wkup, | |
6217 | &omap44xx_mpu__mpu_private, | |
9a817bc8 | 6218 | &omap44xx_l4_cfg__ocp_wp_noc, |
b0a70cc8 PW |
6219 | /* &omap44xx_l4_abe__aess, */ |
6220 | /* &omap44xx_l4_abe__aess_dma, */ | |
42b9e387 | 6221 | &omap44xx_l3_main_2__c2c, |
0a78c5c5 | 6222 | &omap44xx_l4_wkup__counter_32k, |
a0b5d813 PW |
6223 | &omap44xx_l4_cfg__ctrl_module_core, |
6224 | &omap44xx_l4_cfg__ctrl_module_pad_core, | |
6225 | &omap44xx_l4_wkup__ctrl_module_wkup, | |
6226 | &omap44xx_l4_wkup__ctrl_module_pad_wkup, | |
96566043 | 6227 | &omap44xx_l3_instr__debugss, |
0a78c5c5 PW |
6228 | &omap44xx_l4_cfg__dma_system, |
6229 | &omap44xx_l4_abe__dmic, | |
6230 | &omap44xx_l4_abe__dmic_dma, | |
6231 | &omap44xx_dsp__iva, | |
b360124e | 6232 | /* &omap44xx_dsp__sl2if, */ |
0a78c5c5 PW |
6233 | &omap44xx_l4_cfg__dsp, |
6234 | &omap44xx_l3_main_2__dss, | |
6235 | &omap44xx_l4_per__dss, | |
6236 | &omap44xx_l3_main_2__dss_dispc, | |
6237 | &omap44xx_l4_per__dss_dispc, | |
6238 | &omap44xx_l3_main_2__dss_dsi1, | |
6239 | &omap44xx_l4_per__dss_dsi1, | |
6240 | &omap44xx_l3_main_2__dss_dsi2, | |
6241 | &omap44xx_l4_per__dss_dsi2, | |
6242 | &omap44xx_l3_main_2__dss_hdmi, | |
6243 | &omap44xx_l4_per__dss_hdmi, | |
6244 | &omap44xx_l3_main_2__dss_rfbi, | |
6245 | &omap44xx_l4_per__dss_rfbi, | |
6246 | &omap44xx_l3_main_2__dss_venc, | |
6247 | &omap44xx_l4_per__dss_venc, | |
42b9e387 | 6248 | &omap44xx_l4_per__elm, |
bf30f950 PW |
6249 | &omap44xx_emif_fw__emif1, |
6250 | &omap44xx_emif_fw__emif2, | |
b050f688 | 6251 | &omap44xx_l4_cfg__fdif, |
0a78c5c5 PW |
6252 | &omap44xx_l4_wkup__gpio1, |
6253 | &omap44xx_l4_per__gpio2, | |
6254 | &omap44xx_l4_per__gpio3, | |
6255 | &omap44xx_l4_per__gpio4, | |
6256 | &omap44xx_l4_per__gpio5, | |
6257 | &omap44xx_l4_per__gpio6, | |
eb42b5d3 | 6258 | &omap44xx_l3_main_2__gpmc, |
9def390e | 6259 | &omap44xx_l3_main_2__gpu, |
a091c08e | 6260 | &omap44xx_l4_per__hdq1w, |
0a78c5c5 PW |
6261 | &omap44xx_l4_cfg__hsi, |
6262 | &omap44xx_l4_per__i2c1, | |
6263 | &omap44xx_l4_per__i2c2, | |
6264 | &omap44xx_l4_per__i2c3, | |
6265 | &omap44xx_l4_per__i2c4, | |
6266 | &omap44xx_l3_main_2__ipu, | |
6267 | &omap44xx_l3_main_2__iss, | |
b360124e | 6268 | /* &omap44xx_iva__sl2if, */ |
0a78c5c5 PW |
6269 | &omap44xx_l3_main_2__iva, |
6270 | &omap44xx_l4_wkup__kbd, | |
6271 | &omap44xx_l4_cfg__mailbox, | |
896d4e98 BC |
6272 | &omap44xx_l4_abe__mcasp, |
6273 | &omap44xx_l4_abe__mcasp_dma, | |
0a78c5c5 PW |
6274 | &omap44xx_l4_abe__mcbsp1, |
6275 | &omap44xx_l4_abe__mcbsp1_dma, | |
6276 | &omap44xx_l4_abe__mcbsp2, | |
6277 | &omap44xx_l4_abe__mcbsp2_dma, | |
6278 | &omap44xx_l4_abe__mcbsp3, | |
6279 | &omap44xx_l4_abe__mcbsp3_dma, | |
6280 | &omap44xx_l4_per__mcbsp4, | |
6281 | &omap44xx_l4_abe__mcpdm, | |
6282 | &omap44xx_l4_abe__mcpdm_dma, | |
6283 | &omap44xx_l4_per__mcspi1, | |
6284 | &omap44xx_l4_per__mcspi2, | |
6285 | &omap44xx_l4_per__mcspi3, | |
6286 | &omap44xx_l4_per__mcspi4, | |
6287 | &omap44xx_l4_per__mmc1, | |
6288 | &omap44xx_l4_per__mmc2, | |
6289 | &omap44xx_l4_per__mmc3, | |
6290 | &omap44xx_l4_per__mmc4, | |
6291 | &omap44xx_l4_per__mmc5, | |
230844db ORL |
6292 | &omap44xx_l3_main_2__mmu_ipu, |
6293 | &omap44xx_l4_cfg__mmu_dsp, | |
e17f18c0 | 6294 | &omap44xx_l3_main_2__ocmc_ram, |
0c668875 | 6295 | &omap44xx_l4_cfg__ocp2scp_usb_phy, |
794b480a PW |
6296 | &omap44xx_mpu_private__prcm_mpu, |
6297 | &omap44xx_l4_wkup__cm_core_aon, | |
6298 | &omap44xx_l4_cfg__cm_core, | |
6299 | &omap44xx_l4_wkup__prm, | |
6300 | &omap44xx_l4_wkup__scrm, | |
b360124e | 6301 | /* &omap44xx_l3_main_2__sl2if, */ |
1e3b5e59 BC |
6302 | &omap44xx_l4_abe__slimbus1, |
6303 | &omap44xx_l4_abe__slimbus1_dma, | |
6304 | &omap44xx_l4_per__slimbus2, | |
0a78c5c5 PW |
6305 | &omap44xx_l4_cfg__smartreflex_core, |
6306 | &omap44xx_l4_cfg__smartreflex_iva, | |
6307 | &omap44xx_l4_cfg__smartreflex_mpu, | |
6308 | &omap44xx_l4_cfg__spinlock, | |
6309 | &omap44xx_l4_wkup__timer1, | |
6310 | &omap44xx_l4_per__timer2, | |
6311 | &omap44xx_l4_per__timer3, | |
6312 | &omap44xx_l4_per__timer4, | |
6313 | &omap44xx_l4_abe__timer5, | |
6314 | &omap44xx_l4_abe__timer5_dma, | |
6315 | &omap44xx_l4_abe__timer6, | |
6316 | &omap44xx_l4_abe__timer6_dma, | |
6317 | &omap44xx_l4_abe__timer7, | |
6318 | &omap44xx_l4_abe__timer7_dma, | |
6319 | &omap44xx_l4_abe__timer8, | |
6320 | &omap44xx_l4_abe__timer8_dma, | |
6321 | &omap44xx_l4_per__timer9, | |
6322 | &omap44xx_l4_per__timer10, | |
6323 | &omap44xx_l4_per__timer11, | |
6324 | &omap44xx_l4_per__uart1, | |
6325 | &omap44xx_l4_per__uart2, | |
6326 | &omap44xx_l4_per__uart3, | |
6327 | &omap44xx_l4_per__uart4, | |
b0a70cc8 | 6328 | /* &omap44xx_l4_cfg__usb_host_fs, */ |
0a78c5c5 PW |
6329 | &omap44xx_l4_cfg__usb_host_hs, |
6330 | &omap44xx_l4_cfg__usb_otg_hs, | |
6331 | &omap44xx_l4_cfg__usb_tll_hs, | |
6332 | &omap44xx_l4_wkup__wd_timer2, | |
6333 | &omap44xx_l4_abe__wd_timer3, | |
6334 | &omap44xx_l4_abe__wd_timer3_dma, | |
55d2cb08 BC |
6335 | NULL, |
6336 | }; | |
6337 | ||
6338 | int __init omap44xx_hwmod_init(void) | |
6339 | { | |
9ebfd285 | 6340 | omap_hwmod_init(); |
0a78c5c5 | 6341 | return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); |
55d2cb08 BC |
6342 | } |
6343 |