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55d2cb08 BC |
1 | /* |
2 | * Hardware modules present on the OMAP44xx chips | |
3 | * | |
4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. | |
5 | * Copyright (C) 2009-2010 Nokia Corporation | |
6 | * | |
7 | * Paul Walmsley | |
8 | * Benoit Cousson | |
9 | * | |
10 | * This file is automatically generated from the OMAP hardware databases. | |
11 | * We respectfully ask that any modifications to this file be coordinated | |
12 | * with the public linux-omap@vger.kernel.org mailing list and the | |
13 | * authors above to ensure that the autogeneration scripts are kept | |
14 | * up-to-date with the file contents. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/io.h> | |
22 | ||
23 | #include <plat/omap_hwmod.h> | |
24 | #include <plat/cpu.h> | |
9780a9cf | 25 | #include <plat/gpio.h> |
531ce0d5 | 26 | #include <plat/dma.h> |
55d2cb08 BC |
27 | |
28 | #include "omap_hwmod_common_data.h" | |
29 | ||
d198b514 PW |
30 | #include "cm1_44xx.h" |
31 | #include "cm2_44xx.h" | |
32 | #include "prm44xx.h" | |
55d2cb08 | 33 | #include "prm-regbits-44xx.h" |
ff2516fb | 34 | #include "wd_timer.h" |
55d2cb08 BC |
35 | |
36 | /* Base offset for all OMAP4 interrupts external to MPUSS */ | |
37 | #define OMAP44XX_IRQ_GIC_START 32 | |
38 | ||
39 | /* Base offset for all OMAP4 dma requests */ | |
40 | #define OMAP44XX_DMA_REQ_START 1 | |
41 | ||
42 | /* Backward references (IPs with Bus Master capability) */ | |
531ce0d5 | 43 | static struct omap_hwmod omap44xx_dma_system_hwmod; |
55d2cb08 | 44 | static struct omap_hwmod omap44xx_dmm_hwmod; |
8f25bdc5 | 45 | static struct omap_hwmod omap44xx_dsp_hwmod; |
55d2cb08 | 46 | static struct omap_hwmod omap44xx_emif_fw_hwmod; |
8f25bdc5 | 47 | static struct omap_hwmod omap44xx_iva_hwmod; |
55d2cb08 BC |
48 | static struct omap_hwmod omap44xx_l3_instr_hwmod; |
49 | static struct omap_hwmod omap44xx_l3_main_1_hwmod; | |
50 | static struct omap_hwmod omap44xx_l3_main_2_hwmod; | |
51 | static struct omap_hwmod omap44xx_l3_main_3_hwmod; | |
52 | static struct omap_hwmod omap44xx_l4_abe_hwmod; | |
53 | static struct omap_hwmod omap44xx_l4_cfg_hwmod; | |
54 | static struct omap_hwmod omap44xx_l4_per_hwmod; | |
55 | static struct omap_hwmod omap44xx_l4_wkup_hwmod; | |
56 | static struct omap_hwmod omap44xx_mpu_hwmod; | |
57 | static struct omap_hwmod omap44xx_mpu_private_hwmod; | |
58 | ||
59 | /* | |
60 | * Interconnects omap_hwmod structures | |
61 | * hwmods that compose the global OMAP interconnect | |
62 | */ | |
63 | ||
64 | /* | |
65 | * 'dmm' class | |
66 | * instance(s): dmm | |
67 | */ | |
68 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { | |
fe13471c | 69 | .name = "dmm", |
55d2cb08 BC |
70 | }; |
71 | ||
72 | /* dmm interface data */ | |
73 | /* l3_main_1 -> dmm */ | |
74 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { | |
75 | .master = &omap44xx_l3_main_1_hwmod, | |
76 | .slave = &omap44xx_dmm_hwmod, | |
77 | .clk = "l3_div_ck", | |
659fa822 BC |
78 | .user = OCP_USER_SDMA, |
79 | }; | |
80 | ||
81 | static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { | |
82 | { | |
83 | .pa_start = 0x4e000000, | |
84 | .pa_end = 0x4e0007ff, | |
85 | .flags = ADDR_TYPE_RT | |
86 | }, | |
55d2cb08 BC |
87 | }; |
88 | ||
89 | /* mpu -> dmm */ | |
90 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { | |
91 | .master = &omap44xx_mpu_hwmod, | |
92 | .slave = &omap44xx_dmm_hwmod, | |
93 | .clk = "l3_div_ck", | |
659fa822 BC |
94 | .addr = omap44xx_dmm_addrs, |
95 | .addr_cnt = ARRAY_SIZE(omap44xx_dmm_addrs), | |
96 | .user = OCP_USER_MPU, | |
55d2cb08 BC |
97 | }; |
98 | ||
99 | /* dmm slave ports */ | |
100 | static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = { | |
101 | &omap44xx_l3_main_1__dmm, | |
102 | &omap44xx_mpu__dmm, | |
103 | }; | |
104 | ||
105 | static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { | |
106 | { .irq = 113 + OMAP44XX_IRQ_GIC_START }, | |
107 | }; | |
108 | ||
109 | static struct omap_hwmod omap44xx_dmm_hwmod = { | |
110 | .name = "dmm", | |
111 | .class = &omap44xx_dmm_hwmod_class, | |
112 | .slaves = omap44xx_dmm_slaves, | |
113 | .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), | |
114 | .mpu_irqs = omap44xx_dmm_irqs, | |
115 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs), | |
116 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
117 | }; | |
118 | ||
119 | /* | |
120 | * 'emif_fw' class | |
121 | * instance(s): emif_fw | |
122 | */ | |
123 | static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { | |
fe13471c | 124 | .name = "emif_fw", |
55d2cb08 BC |
125 | }; |
126 | ||
127 | /* emif_fw interface data */ | |
128 | /* dmm -> emif_fw */ | |
129 | static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { | |
130 | .master = &omap44xx_dmm_hwmod, | |
131 | .slave = &omap44xx_emif_fw_hwmod, | |
132 | .clk = "l3_div_ck", | |
133 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
134 | }; | |
135 | ||
659fa822 BC |
136 | static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { |
137 | { | |
138 | .pa_start = 0x4a20c000, | |
139 | .pa_end = 0x4a20c0ff, | |
140 | .flags = ADDR_TYPE_RT | |
141 | }, | |
142 | }; | |
143 | ||
55d2cb08 BC |
144 | /* l4_cfg -> emif_fw */ |
145 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { | |
146 | .master = &omap44xx_l4_cfg_hwmod, | |
147 | .slave = &omap44xx_emif_fw_hwmod, | |
148 | .clk = "l4_div_ck", | |
659fa822 BC |
149 | .addr = omap44xx_emif_fw_addrs, |
150 | .addr_cnt = ARRAY_SIZE(omap44xx_emif_fw_addrs), | |
151 | .user = OCP_USER_MPU, | |
55d2cb08 BC |
152 | }; |
153 | ||
154 | /* emif_fw slave ports */ | |
155 | static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = { | |
156 | &omap44xx_dmm__emif_fw, | |
157 | &omap44xx_l4_cfg__emif_fw, | |
158 | }; | |
159 | ||
160 | static struct omap_hwmod omap44xx_emif_fw_hwmod = { | |
161 | .name = "emif_fw", | |
162 | .class = &omap44xx_emif_fw_hwmod_class, | |
163 | .slaves = omap44xx_emif_fw_slaves, | |
164 | .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves), | |
165 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
166 | }; | |
167 | ||
168 | /* | |
169 | * 'l3' class | |
170 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 | |
171 | */ | |
172 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { | |
fe13471c | 173 | .name = "l3", |
55d2cb08 BC |
174 | }; |
175 | ||
176 | /* l3_instr interface data */ | |
8f25bdc5 BC |
177 | /* iva -> l3_instr */ |
178 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { | |
179 | .master = &omap44xx_iva_hwmod, | |
180 | .slave = &omap44xx_l3_instr_hwmod, | |
181 | .clk = "l3_div_ck", | |
182 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
183 | }; | |
184 | ||
55d2cb08 BC |
185 | /* l3_main_3 -> l3_instr */ |
186 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { | |
187 | .master = &omap44xx_l3_main_3_hwmod, | |
188 | .slave = &omap44xx_l3_instr_hwmod, | |
189 | .clk = "l3_div_ck", | |
190 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
191 | }; | |
192 | ||
193 | /* l3_instr slave ports */ | |
194 | static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = { | |
8f25bdc5 | 195 | &omap44xx_iva__l3_instr, |
55d2cb08 BC |
196 | &omap44xx_l3_main_3__l3_instr, |
197 | }; | |
198 | ||
199 | static struct omap_hwmod omap44xx_l3_instr_hwmod = { | |
200 | .name = "l3_instr", | |
201 | .class = &omap44xx_l3_hwmod_class, | |
202 | .slaves = omap44xx_l3_instr_slaves, | |
203 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves), | |
204 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
205 | }; | |
206 | ||
3b54baad | 207 | /* l3_main_1 interface data */ |
8f25bdc5 BC |
208 | /* dsp -> l3_main_1 */ |
209 | static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { | |
210 | .master = &omap44xx_dsp_hwmod, | |
211 | .slave = &omap44xx_l3_main_1_hwmod, | |
212 | .clk = "l3_div_ck", | |
213 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
214 | }; | |
215 | ||
55d2cb08 BC |
216 | /* l3_main_2 -> l3_main_1 */ |
217 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { | |
218 | .master = &omap44xx_l3_main_2_hwmod, | |
219 | .slave = &omap44xx_l3_main_1_hwmod, | |
220 | .clk = "l3_div_ck", | |
221 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
222 | }; | |
223 | ||
224 | /* l4_cfg -> l3_main_1 */ | |
225 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { | |
226 | .master = &omap44xx_l4_cfg_hwmod, | |
227 | .slave = &omap44xx_l3_main_1_hwmod, | |
228 | .clk = "l4_div_ck", | |
229 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
230 | }; | |
231 | ||
232 | /* mpu -> l3_main_1 */ | |
233 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { | |
234 | .master = &omap44xx_mpu_hwmod, | |
235 | .slave = &omap44xx_l3_main_1_hwmod, | |
236 | .clk = "l3_div_ck", | |
237 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
238 | }; | |
239 | ||
240 | /* l3_main_1 slave ports */ | |
241 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { | |
8f25bdc5 | 242 | &omap44xx_dsp__l3_main_1, |
55d2cb08 BC |
243 | &omap44xx_l3_main_2__l3_main_1, |
244 | &omap44xx_l4_cfg__l3_main_1, | |
245 | &omap44xx_mpu__l3_main_1, | |
246 | }; | |
247 | ||
248 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { | |
249 | .name = "l3_main_1", | |
250 | .class = &omap44xx_l3_hwmod_class, | |
251 | .slaves = omap44xx_l3_main_1_slaves, | |
252 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), | |
253 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
254 | }; | |
255 | ||
256 | /* l3_main_2 interface data */ | |
d7cf5f33 BC |
257 | /* dma_system -> l3_main_2 */ |
258 | static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { | |
259 | .master = &omap44xx_dma_system_hwmod, | |
260 | .slave = &omap44xx_l3_main_2_hwmod, | |
261 | .clk = "l3_div_ck", | |
262 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
263 | }; | |
264 | ||
8f25bdc5 BC |
265 | /* iva -> l3_main_2 */ |
266 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { | |
267 | .master = &omap44xx_iva_hwmod, | |
268 | .slave = &omap44xx_l3_main_2_hwmod, | |
269 | .clk = "l3_div_ck", | |
270 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
271 | }; | |
272 | ||
55d2cb08 BC |
273 | /* l3_main_1 -> l3_main_2 */ |
274 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { | |
275 | .master = &omap44xx_l3_main_1_hwmod, | |
276 | .slave = &omap44xx_l3_main_2_hwmod, | |
277 | .clk = "l3_div_ck", | |
278 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
279 | }; | |
280 | ||
281 | /* l4_cfg -> l3_main_2 */ | |
282 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { | |
283 | .master = &omap44xx_l4_cfg_hwmod, | |
284 | .slave = &omap44xx_l3_main_2_hwmod, | |
285 | .clk = "l4_div_ck", | |
286 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
287 | }; | |
288 | ||
289 | /* l3_main_2 slave ports */ | |
290 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { | |
531ce0d5 | 291 | &omap44xx_dma_system__l3_main_2, |
8f25bdc5 | 292 | &omap44xx_iva__l3_main_2, |
55d2cb08 BC |
293 | &omap44xx_l3_main_1__l3_main_2, |
294 | &omap44xx_l4_cfg__l3_main_2, | |
295 | }; | |
296 | ||
297 | static struct omap_hwmod omap44xx_l3_main_2_hwmod = { | |
298 | .name = "l3_main_2", | |
299 | .class = &omap44xx_l3_hwmod_class, | |
300 | .slaves = omap44xx_l3_main_2_slaves, | |
301 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves), | |
302 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
303 | }; | |
304 | ||
305 | /* l3_main_3 interface data */ | |
306 | /* l3_main_1 -> l3_main_3 */ | |
307 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { | |
308 | .master = &omap44xx_l3_main_1_hwmod, | |
309 | .slave = &omap44xx_l3_main_3_hwmod, | |
310 | .clk = "l3_div_ck", | |
311 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
312 | }; | |
313 | ||
314 | /* l3_main_2 -> l3_main_3 */ | |
315 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { | |
316 | .master = &omap44xx_l3_main_2_hwmod, | |
317 | .slave = &omap44xx_l3_main_3_hwmod, | |
318 | .clk = "l3_div_ck", | |
319 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
320 | }; | |
321 | ||
322 | /* l4_cfg -> l3_main_3 */ | |
323 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { | |
324 | .master = &omap44xx_l4_cfg_hwmod, | |
325 | .slave = &omap44xx_l3_main_3_hwmod, | |
326 | .clk = "l4_div_ck", | |
327 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
328 | }; | |
329 | ||
330 | /* l3_main_3 slave ports */ | |
331 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = { | |
332 | &omap44xx_l3_main_1__l3_main_3, | |
333 | &omap44xx_l3_main_2__l3_main_3, | |
334 | &omap44xx_l4_cfg__l3_main_3, | |
335 | }; | |
336 | ||
337 | static struct omap_hwmod omap44xx_l3_main_3_hwmod = { | |
338 | .name = "l3_main_3", | |
339 | .class = &omap44xx_l3_hwmod_class, | |
340 | .slaves = omap44xx_l3_main_3_slaves, | |
341 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves), | |
342 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
343 | }; | |
344 | ||
345 | /* | |
346 | * 'l4' class | |
347 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup | |
348 | */ | |
349 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { | |
fe13471c | 350 | .name = "l4", |
55d2cb08 BC |
351 | }; |
352 | ||
353 | /* l4_abe interface data */ | |
8f25bdc5 BC |
354 | /* dsp -> l4_abe */ |
355 | static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { | |
356 | .master = &omap44xx_dsp_hwmod, | |
357 | .slave = &omap44xx_l4_abe_hwmod, | |
358 | .clk = "ocp_abe_iclk", | |
359 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
360 | }; | |
361 | ||
55d2cb08 BC |
362 | /* l3_main_1 -> l4_abe */ |
363 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { | |
364 | .master = &omap44xx_l3_main_1_hwmod, | |
365 | .slave = &omap44xx_l4_abe_hwmod, | |
366 | .clk = "l3_div_ck", | |
367 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
368 | }; | |
369 | ||
370 | /* mpu -> l4_abe */ | |
371 | static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { | |
372 | .master = &omap44xx_mpu_hwmod, | |
373 | .slave = &omap44xx_l4_abe_hwmod, | |
374 | .clk = "ocp_abe_iclk", | |
375 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
376 | }; | |
377 | ||
378 | /* l4_abe slave ports */ | |
379 | static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { | |
8f25bdc5 | 380 | &omap44xx_dsp__l4_abe, |
55d2cb08 BC |
381 | &omap44xx_l3_main_1__l4_abe, |
382 | &omap44xx_mpu__l4_abe, | |
383 | }; | |
384 | ||
385 | static struct omap_hwmod omap44xx_l4_abe_hwmod = { | |
386 | .name = "l4_abe", | |
387 | .class = &omap44xx_l4_hwmod_class, | |
388 | .slaves = omap44xx_l4_abe_slaves, | |
389 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves), | |
390 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
391 | }; | |
392 | ||
393 | /* l4_cfg interface data */ | |
394 | /* l3_main_1 -> l4_cfg */ | |
395 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { | |
396 | .master = &omap44xx_l3_main_1_hwmod, | |
397 | .slave = &omap44xx_l4_cfg_hwmod, | |
398 | .clk = "l3_div_ck", | |
399 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
400 | }; | |
401 | ||
402 | /* l4_cfg slave ports */ | |
403 | static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = { | |
404 | &omap44xx_l3_main_1__l4_cfg, | |
405 | }; | |
406 | ||
407 | static struct omap_hwmod omap44xx_l4_cfg_hwmod = { | |
408 | .name = "l4_cfg", | |
409 | .class = &omap44xx_l4_hwmod_class, | |
410 | .slaves = omap44xx_l4_cfg_slaves, | |
411 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves), | |
412 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
413 | }; | |
414 | ||
415 | /* l4_per interface data */ | |
416 | /* l3_main_2 -> l4_per */ | |
417 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { | |
418 | .master = &omap44xx_l3_main_2_hwmod, | |
419 | .slave = &omap44xx_l4_per_hwmod, | |
420 | .clk = "l3_div_ck", | |
421 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
422 | }; | |
423 | ||
424 | /* l4_per slave ports */ | |
425 | static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = { | |
426 | &omap44xx_l3_main_2__l4_per, | |
427 | }; | |
428 | ||
429 | static struct omap_hwmod omap44xx_l4_per_hwmod = { | |
430 | .name = "l4_per", | |
431 | .class = &omap44xx_l4_hwmod_class, | |
432 | .slaves = omap44xx_l4_per_slaves, | |
433 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves), | |
434 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
435 | }; | |
436 | ||
437 | /* l4_wkup interface data */ | |
438 | /* l4_cfg -> l4_wkup */ | |
439 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { | |
440 | .master = &omap44xx_l4_cfg_hwmod, | |
441 | .slave = &omap44xx_l4_wkup_hwmod, | |
442 | .clk = "l4_div_ck", | |
443 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
444 | }; | |
445 | ||
446 | /* l4_wkup slave ports */ | |
447 | static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = { | |
448 | &omap44xx_l4_cfg__l4_wkup, | |
449 | }; | |
450 | ||
451 | static struct omap_hwmod omap44xx_l4_wkup_hwmod = { | |
452 | .name = "l4_wkup", | |
453 | .class = &omap44xx_l4_hwmod_class, | |
454 | .slaves = omap44xx_l4_wkup_slaves, | |
455 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves), | |
456 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
457 | }; | |
458 | ||
f776471f | 459 | /* |
3b54baad BC |
460 | * 'mpu_bus' class |
461 | * instance(s): mpu_private | |
f776471f | 462 | */ |
3b54baad | 463 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { |
fe13471c | 464 | .name = "mpu_bus", |
3b54baad | 465 | }; |
f776471f | 466 | |
3b54baad BC |
467 | /* mpu_private interface data */ |
468 | /* mpu -> mpu_private */ | |
469 | static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { | |
470 | .master = &omap44xx_mpu_hwmod, | |
471 | .slave = &omap44xx_mpu_private_hwmod, | |
472 | .clk = "l3_div_ck", | |
473 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
474 | }; | |
475 | ||
476 | /* mpu_private slave ports */ | |
477 | static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = { | |
478 | &omap44xx_mpu__mpu_private, | |
479 | }; | |
480 | ||
481 | static struct omap_hwmod omap44xx_mpu_private_hwmod = { | |
482 | .name = "mpu_private", | |
483 | .class = &omap44xx_mpu_bus_hwmod_class, | |
484 | .slaves = omap44xx_mpu_private_slaves, | |
485 | .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves), | |
486 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
487 | }; | |
488 | ||
489 | /* | |
490 | * Modules omap_hwmod structures | |
491 | * | |
492 | * The following IPs are excluded for the moment because: | |
493 | * - They do not need an explicit SW control using omap_hwmod API. | |
494 | * - They still need to be validated with the driver | |
495 | * properly adapted to omap_hwmod / omap_device | |
496 | * | |
497 | * aess | |
498 | * bandgap | |
499 | * c2c | |
500 | * c2c_target_fw | |
501 | * cm_core | |
502 | * cm_core_aon | |
503 | * counter_32k | |
504 | * ctrl_module_core | |
505 | * ctrl_module_pad_core | |
506 | * ctrl_module_pad_wkup | |
507 | * ctrl_module_wkup | |
508 | * debugss | |
3b54baad | 509 | * dmic |
3b54baad BC |
510 | * dss |
511 | * dss_dispc | |
512 | * dss_dsi1 | |
513 | * dss_dsi2 | |
514 | * dss_hdmi | |
515 | * dss_rfbi | |
516 | * dss_venc | |
517 | * efuse_ctrl_cust | |
518 | * efuse_ctrl_std | |
519 | * elm | |
520 | * emif1 | |
521 | * emif2 | |
522 | * fdif | |
523 | * gpmc | |
524 | * gpu | |
525 | * hdq1w | |
526 | * hsi | |
527 | * ipu | |
528 | * iss | |
3b54baad BC |
529 | * kbd |
530 | * mailbox | |
531 | * mcasp | |
532 | * mcbsp1 | |
533 | * mcbsp2 | |
534 | * mcbsp3 | |
535 | * mcbsp4 | |
536 | * mcpdm | |
3b54baad BC |
537 | * mmc1 |
538 | * mmc2 | |
539 | * mmc3 | |
540 | * mmc4 | |
541 | * mmc5 | |
542 | * mpu_c0 | |
543 | * mpu_c1 | |
544 | * ocmc_ram | |
545 | * ocp2scp_usb_phy | |
546 | * ocp_wp_noc | |
547 | * prcm | |
548 | * prcm_mpu | |
549 | * prm | |
550 | * scrm | |
551 | * sl2if | |
552 | * slimbus1 | |
553 | * slimbus2 | |
3b54baad BC |
554 | * timer1 |
555 | * timer10 | |
556 | * timer11 | |
557 | * timer2 | |
558 | * timer3 | |
559 | * timer4 | |
560 | * timer5 | |
561 | * timer6 | |
562 | * timer7 | |
563 | * timer8 | |
564 | * timer9 | |
565 | * usb_host_fs | |
566 | * usb_host_hs | |
567 | * usb_otg_hs | |
568 | * usb_phy_cm | |
569 | * usb_tll_hs | |
570 | * usim | |
571 | */ | |
572 | ||
d7cf5f33 BC |
573 | /* |
574 | * 'dma' class | |
575 | * dma controller for data exchange between memory to memory (i.e. internal or | |
576 | * external memory) and gp peripherals to memory or memory to gp peripherals | |
577 | */ | |
578 | ||
579 | static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { | |
580 | .rev_offs = 0x0000, | |
581 | .sysc_offs = 0x002c, | |
582 | .syss_offs = 0x0028, | |
583 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
584 | SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
585 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
586 | SYSS_HAS_RESET_STATUS), | |
587 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
588 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
589 | .sysc_fields = &omap_hwmod_sysc_type1, | |
590 | }; | |
591 | ||
592 | static struct omap_hwmod_class omap44xx_dma_hwmod_class = { | |
593 | .name = "dma", | |
594 | .sysc = &omap44xx_dma_sysc, | |
595 | }; | |
596 | ||
597 | /* dma dev_attr */ | |
598 | static struct omap_dma_dev_attr dma_dev_attr = { | |
599 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
600 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
601 | .lch_count = 32, | |
602 | }; | |
603 | ||
604 | /* dma_system */ | |
605 | static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { | |
606 | { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, | |
607 | { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, | |
608 | { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, | |
609 | { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, | |
610 | }; | |
611 | ||
612 | /* dma_system master ports */ | |
613 | static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = { | |
614 | &omap44xx_dma_system__l3_main_2, | |
615 | }; | |
616 | ||
617 | static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { | |
618 | { | |
619 | .pa_start = 0x4a056000, | |
620 | .pa_end = 0x4a0560ff, | |
621 | .flags = ADDR_TYPE_RT | |
622 | }, | |
623 | }; | |
624 | ||
625 | /* l4_cfg -> dma_system */ | |
626 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { | |
627 | .master = &omap44xx_l4_cfg_hwmod, | |
628 | .slave = &omap44xx_dma_system_hwmod, | |
629 | .clk = "l4_div_ck", | |
630 | .addr = omap44xx_dma_system_addrs, | |
631 | .addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs), | |
632 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
633 | }; | |
634 | ||
635 | /* dma_system slave ports */ | |
636 | static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = { | |
637 | &omap44xx_l4_cfg__dma_system, | |
638 | }; | |
639 | ||
640 | static struct omap_hwmod omap44xx_dma_system_hwmod = { | |
641 | .name = "dma_system", | |
642 | .class = &omap44xx_dma_hwmod_class, | |
643 | .mpu_irqs = omap44xx_dma_system_irqs, | |
644 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs), | |
645 | .main_clk = "l3_div_ck", | |
646 | .prcm = { | |
647 | .omap4 = { | |
648 | .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL, | |
649 | }, | |
650 | }, | |
651 | .dev_attr = &dma_dev_attr, | |
652 | .slaves = omap44xx_dma_system_slaves, | |
653 | .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves), | |
654 | .masters = omap44xx_dma_system_masters, | |
655 | .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters), | |
656 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
657 | }; | |
658 | ||
8f25bdc5 BC |
659 | /* |
660 | * 'dsp' class | |
661 | * dsp sub-system | |
662 | */ | |
663 | ||
664 | static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { | |
fe13471c | 665 | .name = "dsp", |
8f25bdc5 BC |
666 | }; |
667 | ||
668 | /* dsp */ | |
669 | static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { | |
670 | { .irq = 28 + OMAP44XX_IRQ_GIC_START }, | |
671 | }; | |
672 | ||
673 | static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { | |
674 | { .name = "mmu_cache", .rst_shift = 1 }, | |
675 | }; | |
676 | ||
677 | static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = { | |
678 | { .name = "dsp", .rst_shift = 0 }, | |
679 | }; | |
680 | ||
681 | /* dsp -> iva */ | |
682 | static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { | |
683 | .master = &omap44xx_dsp_hwmod, | |
684 | .slave = &omap44xx_iva_hwmod, | |
685 | .clk = "dpll_iva_m5x2_ck", | |
686 | }; | |
687 | ||
688 | /* dsp master ports */ | |
689 | static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = { | |
690 | &omap44xx_dsp__l3_main_1, | |
691 | &omap44xx_dsp__l4_abe, | |
692 | &omap44xx_dsp__iva, | |
693 | }; | |
694 | ||
695 | /* l4_cfg -> dsp */ | |
696 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { | |
697 | .master = &omap44xx_l4_cfg_hwmod, | |
698 | .slave = &omap44xx_dsp_hwmod, | |
699 | .clk = "l4_div_ck", | |
700 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
701 | }; | |
702 | ||
703 | /* dsp slave ports */ | |
704 | static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = { | |
705 | &omap44xx_l4_cfg__dsp, | |
706 | }; | |
707 | ||
708 | /* Pseudo hwmod for reset control purpose only */ | |
709 | static struct omap_hwmod omap44xx_dsp_c0_hwmod = { | |
710 | .name = "dsp_c0", | |
711 | .class = &omap44xx_dsp_hwmod_class, | |
712 | .flags = HWMOD_INIT_NO_RESET, | |
713 | .rst_lines = omap44xx_dsp_c0_resets, | |
714 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets), | |
715 | .prcm = { | |
716 | .omap4 = { | |
717 | .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL, | |
718 | }, | |
719 | }, | |
720 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
721 | }; | |
722 | ||
723 | static struct omap_hwmod omap44xx_dsp_hwmod = { | |
724 | .name = "dsp", | |
725 | .class = &omap44xx_dsp_hwmod_class, | |
726 | .mpu_irqs = omap44xx_dsp_irqs, | |
727 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dsp_irqs), | |
728 | .rst_lines = omap44xx_dsp_resets, | |
729 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), | |
730 | .main_clk = "dsp_fck", | |
731 | .prcm = { | |
732 | .omap4 = { | |
733 | .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, | |
734 | .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL, | |
735 | }, | |
736 | }, | |
737 | .slaves = omap44xx_dsp_slaves, | |
738 | .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves), | |
739 | .masters = omap44xx_dsp_masters, | |
740 | .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters), | |
741 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
742 | }; | |
743 | ||
3b54baad BC |
744 | /* |
745 | * 'gpio' class | |
746 | * general purpose io module | |
747 | */ | |
748 | ||
749 | static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { | |
750 | .rev_offs = 0x0000, | |
f776471f | 751 | .sysc_offs = 0x0010, |
3b54baad | 752 | .syss_offs = 0x0114, |
0cfe8751 BC |
753 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
754 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
755 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
756 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
757 | SIDLE_SMART_WKUP), | |
f776471f BC |
758 | .sysc_fields = &omap_hwmod_sysc_type1, |
759 | }; | |
760 | ||
3b54baad | 761 | static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { |
fe13471c BC |
762 | .name = "gpio", |
763 | .sysc = &omap44xx_gpio_sysc, | |
764 | .rev = 2, | |
f776471f BC |
765 | }; |
766 | ||
3b54baad BC |
767 | /* gpio dev_attr */ |
768 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
fe13471c BC |
769 | .bank_width = 32, |
770 | .dbck_flag = true, | |
f776471f BC |
771 | }; |
772 | ||
3b54baad BC |
773 | /* gpio1 */ |
774 | static struct omap_hwmod omap44xx_gpio1_hwmod; | |
775 | static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { | |
776 | { .irq = 29 + OMAP44XX_IRQ_GIC_START }, | |
f776471f BC |
777 | }; |
778 | ||
3b54baad | 779 | static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { |
f776471f | 780 | { |
3b54baad BC |
781 | .pa_start = 0x4a310000, |
782 | .pa_end = 0x4a3101ff, | |
f776471f BC |
783 | .flags = ADDR_TYPE_RT |
784 | }, | |
785 | }; | |
786 | ||
3b54baad BC |
787 | /* l4_wkup -> gpio1 */ |
788 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { | |
789 | .master = &omap44xx_l4_wkup_hwmod, | |
790 | .slave = &omap44xx_gpio1_hwmod, | |
b399bca8 | 791 | .clk = "l4_wkup_clk_mux_ck", |
3b54baad BC |
792 | .addr = omap44xx_gpio1_addrs, |
793 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs), | |
f776471f BC |
794 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
795 | }; | |
796 | ||
3b54baad BC |
797 | /* gpio1 slave ports */ |
798 | static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = { | |
799 | &omap44xx_l4_wkup__gpio1, | |
f776471f BC |
800 | }; |
801 | ||
3b54baad | 802 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
b399bca8 | 803 | { .role = "dbclk", .clk = "gpio1_dbclk" }, |
3b54baad BC |
804 | }; |
805 | ||
806 | static struct omap_hwmod omap44xx_gpio1_hwmod = { | |
807 | .name = "gpio1", | |
808 | .class = &omap44xx_gpio_hwmod_class, | |
809 | .mpu_irqs = omap44xx_gpio1_irqs, | |
810 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs), | |
811 | .main_clk = "gpio1_ick", | |
f776471f BC |
812 | .prcm = { |
813 | .omap4 = { | |
3b54baad | 814 | .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, |
f776471f BC |
815 | }, |
816 | }, | |
3b54baad BC |
817 | .opt_clks = gpio1_opt_clks, |
818 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
819 | .dev_attr = &gpio_dev_attr, | |
820 | .slaves = omap44xx_gpio1_slaves, | |
821 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves), | |
f776471f BC |
822 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
823 | }; | |
824 | ||
3b54baad BC |
825 | /* gpio2 */ |
826 | static struct omap_hwmod omap44xx_gpio2_hwmod; | |
827 | static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { | |
828 | { .irq = 30 + OMAP44XX_IRQ_GIC_START }, | |
f776471f BC |
829 | }; |
830 | ||
3b54baad | 831 | static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { |
f776471f | 832 | { |
3b54baad BC |
833 | .pa_start = 0x48055000, |
834 | .pa_end = 0x480551ff, | |
f776471f BC |
835 | .flags = ADDR_TYPE_RT |
836 | }, | |
837 | }; | |
838 | ||
3b54baad BC |
839 | /* l4_per -> gpio2 */ |
840 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { | |
f776471f | 841 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 842 | .slave = &omap44xx_gpio2_hwmod, |
b399bca8 | 843 | .clk = "l4_div_ck", |
3b54baad BC |
844 | .addr = omap44xx_gpio2_addrs, |
845 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs), | |
f776471f BC |
846 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
847 | }; | |
848 | ||
3b54baad BC |
849 | /* gpio2 slave ports */ |
850 | static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = { | |
851 | &omap44xx_l4_per__gpio2, | |
f776471f BC |
852 | }; |
853 | ||
3b54baad | 854 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
b399bca8 | 855 | { .role = "dbclk", .clk = "gpio2_dbclk" }, |
3b54baad BC |
856 | }; |
857 | ||
858 | static struct omap_hwmod omap44xx_gpio2_hwmod = { | |
859 | .name = "gpio2", | |
860 | .class = &omap44xx_gpio_hwmod_class, | |
b399bca8 | 861 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad BC |
862 | .mpu_irqs = omap44xx_gpio2_irqs, |
863 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs), | |
864 | .main_clk = "gpio2_ick", | |
f776471f BC |
865 | .prcm = { |
866 | .omap4 = { | |
3b54baad | 867 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, |
f776471f BC |
868 | }, |
869 | }, | |
3b54baad BC |
870 | .opt_clks = gpio2_opt_clks, |
871 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
872 | .dev_attr = &gpio_dev_attr, | |
873 | .slaves = omap44xx_gpio2_slaves, | |
874 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves), | |
f776471f BC |
875 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
876 | }; | |
877 | ||
3b54baad BC |
878 | /* gpio3 */ |
879 | static struct omap_hwmod omap44xx_gpio3_hwmod; | |
880 | static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { | |
881 | { .irq = 31 + OMAP44XX_IRQ_GIC_START }, | |
f776471f BC |
882 | }; |
883 | ||
3b54baad | 884 | static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { |
f776471f | 885 | { |
3b54baad BC |
886 | .pa_start = 0x48057000, |
887 | .pa_end = 0x480571ff, | |
f776471f BC |
888 | .flags = ADDR_TYPE_RT |
889 | }, | |
890 | }; | |
891 | ||
3b54baad BC |
892 | /* l4_per -> gpio3 */ |
893 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { | |
f776471f | 894 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 895 | .slave = &omap44xx_gpio3_hwmod, |
b399bca8 | 896 | .clk = "l4_div_ck", |
3b54baad BC |
897 | .addr = omap44xx_gpio3_addrs, |
898 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs), | |
f776471f BC |
899 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
900 | }; | |
901 | ||
3b54baad BC |
902 | /* gpio3 slave ports */ |
903 | static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = { | |
904 | &omap44xx_l4_per__gpio3, | |
f776471f BC |
905 | }; |
906 | ||
3b54baad | 907 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
b399bca8 | 908 | { .role = "dbclk", .clk = "gpio3_dbclk" }, |
3b54baad BC |
909 | }; |
910 | ||
911 | static struct omap_hwmod omap44xx_gpio3_hwmod = { | |
912 | .name = "gpio3", | |
913 | .class = &omap44xx_gpio_hwmod_class, | |
b399bca8 | 914 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad BC |
915 | .mpu_irqs = omap44xx_gpio3_irqs, |
916 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs), | |
917 | .main_clk = "gpio3_ick", | |
f776471f BC |
918 | .prcm = { |
919 | .omap4 = { | |
3b54baad | 920 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, |
f776471f BC |
921 | }, |
922 | }, | |
3b54baad BC |
923 | .opt_clks = gpio3_opt_clks, |
924 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
925 | .dev_attr = &gpio_dev_attr, | |
926 | .slaves = omap44xx_gpio3_slaves, | |
927 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves), | |
f776471f BC |
928 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
929 | }; | |
930 | ||
3b54baad BC |
931 | /* gpio4 */ |
932 | static struct omap_hwmod omap44xx_gpio4_hwmod; | |
933 | static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { | |
934 | { .irq = 32 + OMAP44XX_IRQ_GIC_START }, | |
f776471f BC |
935 | }; |
936 | ||
3b54baad | 937 | static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { |
f776471f | 938 | { |
3b54baad BC |
939 | .pa_start = 0x48059000, |
940 | .pa_end = 0x480591ff, | |
f776471f BC |
941 | .flags = ADDR_TYPE_RT |
942 | }, | |
943 | }; | |
944 | ||
3b54baad BC |
945 | /* l4_per -> gpio4 */ |
946 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { | |
f776471f | 947 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 948 | .slave = &omap44xx_gpio4_hwmod, |
b399bca8 | 949 | .clk = "l4_div_ck", |
3b54baad BC |
950 | .addr = omap44xx_gpio4_addrs, |
951 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs), | |
f776471f BC |
952 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
953 | }; | |
954 | ||
3b54baad BC |
955 | /* gpio4 slave ports */ |
956 | static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = { | |
957 | &omap44xx_l4_per__gpio4, | |
f776471f BC |
958 | }; |
959 | ||
3b54baad | 960 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { |
b399bca8 | 961 | { .role = "dbclk", .clk = "gpio4_dbclk" }, |
3b54baad BC |
962 | }; |
963 | ||
964 | static struct omap_hwmod omap44xx_gpio4_hwmod = { | |
965 | .name = "gpio4", | |
966 | .class = &omap44xx_gpio_hwmod_class, | |
b399bca8 | 967 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad BC |
968 | .mpu_irqs = omap44xx_gpio4_irqs, |
969 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs), | |
970 | .main_clk = "gpio4_ick", | |
f776471f BC |
971 | .prcm = { |
972 | .omap4 = { | |
3b54baad | 973 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, |
f776471f BC |
974 | }, |
975 | }, | |
3b54baad BC |
976 | .opt_clks = gpio4_opt_clks, |
977 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
978 | .dev_attr = &gpio_dev_attr, | |
979 | .slaves = omap44xx_gpio4_slaves, | |
980 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves), | |
f776471f BC |
981 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
982 | }; | |
983 | ||
3b54baad BC |
984 | /* gpio5 */ |
985 | static struct omap_hwmod omap44xx_gpio5_hwmod; | |
986 | static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { | |
987 | { .irq = 33 + OMAP44XX_IRQ_GIC_START }, | |
55d2cb08 BC |
988 | }; |
989 | ||
3b54baad BC |
990 | static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { |
991 | { | |
992 | .pa_start = 0x4805b000, | |
993 | .pa_end = 0x4805b1ff, | |
994 | .flags = ADDR_TYPE_RT | |
995 | }, | |
55d2cb08 BC |
996 | }; |
997 | ||
3b54baad BC |
998 | /* l4_per -> gpio5 */ |
999 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { | |
1000 | .master = &omap44xx_l4_per_hwmod, | |
1001 | .slave = &omap44xx_gpio5_hwmod, | |
b399bca8 | 1002 | .clk = "l4_div_ck", |
3b54baad BC |
1003 | .addr = omap44xx_gpio5_addrs, |
1004 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs), | |
1005 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
55d2cb08 BC |
1006 | }; |
1007 | ||
3b54baad BC |
1008 | /* gpio5 slave ports */ |
1009 | static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = { | |
1010 | &omap44xx_l4_per__gpio5, | |
55d2cb08 BC |
1011 | }; |
1012 | ||
3b54baad | 1013 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
b399bca8 | 1014 | { .role = "dbclk", .clk = "gpio5_dbclk" }, |
55d2cb08 BC |
1015 | }; |
1016 | ||
3b54baad BC |
1017 | static struct omap_hwmod omap44xx_gpio5_hwmod = { |
1018 | .name = "gpio5", | |
1019 | .class = &omap44xx_gpio_hwmod_class, | |
b399bca8 | 1020 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad BC |
1021 | .mpu_irqs = omap44xx_gpio5_irqs, |
1022 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs), | |
1023 | .main_clk = "gpio5_ick", | |
55d2cb08 BC |
1024 | .prcm = { |
1025 | .omap4 = { | |
3b54baad | 1026 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, |
55d2cb08 BC |
1027 | }, |
1028 | }, | |
3b54baad BC |
1029 | .opt_clks = gpio5_opt_clks, |
1030 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
1031 | .dev_attr = &gpio_dev_attr, | |
1032 | .slaves = omap44xx_gpio5_slaves, | |
1033 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves), | |
55d2cb08 BC |
1034 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1035 | }; | |
1036 | ||
3b54baad BC |
1037 | /* gpio6 */ |
1038 | static struct omap_hwmod omap44xx_gpio6_hwmod; | |
1039 | static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { | |
1040 | { .irq = 34 + OMAP44XX_IRQ_GIC_START }, | |
92b18d1c BC |
1041 | }; |
1042 | ||
3b54baad | 1043 | static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { |
92b18d1c | 1044 | { |
3b54baad BC |
1045 | .pa_start = 0x4805d000, |
1046 | .pa_end = 0x4805d1ff, | |
92b18d1c BC |
1047 | .flags = ADDR_TYPE_RT |
1048 | }, | |
1049 | }; | |
1050 | ||
3b54baad BC |
1051 | /* l4_per -> gpio6 */ |
1052 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { | |
1053 | .master = &omap44xx_l4_per_hwmod, | |
1054 | .slave = &omap44xx_gpio6_hwmod, | |
b399bca8 | 1055 | .clk = "l4_div_ck", |
3b54baad BC |
1056 | .addr = omap44xx_gpio6_addrs, |
1057 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs), | |
1058 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
db12ba53 BC |
1059 | }; |
1060 | ||
3b54baad BC |
1061 | /* gpio6 slave ports */ |
1062 | static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = { | |
1063 | &omap44xx_l4_per__gpio6, | |
db12ba53 BC |
1064 | }; |
1065 | ||
3b54baad | 1066 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
b399bca8 | 1067 | { .role = "dbclk", .clk = "gpio6_dbclk" }, |
db12ba53 BC |
1068 | }; |
1069 | ||
3b54baad BC |
1070 | static struct omap_hwmod omap44xx_gpio6_hwmod = { |
1071 | .name = "gpio6", | |
1072 | .class = &omap44xx_gpio_hwmod_class, | |
b399bca8 | 1073 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad BC |
1074 | .mpu_irqs = omap44xx_gpio6_irqs, |
1075 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs), | |
1076 | .main_clk = "gpio6_ick", | |
1077 | .prcm = { | |
1078 | .omap4 = { | |
1079 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, | |
1080 | }, | |
db12ba53 | 1081 | }, |
3b54baad BC |
1082 | .opt_clks = gpio6_opt_clks, |
1083 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
1084 | .dev_attr = &gpio_dev_attr, | |
1085 | .slaves = omap44xx_gpio6_slaves, | |
1086 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves), | |
1087 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
db12ba53 BC |
1088 | }; |
1089 | ||
3b54baad BC |
1090 | /* |
1091 | * 'i2c' class | |
1092 | * multimaster high-speed i2c controller | |
1093 | */ | |
db12ba53 | 1094 | |
3b54baad BC |
1095 | static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { |
1096 | .sysc_offs = 0x0010, | |
1097 | .syss_offs = 0x0090, | |
1098 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1099 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 1100 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
1101 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1102 | SIDLE_SMART_WKUP), | |
3b54baad | 1103 | .sysc_fields = &omap_hwmod_sysc_type1, |
db12ba53 BC |
1104 | }; |
1105 | ||
3b54baad | 1106 | static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { |
fe13471c BC |
1107 | .name = "i2c", |
1108 | .sysc = &omap44xx_i2c_sysc, | |
db12ba53 BC |
1109 | }; |
1110 | ||
3b54baad BC |
1111 | /* i2c1 */ |
1112 | static struct omap_hwmod omap44xx_i2c1_hwmod; | |
1113 | static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { | |
1114 | { .irq = 56 + OMAP44XX_IRQ_GIC_START }, | |
db12ba53 BC |
1115 | }; |
1116 | ||
3b54baad BC |
1117 | static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { |
1118 | { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, | |
1119 | { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, | |
db12ba53 BC |
1120 | }; |
1121 | ||
3b54baad | 1122 | static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { |
db12ba53 | 1123 | { |
3b54baad BC |
1124 | .pa_start = 0x48070000, |
1125 | .pa_end = 0x480700ff, | |
db12ba53 BC |
1126 | .flags = ADDR_TYPE_RT |
1127 | }, | |
1128 | }; | |
1129 | ||
3b54baad BC |
1130 | /* l4_per -> i2c1 */ |
1131 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { | |
1132 | .master = &omap44xx_l4_per_hwmod, | |
1133 | .slave = &omap44xx_i2c1_hwmod, | |
1134 | .clk = "l4_div_ck", | |
1135 | .addr = omap44xx_i2c1_addrs, | |
1136 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs), | |
92b18d1c BC |
1137 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1138 | }; | |
1139 | ||
3b54baad BC |
1140 | /* i2c1 slave ports */ |
1141 | static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = { | |
1142 | &omap44xx_l4_per__i2c1, | |
92b18d1c BC |
1143 | }; |
1144 | ||
3b54baad BC |
1145 | static struct omap_hwmod omap44xx_i2c1_hwmod = { |
1146 | .name = "i2c1", | |
1147 | .class = &omap44xx_i2c_hwmod_class, | |
1148 | .flags = HWMOD_INIT_NO_RESET, | |
1149 | .mpu_irqs = omap44xx_i2c1_irqs, | |
1150 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs), | |
1151 | .sdma_reqs = omap44xx_i2c1_sdma_reqs, | |
1152 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs), | |
1153 | .main_clk = "i2c1_fck", | |
92b18d1c BC |
1154 | .prcm = { |
1155 | .omap4 = { | |
3b54baad | 1156 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, |
92b18d1c BC |
1157 | }, |
1158 | }, | |
3b54baad BC |
1159 | .slaves = omap44xx_i2c1_slaves, |
1160 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves), | |
92b18d1c BC |
1161 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1162 | }; | |
1163 | ||
3b54baad BC |
1164 | /* i2c2 */ |
1165 | static struct omap_hwmod omap44xx_i2c2_hwmod; | |
1166 | static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { | |
1167 | { .irq = 57 + OMAP44XX_IRQ_GIC_START }, | |
92b18d1c BC |
1168 | }; |
1169 | ||
3b54baad BC |
1170 | static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { |
1171 | { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, | |
1172 | { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, | |
1173 | }; | |
1174 | ||
1175 | static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { | |
92b18d1c | 1176 | { |
3b54baad BC |
1177 | .pa_start = 0x48072000, |
1178 | .pa_end = 0x480720ff, | |
92b18d1c BC |
1179 | .flags = ADDR_TYPE_RT |
1180 | }, | |
1181 | }; | |
1182 | ||
3b54baad BC |
1183 | /* l4_per -> i2c2 */ |
1184 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { | |
db12ba53 | 1185 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 1186 | .slave = &omap44xx_i2c2_hwmod, |
db12ba53 | 1187 | .clk = "l4_div_ck", |
3b54baad BC |
1188 | .addr = omap44xx_i2c2_addrs, |
1189 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs), | |
db12ba53 BC |
1190 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1191 | }; | |
1192 | ||
3b54baad BC |
1193 | /* i2c2 slave ports */ |
1194 | static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = { | |
1195 | &omap44xx_l4_per__i2c2, | |
db12ba53 BC |
1196 | }; |
1197 | ||
3b54baad BC |
1198 | static struct omap_hwmod omap44xx_i2c2_hwmod = { |
1199 | .name = "i2c2", | |
1200 | .class = &omap44xx_i2c_hwmod_class, | |
1201 | .flags = HWMOD_INIT_NO_RESET, | |
1202 | .mpu_irqs = omap44xx_i2c2_irqs, | |
1203 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs), | |
1204 | .sdma_reqs = omap44xx_i2c2_sdma_reqs, | |
1205 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs), | |
1206 | .main_clk = "i2c2_fck", | |
db12ba53 BC |
1207 | .prcm = { |
1208 | .omap4 = { | |
3b54baad | 1209 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, |
db12ba53 BC |
1210 | }, |
1211 | }, | |
3b54baad BC |
1212 | .slaves = omap44xx_i2c2_slaves, |
1213 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves), | |
db12ba53 BC |
1214 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1215 | }; | |
1216 | ||
3b54baad BC |
1217 | /* i2c3 */ |
1218 | static struct omap_hwmod omap44xx_i2c3_hwmod; | |
1219 | static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { | |
1220 | { .irq = 61 + OMAP44XX_IRQ_GIC_START }, | |
db12ba53 BC |
1221 | }; |
1222 | ||
3b54baad BC |
1223 | static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { |
1224 | { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, | |
1225 | { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, | |
92b18d1c BC |
1226 | }; |
1227 | ||
3b54baad | 1228 | static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { |
92b18d1c | 1229 | { |
3b54baad BC |
1230 | .pa_start = 0x48060000, |
1231 | .pa_end = 0x480600ff, | |
92b18d1c BC |
1232 | .flags = ADDR_TYPE_RT |
1233 | }, | |
1234 | }; | |
1235 | ||
3b54baad BC |
1236 | /* l4_per -> i2c3 */ |
1237 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { | |
db12ba53 | 1238 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 1239 | .slave = &omap44xx_i2c3_hwmod, |
db12ba53 | 1240 | .clk = "l4_div_ck", |
3b54baad BC |
1241 | .addr = omap44xx_i2c3_addrs, |
1242 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs), | |
db12ba53 BC |
1243 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1244 | }; | |
1245 | ||
3b54baad BC |
1246 | /* i2c3 slave ports */ |
1247 | static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = { | |
1248 | &omap44xx_l4_per__i2c3, | |
db12ba53 BC |
1249 | }; |
1250 | ||
3b54baad BC |
1251 | static struct omap_hwmod omap44xx_i2c3_hwmod = { |
1252 | .name = "i2c3", | |
1253 | .class = &omap44xx_i2c_hwmod_class, | |
1254 | .flags = HWMOD_INIT_NO_RESET, | |
1255 | .mpu_irqs = omap44xx_i2c3_irqs, | |
1256 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs), | |
1257 | .sdma_reqs = omap44xx_i2c3_sdma_reqs, | |
1258 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs), | |
1259 | .main_clk = "i2c3_fck", | |
db12ba53 BC |
1260 | .prcm = { |
1261 | .omap4 = { | |
3b54baad | 1262 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, |
db12ba53 BC |
1263 | }, |
1264 | }, | |
3b54baad BC |
1265 | .slaves = omap44xx_i2c3_slaves, |
1266 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves), | |
db12ba53 BC |
1267 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1268 | }; | |
1269 | ||
3b54baad BC |
1270 | /* i2c4 */ |
1271 | static struct omap_hwmod omap44xx_i2c4_hwmod; | |
1272 | static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { | |
1273 | { .irq = 62 + OMAP44XX_IRQ_GIC_START }, | |
db12ba53 BC |
1274 | }; |
1275 | ||
3b54baad BC |
1276 | static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { |
1277 | { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, | |
1278 | { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, | |
db12ba53 BC |
1279 | }; |
1280 | ||
3b54baad | 1281 | static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { |
db12ba53 | 1282 | { |
3b54baad BC |
1283 | .pa_start = 0x48350000, |
1284 | .pa_end = 0x483500ff, | |
db12ba53 BC |
1285 | .flags = ADDR_TYPE_RT |
1286 | }, | |
1287 | }; | |
1288 | ||
3b54baad BC |
1289 | /* l4_per -> i2c4 */ |
1290 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { | |
1291 | .master = &omap44xx_l4_per_hwmod, | |
1292 | .slave = &omap44xx_i2c4_hwmod, | |
1293 | .clk = "l4_div_ck", | |
1294 | .addr = omap44xx_i2c4_addrs, | |
1295 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs), | |
1296 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
92b18d1c BC |
1297 | }; |
1298 | ||
3b54baad BC |
1299 | /* i2c4 slave ports */ |
1300 | static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = { | |
1301 | &omap44xx_l4_per__i2c4, | |
92b18d1c BC |
1302 | }; |
1303 | ||
3b54baad BC |
1304 | static struct omap_hwmod omap44xx_i2c4_hwmod = { |
1305 | .name = "i2c4", | |
1306 | .class = &omap44xx_i2c_hwmod_class, | |
1307 | .flags = HWMOD_INIT_NO_RESET, | |
1308 | .mpu_irqs = omap44xx_i2c4_irqs, | |
1309 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs), | |
1310 | .sdma_reqs = omap44xx_i2c4_sdma_reqs, | |
1311 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs), | |
1312 | .main_clk = "i2c4_fck", | |
92b18d1c BC |
1313 | .prcm = { |
1314 | .omap4 = { | |
3b54baad | 1315 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, |
92b18d1c BC |
1316 | }, |
1317 | }, | |
3b54baad BC |
1318 | .slaves = omap44xx_i2c4_slaves, |
1319 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves), | |
92b18d1c BC |
1320 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1321 | }; | |
1322 | ||
8f25bdc5 BC |
1323 | /* |
1324 | * 'iva' class | |
1325 | * multi-standard video encoder/decoder hardware accelerator | |
1326 | */ | |
1327 | ||
1328 | static struct omap_hwmod_class omap44xx_iva_hwmod_class = { | |
fe13471c | 1329 | .name = "iva", |
8f25bdc5 BC |
1330 | }; |
1331 | ||
1332 | /* iva */ | |
1333 | static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { | |
1334 | { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, | |
1335 | { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, | |
1336 | { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, | |
1337 | }; | |
1338 | ||
1339 | static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { | |
1340 | { .name = "logic", .rst_shift = 2 }, | |
1341 | }; | |
1342 | ||
1343 | static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = { | |
1344 | { .name = "seq0", .rst_shift = 0 }, | |
1345 | }; | |
1346 | ||
1347 | static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = { | |
1348 | { .name = "seq1", .rst_shift = 1 }, | |
1349 | }; | |
1350 | ||
1351 | /* iva master ports */ | |
1352 | static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = { | |
1353 | &omap44xx_iva__l3_main_2, | |
1354 | &omap44xx_iva__l3_instr, | |
1355 | }; | |
1356 | ||
1357 | static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { | |
1358 | { | |
1359 | .pa_start = 0x5a000000, | |
1360 | .pa_end = 0x5a07ffff, | |
1361 | .flags = ADDR_TYPE_RT | |
1362 | }, | |
1363 | }; | |
1364 | ||
1365 | /* l3_main_2 -> iva */ | |
1366 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { | |
1367 | .master = &omap44xx_l3_main_2_hwmod, | |
1368 | .slave = &omap44xx_iva_hwmod, | |
1369 | .clk = "l3_div_ck", | |
1370 | .addr = omap44xx_iva_addrs, | |
1371 | .addr_cnt = ARRAY_SIZE(omap44xx_iva_addrs), | |
1372 | .user = OCP_USER_MPU, | |
1373 | }; | |
1374 | ||
1375 | /* iva slave ports */ | |
1376 | static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = { | |
1377 | &omap44xx_dsp__iva, | |
1378 | &omap44xx_l3_main_2__iva, | |
1379 | }; | |
1380 | ||
1381 | /* Pseudo hwmod for reset control purpose only */ | |
1382 | static struct omap_hwmod omap44xx_iva_seq0_hwmod = { | |
1383 | .name = "iva_seq0", | |
1384 | .class = &omap44xx_iva_hwmod_class, | |
1385 | .flags = HWMOD_INIT_NO_RESET, | |
1386 | .rst_lines = omap44xx_iva_seq0_resets, | |
1387 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets), | |
1388 | .prcm = { | |
1389 | .omap4 = { | |
1390 | .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, | |
1391 | }, | |
1392 | }, | |
1393 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
1394 | }; | |
1395 | ||
1396 | /* Pseudo hwmod for reset control purpose only */ | |
1397 | static struct omap_hwmod omap44xx_iva_seq1_hwmod = { | |
1398 | .name = "iva_seq1", | |
1399 | .class = &omap44xx_iva_hwmod_class, | |
1400 | .flags = HWMOD_INIT_NO_RESET, | |
1401 | .rst_lines = omap44xx_iva_seq1_resets, | |
1402 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets), | |
1403 | .prcm = { | |
1404 | .omap4 = { | |
1405 | .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, | |
1406 | }, | |
1407 | }, | |
1408 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
1409 | }; | |
1410 | ||
1411 | static struct omap_hwmod omap44xx_iva_hwmod = { | |
1412 | .name = "iva", | |
1413 | .class = &omap44xx_iva_hwmod_class, | |
1414 | .mpu_irqs = omap44xx_iva_irqs, | |
1415 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iva_irqs), | |
1416 | .rst_lines = omap44xx_iva_resets, | |
1417 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), | |
1418 | .main_clk = "iva_fck", | |
1419 | .prcm = { | |
1420 | .omap4 = { | |
1421 | .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, | |
1422 | .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, | |
1423 | }, | |
1424 | }, | |
1425 | .slaves = omap44xx_iva_slaves, | |
1426 | .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves), | |
1427 | .masters = omap44xx_iva_masters, | |
1428 | .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters), | |
1429 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
1430 | }; | |
1431 | ||
9bcbd7f0 BC |
1432 | /* |
1433 | * 'mcspi' class | |
1434 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
1435 | * bus | |
1436 | */ | |
1437 | ||
1438 | static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = { | |
1439 | .rev_offs = 0x0000, | |
1440 | .sysc_offs = 0x0010, | |
1441 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
1442 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1443 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1444 | SIDLE_SMART_WKUP), | |
1445 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1446 | }; | |
1447 | ||
1448 | static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { | |
1449 | .name = "mcspi", | |
1450 | .sysc = &omap44xx_mcspi_sysc, | |
1451 | }; | |
1452 | ||
1453 | /* mcspi1 */ | |
1454 | static struct omap_hwmod omap44xx_mcspi1_hwmod; | |
1455 | static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { | |
1456 | { .irq = 65 + OMAP44XX_IRQ_GIC_START }, | |
1457 | }; | |
1458 | ||
1459 | static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { | |
1460 | { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, | |
1461 | { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, | |
1462 | { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START }, | |
1463 | { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START }, | |
1464 | { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START }, | |
1465 | { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, | |
1466 | { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, | |
1467 | { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, | |
1468 | }; | |
1469 | ||
1470 | static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { | |
1471 | { | |
1472 | .pa_start = 0x48098000, | |
1473 | .pa_end = 0x480981ff, | |
1474 | .flags = ADDR_TYPE_RT | |
1475 | }, | |
1476 | }; | |
1477 | ||
1478 | /* l4_per -> mcspi1 */ | |
1479 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { | |
1480 | .master = &omap44xx_l4_per_hwmod, | |
1481 | .slave = &omap44xx_mcspi1_hwmod, | |
1482 | .clk = "l4_div_ck", | |
1483 | .addr = omap44xx_mcspi1_addrs, | |
1484 | .addr_cnt = ARRAY_SIZE(omap44xx_mcspi1_addrs), | |
1485 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1486 | }; | |
1487 | ||
1488 | /* mcspi1 slave ports */ | |
1489 | static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = { | |
1490 | &omap44xx_l4_per__mcspi1, | |
1491 | }; | |
1492 | ||
1493 | static struct omap_hwmod omap44xx_mcspi1_hwmod = { | |
1494 | .name = "mcspi1", | |
1495 | .class = &omap44xx_mcspi_hwmod_class, | |
1496 | .mpu_irqs = omap44xx_mcspi1_irqs, | |
1497 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_irqs), | |
1498 | .sdma_reqs = omap44xx_mcspi1_sdma_reqs, | |
1499 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs), | |
1500 | .main_clk = "mcspi1_fck", | |
1501 | .prcm = { | |
1502 | .omap4 = { | |
1503 | .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, | |
1504 | }, | |
1505 | }, | |
1506 | .slaves = omap44xx_mcspi1_slaves, | |
1507 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves), | |
1508 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
1509 | }; | |
1510 | ||
1511 | /* mcspi2 */ | |
1512 | static struct omap_hwmod omap44xx_mcspi2_hwmod; | |
1513 | static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { | |
1514 | { .irq = 66 + OMAP44XX_IRQ_GIC_START }, | |
1515 | }; | |
1516 | ||
1517 | static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { | |
1518 | { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, | |
1519 | { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, | |
1520 | { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, | |
1521 | { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, | |
1522 | }; | |
1523 | ||
1524 | static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { | |
1525 | { | |
1526 | .pa_start = 0x4809a000, | |
1527 | .pa_end = 0x4809a1ff, | |
1528 | .flags = ADDR_TYPE_RT | |
1529 | }, | |
1530 | }; | |
1531 | ||
1532 | /* l4_per -> mcspi2 */ | |
1533 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { | |
1534 | .master = &omap44xx_l4_per_hwmod, | |
1535 | .slave = &omap44xx_mcspi2_hwmod, | |
1536 | .clk = "l4_div_ck", | |
1537 | .addr = omap44xx_mcspi2_addrs, | |
1538 | .addr_cnt = ARRAY_SIZE(omap44xx_mcspi2_addrs), | |
1539 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1540 | }; | |
1541 | ||
1542 | /* mcspi2 slave ports */ | |
1543 | static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = { | |
1544 | &omap44xx_l4_per__mcspi2, | |
1545 | }; | |
1546 | ||
1547 | static struct omap_hwmod omap44xx_mcspi2_hwmod = { | |
1548 | .name = "mcspi2", | |
1549 | .class = &omap44xx_mcspi_hwmod_class, | |
1550 | .mpu_irqs = omap44xx_mcspi2_irqs, | |
1551 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_irqs), | |
1552 | .sdma_reqs = omap44xx_mcspi2_sdma_reqs, | |
1553 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs), | |
1554 | .main_clk = "mcspi2_fck", | |
1555 | .prcm = { | |
1556 | .omap4 = { | |
1557 | .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, | |
1558 | }, | |
1559 | }, | |
1560 | .slaves = omap44xx_mcspi2_slaves, | |
1561 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves), | |
1562 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
1563 | }; | |
1564 | ||
1565 | /* mcspi3 */ | |
1566 | static struct omap_hwmod omap44xx_mcspi3_hwmod; | |
1567 | static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { | |
1568 | { .irq = 91 + OMAP44XX_IRQ_GIC_START }, | |
1569 | }; | |
1570 | ||
1571 | static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { | |
1572 | { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, | |
1573 | { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, | |
1574 | { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, | |
1575 | { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, | |
1576 | }; | |
1577 | ||
1578 | static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { | |
1579 | { | |
1580 | .pa_start = 0x480b8000, | |
1581 | .pa_end = 0x480b81ff, | |
1582 | .flags = ADDR_TYPE_RT | |
1583 | }, | |
1584 | }; | |
1585 | ||
1586 | /* l4_per -> mcspi3 */ | |
1587 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { | |
1588 | .master = &omap44xx_l4_per_hwmod, | |
1589 | .slave = &omap44xx_mcspi3_hwmod, | |
1590 | .clk = "l4_div_ck", | |
1591 | .addr = omap44xx_mcspi3_addrs, | |
1592 | .addr_cnt = ARRAY_SIZE(omap44xx_mcspi3_addrs), | |
1593 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1594 | }; | |
1595 | ||
1596 | /* mcspi3 slave ports */ | |
1597 | static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = { | |
1598 | &omap44xx_l4_per__mcspi3, | |
1599 | }; | |
1600 | ||
1601 | static struct omap_hwmod omap44xx_mcspi3_hwmod = { | |
1602 | .name = "mcspi3", | |
1603 | .class = &omap44xx_mcspi_hwmod_class, | |
1604 | .mpu_irqs = omap44xx_mcspi3_irqs, | |
1605 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_irqs), | |
1606 | .sdma_reqs = omap44xx_mcspi3_sdma_reqs, | |
1607 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs), | |
1608 | .main_clk = "mcspi3_fck", | |
1609 | .prcm = { | |
1610 | .omap4 = { | |
1611 | .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, | |
1612 | }, | |
1613 | }, | |
1614 | .slaves = omap44xx_mcspi3_slaves, | |
1615 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves), | |
1616 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
1617 | }; | |
1618 | ||
1619 | /* mcspi4 */ | |
1620 | static struct omap_hwmod omap44xx_mcspi4_hwmod; | |
1621 | static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { | |
1622 | { .irq = 48 + OMAP44XX_IRQ_GIC_START }, | |
1623 | }; | |
1624 | ||
1625 | static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { | |
1626 | { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, | |
1627 | { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, | |
1628 | }; | |
1629 | ||
1630 | static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { | |
1631 | { | |
1632 | .pa_start = 0x480ba000, | |
1633 | .pa_end = 0x480ba1ff, | |
1634 | .flags = ADDR_TYPE_RT | |
1635 | }, | |
1636 | }; | |
1637 | ||
1638 | /* l4_per -> mcspi4 */ | |
1639 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { | |
1640 | .master = &omap44xx_l4_per_hwmod, | |
1641 | .slave = &omap44xx_mcspi4_hwmod, | |
1642 | .clk = "l4_div_ck", | |
1643 | .addr = omap44xx_mcspi4_addrs, | |
1644 | .addr_cnt = ARRAY_SIZE(omap44xx_mcspi4_addrs), | |
1645 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1646 | }; | |
1647 | ||
1648 | /* mcspi4 slave ports */ | |
1649 | static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = { | |
1650 | &omap44xx_l4_per__mcspi4, | |
1651 | }; | |
1652 | ||
1653 | static struct omap_hwmod omap44xx_mcspi4_hwmod = { | |
1654 | .name = "mcspi4", | |
1655 | .class = &omap44xx_mcspi_hwmod_class, | |
1656 | .mpu_irqs = omap44xx_mcspi4_irqs, | |
1657 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_irqs), | |
1658 | .sdma_reqs = omap44xx_mcspi4_sdma_reqs, | |
1659 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs), | |
1660 | .main_clk = "mcspi4_fck", | |
1661 | .prcm = { | |
1662 | .omap4 = { | |
1663 | .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, | |
1664 | }, | |
1665 | }, | |
1666 | .slaves = omap44xx_mcspi4_slaves, | |
1667 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves), | |
1668 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
1669 | }; | |
1670 | ||
3b54baad BC |
1671 | /* |
1672 | * 'mpu' class | |
1673 | * mpu sub-system | |
1674 | */ | |
1675 | ||
1676 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { | |
fe13471c | 1677 | .name = "mpu", |
db12ba53 BC |
1678 | }; |
1679 | ||
3b54baad BC |
1680 | /* mpu */ |
1681 | static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { | |
1682 | { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, | |
1683 | { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, | |
1684 | { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, | |
db12ba53 BC |
1685 | }; |
1686 | ||
3b54baad BC |
1687 | /* mpu master ports */ |
1688 | static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = { | |
1689 | &omap44xx_mpu__l3_main_1, | |
1690 | &omap44xx_mpu__l4_abe, | |
1691 | &omap44xx_mpu__dmm, | |
1692 | }; | |
1693 | ||
1694 | static struct omap_hwmod omap44xx_mpu_hwmod = { | |
1695 | .name = "mpu", | |
1696 | .class = &omap44xx_mpu_hwmod_class, | |
1697 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
1698 | .mpu_irqs = omap44xx_mpu_irqs, | |
1699 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs), | |
1700 | .main_clk = "dpll_mpu_m2_ck", | |
db12ba53 BC |
1701 | .prcm = { |
1702 | .omap4 = { | |
3b54baad | 1703 | .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL, |
db12ba53 BC |
1704 | }, |
1705 | }, | |
3b54baad BC |
1706 | .masters = omap44xx_mpu_masters, |
1707 | .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters), | |
db12ba53 BC |
1708 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
1709 | }; | |
1710 | ||
1f6a717f BC |
1711 | /* |
1712 | * 'smartreflex' class | |
1713 | * smartreflex module (monitor silicon performance and outputs a measure of | |
1714 | * performance error) | |
1715 | */ | |
1716 | ||
1717 | /* The IP is not compliant to type1 / type2 scheme */ | |
1718 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { | |
1719 | .sidle_shift = 24, | |
1720 | .enwkup_shift = 26, | |
1721 | }; | |
1722 | ||
1723 | static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { | |
1724 | .sysc_offs = 0x0038, | |
1725 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), | |
1726 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1727 | SIDLE_SMART_WKUP), | |
1728 | .sysc_fields = &omap_hwmod_sysc_type_smartreflex, | |
1729 | }; | |
1730 | ||
1731 | static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { | |
fe13471c BC |
1732 | .name = "smartreflex", |
1733 | .sysc = &omap44xx_smartreflex_sysc, | |
1734 | .rev = 2, | |
1f6a717f BC |
1735 | }; |
1736 | ||
1737 | /* smartreflex_core */ | |
1738 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod; | |
1739 | static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { | |
1740 | { .irq = 19 + OMAP44XX_IRQ_GIC_START }, | |
1741 | }; | |
1742 | ||
1743 | static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { | |
1744 | { | |
1745 | .pa_start = 0x4a0dd000, | |
1746 | .pa_end = 0x4a0dd03f, | |
1747 | .flags = ADDR_TYPE_RT | |
1748 | }, | |
1749 | }; | |
1750 | ||
1751 | /* l4_cfg -> smartreflex_core */ | |
1752 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { | |
1753 | .master = &omap44xx_l4_cfg_hwmod, | |
1754 | .slave = &omap44xx_smartreflex_core_hwmod, | |
1755 | .clk = "l4_div_ck", | |
1756 | .addr = omap44xx_smartreflex_core_addrs, | |
1757 | .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs), | |
1758 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1759 | }; | |
1760 | ||
1761 | /* smartreflex_core slave ports */ | |
1762 | static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = { | |
1763 | &omap44xx_l4_cfg__smartreflex_core, | |
1764 | }; | |
1765 | ||
1766 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { | |
1767 | .name = "smartreflex_core", | |
1768 | .class = &omap44xx_smartreflex_hwmod_class, | |
1769 | .mpu_irqs = omap44xx_smartreflex_core_irqs, | |
1770 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs), | |
1771 | .main_clk = "smartreflex_core_fck", | |
1772 | .vdd_name = "core", | |
1773 | .prcm = { | |
1774 | .omap4 = { | |
1775 | .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, | |
1776 | }, | |
1777 | }, | |
1778 | .slaves = omap44xx_smartreflex_core_slaves, | |
1779 | .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves), | |
1780 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
1781 | }; | |
1782 | ||
1783 | /* smartreflex_iva */ | |
1784 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod; | |
1785 | static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { | |
1786 | { .irq = 102 + OMAP44XX_IRQ_GIC_START }, | |
1787 | }; | |
1788 | ||
1789 | static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { | |
1790 | { | |
1791 | .pa_start = 0x4a0db000, | |
1792 | .pa_end = 0x4a0db03f, | |
1793 | .flags = ADDR_TYPE_RT | |
1794 | }, | |
1795 | }; | |
1796 | ||
1797 | /* l4_cfg -> smartreflex_iva */ | |
1798 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { | |
1799 | .master = &omap44xx_l4_cfg_hwmod, | |
1800 | .slave = &omap44xx_smartreflex_iva_hwmod, | |
1801 | .clk = "l4_div_ck", | |
1802 | .addr = omap44xx_smartreflex_iva_addrs, | |
1803 | .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs), | |
1804 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1805 | }; | |
1806 | ||
1807 | /* smartreflex_iva slave ports */ | |
1808 | static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = { | |
1809 | &omap44xx_l4_cfg__smartreflex_iva, | |
1810 | }; | |
1811 | ||
1812 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { | |
1813 | .name = "smartreflex_iva", | |
1814 | .class = &omap44xx_smartreflex_hwmod_class, | |
1815 | .mpu_irqs = omap44xx_smartreflex_iva_irqs, | |
1816 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs), | |
1817 | .main_clk = "smartreflex_iva_fck", | |
1818 | .vdd_name = "iva", | |
1819 | .prcm = { | |
1820 | .omap4 = { | |
1821 | .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, | |
1822 | }, | |
1823 | }, | |
1824 | .slaves = omap44xx_smartreflex_iva_slaves, | |
1825 | .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves), | |
1826 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
1827 | }; | |
1828 | ||
1829 | /* smartreflex_mpu */ | |
1830 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod; | |
1831 | static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { | |
1832 | { .irq = 18 + OMAP44XX_IRQ_GIC_START }, | |
1833 | }; | |
1834 | ||
1835 | static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { | |
1836 | { | |
1837 | .pa_start = 0x4a0d9000, | |
1838 | .pa_end = 0x4a0d903f, | |
1839 | .flags = ADDR_TYPE_RT | |
1840 | }, | |
1841 | }; | |
1842 | ||
1843 | /* l4_cfg -> smartreflex_mpu */ | |
1844 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { | |
1845 | .master = &omap44xx_l4_cfg_hwmod, | |
1846 | .slave = &omap44xx_smartreflex_mpu_hwmod, | |
1847 | .clk = "l4_div_ck", | |
1848 | .addr = omap44xx_smartreflex_mpu_addrs, | |
1849 | .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs), | |
1850 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1851 | }; | |
1852 | ||
1853 | /* smartreflex_mpu slave ports */ | |
1854 | static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = { | |
1855 | &omap44xx_l4_cfg__smartreflex_mpu, | |
1856 | }; | |
1857 | ||
1858 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { | |
1859 | .name = "smartreflex_mpu", | |
1860 | .class = &omap44xx_smartreflex_hwmod_class, | |
1861 | .mpu_irqs = omap44xx_smartreflex_mpu_irqs, | |
1862 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs), | |
1863 | .main_clk = "smartreflex_mpu_fck", | |
1864 | .vdd_name = "mpu", | |
1865 | .prcm = { | |
1866 | .omap4 = { | |
1867 | .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, | |
1868 | }, | |
1869 | }, | |
1870 | .slaves = omap44xx_smartreflex_mpu_slaves, | |
1871 | .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves), | |
1872 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
1873 | }; | |
1874 | ||
d11c217f BC |
1875 | /* |
1876 | * 'spinlock' class | |
1877 | * spinlock provides hardware assistance for synchronizing the processes | |
1878 | * running on multiple processors | |
1879 | */ | |
1880 | ||
1881 | static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = { | |
1882 | .rev_offs = 0x0000, | |
1883 | .sysc_offs = 0x0010, | |
1884 | .syss_offs = 0x0014, | |
1885 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1886 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
1887 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1888 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1889 | SIDLE_SMART_WKUP), | |
1890 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1891 | }; | |
1892 | ||
1893 | static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { | |
1894 | .name = "spinlock", | |
1895 | .sysc = &omap44xx_spinlock_sysc, | |
1896 | }; | |
1897 | ||
1898 | /* spinlock */ | |
1899 | static struct omap_hwmod omap44xx_spinlock_hwmod; | |
1900 | static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { | |
1901 | { | |
1902 | .pa_start = 0x4a0f6000, | |
1903 | .pa_end = 0x4a0f6fff, | |
1904 | .flags = ADDR_TYPE_RT | |
1905 | }, | |
1906 | }; | |
1907 | ||
1908 | /* l4_cfg -> spinlock */ | |
1909 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { | |
1910 | .master = &omap44xx_l4_cfg_hwmod, | |
1911 | .slave = &omap44xx_spinlock_hwmod, | |
1912 | .clk = "l4_div_ck", | |
1913 | .addr = omap44xx_spinlock_addrs, | |
1914 | .addr_cnt = ARRAY_SIZE(omap44xx_spinlock_addrs), | |
1915 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1916 | }; | |
1917 | ||
1918 | /* spinlock slave ports */ | |
1919 | static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = { | |
1920 | &omap44xx_l4_cfg__spinlock, | |
1921 | }; | |
1922 | ||
1923 | static struct omap_hwmod omap44xx_spinlock_hwmod = { | |
1924 | .name = "spinlock", | |
1925 | .class = &omap44xx_spinlock_hwmod_class, | |
1926 | .prcm = { | |
1927 | .omap4 = { | |
1928 | .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL, | |
1929 | }, | |
1930 | }, | |
1931 | .slaves = omap44xx_spinlock_slaves, | |
1932 | .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves), | |
1933 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | |
1934 | }; | |
1935 | ||
9780a9cf | 1936 | /* |
3b54baad BC |
1937 | * 'uart' class |
1938 | * universal asynchronous receiver/transmitter (uart) | |
9780a9cf BC |
1939 | */ |
1940 | ||
3b54baad BC |
1941 | static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { |
1942 | .rev_offs = 0x0050, | |
1943 | .sysc_offs = 0x0054, | |
1944 | .syss_offs = 0x0058, | |
1945 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
0cfe8751 BC |
1946 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
1947 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
1948 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1949 | SIDLE_SMART_WKUP), | |
9780a9cf BC |
1950 | .sysc_fields = &omap_hwmod_sysc_type1, |
1951 | }; | |
1952 | ||
3b54baad | 1953 | static struct omap_hwmod_class omap44xx_uart_hwmod_class = { |
fe13471c BC |
1954 | .name = "uart", |
1955 | .sysc = &omap44xx_uart_sysc, | |
9780a9cf BC |
1956 | }; |
1957 | ||
3b54baad BC |
1958 | /* uart1 */ |
1959 | static struct omap_hwmod omap44xx_uart1_hwmod; | |
1960 | static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { | |
1961 | { .irq = 72 + OMAP44XX_IRQ_GIC_START }, | |
9780a9cf BC |
1962 | }; |
1963 | ||
3b54baad BC |
1964 | static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { |
1965 | { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, | |
1966 | { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, | |
9780a9cf BC |
1967 | }; |
1968 | ||
3b54baad | 1969 | static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { |
9780a9cf | 1970 | { |
3b54baad BC |
1971 | .pa_start = 0x4806a000, |
1972 | .pa_end = 0x4806a0ff, | |
9780a9cf BC |
1973 | .flags = ADDR_TYPE_RT |
1974 | }, | |
1975 | }; | |
1976 | ||
3b54baad BC |
1977 | /* l4_per -> uart1 */ |
1978 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { | |
1979 | .master = &omap44xx_l4_per_hwmod, | |
1980 | .slave = &omap44xx_uart1_hwmod, | |
1981 | .clk = "l4_div_ck", | |
1982 | .addr = omap44xx_uart1_addrs, | |
1983 | .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs), | |
9780a9cf BC |
1984 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1985 | }; | |
1986 | ||
3b54baad BC |
1987 | /* uart1 slave ports */ |
1988 | static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = { | |
1989 | &omap44xx_l4_per__uart1, | |
9780a9cf BC |
1990 | }; |
1991 | ||
3b54baad BC |
1992 | static struct omap_hwmod omap44xx_uart1_hwmod = { |
1993 | .name = "uart1", | |
1994 | .class = &omap44xx_uart_hwmod_class, | |
1995 | .mpu_irqs = omap44xx_uart1_irqs, | |
1996 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs), | |
1997 | .sdma_reqs = omap44xx_uart1_sdma_reqs, | |
1998 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs), | |
1999 | .main_clk = "uart1_fck", | |
9780a9cf BC |
2000 | .prcm = { |
2001 | .omap4 = { | |
3b54baad | 2002 | .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, |
9780a9cf BC |
2003 | }, |
2004 | }, | |
3b54baad BC |
2005 | .slaves = omap44xx_uart1_slaves, |
2006 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves), | |
9780a9cf BC |
2007 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
2008 | }; | |
2009 | ||
3b54baad BC |
2010 | /* uart2 */ |
2011 | static struct omap_hwmod omap44xx_uart2_hwmod; | |
2012 | static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { | |
2013 | { .irq = 73 + OMAP44XX_IRQ_GIC_START }, | |
9780a9cf BC |
2014 | }; |
2015 | ||
3b54baad BC |
2016 | static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { |
2017 | { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, | |
2018 | { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, | |
2019 | }; | |
2020 | ||
2021 | static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { | |
9780a9cf | 2022 | { |
3b54baad BC |
2023 | .pa_start = 0x4806c000, |
2024 | .pa_end = 0x4806c0ff, | |
9780a9cf BC |
2025 | .flags = ADDR_TYPE_RT |
2026 | }, | |
2027 | }; | |
2028 | ||
3b54baad BC |
2029 | /* l4_per -> uart2 */ |
2030 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { | |
9780a9cf | 2031 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
2032 | .slave = &omap44xx_uart2_hwmod, |
2033 | .clk = "l4_div_ck", | |
2034 | .addr = omap44xx_uart2_addrs, | |
2035 | .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs), | |
9780a9cf BC |
2036 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2037 | }; | |
2038 | ||
3b54baad BC |
2039 | /* uart2 slave ports */ |
2040 | static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = { | |
2041 | &omap44xx_l4_per__uart2, | |
9780a9cf BC |
2042 | }; |
2043 | ||
3b54baad BC |
2044 | static struct omap_hwmod omap44xx_uart2_hwmod = { |
2045 | .name = "uart2", | |
2046 | .class = &omap44xx_uart_hwmod_class, | |
2047 | .mpu_irqs = omap44xx_uart2_irqs, | |
2048 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs), | |
2049 | .sdma_reqs = omap44xx_uart2_sdma_reqs, | |
2050 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs), | |
2051 | .main_clk = "uart2_fck", | |
9780a9cf BC |
2052 | .prcm = { |
2053 | .omap4 = { | |
3b54baad | 2054 | .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, |
9780a9cf BC |
2055 | }, |
2056 | }, | |
3b54baad BC |
2057 | .slaves = omap44xx_uart2_slaves, |
2058 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves), | |
9780a9cf BC |
2059 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
2060 | }; | |
2061 | ||
3b54baad BC |
2062 | /* uart3 */ |
2063 | static struct omap_hwmod omap44xx_uart3_hwmod; | |
2064 | static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { | |
2065 | { .irq = 74 + OMAP44XX_IRQ_GIC_START }, | |
9780a9cf BC |
2066 | }; |
2067 | ||
3b54baad BC |
2068 | static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { |
2069 | { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, | |
2070 | { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, | |
2071 | }; | |
2072 | ||
2073 | static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { | |
9780a9cf | 2074 | { |
3b54baad BC |
2075 | .pa_start = 0x48020000, |
2076 | .pa_end = 0x480200ff, | |
9780a9cf BC |
2077 | .flags = ADDR_TYPE_RT |
2078 | }, | |
2079 | }; | |
2080 | ||
3b54baad BC |
2081 | /* l4_per -> uart3 */ |
2082 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { | |
9780a9cf | 2083 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
2084 | .slave = &omap44xx_uart3_hwmod, |
2085 | .clk = "l4_div_ck", | |
2086 | .addr = omap44xx_uart3_addrs, | |
2087 | .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs), | |
9780a9cf BC |
2088 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2089 | }; | |
2090 | ||
3b54baad BC |
2091 | /* uart3 slave ports */ |
2092 | static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = { | |
2093 | &omap44xx_l4_per__uart3, | |
2094 | }; | |
2095 | ||
2096 | static struct omap_hwmod omap44xx_uart3_hwmod = { | |
2097 | .name = "uart3", | |
2098 | .class = &omap44xx_uart_hwmod_class, | |
2099 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), | |
2100 | .mpu_irqs = omap44xx_uart3_irqs, | |
2101 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs), | |
2102 | .sdma_reqs = omap44xx_uart3_sdma_reqs, | |
2103 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs), | |
2104 | .main_clk = "uart3_fck", | |
9780a9cf BC |
2105 | .prcm = { |
2106 | .omap4 = { | |
3b54baad | 2107 | .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, |
9780a9cf BC |
2108 | }, |
2109 | }, | |
3b54baad BC |
2110 | .slaves = omap44xx_uart3_slaves, |
2111 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves), | |
9780a9cf BC |
2112 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
2113 | }; | |
2114 | ||
3b54baad BC |
2115 | /* uart4 */ |
2116 | static struct omap_hwmod omap44xx_uart4_hwmod; | |
2117 | static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { | |
2118 | { .irq = 70 + OMAP44XX_IRQ_GIC_START }, | |
9780a9cf BC |
2119 | }; |
2120 | ||
3b54baad BC |
2121 | static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { |
2122 | { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, | |
2123 | { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, | |
2124 | }; | |
2125 | ||
2126 | static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { | |
9780a9cf | 2127 | { |
3b54baad BC |
2128 | .pa_start = 0x4806e000, |
2129 | .pa_end = 0x4806e0ff, | |
9780a9cf BC |
2130 | .flags = ADDR_TYPE_RT |
2131 | }, | |
2132 | }; | |
2133 | ||
3b54baad BC |
2134 | /* l4_per -> uart4 */ |
2135 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { | |
9780a9cf | 2136 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
2137 | .slave = &omap44xx_uart4_hwmod, |
2138 | .clk = "l4_div_ck", | |
2139 | .addr = omap44xx_uart4_addrs, | |
2140 | .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs), | |
9780a9cf BC |
2141 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2142 | }; | |
2143 | ||
3b54baad BC |
2144 | /* uart4 slave ports */ |
2145 | static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = { | |
2146 | &omap44xx_l4_per__uart4, | |
9780a9cf BC |
2147 | }; |
2148 | ||
3b54baad BC |
2149 | static struct omap_hwmod omap44xx_uart4_hwmod = { |
2150 | .name = "uart4", | |
2151 | .class = &omap44xx_uart_hwmod_class, | |
2152 | .mpu_irqs = omap44xx_uart4_irqs, | |
2153 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs), | |
2154 | .sdma_reqs = omap44xx_uart4_sdma_reqs, | |
2155 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs), | |
2156 | .main_clk = "uart4_fck", | |
9780a9cf BC |
2157 | .prcm = { |
2158 | .omap4 = { | |
3b54baad | 2159 | .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, |
9780a9cf BC |
2160 | }, |
2161 | }, | |
3b54baad BC |
2162 | .slaves = omap44xx_uart4_slaves, |
2163 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves), | |
9780a9cf BC |
2164 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
2165 | }; | |
2166 | ||
3b54baad BC |
2167 | /* |
2168 | * 'wd_timer' class | |
2169 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
2170 | * overflow condition | |
2171 | */ | |
2172 | ||
2173 | static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { | |
2174 | .rev_offs = 0x0000, | |
2175 | .sysc_offs = 0x0010, | |
2176 | .syss_offs = 0x0014, | |
2177 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 2178 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
2179 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
2180 | SIDLE_SMART_WKUP), | |
3b54baad | 2181 | .sysc_fields = &omap_hwmod_sysc_type1, |
9780a9cf BC |
2182 | }; |
2183 | ||
3b54baad BC |
2184 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { |
2185 | .name = "wd_timer", | |
2186 | .sysc = &omap44xx_wd_timer_sysc, | |
fe13471c | 2187 | .pre_shutdown = &omap2_wd_timer_disable, |
3b54baad BC |
2188 | }; |
2189 | ||
2190 | /* wd_timer2 */ | |
2191 | static struct omap_hwmod omap44xx_wd_timer2_hwmod; | |
2192 | static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { | |
2193 | { .irq = 80 + OMAP44XX_IRQ_GIC_START }, | |
2194 | }; | |
2195 | ||
2196 | static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { | |
9780a9cf | 2197 | { |
3b54baad BC |
2198 | .pa_start = 0x4a314000, |
2199 | .pa_end = 0x4a31407f, | |
9780a9cf BC |
2200 | .flags = ADDR_TYPE_RT |
2201 | }, | |
2202 | }; | |
2203 | ||
3b54baad BC |
2204 | /* l4_wkup -> wd_timer2 */ |
2205 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { | |
2206 | .master = &omap44xx_l4_wkup_hwmod, | |
2207 | .slave = &omap44xx_wd_timer2_hwmod, | |
2208 | .clk = "l4_wkup_clk_mux_ck", | |
2209 | .addr = omap44xx_wd_timer2_addrs, | |
2210 | .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs), | |
9780a9cf BC |
2211 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2212 | }; | |
2213 | ||
3b54baad BC |
2214 | /* wd_timer2 slave ports */ |
2215 | static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = { | |
2216 | &omap44xx_l4_wkup__wd_timer2, | |
9780a9cf BC |
2217 | }; |
2218 | ||
3b54baad BC |
2219 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { |
2220 | .name = "wd_timer2", | |
2221 | .class = &omap44xx_wd_timer_hwmod_class, | |
2222 | .mpu_irqs = omap44xx_wd_timer2_irqs, | |
2223 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs), | |
2224 | .main_clk = "wd_timer2_fck", | |
9780a9cf BC |
2225 | .prcm = { |
2226 | .omap4 = { | |
3b54baad | 2227 | .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, |
9780a9cf BC |
2228 | }, |
2229 | }, | |
3b54baad BC |
2230 | .slaves = omap44xx_wd_timer2_slaves, |
2231 | .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves), | |
9780a9cf BC |
2232 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
2233 | }; | |
2234 | ||
3b54baad BC |
2235 | /* wd_timer3 */ |
2236 | static struct omap_hwmod omap44xx_wd_timer3_hwmod; | |
2237 | static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { | |
2238 | { .irq = 36 + OMAP44XX_IRQ_GIC_START }, | |
9780a9cf BC |
2239 | }; |
2240 | ||
3b54baad | 2241 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { |
9780a9cf | 2242 | { |
3b54baad BC |
2243 | .pa_start = 0x40130000, |
2244 | .pa_end = 0x4013007f, | |
9780a9cf BC |
2245 | .flags = ADDR_TYPE_RT |
2246 | }, | |
2247 | }; | |
2248 | ||
3b54baad BC |
2249 | /* l4_abe -> wd_timer3 */ |
2250 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { | |
2251 | .master = &omap44xx_l4_abe_hwmod, | |
2252 | .slave = &omap44xx_wd_timer3_hwmod, | |
2253 | .clk = "ocp_abe_iclk", | |
2254 | .addr = omap44xx_wd_timer3_addrs, | |
2255 | .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs), | |
2256 | .user = OCP_USER_MPU, | |
9780a9cf BC |
2257 | }; |
2258 | ||
3b54baad BC |
2259 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { |
2260 | { | |
2261 | .pa_start = 0x49030000, | |
2262 | .pa_end = 0x4903007f, | |
2263 | .flags = ADDR_TYPE_RT | |
2264 | }, | |
9780a9cf BC |
2265 | }; |
2266 | ||
3b54baad BC |
2267 | /* l4_abe -> wd_timer3 (dma) */ |
2268 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { | |
2269 | .master = &omap44xx_l4_abe_hwmod, | |
2270 | .slave = &omap44xx_wd_timer3_hwmod, | |
2271 | .clk = "ocp_abe_iclk", | |
2272 | .addr = omap44xx_wd_timer3_dma_addrs, | |
2273 | .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs), | |
2274 | .user = OCP_USER_SDMA, | |
9780a9cf BC |
2275 | }; |
2276 | ||
3b54baad BC |
2277 | /* wd_timer3 slave ports */ |
2278 | static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = { | |
2279 | &omap44xx_l4_abe__wd_timer3, | |
2280 | &omap44xx_l4_abe__wd_timer3_dma, | |
2281 | }; | |
2282 | ||
2283 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { | |
2284 | .name = "wd_timer3", | |
2285 | .class = &omap44xx_wd_timer_hwmod_class, | |
2286 | .mpu_irqs = omap44xx_wd_timer3_irqs, | |
2287 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs), | |
2288 | .main_clk = "wd_timer3_fck", | |
9780a9cf BC |
2289 | .prcm = { |
2290 | .omap4 = { | |
3b54baad | 2291 | .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, |
9780a9cf BC |
2292 | }, |
2293 | }, | |
3b54baad BC |
2294 | .slaves = omap44xx_wd_timer3_slaves, |
2295 | .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), | |
9780a9cf BC |
2296 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
2297 | }; | |
531ce0d5 | 2298 | |
55d2cb08 | 2299 | static __initdata struct omap_hwmod *omap44xx_hwmods[] = { |
fe13471c | 2300 | |
55d2cb08 BC |
2301 | /* dmm class */ |
2302 | &omap44xx_dmm_hwmod, | |
3b54baad | 2303 | |
55d2cb08 BC |
2304 | /* emif_fw class */ |
2305 | &omap44xx_emif_fw_hwmod, | |
3b54baad | 2306 | |
55d2cb08 BC |
2307 | /* l3 class */ |
2308 | &omap44xx_l3_instr_hwmod, | |
2309 | &omap44xx_l3_main_1_hwmod, | |
2310 | &omap44xx_l3_main_2_hwmod, | |
2311 | &omap44xx_l3_main_3_hwmod, | |
3b54baad | 2312 | |
55d2cb08 BC |
2313 | /* l4 class */ |
2314 | &omap44xx_l4_abe_hwmod, | |
2315 | &omap44xx_l4_cfg_hwmod, | |
2316 | &omap44xx_l4_per_hwmod, | |
2317 | &omap44xx_l4_wkup_hwmod, | |
531ce0d5 | 2318 | |
55d2cb08 BC |
2319 | /* mpu_bus class */ |
2320 | &omap44xx_mpu_private_hwmod, | |
2321 | ||
d7cf5f33 BC |
2322 | /* dma class */ |
2323 | &omap44xx_dma_system_hwmod, | |
2324 | ||
8f25bdc5 BC |
2325 | /* dsp class */ |
2326 | &omap44xx_dsp_hwmod, | |
2327 | &omap44xx_dsp_c0_hwmod, | |
2328 | ||
9780a9cf BC |
2329 | /* gpio class */ |
2330 | &omap44xx_gpio1_hwmod, | |
2331 | &omap44xx_gpio2_hwmod, | |
2332 | &omap44xx_gpio3_hwmod, | |
2333 | &omap44xx_gpio4_hwmod, | |
2334 | &omap44xx_gpio5_hwmod, | |
2335 | &omap44xx_gpio6_hwmod, | |
2336 | ||
3b54baad BC |
2337 | /* i2c class */ |
2338 | &omap44xx_i2c1_hwmod, | |
2339 | &omap44xx_i2c2_hwmod, | |
2340 | &omap44xx_i2c3_hwmod, | |
2341 | &omap44xx_i2c4_hwmod, | |
2342 | ||
8f25bdc5 BC |
2343 | /* iva class */ |
2344 | &omap44xx_iva_hwmod, | |
2345 | &omap44xx_iva_seq0_hwmod, | |
2346 | &omap44xx_iva_seq1_hwmod, | |
2347 | ||
9bcbd7f0 BC |
2348 | /* mcspi class */ |
2349 | &omap44xx_mcspi1_hwmod, | |
2350 | &omap44xx_mcspi2_hwmod, | |
2351 | &omap44xx_mcspi3_hwmod, | |
2352 | &omap44xx_mcspi4_hwmod, | |
2353 | ||
55d2cb08 BC |
2354 | /* mpu class */ |
2355 | &omap44xx_mpu_hwmod, | |
db12ba53 | 2356 | |
1f6a717f BC |
2357 | /* smartreflex class */ |
2358 | &omap44xx_smartreflex_core_hwmod, | |
2359 | &omap44xx_smartreflex_iva_hwmod, | |
2360 | &omap44xx_smartreflex_mpu_hwmod, | |
2361 | ||
d11c217f BC |
2362 | /* spinlock class */ |
2363 | &omap44xx_spinlock_hwmod, | |
2364 | ||
db12ba53 BC |
2365 | /* uart class */ |
2366 | &omap44xx_uart1_hwmod, | |
2367 | &omap44xx_uart2_hwmod, | |
2368 | &omap44xx_uart3_hwmod, | |
2369 | &omap44xx_uart4_hwmod, | |
3b54baad BC |
2370 | |
2371 | /* wd_timer class */ | |
2372 | &omap44xx_wd_timer2_hwmod, | |
2373 | &omap44xx_wd_timer3_hwmod, | |
2374 | ||
55d2cb08 BC |
2375 | NULL, |
2376 | }; | |
2377 | ||
2378 | int __init omap44xx_hwmod_init(void) | |
2379 | { | |
2380 | return omap_hwmod_init(omap44xx_hwmods); | |
2381 | } | |
2382 |