Commit | Line | Data |
---|---|---|
55d2cb08 BC |
1 | /* |
2 | * Hardware modules present on the OMAP44xx chips | |
3 | * | |
d63bd74f | 4 | * Copyright (C) 2009-2011 Texas Instruments, Inc. |
55d2cb08 BC |
5 | * Copyright (C) 2009-2010 Nokia Corporation |
6 | * | |
7 | * Paul Walmsley | |
8 | * Benoit Cousson | |
9 | * | |
10 | * This file is automatically generated from the OMAP hardware databases. | |
11 | * We respectfully ask that any modifications to this file be coordinated | |
12 | * with the public linux-omap@vger.kernel.org mailing list and the | |
13 | * authors above to ensure that the autogeneration scripts are kept | |
14 | * up-to-date with the file contents. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/io.h> | |
22 | ||
23 | #include <plat/omap_hwmod.h> | |
24 | #include <plat/cpu.h> | |
6d3c55fd | 25 | #include <plat/i2c.h> |
9780a9cf | 26 | #include <plat/gpio.h> |
531ce0d5 | 27 | #include <plat/dma.h> |
905a74d9 | 28 | #include <plat/mcspi.h> |
cb7e9ded | 29 | #include <plat/mcbsp.h> |
6ab8946f | 30 | #include <plat/mmc.h> |
4d4441a6 | 31 | #include <plat/i2c.h> |
c345c8b0 | 32 | #include <plat/dmtimer.h> |
13662dc5 | 33 | #include <plat/common.h> |
55d2cb08 BC |
34 | |
35 | #include "omap_hwmod_common_data.h" | |
36 | ||
cea6b942 | 37 | #include "smartreflex.h" |
d198b514 PW |
38 | #include "cm1_44xx.h" |
39 | #include "cm2_44xx.h" | |
40 | #include "prm44xx.h" | |
55d2cb08 | 41 | #include "prm-regbits-44xx.h" |
ff2516fb | 42 | #include "wd_timer.h" |
55d2cb08 BC |
43 | |
44 | /* Base offset for all OMAP4 interrupts external to MPUSS */ | |
45 | #define OMAP44XX_IRQ_GIC_START 32 | |
46 | ||
47 | /* Base offset for all OMAP4 dma requests */ | |
48 | #define OMAP44XX_DMA_REQ_START 1 | |
49 | ||
50 | /* Backward references (IPs with Bus Master capability) */ | |
407a6888 | 51 | static struct omap_hwmod omap44xx_aess_hwmod; |
531ce0d5 | 52 | static struct omap_hwmod omap44xx_dma_system_hwmod; |
55d2cb08 | 53 | static struct omap_hwmod omap44xx_dmm_hwmod; |
8f25bdc5 | 54 | static struct omap_hwmod omap44xx_dsp_hwmod; |
d63bd74f | 55 | static struct omap_hwmod omap44xx_dss_hwmod; |
55d2cb08 | 56 | static struct omap_hwmod omap44xx_emif_fw_hwmod; |
407a6888 BC |
57 | static struct omap_hwmod omap44xx_hsi_hwmod; |
58 | static struct omap_hwmod omap44xx_ipu_hwmod; | |
59 | static struct omap_hwmod omap44xx_iss_hwmod; | |
8f25bdc5 | 60 | static struct omap_hwmod omap44xx_iva_hwmod; |
55d2cb08 BC |
61 | static struct omap_hwmod omap44xx_l3_instr_hwmod; |
62 | static struct omap_hwmod omap44xx_l3_main_1_hwmod; | |
63 | static struct omap_hwmod omap44xx_l3_main_2_hwmod; | |
64 | static struct omap_hwmod omap44xx_l3_main_3_hwmod; | |
65 | static struct omap_hwmod omap44xx_l4_abe_hwmod; | |
66 | static struct omap_hwmod omap44xx_l4_cfg_hwmod; | |
67 | static struct omap_hwmod omap44xx_l4_per_hwmod; | |
68 | static struct omap_hwmod omap44xx_l4_wkup_hwmod; | |
407a6888 BC |
69 | static struct omap_hwmod omap44xx_mmc1_hwmod; |
70 | static struct omap_hwmod omap44xx_mmc2_hwmod; | |
55d2cb08 BC |
71 | static struct omap_hwmod omap44xx_mpu_hwmod; |
72 | static struct omap_hwmod omap44xx_mpu_private_hwmod; | |
5844c4ea | 73 | static struct omap_hwmod omap44xx_usb_otg_hs_hwmod; |
af88fa9a BC |
74 | static struct omap_hwmod omap44xx_usb_host_hs_hwmod; |
75 | static struct omap_hwmod omap44xx_usb_tll_hs_hwmod; | |
55d2cb08 BC |
76 | |
77 | /* | |
78 | * Interconnects omap_hwmod structures | |
79 | * hwmods that compose the global OMAP interconnect | |
80 | */ | |
81 | ||
82 | /* | |
83 | * 'dmm' class | |
84 | * instance(s): dmm | |
85 | */ | |
86 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { | |
fe13471c | 87 | .name = "dmm", |
55d2cb08 BC |
88 | }; |
89 | ||
7e69ed97 BC |
90 | /* dmm */ |
91 | static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { | |
92 | { .irq = 113 + OMAP44XX_IRQ_GIC_START }, | |
93 | { .irq = -1 } | |
94 | }; | |
95 | ||
55d2cb08 BC |
96 | /* l3_main_1 -> dmm */ |
97 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { | |
98 | .master = &omap44xx_l3_main_1_hwmod, | |
99 | .slave = &omap44xx_dmm_hwmod, | |
100 | .clk = "l3_div_ck", | |
659fa822 BC |
101 | .user = OCP_USER_SDMA, |
102 | }; | |
103 | ||
104 | static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { | |
105 | { | |
106 | .pa_start = 0x4e000000, | |
107 | .pa_end = 0x4e0007ff, | |
108 | .flags = ADDR_TYPE_RT | |
109 | }, | |
78183f3f | 110 | { } |
55d2cb08 BC |
111 | }; |
112 | ||
113 | /* mpu -> dmm */ | |
114 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { | |
115 | .master = &omap44xx_mpu_hwmod, | |
116 | .slave = &omap44xx_dmm_hwmod, | |
117 | .clk = "l3_div_ck", | |
659fa822 | 118 | .addr = omap44xx_dmm_addrs, |
659fa822 | 119 | .user = OCP_USER_MPU, |
55d2cb08 BC |
120 | }; |
121 | ||
122 | /* dmm slave ports */ | |
123 | static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = { | |
124 | &omap44xx_l3_main_1__dmm, | |
125 | &omap44xx_mpu__dmm, | |
126 | }; | |
127 | ||
55d2cb08 BC |
128 | static struct omap_hwmod omap44xx_dmm_hwmod = { |
129 | .name = "dmm", | |
130 | .class = &omap44xx_dmm_hwmod_class, | |
a5322c6f | 131 | .clkdm_name = "l3_emif_clkdm", |
d0f0631d BC |
132 | .prcm = { |
133 | .omap4 = { | |
134 | .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, | |
27bb00b5 | 135 | .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, |
d0f0631d BC |
136 | }, |
137 | }, | |
55d2cb08 BC |
138 | .slaves = omap44xx_dmm_slaves, |
139 | .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), | |
a5322c6f | 140 | .mpu_irqs = omap44xx_dmm_irqs, |
55d2cb08 BC |
141 | }; |
142 | ||
143 | /* | |
144 | * 'emif_fw' class | |
145 | * instance(s): emif_fw | |
146 | */ | |
147 | static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { | |
fe13471c | 148 | .name = "emif_fw", |
55d2cb08 BC |
149 | }; |
150 | ||
7e69ed97 | 151 | /* emif_fw */ |
55d2cb08 BC |
152 | /* dmm -> emif_fw */ |
153 | static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { | |
154 | .master = &omap44xx_dmm_hwmod, | |
155 | .slave = &omap44xx_emif_fw_hwmod, | |
156 | .clk = "l3_div_ck", | |
157 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
158 | }; | |
159 | ||
659fa822 BC |
160 | static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { |
161 | { | |
162 | .pa_start = 0x4a20c000, | |
163 | .pa_end = 0x4a20c0ff, | |
164 | .flags = ADDR_TYPE_RT | |
165 | }, | |
78183f3f | 166 | { } |
659fa822 BC |
167 | }; |
168 | ||
55d2cb08 BC |
169 | /* l4_cfg -> emif_fw */ |
170 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { | |
171 | .master = &omap44xx_l4_cfg_hwmod, | |
172 | .slave = &omap44xx_emif_fw_hwmod, | |
173 | .clk = "l4_div_ck", | |
659fa822 | 174 | .addr = omap44xx_emif_fw_addrs, |
659fa822 | 175 | .user = OCP_USER_MPU, |
55d2cb08 BC |
176 | }; |
177 | ||
178 | /* emif_fw slave ports */ | |
179 | static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = { | |
180 | &omap44xx_dmm__emif_fw, | |
181 | &omap44xx_l4_cfg__emif_fw, | |
182 | }; | |
183 | ||
184 | static struct omap_hwmod omap44xx_emif_fw_hwmod = { | |
185 | .name = "emif_fw", | |
186 | .class = &omap44xx_emif_fw_hwmod_class, | |
a5322c6f | 187 | .clkdm_name = "l3_emif_clkdm", |
d0f0631d BC |
188 | .prcm = { |
189 | .omap4 = { | |
190 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET, | |
27bb00b5 | 191 | .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET, |
d0f0631d BC |
192 | }, |
193 | }, | |
55d2cb08 BC |
194 | .slaves = omap44xx_emif_fw_slaves, |
195 | .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves), | |
55d2cb08 BC |
196 | }; |
197 | ||
198 | /* | |
199 | * 'l3' class | |
200 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 | |
201 | */ | |
202 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { | |
fe13471c | 203 | .name = "l3", |
55d2cb08 BC |
204 | }; |
205 | ||
7e69ed97 | 206 | /* l3_instr */ |
8f25bdc5 BC |
207 | /* iva -> l3_instr */ |
208 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { | |
209 | .master = &omap44xx_iva_hwmod, | |
210 | .slave = &omap44xx_l3_instr_hwmod, | |
211 | .clk = "l3_div_ck", | |
212 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
213 | }; | |
214 | ||
55d2cb08 BC |
215 | /* l3_main_3 -> l3_instr */ |
216 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { | |
217 | .master = &omap44xx_l3_main_3_hwmod, | |
218 | .slave = &omap44xx_l3_instr_hwmod, | |
219 | .clk = "l3_div_ck", | |
220 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
221 | }; | |
222 | ||
223 | /* l3_instr slave ports */ | |
224 | static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = { | |
8f25bdc5 | 225 | &omap44xx_iva__l3_instr, |
55d2cb08 BC |
226 | &omap44xx_l3_main_3__l3_instr, |
227 | }; | |
228 | ||
229 | static struct omap_hwmod omap44xx_l3_instr_hwmod = { | |
230 | .name = "l3_instr", | |
231 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 232 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
233 | .prcm = { |
234 | .omap4 = { | |
235 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, | |
27bb00b5 | 236 | .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, |
03fdefe5 | 237 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
238 | }, |
239 | }, | |
55d2cb08 BC |
240 | .slaves = omap44xx_l3_instr_slaves, |
241 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves), | |
55d2cb08 BC |
242 | }; |
243 | ||
7e69ed97 | 244 | /* l3_main_1 */ |
9b4021be BC |
245 | static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = { |
246 | { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START }, | |
247 | { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START }, | |
248 | { .irq = -1 } | |
249 | }; | |
250 | ||
8f25bdc5 BC |
251 | /* dsp -> l3_main_1 */ |
252 | static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { | |
253 | .master = &omap44xx_dsp_hwmod, | |
254 | .slave = &omap44xx_l3_main_1_hwmod, | |
255 | .clk = "l3_div_ck", | |
256 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
257 | }; | |
258 | ||
d63bd74f BC |
259 | /* dss -> l3_main_1 */ |
260 | static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { | |
261 | .master = &omap44xx_dss_hwmod, | |
262 | .slave = &omap44xx_l3_main_1_hwmod, | |
263 | .clk = "l3_div_ck", | |
264 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
265 | }; | |
266 | ||
55d2cb08 BC |
267 | /* l3_main_2 -> l3_main_1 */ |
268 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { | |
269 | .master = &omap44xx_l3_main_2_hwmod, | |
270 | .slave = &omap44xx_l3_main_1_hwmod, | |
271 | .clk = "l3_div_ck", | |
272 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
273 | }; | |
274 | ||
275 | /* l4_cfg -> l3_main_1 */ | |
276 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { | |
277 | .master = &omap44xx_l4_cfg_hwmod, | |
278 | .slave = &omap44xx_l3_main_1_hwmod, | |
279 | .clk = "l4_div_ck", | |
280 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
281 | }; | |
282 | ||
407a6888 BC |
283 | /* mmc1 -> l3_main_1 */ |
284 | static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { | |
285 | .master = &omap44xx_mmc1_hwmod, | |
286 | .slave = &omap44xx_l3_main_1_hwmod, | |
287 | .clk = "l3_div_ck", | |
288 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
289 | }; | |
290 | ||
291 | /* mmc2 -> l3_main_1 */ | |
292 | static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { | |
293 | .master = &omap44xx_mmc2_hwmod, | |
294 | .slave = &omap44xx_l3_main_1_hwmod, | |
295 | .clk = "l3_div_ck", | |
296 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
297 | }; | |
298 | ||
c4645234 | 299 | static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { |
300 | { | |
301 | .pa_start = 0x44000000, | |
302 | .pa_end = 0x44000fff, | |
9b4021be | 303 | .flags = ADDR_TYPE_RT |
c4645234 | 304 | }, |
78183f3f | 305 | { } |
c4645234 | 306 | }; |
307 | ||
55d2cb08 BC |
308 | /* mpu -> l3_main_1 */ |
309 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { | |
310 | .master = &omap44xx_mpu_hwmod, | |
311 | .slave = &omap44xx_l3_main_1_hwmod, | |
312 | .clk = "l3_div_ck", | |
c4645234 | 313 | .addr = omap44xx_l3_main_1_addrs, |
9b4021be | 314 | .user = OCP_USER_MPU, |
55d2cb08 BC |
315 | }; |
316 | ||
317 | /* l3_main_1 slave ports */ | |
318 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { | |
8f25bdc5 | 319 | &omap44xx_dsp__l3_main_1, |
d63bd74f | 320 | &omap44xx_dss__l3_main_1, |
55d2cb08 BC |
321 | &omap44xx_l3_main_2__l3_main_1, |
322 | &omap44xx_l4_cfg__l3_main_1, | |
407a6888 BC |
323 | &omap44xx_mmc1__l3_main_1, |
324 | &omap44xx_mmc2__l3_main_1, | |
55d2cb08 BC |
325 | &omap44xx_mpu__l3_main_1, |
326 | }; | |
327 | ||
328 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { | |
329 | .name = "l3_main_1", | |
330 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 331 | .clkdm_name = "l3_1_clkdm", |
7e69ed97 | 332 | .mpu_irqs = omap44xx_l3_main_1_irqs, |
d0f0631d BC |
333 | .prcm = { |
334 | .omap4 = { | |
335 | .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, | |
27bb00b5 | 336 | .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, |
d0f0631d BC |
337 | }, |
338 | }, | |
55d2cb08 BC |
339 | .slaves = omap44xx_l3_main_1_slaves, |
340 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), | |
55d2cb08 BC |
341 | }; |
342 | ||
7e69ed97 | 343 | /* l3_main_2 */ |
d7cf5f33 BC |
344 | /* dma_system -> l3_main_2 */ |
345 | static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { | |
346 | .master = &omap44xx_dma_system_hwmod, | |
347 | .slave = &omap44xx_l3_main_2_hwmod, | |
348 | .clk = "l3_div_ck", | |
349 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
350 | }; | |
351 | ||
407a6888 BC |
352 | /* hsi -> l3_main_2 */ |
353 | static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { | |
354 | .master = &omap44xx_hsi_hwmod, | |
355 | .slave = &omap44xx_l3_main_2_hwmod, | |
356 | .clk = "l3_div_ck", | |
357 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
358 | }; | |
359 | ||
360 | /* ipu -> l3_main_2 */ | |
361 | static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { | |
362 | .master = &omap44xx_ipu_hwmod, | |
363 | .slave = &omap44xx_l3_main_2_hwmod, | |
364 | .clk = "l3_div_ck", | |
365 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
366 | }; | |
367 | ||
368 | /* iss -> l3_main_2 */ | |
369 | static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { | |
370 | .master = &omap44xx_iss_hwmod, | |
371 | .slave = &omap44xx_l3_main_2_hwmod, | |
372 | .clk = "l3_div_ck", | |
373 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
374 | }; | |
375 | ||
8f25bdc5 BC |
376 | /* iva -> l3_main_2 */ |
377 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { | |
378 | .master = &omap44xx_iva_hwmod, | |
379 | .slave = &omap44xx_l3_main_2_hwmod, | |
380 | .clk = "l3_div_ck", | |
381 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
382 | }; | |
383 | ||
c4645234 | 384 | static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { |
385 | { | |
386 | .pa_start = 0x44800000, | |
387 | .pa_end = 0x44801fff, | |
9b4021be | 388 | .flags = ADDR_TYPE_RT |
c4645234 | 389 | }, |
78183f3f | 390 | { } |
c4645234 | 391 | }; |
392 | ||
55d2cb08 BC |
393 | /* l3_main_1 -> l3_main_2 */ |
394 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { | |
395 | .master = &omap44xx_l3_main_1_hwmod, | |
396 | .slave = &omap44xx_l3_main_2_hwmod, | |
397 | .clk = "l3_div_ck", | |
c4645234 | 398 | .addr = omap44xx_l3_main_2_addrs, |
9b4021be | 399 | .user = OCP_USER_MPU, |
55d2cb08 BC |
400 | }; |
401 | ||
402 | /* l4_cfg -> l3_main_2 */ | |
403 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { | |
404 | .master = &omap44xx_l4_cfg_hwmod, | |
405 | .slave = &omap44xx_l3_main_2_hwmod, | |
406 | .clk = "l4_div_ck", | |
407 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
408 | }; | |
409 | ||
5844c4ea BC |
410 | /* usb_otg_hs -> l3_main_2 */ |
411 | static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { | |
412 | .master = &omap44xx_usb_otg_hs_hwmod, | |
413 | .slave = &omap44xx_l3_main_2_hwmod, | |
414 | .clk = "l3_div_ck", | |
415 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
416 | }; | |
417 | ||
55d2cb08 BC |
418 | /* l3_main_2 slave ports */ |
419 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { | |
531ce0d5 | 420 | &omap44xx_dma_system__l3_main_2, |
407a6888 BC |
421 | &omap44xx_hsi__l3_main_2, |
422 | &omap44xx_ipu__l3_main_2, | |
423 | &omap44xx_iss__l3_main_2, | |
8f25bdc5 | 424 | &omap44xx_iva__l3_main_2, |
55d2cb08 BC |
425 | &omap44xx_l3_main_1__l3_main_2, |
426 | &omap44xx_l4_cfg__l3_main_2, | |
5844c4ea | 427 | &omap44xx_usb_otg_hs__l3_main_2, |
55d2cb08 BC |
428 | }; |
429 | ||
430 | static struct omap_hwmod omap44xx_l3_main_2_hwmod = { | |
431 | .name = "l3_main_2", | |
432 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 433 | .clkdm_name = "l3_2_clkdm", |
d0f0631d BC |
434 | .prcm = { |
435 | .omap4 = { | |
436 | .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET, | |
27bb00b5 | 437 | .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, |
d0f0631d BC |
438 | }, |
439 | }, | |
55d2cb08 BC |
440 | .slaves = omap44xx_l3_main_2_slaves, |
441 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves), | |
55d2cb08 BC |
442 | }; |
443 | ||
7e69ed97 | 444 | /* l3_main_3 */ |
c4645234 | 445 | static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { |
446 | { | |
447 | .pa_start = 0x45000000, | |
448 | .pa_end = 0x45000fff, | |
9b4021be | 449 | .flags = ADDR_TYPE_RT |
c4645234 | 450 | }, |
78183f3f | 451 | { } |
c4645234 | 452 | }; |
453 | ||
55d2cb08 BC |
454 | /* l3_main_1 -> l3_main_3 */ |
455 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { | |
456 | .master = &omap44xx_l3_main_1_hwmod, | |
457 | .slave = &omap44xx_l3_main_3_hwmod, | |
458 | .clk = "l3_div_ck", | |
c4645234 | 459 | .addr = omap44xx_l3_main_3_addrs, |
9b4021be | 460 | .user = OCP_USER_MPU, |
55d2cb08 BC |
461 | }; |
462 | ||
463 | /* l3_main_2 -> l3_main_3 */ | |
464 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { | |
465 | .master = &omap44xx_l3_main_2_hwmod, | |
466 | .slave = &omap44xx_l3_main_3_hwmod, | |
467 | .clk = "l3_div_ck", | |
468 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
469 | }; | |
470 | ||
471 | /* l4_cfg -> l3_main_3 */ | |
472 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { | |
473 | .master = &omap44xx_l4_cfg_hwmod, | |
474 | .slave = &omap44xx_l3_main_3_hwmod, | |
475 | .clk = "l4_div_ck", | |
476 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
477 | }; | |
478 | ||
479 | /* l3_main_3 slave ports */ | |
480 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = { | |
481 | &omap44xx_l3_main_1__l3_main_3, | |
482 | &omap44xx_l3_main_2__l3_main_3, | |
483 | &omap44xx_l4_cfg__l3_main_3, | |
484 | }; | |
485 | ||
486 | static struct omap_hwmod omap44xx_l3_main_3_hwmod = { | |
487 | .name = "l3_main_3", | |
488 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 489 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
490 | .prcm = { |
491 | .omap4 = { | |
492 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET, | |
27bb00b5 | 493 | .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET, |
03fdefe5 | 494 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
495 | }, |
496 | }, | |
55d2cb08 BC |
497 | .slaves = omap44xx_l3_main_3_slaves, |
498 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves), | |
55d2cb08 BC |
499 | }; |
500 | ||
501 | /* | |
502 | * 'l4' class | |
503 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup | |
504 | */ | |
505 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { | |
fe13471c | 506 | .name = "l4", |
55d2cb08 BC |
507 | }; |
508 | ||
7e69ed97 | 509 | /* l4_abe */ |
407a6888 BC |
510 | /* aess -> l4_abe */ |
511 | static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { | |
512 | .master = &omap44xx_aess_hwmod, | |
513 | .slave = &omap44xx_l4_abe_hwmod, | |
514 | .clk = "ocp_abe_iclk", | |
515 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
516 | }; | |
517 | ||
8f25bdc5 BC |
518 | /* dsp -> l4_abe */ |
519 | static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { | |
520 | .master = &omap44xx_dsp_hwmod, | |
521 | .slave = &omap44xx_l4_abe_hwmod, | |
522 | .clk = "ocp_abe_iclk", | |
523 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
524 | }; | |
525 | ||
55d2cb08 BC |
526 | /* l3_main_1 -> l4_abe */ |
527 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { | |
528 | .master = &omap44xx_l3_main_1_hwmod, | |
529 | .slave = &omap44xx_l4_abe_hwmod, | |
530 | .clk = "l3_div_ck", | |
531 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
532 | }; | |
533 | ||
534 | /* mpu -> l4_abe */ | |
535 | static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { | |
536 | .master = &omap44xx_mpu_hwmod, | |
537 | .slave = &omap44xx_l4_abe_hwmod, | |
538 | .clk = "ocp_abe_iclk", | |
539 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
540 | }; | |
541 | ||
542 | /* l4_abe slave ports */ | |
543 | static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { | |
407a6888 | 544 | &omap44xx_aess__l4_abe, |
8f25bdc5 | 545 | &omap44xx_dsp__l4_abe, |
55d2cb08 BC |
546 | &omap44xx_l3_main_1__l4_abe, |
547 | &omap44xx_mpu__l4_abe, | |
548 | }; | |
549 | ||
550 | static struct omap_hwmod omap44xx_l4_abe_hwmod = { | |
551 | .name = "l4_abe", | |
552 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 553 | .clkdm_name = "abe_clkdm", |
d0f0631d BC |
554 | .prcm = { |
555 | .omap4 = { | |
556 | .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, | |
557 | }, | |
558 | }, | |
55d2cb08 BC |
559 | .slaves = omap44xx_l4_abe_slaves, |
560 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves), | |
55d2cb08 BC |
561 | }; |
562 | ||
7e69ed97 | 563 | /* l4_cfg */ |
55d2cb08 BC |
564 | /* l3_main_1 -> l4_cfg */ |
565 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { | |
566 | .master = &omap44xx_l3_main_1_hwmod, | |
567 | .slave = &omap44xx_l4_cfg_hwmod, | |
568 | .clk = "l3_div_ck", | |
569 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
570 | }; | |
571 | ||
572 | /* l4_cfg slave ports */ | |
573 | static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = { | |
574 | &omap44xx_l3_main_1__l4_cfg, | |
575 | }; | |
576 | ||
577 | static struct omap_hwmod omap44xx_l4_cfg_hwmod = { | |
578 | .name = "l4_cfg", | |
579 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 580 | .clkdm_name = "l4_cfg_clkdm", |
d0f0631d BC |
581 | .prcm = { |
582 | .omap4 = { | |
583 | .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, | |
27bb00b5 | 584 | .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, |
d0f0631d BC |
585 | }, |
586 | }, | |
55d2cb08 BC |
587 | .slaves = omap44xx_l4_cfg_slaves, |
588 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves), | |
55d2cb08 BC |
589 | }; |
590 | ||
7e69ed97 | 591 | /* l4_per */ |
55d2cb08 BC |
592 | /* l3_main_2 -> l4_per */ |
593 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { | |
594 | .master = &omap44xx_l3_main_2_hwmod, | |
595 | .slave = &omap44xx_l4_per_hwmod, | |
596 | .clk = "l3_div_ck", | |
597 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
598 | }; | |
599 | ||
600 | /* l4_per slave ports */ | |
601 | static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = { | |
602 | &omap44xx_l3_main_2__l4_per, | |
603 | }; | |
604 | ||
605 | static struct omap_hwmod omap44xx_l4_per_hwmod = { | |
606 | .name = "l4_per", | |
607 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 608 | .clkdm_name = "l4_per_clkdm", |
d0f0631d BC |
609 | .prcm = { |
610 | .omap4 = { | |
611 | .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET, | |
27bb00b5 | 612 | .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, |
d0f0631d BC |
613 | }, |
614 | }, | |
55d2cb08 BC |
615 | .slaves = omap44xx_l4_per_slaves, |
616 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves), | |
55d2cb08 BC |
617 | }; |
618 | ||
7e69ed97 | 619 | /* l4_wkup */ |
55d2cb08 BC |
620 | /* l4_cfg -> l4_wkup */ |
621 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { | |
622 | .master = &omap44xx_l4_cfg_hwmod, | |
623 | .slave = &omap44xx_l4_wkup_hwmod, | |
624 | .clk = "l4_div_ck", | |
625 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
626 | }; | |
627 | ||
628 | /* l4_wkup slave ports */ | |
629 | static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = { | |
630 | &omap44xx_l4_cfg__l4_wkup, | |
631 | }; | |
632 | ||
633 | static struct omap_hwmod omap44xx_l4_wkup_hwmod = { | |
634 | .name = "l4_wkup", | |
635 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 636 | .clkdm_name = "l4_wkup_clkdm", |
d0f0631d BC |
637 | .prcm = { |
638 | .omap4 = { | |
639 | .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, | |
27bb00b5 | 640 | .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, |
d0f0631d BC |
641 | }, |
642 | }, | |
55d2cb08 BC |
643 | .slaves = omap44xx_l4_wkup_slaves, |
644 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves), | |
55d2cb08 BC |
645 | }; |
646 | ||
f776471f | 647 | /* |
3b54baad BC |
648 | * 'mpu_bus' class |
649 | * instance(s): mpu_private | |
f776471f | 650 | */ |
3b54baad | 651 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { |
fe13471c | 652 | .name = "mpu_bus", |
3b54baad | 653 | }; |
f776471f | 654 | |
7e69ed97 | 655 | /* mpu_private */ |
3b54baad BC |
656 | /* mpu -> mpu_private */ |
657 | static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { | |
658 | .master = &omap44xx_mpu_hwmod, | |
659 | .slave = &omap44xx_mpu_private_hwmod, | |
660 | .clk = "l3_div_ck", | |
661 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
662 | }; | |
663 | ||
664 | /* mpu_private slave ports */ | |
665 | static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = { | |
666 | &omap44xx_mpu__mpu_private, | |
667 | }; | |
668 | ||
669 | static struct omap_hwmod omap44xx_mpu_private_hwmod = { | |
670 | .name = "mpu_private", | |
671 | .class = &omap44xx_mpu_bus_hwmod_class, | |
a5322c6f | 672 | .clkdm_name = "mpuss_clkdm", |
3b54baad BC |
673 | .slaves = omap44xx_mpu_private_slaves, |
674 | .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves), | |
3b54baad BC |
675 | }; |
676 | ||
677 | /* | |
678 | * Modules omap_hwmod structures | |
679 | * | |
680 | * The following IPs are excluded for the moment because: | |
681 | * - They do not need an explicit SW control using omap_hwmod API. | |
682 | * - They still need to be validated with the driver | |
683 | * properly adapted to omap_hwmod / omap_device | |
684 | * | |
3b54baad BC |
685 | * c2c |
686 | * c2c_target_fw | |
687 | * cm_core | |
688 | * cm_core_aon | |
3b54baad BC |
689 | * ctrl_module_core |
690 | * ctrl_module_pad_core | |
691 | * ctrl_module_pad_wkup | |
692 | * ctrl_module_wkup | |
693 | * debugss | |
3b54baad BC |
694 | * efuse_ctrl_cust |
695 | * efuse_ctrl_std | |
696 | * elm | |
697 | * emif1 | |
698 | * emif2 | |
699 | * fdif | |
700 | * gpmc | |
701 | * gpu | |
702 | * hdq1w | |
00fe610b BC |
703 | * mcasp |
704 | * mpu_c0 | |
705 | * mpu_c1 | |
3b54baad BC |
706 | * ocmc_ram |
707 | * ocp2scp_usb_phy | |
708 | * ocp_wp_noc | |
3b54baad BC |
709 | * prcm_mpu |
710 | * prm | |
711 | * scrm | |
712 | * sl2if | |
713 | * slimbus1 | |
714 | * slimbus2 | |
3b54baad BC |
715 | * usb_host_fs |
716 | * usb_host_hs | |
3b54baad BC |
717 | * usb_phy_cm |
718 | * usb_tll_hs | |
719 | * usim | |
720 | */ | |
721 | ||
407a6888 BC |
722 | /* |
723 | * 'aess' class | |
724 | * audio engine sub system | |
725 | */ | |
726 | ||
727 | static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = { | |
728 | .rev_offs = 0x0000, | |
729 | .sysc_offs = 0x0010, | |
730 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
731 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
c614ebf6 BC |
732 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART | |
733 | MSTANDBY_SMART_WKUP), | |
407a6888 BC |
734 | .sysc_fields = &omap_hwmod_sysc_type2, |
735 | }; | |
736 | ||
737 | static struct omap_hwmod_class omap44xx_aess_hwmod_class = { | |
738 | .name = "aess", | |
739 | .sysc = &omap44xx_aess_sysc, | |
740 | }; | |
741 | ||
742 | /* aess */ | |
743 | static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { | |
744 | { .irq = 99 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 745 | { .irq = -1 } |
407a6888 BC |
746 | }; |
747 | ||
748 | static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { | |
749 | { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START }, | |
750 | { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START }, | |
751 | { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START }, | |
752 | { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START }, | |
753 | { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START }, | |
754 | { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START }, | |
755 | { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START }, | |
756 | { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 757 | { .dma_req = -1 } |
407a6888 BC |
758 | }; |
759 | ||
760 | /* aess master ports */ | |
761 | static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = { | |
762 | &omap44xx_aess__l4_abe, | |
763 | }; | |
764 | ||
765 | static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { | |
766 | { | |
767 | .pa_start = 0x401f1000, | |
768 | .pa_end = 0x401f13ff, | |
769 | .flags = ADDR_TYPE_RT | |
770 | }, | |
78183f3f | 771 | { } |
407a6888 BC |
772 | }; |
773 | ||
774 | /* l4_abe -> aess */ | |
775 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = { | |
776 | .master = &omap44xx_l4_abe_hwmod, | |
777 | .slave = &omap44xx_aess_hwmod, | |
778 | .clk = "ocp_abe_iclk", | |
779 | .addr = omap44xx_aess_addrs, | |
407a6888 BC |
780 | .user = OCP_USER_MPU, |
781 | }; | |
782 | ||
783 | static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { | |
784 | { | |
785 | .pa_start = 0x490f1000, | |
786 | .pa_end = 0x490f13ff, | |
787 | .flags = ADDR_TYPE_RT | |
788 | }, | |
78183f3f | 789 | { } |
407a6888 BC |
790 | }; |
791 | ||
792 | /* l4_abe -> aess (dma) */ | |
793 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { | |
794 | .master = &omap44xx_l4_abe_hwmod, | |
795 | .slave = &omap44xx_aess_hwmod, | |
796 | .clk = "ocp_abe_iclk", | |
797 | .addr = omap44xx_aess_dma_addrs, | |
407a6888 BC |
798 | .user = OCP_USER_SDMA, |
799 | }; | |
800 | ||
801 | /* aess slave ports */ | |
802 | static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = { | |
803 | &omap44xx_l4_abe__aess, | |
804 | &omap44xx_l4_abe__aess_dma, | |
805 | }; | |
806 | ||
807 | static struct omap_hwmod omap44xx_aess_hwmod = { | |
808 | .name = "aess", | |
809 | .class = &omap44xx_aess_hwmod_class, | |
a5322c6f | 810 | .clkdm_name = "abe_clkdm", |
407a6888 | 811 | .mpu_irqs = omap44xx_aess_irqs, |
407a6888 | 812 | .sdma_reqs = omap44xx_aess_sdma_reqs, |
407a6888 | 813 | .main_clk = "aess_fck", |
00fe610b | 814 | .prcm = { |
407a6888 | 815 | .omap4 = { |
d0f0631d | 816 | .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, |
27bb00b5 | 817 | .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, |
03fdefe5 | 818 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
819 | }, |
820 | }, | |
821 | .slaves = omap44xx_aess_slaves, | |
822 | .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves), | |
823 | .masters = omap44xx_aess_masters, | |
824 | .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters), | |
407a6888 BC |
825 | }; |
826 | ||
827 | /* | |
828 | * 'bandgap' class | |
829 | * bangap reference for ldo regulators | |
830 | */ | |
831 | ||
832 | static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = { | |
833 | .name = "bandgap", | |
834 | }; | |
835 | ||
836 | /* bandgap */ | |
837 | static struct omap_hwmod_opt_clk bandgap_opt_clks[] = { | |
838 | { .role = "fclk", .clk = "bandgap_fclk" }, | |
839 | }; | |
840 | ||
841 | static struct omap_hwmod omap44xx_bandgap_hwmod = { | |
842 | .name = "bandgap", | |
843 | .class = &omap44xx_bandgap_hwmod_class, | |
a5322c6f | 844 | .clkdm_name = "l4_wkup_clkdm", |
00fe610b | 845 | .prcm = { |
407a6888 | 846 | .omap4 = { |
d0f0631d | 847 | .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET, |
407a6888 BC |
848 | }, |
849 | }, | |
850 | .opt_clks = bandgap_opt_clks, | |
851 | .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks), | |
407a6888 BC |
852 | }; |
853 | ||
854 | /* | |
855 | * 'counter' class | |
856 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock | |
857 | */ | |
858 | ||
859 | static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = { | |
860 | .rev_offs = 0x0000, | |
861 | .sysc_offs = 0x0004, | |
862 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
863 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
864 | SIDLE_SMART_WKUP), | |
865 | .sysc_fields = &omap_hwmod_sysc_type1, | |
866 | }; | |
867 | ||
868 | static struct omap_hwmod_class omap44xx_counter_hwmod_class = { | |
869 | .name = "counter", | |
870 | .sysc = &omap44xx_counter_sysc, | |
871 | }; | |
872 | ||
873 | /* counter_32k */ | |
874 | static struct omap_hwmod omap44xx_counter_32k_hwmod; | |
875 | static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { | |
876 | { | |
877 | .pa_start = 0x4a304000, | |
878 | .pa_end = 0x4a30401f, | |
879 | .flags = ADDR_TYPE_RT | |
880 | }, | |
78183f3f | 881 | { } |
407a6888 BC |
882 | }; |
883 | ||
884 | /* l4_wkup -> counter_32k */ | |
885 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { | |
886 | .master = &omap44xx_l4_wkup_hwmod, | |
887 | .slave = &omap44xx_counter_32k_hwmod, | |
888 | .clk = "l4_wkup_clk_mux_ck", | |
889 | .addr = omap44xx_counter_32k_addrs, | |
407a6888 BC |
890 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
891 | }; | |
892 | ||
893 | /* counter_32k slave ports */ | |
894 | static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = { | |
895 | &omap44xx_l4_wkup__counter_32k, | |
896 | }; | |
897 | ||
898 | static struct omap_hwmod omap44xx_counter_32k_hwmod = { | |
899 | .name = "counter_32k", | |
900 | .class = &omap44xx_counter_hwmod_class, | |
a5322c6f | 901 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 BC |
902 | .flags = HWMOD_SWSUP_SIDLE, |
903 | .main_clk = "sys_32k_ck", | |
00fe610b | 904 | .prcm = { |
407a6888 | 905 | .omap4 = { |
d0f0631d | 906 | .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, |
27bb00b5 | 907 | .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, |
407a6888 BC |
908 | }, |
909 | }, | |
910 | .slaves = omap44xx_counter_32k_slaves, | |
911 | .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves), | |
407a6888 BC |
912 | }; |
913 | ||
d7cf5f33 BC |
914 | /* |
915 | * 'dma' class | |
916 | * dma controller for data exchange between memory to memory (i.e. internal or | |
917 | * external memory) and gp peripherals to memory or memory to gp peripherals | |
918 | */ | |
919 | ||
920 | static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { | |
921 | .rev_offs = 0x0000, | |
922 | .sysc_offs = 0x002c, | |
923 | .syss_offs = 0x0028, | |
924 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
925 | SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
926 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
927 | SYSS_HAS_RESET_STATUS), | |
928 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
929 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
930 | .sysc_fields = &omap_hwmod_sysc_type1, | |
931 | }; | |
932 | ||
933 | static struct omap_hwmod_class omap44xx_dma_hwmod_class = { | |
934 | .name = "dma", | |
935 | .sysc = &omap44xx_dma_sysc, | |
936 | }; | |
937 | ||
938 | /* dma dev_attr */ | |
939 | static struct omap_dma_dev_attr dma_dev_attr = { | |
940 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
941 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
942 | .lch_count = 32, | |
943 | }; | |
944 | ||
945 | /* dma_system */ | |
946 | static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { | |
947 | { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, | |
948 | { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, | |
949 | { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, | |
950 | { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 951 | { .irq = -1 } |
d7cf5f33 BC |
952 | }; |
953 | ||
954 | /* dma_system master ports */ | |
955 | static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = { | |
956 | &omap44xx_dma_system__l3_main_2, | |
957 | }; | |
958 | ||
959 | static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { | |
960 | { | |
961 | .pa_start = 0x4a056000, | |
1286eeb2 | 962 | .pa_end = 0x4a056fff, |
d7cf5f33 BC |
963 | .flags = ADDR_TYPE_RT |
964 | }, | |
78183f3f | 965 | { } |
d7cf5f33 BC |
966 | }; |
967 | ||
968 | /* l4_cfg -> dma_system */ | |
969 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { | |
970 | .master = &omap44xx_l4_cfg_hwmod, | |
971 | .slave = &omap44xx_dma_system_hwmod, | |
972 | .clk = "l4_div_ck", | |
973 | .addr = omap44xx_dma_system_addrs, | |
d7cf5f33 BC |
974 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
975 | }; | |
976 | ||
977 | /* dma_system slave ports */ | |
978 | static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = { | |
979 | &omap44xx_l4_cfg__dma_system, | |
980 | }; | |
981 | ||
982 | static struct omap_hwmod omap44xx_dma_system_hwmod = { | |
983 | .name = "dma_system", | |
984 | .class = &omap44xx_dma_hwmod_class, | |
a5322c6f | 985 | .clkdm_name = "l3_dma_clkdm", |
d7cf5f33 | 986 | .mpu_irqs = omap44xx_dma_system_irqs, |
d7cf5f33 BC |
987 | .main_clk = "l3_div_ck", |
988 | .prcm = { | |
989 | .omap4 = { | |
d0f0631d | 990 | .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET, |
27bb00b5 | 991 | .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET, |
d7cf5f33 BC |
992 | }, |
993 | }, | |
994 | .dev_attr = &dma_dev_attr, | |
995 | .slaves = omap44xx_dma_system_slaves, | |
996 | .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves), | |
997 | .masters = omap44xx_dma_system_masters, | |
998 | .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters), | |
d7cf5f33 BC |
999 | }; |
1000 | ||
8ca476da BC |
1001 | /* |
1002 | * 'dmic' class | |
1003 | * digital microphone controller | |
1004 | */ | |
1005 | ||
1006 | static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = { | |
1007 | .rev_offs = 0x0000, | |
1008 | .sysc_offs = 0x0010, | |
1009 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
1010 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1011 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1012 | SIDLE_SMART_WKUP), | |
1013 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1014 | }; | |
1015 | ||
1016 | static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { | |
1017 | .name = "dmic", | |
1018 | .sysc = &omap44xx_dmic_sysc, | |
1019 | }; | |
1020 | ||
1021 | /* dmic */ | |
1022 | static struct omap_hwmod omap44xx_dmic_hwmod; | |
1023 | static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { | |
1024 | { .irq = 114 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1025 | { .irq = -1 } |
8ca476da BC |
1026 | }; |
1027 | ||
1028 | static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { | |
1029 | { .dma_req = 66 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1030 | { .dma_req = -1 } |
8ca476da BC |
1031 | }; |
1032 | ||
1033 | static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { | |
1034 | { | |
6af486e2 | 1035 | .name = "mpu", |
8ca476da BC |
1036 | .pa_start = 0x4012e000, |
1037 | .pa_end = 0x4012e07f, | |
1038 | .flags = ADDR_TYPE_RT | |
1039 | }, | |
78183f3f | 1040 | { } |
8ca476da BC |
1041 | }; |
1042 | ||
1043 | /* l4_abe -> dmic */ | |
1044 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { | |
1045 | .master = &omap44xx_l4_abe_hwmod, | |
1046 | .slave = &omap44xx_dmic_hwmod, | |
1047 | .clk = "ocp_abe_iclk", | |
1048 | .addr = omap44xx_dmic_addrs, | |
8ca476da BC |
1049 | .user = OCP_USER_MPU, |
1050 | }; | |
1051 | ||
1052 | static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { | |
1053 | { | |
6af486e2 | 1054 | .name = "dma", |
8ca476da BC |
1055 | .pa_start = 0x4902e000, |
1056 | .pa_end = 0x4902e07f, | |
1057 | .flags = ADDR_TYPE_RT | |
1058 | }, | |
78183f3f | 1059 | { } |
8ca476da BC |
1060 | }; |
1061 | ||
1062 | /* l4_abe -> dmic (dma) */ | |
1063 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { | |
1064 | .master = &omap44xx_l4_abe_hwmod, | |
1065 | .slave = &omap44xx_dmic_hwmod, | |
1066 | .clk = "ocp_abe_iclk", | |
1067 | .addr = omap44xx_dmic_dma_addrs, | |
8ca476da BC |
1068 | .user = OCP_USER_SDMA, |
1069 | }; | |
1070 | ||
1071 | /* dmic slave ports */ | |
1072 | static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = { | |
1073 | &omap44xx_l4_abe__dmic, | |
1074 | &omap44xx_l4_abe__dmic_dma, | |
1075 | }; | |
1076 | ||
1077 | static struct omap_hwmod omap44xx_dmic_hwmod = { | |
1078 | .name = "dmic", | |
1079 | .class = &omap44xx_dmic_hwmod_class, | |
a5322c6f | 1080 | .clkdm_name = "abe_clkdm", |
8ca476da | 1081 | .mpu_irqs = omap44xx_dmic_irqs, |
8ca476da | 1082 | .sdma_reqs = omap44xx_dmic_sdma_reqs, |
8ca476da | 1083 | .main_clk = "dmic_fck", |
00fe610b | 1084 | .prcm = { |
8ca476da | 1085 | .omap4 = { |
d0f0631d | 1086 | .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, |
27bb00b5 | 1087 | .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET, |
03fdefe5 | 1088 | .modulemode = MODULEMODE_SWCTRL, |
8ca476da BC |
1089 | }, |
1090 | }, | |
1091 | .slaves = omap44xx_dmic_slaves, | |
1092 | .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves), | |
8ca476da BC |
1093 | }; |
1094 | ||
8f25bdc5 BC |
1095 | /* |
1096 | * 'dsp' class | |
1097 | * dsp sub-system | |
1098 | */ | |
1099 | ||
1100 | static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { | |
fe13471c | 1101 | .name = "dsp", |
8f25bdc5 BC |
1102 | }; |
1103 | ||
1104 | /* dsp */ | |
1105 | static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { | |
1106 | { .irq = 28 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1107 | { .irq = -1 } |
8f25bdc5 BC |
1108 | }; |
1109 | ||
1110 | static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { | |
1111 | { .name = "mmu_cache", .rst_shift = 1 }, | |
1112 | }; | |
1113 | ||
1114 | static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = { | |
1115 | { .name = "dsp", .rst_shift = 0 }, | |
1116 | }; | |
1117 | ||
1118 | /* dsp -> iva */ | |
1119 | static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { | |
1120 | .master = &omap44xx_dsp_hwmod, | |
1121 | .slave = &omap44xx_iva_hwmod, | |
1122 | .clk = "dpll_iva_m5x2_ck", | |
1123 | }; | |
1124 | ||
1125 | /* dsp master ports */ | |
1126 | static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = { | |
1127 | &omap44xx_dsp__l3_main_1, | |
1128 | &omap44xx_dsp__l4_abe, | |
1129 | &omap44xx_dsp__iva, | |
1130 | }; | |
1131 | ||
1132 | /* l4_cfg -> dsp */ | |
1133 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { | |
1134 | .master = &omap44xx_l4_cfg_hwmod, | |
1135 | .slave = &omap44xx_dsp_hwmod, | |
1136 | .clk = "l4_div_ck", | |
1137 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1138 | }; | |
1139 | ||
1140 | /* dsp slave ports */ | |
1141 | static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = { | |
1142 | &omap44xx_l4_cfg__dsp, | |
1143 | }; | |
1144 | ||
1145 | /* Pseudo hwmod for reset control purpose only */ | |
1146 | static struct omap_hwmod omap44xx_dsp_c0_hwmod = { | |
1147 | .name = "dsp_c0", | |
1148 | .class = &omap44xx_dsp_hwmod_class, | |
a5322c6f | 1149 | .clkdm_name = "tesla_clkdm", |
8f25bdc5 BC |
1150 | .flags = HWMOD_INIT_NO_RESET, |
1151 | .rst_lines = omap44xx_dsp_c0_resets, | |
1152 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets), | |
1153 | .prcm = { | |
1154 | .omap4 = { | |
eaac329d | 1155 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, |
8f25bdc5 BC |
1156 | }, |
1157 | }, | |
8f25bdc5 BC |
1158 | }; |
1159 | ||
1160 | static struct omap_hwmod omap44xx_dsp_hwmod = { | |
1161 | .name = "dsp", | |
1162 | .class = &omap44xx_dsp_hwmod_class, | |
a5322c6f | 1163 | .clkdm_name = "tesla_clkdm", |
8f25bdc5 | 1164 | .mpu_irqs = omap44xx_dsp_irqs, |
8f25bdc5 BC |
1165 | .rst_lines = omap44xx_dsp_resets, |
1166 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), | |
1167 | .main_clk = "dsp_fck", | |
1168 | .prcm = { | |
1169 | .omap4 = { | |
d0f0631d | 1170 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, |
eaac329d | 1171 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, |
27bb00b5 | 1172 | .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, |
03fdefe5 | 1173 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
1174 | }, |
1175 | }, | |
1176 | .slaves = omap44xx_dsp_slaves, | |
1177 | .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves), | |
1178 | .masters = omap44xx_dsp_masters, | |
1179 | .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters), | |
8f25bdc5 BC |
1180 | }; |
1181 | ||
d63bd74f BC |
1182 | /* |
1183 | * 'dss' class | |
1184 | * display sub-system | |
1185 | */ | |
1186 | ||
1187 | static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = { | |
1188 | .rev_offs = 0x0000, | |
1189 | .syss_offs = 0x0014, | |
1190 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
1191 | }; | |
1192 | ||
1193 | static struct omap_hwmod_class omap44xx_dss_hwmod_class = { | |
1194 | .name = "dss", | |
1195 | .sysc = &omap44xx_dss_sysc, | |
13662dc5 | 1196 | .reset = omap_dss_reset, |
d63bd74f BC |
1197 | }; |
1198 | ||
1199 | /* dss */ | |
1200 | /* dss master ports */ | |
1201 | static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = { | |
1202 | &omap44xx_dss__l3_main_1, | |
1203 | }; | |
1204 | ||
1205 | static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { | |
1206 | { | |
1207 | .pa_start = 0x58000000, | |
1208 | .pa_end = 0x5800007f, | |
1209 | .flags = ADDR_TYPE_RT | |
1210 | }, | |
78183f3f | 1211 | { } |
d63bd74f BC |
1212 | }; |
1213 | ||
1214 | /* l3_main_2 -> dss */ | |
1215 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { | |
1216 | .master = &omap44xx_l3_main_2_hwmod, | |
1217 | .slave = &omap44xx_dss_hwmod, | |
da7cdfac | 1218 | .clk = "dss_fck", |
d63bd74f | 1219 | .addr = omap44xx_dss_dma_addrs, |
d63bd74f BC |
1220 | .user = OCP_USER_SDMA, |
1221 | }; | |
1222 | ||
1223 | static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { | |
1224 | { | |
1225 | .pa_start = 0x48040000, | |
1226 | .pa_end = 0x4804007f, | |
1227 | .flags = ADDR_TYPE_RT | |
1228 | }, | |
78183f3f | 1229 | { } |
d63bd74f BC |
1230 | }; |
1231 | ||
1232 | /* l4_per -> dss */ | |
1233 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { | |
1234 | .master = &omap44xx_l4_per_hwmod, | |
1235 | .slave = &omap44xx_dss_hwmod, | |
1236 | .clk = "l4_div_ck", | |
1237 | .addr = omap44xx_dss_addrs, | |
d63bd74f BC |
1238 | .user = OCP_USER_MPU, |
1239 | }; | |
1240 | ||
1241 | /* dss slave ports */ | |
1242 | static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = { | |
1243 | &omap44xx_l3_main_2__dss, | |
1244 | &omap44xx_l4_per__dss, | |
1245 | }; | |
1246 | ||
1247 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |
1248 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
1249 | { .role = "tv_clk", .clk = "dss_tv_clk" }, | |
4d0698d9 | 1250 | { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, |
d63bd74f BC |
1251 | }; |
1252 | ||
1253 | static struct omap_hwmod omap44xx_dss_hwmod = { | |
1254 | .name = "dss_core", | |
37ad0855 | 1255 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
d63bd74f | 1256 | .class = &omap44xx_dss_hwmod_class, |
a5322c6f | 1257 | .clkdm_name = "l3_dss_clkdm", |
da7cdfac | 1258 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
1259 | .prcm = { |
1260 | .omap4 = { | |
d0f0631d | 1261 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 1262 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
1263 | }, |
1264 | }, | |
1265 | .opt_clks = dss_opt_clks, | |
1266 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
1267 | .slaves = omap44xx_dss_slaves, | |
1268 | .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves), | |
1269 | .masters = omap44xx_dss_masters, | |
1270 | .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters), | |
d63bd74f BC |
1271 | }; |
1272 | ||
1273 | /* | |
1274 | * 'dispc' class | |
1275 | * display controller | |
1276 | */ | |
1277 | ||
1278 | static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = { | |
1279 | .rev_offs = 0x0000, | |
1280 | .sysc_offs = 0x0010, | |
1281 | .syss_offs = 0x0014, | |
1282 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1283 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | | |
1284 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1285 | SYSS_HAS_RESET_STATUS), | |
1286 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1287 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1288 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1289 | }; | |
1290 | ||
1291 | static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { | |
1292 | .name = "dispc", | |
1293 | .sysc = &omap44xx_dispc_sysc, | |
1294 | }; | |
1295 | ||
1296 | /* dss_dispc */ | |
1297 | static struct omap_hwmod omap44xx_dss_dispc_hwmod; | |
1298 | static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { | |
1299 | { .irq = 25 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1300 | { .irq = -1 } |
d63bd74f BC |
1301 | }; |
1302 | ||
1303 | static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { | |
1304 | { .dma_req = 5 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1305 | { .dma_req = -1 } |
d63bd74f BC |
1306 | }; |
1307 | ||
1308 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { | |
1309 | { | |
1310 | .pa_start = 0x58001000, | |
1311 | .pa_end = 0x58001fff, | |
1312 | .flags = ADDR_TYPE_RT | |
1313 | }, | |
78183f3f | 1314 | { } |
d63bd74f BC |
1315 | }; |
1316 | ||
1317 | /* l3_main_2 -> dss_dispc */ | |
1318 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { | |
1319 | .master = &omap44xx_l3_main_2_hwmod, | |
1320 | .slave = &omap44xx_dss_dispc_hwmod, | |
da7cdfac | 1321 | .clk = "dss_fck", |
d63bd74f | 1322 | .addr = omap44xx_dss_dispc_dma_addrs, |
d63bd74f BC |
1323 | .user = OCP_USER_SDMA, |
1324 | }; | |
1325 | ||
1326 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { | |
1327 | { | |
1328 | .pa_start = 0x48041000, | |
1329 | .pa_end = 0x48041fff, | |
1330 | .flags = ADDR_TYPE_RT | |
1331 | }, | |
78183f3f | 1332 | { } |
d63bd74f BC |
1333 | }; |
1334 | ||
b923d40d AT |
1335 | static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { |
1336 | .manager_count = 3, | |
1337 | .has_framedonetv_irq = 1 | |
1338 | }; | |
1339 | ||
d63bd74f BC |
1340 | /* l4_per -> dss_dispc */ |
1341 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { | |
1342 | .master = &omap44xx_l4_per_hwmod, | |
1343 | .slave = &omap44xx_dss_dispc_hwmod, | |
1344 | .clk = "l4_div_ck", | |
1345 | .addr = omap44xx_dss_dispc_addrs, | |
d63bd74f BC |
1346 | .user = OCP_USER_MPU, |
1347 | }; | |
1348 | ||
1349 | /* dss_dispc slave ports */ | |
1350 | static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = { | |
1351 | &omap44xx_l3_main_2__dss_dispc, | |
1352 | &omap44xx_l4_per__dss_dispc, | |
1353 | }; | |
1354 | ||
1355 | static struct omap_hwmod omap44xx_dss_dispc_hwmod = { | |
1356 | .name = "dss_dispc", | |
1357 | .class = &omap44xx_dispc_hwmod_class, | |
a5322c6f | 1358 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 1359 | .mpu_irqs = omap44xx_dss_dispc_irqs, |
d63bd74f | 1360 | .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, |
da7cdfac | 1361 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
1362 | .prcm = { |
1363 | .omap4 = { | |
d0f0631d | 1364 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 1365 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
1366 | }, |
1367 | }, | |
1368 | .slaves = omap44xx_dss_dispc_slaves, | |
1369 | .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves), | |
b923d40d | 1370 | .dev_attr = &omap44xx_dss_dispc_dev_attr |
d63bd74f BC |
1371 | }; |
1372 | ||
1373 | /* | |
1374 | * 'dsi' class | |
1375 | * display serial interface controller | |
1376 | */ | |
1377 | ||
1378 | static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = { | |
1379 | .rev_offs = 0x0000, | |
1380 | .sysc_offs = 0x0010, | |
1381 | .syss_offs = 0x0014, | |
1382 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1383 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
1384 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1385 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1386 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1387 | }; | |
1388 | ||
1389 | static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { | |
1390 | .name = "dsi", | |
1391 | .sysc = &omap44xx_dsi_sysc, | |
1392 | }; | |
1393 | ||
1394 | /* dss_dsi1 */ | |
1395 | static struct omap_hwmod omap44xx_dss_dsi1_hwmod; | |
1396 | static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { | |
1397 | { .irq = 53 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1398 | { .irq = -1 } |
d63bd74f BC |
1399 | }; |
1400 | ||
1401 | static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { | |
1402 | { .dma_req = 74 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1403 | { .dma_req = -1 } |
d63bd74f BC |
1404 | }; |
1405 | ||
1406 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { | |
1407 | { | |
1408 | .pa_start = 0x58004000, | |
1409 | .pa_end = 0x580041ff, | |
1410 | .flags = ADDR_TYPE_RT | |
1411 | }, | |
78183f3f | 1412 | { } |
d63bd74f BC |
1413 | }; |
1414 | ||
1415 | /* l3_main_2 -> dss_dsi1 */ | |
1416 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { | |
1417 | .master = &omap44xx_l3_main_2_hwmod, | |
1418 | .slave = &omap44xx_dss_dsi1_hwmod, | |
da7cdfac | 1419 | .clk = "dss_fck", |
d63bd74f | 1420 | .addr = omap44xx_dss_dsi1_dma_addrs, |
d63bd74f BC |
1421 | .user = OCP_USER_SDMA, |
1422 | }; | |
1423 | ||
1424 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { | |
1425 | { | |
1426 | .pa_start = 0x48044000, | |
1427 | .pa_end = 0x480441ff, | |
1428 | .flags = ADDR_TYPE_RT | |
1429 | }, | |
78183f3f | 1430 | { } |
d63bd74f BC |
1431 | }; |
1432 | ||
1433 | /* l4_per -> dss_dsi1 */ | |
1434 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { | |
1435 | .master = &omap44xx_l4_per_hwmod, | |
1436 | .slave = &omap44xx_dss_dsi1_hwmod, | |
1437 | .clk = "l4_div_ck", | |
1438 | .addr = omap44xx_dss_dsi1_addrs, | |
d63bd74f BC |
1439 | .user = OCP_USER_MPU, |
1440 | }; | |
1441 | ||
1442 | /* dss_dsi1 slave ports */ | |
1443 | static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = { | |
1444 | &omap44xx_l3_main_2__dss_dsi1, | |
1445 | &omap44xx_l4_per__dss_dsi1, | |
1446 | }; | |
1447 | ||
3a23aafc TV |
1448 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { |
1449 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
1450 | }; | |
1451 | ||
d63bd74f BC |
1452 | static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { |
1453 | .name = "dss_dsi1", | |
1454 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 1455 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 1456 | .mpu_irqs = omap44xx_dss_dsi1_irqs, |
d63bd74f | 1457 | .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, |
da7cdfac | 1458 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
1459 | .prcm = { |
1460 | .omap4 = { | |
d0f0631d | 1461 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 1462 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
1463 | }, |
1464 | }, | |
3a23aafc TV |
1465 | .opt_clks = dss_dsi1_opt_clks, |
1466 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
d63bd74f BC |
1467 | .slaves = omap44xx_dss_dsi1_slaves, |
1468 | .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves), | |
d63bd74f BC |
1469 | }; |
1470 | ||
1471 | /* dss_dsi2 */ | |
1472 | static struct omap_hwmod omap44xx_dss_dsi2_hwmod; | |
1473 | static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { | |
1474 | { .irq = 84 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1475 | { .irq = -1 } |
d63bd74f BC |
1476 | }; |
1477 | ||
1478 | static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { | |
1479 | { .dma_req = 83 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1480 | { .dma_req = -1 } |
d63bd74f BC |
1481 | }; |
1482 | ||
1483 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { | |
1484 | { | |
1485 | .pa_start = 0x58005000, | |
1486 | .pa_end = 0x580051ff, | |
1487 | .flags = ADDR_TYPE_RT | |
1488 | }, | |
78183f3f | 1489 | { } |
d63bd74f BC |
1490 | }; |
1491 | ||
1492 | /* l3_main_2 -> dss_dsi2 */ | |
1493 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { | |
1494 | .master = &omap44xx_l3_main_2_hwmod, | |
1495 | .slave = &omap44xx_dss_dsi2_hwmod, | |
da7cdfac | 1496 | .clk = "dss_fck", |
d63bd74f | 1497 | .addr = omap44xx_dss_dsi2_dma_addrs, |
d63bd74f BC |
1498 | .user = OCP_USER_SDMA, |
1499 | }; | |
1500 | ||
1501 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { | |
1502 | { | |
1503 | .pa_start = 0x48045000, | |
1504 | .pa_end = 0x480451ff, | |
1505 | .flags = ADDR_TYPE_RT | |
1506 | }, | |
78183f3f | 1507 | { } |
d63bd74f BC |
1508 | }; |
1509 | ||
1510 | /* l4_per -> dss_dsi2 */ | |
1511 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { | |
1512 | .master = &omap44xx_l4_per_hwmod, | |
1513 | .slave = &omap44xx_dss_dsi2_hwmod, | |
1514 | .clk = "l4_div_ck", | |
1515 | .addr = omap44xx_dss_dsi2_addrs, | |
d63bd74f BC |
1516 | .user = OCP_USER_MPU, |
1517 | }; | |
1518 | ||
1519 | /* dss_dsi2 slave ports */ | |
1520 | static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = { | |
1521 | &omap44xx_l3_main_2__dss_dsi2, | |
1522 | &omap44xx_l4_per__dss_dsi2, | |
1523 | }; | |
1524 | ||
3a23aafc TV |
1525 | static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { |
1526 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
1527 | }; | |
1528 | ||
d63bd74f BC |
1529 | static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { |
1530 | .name = "dss_dsi2", | |
1531 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 1532 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 1533 | .mpu_irqs = omap44xx_dss_dsi2_irqs, |
d63bd74f | 1534 | .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, |
da7cdfac | 1535 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
1536 | .prcm = { |
1537 | .omap4 = { | |
d0f0631d | 1538 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 1539 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
1540 | }, |
1541 | }, | |
3a23aafc TV |
1542 | .opt_clks = dss_dsi2_opt_clks, |
1543 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), | |
d63bd74f BC |
1544 | .slaves = omap44xx_dss_dsi2_slaves, |
1545 | .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves), | |
d63bd74f BC |
1546 | }; |
1547 | ||
1548 | /* | |
1549 | * 'hdmi' class | |
1550 | * hdmi controller | |
1551 | */ | |
1552 | ||
1553 | static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = { | |
1554 | .rev_offs = 0x0000, | |
1555 | .sysc_offs = 0x0010, | |
1556 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1557 | SYSC_HAS_SOFTRESET), | |
1558 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1559 | SIDLE_SMART_WKUP), | |
1560 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1561 | }; | |
1562 | ||
1563 | static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { | |
1564 | .name = "hdmi", | |
1565 | .sysc = &omap44xx_hdmi_sysc, | |
1566 | }; | |
1567 | ||
1568 | /* dss_hdmi */ | |
1569 | static struct omap_hwmod omap44xx_dss_hdmi_hwmod; | |
1570 | static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { | |
1571 | { .irq = 101 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1572 | { .irq = -1 } |
d63bd74f BC |
1573 | }; |
1574 | ||
1575 | static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { | |
1576 | { .dma_req = 75 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1577 | { .dma_req = -1 } |
d63bd74f BC |
1578 | }; |
1579 | ||
1580 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { | |
1581 | { | |
1582 | .pa_start = 0x58006000, | |
1583 | .pa_end = 0x58006fff, | |
1584 | .flags = ADDR_TYPE_RT | |
1585 | }, | |
78183f3f | 1586 | { } |
d63bd74f BC |
1587 | }; |
1588 | ||
1589 | /* l3_main_2 -> dss_hdmi */ | |
1590 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { | |
1591 | .master = &omap44xx_l3_main_2_hwmod, | |
1592 | .slave = &omap44xx_dss_hdmi_hwmod, | |
da7cdfac | 1593 | .clk = "dss_fck", |
d63bd74f | 1594 | .addr = omap44xx_dss_hdmi_dma_addrs, |
d63bd74f BC |
1595 | .user = OCP_USER_SDMA, |
1596 | }; | |
1597 | ||
1598 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { | |
1599 | { | |
1600 | .pa_start = 0x48046000, | |
1601 | .pa_end = 0x48046fff, | |
1602 | .flags = ADDR_TYPE_RT | |
1603 | }, | |
78183f3f | 1604 | { } |
d63bd74f BC |
1605 | }; |
1606 | ||
1607 | /* l4_per -> dss_hdmi */ | |
1608 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { | |
1609 | .master = &omap44xx_l4_per_hwmod, | |
1610 | .slave = &omap44xx_dss_hdmi_hwmod, | |
1611 | .clk = "l4_div_ck", | |
1612 | .addr = omap44xx_dss_hdmi_addrs, | |
d63bd74f BC |
1613 | .user = OCP_USER_MPU, |
1614 | }; | |
1615 | ||
1616 | /* dss_hdmi slave ports */ | |
1617 | static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = { | |
1618 | &omap44xx_l3_main_2__dss_hdmi, | |
1619 | &omap44xx_l4_per__dss_hdmi, | |
1620 | }; | |
1621 | ||
3a23aafc TV |
1622 | static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { |
1623 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
1624 | }; | |
1625 | ||
d63bd74f BC |
1626 | static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { |
1627 | .name = "dss_hdmi", | |
1628 | .class = &omap44xx_hdmi_hwmod_class, | |
a5322c6f | 1629 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 1630 | .mpu_irqs = omap44xx_dss_hdmi_irqs, |
d63bd74f | 1631 | .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, |
4d0698d9 | 1632 | .main_clk = "dss_48mhz_clk", |
d63bd74f BC |
1633 | .prcm = { |
1634 | .omap4 = { | |
d0f0631d | 1635 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 1636 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
1637 | }, |
1638 | }, | |
3a23aafc TV |
1639 | .opt_clks = dss_hdmi_opt_clks, |
1640 | .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), | |
d63bd74f BC |
1641 | .slaves = omap44xx_dss_hdmi_slaves, |
1642 | .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves), | |
d63bd74f BC |
1643 | }; |
1644 | ||
1645 | /* | |
1646 | * 'rfbi' class | |
1647 | * remote frame buffer interface | |
1648 | */ | |
1649 | ||
1650 | static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = { | |
1651 | .rev_offs = 0x0000, | |
1652 | .sysc_offs = 0x0010, | |
1653 | .syss_offs = 0x0014, | |
1654 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
1655 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1656 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1657 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1658 | }; | |
1659 | ||
1660 | static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { | |
1661 | .name = "rfbi", | |
1662 | .sysc = &omap44xx_rfbi_sysc, | |
1663 | }; | |
1664 | ||
1665 | /* dss_rfbi */ | |
1666 | static struct omap_hwmod omap44xx_dss_rfbi_hwmod; | |
1667 | static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { | |
1668 | { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1669 | { .dma_req = -1 } |
d63bd74f BC |
1670 | }; |
1671 | ||
1672 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { | |
1673 | { | |
1674 | .pa_start = 0x58002000, | |
1675 | .pa_end = 0x580020ff, | |
1676 | .flags = ADDR_TYPE_RT | |
1677 | }, | |
78183f3f | 1678 | { } |
d63bd74f BC |
1679 | }; |
1680 | ||
1681 | /* l3_main_2 -> dss_rfbi */ | |
1682 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { | |
1683 | .master = &omap44xx_l3_main_2_hwmod, | |
1684 | .slave = &omap44xx_dss_rfbi_hwmod, | |
da7cdfac | 1685 | .clk = "dss_fck", |
d63bd74f | 1686 | .addr = omap44xx_dss_rfbi_dma_addrs, |
d63bd74f BC |
1687 | .user = OCP_USER_SDMA, |
1688 | }; | |
1689 | ||
1690 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { | |
1691 | { | |
1692 | .pa_start = 0x48042000, | |
1693 | .pa_end = 0x480420ff, | |
1694 | .flags = ADDR_TYPE_RT | |
1695 | }, | |
78183f3f | 1696 | { } |
d63bd74f BC |
1697 | }; |
1698 | ||
1699 | /* l4_per -> dss_rfbi */ | |
1700 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { | |
1701 | .master = &omap44xx_l4_per_hwmod, | |
1702 | .slave = &omap44xx_dss_rfbi_hwmod, | |
1703 | .clk = "l4_div_ck", | |
1704 | .addr = omap44xx_dss_rfbi_addrs, | |
d63bd74f BC |
1705 | .user = OCP_USER_MPU, |
1706 | }; | |
1707 | ||
1708 | /* dss_rfbi slave ports */ | |
1709 | static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = { | |
1710 | &omap44xx_l3_main_2__dss_rfbi, | |
1711 | &omap44xx_l4_per__dss_rfbi, | |
1712 | }; | |
1713 | ||
3a23aafc TV |
1714 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
1715 | { .role = "ick", .clk = "dss_fck" }, | |
1716 | }; | |
1717 | ||
d63bd74f BC |
1718 | static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { |
1719 | .name = "dss_rfbi", | |
1720 | .class = &omap44xx_rfbi_hwmod_class, | |
a5322c6f | 1721 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 1722 | .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, |
da7cdfac | 1723 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
1724 | .prcm = { |
1725 | .omap4 = { | |
d0f0631d | 1726 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 1727 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
1728 | }, |
1729 | }, | |
3a23aafc TV |
1730 | .opt_clks = dss_rfbi_opt_clks, |
1731 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
d63bd74f BC |
1732 | .slaves = omap44xx_dss_rfbi_slaves, |
1733 | .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves), | |
d63bd74f BC |
1734 | }; |
1735 | ||
1736 | /* | |
1737 | * 'venc' class | |
1738 | * video encoder | |
1739 | */ | |
1740 | ||
1741 | static struct omap_hwmod_class omap44xx_venc_hwmod_class = { | |
1742 | .name = "venc", | |
1743 | }; | |
1744 | ||
1745 | /* dss_venc */ | |
1746 | static struct omap_hwmod omap44xx_dss_venc_hwmod; | |
1747 | static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { | |
1748 | { | |
1749 | .pa_start = 0x58003000, | |
1750 | .pa_end = 0x580030ff, | |
1751 | .flags = ADDR_TYPE_RT | |
1752 | }, | |
78183f3f | 1753 | { } |
d63bd74f BC |
1754 | }; |
1755 | ||
1756 | /* l3_main_2 -> dss_venc */ | |
1757 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { | |
1758 | .master = &omap44xx_l3_main_2_hwmod, | |
1759 | .slave = &omap44xx_dss_venc_hwmod, | |
da7cdfac | 1760 | .clk = "dss_fck", |
d63bd74f | 1761 | .addr = omap44xx_dss_venc_dma_addrs, |
d63bd74f BC |
1762 | .user = OCP_USER_SDMA, |
1763 | }; | |
1764 | ||
1765 | static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { | |
1766 | { | |
1767 | .pa_start = 0x48043000, | |
1768 | .pa_end = 0x480430ff, | |
1769 | .flags = ADDR_TYPE_RT | |
1770 | }, | |
78183f3f | 1771 | { } |
d63bd74f BC |
1772 | }; |
1773 | ||
1774 | /* l4_per -> dss_venc */ | |
1775 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { | |
1776 | .master = &omap44xx_l4_per_hwmod, | |
1777 | .slave = &omap44xx_dss_venc_hwmod, | |
1778 | .clk = "l4_div_ck", | |
1779 | .addr = omap44xx_dss_venc_addrs, | |
d63bd74f BC |
1780 | .user = OCP_USER_MPU, |
1781 | }; | |
1782 | ||
1783 | /* dss_venc slave ports */ | |
1784 | static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = { | |
1785 | &omap44xx_l3_main_2__dss_venc, | |
1786 | &omap44xx_l4_per__dss_venc, | |
1787 | }; | |
1788 | ||
1789 | static struct omap_hwmod omap44xx_dss_venc_hwmod = { | |
1790 | .name = "dss_venc", | |
1791 | .class = &omap44xx_venc_hwmod_class, | |
a5322c6f | 1792 | .clkdm_name = "l3_dss_clkdm", |
4d0698d9 | 1793 | .main_clk = "dss_tv_clk", |
d63bd74f BC |
1794 | .prcm = { |
1795 | .omap4 = { | |
d0f0631d | 1796 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 1797 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
1798 | }, |
1799 | }, | |
1800 | .slaves = omap44xx_dss_venc_slaves, | |
1801 | .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves), | |
d63bd74f BC |
1802 | }; |
1803 | ||
3b54baad BC |
1804 | /* |
1805 | * 'gpio' class | |
1806 | * general purpose io module | |
1807 | */ | |
1808 | ||
1809 | static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { | |
1810 | .rev_offs = 0x0000, | |
f776471f | 1811 | .sysc_offs = 0x0010, |
3b54baad | 1812 | .syss_offs = 0x0114, |
0cfe8751 BC |
1813 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
1814 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1815 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
1816 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1817 | SIDLE_SMART_WKUP), | |
f776471f BC |
1818 | .sysc_fields = &omap_hwmod_sysc_type1, |
1819 | }; | |
1820 | ||
3b54baad | 1821 | static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { |
fe13471c BC |
1822 | .name = "gpio", |
1823 | .sysc = &omap44xx_gpio_sysc, | |
1824 | .rev = 2, | |
f776471f BC |
1825 | }; |
1826 | ||
3b54baad BC |
1827 | /* gpio dev_attr */ |
1828 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
fe13471c BC |
1829 | .bank_width = 32, |
1830 | .dbck_flag = true, | |
f776471f BC |
1831 | }; |
1832 | ||
3b54baad BC |
1833 | /* gpio1 */ |
1834 | static struct omap_hwmod omap44xx_gpio1_hwmod; | |
1835 | static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { | |
1836 | { .irq = 29 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1837 | { .irq = -1 } |
f776471f BC |
1838 | }; |
1839 | ||
3b54baad | 1840 | static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { |
f776471f | 1841 | { |
3b54baad BC |
1842 | .pa_start = 0x4a310000, |
1843 | .pa_end = 0x4a3101ff, | |
f776471f BC |
1844 | .flags = ADDR_TYPE_RT |
1845 | }, | |
78183f3f | 1846 | { } |
f776471f BC |
1847 | }; |
1848 | ||
3b54baad BC |
1849 | /* l4_wkup -> gpio1 */ |
1850 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { | |
1851 | .master = &omap44xx_l4_wkup_hwmod, | |
1852 | .slave = &omap44xx_gpio1_hwmod, | |
b399bca8 | 1853 | .clk = "l4_wkup_clk_mux_ck", |
3b54baad | 1854 | .addr = omap44xx_gpio1_addrs, |
f776471f BC |
1855 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1856 | }; | |
1857 | ||
3b54baad BC |
1858 | /* gpio1 slave ports */ |
1859 | static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = { | |
1860 | &omap44xx_l4_wkup__gpio1, | |
f776471f BC |
1861 | }; |
1862 | ||
3b54baad | 1863 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
b399bca8 | 1864 | { .role = "dbclk", .clk = "gpio1_dbclk" }, |
3b54baad BC |
1865 | }; |
1866 | ||
1867 | static struct omap_hwmod omap44xx_gpio1_hwmod = { | |
1868 | .name = "gpio1", | |
1869 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1870 | .clkdm_name = "l4_wkup_clkdm", |
3b54baad | 1871 | .mpu_irqs = omap44xx_gpio1_irqs, |
3b54baad | 1872 | .main_clk = "gpio1_ick", |
f776471f BC |
1873 | .prcm = { |
1874 | .omap4 = { | |
d0f0631d | 1875 | .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, |
27bb00b5 | 1876 | .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET, |
03fdefe5 | 1877 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1878 | }, |
1879 | }, | |
3b54baad BC |
1880 | .opt_clks = gpio1_opt_clks, |
1881 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
1882 | .dev_attr = &gpio_dev_attr, | |
1883 | .slaves = omap44xx_gpio1_slaves, | |
1884 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves), | |
f776471f BC |
1885 | }; |
1886 | ||
3b54baad BC |
1887 | /* gpio2 */ |
1888 | static struct omap_hwmod omap44xx_gpio2_hwmod; | |
1889 | static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { | |
1890 | { .irq = 30 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1891 | { .irq = -1 } |
f776471f BC |
1892 | }; |
1893 | ||
3b54baad | 1894 | static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { |
f776471f | 1895 | { |
3b54baad BC |
1896 | .pa_start = 0x48055000, |
1897 | .pa_end = 0x480551ff, | |
f776471f BC |
1898 | .flags = ADDR_TYPE_RT |
1899 | }, | |
78183f3f | 1900 | { } |
f776471f BC |
1901 | }; |
1902 | ||
3b54baad BC |
1903 | /* l4_per -> gpio2 */ |
1904 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { | |
f776471f | 1905 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 1906 | .slave = &omap44xx_gpio2_hwmod, |
b399bca8 | 1907 | .clk = "l4_div_ck", |
3b54baad | 1908 | .addr = omap44xx_gpio2_addrs, |
f776471f BC |
1909 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1910 | }; | |
1911 | ||
3b54baad BC |
1912 | /* gpio2 slave ports */ |
1913 | static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = { | |
1914 | &omap44xx_l4_per__gpio2, | |
f776471f BC |
1915 | }; |
1916 | ||
3b54baad | 1917 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
b399bca8 | 1918 | { .role = "dbclk", .clk = "gpio2_dbclk" }, |
3b54baad BC |
1919 | }; |
1920 | ||
1921 | static struct omap_hwmod omap44xx_gpio2_hwmod = { | |
1922 | .name = "gpio2", | |
1923 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1924 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1925 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1926 | .mpu_irqs = omap44xx_gpio2_irqs, |
3b54baad | 1927 | .main_clk = "gpio2_ick", |
f776471f BC |
1928 | .prcm = { |
1929 | .omap4 = { | |
d0f0631d | 1930 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET, |
27bb00b5 | 1931 | .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET, |
03fdefe5 | 1932 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1933 | }, |
1934 | }, | |
3b54baad BC |
1935 | .opt_clks = gpio2_opt_clks, |
1936 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
1937 | .dev_attr = &gpio_dev_attr, | |
1938 | .slaves = omap44xx_gpio2_slaves, | |
1939 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves), | |
f776471f BC |
1940 | }; |
1941 | ||
3b54baad BC |
1942 | /* gpio3 */ |
1943 | static struct omap_hwmod omap44xx_gpio3_hwmod; | |
1944 | static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { | |
1945 | { .irq = 31 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1946 | { .irq = -1 } |
f776471f BC |
1947 | }; |
1948 | ||
3b54baad | 1949 | static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { |
f776471f | 1950 | { |
3b54baad BC |
1951 | .pa_start = 0x48057000, |
1952 | .pa_end = 0x480571ff, | |
f776471f BC |
1953 | .flags = ADDR_TYPE_RT |
1954 | }, | |
78183f3f | 1955 | { } |
f776471f BC |
1956 | }; |
1957 | ||
3b54baad BC |
1958 | /* l4_per -> gpio3 */ |
1959 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { | |
f776471f | 1960 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 1961 | .slave = &omap44xx_gpio3_hwmod, |
b399bca8 | 1962 | .clk = "l4_div_ck", |
3b54baad | 1963 | .addr = omap44xx_gpio3_addrs, |
f776471f BC |
1964 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1965 | }; | |
1966 | ||
3b54baad BC |
1967 | /* gpio3 slave ports */ |
1968 | static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = { | |
1969 | &omap44xx_l4_per__gpio3, | |
f776471f BC |
1970 | }; |
1971 | ||
3b54baad | 1972 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
b399bca8 | 1973 | { .role = "dbclk", .clk = "gpio3_dbclk" }, |
3b54baad BC |
1974 | }; |
1975 | ||
1976 | static struct omap_hwmod omap44xx_gpio3_hwmod = { | |
1977 | .name = "gpio3", | |
1978 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1979 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1980 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1981 | .mpu_irqs = omap44xx_gpio3_irqs, |
3b54baad | 1982 | .main_clk = "gpio3_ick", |
f776471f BC |
1983 | .prcm = { |
1984 | .omap4 = { | |
d0f0631d | 1985 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET, |
27bb00b5 | 1986 | .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET, |
03fdefe5 | 1987 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1988 | }, |
1989 | }, | |
3b54baad BC |
1990 | .opt_clks = gpio3_opt_clks, |
1991 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
1992 | .dev_attr = &gpio_dev_attr, | |
1993 | .slaves = omap44xx_gpio3_slaves, | |
1994 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves), | |
f776471f BC |
1995 | }; |
1996 | ||
3b54baad BC |
1997 | /* gpio4 */ |
1998 | static struct omap_hwmod omap44xx_gpio4_hwmod; | |
1999 | static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { | |
2000 | { .irq = 32 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2001 | { .irq = -1 } |
f776471f BC |
2002 | }; |
2003 | ||
3b54baad | 2004 | static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { |
f776471f | 2005 | { |
3b54baad BC |
2006 | .pa_start = 0x48059000, |
2007 | .pa_end = 0x480591ff, | |
f776471f BC |
2008 | .flags = ADDR_TYPE_RT |
2009 | }, | |
78183f3f | 2010 | { } |
f776471f BC |
2011 | }; |
2012 | ||
3b54baad BC |
2013 | /* l4_per -> gpio4 */ |
2014 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { | |
f776471f | 2015 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 2016 | .slave = &omap44xx_gpio4_hwmod, |
b399bca8 | 2017 | .clk = "l4_div_ck", |
3b54baad | 2018 | .addr = omap44xx_gpio4_addrs, |
f776471f BC |
2019 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2020 | }; | |
2021 | ||
3b54baad BC |
2022 | /* gpio4 slave ports */ |
2023 | static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = { | |
2024 | &omap44xx_l4_per__gpio4, | |
f776471f BC |
2025 | }; |
2026 | ||
3b54baad | 2027 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { |
b399bca8 | 2028 | { .role = "dbclk", .clk = "gpio4_dbclk" }, |
3b54baad BC |
2029 | }; |
2030 | ||
2031 | static struct omap_hwmod omap44xx_gpio4_hwmod = { | |
2032 | .name = "gpio4", | |
2033 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 2034 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 2035 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 2036 | .mpu_irqs = omap44xx_gpio4_irqs, |
3b54baad | 2037 | .main_clk = "gpio4_ick", |
f776471f BC |
2038 | .prcm = { |
2039 | .omap4 = { | |
d0f0631d | 2040 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET, |
27bb00b5 | 2041 | .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET, |
03fdefe5 | 2042 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
2043 | }, |
2044 | }, | |
3b54baad BC |
2045 | .opt_clks = gpio4_opt_clks, |
2046 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
2047 | .dev_attr = &gpio_dev_attr, | |
2048 | .slaves = omap44xx_gpio4_slaves, | |
2049 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves), | |
f776471f BC |
2050 | }; |
2051 | ||
3b54baad BC |
2052 | /* gpio5 */ |
2053 | static struct omap_hwmod omap44xx_gpio5_hwmod; | |
2054 | static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { | |
2055 | { .irq = 33 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2056 | { .irq = -1 } |
55d2cb08 BC |
2057 | }; |
2058 | ||
3b54baad BC |
2059 | static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { |
2060 | { | |
2061 | .pa_start = 0x4805b000, | |
2062 | .pa_end = 0x4805b1ff, | |
2063 | .flags = ADDR_TYPE_RT | |
2064 | }, | |
78183f3f | 2065 | { } |
55d2cb08 BC |
2066 | }; |
2067 | ||
3b54baad BC |
2068 | /* l4_per -> gpio5 */ |
2069 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { | |
2070 | .master = &omap44xx_l4_per_hwmod, | |
2071 | .slave = &omap44xx_gpio5_hwmod, | |
b399bca8 | 2072 | .clk = "l4_div_ck", |
3b54baad | 2073 | .addr = omap44xx_gpio5_addrs, |
3b54baad | 2074 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
55d2cb08 BC |
2075 | }; |
2076 | ||
3b54baad BC |
2077 | /* gpio5 slave ports */ |
2078 | static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = { | |
2079 | &omap44xx_l4_per__gpio5, | |
55d2cb08 BC |
2080 | }; |
2081 | ||
3b54baad | 2082 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
b399bca8 | 2083 | { .role = "dbclk", .clk = "gpio5_dbclk" }, |
55d2cb08 BC |
2084 | }; |
2085 | ||
3b54baad BC |
2086 | static struct omap_hwmod omap44xx_gpio5_hwmod = { |
2087 | .name = "gpio5", | |
2088 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 2089 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 2090 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 2091 | .mpu_irqs = omap44xx_gpio5_irqs, |
3b54baad | 2092 | .main_clk = "gpio5_ick", |
55d2cb08 BC |
2093 | .prcm = { |
2094 | .omap4 = { | |
d0f0631d | 2095 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET, |
27bb00b5 | 2096 | .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET, |
03fdefe5 | 2097 | .modulemode = MODULEMODE_HWCTRL, |
55d2cb08 BC |
2098 | }, |
2099 | }, | |
3b54baad BC |
2100 | .opt_clks = gpio5_opt_clks, |
2101 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
2102 | .dev_attr = &gpio_dev_attr, | |
2103 | .slaves = omap44xx_gpio5_slaves, | |
2104 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves), | |
55d2cb08 BC |
2105 | }; |
2106 | ||
3b54baad BC |
2107 | /* gpio6 */ |
2108 | static struct omap_hwmod omap44xx_gpio6_hwmod; | |
2109 | static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { | |
2110 | { .irq = 34 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2111 | { .irq = -1 } |
92b18d1c BC |
2112 | }; |
2113 | ||
3b54baad | 2114 | static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { |
92b18d1c | 2115 | { |
3b54baad BC |
2116 | .pa_start = 0x4805d000, |
2117 | .pa_end = 0x4805d1ff, | |
92b18d1c BC |
2118 | .flags = ADDR_TYPE_RT |
2119 | }, | |
78183f3f | 2120 | { } |
92b18d1c BC |
2121 | }; |
2122 | ||
3b54baad BC |
2123 | /* l4_per -> gpio6 */ |
2124 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { | |
2125 | .master = &omap44xx_l4_per_hwmod, | |
2126 | .slave = &omap44xx_gpio6_hwmod, | |
b399bca8 | 2127 | .clk = "l4_div_ck", |
3b54baad | 2128 | .addr = omap44xx_gpio6_addrs, |
3b54baad | 2129 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
db12ba53 BC |
2130 | }; |
2131 | ||
3b54baad BC |
2132 | /* gpio6 slave ports */ |
2133 | static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = { | |
2134 | &omap44xx_l4_per__gpio6, | |
db12ba53 BC |
2135 | }; |
2136 | ||
3b54baad | 2137 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
b399bca8 | 2138 | { .role = "dbclk", .clk = "gpio6_dbclk" }, |
db12ba53 BC |
2139 | }; |
2140 | ||
3b54baad BC |
2141 | static struct omap_hwmod omap44xx_gpio6_hwmod = { |
2142 | .name = "gpio6", | |
2143 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 2144 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 2145 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 2146 | .mpu_irqs = omap44xx_gpio6_irqs, |
3b54baad BC |
2147 | .main_clk = "gpio6_ick", |
2148 | .prcm = { | |
2149 | .omap4 = { | |
d0f0631d | 2150 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET, |
27bb00b5 | 2151 | .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET, |
03fdefe5 | 2152 | .modulemode = MODULEMODE_HWCTRL, |
3b54baad | 2153 | }, |
db12ba53 | 2154 | }, |
3b54baad BC |
2155 | .opt_clks = gpio6_opt_clks, |
2156 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
2157 | .dev_attr = &gpio_dev_attr, | |
2158 | .slaves = omap44xx_gpio6_slaves, | |
2159 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves), | |
db12ba53 BC |
2160 | }; |
2161 | ||
407a6888 BC |
2162 | /* |
2163 | * 'hsi' class | |
2164 | * mipi high-speed synchronous serial interface (multichannel and full-duplex | |
2165 | * serial if) | |
2166 | */ | |
2167 | ||
2168 | static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = { | |
2169 | .rev_offs = 0x0000, | |
2170 | .sysc_offs = 0x0010, | |
2171 | .syss_offs = 0x0014, | |
2172 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | | |
2173 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
2174 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
2175 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2176 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 2177 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
2178 | .sysc_fields = &omap_hwmod_sysc_type1, |
2179 | }; | |
2180 | ||
2181 | static struct omap_hwmod_class omap44xx_hsi_hwmod_class = { | |
2182 | .name = "hsi", | |
2183 | .sysc = &omap44xx_hsi_sysc, | |
2184 | }; | |
2185 | ||
2186 | /* hsi */ | |
2187 | static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { | |
2188 | { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START }, | |
2189 | { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START }, | |
2190 | { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2191 | { .irq = -1 } |
407a6888 BC |
2192 | }; |
2193 | ||
2194 | /* hsi master ports */ | |
2195 | static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = { | |
2196 | &omap44xx_hsi__l3_main_2, | |
2197 | }; | |
2198 | ||
2199 | static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { | |
2200 | { | |
2201 | .pa_start = 0x4a058000, | |
2202 | .pa_end = 0x4a05bfff, | |
2203 | .flags = ADDR_TYPE_RT | |
2204 | }, | |
78183f3f | 2205 | { } |
407a6888 BC |
2206 | }; |
2207 | ||
2208 | /* l4_cfg -> hsi */ | |
2209 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { | |
2210 | .master = &omap44xx_l4_cfg_hwmod, | |
2211 | .slave = &omap44xx_hsi_hwmod, | |
2212 | .clk = "l4_div_ck", | |
2213 | .addr = omap44xx_hsi_addrs, | |
407a6888 BC |
2214 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2215 | }; | |
2216 | ||
2217 | /* hsi slave ports */ | |
2218 | static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = { | |
2219 | &omap44xx_l4_cfg__hsi, | |
2220 | }; | |
2221 | ||
2222 | static struct omap_hwmod omap44xx_hsi_hwmod = { | |
2223 | .name = "hsi", | |
2224 | .class = &omap44xx_hsi_hwmod_class, | |
a5322c6f | 2225 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 2226 | .mpu_irqs = omap44xx_hsi_irqs, |
407a6888 | 2227 | .main_clk = "hsi_fck", |
00fe610b | 2228 | .prcm = { |
407a6888 | 2229 | .omap4 = { |
d0f0631d | 2230 | .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET, |
27bb00b5 | 2231 | .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET, |
03fdefe5 | 2232 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
2233 | }, |
2234 | }, | |
2235 | .slaves = omap44xx_hsi_slaves, | |
2236 | .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves), | |
2237 | .masters = omap44xx_hsi_masters, | |
2238 | .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters), | |
407a6888 BC |
2239 | }; |
2240 | ||
3b54baad BC |
2241 | /* |
2242 | * 'i2c' class | |
2243 | * multimaster high-speed i2c controller | |
2244 | */ | |
db12ba53 | 2245 | |
3b54baad BC |
2246 | static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { |
2247 | .sysc_offs = 0x0010, | |
2248 | .syss_offs = 0x0090, | |
2249 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2250 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 2251 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
2252 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
2253 | SIDLE_SMART_WKUP), | |
3e47dc6a | 2254 | .clockact = CLOCKACT_TEST_ICLK, |
3b54baad | 2255 | .sysc_fields = &omap_hwmod_sysc_type1, |
db12ba53 BC |
2256 | }; |
2257 | ||
3b54baad | 2258 | static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { |
fe13471c BC |
2259 | .name = "i2c", |
2260 | .sysc = &omap44xx_i2c_sysc, | |
db791a75 | 2261 | .rev = OMAP_I2C_IP_VERSION_2, |
6d3c55fd | 2262 | .reset = &omap_i2c_reset, |
db12ba53 BC |
2263 | }; |
2264 | ||
4d4441a6 AG |
2265 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
2266 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, | |
2267 | }; | |
2268 | ||
3b54baad BC |
2269 | /* i2c1 */ |
2270 | static struct omap_hwmod omap44xx_i2c1_hwmod; | |
2271 | static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { | |
2272 | { .irq = 56 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2273 | { .irq = -1 } |
db12ba53 BC |
2274 | }; |
2275 | ||
3b54baad BC |
2276 | static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { |
2277 | { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, | |
2278 | { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2279 | { .dma_req = -1 } |
db12ba53 BC |
2280 | }; |
2281 | ||
3b54baad | 2282 | static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { |
db12ba53 | 2283 | { |
3b54baad BC |
2284 | .pa_start = 0x48070000, |
2285 | .pa_end = 0x480700ff, | |
db12ba53 BC |
2286 | .flags = ADDR_TYPE_RT |
2287 | }, | |
78183f3f | 2288 | { } |
db12ba53 BC |
2289 | }; |
2290 | ||
3b54baad BC |
2291 | /* l4_per -> i2c1 */ |
2292 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { | |
2293 | .master = &omap44xx_l4_per_hwmod, | |
2294 | .slave = &omap44xx_i2c1_hwmod, | |
2295 | .clk = "l4_div_ck", | |
2296 | .addr = omap44xx_i2c1_addrs, | |
92b18d1c BC |
2297 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2298 | }; | |
2299 | ||
3b54baad BC |
2300 | /* i2c1 slave ports */ |
2301 | static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = { | |
2302 | &omap44xx_l4_per__i2c1, | |
92b18d1c BC |
2303 | }; |
2304 | ||
3b54baad BC |
2305 | static struct omap_hwmod omap44xx_i2c1_hwmod = { |
2306 | .name = "i2c1", | |
2307 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 2308 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 2309 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 2310 | .mpu_irqs = omap44xx_i2c1_irqs, |
3b54baad | 2311 | .sdma_reqs = omap44xx_i2c1_sdma_reqs, |
3b54baad | 2312 | .main_clk = "i2c1_fck", |
92b18d1c BC |
2313 | .prcm = { |
2314 | .omap4 = { | |
d0f0631d | 2315 | .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET, |
27bb00b5 | 2316 | .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET, |
03fdefe5 | 2317 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
2318 | }, |
2319 | }, | |
3b54baad BC |
2320 | .slaves = omap44xx_i2c1_slaves, |
2321 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves), | |
4d4441a6 | 2322 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
2323 | }; |
2324 | ||
3b54baad BC |
2325 | /* i2c2 */ |
2326 | static struct omap_hwmod omap44xx_i2c2_hwmod; | |
2327 | static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { | |
2328 | { .irq = 57 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2329 | { .irq = -1 } |
92b18d1c BC |
2330 | }; |
2331 | ||
3b54baad BC |
2332 | static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { |
2333 | { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, | |
2334 | { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2335 | { .dma_req = -1 } |
3b54baad BC |
2336 | }; |
2337 | ||
2338 | static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { | |
92b18d1c | 2339 | { |
3b54baad BC |
2340 | .pa_start = 0x48072000, |
2341 | .pa_end = 0x480720ff, | |
92b18d1c BC |
2342 | .flags = ADDR_TYPE_RT |
2343 | }, | |
78183f3f | 2344 | { } |
92b18d1c BC |
2345 | }; |
2346 | ||
3b54baad BC |
2347 | /* l4_per -> i2c2 */ |
2348 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { | |
db12ba53 | 2349 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 2350 | .slave = &omap44xx_i2c2_hwmod, |
db12ba53 | 2351 | .clk = "l4_div_ck", |
3b54baad | 2352 | .addr = omap44xx_i2c2_addrs, |
db12ba53 BC |
2353 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2354 | }; | |
2355 | ||
3b54baad BC |
2356 | /* i2c2 slave ports */ |
2357 | static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = { | |
2358 | &omap44xx_l4_per__i2c2, | |
db12ba53 BC |
2359 | }; |
2360 | ||
3b54baad BC |
2361 | static struct omap_hwmod omap44xx_i2c2_hwmod = { |
2362 | .name = "i2c2", | |
2363 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 2364 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 2365 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 2366 | .mpu_irqs = omap44xx_i2c2_irqs, |
3b54baad | 2367 | .sdma_reqs = omap44xx_i2c2_sdma_reqs, |
3b54baad | 2368 | .main_clk = "i2c2_fck", |
db12ba53 BC |
2369 | .prcm = { |
2370 | .omap4 = { | |
d0f0631d | 2371 | .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, |
27bb00b5 | 2372 | .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET, |
03fdefe5 | 2373 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
2374 | }, |
2375 | }, | |
3b54baad BC |
2376 | .slaves = omap44xx_i2c2_slaves, |
2377 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves), | |
4d4441a6 | 2378 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
2379 | }; |
2380 | ||
3b54baad BC |
2381 | /* i2c3 */ |
2382 | static struct omap_hwmod omap44xx_i2c3_hwmod; | |
2383 | static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { | |
2384 | { .irq = 61 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2385 | { .irq = -1 } |
db12ba53 BC |
2386 | }; |
2387 | ||
3b54baad BC |
2388 | static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { |
2389 | { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, | |
2390 | { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2391 | { .dma_req = -1 } |
92b18d1c BC |
2392 | }; |
2393 | ||
3b54baad | 2394 | static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { |
92b18d1c | 2395 | { |
3b54baad BC |
2396 | .pa_start = 0x48060000, |
2397 | .pa_end = 0x480600ff, | |
92b18d1c BC |
2398 | .flags = ADDR_TYPE_RT |
2399 | }, | |
78183f3f | 2400 | { } |
92b18d1c BC |
2401 | }; |
2402 | ||
3b54baad BC |
2403 | /* l4_per -> i2c3 */ |
2404 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { | |
db12ba53 | 2405 | .master = &omap44xx_l4_per_hwmod, |
3b54baad | 2406 | .slave = &omap44xx_i2c3_hwmod, |
db12ba53 | 2407 | .clk = "l4_div_ck", |
3b54baad | 2408 | .addr = omap44xx_i2c3_addrs, |
db12ba53 BC |
2409 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2410 | }; | |
2411 | ||
3b54baad BC |
2412 | /* i2c3 slave ports */ |
2413 | static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = { | |
2414 | &omap44xx_l4_per__i2c3, | |
db12ba53 BC |
2415 | }; |
2416 | ||
3b54baad BC |
2417 | static struct omap_hwmod omap44xx_i2c3_hwmod = { |
2418 | .name = "i2c3", | |
2419 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 2420 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 2421 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 2422 | .mpu_irqs = omap44xx_i2c3_irqs, |
3b54baad | 2423 | .sdma_reqs = omap44xx_i2c3_sdma_reqs, |
3b54baad | 2424 | .main_clk = "i2c3_fck", |
db12ba53 BC |
2425 | .prcm = { |
2426 | .omap4 = { | |
d0f0631d | 2427 | .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET, |
27bb00b5 | 2428 | .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET, |
03fdefe5 | 2429 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
2430 | }, |
2431 | }, | |
3b54baad BC |
2432 | .slaves = omap44xx_i2c3_slaves, |
2433 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves), | |
4d4441a6 | 2434 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
2435 | }; |
2436 | ||
3b54baad BC |
2437 | /* i2c4 */ |
2438 | static struct omap_hwmod omap44xx_i2c4_hwmod; | |
2439 | static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { | |
2440 | { .irq = 62 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2441 | { .irq = -1 } |
db12ba53 BC |
2442 | }; |
2443 | ||
3b54baad BC |
2444 | static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { |
2445 | { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, | |
2446 | { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2447 | { .dma_req = -1 } |
db12ba53 BC |
2448 | }; |
2449 | ||
3b54baad | 2450 | static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { |
db12ba53 | 2451 | { |
3b54baad BC |
2452 | .pa_start = 0x48350000, |
2453 | .pa_end = 0x483500ff, | |
db12ba53 BC |
2454 | .flags = ADDR_TYPE_RT |
2455 | }, | |
78183f3f | 2456 | { } |
db12ba53 BC |
2457 | }; |
2458 | ||
3b54baad BC |
2459 | /* l4_per -> i2c4 */ |
2460 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { | |
2461 | .master = &omap44xx_l4_per_hwmod, | |
2462 | .slave = &omap44xx_i2c4_hwmod, | |
2463 | .clk = "l4_div_ck", | |
2464 | .addr = omap44xx_i2c4_addrs, | |
3b54baad | 2465 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
92b18d1c BC |
2466 | }; |
2467 | ||
3b54baad BC |
2468 | /* i2c4 slave ports */ |
2469 | static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = { | |
2470 | &omap44xx_l4_per__i2c4, | |
92b18d1c BC |
2471 | }; |
2472 | ||
3b54baad BC |
2473 | static struct omap_hwmod omap44xx_i2c4_hwmod = { |
2474 | .name = "i2c4", | |
2475 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 2476 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 2477 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 2478 | .mpu_irqs = omap44xx_i2c4_irqs, |
3b54baad | 2479 | .sdma_reqs = omap44xx_i2c4_sdma_reqs, |
3b54baad | 2480 | .main_clk = "i2c4_fck", |
92b18d1c BC |
2481 | .prcm = { |
2482 | .omap4 = { | |
d0f0631d | 2483 | .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET, |
27bb00b5 | 2484 | .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET, |
03fdefe5 | 2485 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
2486 | }, |
2487 | }, | |
3b54baad BC |
2488 | .slaves = omap44xx_i2c4_slaves, |
2489 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves), | |
4d4441a6 | 2490 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
2491 | }; |
2492 | ||
407a6888 BC |
2493 | /* |
2494 | * 'ipu' class | |
2495 | * imaging processor unit | |
2496 | */ | |
2497 | ||
2498 | static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { | |
2499 | .name = "ipu", | |
2500 | }; | |
2501 | ||
2502 | /* ipu */ | |
2503 | static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { | |
2504 | { .irq = 100 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2505 | { .irq = -1 } |
407a6888 BC |
2506 | }; |
2507 | ||
2508 | static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = { | |
2509 | { .name = "cpu0", .rst_shift = 0 }, | |
2510 | }; | |
2511 | ||
2512 | static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = { | |
2513 | { .name = "cpu1", .rst_shift = 1 }, | |
2514 | }; | |
2515 | ||
2516 | static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { | |
2517 | { .name = "mmu_cache", .rst_shift = 2 }, | |
2518 | }; | |
2519 | ||
2520 | /* ipu master ports */ | |
2521 | static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = { | |
2522 | &omap44xx_ipu__l3_main_2, | |
2523 | }; | |
2524 | ||
2525 | /* l3_main_2 -> ipu */ | |
2526 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { | |
2527 | .master = &omap44xx_l3_main_2_hwmod, | |
2528 | .slave = &omap44xx_ipu_hwmod, | |
2529 | .clk = "l3_div_ck", | |
2530 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2531 | }; | |
2532 | ||
2533 | /* ipu slave ports */ | |
2534 | static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = { | |
2535 | &omap44xx_l3_main_2__ipu, | |
2536 | }; | |
2537 | ||
2538 | /* Pseudo hwmod for reset control purpose only */ | |
2539 | static struct omap_hwmod omap44xx_ipu_c0_hwmod = { | |
2540 | .name = "ipu_c0", | |
2541 | .class = &omap44xx_ipu_hwmod_class, | |
a5322c6f | 2542 | .clkdm_name = "ducati_clkdm", |
407a6888 BC |
2543 | .flags = HWMOD_INIT_NO_RESET, |
2544 | .rst_lines = omap44xx_ipu_c0_resets, | |
2545 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets), | |
00fe610b | 2546 | .prcm = { |
407a6888 | 2547 | .omap4 = { |
eaac329d | 2548 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, |
407a6888 BC |
2549 | }, |
2550 | }, | |
407a6888 BC |
2551 | }; |
2552 | ||
2553 | /* Pseudo hwmod for reset control purpose only */ | |
2554 | static struct omap_hwmod omap44xx_ipu_c1_hwmod = { | |
2555 | .name = "ipu_c1", | |
2556 | .class = &omap44xx_ipu_hwmod_class, | |
a5322c6f | 2557 | .clkdm_name = "ducati_clkdm", |
407a6888 BC |
2558 | .flags = HWMOD_INIT_NO_RESET, |
2559 | .rst_lines = omap44xx_ipu_c1_resets, | |
2560 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets), | |
00fe610b | 2561 | .prcm = { |
407a6888 | 2562 | .omap4 = { |
eaac329d | 2563 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, |
407a6888 BC |
2564 | }, |
2565 | }, | |
407a6888 BC |
2566 | }; |
2567 | ||
2568 | static struct omap_hwmod omap44xx_ipu_hwmod = { | |
2569 | .name = "ipu", | |
2570 | .class = &omap44xx_ipu_hwmod_class, | |
a5322c6f | 2571 | .clkdm_name = "ducati_clkdm", |
407a6888 | 2572 | .mpu_irqs = omap44xx_ipu_irqs, |
407a6888 BC |
2573 | .rst_lines = omap44xx_ipu_resets, |
2574 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), | |
2575 | .main_clk = "ipu_fck", | |
00fe610b | 2576 | .prcm = { |
407a6888 | 2577 | .omap4 = { |
d0f0631d | 2578 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, |
eaac329d | 2579 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, |
27bb00b5 | 2580 | .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, |
03fdefe5 | 2581 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
2582 | }, |
2583 | }, | |
2584 | .slaves = omap44xx_ipu_slaves, | |
2585 | .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves), | |
2586 | .masters = omap44xx_ipu_masters, | |
2587 | .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters), | |
407a6888 BC |
2588 | }; |
2589 | ||
2590 | /* | |
2591 | * 'iss' class | |
2592 | * external images sensor pixel data processor | |
2593 | */ | |
2594 | ||
2595 | static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { | |
2596 | .rev_offs = 0x0000, | |
2597 | .sysc_offs = 0x0010, | |
2598 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | | |
2599 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2600 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2601 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 2602 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
2603 | .sysc_fields = &omap_hwmod_sysc_type2, |
2604 | }; | |
2605 | ||
2606 | static struct omap_hwmod_class omap44xx_iss_hwmod_class = { | |
2607 | .name = "iss", | |
2608 | .sysc = &omap44xx_iss_sysc, | |
2609 | }; | |
2610 | ||
2611 | /* iss */ | |
2612 | static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = { | |
2613 | { .irq = 24 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2614 | { .irq = -1 } |
407a6888 BC |
2615 | }; |
2616 | ||
2617 | static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { | |
2618 | { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START }, | |
2619 | { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START }, | |
2620 | { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START }, | |
2621 | { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2622 | { .dma_req = -1 } |
407a6888 BC |
2623 | }; |
2624 | ||
2625 | /* iss master ports */ | |
2626 | static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = { | |
2627 | &omap44xx_iss__l3_main_2, | |
2628 | }; | |
2629 | ||
2630 | static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { | |
2631 | { | |
2632 | .pa_start = 0x52000000, | |
2633 | .pa_end = 0x520000ff, | |
2634 | .flags = ADDR_TYPE_RT | |
2635 | }, | |
78183f3f | 2636 | { } |
407a6888 BC |
2637 | }; |
2638 | ||
2639 | /* l3_main_2 -> iss */ | |
2640 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { | |
2641 | .master = &omap44xx_l3_main_2_hwmod, | |
2642 | .slave = &omap44xx_iss_hwmod, | |
2643 | .clk = "l3_div_ck", | |
2644 | .addr = omap44xx_iss_addrs, | |
407a6888 BC |
2645 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2646 | }; | |
2647 | ||
2648 | /* iss slave ports */ | |
2649 | static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = { | |
2650 | &omap44xx_l3_main_2__iss, | |
2651 | }; | |
2652 | ||
2653 | static struct omap_hwmod_opt_clk iss_opt_clks[] = { | |
2654 | { .role = "ctrlclk", .clk = "iss_ctrlclk" }, | |
2655 | }; | |
2656 | ||
2657 | static struct omap_hwmod omap44xx_iss_hwmod = { | |
2658 | .name = "iss", | |
2659 | .class = &omap44xx_iss_hwmod_class, | |
a5322c6f | 2660 | .clkdm_name = "iss_clkdm", |
407a6888 | 2661 | .mpu_irqs = omap44xx_iss_irqs, |
407a6888 | 2662 | .sdma_reqs = omap44xx_iss_sdma_reqs, |
407a6888 | 2663 | .main_clk = "iss_fck", |
00fe610b | 2664 | .prcm = { |
407a6888 | 2665 | .omap4 = { |
d0f0631d | 2666 | .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, |
27bb00b5 | 2667 | .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET, |
03fdefe5 | 2668 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2669 | }, |
2670 | }, | |
2671 | .opt_clks = iss_opt_clks, | |
2672 | .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), | |
2673 | .slaves = omap44xx_iss_slaves, | |
2674 | .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves), | |
2675 | .masters = omap44xx_iss_masters, | |
2676 | .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters), | |
407a6888 BC |
2677 | }; |
2678 | ||
8f25bdc5 BC |
2679 | /* |
2680 | * 'iva' class | |
2681 | * multi-standard video encoder/decoder hardware accelerator | |
2682 | */ | |
2683 | ||
2684 | static struct omap_hwmod_class omap44xx_iva_hwmod_class = { | |
fe13471c | 2685 | .name = "iva", |
8f25bdc5 BC |
2686 | }; |
2687 | ||
2688 | /* iva */ | |
2689 | static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { | |
2690 | { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, | |
2691 | { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, | |
2692 | { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2693 | { .irq = -1 } |
8f25bdc5 BC |
2694 | }; |
2695 | ||
2696 | static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { | |
2697 | { .name = "logic", .rst_shift = 2 }, | |
2698 | }; | |
2699 | ||
2700 | static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = { | |
2701 | { .name = "seq0", .rst_shift = 0 }, | |
2702 | }; | |
2703 | ||
2704 | static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = { | |
2705 | { .name = "seq1", .rst_shift = 1 }, | |
2706 | }; | |
2707 | ||
2708 | /* iva master ports */ | |
2709 | static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = { | |
2710 | &omap44xx_iva__l3_main_2, | |
2711 | &omap44xx_iva__l3_instr, | |
2712 | }; | |
2713 | ||
2714 | static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { | |
2715 | { | |
2716 | .pa_start = 0x5a000000, | |
2717 | .pa_end = 0x5a07ffff, | |
2718 | .flags = ADDR_TYPE_RT | |
2719 | }, | |
78183f3f | 2720 | { } |
8f25bdc5 BC |
2721 | }; |
2722 | ||
2723 | /* l3_main_2 -> iva */ | |
2724 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { | |
2725 | .master = &omap44xx_l3_main_2_hwmod, | |
2726 | .slave = &omap44xx_iva_hwmod, | |
2727 | .clk = "l3_div_ck", | |
2728 | .addr = omap44xx_iva_addrs, | |
8f25bdc5 BC |
2729 | .user = OCP_USER_MPU, |
2730 | }; | |
2731 | ||
2732 | /* iva slave ports */ | |
2733 | static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = { | |
2734 | &omap44xx_dsp__iva, | |
2735 | &omap44xx_l3_main_2__iva, | |
2736 | }; | |
2737 | ||
2738 | /* Pseudo hwmod for reset control purpose only */ | |
2739 | static struct omap_hwmod omap44xx_iva_seq0_hwmod = { | |
2740 | .name = "iva_seq0", | |
2741 | .class = &omap44xx_iva_hwmod_class, | |
a5322c6f | 2742 | .clkdm_name = "ivahd_clkdm", |
8f25bdc5 BC |
2743 | .flags = HWMOD_INIT_NO_RESET, |
2744 | .rst_lines = omap44xx_iva_seq0_resets, | |
2745 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets), | |
2746 | .prcm = { | |
2747 | .omap4 = { | |
eaac329d | 2748 | .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, |
8f25bdc5 BC |
2749 | }, |
2750 | }, | |
8f25bdc5 BC |
2751 | }; |
2752 | ||
2753 | /* Pseudo hwmod for reset control purpose only */ | |
2754 | static struct omap_hwmod omap44xx_iva_seq1_hwmod = { | |
2755 | .name = "iva_seq1", | |
2756 | .class = &omap44xx_iva_hwmod_class, | |
a5322c6f | 2757 | .clkdm_name = "ivahd_clkdm", |
8f25bdc5 BC |
2758 | .flags = HWMOD_INIT_NO_RESET, |
2759 | .rst_lines = omap44xx_iva_seq1_resets, | |
2760 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets), | |
2761 | .prcm = { | |
2762 | .omap4 = { | |
eaac329d | 2763 | .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, |
8f25bdc5 BC |
2764 | }, |
2765 | }, | |
8f25bdc5 BC |
2766 | }; |
2767 | ||
2768 | static struct omap_hwmod omap44xx_iva_hwmod = { | |
2769 | .name = "iva", | |
2770 | .class = &omap44xx_iva_hwmod_class, | |
a5322c6f | 2771 | .clkdm_name = "ivahd_clkdm", |
8f25bdc5 | 2772 | .mpu_irqs = omap44xx_iva_irqs, |
8f25bdc5 BC |
2773 | .rst_lines = omap44xx_iva_resets, |
2774 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), | |
2775 | .main_clk = "iva_fck", | |
2776 | .prcm = { | |
2777 | .omap4 = { | |
d0f0631d | 2778 | .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, |
eaac329d | 2779 | .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, |
27bb00b5 | 2780 | .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET, |
03fdefe5 | 2781 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
2782 | }, |
2783 | }, | |
2784 | .slaves = omap44xx_iva_slaves, | |
2785 | .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves), | |
2786 | .masters = omap44xx_iva_masters, | |
2787 | .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters), | |
8f25bdc5 BC |
2788 | }; |
2789 | ||
407a6888 BC |
2790 | /* |
2791 | * 'kbd' class | |
2792 | * keyboard controller | |
2793 | */ | |
2794 | ||
2795 | static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = { | |
2796 | .rev_offs = 0x0000, | |
2797 | .sysc_offs = 0x0010, | |
2798 | .syss_offs = 0x0014, | |
2799 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2800 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
2801 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
2802 | SYSS_HAS_RESET_STATUS), | |
2803 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2804 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2805 | }; | |
2806 | ||
2807 | static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { | |
2808 | .name = "kbd", | |
2809 | .sysc = &omap44xx_kbd_sysc, | |
2810 | }; | |
2811 | ||
2812 | /* kbd */ | |
2813 | static struct omap_hwmod omap44xx_kbd_hwmod; | |
2814 | static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { | |
2815 | { .irq = 120 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2816 | { .irq = -1 } |
407a6888 BC |
2817 | }; |
2818 | ||
2819 | static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { | |
2820 | { | |
2821 | .pa_start = 0x4a31c000, | |
2822 | .pa_end = 0x4a31c07f, | |
2823 | .flags = ADDR_TYPE_RT | |
2824 | }, | |
78183f3f | 2825 | { } |
407a6888 BC |
2826 | }; |
2827 | ||
2828 | /* l4_wkup -> kbd */ | |
2829 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { | |
2830 | .master = &omap44xx_l4_wkup_hwmod, | |
2831 | .slave = &omap44xx_kbd_hwmod, | |
2832 | .clk = "l4_wkup_clk_mux_ck", | |
2833 | .addr = omap44xx_kbd_addrs, | |
407a6888 BC |
2834 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2835 | }; | |
2836 | ||
2837 | /* kbd slave ports */ | |
2838 | static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = { | |
2839 | &omap44xx_l4_wkup__kbd, | |
2840 | }; | |
2841 | ||
2842 | static struct omap_hwmod omap44xx_kbd_hwmod = { | |
2843 | .name = "kbd", | |
2844 | .class = &omap44xx_kbd_hwmod_class, | |
a5322c6f | 2845 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 | 2846 | .mpu_irqs = omap44xx_kbd_irqs, |
407a6888 | 2847 | .main_clk = "kbd_fck", |
00fe610b | 2848 | .prcm = { |
407a6888 | 2849 | .omap4 = { |
d0f0631d | 2850 | .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, |
27bb00b5 | 2851 | .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET, |
03fdefe5 | 2852 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2853 | }, |
2854 | }, | |
2855 | .slaves = omap44xx_kbd_slaves, | |
2856 | .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves), | |
407a6888 BC |
2857 | }; |
2858 | ||
ec5df927 BC |
2859 | /* |
2860 | * 'mailbox' class | |
2861 | * mailbox module allowing communication between the on-chip processors using a | |
2862 | * queued mailbox-interrupt mechanism. | |
2863 | */ | |
2864 | ||
2865 | static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = { | |
2866 | .rev_offs = 0x0000, | |
2867 | .sysc_offs = 0x0010, | |
2868 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
2869 | SYSC_HAS_SOFTRESET), | |
2870 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2871 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2872 | }; | |
2873 | ||
2874 | static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { | |
2875 | .name = "mailbox", | |
2876 | .sysc = &omap44xx_mailbox_sysc, | |
2877 | }; | |
2878 | ||
2879 | /* mailbox */ | |
2880 | static struct omap_hwmod omap44xx_mailbox_hwmod; | |
2881 | static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { | |
2882 | { .irq = 26 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2883 | { .irq = -1 } |
ec5df927 BC |
2884 | }; |
2885 | ||
2886 | static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { | |
2887 | { | |
2888 | .pa_start = 0x4a0f4000, | |
2889 | .pa_end = 0x4a0f41ff, | |
2890 | .flags = ADDR_TYPE_RT | |
2891 | }, | |
78183f3f | 2892 | { } |
ec5df927 BC |
2893 | }; |
2894 | ||
2895 | /* l4_cfg -> mailbox */ | |
2896 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { | |
2897 | .master = &omap44xx_l4_cfg_hwmod, | |
2898 | .slave = &omap44xx_mailbox_hwmod, | |
2899 | .clk = "l4_div_ck", | |
2900 | .addr = omap44xx_mailbox_addrs, | |
ec5df927 BC |
2901 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2902 | }; | |
2903 | ||
2904 | /* mailbox slave ports */ | |
2905 | static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = { | |
2906 | &omap44xx_l4_cfg__mailbox, | |
2907 | }; | |
2908 | ||
2909 | static struct omap_hwmod omap44xx_mailbox_hwmod = { | |
2910 | .name = "mailbox", | |
2911 | .class = &omap44xx_mailbox_hwmod_class, | |
a5322c6f | 2912 | .clkdm_name = "l4_cfg_clkdm", |
ec5df927 | 2913 | .mpu_irqs = omap44xx_mailbox_irqs, |
00fe610b | 2914 | .prcm = { |
ec5df927 | 2915 | .omap4 = { |
d0f0631d | 2916 | .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, |
27bb00b5 | 2917 | .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, |
ec5df927 BC |
2918 | }, |
2919 | }, | |
2920 | .slaves = omap44xx_mailbox_slaves, | |
2921 | .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves), | |
ec5df927 BC |
2922 | }; |
2923 | ||
4ddff493 BC |
2924 | /* |
2925 | * 'mcbsp' class | |
2926 | * multi channel buffered serial port controller | |
2927 | */ | |
2928 | ||
2929 | static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { | |
2930 | .sysc_offs = 0x008c, | |
2931 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
2932 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2933 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2934 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2935 | }; | |
2936 | ||
2937 | static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { | |
2938 | .name = "mcbsp", | |
2939 | .sysc = &omap44xx_mcbsp_sysc, | |
cb7e9ded | 2940 | .rev = MCBSP_CONFIG_TYPE4, |
4ddff493 BC |
2941 | }; |
2942 | ||
2943 | /* mcbsp1 */ | |
2944 | static struct omap_hwmod omap44xx_mcbsp1_hwmod; | |
2945 | static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { | |
2946 | { .irq = 17 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2947 | { .irq = -1 } |
4ddff493 BC |
2948 | }; |
2949 | ||
2950 | static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { | |
2951 | { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, | |
2952 | { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2953 | { .dma_req = -1 } |
4ddff493 BC |
2954 | }; |
2955 | ||
2956 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { | |
2957 | { | |
cb7e9ded | 2958 | .name = "mpu", |
4ddff493 BC |
2959 | .pa_start = 0x40122000, |
2960 | .pa_end = 0x401220ff, | |
2961 | .flags = ADDR_TYPE_RT | |
2962 | }, | |
78183f3f | 2963 | { } |
4ddff493 BC |
2964 | }; |
2965 | ||
2966 | /* l4_abe -> mcbsp1 */ | |
2967 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { | |
2968 | .master = &omap44xx_l4_abe_hwmod, | |
2969 | .slave = &omap44xx_mcbsp1_hwmod, | |
2970 | .clk = "ocp_abe_iclk", | |
2971 | .addr = omap44xx_mcbsp1_addrs, | |
4ddff493 BC |
2972 | .user = OCP_USER_MPU, |
2973 | }; | |
2974 | ||
2975 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { | |
2976 | { | |
cb7e9ded | 2977 | .name = "dma", |
4ddff493 BC |
2978 | .pa_start = 0x49022000, |
2979 | .pa_end = 0x490220ff, | |
2980 | .flags = ADDR_TYPE_RT | |
2981 | }, | |
78183f3f | 2982 | { } |
4ddff493 BC |
2983 | }; |
2984 | ||
2985 | /* l4_abe -> mcbsp1 (dma) */ | |
2986 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { | |
2987 | .master = &omap44xx_l4_abe_hwmod, | |
2988 | .slave = &omap44xx_mcbsp1_hwmod, | |
2989 | .clk = "ocp_abe_iclk", | |
2990 | .addr = omap44xx_mcbsp1_dma_addrs, | |
4ddff493 BC |
2991 | .user = OCP_USER_SDMA, |
2992 | }; | |
2993 | ||
2994 | /* mcbsp1 slave ports */ | |
2995 | static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = { | |
2996 | &omap44xx_l4_abe__mcbsp1, | |
2997 | &omap44xx_l4_abe__mcbsp1_dma, | |
2998 | }; | |
2999 | ||
3000 | static struct omap_hwmod omap44xx_mcbsp1_hwmod = { | |
3001 | .name = "mcbsp1", | |
3002 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 3003 | .clkdm_name = "abe_clkdm", |
4ddff493 | 3004 | .mpu_irqs = omap44xx_mcbsp1_irqs, |
4ddff493 | 3005 | .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, |
4ddff493 BC |
3006 | .main_clk = "mcbsp1_fck", |
3007 | .prcm = { | |
3008 | .omap4 = { | |
d0f0631d | 3009 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, |
27bb00b5 | 3010 | .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET, |
03fdefe5 | 3011 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
3012 | }, |
3013 | }, | |
3014 | .slaves = omap44xx_mcbsp1_slaves, | |
3015 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves), | |
4ddff493 BC |
3016 | }; |
3017 | ||
3018 | /* mcbsp2 */ | |
3019 | static struct omap_hwmod omap44xx_mcbsp2_hwmod; | |
3020 | static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { | |
3021 | { .irq = 22 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3022 | { .irq = -1 } |
4ddff493 BC |
3023 | }; |
3024 | ||
3025 | static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { | |
3026 | { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START }, | |
3027 | { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3028 | { .dma_req = -1 } |
4ddff493 BC |
3029 | }; |
3030 | ||
3031 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { | |
3032 | { | |
cb7e9ded | 3033 | .name = "mpu", |
4ddff493 BC |
3034 | .pa_start = 0x40124000, |
3035 | .pa_end = 0x401240ff, | |
3036 | .flags = ADDR_TYPE_RT | |
3037 | }, | |
78183f3f | 3038 | { } |
4ddff493 BC |
3039 | }; |
3040 | ||
3041 | /* l4_abe -> mcbsp2 */ | |
3042 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { | |
3043 | .master = &omap44xx_l4_abe_hwmod, | |
3044 | .slave = &omap44xx_mcbsp2_hwmod, | |
3045 | .clk = "ocp_abe_iclk", | |
3046 | .addr = omap44xx_mcbsp2_addrs, | |
4ddff493 BC |
3047 | .user = OCP_USER_MPU, |
3048 | }; | |
3049 | ||
3050 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { | |
3051 | { | |
cb7e9ded | 3052 | .name = "dma", |
4ddff493 BC |
3053 | .pa_start = 0x49024000, |
3054 | .pa_end = 0x490240ff, | |
3055 | .flags = ADDR_TYPE_RT | |
3056 | }, | |
78183f3f | 3057 | { } |
4ddff493 BC |
3058 | }; |
3059 | ||
3060 | /* l4_abe -> mcbsp2 (dma) */ | |
3061 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { | |
3062 | .master = &omap44xx_l4_abe_hwmod, | |
3063 | .slave = &omap44xx_mcbsp2_hwmod, | |
3064 | .clk = "ocp_abe_iclk", | |
3065 | .addr = omap44xx_mcbsp2_dma_addrs, | |
4ddff493 BC |
3066 | .user = OCP_USER_SDMA, |
3067 | }; | |
3068 | ||
3069 | /* mcbsp2 slave ports */ | |
3070 | static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = { | |
3071 | &omap44xx_l4_abe__mcbsp2, | |
3072 | &omap44xx_l4_abe__mcbsp2_dma, | |
3073 | }; | |
3074 | ||
3075 | static struct omap_hwmod omap44xx_mcbsp2_hwmod = { | |
3076 | .name = "mcbsp2", | |
3077 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 3078 | .clkdm_name = "abe_clkdm", |
4ddff493 | 3079 | .mpu_irqs = omap44xx_mcbsp2_irqs, |
4ddff493 | 3080 | .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, |
4ddff493 BC |
3081 | .main_clk = "mcbsp2_fck", |
3082 | .prcm = { | |
3083 | .omap4 = { | |
d0f0631d | 3084 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, |
27bb00b5 | 3085 | .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET, |
03fdefe5 | 3086 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
3087 | }, |
3088 | }, | |
3089 | .slaves = omap44xx_mcbsp2_slaves, | |
3090 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves), | |
4ddff493 BC |
3091 | }; |
3092 | ||
3093 | /* mcbsp3 */ | |
3094 | static struct omap_hwmod omap44xx_mcbsp3_hwmod; | |
3095 | static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { | |
3096 | { .irq = 23 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3097 | { .irq = -1 } |
4ddff493 BC |
3098 | }; |
3099 | ||
3100 | static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { | |
3101 | { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START }, | |
3102 | { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3103 | { .dma_req = -1 } |
4ddff493 BC |
3104 | }; |
3105 | ||
3106 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { | |
3107 | { | |
cb7e9ded | 3108 | .name = "mpu", |
4ddff493 BC |
3109 | .pa_start = 0x40126000, |
3110 | .pa_end = 0x401260ff, | |
3111 | .flags = ADDR_TYPE_RT | |
3112 | }, | |
78183f3f | 3113 | { } |
4ddff493 BC |
3114 | }; |
3115 | ||
3116 | /* l4_abe -> mcbsp3 */ | |
3117 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { | |
3118 | .master = &omap44xx_l4_abe_hwmod, | |
3119 | .slave = &omap44xx_mcbsp3_hwmod, | |
3120 | .clk = "ocp_abe_iclk", | |
3121 | .addr = omap44xx_mcbsp3_addrs, | |
4ddff493 BC |
3122 | .user = OCP_USER_MPU, |
3123 | }; | |
3124 | ||
3125 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { | |
3126 | { | |
cb7e9ded | 3127 | .name = "dma", |
4ddff493 BC |
3128 | .pa_start = 0x49026000, |
3129 | .pa_end = 0x490260ff, | |
3130 | .flags = ADDR_TYPE_RT | |
3131 | }, | |
78183f3f | 3132 | { } |
4ddff493 BC |
3133 | }; |
3134 | ||
3135 | /* l4_abe -> mcbsp3 (dma) */ | |
3136 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { | |
3137 | .master = &omap44xx_l4_abe_hwmod, | |
3138 | .slave = &omap44xx_mcbsp3_hwmod, | |
3139 | .clk = "ocp_abe_iclk", | |
3140 | .addr = omap44xx_mcbsp3_dma_addrs, | |
4ddff493 BC |
3141 | .user = OCP_USER_SDMA, |
3142 | }; | |
3143 | ||
3144 | /* mcbsp3 slave ports */ | |
3145 | static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = { | |
3146 | &omap44xx_l4_abe__mcbsp3, | |
3147 | &omap44xx_l4_abe__mcbsp3_dma, | |
3148 | }; | |
3149 | ||
3150 | static struct omap_hwmod omap44xx_mcbsp3_hwmod = { | |
3151 | .name = "mcbsp3", | |
3152 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 3153 | .clkdm_name = "abe_clkdm", |
4ddff493 | 3154 | .mpu_irqs = omap44xx_mcbsp3_irqs, |
4ddff493 | 3155 | .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, |
4ddff493 BC |
3156 | .main_clk = "mcbsp3_fck", |
3157 | .prcm = { | |
3158 | .omap4 = { | |
d0f0631d | 3159 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, |
27bb00b5 | 3160 | .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET, |
03fdefe5 | 3161 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
3162 | }, |
3163 | }, | |
3164 | .slaves = omap44xx_mcbsp3_slaves, | |
3165 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves), | |
4ddff493 BC |
3166 | }; |
3167 | ||
3168 | /* mcbsp4 */ | |
3169 | static struct omap_hwmod omap44xx_mcbsp4_hwmod; | |
3170 | static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { | |
3171 | { .irq = 16 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3172 | { .irq = -1 } |
4ddff493 BC |
3173 | }; |
3174 | ||
3175 | static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { | |
3176 | { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START }, | |
3177 | { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3178 | { .dma_req = -1 } |
4ddff493 BC |
3179 | }; |
3180 | ||
3181 | static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { | |
3182 | { | |
3183 | .pa_start = 0x48096000, | |
3184 | .pa_end = 0x480960ff, | |
3185 | .flags = ADDR_TYPE_RT | |
3186 | }, | |
78183f3f | 3187 | { } |
4ddff493 BC |
3188 | }; |
3189 | ||
3190 | /* l4_per -> mcbsp4 */ | |
3191 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { | |
3192 | .master = &omap44xx_l4_per_hwmod, | |
3193 | .slave = &omap44xx_mcbsp4_hwmod, | |
3194 | .clk = "l4_div_ck", | |
3195 | .addr = omap44xx_mcbsp4_addrs, | |
4ddff493 BC |
3196 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3197 | }; | |
3198 | ||
3199 | /* mcbsp4 slave ports */ | |
3200 | static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = { | |
3201 | &omap44xx_l4_per__mcbsp4, | |
3202 | }; | |
3203 | ||
3204 | static struct omap_hwmod omap44xx_mcbsp4_hwmod = { | |
3205 | .name = "mcbsp4", | |
3206 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 3207 | .clkdm_name = "l4_per_clkdm", |
4ddff493 | 3208 | .mpu_irqs = omap44xx_mcbsp4_irqs, |
4ddff493 | 3209 | .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, |
4ddff493 BC |
3210 | .main_clk = "mcbsp4_fck", |
3211 | .prcm = { | |
3212 | .omap4 = { | |
d0f0631d | 3213 | .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, |
27bb00b5 | 3214 | .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET, |
03fdefe5 | 3215 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
3216 | }, |
3217 | }, | |
3218 | .slaves = omap44xx_mcbsp4_slaves, | |
3219 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves), | |
4ddff493 BC |
3220 | }; |
3221 | ||
407a6888 BC |
3222 | /* |
3223 | * 'mcpdm' class | |
3224 | * multi channel pdm controller (proprietary interface with phoenix power | |
3225 | * ic) | |
3226 | */ | |
3227 | ||
3228 | static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = { | |
3229 | .rev_offs = 0x0000, | |
3230 | .sysc_offs = 0x0010, | |
3231 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
3232 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
3233 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3234 | SIDLE_SMART_WKUP), | |
3235 | .sysc_fields = &omap_hwmod_sysc_type2, | |
3236 | }; | |
3237 | ||
3238 | static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { | |
3239 | .name = "mcpdm", | |
3240 | .sysc = &omap44xx_mcpdm_sysc, | |
3241 | }; | |
3242 | ||
3243 | /* mcpdm */ | |
3244 | static struct omap_hwmod omap44xx_mcpdm_hwmod; | |
3245 | static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { | |
3246 | { .irq = 112 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3247 | { .irq = -1 } |
407a6888 BC |
3248 | }; |
3249 | ||
3250 | static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { | |
3251 | { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START }, | |
3252 | { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3253 | { .dma_req = -1 } |
407a6888 BC |
3254 | }; |
3255 | ||
3256 | static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { | |
3257 | { | |
3258 | .pa_start = 0x40132000, | |
3259 | .pa_end = 0x4013207f, | |
3260 | .flags = ADDR_TYPE_RT | |
3261 | }, | |
78183f3f | 3262 | { } |
407a6888 BC |
3263 | }; |
3264 | ||
3265 | /* l4_abe -> mcpdm */ | |
3266 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { | |
3267 | .master = &omap44xx_l4_abe_hwmod, | |
3268 | .slave = &omap44xx_mcpdm_hwmod, | |
3269 | .clk = "ocp_abe_iclk", | |
3270 | .addr = omap44xx_mcpdm_addrs, | |
407a6888 BC |
3271 | .user = OCP_USER_MPU, |
3272 | }; | |
3273 | ||
3274 | static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { | |
3275 | { | |
3276 | .pa_start = 0x49032000, | |
3277 | .pa_end = 0x4903207f, | |
3278 | .flags = ADDR_TYPE_RT | |
3279 | }, | |
78183f3f | 3280 | { } |
407a6888 BC |
3281 | }; |
3282 | ||
3283 | /* l4_abe -> mcpdm (dma) */ | |
3284 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { | |
3285 | .master = &omap44xx_l4_abe_hwmod, | |
3286 | .slave = &omap44xx_mcpdm_hwmod, | |
3287 | .clk = "ocp_abe_iclk", | |
3288 | .addr = omap44xx_mcpdm_dma_addrs, | |
407a6888 BC |
3289 | .user = OCP_USER_SDMA, |
3290 | }; | |
3291 | ||
3292 | /* mcpdm slave ports */ | |
3293 | static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = { | |
3294 | &omap44xx_l4_abe__mcpdm, | |
3295 | &omap44xx_l4_abe__mcpdm_dma, | |
3296 | }; | |
3297 | ||
3298 | static struct omap_hwmod omap44xx_mcpdm_hwmod = { | |
3299 | .name = "mcpdm", | |
3300 | .class = &omap44xx_mcpdm_hwmod_class, | |
a5322c6f | 3301 | .clkdm_name = "abe_clkdm", |
407a6888 | 3302 | .mpu_irqs = omap44xx_mcpdm_irqs, |
407a6888 | 3303 | .sdma_reqs = omap44xx_mcpdm_sdma_reqs, |
407a6888 | 3304 | .main_clk = "mcpdm_fck", |
00fe610b | 3305 | .prcm = { |
407a6888 | 3306 | .omap4 = { |
d0f0631d | 3307 | .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, |
27bb00b5 | 3308 | .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET, |
03fdefe5 | 3309 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
3310 | }, |
3311 | }, | |
3312 | .slaves = omap44xx_mcpdm_slaves, | |
3313 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves), | |
407a6888 BC |
3314 | }; |
3315 | ||
9bcbd7f0 BC |
3316 | /* |
3317 | * 'mcspi' class | |
3318 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
3319 | * bus | |
3320 | */ | |
3321 | ||
3322 | static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = { | |
3323 | .rev_offs = 0x0000, | |
3324 | .sysc_offs = 0x0010, | |
3325 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
3326 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
3327 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3328 | SIDLE_SMART_WKUP), | |
3329 | .sysc_fields = &omap_hwmod_sysc_type2, | |
3330 | }; | |
3331 | ||
3332 | static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { | |
3333 | .name = "mcspi", | |
3334 | .sysc = &omap44xx_mcspi_sysc, | |
905a74d9 | 3335 | .rev = OMAP4_MCSPI_REV, |
9bcbd7f0 BC |
3336 | }; |
3337 | ||
3338 | /* mcspi1 */ | |
3339 | static struct omap_hwmod omap44xx_mcspi1_hwmod; | |
3340 | static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { | |
3341 | { .irq = 65 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3342 | { .irq = -1 } |
9bcbd7f0 BC |
3343 | }; |
3344 | ||
3345 | static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { | |
3346 | { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, | |
3347 | { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, | |
3348 | { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START }, | |
3349 | { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START }, | |
3350 | { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START }, | |
3351 | { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, | |
3352 | { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, | |
3353 | { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3354 | { .dma_req = -1 } |
9bcbd7f0 BC |
3355 | }; |
3356 | ||
3357 | static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { | |
3358 | { | |
3359 | .pa_start = 0x48098000, | |
3360 | .pa_end = 0x480981ff, | |
3361 | .flags = ADDR_TYPE_RT | |
3362 | }, | |
78183f3f | 3363 | { } |
9bcbd7f0 BC |
3364 | }; |
3365 | ||
3366 | /* l4_per -> mcspi1 */ | |
3367 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { | |
3368 | .master = &omap44xx_l4_per_hwmod, | |
3369 | .slave = &omap44xx_mcspi1_hwmod, | |
3370 | .clk = "l4_div_ck", | |
3371 | .addr = omap44xx_mcspi1_addrs, | |
9bcbd7f0 BC |
3372 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3373 | }; | |
3374 | ||
3375 | /* mcspi1 slave ports */ | |
3376 | static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = { | |
3377 | &omap44xx_l4_per__mcspi1, | |
3378 | }; | |
3379 | ||
905a74d9 BC |
3380 | /* mcspi1 dev_attr */ |
3381 | static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { | |
3382 | .num_chipselect = 4, | |
3383 | }; | |
3384 | ||
9bcbd7f0 BC |
3385 | static struct omap_hwmod omap44xx_mcspi1_hwmod = { |
3386 | .name = "mcspi1", | |
3387 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 3388 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 3389 | .mpu_irqs = omap44xx_mcspi1_irqs, |
9bcbd7f0 | 3390 | .sdma_reqs = omap44xx_mcspi1_sdma_reqs, |
9bcbd7f0 BC |
3391 | .main_clk = "mcspi1_fck", |
3392 | .prcm = { | |
3393 | .omap4 = { | |
d0f0631d | 3394 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, |
27bb00b5 | 3395 | .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET, |
03fdefe5 | 3396 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
3397 | }, |
3398 | }, | |
905a74d9 | 3399 | .dev_attr = &mcspi1_dev_attr, |
9bcbd7f0 BC |
3400 | .slaves = omap44xx_mcspi1_slaves, |
3401 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves), | |
9bcbd7f0 BC |
3402 | }; |
3403 | ||
3404 | /* mcspi2 */ | |
3405 | static struct omap_hwmod omap44xx_mcspi2_hwmod; | |
3406 | static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { | |
3407 | { .irq = 66 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3408 | { .irq = -1 } |
9bcbd7f0 BC |
3409 | }; |
3410 | ||
3411 | static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { | |
3412 | { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, | |
3413 | { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, | |
3414 | { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, | |
3415 | { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3416 | { .dma_req = -1 } |
9bcbd7f0 BC |
3417 | }; |
3418 | ||
3419 | static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { | |
3420 | { | |
3421 | .pa_start = 0x4809a000, | |
3422 | .pa_end = 0x4809a1ff, | |
3423 | .flags = ADDR_TYPE_RT | |
3424 | }, | |
78183f3f | 3425 | { } |
9bcbd7f0 BC |
3426 | }; |
3427 | ||
3428 | /* l4_per -> mcspi2 */ | |
3429 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { | |
3430 | .master = &omap44xx_l4_per_hwmod, | |
3431 | .slave = &omap44xx_mcspi2_hwmod, | |
3432 | .clk = "l4_div_ck", | |
3433 | .addr = omap44xx_mcspi2_addrs, | |
9bcbd7f0 BC |
3434 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3435 | }; | |
3436 | ||
3437 | /* mcspi2 slave ports */ | |
3438 | static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = { | |
3439 | &omap44xx_l4_per__mcspi2, | |
3440 | }; | |
3441 | ||
905a74d9 BC |
3442 | /* mcspi2 dev_attr */ |
3443 | static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { | |
3444 | .num_chipselect = 2, | |
3445 | }; | |
3446 | ||
9bcbd7f0 BC |
3447 | static struct omap_hwmod omap44xx_mcspi2_hwmod = { |
3448 | .name = "mcspi2", | |
3449 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 3450 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 3451 | .mpu_irqs = omap44xx_mcspi2_irqs, |
9bcbd7f0 | 3452 | .sdma_reqs = omap44xx_mcspi2_sdma_reqs, |
9bcbd7f0 BC |
3453 | .main_clk = "mcspi2_fck", |
3454 | .prcm = { | |
3455 | .omap4 = { | |
d0f0631d | 3456 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, |
27bb00b5 | 3457 | .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET, |
03fdefe5 | 3458 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
3459 | }, |
3460 | }, | |
905a74d9 | 3461 | .dev_attr = &mcspi2_dev_attr, |
9bcbd7f0 BC |
3462 | .slaves = omap44xx_mcspi2_slaves, |
3463 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves), | |
9bcbd7f0 BC |
3464 | }; |
3465 | ||
3466 | /* mcspi3 */ | |
3467 | static struct omap_hwmod omap44xx_mcspi3_hwmod; | |
3468 | static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { | |
3469 | { .irq = 91 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3470 | { .irq = -1 } |
9bcbd7f0 BC |
3471 | }; |
3472 | ||
3473 | static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { | |
3474 | { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, | |
3475 | { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, | |
3476 | { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, | |
3477 | { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3478 | { .dma_req = -1 } |
9bcbd7f0 BC |
3479 | }; |
3480 | ||
3481 | static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { | |
3482 | { | |
3483 | .pa_start = 0x480b8000, | |
3484 | .pa_end = 0x480b81ff, | |
3485 | .flags = ADDR_TYPE_RT | |
3486 | }, | |
78183f3f | 3487 | { } |
9bcbd7f0 BC |
3488 | }; |
3489 | ||
3490 | /* l4_per -> mcspi3 */ | |
3491 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { | |
3492 | .master = &omap44xx_l4_per_hwmod, | |
3493 | .slave = &omap44xx_mcspi3_hwmod, | |
3494 | .clk = "l4_div_ck", | |
3495 | .addr = omap44xx_mcspi3_addrs, | |
9bcbd7f0 BC |
3496 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3497 | }; | |
3498 | ||
3499 | /* mcspi3 slave ports */ | |
3500 | static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = { | |
3501 | &omap44xx_l4_per__mcspi3, | |
3502 | }; | |
3503 | ||
905a74d9 BC |
3504 | /* mcspi3 dev_attr */ |
3505 | static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { | |
3506 | .num_chipselect = 2, | |
3507 | }; | |
3508 | ||
9bcbd7f0 BC |
3509 | static struct omap_hwmod omap44xx_mcspi3_hwmod = { |
3510 | .name = "mcspi3", | |
3511 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 3512 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 3513 | .mpu_irqs = omap44xx_mcspi3_irqs, |
9bcbd7f0 | 3514 | .sdma_reqs = omap44xx_mcspi3_sdma_reqs, |
9bcbd7f0 BC |
3515 | .main_clk = "mcspi3_fck", |
3516 | .prcm = { | |
3517 | .omap4 = { | |
d0f0631d | 3518 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, |
27bb00b5 | 3519 | .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET, |
03fdefe5 | 3520 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
3521 | }, |
3522 | }, | |
905a74d9 | 3523 | .dev_attr = &mcspi3_dev_attr, |
9bcbd7f0 BC |
3524 | .slaves = omap44xx_mcspi3_slaves, |
3525 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves), | |
9bcbd7f0 BC |
3526 | }; |
3527 | ||
3528 | /* mcspi4 */ | |
3529 | static struct omap_hwmod omap44xx_mcspi4_hwmod; | |
3530 | static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { | |
3531 | { .irq = 48 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3532 | { .irq = -1 } |
9bcbd7f0 BC |
3533 | }; |
3534 | ||
3535 | static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { | |
3536 | { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, | |
3537 | { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3538 | { .dma_req = -1 } |
9bcbd7f0 BC |
3539 | }; |
3540 | ||
3541 | static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { | |
3542 | { | |
3543 | .pa_start = 0x480ba000, | |
3544 | .pa_end = 0x480ba1ff, | |
3545 | .flags = ADDR_TYPE_RT | |
3546 | }, | |
78183f3f | 3547 | { } |
9bcbd7f0 BC |
3548 | }; |
3549 | ||
3550 | /* l4_per -> mcspi4 */ | |
3551 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { | |
3552 | .master = &omap44xx_l4_per_hwmod, | |
3553 | .slave = &omap44xx_mcspi4_hwmod, | |
3554 | .clk = "l4_div_ck", | |
3555 | .addr = omap44xx_mcspi4_addrs, | |
9bcbd7f0 BC |
3556 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3557 | }; | |
3558 | ||
3559 | /* mcspi4 slave ports */ | |
3560 | static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = { | |
3561 | &omap44xx_l4_per__mcspi4, | |
3562 | }; | |
3563 | ||
905a74d9 BC |
3564 | /* mcspi4 dev_attr */ |
3565 | static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { | |
3566 | .num_chipselect = 1, | |
3567 | }; | |
3568 | ||
9bcbd7f0 BC |
3569 | static struct omap_hwmod omap44xx_mcspi4_hwmod = { |
3570 | .name = "mcspi4", | |
3571 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 3572 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 3573 | .mpu_irqs = omap44xx_mcspi4_irqs, |
9bcbd7f0 | 3574 | .sdma_reqs = omap44xx_mcspi4_sdma_reqs, |
9bcbd7f0 BC |
3575 | .main_clk = "mcspi4_fck", |
3576 | .prcm = { | |
3577 | .omap4 = { | |
d0f0631d | 3578 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, |
27bb00b5 | 3579 | .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET, |
03fdefe5 | 3580 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
3581 | }, |
3582 | }, | |
905a74d9 | 3583 | .dev_attr = &mcspi4_dev_attr, |
9bcbd7f0 BC |
3584 | .slaves = omap44xx_mcspi4_slaves, |
3585 | .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves), | |
9bcbd7f0 BC |
3586 | }; |
3587 | ||
407a6888 BC |
3588 | /* |
3589 | * 'mmc' class | |
3590 | * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller | |
3591 | */ | |
3592 | ||
3593 | static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = { | |
3594 | .rev_offs = 0x0000, | |
3595 | .sysc_offs = 0x0010, | |
3596 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
3597 | SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
3598 | SYSC_HAS_SOFTRESET), | |
3599 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3600 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 3601 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
3602 | .sysc_fields = &omap_hwmod_sysc_type2, |
3603 | }; | |
3604 | ||
3605 | static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { | |
3606 | .name = "mmc", | |
3607 | .sysc = &omap44xx_mmc_sysc, | |
3608 | }; | |
3609 | ||
3610 | /* mmc1 */ | |
3611 | static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { | |
3612 | { .irq = 83 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3613 | { .irq = -1 } |
407a6888 BC |
3614 | }; |
3615 | ||
3616 | static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { | |
3617 | { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, | |
3618 | { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3619 | { .dma_req = -1 } |
407a6888 BC |
3620 | }; |
3621 | ||
3622 | /* mmc1 master ports */ | |
3623 | static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = { | |
3624 | &omap44xx_mmc1__l3_main_1, | |
3625 | }; | |
3626 | ||
3627 | static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { | |
3628 | { | |
3629 | .pa_start = 0x4809c000, | |
3630 | .pa_end = 0x4809c3ff, | |
3631 | .flags = ADDR_TYPE_RT | |
3632 | }, | |
78183f3f | 3633 | { } |
407a6888 BC |
3634 | }; |
3635 | ||
3636 | /* l4_per -> mmc1 */ | |
3637 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { | |
3638 | .master = &omap44xx_l4_per_hwmod, | |
3639 | .slave = &omap44xx_mmc1_hwmod, | |
3640 | .clk = "l4_div_ck", | |
3641 | .addr = omap44xx_mmc1_addrs, | |
407a6888 BC |
3642 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3643 | }; | |
3644 | ||
3645 | /* mmc1 slave ports */ | |
3646 | static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = { | |
3647 | &omap44xx_l4_per__mmc1, | |
3648 | }; | |
3649 | ||
6ab8946f KK |
3650 | /* mmc1 dev_attr */ |
3651 | static struct omap_mmc_dev_attr mmc1_dev_attr = { | |
3652 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
3653 | }; | |
3654 | ||
407a6888 BC |
3655 | static struct omap_hwmod omap44xx_mmc1_hwmod = { |
3656 | .name = "mmc1", | |
3657 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 3658 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 3659 | .mpu_irqs = omap44xx_mmc1_irqs, |
407a6888 | 3660 | .sdma_reqs = omap44xx_mmc1_sdma_reqs, |
407a6888 | 3661 | .main_clk = "mmc1_fck", |
00fe610b | 3662 | .prcm = { |
407a6888 | 3663 | .omap4 = { |
d0f0631d | 3664 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET, |
27bb00b5 | 3665 | .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET, |
03fdefe5 | 3666 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
3667 | }, |
3668 | }, | |
6ab8946f | 3669 | .dev_attr = &mmc1_dev_attr, |
407a6888 BC |
3670 | .slaves = omap44xx_mmc1_slaves, |
3671 | .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves), | |
3672 | .masters = omap44xx_mmc1_masters, | |
3673 | .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters), | |
407a6888 BC |
3674 | }; |
3675 | ||
3676 | /* mmc2 */ | |
3677 | static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = { | |
3678 | { .irq = 86 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3679 | { .irq = -1 } |
407a6888 BC |
3680 | }; |
3681 | ||
3682 | static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { | |
3683 | { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, | |
3684 | { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3685 | { .dma_req = -1 } |
407a6888 BC |
3686 | }; |
3687 | ||
3688 | /* mmc2 master ports */ | |
3689 | static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = { | |
3690 | &omap44xx_mmc2__l3_main_1, | |
3691 | }; | |
3692 | ||
3693 | static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { | |
3694 | { | |
3695 | .pa_start = 0x480b4000, | |
3696 | .pa_end = 0x480b43ff, | |
3697 | .flags = ADDR_TYPE_RT | |
3698 | }, | |
78183f3f | 3699 | { } |
407a6888 BC |
3700 | }; |
3701 | ||
3702 | /* l4_per -> mmc2 */ | |
3703 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { | |
3704 | .master = &omap44xx_l4_per_hwmod, | |
3705 | .slave = &omap44xx_mmc2_hwmod, | |
3706 | .clk = "l4_div_ck", | |
3707 | .addr = omap44xx_mmc2_addrs, | |
407a6888 BC |
3708 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3709 | }; | |
3710 | ||
3711 | /* mmc2 slave ports */ | |
3712 | static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = { | |
3713 | &omap44xx_l4_per__mmc2, | |
3714 | }; | |
3715 | ||
3716 | static struct omap_hwmod omap44xx_mmc2_hwmod = { | |
3717 | .name = "mmc2", | |
3718 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 3719 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 3720 | .mpu_irqs = omap44xx_mmc2_irqs, |
407a6888 | 3721 | .sdma_reqs = omap44xx_mmc2_sdma_reqs, |
407a6888 | 3722 | .main_clk = "mmc2_fck", |
00fe610b | 3723 | .prcm = { |
407a6888 | 3724 | .omap4 = { |
d0f0631d | 3725 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET, |
27bb00b5 | 3726 | .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET, |
03fdefe5 | 3727 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
3728 | }, |
3729 | }, | |
3730 | .slaves = omap44xx_mmc2_slaves, | |
3731 | .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves), | |
3732 | .masters = omap44xx_mmc2_masters, | |
3733 | .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters), | |
407a6888 BC |
3734 | }; |
3735 | ||
3736 | /* mmc3 */ | |
3737 | static struct omap_hwmod omap44xx_mmc3_hwmod; | |
3738 | static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { | |
3739 | { .irq = 94 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3740 | { .irq = -1 } |
407a6888 BC |
3741 | }; |
3742 | ||
3743 | static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { | |
3744 | { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, | |
3745 | { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3746 | { .dma_req = -1 } |
407a6888 BC |
3747 | }; |
3748 | ||
3749 | static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { | |
3750 | { | |
3751 | .pa_start = 0x480ad000, | |
3752 | .pa_end = 0x480ad3ff, | |
3753 | .flags = ADDR_TYPE_RT | |
3754 | }, | |
78183f3f | 3755 | { } |
407a6888 BC |
3756 | }; |
3757 | ||
3758 | /* l4_per -> mmc3 */ | |
3759 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { | |
3760 | .master = &omap44xx_l4_per_hwmod, | |
3761 | .slave = &omap44xx_mmc3_hwmod, | |
3762 | .clk = "l4_div_ck", | |
3763 | .addr = omap44xx_mmc3_addrs, | |
407a6888 BC |
3764 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3765 | }; | |
3766 | ||
3767 | /* mmc3 slave ports */ | |
3768 | static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = { | |
3769 | &omap44xx_l4_per__mmc3, | |
3770 | }; | |
3771 | ||
3772 | static struct omap_hwmod omap44xx_mmc3_hwmod = { | |
3773 | .name = "mmc3", | |
3774 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 3775 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 3776 | .mpu_irqs = omap44xx_mmc3_irqs, |
407a6888 | 3777 | .sdma_reqs = omap44xx_mmc3_sdma_reqs, |
407a6888 | 3778 | .main_clk = "mmc3_fck", |
00fe610b | 3779 | .prcm = { |
407a6888 | 3780 | .omap4 = { |
d0f0631d | 3781 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET, |
27bb00b5 | 3782 | .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET, |
03fdefe5 | 3783 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
3784 | }, |
3785 | }, | |
3786 | .slaves = omap44xx_mmc3_slaves, | |
3787 | .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves), | |
407a6888 BC |
3788 | }; |
3789 | ||
3790 | /* mmc4 */ | |
3791 | static struct omap_hwmod omap44xx_mmc4_hwmod; | |
3792 | static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { | |
3793 | { .irq = 96 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3794 | { .irq = -1 } |
407a6888 BC |
3795 | }; |
3796 | ||
3797 | static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { | |
3798 | { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, | |
3799 | { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3800 | { .dma_req = -1 } |
407a6888 BC |
3801 | }; |
3802 | ||
3803 | static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { | |
3804 | { | |
3805 | .pa_start = 0x480d1000, | |
3806 | .pa_end = 0x480d13ff, | |
3807 | .flags = ADDR_TYPE_RT | |
3808 | }, | |
78183f3f | 3809 | { } |
407a6888 BC |
3810 | }; |
3811 | ||
3812 | /* l4_per -> mmc4 */ | |
3813 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { | |
3814 | .master = &omap44xx_l4_per_hwmod, | |
3815 | .slave = &omap44xx_mmc4_hwmod, | |
3816 | .clk = "l4_div_ck", | |
3817 | .addr = omap44xx_mmc4_addrs, | |
407a6888 BC |
3818 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3819 | }; | |
3820 | ||
3821 | /* mmc4 slave ports */ | |
3822 | static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = { | |
3823 | &omap44xx_l4_per__mmc4, | |
3824 | }; | |
3825 | ||
3826 | static struct omap_hwmod omap44xx_mmc4_hwmod = { | |
3827 | .name = "mmc4", | |
3828 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 3829 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 3830 | .mpu_irqs = omap44xx_mmc4_irqs, |
212738a4 | 3831 | |
407a6888 | 3832 | .sdma_reqs = omap44xx_mmc4_sdma_reqs, |
407a6888 | 3833 | .main_clk = "mmc4_fck", |
00fe610b | 3834 | .prcm = { |
407a6888 | 3835 | .omap4 = { |
d0f0631d | 3836 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET, |
27bb00b5 | 3837 | .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET, |
03fdefe5 | 3838 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
3839 | }, |
3840 | }, | |
3841 | .slaves = omap44xx_mmc4_slaves, | |
3842 | .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves), | |
407a6888 BC |
3843 | }; |
3844 | ||
3845 | /* mmc5 */ | |
3846 | static struct omap_hwmod omap44xx_mmc5_hwmod; | |
3847 | static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { | |
3848 | { .irq = 59 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3849 | { .irq = -1 } |
407a6888 BC |
3850 | }; |
3851 | ||
3852 | static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { | |
3853 | { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, | |
3854 | { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3855 | { .dma_req = -1 } |
407a6888 BC |
3856 | }; |
3857 | ||
3858 | static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { | |
3859 | { | |
3860 | .pa_start = 0x480d5000, | |
3861 | .pa_end = 0x480d53ff, | |
3862 | .flags = ADDR_TYPE_RT | |
3863 | }, | |
78183f3f | 3864 | { } |
407a6888 BC |
3865 | }; |
3866 | ||
3867 | /* l4_per -> mmc5 */ | |
3868 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { | |
3869 | .master = &omap44xx_l4_per_hwmod, | |
3870 | .slave = &omap44xx_mmc5_hwmod, | |
3871 | .clk = "l4_div_ck", | |
3872 | .addr = omap44xx_mmc5_addrs, | |
407a6888 BC |
3873 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3874 | }; | |
3875 | ||
3876 | /* mmc5 slave ports */ | |
3877 | static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = { | |
3878 | &omap44xx_l4_per__mmc5, | |
3879 | }; | |
3880 | ||
3881 | static struct omap_hwmod omap44xx_mmc5_hwmod = { | |
3882 | .name = "mmc5", | |
3883 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 3884 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 3885 | .mpu_irqs = omap44xx_mmc5_irqs, |
407a6888 | 3886 | .sdma_reqs = omap44xx_mmc5_sdma_reqs, |
407a6888 | 3887 | .main_clk = "mmc5_fck", |
00fe610b | 3888 | .prcm = { |
407a6888 | 3889 | .omap4 = { |
d0f0631d | 3890 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET, |
27bb00b5 | 3891 | .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET, |
03fdefe5 | 3892 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
3893 | }, |
3894 | }, | |
3895 | .slaves = omap44xx_mmc5_slaves, | |
3896 | .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves), | |
407a6888 BC |
3897 | }; |
3898 | ||
3b54baad BC |
3899 | /* |
3900 | * 'mpu' class | |
3901 | * mpu sub-system | |
3902 | */ | |
3903 | ||
3904 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { | |
fe13471c | 3905 | .name = "mpu", |
db12ba53 BC |
3906 | }; |
3907 | ||
3b54baad BC |
3908 | /* mpu */ |
3909 | static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { | |
3910 | { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, | |
3911 | { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, | |
3912 | { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3913 | { .irq = -1 } |
db12ba53 BC |
3914 | }; |
3915 | ||
3b54baad BC |
3916 | /* mpu master ports */ |
3917 | static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = { | |
3918 | &omap44xx_mpu__l3_main_1, | |
3919 | &omap44xx_mpu__l4_abe, | |
3920 | &omap44xx_mpu__dmm, | |
3921 | }; | |
3922 | ||
3923 | static struct omap_hwmod omap44xx_mpu_hwmod = { | |
3924 | .name = "mpu", | |
3925 | .class = &omap44xx_mpu_hwmod_class, | |
a5322c6f | 3926 | .clkdm_name = "mpuss_clkdm", |
7ecc5373 | 3927 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
3b54baad | 3928 | .mpu_irqs = omap44xx_mpu_irqs, |
3b54baad | 3929 | .main_clk = "dpll_mpu_m2_ck", |
db12ba53 BC |
3930 | .prcm = { |
3931 | .omap4 = { | |
d0f0631d | 3932 | .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 3933 | .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, |
db12ba53 BC |
3934 | }, |
3935 | }, | |
3b54baad BC |
3936 | .masters = omap44xx_mpu_masters, |
3937 | .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters), | |
db12ba53 BC |
3938 | }; |
3939 | ||
1f6a717f BC |
3940 | /* |
3941 | * 'smartreflex' class | |
3942 | * smartreflex module (monitor silicon performance and outputs a measure of | |
3943 | * performance error) | |
3944 | */ | |
3945 | ||
3946 | /* The IP is not compliant to type1 / type2 scheme */ | |
3947 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { | |
3948 | .sidle_shift = 24, | |
3949 | .enwkup_shift = 26, | |
3950 | }; | |
3951 | ||
3952 | static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { | |
3953 | .sysc_offs = 0x0038, | |
3954 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), | |
3955 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3956 | SIDLE_SMART_WKUP), | |
3957 | .sysc_fields = &omap_hwmod_sysc_type_smartreflex, | |
3958 | }; | |
3959 | ||
3960 | static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { | |
fe13471c BC |
3961 | .name = "smartreflex", |
3962 | .sysc = &omap44xx_smartreflex_sysc, | |
3963 | .rev = 2, | |
1f6a717f BC |
3964 | }; |
3965 | ||
3966 | /* smartreflex_core */ | |
cea6b942 SG |
3967 | static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { |
3968 | .sensor_voltdm_name = "core", | |
3969 | }; | |
3970 | ||
1f6a717f BC |
3971 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod; |
3972 | static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { | |
3973 | { .irq = 19 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3974 | { .irq = -1 } |
1f6a717f BC |
3975 | }; |
3976 | ||
3977 | static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { | |
3978 | { | |
3979 | .pa_start = 0x4a0dd000, | |
3980 | .pa_end = 0x4a0dd03f, | |
3981 | .flags = ADDR_TYPE_RT | |
3982 | }, | |
78183f3f | 3983 | { } |
1f6a717f BC |
3984 | }; |
3985 | ||
3986 | /* l4_cfg -> smartreflex_core */ | |
3987 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { | |
3988 | .master = &omap44xx_l4_cfg_hwmod, | |
3989 | .slave = &omap44xx_smartreflex_core_hwmod, | |
3990 | .clk = "l4_div_ck", | |
3991 | .addr = omap44xx_smartreflex_core_addrs, | |
1f6a717f BC |
3992 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3993 | }; | |
3994 | ||
3995 | /* smartreflex_core slave ports */ | |
3996 | static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = { | |
3997 | &omap44xx_l4_cfg__smartreflex_core, | |
3998 | }; | |
3999 | ||
4000 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { | |
4001 | .name = "smartreflex_core", | |
4002 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 4003 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 4004 | .mpu_irqs = omap44xx_smartreflex_core_irqs, |
212738a4 | 4005 | |
1f6a717f | 4006 | .main_clk = "smartreflex_core_fck", |
1f6a717f BC |
4007 | .prcm = { |
4008 | .omap4 = { | |
d0f0631d | 4009 | .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET, |
27bb00b5 | 4010 | .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET, |
03fdefe5 | 4011 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
4012 | }, |
4013 | }, | |
4014 | .slaves = omap44xx_smartreflex_core_slaves, | |
4015 | .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves), | |
cea6b942 | 4016 | .dev_attr = &smartreflex_core_dev_attr, |
1f6a717f BC |
4017 | }; |
4018 | ||
4019 | /* smartreflex_iva */ | |
cea6b942 SG |
4020 | static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { |
4021 | .sensor_voltdm_name = "iva", | |
4022 | }; | |
4023 | ||
1f6a717f BC |
4024 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod; |
4025 | static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { | |
4026 | { .irq = 102 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4027 | { .irq = -1 } |
1f6a717f BC |
4028 | }; |
4029 | ||
4030 | static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { | |
4031 | { | |
4032 | .pa_start = 0x4a0db000, | |
4033 | .pa_end = 0x4a0db03f, | |
4034 | .flags = ADDR_TYPE_RT | |
4035 | }, | |
78183f3f | 4036 | { } |
1f6a717f BC |
4037 | }; |
4038 | ||
4039 | /* l4_cfg -> smartreflex_iva */ | |
4040 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { | |
4041 | .master = &omap44xx_l4_cfg_hwmod, | |
4042 | .slave = &omap44xx_smartreflex_iva_hwmod, | |
4043 | .clk = "l4_div_ck", | |
4044 | .addr = omap44xx_smartreflex_iva_addrs, | |
1f6a717f BC |
4045 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4046 | }; | |
4047 | ||
4048 | /* smartreflex_iva slave ports */ | |
4049 | static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = { | |
4050 | &omap44xx_l4_cfg__smartreflex_iva, | |
4051 | }; | |
4052 | ||
4053 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { | |
4054 | .name = "smartreflex_iva", | |
4055 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 4056 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 4057 | .mpu_irqs = omap44xx_smartreflex_iva_irqs, |
1f6a717f | 4058 | .main_clk = "smartreflex_iva_fck", |
1f6a717f BC |
4059 | .prcm = { |
4060 | .omap4 = { | |
d0f0631d | 4061 | .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET, |
27bb00b5 | 4062 | .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET, |
03fdefe5 | 4063 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
4064 | }, |
4065 | }, | |
4066 | .slaves = omap44xx_smartreflex_iva_slaves, | |
4067 | .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves), | |
cea6b942 | 4068 | .dev_attr = &smartreflex_iva_dev_attr, |
1f6a717f BC |
4069 | }; |
4070 | ||
4071 | /* smartreflex_mpu */ | |
cea6b942 SG |
4072 | static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { |
4073 | .sensor_voltdm_name = "mpu", | |
4074 | }; | |
4075 | ||
1f6a717f BC |
4076 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod; |
4077 | static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { | |
4078 | { .irq = 18 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4079 | { .irq = -1 } |
1f6a717f BC |
4080 | }; |
4081 | ||
4082 | static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { | |
4083 | { | |
4084 | .pa_start = 0x4a0d9000, | |
4085 | .pa_end = 0x4a0d903f, | |
4086 | .flags = ADDR_TYPE_RT | |
4087 | }, | |
78183f3f | 4088 | { } |
1f6a717f BC |
4089 | }; |
4090 | ||
4091 | /* l4_cfg -> smartreflex_mpu */ | |
4092 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { | |
4093 | .master = &omap44xx_l4_cfg_hwmod, | |
4094 | .slave = &omap44xx_smartreflex_mpu_hwmod, | |
4095 | .clk = "l4_div_ck", | |
4096 | .addr = omap44xx_smartreflex_mpu_addrs, | |
1f6a717f BC |
4097 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4098 | }; | |
4099 | ||
4100 | /* smartreflex_mpu slave ports */ | |
4101 | static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = { | |
4102 | &omap44xx_l4_cfg__smartreflex_mpu, | |
4103 | }; | |
4104 | ||
4105 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { | |
4106 | .name = "smartreflex_mpu", | |
4107 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 4108 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 4109 | .mpu_irqs = omap44xx_smartreflex_mpu_irqs, |
1f6a717f | 4110 | .main_clk = "smartreflex_mpu_fck", |
1f6a717f BC |
4111 | .prcm = { |
4112 | .omap4 = { | |
d0f0631d | 4113 | .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 4114 | .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET, |
03fdefe5 | 4115 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
4116 | }, |
4117 | }, | |
4118 | .slaves = omap44xx_smartreflex_mpu_slaves, | |
4119 | .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves), | |
cea6b942 | 4120 | .dev_attr = &smartreflex_mpu_dev_attr, |
1f6a717f BC |
4121 | }; |
4122 | ||
d11c217f BC |
4123 | /* |
4124 | * 'spinlock' class | |
4125 | * spinlock provides hardware assistance for synchronizing the processes | |
4126 | * running on multiple processors | |
4127 | */ | |
4128 | ||
4129 | static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = { | |
4130 | .rev_offs = 0x0000, | |
4131 | .sysc_offs = 0x0010, | |
4132 | .syss_offs = 0x0014, | |
4133 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
4134 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
4135 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
4136 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
4137 | SIDLE_SMART_WKUP), | |
4138 | .sysc_fields = &omap_hwmod_sysc_type1, | |
4139 | }; | |
4140 | ||
4141 | static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { | |
4142 | .name = "spinlock", | |
4143 | .sysc = &omap44xx_spinlock_sysc, | |
4144 | }; | |
4145 | ||
4146 | /* spinlock */ | |
4147 | static struct omap_hwmod omap44xx_spinlock_hwmod; | |
4148 | static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { | |
4149 | { | |
4150 | .pa_start = 0x4a0f6000, | |
4151 | .pa_end = 0x4a0f6fff, | |
4152 | .flags = ADDR_TYPE_RT | |
4153 | }, | |
78183f3f | 4154 | { } |
d11c217f BC |
4155 | }; |
4156 | ||
4157 | /* l4_cfg -> spinlock */ | |
4158 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { | |
4159 | .master = &omap44xx_l4_cfg_hwmod, | |
4160 | .slave = &omap44xx_spinlock_hwmod, | |
4161 | .clk = "l4_div_ck", | |
4162 | .addr = omap44xx_spinlock_addrs, | |
d11c217f BC |
4163 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4164 | }; | |
4165 | ||
4166 | /* spinlock slave ports */ | |
4167 | static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = { | |
4168 | &omap44xx_l4_cfg__spinlock, | |
4169 | }; | |
4170 | ||
4171 | static struct omap_hwmod omap44xx_spinlock_hwmod = { | |
4172 | .name = "spinlock", | |
4173 | .class = &omap44xx_spinlock_hwmod_class, | |
a5322c6f | 4174 | .clkdm_name = "l4_cfg_clkdm", |
d11c217f BC |
4175 | .prcm = { |
4176 | .omap4 = { | |
d0f0631d | 4177 | .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET, |
27bb00b5 | 4178 | .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, |
d11c217f BC |
4179 | }, |
4180 | }, | |
4181 | .slaves = omap44xx_spinlock_slaves, | |
4182 | .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves), | |
d11c217f BC |
4183 | }; |
4184 | ||
35d1a66a BC |
4185 | /* |
4186 | * 'timer' class | |
4187 | * general purpose timer module with accurate 1ms tick | |
4188 | * This class contains several variants: ['timer_1ms', 'timer'] | |
4189 | */ | |
4190 | ||
4191 | static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = { | |
4192 | .rev_offs = 0x0000, | |
4193 | .sysc_offs = 0x0010, | |
4194 | .syss_offs = 0x0014, | |
4195 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
4196 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
4197 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
4198 | SYSS_HAS_RESET_STATUS), | |
4199 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
4200 | .sysc_fields = &omap_hwmod_sysc_type1, | |
4201 | }; | |
4202 | ||
4203 | static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = { | |
4204 | .name = "timer", | |
4205 | .sysc = &omap44xx_timer_1ms_sysc, | |
4206 | }; | |
4207 | ||
4208 | static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = { | |
4209 | .rev_offs = 0x0000, | |
4210 | .sysc_offs = 0x0010, | |
4211 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
4212 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
4213 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
4214 | SIDLE_SMART_WKUP), | |
4215 | .sysc_fields = &omap_hwmod_sysc_type2, | |
4216 | }; | |
4217 | ||
4218 | static struct omap_hwmod_class omap44xx_timer_hwmod_class = { | |
4219 | .name = "timer", | |
4220 | .sysc = &omap44xx_timer_sysc, | |
4221 | }; | |
4222 | ||
c345c8b0 TKD |
4223 | /* always-on timers dev attribute */ |
4224 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
4225 | .timer_capability = OMAP_TIMER_ALWON, | |
4226 | }; | |
4227 | ||
4228 | /* pwm timers dev attribute */ | |
4229 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
4230 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
4231 | }; | |
4232 | ||
35d1a66a BC |
4233 | /* timer1 */ |
4234 | static struct omap_hwmod omap44xx_timer1_hwmod; | |
4235 | static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { | |
4236 | { .irq = 37 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4237 | { .irq = -1 } |
35d1a66a BC |
4238 | }; |
4239 | ||
4240 | static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { | |
4241 | { | |
4242 | .pa_start = 0x4a318000, | |
4243 | .pa_end = 0x4a31807f, | |
4244 | .flags = ADDR_TYPE_RT | |
4245 | }, | |
78183f3f | 4246 | { } |
35d1a66a BC |
4247 | }; |
4248 | ||
4249 | /* l4_wkup -> timer1 */ | |
4250 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { | |
4251 | .master = &omap44xx_l4_wkup_hwmod, | |
4252 | .slave = &omap44xx_timer1_hwmod, | |
4253 | .clk = "l4_wkup_clk_mux_ck", | |
4254 | .addr = omap44xx_timer1_addrs, | |
35d1a66a BC |
4255 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4256 | }; | |
4257 | ||
4258 | /* timer1 slave ports */ | |
4259 | static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = { | |
4260 | &omap44xx_l4_wkup__timer1, | |
4261 | }; | |
4262 | ||
4263 | static struct omap_hwmod omap44xx_timer1_hwmod = { | |
4264 | .name = "timer1", | |
4265 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 4266 | .clkdm_name = "l4_wkup_clkdm", |
35d1a66a | 4267 | .mpu_irqs = omap44xx_timer1_irqs, |
35d1a66a BC |
4268 | .main_clk = "timer1_fck", |
4269 | .prcm = { | |
4270 | .omap4 = { | |
d0f0631d | 4271 | .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, |
27bb00b5 | 4272 | .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET, |
03fdefe5 | 4273 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4274 | }, |
4275 | }, | |
c345c8b0 | 4276 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
4277 | .slaves = omap44xx_timer1_slaves, |
4278 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves), | |
35d1a66a BC |
4279 | }; |
4280 | ||
4281 | /* timer2 */ | |
4282 | static struct omap_hwmod omap44xx_timer2_hwmod; | |
4283 | static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { | |
4284 | { .irq = 38 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4285 | { .irq = -1 } |
35d1a66a BC |
4286 | }; |
4287 | ||
4288 | static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { | |
4289 | { | |
4290 | .pa_start = 0x48032000, | |
4291 | .pa_end = 0x4803207f, | |
4292 | .flags = ADDR_TYPE_RT | |
4293 | }, | |
78183f3f | 4294 | { } |
35d1a66a BC |
4295 | }; |
4296 | ||
4297 | /* l4_per -> timer2 */ | |
4298 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { | |
4299 | .master = &omap44xx_l4_per_hwmod, | |
4300 | .slave = &omap44xx_timer2_hwmod, | |
4301 | .clk = "l4_div_ck", | |
4302 | .addr = omap44xx_timer2_addrs, | |
35d1a66a BC |
4303 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4304 | }; | |
4305 | ||
4306 | /* timer2 slave ports */ | |
4307 | static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = { | |
4308 | &omap44xx_l4_per__timer2, | |
4309 | }; | |
4310 | ||
4311 | static struct omap_hwmod omap44xx_timer2_hwmod = { | |
4312 | .name = "timer2", | |
4313 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 4314 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 4315 | .mpu_irqs = omap44xx_timer2_irqs, |
35d1a66a BC |
4316 | .main_clk = "timer2_fck", |
4317 | .prcm = { | |
4318 | .omap4 = { | |
d0f0631d | 4319 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, |
27bb00b5 | 4320 | .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET, |
03fdefe5 | 4321 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4322 | }, |
4323 | }, | |
c345c8b0 | 4324 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
4325 | .slaves = omap44xx_timer2_slaves, |
4326 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves), | |
35d1a66a BC |
4327 | }; |
4328 | ||
4329 | /* timer3 */ | |
4330 | static struct omap_hwmod omap44xx_timer3_hwmod; | |
4331 | static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { | |
4332 | { .irq = 39 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4333 | { .irq = -1 } |
35d1a66a BC |
4334 | }; |
4335 | ||
4336 | static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { | |
4337 | { | |
4338 | .pa_start = 0x48034000, | |
4339 | .pa_end = 0x4803407f, | |
4340 | .flags = ADDR_TYPE_RT | |
4341 | }, | |
78183f3f | 4342 | { } |
35d1a66a BC |
4343 | }; |
4344 | ||
4345 | /* l4_per -> timer3 */ | |
4346 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { | |
4347 | .master = &omap44xx_l4_per_hwmod, | |
4348 | .slave = &omap44xx_timer3_hwmod, | |
4349 | .clk = "l4_div_ck", | |
4350 | .addr = omap44xx_timer3_addrs, | |
35d1a66a BC |
4351 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4352 | }; | |
4353 | ||
4354 | /* timer3 slave ports */ | |
4355 | static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = { | |
4356 | &omap44xx_l4_per__timer3, | |
4357 | }; | |
4358 | ||
4359 | static struct omap_hwmod omap44xx_timer3_hwmod = { | |
4360 | .name = "timer3", | |
4361 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4362 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 4363 | .mpu_irqs = omap44xx_timer3_irqs, |
35d1a66a BC |
4364 | .main_clk = "timer3_fck", |
4365 | .prcm = { | |
4366 | .omap4 = { | |
d0f0631d | 4367 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, |
27bb00b5 | 4368 | .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET, |
03fdefe5 | 4369 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4370 | }, |
4371 | }, | |
c345c8b0 | 4372 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
4373 | .slaves = omap44xx_timer3_slaves, |
4374 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves), | |
35d1a66a BC |
4375 | }; |
4376 | ||
4377 | /* timer4 */ | |
4378 | static struct omap_hwmod omap44xx_timer4_hwmod; | |
4379 | static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { | |
4380 | { .irq = 40 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4381 | { .irq = -1 } |
35d1a66a BC |
4382 | }; |
4383 | ||
4384 | static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { | |
4385 | { | |
4386 | .pa_start = 0x48036000, | |
4387 | .pa_end = 0x4803607f, | |
4388 | .flags = ADDR_TYPE_RT | |
4389 | }, | |
78183f3f | 4390 | { } |
35d1a66a BC |
4391 | }; |
4392 | ||
4393 | /* l4_per -> timer4 */ | |
4394 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { | |
4395 | .master = &omap44xx_l4_per_hwmod, | |
4396 | .slave = &omap44xx_timer4_hwmod, | |
4397 | .clk = "l4_div_ck", | |
4398 | .addr = omap44xx_timer4_addrs, | |
35d1a66a BC |
4399 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4400 | }; | |
4401 | ||
4402 | /* timer4 slave ports */ | |
4403 | static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = { | |
4404 | &omap44xx_l4_per__timer4, | |
4405 | }; | |
4406 | ||
4407 | static struct omap_hwmod omap44xx_timer4_hwmod = { | |
4408 | .name = "timer4", | |
4409 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4410 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 4411 | .mpu_irqs = omap44xx_timer4_irqs, |
35d1a66a BC |
4412 | .main_clk = "timer4_fck", |
4413 | .prcm = { | |
4414 | .omap4 = { | |
d0f0631d | 4415 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, |
27bb00b5 | 4416 | .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET, |
03fdefe5 | 4417 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4418 | }, |
4419 | }, | |
c345c8b0 | 4420 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
4421 | .slaves = omap44xx_timer4_slaves, |
4422 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves), | |
35d1a66a BC |
4423 | }; |
4424 | ||
4425 | /* timer5 */ | |
4426 | static struct omap_hwmod omap44xx_timer5_hwmod; | |
4427 | static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { | |
4428 | { .irq = 41 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4429 | { .irq = -1 } |
35d1a66a BC |
4430 | }; |
4431 | ||
4432 | static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { | |
4433 | { | |
4434 | .pa_start = 0x40138000, | |
4435 | .pa_end = 0x4013807f, | |
4436 | .flags = ADDR_TYPE_RT | |
4437 | }, | |
78183f3f | 4438 | { } |
35d1a66a BC |
4439 | }; |
4440 | ||
4441 | /* l4_abe -> timer5 */ | |
4442 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { | |
4443 | .master = &omap44xx_l4_abe_hwmod, | |
4444 | .slave = &omap44xx_timer5_hwmod, | |
4445 | .clk = "ocp_abe_iclk", | |
4446 | .addr = omap44xx_timer5_addrs, | |
35d1a66a BC |
4447 | .user = OCP_USER_MPU, |
4448 | }; | |
4449 | ||
4450 | static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { | |
4451 | { | |
4452 | .pa_start = 0x49038000, | |
4453 | .pa_end = 0x4903807f, | |
4454 | .flags = ADDR_TYPE_RT | |
4455 | }, | |
78183f3f | 4456 | { } |
35d1a66a BC |
4457 | }; |
4458 | ||
4459 | /* l4_abe -> timer5 (dma) */ | |
4460 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { | |
4461 | .master = &omap44xx_l4_abe_hwmod, | |
4462 | .slave = &omap44xx_timer5_hwmod, | |
4463 | .clk = "ocp_abe_iclk", | |
4464 | .addr = omap44xx_timer5_dma_addrs, | |
35d1a66a BC |
4465 | .user = OCP_USER_SDMA, |
4466 | }; | |
4467 | ||
4468 | /* timer5 slave ports */ | |
4469 | static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = { | |
4470 | &omap44xx_l4_abe__timer5, | |
4471 | &omap44xx_l4_abe__timer5_dma, | |
4472 | }; | |
4473 | ||
4474 | static struct omap_hwmod omap44xx_timer5_hwmod = { | |
4475 | .name = "timer5", | |
4476 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4477 | .clkdm_name = "abe_clkdm", |
35d1a66a | 4478 | .mpu_irqs = omap44xx_timer5_irqs, |
35d1a66a BC |
4479 | .main_clk = "timer5_fck", |
4480 | .prcm = { | |
4481 | .omap4 = { | |
d0f0631d | 4482 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, |
27bb00b5 | 4483 | .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET, |
03fdefe5 | 4484 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4485 | }, |
4486 | }, | |
c345c8b0 | 4487 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
4488 | .slaves = omap44xx_timer5_slaves, |
4489 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves), | |
35d1a66a BC |
4490 | }; |
4491 | ||
4492 | /* timer6 */ | |
4493 | static struct omap_hwmod omap44xx_timer6_hwmod; | |
4494 | static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { | |
4495 | { .irq = 42 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4496 | { .irq = -1 } |
35d1a66a BC |
4497 | }; |
4498 | ||
4499 | static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { | |
4500 | { | |
4501 | .pa_start = 0x4013a000, | |
4502 | .pa_end = 0x4013a07f, | |
4503 | .flags = ADDR_TYPE_RT | |
4504 | }, | |
78183f3f | 4505 | { } |
35d1a66a BC |
4506 | }; |
4507 | ||
4508 | /* l4_abe -> timer6 */ | |
4509 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { | |
4510 | .master = &omap44xx_l4_abe_hwmod, | |
4511 | .slave = &omap44xx_timer6_hwmod, | |
4512 | .clk = "ocp_abe_iclk", | |
4513 | .addr = omap44xx_timer6_addrs, | |
35d1a66a BC |
4514 | .user = OCP_USER_MPU, |
4515 | }; | |
4516 | ||
4517 | static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { | |
4518 | { | |
4519 | .pa_start = 0x4903a000, | |
4520 | .pa_end = 0x4903a07f, | |
4521 | .flags = ADDR_TYPE_RT | |
4522 | }, | |
78183f3f | 4523 | { } |
35d1a66a BC |
4524 | }; |
4525 | ||
4526 | /* l4_abe -> timer6 (dma) */ | |
4527 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { | |
4528 | .master = &omap44xx_l4_abe_hwmod, | |
4529 | .slave = &omap44xx_timer6_hwmod, | |
4530 | .clk = "ocp_abe_iclk", | |
4531 | .addr = omap44xx_timer6_dma_addrs, | |
35d1a66a BC |
4532 | .user = OCP_USER_SDMA, |
4533 | }; | |
4534 | ||
4535 | /* timer6 slave ports */ | |
4536 | static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = { | |
4537 | &omap44xx_l4_abe__timer6, | |
4538 | &omap44xx_l4_abe__timer6_dma, | |
4539 | }; | |
4540 | ||
4541 | static struct omap_hwmod omap44xx_timer6_hwmod = { | |
4542 | .name = "timer6", | |
4543 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4544 | .clkdm_name = "abe_clkdm", |
35d1a66a | 4545 | .mpu_irqs = omap44xx_timer6_irqs, |
212738a4 | 4546 | |
35d1a66a BC |
4547 | .main_clk = "timer6_fck", |
4548 | .prcm = { | |
4549 | .omap4 = { | |
d0f0631d | 4550 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, |
27bb00b5 | 4551 | .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET, |
03fdefe5 | 4552 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4553 | }, |
4554 | }, | |
c345c8b0 | 4555 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
4556 | .slaves = omap44xx_timer6_slaves, |
4557 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves), | |
35d1a66a BC |
4558 | }; |
4559 | ||
4560 | /* timer7 */ | |
4561 | static struct omap_hwmod omap44xx_timer7_hwmod; | |
4562 | static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { | |
4563 | { .irq = 43 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4564 | { .irq = -1 } |
35d1a66a BC |
4565 | }; |
4566 | ||
4567 | static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { | |
4568 | { | |
4569 | .pa_start = 0x4013c000, | |
4570 | .pa_end = 0x4013c07f, | |
4571 | .flags = ADDR_TYPE_RT | |
4572 | }, | |
78183f3f | 4573 | { } |
35d1a66a BC |
4574 | }; |
4575 | ||
4576 | /* l4_abe -> timer7 */ | |
4577 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { | |
4578 | .master = &omap44xx_l4_abe_hwmod, | |
4579 | .slave = &omap44xx_timer7_hwmod, | |
4580 | .clk = "ocp_abe_iclk", | |
4581 | .addr = omap44xx_timer7_addrs, | |
35d1a66a BC |
4582 | .user = OCP_USER_MPU, |
4583 | }; | |
4584 | ||
4585 | static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { | |
4586 | { | |
4587 | .pa_start = 0x4903c000, | |
4588 | .pa_end = 0x4903c07f, | |
4589 | .flags = ADDR_TYPE_RT | |
4590 | }, | |
78183f3f | 4591 | { } |
35d1a66a BC |
4592 | }; |
4593 | ||
4594 | /* l4_abe -> timer7 (dma) */ | |
4595 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { | |
4596 | .master = &omap44xx_l4_abe_hwmod, | |
4597 | .slave = &omap44xx_timer7_hwmod, | |
4598 | .clk = "ocp_abe_iclk", | |
4599 | .addr = omap44xx_timer7_dma_addrs, | |
35d1a66a BC |
4600 | .user = OCP_USER_SDMA, |
4601 | }; | |
4602 | ||
4603 | /* timer7 slave ports */ | |
4604 | static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = { | |
4605 | &omap44xx_l4_abe__timer7, | |
4606 | &omap44xx_l4_abe__timer7_dma, | |
4607 | }; | |
4608 | ||
4609 | static struct omap_hwmod omap44xx_timer7_hwmod = { | |
4610 | .name = "timer7", | |
4611 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4612 | .clkdm_name = "abe_clkdm", |
35d1a66a | 4613 | .mpu_irqs = omap44xx_timer7_irqs, |
35d1a66a BC |
4614 | .main_clk = "timer7_fck", |
4615 | .prcm = { | |
4616 | .omap4 = { | |
d0f0631d | 4617 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, |
27bb00b5 | 4618 | .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET, |
03fdefe5 | 4619 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4620 | }, |
4621 | }, | |
c345c8b0 | 4622 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
4623 | .slaves = omap44xx_timer7_slaves, |
4624 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves), | |
35d1a66a BC |
4625 | }; |
4626 | ||
4627 | /* timer8 */ | |
4628 | static struct omap_hwmod omap44xx_timer8_hwmod; | |
4629 | static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { | |
4630 | { .irq = 44 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4631 | { .irq = -1 } |
35d1a66a BC |
4632 | }; |
4633 | ||
4634 | static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { | |
4635 | { | |
4636 | .pa_start = 0x4013e000, | |
4637 | .pa_end = 0x4013e07f, | |
4638 | .flags = ADDR_TYPE_RT | |
4639 | }, | |
78183f3f | 4640 | { } |
35d1a66a BC |
4641 | }; |
4642 | ||
4643 | /* l4_abe -> timer8 */ | |
4644 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { | |
4645 | .master = &omap44xx_l4_abe_hwmod, | |
4646 | .slave = &omap44xx_timer8_hwmod, | |
4647 | .clk = "ocp_abe_iclk", | |
4648 | .addr = omap44xx_timer8_addrs, | |
35d1a66a BC |
4649 | .user = OCP_USER_MPU, |
4650 | }; | |
4651 | ||
4652 | static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { | |
4653 | { | |
4654 | .pa_start = 0x4903e000, | |
4655 | .pa_end = 0x4903e07f, | |
4656 | .flags = ADDR_TYPE_RT | |
4657 | }, | |
78183f3f | 4658 | { } |
35d1a66a BC |
4659 | }; |
4660 | ||
4661 | /* l4_abe -> timer8 (dma) */ | |
4662 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { | |
4663 | .master = &omap44xx_l4_abe_hwmod, | |
4664 | .slave = &omap44xx_timer8_hwmod, | |
4665 | .clk = "ocp_abe_iclk", | |
4666 | .addr = omap44xx_timer8_dma_addrs, | |
35d1a66a BC |
4667 | .user = OCP_USER_SDMA, |
4668 | }; | |
4669 | ||
4670 | /* timer8 slave ports */ | |
4671 | static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = { | |
4672 | &omap44xx_l4_abe__timer8, | |
4673 | &omap44xx_l4_abe__timer8_dma, | |
4674 | }; | |
4675 | ||
4676 | static struct omap_hwmod omap44xx_timer8_hwmod = { | |
4677 | .name = "timer8", | |
4678 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4679 | .clkdm_name = "abe_clkdm", |
35d1a66a | 4680 | .mpu_irqs = omap44xx_timer8_irqs, |
35d1a66a BC |
4681 | .main_clk = "timer8_fck", |
4682 | .prcm = { | |
4683 | .omap4 = { | |
d0f0631d | 4684 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, |
27bb00b5 | 4685 | .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET, |
03fdefe5 | 4686 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4687 | }, |
4688 | }, | |
c345c8b0 | 4689 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
4690 | .slaves = omap44xx_timer8_slaves, |
4691 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves), | |
35d1a66a BC |
4692 | }; |
4693 | ||
4694 | /* timer9 */ | |
4695 | static struct omap_hwmod omap44xx_timer9_hwmod; | |
4696 | static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { | |
4697 | { .irq = 45 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4698 | { .irq = -1 } |
35d1a66a BC |
4699 | }; |
4700 | ||
4701 | static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { | |
4702 | { | |
4703 | .pa_start = 0x4803e000, | |
4704 | .pa_end = 0x4803e07f, | |
4705 | .flags = ADDR_TYPE_RT | |
4706 | }, | |
78183f3f | 4707 | { } |
35d1a66a BC |
4708 | }; |
4709 | ||
4710 | /* l4_per -> timer9 */ | |
4711 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { | |
4712 | .master = &omap44xx_l4_per_hwmod, | |
4713 | .slave = &omap44xx_timer9_hwmod, | |
4714 | .clk = "l4_div_ck", | |
4715 | .addr = omap44xx_timer9_addrs, | |
35d1a66a BC |
4716 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4717 | }; | |
4718 | ||
4719 | /* timer9 slave ports */ | |
4720 | static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = { | |
4721 | &omap44xx_l4_per__timer9, | |
4722 | }; | |
4723 | ||
4724 | static struct omap_hwmod omap44xx_timer9_hwmod = { | |
4725 | .name = "timer9", | |
4726 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4727 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 4728 | .mpu_irqs = omap44xx_timer9_irqs, |
35d1a66a BC |
4729 | .main_clk = "timer9_fck", |
4730 | .prcm = { | |
4731 | .omap4 = { | |
d0f0631d | 4732 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, |
27bb00b5 | 4733 | .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET, |
03fdefe5 | 4734 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4735 | }, |
4736 | }, | |
c345c8b0 | 4737 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
4738 | .slaves = omap44xx_timer9_slaves, |
4739 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves), | |
35d1a66a BC |
4740 | }; |
4741 | ||
4742 | /* timer10 */ | |
4743 | static struct omap_hwmod omap44xx_timer10_hwmod; | |
4744 | static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { | |
4745 | { .irq = 46 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4746 | { .irq = -1 } |
35d1a66a BC |
4747 | }; |
4748 | ||
4749 | static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { | |
4750 | { | |
4751 | .pa_start = 0x48086000, | |
4752 | .pa_end = 0x4808607f, | |
4753 | .flags = ADDR_TYPE_RT | |
4754 | }, | |
78183f3f | 4755 | { } |
35d1a66a BC |
4756 | }; |
4757 | ||
4758 | /* l4_per -> timer10 */ | |
4759 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { | |
4760 | .master = &omap44xx_l4_per_hwmod, | |
4761 | .slave = &omap44xx_timer10_hwmod, | |
4762 | .clk = "l4_div_ck", | |
4763 | .addr = omap44xx_timer10_addrs, | |
35d1a66a BC |
4764 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4765 | }; | |
4766 | ||
4767 | /* timer10 slave ports */ | |
4768 | static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = { | |
4769 | &omap44xx_l4_per__timer10, | |
4770 | }; | |
4771 | ||
4772 | static struct omap_hwmod omap44xx_timer10_hwmod = { | |
4773 | .name = "timer10", | |
4774 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 4775 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 4776 | .mpu_irqs = omap44xx_timer10_irqs, |
35d1a66a BC |
4777 | .main_clk = "timer10_fck", |
4778 | .prcm = { | |
4779 | .omap4 = { | |
d0f0631d | 4780 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, |
27bb00b5 | 4781 | .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET, |
03fdefe5 | 4782 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4783 | }, |
4784 | }, | |
c345c8b0 | 4785 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
4786 | .slaves = omap44xx_timer10_slaves, |
4787 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves), | |
35d1a66a BC |
4788 | }; |
4789 | ||
4790 | /* timer11 */ | |
4791 | static struct omap_hwmod omap44xx_timer11_hwmod; | |
4792 | static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { | |
4793 | { .irq = 47 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4794 | { .irq = -1 } |
35d1a66a BC |
4795 | }; |
4796 | ||
4797 | static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { | |
4798 | { | |
4799 | .pa_start = 0x48088000, | |
4800 | .pa_end = 0x4808807f, | |
4801 | .flags = ADDR_TYPE_RT | |
4802 | }, | |
78183f3f | 4803 | { } |
35d1a66a BC |
4804 | }; |
4805 | ||
4806 | /* l4_per -> timer11 */ | |
4807 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { | |
4808 | .master = &omap44xx_l4_per_hwmod, | |
4809 | .slave = &omap44xx_timer11_hwmod, | |
4810 | .clk = "l4_div_ck", | |
4811 | .addr = omap44xx_timer11_addrs, | |
35d1a66a BC |
4812 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4813 | }; | |
4814 | ||
4815 | /* timer11 slave ports */ | |
4816 | static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = { | |
4817 | &omap44xx_l4_per__timer11, | |
4818 | }; | |
4819 | ||
4820 | static struct omap_hwmod omap44xx_timer11_hwmod = { | |
4821 | .name = "timer11", | |
4822 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 4823 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 4824 | .mpu_irqs = omap44xx_timer11_irqs, |
35d1a66a BC |
4825 | .main_clk = "timer11_fck", |
4826 | .prcm = { | |
4827 | .omap4 = { | |
d0f0631d | 4828 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, |
27bb00b5 | 4829 | .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET, |
03fdefe5 | 4830 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
4831 | }, |
4832 | }, | |
c345c8b0 | 4833 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
4834 | .slaves = omap44xx_timer11_slaves, |
4835 | .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves), | |
35d1a66a BC |
4836 | }; |
4837 | ||
9780a9cf | 4838 | /* |
3b54baad BC |
4839 | * 'uart' class |
4840 | * universal asynchronous receiver/transmitter (uart) | |
9780a9cf BC |
4841 | */ |
4842 | ||
3b54baad BC |
4843 | static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { |
4844 | .rev_offs = 0x0050, | |
4845 | .sysc_offs = 0x0054, | |
4846 | .syss_offs = 0x0058, | |
4847 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
0cfe8751 BC |
4848 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
4849 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
4850 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
4851 | SIDLE_SMART_WKUP), | |
9780a9cf BC |
4852 | .sysc_fields = &omap_hwmod_sysc_type1, |
4853 | }; | |
4854 | ||
3b54baad | 4855 | static struct omap_hwmod_class omap44xx_uart_hwmod_class = { |
fe13471c BC |
4856 | .name = "uart", |
4857 | .sysc = &omap44xx_uart_sysc, | |
9780a9cf BC |
4858 | }; |
4859 | ||
3b54baad BC |
4860 | /* uart1 */ |
4861 | static struct omap_hwmod omap44xx_uart1_hwmod; | |
4862 | static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { | |
4863 | { .irq = 72 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4864 | { .irq = -1 } |
9780a9cf BC |
4865 | }; |
4866 | ||
3b54baad BC |
4867 | static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { |
4868 | { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, | |
4869 | { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 4870 | { .dma_req = -1 } |
9780a9cf BC |
4871 | }; |
4872 | ||
3b54baad | 4873 | static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { |
9780a9cf | 4874 | { |
3b54baad BC |
4875 | .pa_start = 0x4806a000, |
4876 | .pa_end = 0x4806a0ff, | |
9780a9cf BC |
4877 | .flags = ADDR_TYPE_RT |
4878 | }, | |
78183f3f | 4879 | { } |
9780a9cf BC |
4880 | }; |
4881 | ||
3b54baad BC |
4882 | /* l4_per -> uart1 */ |
4883 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { | |
4884 | .master = &omap44xx_l4_per_hwmod, | |
4885 | .slave = &omap44xx_uart1_hwmod, | |
4886 | .clk = "l4_div_ck", | |
4887 | .addr = omap44xx_uart1_addrs, | |
9780a9cf BC |
4888 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4889 | }; | |
4890 | ||
3b54baad BC |
4891 | /* uart1 slave ports */ |
4892 | static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = { | |
4893 | &omap44xx_l4_per__uart1, | |
9780a9cf BC |
4894 | }; |
4895 | ||
3b54baad BC |
4896 | static struct omap_hwmod omap44xx_uart1_hwmod = { |
4897 | .name = "uart1", | |
4898 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 4899 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 4900 | .mpu_irqs = omap44xx_uart1_irqs, |
3b54baad | 4901 | .sdma_reqs = omap44xx_uart1_sdma_reqs, |
3b54baad | 4902 | .main_clk = "uart1_fck", |
9780a9cf BC |
4903 | .prcm = { |
4904 | .omap4 = { | |
d0f0631d | 4905 | .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET, |
27bb00b5 | 4906 | .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET, |
03fdefe5 | 4907 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
4908 | }, |
4909 | }, | |
3b54baad BC |
4910 | .slaves = omap44xx_uart1_slaves, |
4911 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves), | |
9780a9cf BC |
4912 | }; |
4913 | ||
3b54baad BC |
4914 | /* uart2 */ |
4915 | static struct omap_hwmod omap44xx_uart2_hwmod; | |
4916 | static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { | |
4917 | { .irq = 73 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4918 | { .irq = -1 } |
9780a9cf BC |
4919 | }; |
4920 | ||
3b54baad BC |
4921 | static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { |
4922 | { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, | |
4923 | { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 4924 | { .dma_req = -1 } |
3b54baad BC |
4925 | }; |
4926 | ||
4927 | static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { | |
9780a9cf | 4928 | { |
3b54baad BC |
4929 | .pa_start = 0x4806c000, |
4930 | .pa_end = 0x4806c0ff, | |
9780a9cf BC |
4931 | .flags = ADDR_TYPE_RT |
4932 | }, | |
78183f3f | 4933 | { } |
9780a9cf BC |
4934 | }; |
4935 | ||
3b54baad BC |
4936 | /* l4_per -> uart2 */ |
4937 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { | |
9780a9cf | 4938 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
4939 | .slave = &omap44xx_uart2_hwmod, |
4940 | .clk = "l4_div_ck", | |
4941 | .addr = omap44xx_uart2_addrs, | |
9780a9cf BC |
4942 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4943 | }; | |
4944 | ||
3b54baad BC |
4945 | /* uart2 slave ports */ |
4946 | static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = { | |
4947 | &omap44xx_l4_per__uart2, | |
9780a9cf BC |
4948 | }; |
4949 | ||
3b54baad BC |
4950 | static struct omap_hwmod omap44xx_uart2_hwmod = { |
4951 | .name = "uart2", | |
4952 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 4953 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 4954 | .mpu_irqs = omap44xx_uart2_irqs, |
3b54baad | 4955 | .sdma_reqs = omap44xx_uart2_sdma_reqs, |
3b54baad | 4956 | .main_clk = "uart2_fck", |
9780a9cf BC |
4957 | .prcm = { |
4958 | .omap4 = { | |
d0f0631d | 4959 | .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET, |
27bb00b5 | 4960 | .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET, |
03fdefe5 | 4961 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
4962 | }, |
4963 | }, | |
3b54baad BC |
4964 | .slaves = omap44xx_uart2_slaves, |
4965 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves), | |
9780a9cf BC |
4966 | }; |
4967 | ||
3b54baad BC |
4968 | /* uart3 */ |
4969 | static struct omap_hwmod omap44xx_uart3_hwmod; | |
4970 | static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { | |
4971 | { .irq = 74 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 4972 | { .irq = -1 } |
9780a9cf BC |
4973 | }; |
4974 | ||
3b54baad BC |
4975 | static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { |
4976 | { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, | |
4977 | { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 4978 | { .dma_req = -1 } |
3b54baad BC |
4979 | }; |
4980 | ||
4981 | static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { | |
9780a9cf | 4982 | { |
3b54baad BC |
4983 | .pa_start = 0x48020000, |
4984 | .pa_end = 0x480200ff, | |
9780a9cf BC |
4985 | .flags = ADDR_TYPE_RT |
4986 | }, | |
78183f3f | 4987 | { } |
9780a9cf BC |
4988 | }; |
4989 | ||
3b54baad BC |
4990 | /* l4_per -> uart3 */ |
4991 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { | |
9780a9cf | 4992 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
4993 | .slave = &omap44xx_uart3_hwmod, |
4994 | .clk = "l4_div_ck", | |
4995 | .addr = omap44xx_uart3_addrs, | |
9780a9cf BC |
4996 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4997 | }; | |
4998 | ||
3b54baad BC |
4999 | /* uart3 slave ports */ |
5000 | static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = { | |
5001 | &omap44xx_l4_per__uart3, | |
5002 | }; | |
5003 | ||
5004 | static struct omap_hwmod omap44xx_uart3_hwmod = { | |
5005 | .name = "uart3", | |
5006 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 5007 | .clkdm_name = "l4_per_clkdm", |
7ecc5373 | 5008 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
3b54baad | 5009 | .mpu_irqs = omap44xx_uart3_irqs, |
3b54baad | 5010 | .sdma_reqs = omap44xx_uart3_sdma_reqs, |
3b54baad | 5011 | .main_clk = "uart3_fck", |
9780a9cf BC |
5012 | .prcm = { |
5013 | .omap4 = { | |
d0f0631d | 5014 | .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET, |
27bb00b5 | 5015 | .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET, |
03fdefe5 | 5016 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
5017 | }, |
5018 | }, | |
3b54baad BC |
5019 | .slaves = omap44xx_uart3_slaves, |
5020 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves), | |
9780a9cf BC |
5021 | }; |
5022 | ||
3b54baad BC |
5023 | /* uart4 */ |
5024 | static struct omap_hwmod omap44xx_uart4_hwmod; | |
5025 | static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { | |
5026 | { .irq = 70 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 5027 | { .irq = -1 } |
9780a9cf BC |
5028 | }; |
5029 | ||
3b54baad BC |
5030 | static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { |
5031 | { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, | |
5032 | { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 5033 | { .dma_req = -1 } |
3b54baad BC |
5034 | }; |
5035 | ||
5036 | static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { | |
9780a9cf | 5037 | { |
3b54baad BC |
5038 | .pa_start = 0x4806e000, |
5039 | .pa_end = 0x4806e0ff, | |
9780a9cf BC |
5040 | .flags = ADDR_TYPE_RT |
5041 | }, | |
78183f3f | 5042 | { } |
9780a9cf BC |
5043 | }; |
5044 | ||
3b54baad BC |
5045 | /* l4_per -> uart4 */ |
5046 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { | |
9780a9cf | 5047 | .master = &omap44xx_l4_per_hwmod, |
3b54baad BC |
5048 | .slave = &omap44xx_uart4_hwmod, |
5049 | .clk = "l4_div_ck", | |
5050 | .addr = omap44xx_uart4_addrs, | |
9780a9cf BC |
5051 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
5052 | }; | |
5053 | ||
3b54baad BC |
5054 | /* uart4 slave ports */ |
5055 | static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = { | |
5056 | &omap44xx_l4_per__uart4, | |
9780a9cf BC |
5057 | }; |
5058 | ||
3b54baad BC |
5059 | static struct omap_hwmod omap44xx_uart4_hwmod = { |
5060 | .name = "uart4", | |
5061 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 5062 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 5063 | .mpu_irqs = omap44xx_uart4_irqs, |
3b54baad | 5064 | .sdma_reqs = omap44xx_uart4_sdma_reqs, |
3b54baad | 5065 | .main_clk = "uart4_fck", |
9780a9cf BC |
5066 | .prcm = { |
5067 | .omap4 = { | |
d0f0631d | 5068 | .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET, |
27bb00b5 | 5069 | .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET, |
03fdefe5 | 5070 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
5071 | }, |
5072 | }, | |
3b54baad BC |
5073 | .slaves = omap44xx_uart4_slaves, |
5074 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves), | |
9780a9cf BC |
5075 | }; |
5076 | ||
5844c4ea BC |
5077 | /* |
5078 | * 'usb_otg_hs' class | |
5079 | * high-speed on-the-go universal serial bus (usb_otg_hs) controller | |
5080 | */ | |
5081 | ||
5082 | static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { | |
5083 | .rev_offs = 0x0400, | |
5084 | .sysc_offs = 0x0404, | |
5085 | .syss_offs = 0x0408, | |
5086 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
5087 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
5088 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
5089 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
5090 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
5091 | MSTANDBY_SMART), | |
5092 | .sysc_fields = &omap_hwmod_sysc_type1, | |
5093 | }; | |
5094 | ||
5095 | static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { | |
00fe610b BC |
5096 | .name = "usb_otg_hs", |
5097 | .sysc = &omap44xx_usb_otg_hs_sysc, | |
5844c4ea BC |
5098 | }; |
5099 | ||
5100 | /* usb_otg_hs */ | |
5101 | static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { | |
5102 | { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, | |
5103 | { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 5104 | { .irq = -1 } |
5844c4ea BC |
5105 | }; |
5106 | ||
5107 | /* usb_otg_hs master ports */ | |
5108 | static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = { | |
5109 | &omap44xx_usb_otg_hs__l3_main_2, | |
5110 | }; | |
5111 | ||
5112 | static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { | |
5113 | { | |
5114 | .pa_start = 0x4a0ab000, | |
5115 | .pa_end = 0x4a0ab003, | |
5116 | .flags = ADDR_TYPE_RT | |
5117 | }, | |
78183f3f | 5118 | { } |
5844c4ea BC |
5119 | }; |
5120 | ||
5121 | /* l4_cfg -> usb_otg_hs */ | |
5122 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { | |
5123 | .master = &omap44xx_l4_cfg_hwmod, | |
5124 | .slave = &omap44xx_usb_otg_hs_hwmod, | |
5125 | .clk = "l4_div_ck", | |
5126 | .addr = omap44xx_usb_otg_hs_addrs, | |
5844c4ea BC |
5127 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
5128 | }; | |
5129 | ||
5130 | /* usb_otg_hs slave ports */ | |
5131 | static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = { | |
5132 | &omap44xx_l4_cfg__usb_otg_hs, | |
5133 | }; | |
5134 | ||
5135 | static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { | |
5136 | { .role = "xclk", .clk = "usb_otg_hs_xclk" }, | |
5137 | }; | |
5138 | ||
5139 | static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { | |
5140 | .name = "usb_otg_hs", | |
5141 | .class = &omap44xx_usb_otg_hs_hwmod_class, | |
a5322c6f | 5142 | .clkdm_name = "l3_init_clkdm", |
5844c4ea BC |
5143 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
5144 | .mpu_irqs = omap44xx_usb_otg_hs_irqs, | |
5844c4ea BC |
5145 | .main_clk = "usb_otg_hs_ick", |
5146 | .prcm = { | |
5147 | .omap4 = { | |
d0f0631d | 5148 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET, |
27bb00b5 | 5149 | .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET, |
03fdefe5 | 5150 | .modulemode = MODULEMODE_HWCTRL, |
5844c4ea BC |
5151 | }, |
5152 | }, | |
5153 | .opt_clks = usb_otg_hs_opt_clks, | |
00fe610b | 5154 | .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), |
5844c4ea BC |
5155 | .slaves = omap44xx_usb_otg_hs_slaves, |
5156 | .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves), | |
5157 | .masters = omap44xx_usb_otg_hs_masters, | |
5158 | .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters), | |
5844c4ea BC |
5159 | }; |
5160 | ||
3b54baad BC |
5161 | /* |
5162 | * 'wd_timer' class | |
5163 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
5164 | * overflow condition | |
5165 | */ | |
5166 | ||
5167 | static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { | |
5168 | .rev_offs = 0x0000, | |
5169 | .sysc_offs = 0x0010, | |
5170 | .syss_offs = 0x0014, | |
5171 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 5172 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
5173 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
5174 | SIDLE_SMART_WKUP), | |
3b54baad | 5175 | .sysc_fields = &omap_hwmod_sysc_type1, |
9780a9cf BC |
5176 | }; |
5177 | ||
3b54baad BC |
5178 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { |
5179 | .name = "wd_timer", | |
5180 | .sysc = &omap44xx_wd_timer_sysc, | |
fe13471c | 5181 | .pre_shutdown = &omap2_wd_timer_disable, |
3b54baad BC |
5182 | }; |
5183 | ||
5184 | /* wd_timer2 */ | |
5185 | static struct omap_hwmod omap44xx_wd_timer2_hwmod; | |
5186 | static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { | |
5187 | { .irq = 80 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 5188 | { .irq = -1 } |
3b54baad BC |
5189 | }; |
5190 | ||
5191 | static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { | |
9780a9cf | 5192 | { |
3b54baad BC |
5193 | .pa_start = 0x4a314000, |
5194 | .pa_end = 0x4a31407f, | |
9780a9cf BC |
5195 | .flags = ADDR_TYPE_RT |
5196 | }, | |
78183f3f | 5197 | { } |
9780a9cf BC |
5198 | }; |
5199 | ||
3b54baad BC |
5200 | /* l4_wkup -> wd_timer2 */ |
5201 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { | |
5202 | .master = &omap44xx_l4_wkup_hwmod, | |
5203 | .slave = &omap44xx_wd_timer2_hwmod, | |
5204 | .clk = "l4_wkup_clk_mux_ck", | |
5205 | .addr = omap44xx_wd_timer2_addrs, | |
9780a9cf BC |
5206 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
5207 | }; | |
5208 | ||
3b54baad BC |
5209 | /* wd_timer2 slave ports */ |
5210 | static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = { | |
5211 | &omap44xx_l4_wkup__wd_timer2, | |
9780a9cf BC |
5212 | }; |
5213 | ||
3b54baad BC |
5214 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { |
5215 | .name = "wd_timer2", | |
5216 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 5217 | .clkdm_name = "l4_wkup_clkdm", |
3b54baad | 5218 | .mpu_irqs = omap44xx_wd_timer2_irqs, |
3b54baad | 5219 | .main_clk = "wd_timer2_fck", |
9780a9cf BC |
5220 | .prcm = { |
5221 | .omap4 = { | |
d0f0631d | 5222 | .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, |
27bb00b5 | 5223 | .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET, |
03fdefe5 | 5224 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
5225 | }, |
5226 | }, | |
3b54baad BC |
5227 | .slaves = omap44xx_wd_timer2_slaves, |
5228 | .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves), | |
9780a9cf BC |
5229 | }; |
5230 | ||
3b54baad BC |
5231 | /* wd_timer3 */ |
5232 | static struct omap_hwmod omap44xx_wd_timer3_hwmod; | |
5233 | static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { | |
5234 | { .irq = 36 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 5235 | { .irq = -1 } |
9780a9cf BC |
5236 | }; |
5237 | ||
3b54baad | 5238 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { |
9780a9cf | 5239 | { |
3b54baad BC |
5240 | .pa_start = 0x40130000, |
5241 | .pa_end = 0x4013007f, | |
9780a9cf BC |
5242 | .flags = ADDR_TYPE_RT |
5243 | }, | |
78183f3f | 5244 | { } |
9780a9cf BC |
5245 | }; |
5246 | ||
3b54baad BC |
5247 | /* l4_abe -> wd_timer3 */ |
5248 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { | |
5249 | .master = &omap44xx_l4_abe_hwmod, | |
5250 | .slave = &omap44xx_wd_timer3_hwmod, | |
5251 | .clk = "ocp_abe_iclk", | |
5252 | .addr = omap44xx_wd_timer3_addrs, | |
3b54baad | 5253 | .user = OCP_USER_MPU, |
9780a9cf BC |
5254 | }; |
5255 | ||
3b54baad BC |
5256 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { |
5257 | { | |
5258 | .pa_start = 0x49030000, | |
5259 | .pa_end = 0x4903007f, | |
5260 | .flags = ADDR_TYPE_RT | |
5261 | }, | |
78183f3f | 5262 | { } |
9780a9cf BC |
5263 | }; |
5264 | ||
3b54baad BC |
5265 | /* l4_abe -> wd_timer3 (dma) */ |
5266 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { | |
5267 | .master = &omap44xx_l4_abe_hwmod, | |
5268 | .slave = &omap44xx_wd_timer3_hwmod, | |
5269 | .clk = "ocp_abe_iclk", | |
5270 | .addr = omap44xx_wd_timer3_dma_addrs, | |
3b54baad | 5271 | .user = OCP_USER_SDMA, |
9780a9cf BC |
5272 | }; |
5273 | ||
3b54baad BC |
5274 | /* wd_timer3 slave ports */ |
5275 | static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = { | |
5276 | &omap44xx_l4_abe__wd_timer3, | |
5277 | &omap44xx_l4_abe__wd_timer3_dma, | |
5278 | }; | |
5279 | ||
5280 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { | |
5281 | .name = "wd_timer3", | |
5282 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 5283 | .clkdm_name = "abe_clkdm", |
3b54baad | 5284 | .mpu_irqs = omap44xx_wd_timer3_irqs, |
3b54baad | 5285 | .main_clk = "wd_timer3_fck", |
9780a9cf BC |
5286 | .prcm = { |
5287 | .omap4 = { | |
d0f0631d | 5288 | .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, |
27bb00b5 | 5289 | .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET, |
03fdefe5 | 5290 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
5291 | }, |
5292 | }, | |
3b54baad BC |
5293 | .slaves = omap44xx_wd_timer3_slaves, |
5294 | .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), | |
9780a9cf | 5295 | }; |
531ce0d5 | 5296 | |
af88fa9a BC |
5297 | /* |
5298 | * 'usb_host_hs' class | |
5299 | * high-speed multi-port usb host controller | |
5300 | */ | |
5301 | static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { | |
5302 | .master = &omap44xx_usb_host_hs_hwmod, | |
5303 | .slave = &omap44xx_l3_main_2_hwmod, | |
5304 | .clk = "l3_div_ck", | |
5305 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5306 | }; | |
5307 | ||
5308 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { | |
5309 | .rev_offs = 0x0000, | |
5310 | .sysc_offs = 0x0010, | |
5311 | .syss_offs = 0x0014, | |
5312 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
5313 | SYSC_HAS_SOFTRESET), | |
5314 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
5315 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
5316 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
5317 | .sysc_fields = &omap_hwmod_sysc_type2, | |
5318 | }; | |
5319 | ||
5320 | static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { | |
5321 | .name = "usb_host_hs", | |
5322 | .sysc = &omap44xx_usb_host_hs_sysc, | |
5323 | }; | |
5324 | ||
5325 | static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = { | |
5326 | &omap44xx_usb_host_hs__l3_main_2, | |
5327 | }; | |
5328 | ||
5329 | static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { | |
5330 | { | |
5331 | .name = "uhh", | |
5332 | .pa_start = 0x4a064000, | |
5333 | .pa_end = 0x4a0647ff, | |
5334 | .flags = ADDR_TYPE_RT | |
5335 | }, | |
5336 | { | |
5337 | .name = "ohci", | |
5338 | .pa_start = 0x4a064800, | |
5339 | .pa_end = 0x4a064bff, | |
5340 | }, | |
5341 | { | |
5342 | .name = "ehci", | |
5343 | .pa_start = 0x4a064c00, | |
5344 | .pa_end = 0x4a064fff, | |
5345 | }, | |
5346 | {} | |
5347 | }; | |
5348 | ||
5349 | static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { | |
5350 | { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, | |
5351 | { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, | |
5352 | { .irq = -1 } | |
5353 | }; | |
5354 | ||
5355 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { | |
5356 | .master = &omap44xx_l4_cfg_hwmod, | |
5357 | .slave = &omap44xx_usb_host_hs_hwmod, | |
5358 | .clk = "l4_div_ck", | |
5359 | .addr = omap44xx_usb_host_hs_addrs, | |
5360 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5361 | }; | |
5362 | ||
5363 | static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = { | |
5364 | &omap44xx_l4_cfg__usb_host_hs, | |
5365 | }; | |
5366 | ||
5367 | static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { | |
5368 | .name = "usb_host_hs", | |
5369 | .class = &omap44xx_usb_host_hs_hwmod_class, | |
5370 | .clkdm_name = "l3_init_clkdm", | |
5371 | .main_clk = "usb_host_hs_fck", | |
5372 | .prcm = { | |
5373 | .omap4 = { | |
5374 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, | |
5375 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, | |
5376 | .modulemode = MODULEMODE_SWCTRL, | |
5377 | }, | |
5378 | }, | |
5379 | .mpu_irqs = omap44xx_usb_host_hs_irqs, | |
5380 | .slaves = omap44xx_usb_host_hs_slaves, | |
5381 | .slaves_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_slaves), | |
5382 | .masters = omap44xx_usb_host_hs_masters, | |
5383 | .masters_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_masters), | |
5384 | ||
5385 | /* | |
5386 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
5387 | * id: i660 | |
5388 | * | |
5389 | * Description: | |
5390 | * In the following configuration : | |
5391 | * - USBHOST module is set to smart-idle mode | |
5392 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
5393 | * happens when the system is going to a low power mode : all ports | |
5394 | * have been suspended, the master part of the USBHOST module has | |
5395 | * entered the standby state, and SW has cut the functional clocks) | |
5396 | * - an USBHOST interrupt occurs before the module is able to answer | |
5397 | * idle_ack, typically a remote wakeup IRQ. | |
5398 | * Then the USB HOST module will enter a deadlock situation where it | |
5399 | * is no more accessible nor functional. | |
5400 | * | |
5401 | * Workaround: | |
5402 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
5403 | */ | |
5404 | ||
5405 | /* | |
5406 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
5407 | * Id: i571 | |
5408 | * | |
5409 | * Description: | |
5410 | * When the USBHOST module is set to smart-standby mode, and when it is | |
5411 | * ready to enter the standby state (i.e. all ports are suspended and | |
5412 | * all attached devices are in suspend mode), then it can wrongly assert | |
5413 | * the Mstandby signal too early while there are still some residual OCP | |
5414 | * transactions ongoing. If this condition occurs, the internal state | |
5415 | * machine may go to an undefined state and the USB link may be stuck | |
5416 | * upon the next resume. | |
5417 | * | |
5418 | * Workaround: | |
5419 | * Don't use smart standby; use only force standby, | |
5420 | * hence HWMOD_SWSUP_MSTANDBY | |
5421 | */ | |
5422 | ||
5423 | /* | |
5424 | * During system boot; If the hwmod framework resets the module | |
5425 | * the module will have smart idle settings; which can lead to deadlock | |
5426 | * (above Errata Id:i660); so, dont reset the module during boot; | |
5427 | * Use HWMOD_INIT_NO_RESET. | |
5428 | */ | |
5429 | ||
5430 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | | |
5431 | HWMOD_INIT_NO_RESET, | |
5432 | }; | |
5433 | ||
5434 | /* | |
5435 | * 'usb_tll_hs' class | |
5436 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
5437 | */ | |
5438 | static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { | |
5439 | .rev_offs = 0x0000, | |
5440 | .sysc_offs = 0x0010, | |
5441 | .syss_offs = 0x0014, | |
5442 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
5443 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
5444 | SYSC_HAS_AUTOIDLE), | |
5445 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
5446 | .sysc_fields = &omap_hwmod_sysc_type1, | |
5447 | }; | |
5448 | ||
5449 | static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { | |
5450 | .name = "usb_tll_hs", | |
5451 | .sysc = &omap44xx_usb_tll_hs_sysc, | |
5452 | }; | |
5453 | ||
5454 | static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { | |
5455 | { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, | |
5456 | { .irq = -1 } | |
5457 | }; | |
5458 | ||
5459 | static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { | |
5460 | { | |
5461 | .name = "tll", | |
5462 | .pa_start = 0x4a062000, | |
5463 | .pa_end = 0x4a063fff, | |
5464 | .flags = ADDR_TYPE_RT | |
5465 | }, | |
5466 | {} | |
5467 | }; | |
5468 | ||
5469 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { | |
5470 | .master = &omap44xx_l4_cfg_hwmod, | |
5471 | .slave = &omap44xx_usb_tll_hs_hwmod, | |
5472 | .clk = "l4_div_ck", | |
5473 | .addr = omap44xx_usb_tll_hs_addrs, | |
5474 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5475 | }; | |
5476 | ||
5477 | static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = { | |
5478 | &omap44xx_l4_cfg__usb_tll_hs, | |
5479 | }; | |
5480 | ||
5481 | static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { | |
5482 | .name = "usb_tll_hs", | |
5483 | .class = &omap44xx_usb_tll_hs_hwmod_class, | |
5484 | .clkdm_name = "l3_init_clkdm", | |
5485 | .main_clk = "usb_tll_hs_ick", | |
5486 | .prcm = { | |
5487 | .omap4 = { | |
5488 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, | |
5489 | .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, | |
5490 | .modulemode = MODULEMODE_HWCTRL, | |
5491 | }, | |
5492 | }, | |
5493 | .mpu_irqs = omap44xx_usb_tll_hs_irqs, | |
5494 | .slaves = omap44xx_usb_tll_hs_slaves, | |
5495 | .slaves_cnt = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves), | |
5496 | }; | |
5497 | ||
55d2cb08 | 5498 | static __initdata struct omap_hwmod *omap44xx_hwmods[] = { |
fe13471c | 5499 | |
55d2cb08 BC |
5500 | /* dmm class */ |
5501 | &omap44xx_dmm_hwmod, | |
3b54baad | 5502 | |
55d2cb08 BC |
5503 | /* emif_fw class */ |
5504 | &omap44xx_emif_fw_hwmod, | |
3b54baad | 5505 | |
55d2cb08 BC |
5506 | /* l3 class */ |
5507 | &omap44xx_l3_instr_hwmod, | |
5508 | &omap44xx_l3_main_1_hwmod, | |
5509 | &omap44xx_l3_main_2_hwmod, | |
5510 | &omap44xx_l3_main_3_hwmod, | |
3b54baad | 5511 | |
55d2cb08 BC |
5512 | /* l4 class */ |
5513 | &omap44xx_l4_abe_hwmod, | |
5514 | &omap44xx_l4_cfg_hwmod, | |
5515 | &omap44xx_l4_per_hwmod, | |
5516 | &omap44xx_l4_wkup_hwmod, | |
531ce0d5 | 5517 | |
55d2cb08 BC |
5518 | /* mpu_bus class */ |
5519 | &omap44xx_mpu_private_hwmod, | |
5520 | ||
407a6888 BC |
5521 | /* aess class */ |
5522 | /* &omap44xx_aess_hwmod, */ | |
5523 | ||
5524 | /* bandgap class */ | |
5525 | &omap44xx_bandgap_hwmod, | |
5526 | ||
5527 | /* counter class */ | |
5528 | /* &omap44xx_counter_32k_hwmod, */ | |
5529 | ||
d7cf5f33 BC |
5530 | /* dma class */ |
5531 | &omap44xx_dma_system_hwmod, | |
5532 | ||
8ca476da BC |
5533 | /* dmic class */ |
5534 | &omap44xx_dmic_hwmod, | |
5535 | ||
8f25bdc5 BC |
5536 | /* dsp class */ |
5537 | &omap44xx_dsp_hwmod, | |
5538 | &omap44xx_dsp_c0_hwmod, | |
5539 | ||
d63bd74f BC |
5540 | /* dss class */ |
5541 | &omap44xx_dss_hwmod, | |
5542 | &omap44xx_dss_dispc_hwmod, | |
5543 | &omap44xx_dss_dsi1_hwmod, | |
5544 | &omap44xx_dss_dsi2_hwmod, | |
5545 | &omap44xx_dss_hdmi_hwmod, | |
5546 | &omap44xx_dss_rfbi_hwmod, | |
5547 | &omap44xx_dss_venc_hwmod, | |
5548 | ||
9780a9cf BC |
5549 | /* gpio class */ |
5550 | &omap44xx_gpio1_hwmod, | |
5551 | &omap44xx_gpio2_hwmod, | |
5552 | &omap44xx_gpio3_hwmod, | |
5553 | &omap44xx_gpio4_hwmod, | |
5554 | &omap44xx_gpio5_hwmod, | |
5555 | &omap44xx_gpio6_hwmod, | |
5556 | ||
407a6888 BC |
5557 | /* hsi class */ |
5558 | /* &omap44xx_hsi_hwmod, */ | |
5559 | ||
3b54baad BC |
5560 | /* i2c class */ |
5561 | &omap44xx_i2c1_hwmod, | |
5562 | &omap44xx_i2c2_hwmod, | |
5563 | &omap44xx_i2c3_hwmod, | |
5564 | &omap44xx_i2c4_hwmod, | |
5565 | ||
407a6888 BC |
5566 | /* ipu class */ |
5567 | &omap44xx_ipu_hwmod, | |
5568 | &omap44xx_ipu_c0_hwmod, | |
5569 | &omap44xx_ipu_c1_hwmod, | |
5570 | ||
5571 | /* iss class */ | |
5572 | /* &omap44xx_iss_hwmod, */ | |
5573 | ||
8f25bdc5 BC |
5574 | /* iva class */ |
5575 | &omap44xx_iva_hwmod, | |
5576 | &omap44xx_iva_seq0_hwmod, | |
5577 | &omap44xx_iva_seq1_hwmod, | |
5578 | ||
407a6888 | 5579 | /* kbd class */ |
4998b245 | 5580 | &omap44xx_kbd_hwmod, |
407a6888 | 5581 | |
ec5df927 BC |
5582 | /* mailbox class */ |
5583 | &omap44xx_mailbox_hwmod, | |
5584 | ||
4ddff493 BC |
5585 | /* mcbsp class */ |
5586 | &omap44xx_mcbsp1_hwmod, | |
5587 | &omap44xx_mcbsp2_hwmod, | |
5588 | &omap44xx_mcbsp3_hwmod, | |
5589 | &omap44xx_mcbsp4_hwmod, | |
5590 | ||
407a6888 | 5591 | /* mcpdm class */ |
d05e2ea8 | 5592 | &omap44xx_mcpdm_hwmod, |
407a6888 | 5593 | |
9bcbd7f0 BC |
5594 | /* mcspi class */ |
5595 | &omap44xx_mcspi1_hwmod, | |
5596 | &omap44xx_mcspi2_hwmod, | |
5597 | &omap44xx_mcspi3_hwmod, | |
5598 | &omap44xx_mcspi4_hwmod, | |
5599 | ||
407a6888 | 5600 | /* mmc class */ |
17203bda AG |
5601 | &omap44xx_mmc1_hwmod, |
5602 | &omap44xx_mmc2_hwmod, | |
5603 | &omap44xx_mmc3_hwmod, | |
5604 | &omap44xx_mmc4_hwmod, | |
5605 | &omap44xx_mmc5_hwmod, | |
407a6888 | 5606 | |
55d2cb08 BC |
5607 | /* mpu class */ |
5608 | &omap44xx_mpu_hwmod, | |
db12ba53 | 5609 | |
1f6a717f BC |
5610 | /* smartreflex class */ |
5611 | &omap44xx_smartreflex_core_hwmod, | |
5612 | &omap44xx_smartreflex_iva_hwmod, | |
5613 | &omap44xx_smartreflex_mpu_hwmod, | |
5614 | ||
d11c217f BC |
5615 | /* spinlock class */ |
5616 | &omap44xx_spinlock_hwmod, | |
5617 | ||
35d1a66a BC |
5618 | /* timer class */ |
5619 | &omap44xx_timer1_hwmod, | |
5620 | &omap44xx_timer2_hwmod, | |
5621 | &omap44xx_timer3_hwmod, | |
5622 | &omap44xx_timer4_hwmod, | |
5623 | &omap44xx_timer5_hwmod, | |
5624 | &omap44xx_timer6_hwmod, | |
5625 | &omap44xx_timer7_hwmod, | |
5626 | &omap44xx_timer8_hwmod, | |
5627 | &omap44xx_timer9_hwmod, | |
5628 | &omap44xx_timer10_hwmod, | |
5629 | &omap44xx_timer11_hwmod, | |
5630 | ||
db12ba53 BC |
5631 | /* uart class */ |
5632 | &omap44xx_uart1_hwmod, | |
5633 | &omap44xx_uart2_hwmod, | |
5634 | &omap44xx_uart3_hwmod, | |
5635 | &omap44xx_uart4_hwmod, | |
3b54baad | 5636 | |
af88fa9a BC |
5637 | /* usb host class */ |
5638 | &omap44xx_usb_host_hs_hwmod, | |
5639 | &omap44xx_usb_tll_hs_hwmod, | |
5640 | ||
5844c4ea BC |
5641 | /* usb_otg_hs class */ |
5642 | &omap44xx_usb_otg_hs_hwmod, | |
5643 | ||
3b54baad BC |
5644 | /* wd_timer class */ |
5645 | &omap44xx_wd_timer2_hwmod, | |
5646 | &omap44xx_wd_timer3_hwmod, | |
55d2cb08 BC |
5647 | NULL, |
5648 | }; | |
5649 | ||
5650 | int __init omap44xx_hwmod_init(void) | |
5651 | { | |
550c8092 | 5652 | return omap_hwmod_register(omap44xx_hwmods); |
55d2cb08 BC |
5653 | } |
5654 |