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OMAP4: hwmod data: Add mailbox
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_44xx_data.c
CommitLineData
55d2cb08
BC		 1/*
2 * Hardware modules present on the OMAP44xx chips
3 *
d63bd74f 4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
55d2cb08
BC		 5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/io.h>
22
23#include <plat/omap_hwmod.h>
24#include <plat/cpu.h>
9780a9cf 25#include <plat/gpio.h>
531ce0d5 26#include <plat/dma.h>
55d2cb08
BC		 27
28#include "omap_hwmod_common_data.h"
29
d198b514
PW		 30#include "cm1_44xx.h"
31#include "cm2_44xx.h"
32#include "prm44xx.h"
55d2cb08 33#include "prm-regbits-44xx.h"
ff2516fb 34#include "wd_timer.h"
55d2cb08
BC		 35
36/* Base offset for all OMAP4 interrupts external to MPUSS */
37#define OMAP44XX_IRQ_GIC_START 32
38
39/* Base offset for all OMAP4 dma requests */
40#define OMAP44XX_DMA_REQ_START 1
41
42/* Backward references (IPs with Bus Master capability) */
531ce0d5 43static struct omap_hwmod omap44xx_dma_system_hwmod;
55d2cb08 44static struct omap_hwmod omap44xx_dmm_hwmod;
8f25bdc5 45static struct omap_hwmod omap44xx_dsp_hwmod;
d63bd74f 46static struct omap_hwmod omap44xx_dss_hwmod;
55d2cb08 47static struct omap_hwmod omap44xx_emif_fw_hwmod;
8f25bdc5 48static struct omap_hwmod omap44xx_iva_hwmod;
55d2cb08
BC		 49static struct omap_hwmod omap44xx_l3_instr_hwmod;
50static struct omap_hwmod omap44xx_l3_main_1_hwmod;
51static struct omap_hwmod omap44xx_l3_main_2_hwmod;
52static struct omap_hwmod omap44xx_l3_main_3_hwmod;
53static struct omap_hwmod omap44xx_l4_abe_hwmod;
54static struct omap_hwmod omap44xx_l4_cfg_hwmod;
55static struct omap_hwmod omap44xx_l4_per_hwmod;
56static struct omap_hwmod omap44xx_l4_wkup_hwmod;
57static struct omap_hwmod omap44xx_mpu_hwmod;
58static struct omap_hwmod omap44xx_mpu_private_hwmod;
59
60/*
61 * Interconnects omap_hwmod structures
62 * hwmods that compose the global OMAP interconnect
63 */
64
65/*
66 * 'dmm' class
67 * instance(s): dmm
68 */
69static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
fe13471c 70 .name = "dmm",
55d2cb08
BC		 71};
72
73/* dmm interface data */
74/* l3_main_1 -> dmm */
75static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
76 .master = &omap44xx_l3_main_1_hwmod,
77 .slave = &omap44xx_dmm_hwmod,
78 .clk = "l3_div_ck",
659fa822
BC		 79 .user = OCP_USER_SDMA,
80};
81
82static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
83 {
84 .pa_start = 0x4e000000,
85 .pa_end = 0x4e0007ff,
86 .flags = ADDR_TYPE_RT
87 },
55d2cb08
BC		 88};
89
90/* mpu -> dmm */
91static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
92 .master = &omap44xx_mpu_hwmod,
93 .slave = &omap44xx_dmm_hwmod,
94 .clk = "l3_div_ck",
659fa822
BC		 95 .addr = omap44xx_dmm_addrs,
96 .addr_cnt = ARRAY_SIZE(omap44xx_dmm_addrs),
97 .user = OCP_USER_MPU,
55d2cb08
BC		 98};
99
100/* dmm slave ports */
101static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
102 &omap44xx_l3_main_1__dmm,
103 &omap44xx_mpu__dmm,
104};
105
106static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
107 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
108};
109
110static struct omap_hwmod omap44xx_dmm_hwmod = {
111 .name = "dmm",
112 .class = &omap44xx_dmm_hwmod_class,
113 .slaves = omap44xx_dmm_slaves,
114 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
115 .mpu_irqs = omap44xx_dmm_irqs,
116 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs),
117 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
118};
119
120/*
121 * 'emif_fw' class
122 * instance(s): emif_fw
123 */
124static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
fe13471c 125 .name = "emif_fw",
55d2cb08
BC		 126};
127
128/* emif_fw interface data */
129/* dmm -> emif_fw */
130static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
131 .master = &omap44xx_dmm_hwmod,
132 .slave = &omap44xx_emif_fw_hwmod,
133 .clk = "l3_div_ck",
134 .user = OCP_USER_MPU | OCP_USER_SDMA,
135};
136
659fa822
BC		 137static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
138 {
139 .pa_start = 0x4a20c000,
140 .pa_end = 0x4a20c0ff,
141 .flags = ADDR_TYPE_RT
142 },
143};
144
55d2cb08
BC		 145/* l4_cfg -> emif_fw */
146static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
147 .master = &omap44xx_l4_cfg_hwmod,
148 .slave = &omap44xx_emif_fw_hwmod,
149 .clk = "l4_div_ck",
659fa822
BC		 150 .addr = omap44xx_emif_fw_addrs,
151 .addr_cnt = ARRAY_SIZE(omap44xx_emif_fw_addrs),
152 .user = OCP_USER_MPU,
55d2cb08
BC		 153};
154
155/* emif_fw slave ports */
156static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
157 &omap44xx_dmm__emif_fw,
158 &omap44xx_l4_cfg__emif_fw,
159};
160
161static struct omap_hwmod omap44xx_emif_fw_hwmod = {
162 .name = "emif_fw",
163 .class = &omap44xx_emif_fw_hwmod_class,
164 .slaves = omap44xx_emif_fw_slaves,
165 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
166 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
167};
168
169/*
170 * 'l3' class
171 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
172 */
173static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
fe13471c 174 .name = "l3",
55d2cb08
BC		 175};
176
177/* l3_instr interface data */
8f25bdc5
BC		 178/* iva -> l3_instr */
179static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
180 .master = &omap44xx_iva_hwmod,
181 .slave = &omap44xx_l3_instr_hwmod,
182 .clk = "l3_div_ck",
183 .user = OCP_USER_MPU | OCP_USER_SDMA,
184};
185
55d2cb08
BC		 186/* l3_main_3 -> l3_instr */
187static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
188 .master = &omap44xx_l3_main_3_hwmod,
189 .slave = &omap44xx_l3_instr_hwmod,
190 .clk = "l3_div_ck",
191 .user = OCP_USER_MPU | OCP_USER_SDMA,
192};
193
194/* l3_instr slave ports */
195static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
8f25bdc5 196 &omap44xx_iva__l3_instr,
55d2cb08
BC		 197 &omap44xx_l3_main_3__l3_instr,
198};
199
200static struct omap_hwmod omap44xx_l3_instr_hwmod = {
201 .name = "l3_instr",
202 .class = &omap44xx_l3_hwmod_class,
203 .slaves = omap44xx_l3_instr_slaves,
204 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
205 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
206};
207
3b54baad 208/* l3_main_1 interface data */
8f25bdc5
BC		 209/* dsp -> l3_main_1 */
210static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
211 .master = &omap44xx_dsp_hwmod,
212 .slave = &omap44xx_l3_main_1_hwmod,
213 .clk = "l3_div_ck",
214 .user = OCP_USER_MPU | OCP_USER_SDMA,
215};
216
d63bd74f
BC		 217/* dss -> l3_main_1 */
218static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
219 .master = &omap44xx_dss_hwmod,
220 .slave = &omap44xx_l3_main_1_hwmod,
221 .clk = "l3_div_ck",
222 .user = OCP_USER_MPU | OCP_USER_SDMA,
223};
224
55d2cb08
BC		 225/* l3_main_2 -> l3_main_1 */
226static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
227 .master = &omap44xx_l3_main_2_hwmod,
228 .slave = &omap44xx_l3_main_1_hwmod,
229 .clk = "l3_div_ck",
230 .user = OCP_USER_MPU | OCP_USER_SDMA,
231};
232
233/* l4_cfg -> l3_main_1 */
234static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
235 .master = &omap44xx_l4_cfg_hwmod,
236 .slave = &omap44xx_l3_main_1_hwmod,
237 .clk = "l4_div_ck",
238 .user = OCP_USER_MPU | OCP_USER_SDMA,
239};
240
241/* mpu -> l3_main_1 */
242static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
243 .master = &omap44xx_mpu_hwmod,
244 .slave = &omap44xx_l3_main_1_hwmod,
245 .clk = "l3_div_ck",
246 .user = OCP_USER_MPU | OCP_USER_SDMA,
247};
248
249/* l3_main_1 slave ports */
250static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
8f25bdc5 251 &omap44xx_dsp__l3_main_1,
d63bd74f 252 &omap44xx_dss__l3_main_1,
55d2cb08
BC		 253 &omap44xx_l3_main_2__l3_main_1,
254 &omap44xx_l4_cfg__l3_main_1,
255 &omap44xx_mpu__l3_main_1,
256};
257
258static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
259 .name = "l3_main_1",
260 .class = &omap44xx_l3_hwmod_class,
261 .slaves = omap44xx_l3_main_1_slaves,
262 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
263 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
264};
265
266/* l3_main_2 interface data */
d7cf5f33
BC		 267/* dma_system -> l3_main_2 */
268static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
269 .master = &omap44xx_dma_system_hwmod,
270 .slave = &omap44xx_l3_main_2_hwmod,
271 .clk = "l3_div_ck",
272 .user = OCP_USER_MPU | OCP_USER_SDMA,
273};
274
8f25bdc5
BC		 275/* iva -> l3_main_2 */
276static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
277 .master = &omap44xx_iva_hwmod,
278 .slave = &omap44xx_l3_main_2_hwmod,
279 .clk = "l3_div_ck",
280 .user = OCP_USER_MPU | OCP_USER_SDMA,
281};
282
55d2cb08
BC		 283/* l3_main_1 -> l3_main_2 */
284static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
285 .master = &omap44xx_l3_main_1_hwmod,
286 .slave = &omap44xx_l3_main_2_hwmod,
287 .clk = "l3_div_ck",
288 .user = OCP_USER_MPU | OCP_USER_SDMA,
289};
290
291/* l4_cfg -> l3_main_2 */
292static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
293 .master = &omap44xx_l4_cfg_hwmod,
294 .slave = &omap44xx_l3_main_2_hwmod,
295 .clk = "l4_div_ck",
296 .user = OCP_USER_MPU | OCP_USER_SDMA,
297};
298
299/* l3_main_2 slave ports */
300static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
531ce0d5 301 &omap44xx_dma_system__l3_main_2,
8f25bdc5 302 &omap44xx_iva__l3_main_2,
55d2cb08
BC		 303 &omap44xx_l3_main_1__l3_main_2,
304 &omap44xx_l4_cfg__l3_main_2,
305};
306
307static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
308 .name = "l3_main_2",
309 .class = &omap44xx_l3_hwmod_class,
310 .slaves = omap44xx_l3_main_2_slaves,
311 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
312 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
313};
314
315/* l3_main_3 interface data */
316/* l3_main_1 -> l3_main_3 */
317static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
318 .master = &omap44xx_l3_main_1_hwmod,
319 .slave = &omap44xx_l3_main_3_hwmod,
320 .clk = "l3_div_ck",
321 .user = OCP_USER_MPU | OCP_USER_SDMA,
322};
323
324/* l3_main_2 -> l3_main_3 */
325static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
326 .master = &omap44xx_l3_main_2_hwmod,
327 .slave = &omap44xx_l3_main_3_hwmod,
328 .clk = "l3_div_ck",
329 .user = OCP_USER_MPU | OCP_USER_SDMA,
330};
331
332/* l4_cfg -> l3_main_3 */
333static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
334 .master = &omap44xx_l4_cfg_hwmod,
335 .slave = &omap44xx_l3_main_3_hwmod,
336 .clk = "l4_div_ck",
337 .user = OCP_USER_MPU | OCP_USER_SDMA,
338};
339
340/* l3_main_3 slave ports */
341static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
342 &omap44xx_l3_main_1__l3_main_3,
343 &omap44xx_l3_main_2__l3_main_3,
344 &omap44xx_l4_cfg__l3_main_3,
345};
346
347static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
348 .name = "l3_main_3",
349 .class = &omap44xx_l3_hwmod_class,
350 .slaves = omap44xx_l3_main_3_slaves,
351 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
352 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
353};
354
355/*
356 * 'l4' class
357 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
358 */
359static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
fe13471c 360 .name = "l4",
55d2cb08
BC		 361};
362
363/* l4_abe interface data */
8f25bdc5
BC		 364/* dsp -> l4_abe */
365static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
366 .master = &omap44xx_dsp_hwmod,
367 .slave = &omap44xx_l4_abe_hwmod,
368 .clk = "ocp_abe_iclk",
369 .user = OCP_USER_MPU | OCP_USER_SDMA,
370};
371
55d2cb08
BC		 372/* l3_main_1 -> l4_abe */
373static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
374 .master = &omap44xx_l3_main_1_hwmod,
375 .slave = &omap44xx_l4_abe_hwmod,
376 .clk = "l3_div_ck",
377 .user = OCP_USER_MPU | OCP_USER_SDMA,
378};
379
380/* mpu -> l4_abe */
381static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
382 .master = &omap44xx_mpu_hwmod,
383 .slave = &omap44xx_l4_abe_hwmod,
384 .clk = "ocp_abe_iclk",
385 .user = OCP_USER_MPU | OCP_USER_SDMA,
386};
387
388/* l4_abe slave ports */
389static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
8f25bdc5 390 &omap44xx_dsp__l4_abe,
55d2cb08
BC		 391 &omap44xx_l3_main_1__l4_abe,
392 &omap44xx_mpu__l4_abe,
393};
394
395static struct omap_hwmod omap44xx_l4_abe_hwmod = {
396 .name = "l4_abe",
397 .class = &omap44xx_l4_hwmod_class,
398 .slaves = omap44xx_l4_abe_slaves,
399 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
400 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
401};
402
403/* l4_cfg interface data */
404/* l3_main_1 -> l4_cfg */
405static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
406 .master = &omap44xx_l3_main_1_hwmod,
407 .slave = &omap44xx_l4_cfg_hwmod,
408 .clk = "l3_div_ck",
409 .user = OCP_USER_MPU | OCP_USER_SDMA,
410};
411
412/* l4_cfg slave ports */
413static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
414 &omap44xx_l3_main_1__l4_cfg,
415};
416
417static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
418 .name = "l4_cfg",
419 .class = &omap44xx_l4_hwmod_class,
420 .slaves = omap44xx_l4_cfg_slaves,
421 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
422 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
423};
424
425/* l4_per interface data */
426/* l3_main_2 -> l4_per */
427static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
428 .master = &omap44xx_l3_main_2_hwmod,
429 .slave = &omap44xx_l4_per_hwmod,
430 .clk = "l3_div_ck",
431 .user = OCP_USER_MPU | OCP_USER_SDMA,
432};
433
434/* l4_per slave ports */
435static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
436 &omap44xx_l3_main_2__l4_per,
437};
438
439static struct omap_hwmod omap44xx_l4_per_hwmod = {
440 .name = "l4_per",
441 .class = &omap44xx_l4_hwmod_class,
442 .slaves = omap44xx_l4_per_slaves,
443 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
444 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
445};
446
447/* l4_wkup interface data */
448/* l4_cfg -> l4_wkup */
449static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
450 .master = &omap44xx_l4_cfg_hwmod,
451 .slave = &omap44xx_l4_wkup_hwmod,
452 .clk = "l4_div_ck",
453 .user = OCP_USER_MPU | OCP_USER_SDMA,
454};
455
456/* l4_wkup slave ports */
457static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
458 &omap44xx_l4_cfg__l4_wkup,
459};
460
461static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
462 .name = "l4_wkup",
463 .class = &omap44xx_l4_hwmod_class,
464 .slaves = omap44xx_l4_wkup_slaves,
465 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
466 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
467};
468
f776471f 469/*
3b54baad
BC		 470 * 'mpu_bus' class
471 * instance(s): mpu_private
f776471f 472 */
3b54baad 473static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
fe13471c 474 .name = "mpu_bus",
3b54baad 475};
f776471f 476
3b54baad
BC		 477/* mpu_private interface data */
478/* mpu -> mpu_private */
479static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
480 .master = &omap44xx_mpu_hwmod,
481 .slave = &omap44xx_mpu_private_hwmod,
482 .clk = "l3_div_ck",
483 .user = OCP_USER_MPU | OCP_USER_SDMA,
484};
485
486/* mpu_private slave ports */
487static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
488 &omap44xx_mpu__mpu_private,
489};
490
491static struct omap_hwmod omap44xx_mpu_private_hwmod = {
492 .name = "mpu_private",
493 .class = &omap44xx_mpu_bus_hwmod_class,
494 .slaves = omap44xx_mpu_private_slaves,
495 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
496 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
497};
498
499/*
500 * Modules omap_hwmod structures
501 *
502 * The following IPs are excluded for the moment because:
503 * - They do not need an explicit SW control using omap_hwmod API.
504 * - They still need to be validated with the driver
505 * properly adapted to omap_hwmod / omap_device
506 *
507 * aess
508 * bandgap
509 * c2c
510 * c2c_target_fw
511 * cm_core
512 * cm_core_aon
513 * counter_32k
514 * ctrl_module_core
515 * ctrl_module_pad_core
516 * ctrl_module_pad_wkup
517 * ctrl_module_wkup
518 * debugss
3b54baad 519 * dmic
3b54baad
BC		 520 * efuse_ctrl_cust
521 * efuse_ctrl_std
522 * elm
523 * emif1
524 * emif2
525 * fdif
526 * gpmc
527 * gpu
528 * hdq1w
529 * hsi
530 * ipu
531 * iss
3b54baad 532 * kbd
3b54baad
BC		 533 * mcasp
534 * mcbsp1
535 * mcbsp2
536 * mcbsp3
537 * mcbsp4
538 * mcpdm
3b54baad
BC		 539 * mmc1
540 * mmc2
541 * mmc3
542 * mmc4
543 * mmc5
544 * mpu_c0
545 * mpu_c1
546 * ocmc_ram
547 * ocp2scp_usb_phy
548 * ocp_wp_noc
549 * prcm
550 * prcm_mpu
551 * prm
552 * scrm
553 * sl2if
554 * slimbus1
555 * slimbus2
3b54baad
BC		 556 * usb_host_fs
557 * usb_host_hs
558 * usb_otg_hs
559 * usb_phy_cm
560 * usb_tll_hs
561 * usim
562 */
563
d7cf5f33
BC		 564/*
565 * 'dma' class
566 * dma controller for data exchange between memory to memory (i.e. internal or
567 * external memory) and gp peripherals to memory or memory to gp peripherals
568 */
569
570static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
571 .rev_offs = 0x0000,
572 .sysc_offs = 0x002c,
573 .syss_offs = 0x0028,
574 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
575 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
576 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
577 SYSS_HAS_RESET_STATUS),
578 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
579 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
580 .sysc_fields = &omap_hwmod_sysc_type1,
581};
582
583static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
584 .name = "dma",
585 .sysc = &omap44xx_dma_sysc,
586};
587
588/* dma dev_attr */
589static struct omap_dma_dev_attr dma_dev_attr = {
590 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
591 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
592 .lch_count = 32,
593};
594
595/* dma_system */
596static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
597 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
598 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
599 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
600 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
601};
602
603/* dma_system master ports */
604static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
605 &omap44xx_dma_system__l3_main_2,
606};
607
608static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
609 {
610 .pa_start = 0x4a056000,
611 .pa_end = 0x4a0560ff,
612 .flags = ADDR_TYPE_RT
613 },
614};
615
616/* l4_cfg -> dma_system */
617static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
618 .master = &omap44xx_l4_cfg_hwmod,
619 .slave = &omap44xx_dma_system_hwmod,
620 .clk = "l4_div_ck",
621 .addr = omap44xx_dma_system_addrs,
622 .addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs),
623 .user = OCP_USER_MPU | OCP_USER_SDMA,
624};
625
626/* dma_system slave ports */
627static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
628 &omap44xx_l4_cfg__dma_system,
629};
630
631static struct omap_hwmod omap44xx_dma_system_hwmod = {
632 .name = "dma_system",
633 .class = &omap44xx_dma_hwmod_class,
634 .mpu_irqs = omap44xx_dma_system_irqs,
635 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs),
636 .main_clk = "l3_div_ck",
637 .prcm = {
638 .omap4 = {
639 .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
640 },
641 },
642 .dev_attr = &dma_dev_attr,
643 .slaves = omap44xx_dma_system_slaves,
644 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
645 .masters = omap44xx_dma_system_masters,
646 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
647 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
648};
649
8f25bdc5
BC		 650/*
651 * 'dsp' class
652 * dsp sub-system
653 */
654
655static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
fe13471c 656 .name = "dsp",
8f25bdc5
BC		 657};
658
659/* dsp */
660static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
661 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
662};
663
664static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
665 { .name = "mmu_cache", .rst_shift = 1 },
666};
667
668static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
669 { .name = "dsp", .rst_shift = 0 },
670};
671
672/* dsp -> iva */
673static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
674 .master = &omap44xx_dsp_hwmod,
675 .slave = &omap44xx_iva_hwmod,
676 .clk = "dpll_iva_m5x2_ck",
677};
678
679/* dsp master ports */
680static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
681 &omap44xx_dsp__l3_main_1,
682 &omap44xx_dsp__l4_abe,
683 &omap44xx_dsp__iva,
684};
685
686/* l4_cfg -> dsp */
687static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
688 .master = &omap44xx_l4_cfg_hwmod,
689 .slave = &omap44xx_dsp_hwmod,
690 .clk = "l4_div_ck",
691 .user = OCP_USER_MPU | OCP_USER_SDMA,
692};
693
694/* dsp slave ports */
695static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
696 &omap44xx_l4_cfg__dsp,
697};
698
699/* Pseudo hwmod for reset control purpose only */
700static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
701 .name = "dsp_c0",
702 .class = &omap44xx_dsp_hwmod_class,
703 .flags = HWMOD_INIT_NO_RESET,
704 .rst_lines = omap44xx_dsp_c0_resets,
705 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
706 .prcm = {
707 .omap4 = {
708 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
709 },
710 },
711 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
712};
713
714static struct omap_hwmod omap44xx_dsp_hwmod = {
715 .name = "dsp",
716 .class = &omap44xx_dsp_hwmod_class,
717 .mpu_irqs = omap44xx_dsp_irqs,
718 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dsp_irqs),
719 .rst_lines = omap44xx_dsp_resets,
720 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
721 .main_clk = "dsp_fck",
722 .prcm = {
723 .omap4 = {
724 .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
725 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
726 },
727 },
728 .slaves = omap44xx_dsp_slaves,
729 .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
730 .masters = omap44xx_dsp_masters,
731 .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
732 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
733};
734
d63bd74f
BC		 735/*
736 * 'dss' class
737 * display sub-system
738 */
739
740static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
741 .rev_offs = 0x0000,
742 .syss_offs = 0x0014,
743 .sysc_flags = SYSS_HAS_RESET_STATUS,
744};
745
746static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
747 .name = "dss",
748 .sysc = &omap44xx_dss_sysc,
749};
750
751/* dss */
752/* dss master ports */
753static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
754 &omap44xx_dss__l3_main_1,
755};
756
757static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
758 {
759 .pa_start = 0x58000000,
760 .pa_end = 0x5800007f,
761 .flags = ADDR_TYPE_RT
762 },
763};
764
765/* l3_main_2 -> dss */
766static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
767 .master = &omap44xx_l3_main_2_hwmod,
768 .slave = &omap44xx_dss_hwmod,
769 .clk = "l3_div_ck",
770 .addr = omap44xx_dss_dma_addrs,
771 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dma_addrs),
772 .user = OCP_USER_SDMA,
773};
774
775static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
776 {
777 .pa_start = 0x48040000,
778 .pa_end = 0x4804007f,
779 .flags = ADDR_TYPE_RT
780 },
781};
782
783/* l4_per -> dss */
784static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
785 .master = &omap44xx_l4_per_hwmod,
786 .slave = &omap44xx_dss_hwmod,
787 .clk = "l4_div_ck",
788 .addr = omap44xx_dss_addrs,
789 .addr_cnt = ARRAY_SIZE(omap44xx_dss_addrs),
790 .user = OCP_USER_MPU,
791};
792
793/* dss slave ports */
794static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
795 &omap44xx_l3_main_2__dss,
796 &omap44xx_l4_per__dss,
797};
798
799static struct omap_hwmod_opt_clk dss_opt_clks[] = {
800 { .role = "sys_clk", .clk = "dss_sys_clk" },
801 { .role = "tv_clk", .clk = "dss_tv_clk" },
802 { .role = "dss_clk", .clk = "dss_dss_clk" },
803 { .role = "video_clk", .clk = "dss_48mhz_clk" },
804};
805
806static struct omap_hwmod omap44xx_dss_hwmod = {
807 .name = "dss_core",
808 .class = &omap44xx_dss_hwmod_class,
809 .main_clk = "dss_fck",
810 .prcm = {
811 .omap4 = {
812 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
813 },
814 },
815 .opt_clks = dss_opt_clks,
816 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
817 .slaves = omap44xx_dss_slaves,
818 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
819 .masters = omap44xx_dss_masters,
820 .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
821 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
822};
823
824/*
825 * 'dispc' class
826 * display controller
827 */
828
829static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
830 .rev_offs = 0x0000,
831 .sysc_offs = 0x0010,
832 .syss_offs = 0x0014,
833 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
834 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
835 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
836 SYSS_HAS_RESET_STATUS),
837 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
838 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
839 .sysc_fields = &omap_hwmod_sysc_type1,
840};
841
842static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
843 .name = "dispc",
844 .sysc = &omap44xx_dispc_sysc,
845};
846
847/* dss_dispc */
848static struct omap_hwmod omap44xx_dss_dispc_hwmod;
849static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
850 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
851};
852
853static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
854 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
855};
856
857static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
858 {
859 .pa_start = 0x58001000,
860 .pa_end = 0x58001fff,
861 .flags = ADDR_TYPE_RT
862 },
863};
864
865/* l3_main_2 -> dss_dispc */
866static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
867 .master = &omap44xx_l3_main_2_hwmod,
868 .slave = &omap44xx_dss_dispc_hwmod,
869 .clk = "l3_div_ck",
870 .addr = omap44xx_dss_dispc_dma_addrs,
871 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs),
872 .user = OCP_USER_SDMA,
873};
874
875static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
876 {
877 .pa_start = 0x48041000,
878 .pa_end = 0x48041fff,
879 .flags = ADDR_TYPE_RT
880 },
881};
882
883/* l4_per -> dss_dispc */
884static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
885 .master = &omap44xx_l4_per_hwmod,
886 .slave = &omap44xx_dss_dispc_hwmod,
887 .clk = "l4_div_ck",
888 .addr = omap44xx_dss_dispc_addrs,
889 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
890 .user = OCP_USER_MPU,
891};
892
893/* dss_dispc slave ports */
894static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
895 &omap44xx_l3_main_2__dss_dispc,
896 &omap44xx_l4_per__dss_dispc,
897};
898
899static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
900 .name = "dss_dispc",
901 .class = &omap44xx_dispc_hwmod_class,
902 .mpu_irqs = omap44xx_dss_dispc_irqs,
903 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_irqs),
904 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
905 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
906 .main_clk = "dss_fck",
907 .prcm = {
908 .omap4 = {
909 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
910 },
911 },
912 .slaves = omap44xx_dss_dispc_slaves,
913 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
914 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
915};
916
917/*
918 * 'dsi' class
919 * display serial interface controller
920 */
921
922static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
923 .rev_offs = 0x0000,
924 .sysc_offs = 0x0010,
925 .syss_offs = 0x0014,
926 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
927 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
928 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
929 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
930 .sysc_fields = &omap_hwmod_sysc_type1,
931};
932
933static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
934 .name = "dsi",
935 .sysc = &omap44xx_dsi_sysc,
936};
937
938/* dss_dsi1 */
939static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
940static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
941 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
942};
943
944static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
945 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
946};
947
948static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
949 {
950 .pa_start = 0x58004000,
951 .pa_end = 0x580041ff,
952 .flags = ADDR_TYPE_RT
953 },
954};
955
956/* l3_main_2 -> dss_dsi1 */
957static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
958 .master = &omap44xx_l3_main_2_hwmod,
959 .slave = &omap44xx_dss_dsi1_hwmod,
960 .clk = "l3_div_ck",
961 .addr = omap44xx_dss_dsi1_dma_addrs,
962 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs),
963 .user = OCP_USER_SDMA,
964};
965
966static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
967 {
968 .pa_start = 0x48044000,
969 .pa_end = 0x480441ff,
970 .flags = ADDR_TYPE_RT
971 },
972};
973
974/* l4_per -> dss_dsi1 */
975static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
976 .master = &omap44xx_l4_per_hwmod,
977 .slave = &omap44xx_dss_dsi1_hwmod,
978 .clk = "l4_div_ck",
979 .addr = omap44xx_dss_dsi1_addrs,
980 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
981 .user = OCP_USER_MPU,
982};
983
984/* dss_dsi1 slave ports */
985static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
986 &omap44xx_l3_main_2__dss_dsi1,
987 &omap44xx_l4_per__dss_dsi1,
988};
989
990static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
991 .name = "dss_dsi1",
992 .class = &omap44xx_dsi_hwmod_class,
993 .mpu_irqs = omap44xx_dss_dsi1_irqs,
994 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
995 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
996 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
997 .main_clk = "dss_fck",
998 .prcm = {
999 .omap4 = {
1000 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1001 },
1002 },
1003 .slaves = omap44xx_dss_dsi1_slaves,
1004 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1005 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1006};
1007
1008/* dss_dsi2 */
1009static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1010static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1011 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1012};
1013
1014static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1015 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1016};
1017
1018static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1019 {
1020 .pa_start = 0x58005000,
1021 .pa_end = 0x580051ff,
1022 .flags = ADDR_TYPE_RT
1023 },
1024};
1025
1026/* l3_main_2 -> dss_dsi2 */
1027static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1028 .master = &omap44xx_l3_main_2_hwmod,
1029 .slave = &omap44xx_dss_dsi2_hwmod,
1030 .clk = "l3_div_ck",
1031 .addr = omap44xx_dss_dsi2_dma_addrs,
1032 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs),
1033 .user = OCP_USER_SDMA,
1034};
1035
1036static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1037 {
1038 .pa_start = 0x48045000,
1039 .pa_end = 0x480451ff,
1040 .flags = ADDR_TYPE_RT
1041 },
1042};
1043
1044/* l4_per -> dss_dsi2 */
1045static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1046 .master = &omap44xx_l4_per_hwmod,
1047 .slave = &omap44xx_dss_dsi2_hwmod,
1048 .clk = "l4_div_ck",
1049 .addr = omap44xx_dss_dsi2_addrs,
1050 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
1051 .user = OCP_USER_MPU,
1052};
1053
1054/* dss_dsi2 slave ports */
1055static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1056 &omap44xx_l3_main_2__dss_dsi2,
1057 &omap44xx_l4_per__dss_dsi2,
1058};
1059
1060static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1061 .name = "dss_dsi2",
1062 .class = &omap44xx_dsi_hwmod_class,
1063 .mpu_irqs = omap44xx_dss_dsi2_irqs,
1064 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
1065 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
1066 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
1067 .main_clk = "dss_fck",
1068 .prcm = {
1069 .omap4 = {
1070 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1071 },
1072 },
1073 .slaves = omap44xx_dss_dsi2_slaves,
1074 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1075 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1076};
1077
1078/*
1079 * 'hdmi' class
1080 * hdmi controller
1081 */
1082
1083static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1084 .rev_offs = 0x0000,
1085 .sysc_offs = 0x0010,
1086 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1087 SYSC_HAS_SOFTRESET),
1088 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1089 SIDLE_SMART_WKUP),
1090 .sysc_fields = &omap_hwmod_sysc_type2,
1091};
1092
1093static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1094 .name = "hdmi",
1095 .sysc = &omap44xx_hdmi_sysc,
1096};
1097
1098/* dss_hdmi */
1099static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1100static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1101 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1102};
1103
1104static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1105 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1106};
1107
1108static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1109 {
1110 .pa_start = 0x58006000,
1111 .pa_end = 0x58006fff,
1112 .flags = ADDR_TYPE_RT
1113 },
1114};
1115
1116/* l3_main_2 -> dss_hdmi */
1117static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1118 .master = &omap44xx_l3_main_2_hwmod,
1119 .slave = &omap44xx_dss_hdmi_hwmod,
1120 .clk = "l3_div_ck",
1121 .addr = omap44xx_dss_hdmi_dma_addrs,
1122 .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
1123 .user = OCP_USER_SDMA,
1124};
1125
1126static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1127 {
1128 .pa_start = 0x48046000,
1129 .pa_end = 0x48046fff,
1130 .flags = ADDR_TYPE_RT
1131 },
1132};
1133
1134/* l4_per -> dss_hdmi */
1135static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1136 .master = &omap44xx_l4_per_hwmod,
1137 .slave = &omap44xx_dss_hdmi_hwmod,
1138 .clk = "l4_div_ck",
1139 .addr = omap44xx_dss_hdmi_addrs,
1140 .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_addrs),
1141 .user = OCP_USER_MPU,
1142};
1143
1144/* dss_hdmi slave ports */
1145static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1146 &omap44xx_l3_main_2__dss_hdmi,
1147 &omap44xx_l4_per__dss_hdmi,
1148};
1149
1150static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1151 .name = "dss_hdmi",
1152 .class = &omap44xx_hdmi_hwmod_class,
1153 .mpu_irqs = omap44xx_dss_hdmi_irqs,
1154 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
1155 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
1156 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
1157 .main_clk = "dss_fck",
1158 .prcm = {
1159 .omap4 = {
1160 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1161 },
1162 },
1163 .slaves = omap44xx_dss_hdmi_slaves,
1164 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1165 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1166};
1167
1168/*
1169 * 'rfbi' class
1170 * remote frame buffer interface
1171 */
1172
1173static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1174 .rev_offs = 0x0000,
1175 .sysc_offs = 0x0010,
1176 .syss_offs = 0x0014,
1177 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1178 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1179 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1180 .sysc_fields = &omap_hwmod_sysc_type1,
1181};
1182
1183static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1184 .name = "rfbi",
1185 .sysc = &omap44xx_rfbi_sysc,
1186};
1187
1188/* dss_rfbi */
1189static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1190static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1191 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1192};
1193
1194static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1195 {
1196 .pa_start = 0x58002000,
1197 .pa_end = 0x580020ff,
1198 .flags = ADDR_TYPE_RT
1199 },
1200};
1201
1202/* l3_main_2 -> dss_rfbi */
1203static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1204 .master = &omap44xx_l3_main_2_hwmod,
1205 .slave = &omap44xx_dss_rfbi_hwmod,
1206 .clk = "l3_div_ck",
1207 .addr = omap44xx_dss_rfbi_dma_addrs,
1208 .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs),
1209 .user = OCP_USER_SDMA,
1210};
1211
1212static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1213 {
1214 .pa_start = 0x48042000,
1215 .pa_end = 0x480420ff,
1216 .flags = ADDR_TYPE_RT
1217 },
1218};
1219
1220/* l4_per -> dss_rfbi */
1221static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1222 .master = &omap44xx_l4_per_hwmod,
1223 .slave = &omap44xx_dss_rfbi_hwmod,
1224 .clk = "l4_div_ck",
1225 .addr = omap44xx_dss_rfbi_addrs,
1226 .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
1227 .user = OCP_USER_MPU,
1228};
1229
1230/* dss_rfbi slave ports */
1231static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1232 &omap44xx_l3_main_2__dss_rfbi,
1233 &omap44xx_l4_per__dss_rfbi,
1234};
1235
1236static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1237 .name = "dss_rfbi",
1238 .class = &omap44xx_rfbi_hwmod_class,
1239 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
1240 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs),
1241 .main_clk = "dss_fck",
1242 .prcm = {
1243 .omap4 = {
1244 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1245 },
1246 },
1247 .slaves = omap44xx_dss_rfbi_slaves,
1248 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1249 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1250};
1251
1252/*
1253 * 'venc' class
1254 * video encoder
1255 */
1256
1257static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1258 .name = "venc",
1259};
1260
1261/* dss_venc */
1262static struct omap_hwmod omap44xx_dss_venc_hwmod;
1263static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1264 {
1265 .pa_start = 0x58003000,
1266 .pa_end = 0x580030ff,
1267 .flags = ADDR_TYPE_RT
1268 },
1269};
1270
1271/* l3_main_2 -> dss_venc */
1272static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1273 .master = &omap44xx_l3_main_2_hwmod,
1274 .slave = &omap44xx_dss_venc_hwmod,
1275 .clk = "l3_div_ck",
1276 .addr = omap44xx_dss_venc_dma_addrs,
1277 .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs),
1278 .user = OCP_USER_SDMA,
1279};
1280
1281static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1282 {
1283 .pa_start = 0x48043000,
1284 .pa_end = 0x480430ff,
1285 .flags = ADDR_TYPE_RT
1286 },
1287};
1288
1289/* l4_per -> dss_venc */
1290static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1291 .master = &omap44xx_l4_per_hwmod,
1292 .slave = &omap44xx_dss_venc_hwmod,
1293 .clk = "l4_div_ck",
1294 .addr = omap44xx_dss_venc_addrs,
1295 .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_addrs),
1296 .user = OCP_USER_MPU,
1297};
1298
1299/* dss_venc slave ports */
1300static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1301 &omap44xx_l3_main_2__dss_venc,
1302 &omap44xx_l4_per__dss_venc,
1303};
1304
1305static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1306 .name = "dss_venc",
1307 .class = &omap44xx_venc_hwmod_class,
1308 .main_clk = "dss_fck",
1309 .prcm = {
1310 .omap4 = {
1311 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1312 },
1313 },
1314 .slaves = omap44xx_dss_venc_slaves,
1315 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1316 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1317};
1318
3b54baad
BC		 1319/*
1320 * 'gpio' class
1321 * general purpose io module
1322 */
1323
1324static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1325 .rev_offs = 0x0000,
f776471f 1326 .sysc_offs = 0x0010,
3b54baad 1327 .syss_offs = 0x0114,
0cfe8751
BC		 1328 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1329 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1330 SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 1331 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1332 SIDLE_SMART_WKUP),
f776471f
BC		 1333 .sysc_fields = &omap_hwmod_sysc_type1,
1334};
1335
3b54baad 1336static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
fe13471c
BC		 1337 .name = "gpio",
1338 .sysc = &omap44xx_gpio_sysc,
1339 .rev = 2,
f776471f
BC		 1340};
1341
3b54baad
BC		 1342/* gpio dev_attr */
1343static struct omap_gpio_dev_attr gpio_dev_attr = {
fe13471c
BC		 1344 .bank_width = 32,
1345 .dbck_flag = true,
f776471f
BC		 1346};
1347
3b54baad
BC		 1348/* gpio1 */
1349static struct omap_hwmod omap44xx_gpio1_hwmod;
1350static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1351 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
f776471f
BC		 1352};
1353
3b54baad 1354static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
f776471f 1355 {
3b54baad
BC		 1356 .pa_start = 0x4a310000,
1357 .pa_end = 0x4a3101ff,
f776471f
BC		 1358 .flags = ADDR_TYPE_RT
1359 },
1360};
1361
3b54baad
BC		 1362/* l4_wkup -> gpio1 */
1363static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1364 .master = &omap44xx_l4_wkup_hwmod,
1365 .slave = &omap44xx_gpio1_hwmod,
b399bca8 1366 .clk = "l4_wkup_clk_mux_ck",
3b54baad
BC		 1367 .addr = omap44xx_gpio1_addrs,
1368 .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs),
f776471f
BC		 1369 .user = OCP_USER_MPU | OCP_USER_SDMA,
1370};
1371
3b54baad
BC		 1372/* gpio1 slave ports */
1373static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1374 &omap44xx_l4_wkup__gpio1,
f776471f
BC		 1375};
1376
3b54baad 1377static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
b399bca8 1378 { .role = "dbclk", .clk = "gpio1_dbclk" },
3b54baad
BC		 1379};
1380
1381static struct omap_hwmod omap44xx_gpio1_hwmod = {
1382 .name = "gpio1",
1383 .class = &omap44xx_gpio_hwmod_class,
1384 .mpu_irqs = omap44xx_gpio1_irqs,
1385 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs),
1386 .main_clk = "gpio1_ick",
f776471f
BC		 1387 .prcm = {
1388 .omap4 = {
3b54baad 1389 .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
f776471f
BC		 1390 },
1391 },
3b54baad
BC		 1392 .opt_clks = gpio1_opt_clks,
1393 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1394 .dev_attr = &gpio_dev_attr,
1395 .slaves = omap44xx_gpio1_slaves,
1396 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
f776471f
BC		 1397 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1398};
1399
3b54baad
BC		 1400/* gpio2 */
1401static struct omap_hwmod omap44xx_gpio2_hwmod;
1402static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1403 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
f776471f
BC		 1404};
1405
3b54baad 1406static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
f776471f 1407 {
3b54baad
BC		 1408 .pa_start = 0x48055000,
1409 .pa_end = 0x480551ff,
f776471f
BC		 1410 .flags = ADDR_TYPE_RT
1411 },
1412};
1413
3b54baad
BC		 1414/* l4_per -> gpio2 */
1415static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
f776471f 1416 .master = &omap44xx_l4_per_hwmod,
3b54baad 1417 .slave = &omap44xx_gpio2_hwmod,
b399bca8 1418 .clk = "l4_div_ck",
3b54baad
BC		 1419 .addr = omap44xx_gpio2_addrs,
1420 .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs),
f776471f
BC		 1421 .user = OCP_USER_MPU | OCP_USER_SDMA,
1422};
1423
3b54baad
BC		 1424/* gpio2 slave ports */
1425static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1426 &omap44xx_l4_per__gpio2,
f776471f
BC		 1427};
1428
3b54baad 1429static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
b399bca8 1430 { .role = "dbclk", .clk = "gpio2_dbclk" },
3b54baad
BC		 1431};
1432
1433static struct omap_hwmod omap44xx_gpio2_hwmod = {
1434 .name = "gpio2",
1435 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1436 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad
BC		 1437 .mpu_irqs = omap44xx_gpio2_irqs,
1438 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs),
1439 .main_clk = "gpio2_ick",
f776471f
BC		 1440 .prcm = {
1441 .omap4 = {
3b54baad 1442 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
f776471f
BC		 1443 },
1444 },
3b54baad
BC		 1445 .opt_clks = gpio2_opt_clks,
1446 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1447 .dev_attr = &gpio_dev_attr,
1448 .slaves = omap44xx_gpio2_slaves,
1449 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
f776471f
BC		 1450 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1451};
1452
3b54baad
BC		 1453/* gpio3 */
1454static struct omap_hwmod omap44xx_gpio3_hwmod;
1455static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1456 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
f776471f
BC		 1457};
1458
3b54baad 1459static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
f776471f 1460 {
3b54baad
BC		 1461 .pa_start = 0x48057000,
1462 .pa_end = 0x480571ff,
f776471f
BC		 1463 .flags = ADDR_TYPE_RT
1464 },
1465};
1466
3b54baad
BC		 1467/* l4_per -> gpio3 */
1468static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
f776471f 1469 .master = &omap44xx_l4_per_hwmod,
3b54baad 1470 .slave = &omap44xx_gpio3_hwmod,
b399bca8 1471 .clk = "l4_div_ck",
3b54baad
BC		 1472 .addr = omap44xx_gpio3_addrs,
1473 .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs),
f776471f
BC		 1474 .user = OCP_USER_MPU | OCP_USER_SDMA,
1475};
1476
3b54baad
BC		 1477/* gpio3 slave ports */
1478static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1479 &omap44xx_l4_per__gpio3,
f776471f
BC		 1480};
1481
3b54baad 1482static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
b399bca8 1483 { .role = "dbclk", .clk = "gpio3_dbclk" },
3b54baad
BC		 1484};
1485
1486static struct omap_hwmod omap44xx_gpio3_hwmod = {
1487 .name = "gpio3",
1488 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1489 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad
BC		 1490 .mpu_irqs = omap44xx_gpio3_irqs,
1491 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs),
1492 .main_clk = "gpio3_ick",
f776471f
BC		 1493 .prcm = {
1494 .omap4 = {
3b54baad 1495 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
f776471f
BC		 1496 },
1497 },
3b54baad
BC		 1498 .opt_clks = gpio3_opt_clks,
1499 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1500 .dev_attr = &gpio_dev_attr,
1501 .slaves = omap44xx_gpio3_slaves,
1502 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
f776471f
BC		 1503 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1504};
1505
3b54baad
BC		 1506/* gpio4 */
1507static struct omap_hwmod omap44xx_gpio4_hwmod;
1508static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1509 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
f776471f
BC		 1510};
1511
3b54baad 1512static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
f776471f 1513 {
3b54baad
BC		 1514 .pa_start = 0x48059000,
1515 .pa_end = 0x480591ff,
f776471f
BC		 1516 .flags = ADDR_TYPE_RT
1517 },
1518};
1519
3b54baad
BC		 1520/* l4_per -> gpio4 */
1521static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
f776471f 1522 .master = &omap44xx_l4_per_hwmod,
3b54baad 1523 .slave = &omap44xx_gpio4_hwmod,
b399bca8 1524 .clk = "l4_div_ck",
3b54baad
BC		 1525 .addr = omap44xx_gpio4_addrs,
1526 .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs),
f776471f
BC		 1527 .user = OCP_USER_MPU | OCP_USER_SDMA,
1528};
1529
3b54baad
BC		 1530/* gpio4 slave ports */
1531static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
1532 &omap44xx_l4_per__gpio4,
f776471f
BC		 1533};
1534
3b54baad 1535static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
b399bca8 1536 { .role = "dbclk", .clk = "gpio4_dbclk" },
3b54baad
BC		 1537};
1538
1539static struct omap_hwmod omap44xx_gpio4_hwmod = {
1540 .name = "gpio4",
1541 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1542 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad
BC		 1543 .mpu_irqs = omap44xx_gpio4_irqs,
1544 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs),
1545 .main_clk = "gpio4_ick",
f776471f
BC		 1546 .prcm = {
1547 .omap4 = {
3b54baad 1548 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
f776471f
BC		 1549 },
1550 },
3b54baad
BC		 1551 .opt_clks = gpio4_opt_clks,
1552 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1553 .dev_attr = &gpio_dev_attr,
1554 .slaves = omap44xx_gpio4_slaves,
1555 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
f776471f
BC		 1556 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1557};
1558
3b54baad
BC		 1559/* gpio5 */
1560static struct omap_hwmod omap44xx_gpio5_hwmod;
1561static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1562 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
55d2cb08
BC		 1563};
1564
3b54baad
BC		 1565static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1566 {
1567 .pa_start = 0x4805b000,
1568 .pa_end = 0x4805b1ff,
1569 .flags = ADDR_TYPE_RT
1570 },
55d2cb08
BC		 1571};
1572
3b54baad
BC		 1573/* l4_per -> gpio5 */
1574static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1575 .master = &omap44xx_l4_per_hwmod,
1576 .slave = &omap44xx_gpio5_hwmod,
b399bca8 1577 .clk = "l4_div_ck",
3b54baad
BC		 1578 .addr = omap44xx_gpio5_addrs,
1579 .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs),
1580 .user = OCP_USER_MPU | OCP_USER_SDMA,
55d2cb08
BC		 1581};
1582
3b54baad
BC		 1583/* gpio5 slave ports */
1584static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
1585 &omap44xx_l4_per__gpio5,
55d2cb08
BC		 1586};
1587
3b54baad 1588static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
b399bca8 1589 { .role = "dbclk", .clk = "gpio5_dbclk" },
55d2cb08
BC		 1590};
1591
3b54baad
BC		 1592static struct omap_hwmod omap44xx_gpio5_hwmod = {
1593 .name = "gpio5",
1594 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1595 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad
BC		 1596 .mpu_irqs = omap44xx_gpio5_irqs,
1597 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs),
1598 .main_clk = "gpio5_ick",
55d2cb08
BC		 1599 .prcm = {
1600 .omap4 = {
3b54baad 1601 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
55d2cb08
BC		 1602 },
1603 },
3b54baad
BC		 1604 .opt_clks = gpio5_opt_clks,
1605 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1606 .dev_attr = &gpio_dev_attr,
1607 .slaves = omap44xx_gpio5_slaves,
1608 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
55d2cb08
BC		 1609 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1610};
1611
3b54baad
BC		 1612/* gpio6 */
1613static struct omap_hwmod omap44xx_gpio6_hwmod;
1614static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1615 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
92b18d1c
BC		 1616};
1617
3b54baad 1618static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
92b18d1c 1619 {
3b54baad
BC		 1620 .pa_start = 0x4805d000,
1621 .pa_end = 0x4805d1ff,
92b18d1c
BC		 1622 .flags = ADDR_TYPE_RT
1623 },
1624};
1625
3b54baad
BC		 1626/* l4_per -> gpio6 */
1627static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1628 .master = &omap44xx_l4_per_hwmod,
1629 .slave = &omap44xx_gpio6_hwmod,
b399bca8 1630 .clk = "l4_div_ck",
3b54baad
BC		 1631 .addr = omap44xx_gpio6_addrs,
1632 .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs),
1633 .user = OCP_USER_MPU | OCP_USER_SDMA,
db12ba53
BC		 1634};
1635
3b54baad
BC		 1636/* gpio6 slave ports */
1637static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
1638 &omap44xx_l4_per__gpio6,
db12ba53
BC		 1639};
1640
3b54baad 1641static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
b399bca8 1642 { .role = "dbclk", .clk = "gpio6_dbclk" },
db12ba53
BC		 1643};
1644
3b54baad
BC		 1645static struct omap_hwmod omap44xx_gpio6_hwmod = {
1646 .name = "gpio6",
1647 .class = &omap44xx_gpio_hwmod_class,
b399bca8 1648 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3b54baad
BC		 1649 .mpu_irqs = omap44xx_gpio6_irqs,
1650 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs),
1651 .main_clk = "gpio6_ick",
1652 .prcm = {
1653 .omap4 = {
1654 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1655 },
db12ba53 1656 },
3b54baad
BC		 1657 .opt_clks = gpio6_opt_clks,
1658 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1659 .dev_attr = &gpio_dev_attr,
1660 .slaves = omap44xx_gpio6_slaves,
1661 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
1662 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
db12ba53
BC		 1663};
1664
3b54baad
BC		 1665/*
1666 * 'i2c' class
1667 * multimaster high-speed i2c controller
1668 */
db12ba53 1669
3b54baad
BC		 1670static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1671 .sysc_offs = 0x0010,
1672 .syss_offs = 0x0090,
1673 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1674 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
0cfe8751 1675 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 1676 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1677 SIDLE_SMART_WKUP),
3b54baad 1678 .sysc_fields = &omap_hwmod_sysc_type1,
db12ba53
BC		 1679};
1680
3b54baad 1681static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
fe13471c
BC		 1682 .name = "i2c",
1683 .sysc = &omap44xx_i2c_sysc,
db12ba53
BC		 1684};
1685
3b54baad
BC		 1686/* i2c1 */
1687static struct omap_hwmod omap44xx_i2c1_hwmod;
1688static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1689 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
db12ba53
BC		 1690};
1691
3b54baad
BC		 1692static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1693 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1694 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
db12ba53
BC		 1695};
1696
3b54baad 1697static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
db12ba53 1698 {
3b54baad
BC		 1699 .pa_start = 0x48070000,
1700 .pa_end = 0x480700ff,
db12ba53
BC		 1701 .flags = ADDR_TYPE_RT
1702 },
1703};
1704
3b54baad
BC		 1705/* l4_per -> i2c1 */
1706static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
1707 .master = &omap44xx_l4_per_hwmod,
1708 .slave = &omap44xx_i2c1_hwmod,
1709 .clk = "l4_div_ck",
1710 .addr = omap44xx_i2c1_addrs,
1711 .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs),
92b18d1c
BC		 1712 .user = OCP_USER_MPU | OCP_USER_SDMA,
1713};
1714
3b54baad
BC		 1715/* i2c1 slave ports */
1716static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
1717 &omap44xx_l4_per__i2c1,
92b18d1c
BC		 1718};
1719
3b54baad
BC		 1720static struct omap_hwmod omap44xx_i2c1_hwmod = {
1721 .name = "i2c1",
1722 .class = &omap44xx_i2c_hwmod_class,
1723 .flags = HWMOD_INIT_NO_RESET,
1724 .mpu_irqs = omap44xx_i2c1_irqs,
1725 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs),
1726 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
1727 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
1728 .main_clk = "i2c1_fck",
92b18d1c
BC		 1729 .prcm = {
1730 .omap4 = {
3b54baad 1731 .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
92b18d1c
BC		 1732 },
1733 },
3b54baad
BC		 1734 .slaves = omap44xx_i2c1_slaves,
1735 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
92b18d1c
BC		 1736 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1737};
1738
3b54baad
BC		 1739/* i2c2 */
1740static struct omap_hwmod omap44xx_i2c2_hwmod;
1741static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1742 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
92b18d1c
BC		 1743};
1744
3b54baad
BC		 1745static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1746 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1747 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1748};
1749
1750static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
92b18d1c 1751 {
3b54baad
BC		 1752 .pa_start = 0x48072000,
1753 .pa_end = 0x480720ff,
92b18d1c
BC		 1754 .flags = ADDR_TYPE_RT
1755 },
1756};
1757
3b54baad
BC		 1758/* l4_per -> i2c2 */
1759static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
db12ba53 1760 .master = &omap44xx_l4_per_hwmod,
3b54baad 1761 .slave = &omap44xx_i2c2_hwmod,
db12ba53 1762 .clk = "l4_div_ck",
3b54baad
BC		 1763 .addr = omap44xx_i2c2_addrs,
1764 .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs),
db12ba53
BC		 1765 .user = OCP_USER_MPU | OCP_USER_SDMA,
1766};
1767
3b54baad
BC		 1768/* i2c2 slave ports */
1769static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
1770 &omap44xx_l4_per__i2c2,
db12ba53
BC		 1771};
1772
3b54baad
BC		 1773static struct omap_hwmod omap44xx_i2c2_hwmod = {
1774 .name = "i2c2",
1775 .class = &omap44xx_i2c_hwmod_class,
1776 .flags = HWMOD_INIT_NO_RESET,
1777 .mpu_irqs = omap44xx_i2c2_irqs,
1778 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs),
1779 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
1780 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
1781 .main_clk = "i2c2_fck",
db12ba53
BC		 1782 .prcm = {
1783 .omap4 = {
3b54baad 1784 .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
db12ba53
BC		 1785 },
1786 },
3b54baad
BC		 1787 .slaves = omap44xx_i2c2_slaves,
1788 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
db12ba53
BC		 1789 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1790};
1791
3b54baad
BC		 1792/* i2c3 */
1793static struct omap_hwmod omap44xx_i2c3_hwmod;
1794static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1795 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
db12ba53
BC		 1796};
1797
3b54baad
BC		 1798static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1799 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1800 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
92b18d1c
BC		 1801};
1802
3b54baad 1803static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
92b18d1c 1804 {
3b54baad
BC		 1805 .pa_start = 0x48060000,
1806 .pa_end = 0x480600ff,
92b18d1c
BC		 1807 .flags = ADDR_TYPE_RT
1808 },
1809};
1810
3b54baad
BC		 1811/* l4_per -> i2c3 */
1812static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
db12ba53 1813 .master = &omap44xx_l4_per_hwmod,
3b54baad 1814 .slave = &omap44xx_i2c3_hwmod,
db12ba53 1815 .clk = "l4_div_ck",
3b54baad
BC		 1816 .addr = omap44xx_i2c3_addrs,
1817 .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs),
db12ba53
BC		 1818 .user = OCP_USER_MPU | OCP_USER_SDMA,
1819};
1820
3b54baad
BC		 1821/* i2c3 slave ports */
1822static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
1823 &omap44xx_l4_per__i2c3,
db12ba53
BC		 1824};
1825
3b54baad
BC		 1826static struct omap_hwmod omap44xx_i2c3_hwmod = {
1827 .name = "i2c3",
1828 .class = &omap44xx_i2c_hwmod_class,
1829 .flags = HWMOD_INIT_NO_RESET,
1830 .mpu_irqs = omap44xx_i2c3_irqs,
1831 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs),
1832 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
1833 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
1834 .main_clk = "i2c3_fck",
db12ba53
BC		 1835 .prcm = {
1836 .omap4 = {
3b54baad 1837 .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
db12ba53
BC		 1838 },
1839 },
3b54baad
BC		 1840 .slaves = omap44xx_i2c3_slaves,
1841 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
db12ba53
BC		 1842 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1843};
1844
3b54baad
BC		 1845/* i2c4 */
1846static struct omap_hwmod omap44xx_i2c4_hwmod;
1847static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1848 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
db12ba53
BC		 1849};
1850
3b54baad
BC		 1851static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1852 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1853 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
db12ba53
BC		 1854};
1855
3b54baad 1856static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
db12ba53 1857 {
3b54baad
BC		 1858 .pa_start = 0x48350000,
1859 .pa_end = 0x483500ff,
db12ba53
BC		 1860 .flags = ADDR_TYPE_RT
1861 },
1862};
1863
3b54baad
BC		 1864/* l4_per -> i2c4 */
1865static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
1866 .master = &omap44xx_l4_per_hwmod,
1867 .slave = &omap44xx_i2c4_hwmod,
1868 .clk = "l4_div_ck",
1869 .addr = omap44xx_i2c4_addrs,
1870 .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs),
1871 .user = OCP_USER_MPU | OCP_USER_SDMA,
92b18d1c
BC		 1872};
1873
3b54baad
BC		 1874/* i2c4 slave ports */
1875static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
1876 &omap44xx_l4_per__i2c4,
92b18d1c
BC		 1877};
1878
3b54baad
BC		 1879static struct omap_hwmod omap44xx_i2c4_hwmod = {
1880 .name = "i2c4",
1881 .class = &omap44xx_i2c_hwmod_class,
1882 .flags = HWMOD_INIT_NO_RESET,
1883 .mpu_irqs = omap44xx_i2c4_irqs,
1884 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs),
1885 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
1886 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
1887 .main_clk = "i2c4_fck",
92b18d1c
BC		 1888 .prcm = {
1889 .omap4 = {
3b54baad 1890 .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
92b18d1c
BC		 1891 },
1892 },
3b54baad
BC		 1893 .slaves = omap44xx_i2c4_slaves,
1894 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
92b18d1c
BC		 1895 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1896};
1897
8f25bdc5
BC		 1898/*
1899 * 'iva' class
1900 * multi-standard video encoder/decoder hardware accelerator
1901 */
1902
1903static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
fe13471c 1904 .name = "iva",
8f25bdc5
BC		 1905};
1906
1907/* iva */
1908static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1909 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1910 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1911 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1912};
1913
1914static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1915 { .name = "logic", .rst_shift = 2 },
1916};
1917
1918static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
1919 { .name = "seq0", .rst_shift = 0 },
1920};
1921
1922static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
1923 { .name = "seq1", .rst_shift = 1 },
1924};
1925
1926/* iva master ports */
1927static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
1928 &omap44xx_iva__l3_main_2,
1929 &omap44xx_iva__l3_instr,
1930};
1931
1932static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
1933 {
1934 .pa_start = 0x5a000000,
1935 .pa_end = 0x5a07ffff,
1936 .flags = ADDR_TYPE_RT
1937 },
1938};
1939
1940/* l3_main_2 -> iva */
1941static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
1942 .master = &omap44xx_l3_main_2_hwmod,
1943 .slave = &omap44xx_iva_hwmod,
1944 .clk = "l3_div_ck",
1945 .addr = omap44xx_iva_addrs,
1946 .addr_cnt = ARRAY_SIZE(omap44xx_iva_addrs),
1947 .user = OCP_USER_MPU,
1948};
1949
1950/* iva slave ports */
1951static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
1952 &omap44xx_dsp__iva,
1953 &omap44xx_l3_main_2__iva,
1954};
1955
1956/* Pseudo hwmod for reset control purpose only */
1957static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
1958 .name = "iva_seq0",
1959 .class = &omap44xx_iva_hwmod_class,
1960 .flags = HWMOD_INIT_NO_RESET,
1961 .rst_lines = omap44xx_iva_seq0_resets,
1962 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
1963 .prcm = {
1964 .omap4 = {
1965 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1966 },
1967 },
1968 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1969};
1970
1971/* Pseudo hwmod for reset control purpose only */
1972static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
1973 .name = "iva_seq1",
1974 .class = &omap44xx_iva_hwmod_class,
1975 .flags = HWMOD_INIT_NO_RESET,
1976 .rst_lines = omap44xx_iva_seq1_resets,
1977 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
1978 .prcm = {
1979 .omap4 = {
1980 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1981 },
1982 },
1983 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1984};
1985
1986static struct omap_hwmod omap44xx_iva_hwmod = {
1987 .name = "iva",
1988 .class = &omap44xx_iva_hwmod_class,
1989 .mpu_irqs = omap44xx_iva_irqs,
1990 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iva_irqs),
1991 .rst_lines = omap44xx_iva_resets,
1992 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
1993 .main_clk = "iva_fck",
1994 .prcm = {
1995 .omap4 = {
1996 .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1997 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1998 },
1999 },
2000 .slaves = omap44xx_iva_slaves,
2001 .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves),
2002 .masters = omap44xx_iva_masters,
2003 .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters),
2004 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2005};
2006
ec5df927
BC		 2007/*
2008 * 'mailbox' class
2009 * mailbox module allowing communication between the on-chip processors using a
2010 * queued mailbox-interrupt mechanism.
2011 */
2012
2013static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2014 .rev_offs = 0x0000,
2015 .sysc_offs = 0x0010,
2016 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2017 SYSC_HAS_SOFTRESET),
2018 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2019 .sysc_fields = &omap_hwmod_sysc_type2,
2020};
2021
2022static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2023 .name = "mailbox",
2024 .sysc = &omap44xx_mailbox_sysc,
2025};
2026
2027/* mailbox */
2028static struct omap_hwmod omap44xx_mailbox_hwmod;
2029static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2030 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2031};
2032
2033static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2034 {
2035 .pa_start = 0x4a0f4000,
2036 .pa_end = 0x4a0f41ff,
2037 .flags = ADDR_TYPE_RT
2038 },
2039};
2040
2041/* l4_cfg -> mailbox */
2042static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2043 .master = &omap44xx_l4_cfg_hwmod,
2044 .slave = &omap44xx_mailbox_hwmod,
2045 .clk = "l4_div_ck",
2046 .addr = omap44xx_mailbox_addrs,
2047 .addr_cnt = ARRAY_SIZE(omap44xx_mailbox_addrs),
2048 .user = OCP_USER_MPU | OCP_USER_SDMA,
2049};
2050
2051/* mailbox slave ports */
2052static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2053 &omap44xx_l4_cfg__mailbox,
2054};
2055
2056static struct omap_hwmod omap44xx_mailbox_hwmod = {
2057 .name = "mailbox",
2058 .class = &omap44xx_mailbox_hwmod_class,
2059 .mpu_irqs = omap44xx_mailbox_irqs,
2060 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mailbox_irqs),
2061 .prcm = {
2062 .omap4 = {
2063 .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
2064 },
2065 },
2066 .slaves = omap44xx_mailbox_slaves,
2067 .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
2068 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2069};
2070
9bcbd7f0
BC		 2071/*
2072 * 'mcspi' class
2073 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2074 * bus
2075 */
2076
2077static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2078 .rev_offs = 0x0000,
2079 .sysc_offs = 0x0010,
2080 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2081 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2082 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2083 SIDLE_SMART_WKUP),
2084 .sysc_fields = &omap_hwmod_sysc_type2,
2085};
2086
2087static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2088 .name = "mcspi",
2089 .sysc = &omap44xx_mcspi_sysc,
2090};
2091
2092/* mcspi1 */
2093static struct omap_hwmod omap44xx_mcspi1_hwmod;
2094static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2095 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2096};
2097
2098static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2099 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2100 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2101 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2102 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2103 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2104 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2105 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2106 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2107};
2108
2109static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
2110 {
2111 .pa_start = 0x48098000,
2112 .pa_end = 0x480981ff,
2113 .flags = ADDR_TYPE_RT
2114 },
2115};
2116
2117/* l4_per -> mcspi1 */
2118static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
2119 .master = &omap44xx_l4_per_hwmod,
2120 .slave = &omap44xx_mcspi1_hwmod,
2121 .clk = "l4_div_ck",
2122 .addr = omap44xx_mcspi1_addrs,
2123 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi1_addrs),
2124 .user = OCP_USER_MPU | OCP_USER_SDMA,
2125};
2126
2127/* mcspi1 slave ports */
2128static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
2129 &omap44xx_l4_per__mcspi1,
2130};
2131
2132static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2133 .name = "mcspi1",
2134 .class = &omap44xx_mcspi_hwmod_class,
2135 .mpu_irqs = omap44xx_mcspi1_irqs,
2136 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_irqs),
2137 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
2138 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
2139 .main_clk = "mcspi1_fck",
2140 .prcm = {
2141 .omap4 = {
2142 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
2143 },
2144 },
2145 .slaves = omap44xx_mcspi1_slaves,
2146 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
2147 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2148};
2149
2150/* mcspi2 */
2151static struct omap_hwmod omap44xx_mcspi2_hwmod;
2152static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2153 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2154};
2155
2156static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2157 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2158 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2159 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2160 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2161};
2162
2163static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
2164 {
2165 .pa_start = 0x4809a000,
2166 .pa_end = 0x4809a1ff,
2167 .flags = ADDR_TYPE_RT
2168 },
2169};
2170
2171/* l4_per -> mcspi2 */
2172static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
2173 .master = &omap44xx_l4_per_hwmod,
2174 .slave = &omap44xx_mcspi2_hwmod,
2175 .clk = "l4_div_ck",
2176 .addr = omap44xx_mcspi2_addrs,
2177 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi2_addrs),
2178 .user = OCP_USER_MPU | OCP_USER_SDMA,
2179};
2180
2181/* mcspi2 slave ports */
2182static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
2183 &omap44xx_l4_per__mcspi2,
2184};
2185
2186static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2187 .name = "mcspi2",
2188 .class = &omap44xx_mcspi_hwmod_class,
2189 .mpu_irqs = omap44xx_mcspi2_irqs,
2190 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_irqs),
2191 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
2192 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
2193 .main_clk = "mcspi2_fck",
2194 .prcm = {
2195 .omap4 = {
2196 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
2197 },
2198 },
2199 .slaves = omap44xx_mcspi2_slaves,
2200 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
2201 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2202};
2203
2204/* mcspi3 */
2205static struct omap_hwmod omap44xx_mcspi3_hwmod;
2206static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2207 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2208};
2209
2210static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2211 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2212 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2213 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2214 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2215};
2216
2217static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
2218 {
2219 .pa_start = 0x480b8000,
2220 .pa_end = 0x480b81ff,
2221 .flags = ADDR_TYPE_RT
2222 },
2223};
2224
2225/* l4_per -> mcspi3 */
2226static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
2227 .master = &omap44xx_l4_per_hwmod,
2228 .slave = &omap44xx_mcspi3_hwmod,
2229 .clk = "l4_div_ck",
2230 .addr = omap44xx_mcspi3_addrs,
2231 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi3_addrs),
2232 .user = OCP_USER_MPU | OCP_USER_SDMA,
2233};
2234
2235/* mcspi3 slave ports */
2236static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
2237 &omap44xx_l4_per__mcspi3,
2238};
2239
2240static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2241 .name = "mcspi3",
2242 .class = &omap44xx_mcspi_hwmod_class,
2243 .mpu_irqs = omap44xx_mcspi3_irqs,
2244 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_irqs),
2245 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
2246 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
2247 .main_clk = "mcspi3_fck",
2248 .prcm = {
2249 .omap4 = {
2250 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
2251 },
2252 },
2253 .slaves = omap44xx_mcspi3_slaves,
2254 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
2255 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2256};
2257
2258/* mcspi4 */
2259static struct omap_hwmod omap44xx_mcspi4_hwmod;
2260static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2261 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2262};
2263
2264static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2265 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2266 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2267};
2268
2269static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
2270 {
2271 .pa_start = 0x480ba000,
2272 .pa_end = 0x480ba1ff,
2273 .flags = ADDR_TYPE_RT
2274 },
2275};
2276
2277/* l4_per -> mcspi4 */
2278static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
2279 .master = &omap44xx_l4_per_hwmod,
2280 .slave = &omap44xx_mcspi4_hwmod,
2281 .clk = "l4_div_ck",
2282 .addr = omap44xx_mcspi4_addrs,
2283 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi4_addrs),
2284 .user = OCP_USER_MPU | OCP_USER_SDMA,
2285};
2286
2287/* mcspi4 slave ports */
2288static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
2289 &omap44xx_l4_per__mcspi4,
2290};
2291
2292static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2293 .name = "mcspi4",
2294 .class = &omap44xx_mcspi_hwmod_class,
2295 .mpu_irqs = omap44xx_mcspi4_irqs,
2296 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_irqs),
2297 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
2298 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
2299 .main_clk = "mcspi4_fck",
2300 .prcm = {
2301 .omap4 = {
2302 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
2303 },
2304 },
2305 .slaves = omap44xx_mcspi4_slaves,
2306 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
2307 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2308};
2309
3b54baad
BC		 2310/*
2311 * 'mpu' class
2312 * mpu sub-system
2313 */
2314
2315static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
fe13471c 2316 .name = "mpu",
db12ba53
BC		 2317};
2318
3b54baad
BC		 2319/* mpu */
2320static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2321 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2322 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2323 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
db12ba53
BC		 2324};
2325
3b54baad
BC		 2326/* mpu master ports */
2327static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
2328 &omap44xx_mpu__l3_main_1,
2329 &omap44xx_mpu__l4_abe,
2330 &omap44xx_mpu__dmm,
2331};
2332
2333static struct omap_hwmod omap44xx_mpu_hwmod = {
2334 .name = "mpu",
2335 .class = &omap44xx_mpu_hwmod_class,
2336 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
2337 .mpu_irqs = omap44xx_mpu_irqs,
2338 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs),
2339 .main_clk = "dpll_mpu_m2_ck",
db12ba53
BC		 2340 .prcm = {
2341 .omap4 = {
3b54baad 2342 .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
db12ba53
BC		 2343 },
2344 },
3b54baad
BC		 2345 .masters = omap44xx_mpu_masters,
2346 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
db12ba53
BC		 2347 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2348};
2349
1f6a717f
BC		 2350/*
2351 * 'smartreflex' class
2352 * smartreflex module (monitor silicon performance and outputs a measure of
2353 * performance error)
2354 */
2355
2356/* The IP is not compliant to type1 / type2 scheme */
2357static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2358 .sidle_shift = 24,
2359 .enwkup_shift = 26,
2360};
2361
2362static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2363 .sysc_offs = 0x0038,
2364 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2365 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2366 SIDLE_SMART_WKUP),
2367 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2368};
2369
2370static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
fe13471c
BC		 2371 .name = "smartreflex",
2372 .sysc = &omap44xx_smartreflex_sysc,
2373 .rev = 2,
1f6a717f
BC		 2374};
2375
2376/* smartreflex_core */
2377static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
2378static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2379 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2380};
2381
2382static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
2383 {
2384 .pa_start = 0x4a0dd000,
2385 .pa_end = 0x4a0dd03f,
2386 .flags = ADDR_TYPE_RT
2387 },
2388};
2389
2390/* l4_cfg -> smartreflex_core */
2391static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
2392 .master = &omap44xx_l4_cfg_hwmod,
2393 .slave = &omap44xx_smartreflex_core_hwmod,
2394 .clk = "l4_div_ck",
2395 .addr = omap44xx_smartreflex_core_addrs,
2396 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
2397 .user = OCP_USER_MPU | OCP_USER_SDMA,
2398};
2399
2400/* smartreflex_core slave ports */
2401static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
2402 &omap44xx_l4_cfg__smartreflex_core,
2403};
2404
2405static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2406 .name = "smartreflex_core",
2407 .class = &omap44xx_smartreflex_hwmod_class,
2408 .mpu_irqs = omap44xx_smartreflex_core_irqs,
2409 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
2410 .main_clk = "smartreflex_core_fck",
2411 .vdd_name = "core",
2412 .prcm = {
2413 .omap4 = {
2414 .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2415 },
2416 },
2417 .slaves = omap44xx_smartreflex_core_slaves,
2418 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
2419 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2420};
2421
2422/* smartreflex_iva */
2423static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
2424static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
2425 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
2426};
2427
2428static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
2429 {
2430 .pa_start = 0x4a0db000,
2431 .pa_end = 0x4a0db03f,
2432 .flags = ADDR_TYPE_RT
2433 },
2434};
2435
2436/* l4_cfg -> smartreflex_iva */
2437static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
2438 .master = &omap44xx_l4_cfg_hwmod,
2439 .slave = &omap44xx_smartreflex_iva_hwmod,
2440 .clk = "l4_div_ck",
2441 .addr = omap44xx_smartreflex_iva_addrs,
2442 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
2443 .user = OCP_USER_MPU | OCP_USER_SDMA,
2444};
2445
2446/* smartreflex_iva slave ports */
2447static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
2448 &omap44xx_l4_cfg__smartreflex_iva,
2449};
2450
2451static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2452 .name = "smartreflex_iva",
2453 .class = &omap44xx_smartreflex_hwmod_class,
2454 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
2455 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
2456 .main_clk = "smartreflex_iva_fck",
2457 .vdd_name = "iva",
2458 .prcm = {
2459 .omap4 = {
2460 .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2461 },
2462 },
2463 .slaves = omap44xx_smartreflex_iva_slaves,
2464 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
2465 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2466};
2467
2468/* smartreflex_mpu */
2469static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
2470static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
2471 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
2472};
2473
2474static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
2475 {
2476 .pa_start = 0x4a0d9000,
2477 .pa_end = 0x4a0d903f,
2478 .flags = ADDR_TYPE_RT
2479 },
2480};
2481
2482/* l4_cfg -> smartreflex_mpu */
2483static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
2484 .master = &omap44xx_l4_cfg_hwmod,
2485 .slave = &omap44xx_smartreflex_mpu_hwmod,
2486 .clk = "l4_div_ck",
2487 .addr = omap44xx_smartreflex_mpu_addrs,
2488 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
2489 .user = OCP_USER_MPU | OCP_USER_SDMA,
2490};
2491
2492/* smartreflex_mpu slave ports */
2493static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
2494 &omap44xx_l4_cfg__smartreflex_mpu,
2495};
2496
2497static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2498 .name = "smartreflex_mpu",
2499 .class = &omap44xx_smartreflex_hwmod_class,
2500 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
2501 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
2502 .main_clk = "smartreflex_mpu_fck",
2503 .vdd_name = "mpu",
2504 .prcm = {
2505 .omap4 = {
2506 .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2507 },
2508 },
2509 .slaves = omap44xx_smartreflex_mpu_slaves,
2510 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
2511 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2512};
2513
d11c217f
BC		 2514/*
2515 * 'spinlock' class
2516 * spinlock provides hardware assistance for synchronizing the processes
2517 * running on multiple processors
2518 */
2519
2520static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2521 .rev_offs = 0x0000,
2522 .sysc_offs = 0x0010,
2523 .syss_offs = 0x0014,
2524 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2525 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2526 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2527 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2528 SIDLE_SMART_WKUP),
2529 .sysc_fields = &omap_hwmod_sysc_type1,
2530};
2531
2532static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2533 .name = "spinlock",
2534 .sysc = &omap44xx_spinlock_sysc,
2535};
2536
2537/* spinlock */
2538static struct omap_hwmod omap44xx_spinlock_hwmod;
2539static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
2540 {
2541 .pa_start = 0x4a0f6000,
2542 .pa_end = 0x4a0f6fff,
2543 .flags = ADDR_TYPE_RT
2544 },
2545};
2546
2547/* l4_cfg -> spinlock */
2548static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
2549 .master = &omap44xx_l4_cfg_hwmod,
2550 .slave = &omap44xx_spinlock_hwmod,
2551 .clk = "l4_div_ck",
2552 .addr = omap44xx_spinlock_addrs,
2553 .addr_cnt = ARRAY_SIZE(omap44xx_spinlock_addrs),
2554 .user = OCP_USER_MPU | OCP_USER_SDMA,
2555};
2556
2557/* spinlock slave ports */
2558static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
2559 &omap44xx_l4_cfg__spinlock,
2560};
2561
2562static struct omap_hwmod omap44xx_spinlock_hwmod = {
2563 .name = "spinlock",
2564 .class = &omap44xx_spinlock_hwmod_class,
2565 .prcm = {
2566 .omap4 = {
2567 .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
2568 },
2569 },
2570 .slaves = omap44xx_spinlock_slaves,
2571 .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves),
2572 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2573};
2574
35d1a66a
BC		 2575/*
2576 * 'timer' class
2577 * general purpose timer module with accurate 1ms tick
2578 * This class contains several variants: ['timer_1ms', 'timer']
2579 */
2580
2581static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2582 .rev_offs = 0x0000,
2583 .sysc_offs = 0x0010,
2584 .syss_offs = 0x0014,
2585 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2586 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2587 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2588 SYSS_HAS_RESET_STATUS),
2589 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2590 .sysc_fields = &omap_hwmod_sysc_type1,
2591};
2592
2593static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2594 .name = "timer",
2595 .sysc = &omap44xx_timer_1ms_sysc,
2596};
2597
2598static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2599 .rev_offs = 0x0000,
2600 .sysc_offs = 0x0010,
2601 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2602 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2603 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2604 SIDLE_SMART_WKUP),
2605 .sysc_fields = &omap_hwmod_sysc_type2,
2606};
2607
2608static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2609 .name = "timer",
2610 .sysc = &omap44xx_timer_sysc,
2611};
2612
2613/* timer1 */
2614static struct omap_hwmod omap44xx_timer1_hwmod;
2615static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
2616 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
2617};
2618
2619static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
2620 {
2621 .pa_start = 0x4a318000,
2622 .pa_end = 0x4a31807f,
2623 .flags = ADDR_TYPE_RT
2624 },
2625};
2626
2627/* l4_wkup -> timer1 */
2628static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
2629 .master = &omap44xx_l4_wkup_hwmod,
2630 .slave = &omap44xx_timer1_hwmod,
2631 .clk = "l4_wkup_clk_mux_ck",
2632 .addr = omap44xx_timer1_addrs,
2633 .addr_cnt = ARRAY_SIZE(omap44xx_timer1_addrs),
2634 .user = OCP_USER_MPU | OCP_USER_SDMA,
2635};
2636
2637/* timer1 slave ports */
2638static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
2639 &omap44xx_l4_wkup__timer1,
2640};
2641
2642static struct omap_hwmod omap44xx_timer1_hwmod = {
2643 .name = "timer1",
2644 .class = &omap44xx_timer_1ms_hwmod_class,
2645 .mpu_irqs = omap44xx_timer1_irqs,
2646 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs),
2647 .main_clk = "timer1_fck",
2648 .prcm = {
2649 .omap4 = {
2650 .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2651 },
2652 },
2653 .slaves = omap44xx_timer1_slaves,
2654 .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
2655 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2656};
2657
2658/* timer2 */
2659static struct omap_hwmod omap44xx_timer2_hwmod;
2660static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
2661 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
2662};
2663
2664static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
2665 {
2666 .pa_start = 0x48032000,
2667 .pa_end = 0x4803207f,
2668 .flags = ADDR_TYPE_RT
2669 },
2670};
2671
2672/* l4_per -> timer2 */
2673static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
2674 .master = &omap44xx_l4_per_hwmod,
2675 .slave = &omap44xx_timer2_hwmod,
2676 .clk = "l4_div_ck",
2677 .addr = omap44xx_timer2_addrs,
2678 .addr_cnt = ARRAY_SIZE(omap44xx_timer2_addrs),
2679 .user = OCP_USER_MPU | OCP_USER_SDMA,
2680};
2681
2682/* timer2 slave ports */
2683static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
2684 &omap44xx_l4_per__timer2,
2685};
2686
2687static struct omap_hwmod omap44xx_timer2_hwmod = {
2688 .name = "timer2",
2689 .class = &omap44xx_timer_1ms_hwmod_class,
2690 .mpu_irqs = omap44xx_timer2_irqs,
2691 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer2_irqs),
2692 .main_clk = "timer2_fck",
2693 .prcm = {
2694 .omap4 = {
2695 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2696 },
2697 },
2698 .slaves = omap44xx_timer2_slaves,
2699 .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
2700 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2701};
2702
2703/* timer3 */
2704static struct omap_hwmod omap44xx_timer3_hwmod;
2705static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
2706 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
2707};
2708
2709static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
2710 {
2711 .pa_start = 0x48034000,
2712 .pa_end = 0x4803407f,
2713 .flags = ADDR_TYPE_RT
2714 },
2715};
2716
2717/* l4_per -> timer3 */
2718static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
2719 .master = &omap44xx_l4_per_hwmod,
2720 .slave = &omap44xx_timer3_hwmod,
2721 .clk = "l4_div_ck",
2722 .addr = omap44xx_timer3_addrs,
2723 .addr_cnt = ARRAY_SIZE(omap44xx_timer3_addrs),
2724 .user = OCP_USER_MPU | OCP_USER_SDMA,
2725};
2726
2727/* timer3 slave ports */
2728static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
2729 &omap44xx_l4_per__timer3,
2730};
2731
2732static struct omap_hwmod omap44xx_timer3_hwmod = {
2733 .name = "timer3",
2734 .class = &omap44xx_timer_hwmod_class,
2735 .mpu_irqs = omap44xx_timer3_irqs,
2736 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer3_irqs),
2737 .main_clk = "timer3_fck",
2738 .prcm = {
2739 .omap4 = {
2740 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2741 },
2742 },
2743 .slaves = omap44xx_timer3_slaves,
2744 .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
2745 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2746};
2747
2748/* timer4 */
2749static struct omap_hwmod omap44xx_timer4_hwmod;
2750static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
2751 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
2752};
2753
2754static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
2755 {
2756 .pa_start = 0x48036000,
2757 .pa_end = 0x4803607f,
2758 .flags = ADDR_TYPE_RT
2759 },
2760};
2761
2762/* l4_per -> timer4 */
2763static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
2764 .master = &omap44xx_l4_per_hwmod,
2765 .slave = &omap44xx_timer4_hwmod,
2766 .clk = "l4_div_ck",
2767 .addr = omap44xx_timer4_addrs,
2768 .addr_cnt = ARRAY_SIZE(omap44xx_timer4_addrs),
2769 .user = OCP_USER_MPU | OCP_USER_SDMA,
2770};
2771
2772/* timer4 slave ports */
2773static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
2774 &omap44xx_l4_per__timer4,
2775};
2776
2777static struct omap_hwmod omap44xx_timer4_hwmod = {
2778 .name = "timer4",
2779 .class = &omap44xx_timer_hwmod_class,
2780 .mpu_irqs = omap44xx_timer4_irqs,
2781 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer4_irqs),
2782 .main_clk = "timer4_fck",
2783 .prcm = {
2784 .omap4 = {
2785 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2786 },
2787 },
2788 .slaves = omap44xx_timer4_slaves,
2789 .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
2790 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2791};
2792
2793/* timer5 */
2794static struct omap_hwmod omap44xx_timer5_hwmod;
2795static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
2796 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
2797};
2798
2799static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
2800 {
2801 .pa_start = 0x40138000,
2802 .pa_end = 0x4013807f,
2803 .flags = ADDR_TYPE_RT
2804 },
2805};
2806
2807/* l4_abe -> timer5 */
2808static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
2809 .master = &omap44xx_l4_abe_hwmod,
2810 .slave = &omap44xx_timer5_hwmod,
2811 .clk = "ocp_abe_iclk",
2812 .addr = omap44xx_timer5_addrs,
2813 .addr_cnt = ARRAY_SIZE(omap44xx_timer5_addrs),
2814 .user = OCP_USER_MPU,
2815};
2816
2817static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
2818 {
2819 .pa_start = 0x49038000,
2820 .pa_end = 0x4903807f,
2821 .flags = ADDR_TYPE_RT
2822 },
2823};
2824
2825/* l4_abe -> timer5 (dma) */
2826static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
2827 .master = &omap44xx_l4_abe_hwmod,
2828 .slave = &omap44xx_timer5_hwmod,
2829 .clk = "ocp_abe_iclk",
2830 .addr = omap44xx_timer5_dma_addrs,
2831 .addr_cnt = ARRAY_SIZE(omap44xx_timer5_dma_addrs),
2832 .user = OCP_USER_SDMA,
2833};
2834
2835/* timer5 slave ports */
2836static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
2837 &omap44xx_l4_abe__timer5,
2838 &omap44xx_l4_abe__timer5_dma,
2839};
2840
2841static struct omap_hwmod omap44xx_timer5_hwmod = {
2842 .name = "timer5",
2843 .class = &omap44xx_timer_hwmod_class,
2844 .mpu_irqs = omap44xx_timer5_irqs,
2845 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer5_irqs),
2846 .main_clk = "timer5_fck",
2847 .prcm = {
2848 .omap4 = {
2849 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2850 },
2851 },
2852 .slaves = omap44xx_timer5_slaves,
2853 .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
2854 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2855};
2856
2857/* timer6 */
2858static struct omap_hwmod omap44xx_timer6_hwmod;
2859static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
2860 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
2861};
2862
2863static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
2864 {
2865 .pa_start = 0x4013a000,
2866 .pa_end = 0x4013a07f,
2867 .flags = ADDR_TYPE_RT
2868 },
2869};
2870
2871/* l4_abe -> timer6 */
2872static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
2873 .master = &omap44xx_l4_abe_hwmod,
2874 .slave = &omap44xx_timer6_hwmod,
2875 .clk = "ocp_abe_iclk",
2876 .addr = omap44xx_timer6_addrs,
2877 .addr_cnt = ARRAY_SIZE(omap44xx_timer6_addrs),
2878 .user = OCP_USER_MPU,
2879};
2880
2881static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
2882 {
2883 .pa_start = 0x4903a000,
2884 .pa_end = 0x4903a07f,
2885 .flags = ADDR_TYPE_RT
2886 },
2887};
2888
2889/* l4_abe -> timer6 (dma) */
2890static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
2891 .master = &omap44xx_l4_abe_hwmod,
2892 .slave = &omap44xx_timer6_hwmod,
2893 .clk = "ocp_abe_iclk",
2894 .addr = omap44xx_timer6_dma_addrs,
2895 .addr_cnt = ARRAY_SIZE(omap44xx_timer6_dma_addrs),
2896 .user = OCP_USER_SDMA,
2897};
2898
2899/* timer6 slave ports */
2900static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
2901 &omap44xx_l4_abe__timer6,
2902 &omap44xx_l4_abe__timer6_dma,
2903};
2904
2905static struct omap_hwmod omap44xx_timer6_hwmod = {
2906 .name = "timer6",
2907 .class = &omap44xx_timer_hwmod_class,
2908 .mpu_irqs = omap44xx_timer6_irqs,
2909 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer6_irqs),
2910 .main_clk = "timer6_fck",
2911 .prcm = {
2912 .omap4 = {
2913 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2914 },
2915 },
2916 .slaves = omap44xx_timer6_slaves,
2917 .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
2918 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2919};
2920
2921/* timer7 */
2922static struct omap_hwmod omap44xx_timer7_hwmod;
2923static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
2924 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
2925};
2926
2927static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
2928 {
2929 .pa_start = 0x4013c000,
2930 .pa_end = 0x4013c07f,
2931 .flags = ADDR_TYPE_RT
2932 },
2933};
2934
2935/* l4_abe -> timer7 */
2936static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
2937 .master = &omap44xx_l4_abe_hwmod,
2938 .slave = &omap44xx_timer7_hwmod,
2939 .clk = "ocp_abe_iclk",
2940 .addr = omap44xx_timer7_addrs,
2941 .addr_cnt = ARRAY_SIZE(omap44xx_timer7_addrs),
2942 .user = OCP_USER_MPU,
2943};
2944
2945static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
2946 {
2947 .pa_start = 0x4903c000,
2948 .pa_end = 0x4903c07f,
2949 .flags = ADDR_TYPE_RT
2950 },
2951};
2952
2953/* l4_abe -> timer7 (dma) */
2954static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
2955 .master = &omap44xx_l4_abe_hwmod,
2956 .slave = &omap44xx_timer7_hwmod,
2957 .clk = "ocp_abe_iclk",
2958 .addr = omap44xx_timer7_dma_addrs,
2959 .addr_cnt = ARRAY_SIZE(omap44xx_timer7_dma_addrs),
2960 .user = OCP_USER_SDMA,
2961};
2962
2963/* timer7 slave ports */
2964static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
2965 &omap44xx_l4_abe__timer7,
2966 &omap44xx_l4_abe__timer7_dma,
2967};
2968
2969static struct omap_hwmod omap44xx_timer7_hwmod = {
2970 .name = "timer7",
2971 .class = &omap44xx_timer_hwmod_class,
2972 .mpu_irqs = omap44xx_timer7_irqs,
2973 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer7_irqs),
2974 .main_clk = "timer7_fck",
2975 .prcm = {
2976 .omap4 = {
2977 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2978 },
2979 },
2980 .slaves = omap44xx_timer7_slaves,
2981 .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
2982 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2983};
2984
2985/* timer8 */
2986static struct omap_hwmod omap44xx_timer8_hwmod;
2987static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
2988 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
2989};
2990
2991static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
2992 {
2993 .pa_start = 0x4013e000,
2994 .pa_end = 0x4013e07f,
2995 .flags = ADDR_TYPE_RT
2996 },
2997};
2998
2999/* l4_abe -> timer8 */
3000static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
3001 .master = &omap44xx_l4_abe_hwmod,
3002 .slave = &omap44xx_timer8_hwmod,
3003 .clk = "ocp_abe_iclk",
3004 .addr = omap44xx_timer8_addrs,
3005 .addr_cnt = ARRAY_SIZE(omap44xx_timer8_addrs),
3006 .user = OCP_USER_MPU,
3007};
3008
3009static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
3010 {
3011 .pa_start = 0x4903e000,
3012 .pa_end = 0x4903e07f,
3013 .flags = ADDR_TYPE_RT
3014 },
3015};
3016
3017/* l4_abe -> timer8 (dma) */
3018static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
3019 .master = &omap44xx_l4_abe_hwmod,
3020 .slave = &omap44xx_timer8_hwmod,
3021 .clk = "ocp_abe_iclk",
3022 .addr = omap44xx_timer8_dma_addrs,
3023 .addr_cnt = ARRAY_SIZE(omap44xx_timer8_dma_addrs),
3024 .user = OCP_USER_SDMA,
3025};
3026
3027/* timer8 slave ports */
3028static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
3029 &omap44xx_l4_abe__timer8,
3030 &omap44xx_l4_abe__timer8_dma,
3031};
3032
3033static struct omap_hwmod omap44xx_timer8_hwmod = {
3034 .name = "timer8",
3035 .class = &omap44xx_timer_hwmod_class,
3036 .mpu_irqs = omap44xx_timer8_irqs,
3037 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer8_irqs),
3038 .main_clk = "timer8_fck",
3039 .prcm = {
3040 .omap4 = {
3041 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
3042 },
3043 },
3044 .slaves = omap44xx_timer8_slaves,
3045 .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
3046 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3047};
3048
3049/* timer9 */
3050static struct omap_hwmod omap44xx_timer9_hwmod;
3051static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3052 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3053};
3054
3055static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
3056 {
3057 .pa_start = 0x4803e000,
3058 .pa_end = 0x4803e07f,
3059 .flags = ADDR_TYPE_RT
3060 },
3061};
3062
3063/* l4_per -> timer9 */
3064static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
3065 .master = &omap44xx_l4_per_hwmod,
3066 .slave = &omap44xx_timer9_hwmod,
3067 .clk = "l4_div_ck",
3068 .addr = omap44xx_timer9_addrs,
3069 .addr_cnt = ARRAY_SIZE(omap44xx_timer9_addrs),
3070 .user = OCP_USER_MPU | OCP_USER_SDMA,
3071};
3072
3073/* timer9 slave ports */
3074static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
3075 &omap44xx_l4_per__timer9,
3076};
3077
3078static struct omap_hwmod omap44xx_timer9_hwmod = {
3079 .name = "timer9",
3080 .class = &omap44xx_timer_hwmod_class,
3081 .mpu_irqs = omap44xx_timer9_irqs,
3082 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer9_irqs),
3083 .main_clk = "timer9_fck",
3084 .prcm = {
3085 .omap4 = {
3086 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
3087 },
3088 },
3089 .slaves = omap44xx_timer9_slaves,
3090 .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
3091 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3092};
3093
3094/* timer10 */
3095static struct omap_hwmod omap44xx_timer10_hwmod;
3096static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3097 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3098};
3099
3100static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
3101 {
3102 .pa_start = 0x48086000,
3103 .pa_end = 0x4808607f,
3104 .flags = ADDR_TYPE_RT
3105 },
3106};
3107
3108/* l4_per -> timer10 */
3109static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
3110 .master = &omap44xx_l4_per_hwmod,
3111 .slave = &omap44xx_timer10_hwmod,
3112 .clk = "l4_div_ck",
3113 .addr = omap44xx_timer10_addrs,
3114 .addr_cnt = ARRAY_SIZE(omap44xx_timer10_addrs),
3115 .user = OCP_USER_MPU | OCP_USER_SDMA,
3116};
3117
3118/* timer10 slave ports */
3119static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
3120 &omap44xx_l4_per__timer10,
3121};
3122
3123static struct omap_hwmod omap44xx_timer10_hwmod = {
3124 .name = "timer10",
3125 .class = &omap44xx_timer_1ms_hwmod_class,
3126 .mpu_irqs = omap44xx_timer10_irqs,
3127 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer10_irqs),
3128 .main_clk = "timer10_fck",
3129 .prcm = {
3130 .omap4 = {
3131 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
3132 },
3133 },
3134 .slaves = omap44xx_timer10_slaves,
3135 .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
3136 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3137};
3138
3139/* timer11 */
3140static struct omap_hwmod omap44xx_timer11_hwmod;
3141static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3142 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3143};
3144
3145static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
3146 {
3147 .pa_start = 0x48088000,
3148 .pa_end = 0x4808807f,
3149 .flags = ADDR_TYPE_RT
3150 },
3151};
3152
3153/* l4_per -> timer11 */
3154static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
3155 .master = &omap44xx_l4_per_hwmod,
3156 .slave = &omap44xx_timer11_hwmod,
3157 .clk = "l4_div_ck",
3158 .addr = omap44xx_timer11_addrs,
3159 .addr_cnt = ARRAY_SIZE(omap44xx_timer11_addrs),
3160 .user = OCP_USER_MPU | OCP_USER_SDMA,
3161};
3162
3163/* timer11 slave ports */
3164static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
3165 &omap44xx_l4_per__timer11,
3166};
3167
3168static struct omap_hwmod omap44xx_timer11_hwmod = {
3169 .name = "timer11",
3170 .class = &omap44xx_timer_hwmod_class,
3171 .mpu_irqs = omap44xx_timer11_irqs,
3172 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer11_irqs),
3173 .main_clk = "timer11_fck",
3174 .prcm = {
3175 .omap4 = {
3176 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
3177 },
3178 },
3179 .slaves = omap44xx_timer11_slaves,
3180 .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
3181 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3182};
3183
9780a9cf 3184/*
3b54baad
BC		 3185 * 'uart' class
3186 * universal asynchronous receiver/transmitter (uart)
9780a9cf
BC		 3187 */
3188
3b54baad
BC		 3189static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3190 .rev_offs = 0x0050,
3191 .sysc_offs = 0x0054,
3192 .syss_offs = 0x0058,
3193 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
0cfe8751
BC		 3194 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3195 SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 3196 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3197 SIDLE_SMART_WKUP),
9780a9cf
BC		 3198 .sysc_fields = &omap_hwmod_sysc_type1,
3199};
3200
3b54baad 3201static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
fe13471c
BC		 3202 .name = "uart",
3203 .sysc = &omap44xx_uart_sysc,
9780a9cf
BC		 3204};
3205
3b54baad
BC		 3206/* uart1 */
3207static struct omap_hwmod omap44xx_uart1_hwmod;
3208static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3209 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
9780a9cf
BC		 3210};
3211
3b54baad
BC		 3212static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3213 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3214 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
9780a9cf
BC		 3215};
3216
3b54baad 3217static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
9780a9cf 3218 {
3b54baad
BC		 3219 .pa_start = 0x4806a000,
3220 .pa_end = 0x4806a0ff,
9780a9cf
BC		 3221 .flags = ADDR_TYPE_RT
3222 },
3223};
3224
3b54baad
BC		 3225/* l4_per -> uart1 */
3226static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
3227 .master = &omap44xx_l4_per_hwmod,
3228 .slave = &omap44xx_uart1_hwmod,
3229 .clk = "l4_div_ck",
3230 .addr = omap44xx_uart1_addrs,
3231 .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs),
9780a9cf
BC		 3232 .user = OCP_USER_MPU | OCP_USER_SDMA,
3233};
3234
3b54baad
BC		 3235/* uart1 slave ports */
3236static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
3237 &omap44xx_l4_per__uart1,
9780a9cf
BC		 3238};
3239
3b54baad
BC		 3240static struct omap_hwmod omap44xx_uart1_hwmod = {
3241 .name = "uart1",
3242 .class = &omap44xx_uart_hwmod_class,
3243 .mpu_irqs = omap44xx_uart1_irqs,
3244 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs),
3245 .sdma_reqs = omap44xx_uart1_sdma_reqs,
3246 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
3247 .main_clk = "uart1_fck",
9780a9cf
BC		 3248 .prcm = {
3249 .omap4 = {
3b54baad 3250 .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
9780a9cf
BC		 3251 },
3252 },
3b54baad
BC		 3253 .slaves = omap44xx_uart1_slaves,
3254 .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
9780a9cf
BC		 3255 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3256};
3257
3b54baad
BC		 3258/* uart2 */
3259static struct omap_hwmod omap44xx_uart2_hwmod;
3260static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3261 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
9780a9cf
BC		 3262};
3263
3b54baad
BC		 3264static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3265 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3266 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3267};
3268
3269static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
9780a9cf 3270 {
3b54baad
BC		 3271 .pa_start = 0x4806c000,
3272 .pa_end = 0x4806c0ff,
9780a9cf
BC		 3273 .flags = ADDR_TYPE_RT
3274 },
3275};
3276
3b54baad
BC		 3277/* l4_per -> uart2 */
3278static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
9780a9cf 3279 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 3280 .slave = &omap44xx_uart2_hwmod,
3281 .clk = "l4_div_ck",
3282 .addr = omap44xx_uart2_addrs,
3283 .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs),
9780a9cf
BC		 3284 .user = OCP_USER_MPU | OCP_USER_SDMA,
3285};
3286
3b54baad
BC		 3287/* uart2 slave ports */
3288static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
3289 &omap44xx_l4_per__uart2,
9780a9cf
BC		 3290};
3291
3b54baad
BC		 3292static struct omap_hwmod omap44xx_uart2_hwmod = {
3293 .name = "uart2",
3294 .class = &omap44xx_uart_hwmod_class,
3295 .mpu_irqs = omap44xx_uart2_irqs,
3296 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs),
3297 .sdma_reqs = omap44xx_uart2_sdma_reqs,
3298 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
3299 .main_clk = "uart2_fck",
9780a9cf
BC		 3300 .prcm = {
3301 .omap4 = {
3b54baad 3302 .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
9780a9cf
BC		 3303 },
3304 },
3b54baad
BC		 3305 .slaves = omap44xx_uart2_slaves,
3306 .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
9780a9cf
BC		 3307 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3308};
3309
3b54baad
BC		 3310/* uart3 */
3311static struct omap_hwmod omap44xx_uart3_hwmod;
3312static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3313 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
9780a9cf
BC		 3314};
3315
3b54baad
BC		 3316static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3317 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3318 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3319};
3320
3321static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
9780a9cf 3322 {
3b54baad
BC		 3323 .pa_start = 0x48020000,
3324 .pa_end = 0x480200ff,
9780a9cf
BC		 3325 .flags = ADDR_TYPE_RT
3326 },
3327};
3328
3b54baad
BC		 3329/* l4_per -> uart3 */
3330static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
9780a9cf 3331 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 3332 .slave = &omap44xx_uart3_hwmod,
3333 .clk = "l4_div_ck",
3334 .addr = omap44xx_uart3_addrs,
3335 .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs),
9780a9cf
BC		 3336 .user = OCP_USER_MPU | OCP_USER_SDMA,
3337};
3338
3b54baad
BC		 3339/* uart3 slave ports */
3340static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
3341 &omap44xx_l4_per__uart3,
3342};
3343
3344static struct omap_hwmod omap44xx_uart3_hwmod = {
3345 .name = "uart3",
3346 .class = &omap44xx_uart_hwmod_class,
3347 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
3348 .mpu_irqs = omap44xx_uart3_irqs,
3349 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs),
3350 .sdma_reqs = omap44xx_uart3_sdma_reqs,
3351 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
3352 .main_clk = "uart3_fck",
9780a9cf
BC		 3353 .prcm = {
3354 .omap4 = {
3b54baad 3355 .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
9780a9cf
BC		 3356 },
3357 },
3b54baad
BC		 3358 .slaves = omap44xx_uart3_slaves,
3359 .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
9780a9cf
BC		 3360 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3361};
3362
3b54baad
BC		 3363/* uart4 */
3364static struct omap_hwmod omap44xx_uart4_hwmod;
3365static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3366 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
9780a9cf
BC		 3367};
3368
3b54baad
BC		 3369static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3370 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3371 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3372};
3373
3374static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
9780a9cf 3375 {
3b54baad
BC		 3376 .pa_start = 0x4806e000,
3377 .pa_end = 0x4806e0ff,
9780a9cf
BC		 3378 .flags = ADDR_TYPE_RT
3379 },
3380};
3381
3b54baad
BC		 3382/* l4_per -> uart4 */
3383static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
9780a9cf 3384 .master = &omap44xx_l4_per_hwmod,
3b54baad
BC		 3385 .slave = &omap44xx_uart4_hwmod,
3386 .clk = "l4_div_ck",
3387 .addr = omap44xx_uart4_addrs,
3388 .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs),
9780a9cf
BC		 3389 .user = OCP_USER_MPU | OCP_USER_SDMA,
3390};
3391
3b54baad
BC		 3392/* uart4 slave ports */
3393static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
3394 &omap44xx_l4_per__uart4,
9780a9cf
BC		 3395};
3396
3b54baad
BC		 3397static struct omap_hwmod omap44xx_uart4_hwmod = {
3398 .name = "uart4",
3399 .class = &omap44xx_uart_hwmod_class,
3400 .mpu_irqs = omap44xx_uart4_irqs,
3401 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs),
3402 .sdma_reqs = omap44xx_uart4_sdma_reqs,
3403 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
3404 .main_clk = "uart4_fck",
9780a9cf
BC		 3405 .prcm = {
3406 .omap4 = {
3b54baad 3407 .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
9780a9cf
BC		 3408 },
3409 },
3b54baad
BC		 3410 .slaves = omap44xx_uart4_slaves,
3411 .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
9780a9cf
BC		 3412 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3413};
3414
3b54baad
BC		 3415/*
3416 * 'wd_timer' class
3417 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3418 * overflow condition
3419 */
3420
3421static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3422 .rev_offs = 0x0000,
3423 .sysc_offs = 0x0010,
3424 .syss_offs = 0x0014,
3425 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
0cfe8751 3426 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
7cffa6b8
BC		 3427 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3428 SIDLE_SMART_WKUP),
3b54baad 3429 .sysc_fields = &omap_hwmod_sysc_type1,
9780a9cf
BC		 3430};
3431
3b54baad
BC		 3432static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3433 .name = "wd_timer",
3434 .sysc = &omap44xx_wd_timer_sysc,
fe13471c 3435 .pre_shutdown = &omap2_wd_timer_disable,
3b54baad
BC		 3436};
3437
3438/* wd_timer2 */
3439static struct omap_hwmod omap44xx_wd_timer2_hwmod;
3440static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3441 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3442};
3443
3444static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
9780a9cf 3445 {
3b54baad
BC		 3446 .pa_start = 0x4a314000,
3447 .pa_end = 0x4a31407f,
9780a9cf
BC		 3448 .flags = ADDR_TYPE_RT
3449 },
3450};
3451
3b54baad
BC		 3452/* l4_wkup -> wd_timer2 */
3453static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
3454 .master = &omap44xx_l4_wkup_hwmod,
3455 .slave = &omap44xx_wd_timer2_hwmod,
3456 .clk = "l4_wkup_clk_mux_ck",
3457 .addr = omap44xx_wd_timer2_addrs,
3458 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
9780a9cf
BC		 3459 .user = OCP_USER_MPU | OCP_USER_SDMA,
3460};
3461
3b54baad
BC		 3462/* wd_timer2 slave ports */
3463static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
3464 &omap44xx_l4_wkup__wd_timer2,
9780a9cf
BC		 3465};
3466
3b54baad
BC		 3467static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3468 .name = "wd_timer2",
3469 .class = &omap44xx_wd_timer_hwmod_class,
3470 .mpu_irqs = omap44xx_wd_timer2_irqs,
3471 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
3472 .main_clk = "wd_timer2_fck",
9780a9cf
BC		 3473 .prcm = {
3474 .omap4 = {
3b54baad 3475 .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
9780a9cf
BC		 3476 },
3477 },
3b54baad
BC		 3478 .slaves = omap44xx_wd_timer2_slaves,
3479 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
9780a9cf
BC		 3480 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3481};
3482
3b54baad
BC		 3483/* wd_timer3 */
3484static struct omap_hwmod omap44xx_wd_timer3_hwmod;
3485static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3486 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
9780a9cf
BC		 3487};
3488
3b54baad 3489static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
9780a9cf 3490 {
3b54baad
BC		 3491 .pa_start = 0x40130000,
3492 .pa_end = 0x4013007f,
9780a9cf
BC		 3493 .flags = ADDR_TYPE_RT
3494 },
3495};
3496
3b54baad
BC		 3497/* l4_abe -> wd_timer3 */
3498static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
3499 .master = &omap44xx_l4_abe_hwmod,
3500 .slave = &omap44xx_wd_timer3_hwmod,
3501 .clk = "ocp_abe_iclk",
3502 .addr = omap44xx_wd_timer3_addrs,
3503 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
3504 .user = OCP_USER_MPU,
9780a9cf
BC		 3505};
3506
3b54baad
BC		 3507static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
3508 {
3509 .pa_start = 0x49030000,
3510 .pa_end = 0x4903007f,
3511 .flags = ADDR_TYPE_RT
3512 },
9780a9cf
BC		 3513};
3514
3b54baad
BC		 3515/* l4_abe -> wd_timer3 (dma) */
3516static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
3517 .master = &omap44xx_l4_abe_hwmod,
3518 .slave = &omap44xx_wd_timer3_hwmod,
3519 .clk = "ocp_abe_iclk",
3520 .addr = omap44xx_wd_timer3_dma_addrs,
3521 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
3522 .user = OCP_USER_SDMA,
9780a9cf
BC		 3523};
3524
3b54baad
BC		 3525/* wd_timer3 slave ports */
3526static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
3527 &omap44xx_l4_abe__wd_timer3,
3528 &omap44xx_l4_abe__wd_timer3_dma,
3529};
3530
3531static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3532 .name = "wd_timer3",
3533 .class = &omap44xx_wd_timer_hwmod_class,
3534 .mpu_irqs = omap44xx_wd_timer3_irqs,
3535 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
3536 .main_clk = "wd_timer3_fck",
9780a9cf
BC		 3537 .prcm = {
3538 .omap4 = {
3b54baad 3539 .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
9780a9cf
BC		 3540 },
3541 },
3b54baad
BC		 3542 .slaves = omap44xx_wd_timer3_slaves,
3543 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
9780a9cf
BC		 3544 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3545};
531ce0d5 3546
55d2cb08 3547static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
fe13471c 3548
55d2cb08
BC		 3549 /* dmm class */
3550 &omap44xx_dmm_hwmod,
3b54baad 3551
55d2cb08
BC		 3552 /* emif_fw class */
3553 &omap44xx_emif_fw_hwmod,
3b54baad 3554
55d2cb08
BC		 3555 /* l3 class */
3556 &omap44xx_l3_instr_hwmod,
3557 &omap44xx_l3_main_1_hwmod,
3558 &omap44xx_l3_main_2_hwmod,
3559 &omap44xx_l3_main_3_hwmod,
3b54baad 3560
55d2cb08
BC		 3561 /* l4 class */
3562 &omap44xx_l4_abe_hwmod,
3563 &omap44xx_l4_cfg_hwmod,
3564 &omap44xx_l4_per_hwmod,
3565 &omap44xx_l4_wkup_hwmod,
531ce0d5 3566
55d2cb08
BC		 3567 /* mpu_bus class */
3568 &omap44xx_mpu_private_hwmod,
3569
d7cf5f33
BC		 3570 /* dma class */
3571 &omap44xx_dma_system_hwmod,
3572
8f25bdc5
BC		 3573 /* dsp class */
3574 &omap44xx_dsp_hwmod,
3575 &omap44xx_dsp_c0_hwmod,
3576
d63bd74f
BC		 3577 /* dss class */
3578 &omap44xx_dss_hwmod,
3579 &omap44xx_dss_dispc_hwmod,
3580 &omap44xx_dss_dsi1_hwmod,
3581 &omap44xx_dss_dsi2_hwmod,
3582 &omap44xx_dss_hdmi_hwmod,
3583 &omap44xx_dss_rfbi_hwmod,
3584 &omap44xx_dss_venc_hwmod,
3585
9780a9cf
BC		 3586 /* gpio class */
3587 &omap44xx_gpio1_hwmod,
3588 &omap44xx_gpio2_hwmod,
3589 &omap44xx_gpio3_hwmod,
3590 &omap44xx_gpio4_hwmod,
3591 &omap44xx_gpio5_hwmod,
3592 &omap44xx_gpio6_hwmod,
3593
3b54baad
BC		 3594 /* i2c class */
3595 &omap44xx_i2c1_hwmod,
3596 &omap44xx_i2c2_hwmod,
3597 &omap44xx_i2c3_hwmod,
3598 &omap44xx_i2c4_hwmod,
3599
8f25bdc5
BC		 3600 /* iva class */
3601 &omap44xx_iva_hwmod,
3602 &omap44xx_iva_seq0_hwmod,
3603 &omap44xx_iva_seq1_hwmod,
3604
ec5df927
BC		 3605 /* mailbox class */
3606 &omap44xx_mailbox_hwmod,
3607
9bcbd7f0
BC		 3608 /* mcspi class */
3609 &omap44xx_mcspi1_hwmod,
3610 &omap44xx_mcspi2_hwmod,
3611 &omap44xx_mcspi3_hwmod,
3612 &omap44xx_mcspi4_hwmod,
3613
55d2cb08
BC		 3614 /* mpu class */
3615 &omap44xx_mpu_hwmod,
db12ba53 3616
1f6a717f
BC		 3617 /* smartreflex class */
3618 &omap44xx_smartreflex_core_hwmod,
3619 &omap44xx_smartreflex_iva_hwmod,
3620 &omap44xx_smartreflex_mpu_hwmod,
3621
d11c217f
BC		 3622 /* spinlock class */
3623 &omap44xx_spinlock_hwmod,
3624
35d1a66a
BC		 3625 /* timer class */
3626 &omap44xx_timer1_hwmod,
3627 &omap44xx_timer2_hwmod,
3628 &omap44xx_timer3_hwmod,
3629 &omap44xx_timer4_hwmod,
3630 &omap44xx_timer5_hwmod,
3631 &omap44xx_timer6_hwmod,
3632 &omap44xx_timer7_hwmod,
3633 &omap44xx_timer8_hwmod,
3634 &omap44xx_timer9_hwmod,
3635 &omap44xx_timer10_hwmod,
3636 &omap44xx_timer11_hwmod,
3637
db12ba53
BC		 3638 /* uart class */
3639 &omap44xx_uart1_hwmod,
3640 &omap44xx_uart2_hwmod,
3641 &omap44xx_uart3_hwmod,
3642 &omap44xx_uart4_hwmod,
3b54baad
BC		 3643
3644 /* wd_timer class */
3645 &omap44xx_wd_timer2_hwmod,
3646 &omap44xx_wd_timer3_hwmod,
3647
55d2cb08
BC		 3648 NULL,
3649};
3650
3651int __init omap44xx_hwmod_init(void)
3652{
3653 return omap_hwmod_init(omap44xx_hwmods);
3654}
3655
Linux kernel - Deliverables
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