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08e4830d BC |
1 | /* |
2 | * Hardware modules present on the OMAP54xx chips | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com | |
5 | * | |
6 | * Paul Walmsley | |
7 | * Benoit Cousson | |
8 | * | |
9 | * This file is automatically generated from the OMAP hardware databases. | |
10 | * We respectfully ask that any modifications to this file be coordinated | |
11 | * with the public linux-omap@vger.kernel.org mailing list and the | |
12 | * authors above to ensure that the autogeneration scripts are kept | |
13 | * up-to-date with the file contents. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
19 | ||
20 | #include <linux/io.h> | |
21 | #include <linux/platform_data/gpio-omap.h> | |
22 | #include <linux/power/smartreflex.h> | |
08e4830d BC |
23 | #include <linux/i2c-omap.h> |
24 | ||
25 | #include <linux/omap-dma.h> | |
26 | #include <linux/platform_data/spi-omap2-mcspi.h> | |
27 | #include <linux/platform_data/asoc-ti-mcbsp.h> | |
28 | #include <plat/dmtimer.h> | |
29 | ||
30 | #include "omap_hwmod.h" | |
31 | #include "omap_hwmod_common_data.h" | |
32 | #include "cm1_54xx.h" | |
33 | #include "cm2_54xx.h" | |
34 | #include "prm54xx.h" | |
08e4830d BC |
35 | #include "i2c.h" |
36 | #include "mmc.h" | |
37 | #include "wd_timer.h" | |
38 | ||
39 | /* Base offset for all OMAP5 interrupts external to MPUSS */ | |
40 | #define OMAP54XX_IRQ_GIC_START 32 | |
41 | ||
42 | /* Base offset for all OMAP5 dma requests */ | |
43 | #define OMAP54XX_DMA_REQ_START 1 | |
44 | ||
45 | ||
46 | /* | |
47 | * IP blocks | |
48 | */ | |
49 | ||
50 | /* | |
51 | * 'dmm' class | |
52 | * instance(s): dmm | |
53 | */ | |
54 | static struct omap_hwmod_class omap54xx_dmm_hwmod_class = { | |
55 | .name = "dmm", | |
56 | }; | |
57 | ||
58 | /* dmm */ | |
59 | static struct omap_hwmod omap54xx_dmm_hwmod = { | |
60 | .name = "dmm", | |
61 | .class = &omap54xx_dmm_hwmod_class, | |
62 | .clkdm_name = "emif_clkdm", | |
63 | .prcm = { | |
64 | .omap4 = { | |
65 | .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET, | |
66 | .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET, | |
67 | }, | |
68 | }, | |
69 | }; | |
70 | ||
71 | /* | |
72 | * 'l3' class | |
73 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 | |
74 | */ | |
75 | static struct omap_hwmod_class omap54xx_l3_hwmod_class = { | |
76 | .name = "l3", | |
77 | }; | |
78 | ||
79 | /* l3_instr */ | |
80 | static struct omap_hwmod omap54xx_l3_instr_hwmod = { | |
81 | .name = "l3_instr", | |
82 | .class = &omap54xx_l3_hwmod_class, | |
83 | .clkdm_name = "l3instr_clkdm", | |
84 | .prcm = { | |
85 | .omap4 = { | |
86 | .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, | |
87 | .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, | |
88 | .modulemode = MODULEMODE_HWCTRL, | |
89 | }, | |
90 | }, | |
91 | }; | |
92 | ||
93 | /* l3_main_1 */ | |
94 | static struct omap_hwmod omap54xx_l3_main_1_hwmod = { | |
95 | .name = "l3_main_1", | |
96 | .class = &omap54xx_l3_hwmod_class, | |
97 | .clkdm_name = "l3main1_clkdm", | |
98 | .prcm = { | |
99 | .omap4 = { | |
100 | .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET, | |
101 | .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET, | |
102 | }, | |
103 | }, | |
104 | }; | |
105 | ||
106 | /* l3_main_2 */ | |
107 | static struct omap_hwmod omap54xx_l3_main_2_hwmod = { | |
108 | .name = "l3_main_2", | |
109 | .class = &omap54xx_l3_hwmod_class, | |
110 | .clkdm_name = "l3main2_clkdm", | |
111 | .prcm = { | |
112 | .omap4 = { | |
113 | .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET, | |
114 | .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET, | |
115 | }, | |
116 | }, | |
117 | }; | |
118 | ||
119 | /* l3_main_3 */ | |
120 | static struct omap_hwmod omap54xx_l3_main_3_hwmod = { | |
121 | .name = "l3_main_3", | |
122 | .class = &omap54xx_l3_hwmod_class, | |
123 | .clkdm_name = "l3instr_clkdm", | |
124 | .prcm = { | |
125 | .omap4 = { | |
126 | .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET, | |
127 | .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET, | |
128 | .modulemode = MODULEMODE_HWCTRL, | |
129 | }, | |
130 | }, | |
131 | }; | |
132 | ||
133 | /* | |
134 | * 'l4' class | |
135 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup | |
136 | */ | |
137 | static struct omap_hwmod_class omap54xx_l4_hwmod_class = { | |
138 | .name = "l4", | |
139 | }; | |
140 | ||
141 | /* l4_abe */ | |
142 | static struct omap_hwmod omap54xx_l4_abe_hwmod = { | |
143 | .name = "l4_abe", | |
144 | .class = &omap54xx_l4_hwmod_class, | |
145 | .clkdm_name = "abe_clkdm", | |
146 | .prcm = { | |
147 | .omap4 = { | |
148 | .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET, | |
149 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
150 | }, | |
151 | }, | |
152 | }; | |
153 | ||
154 | /* l4_cfg */ | |
155 | static struct omap_hwmod omap54xx_l4_cfg_hwmod = { | |
156 | .name = "l4_cfg", | |
157 | .class = &omap54xx_l4_hwmod_class, | |
158 | .clkdm_name = "l4cfg_clkdm", | |
159 | .prcm = { | |
160 | .omap4 = { | |
161 | .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, | |
162 | .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, | |
163 | }, | |
164 | }, | |
165 | }; | |
166 | ||
167 | /* l4_per */ | |
168 | static struct omap_hwmod omap54xx_l4_per_hwmod = { | |
169 | .name = "l4_per", | |
170 | .class = &omap54xx_l4_hwmod_class, | |
171 | .clkdm_name = "l4per_clkdm", | |
172 | .prcm = { | |
173 | .omap4 = { | |
174 | .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET, | |
175 | .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET, | |
176 | }, | |
177 | }, | |
178 | }; | |
179 | ||
180 | /* l4_wkup */ | |
181 | static struct omap_hwmod omap54xx_l4_wkup_hwmod = { | |
182 | .name = "l4_wkup", | |
183 | .class = &omap54xx_l4_hwmod_class, | |
184 | .clkdm_name = "wkupaon_clkdm", | |
185 | .prcm = { | |
186 | .omap4 = { | |
187 | .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET, | |
188 | .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET, | |
189 | }, | |
190 | }, | |
191 | }; | |
192 | ||
193 | /* | |
194 | * 'mpu_bus' class | |
195 | * instance(s): mpu_private | |
196 | */ | |
197 | static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = { | |
198 | .name = "mpu_bus", | |
199 | }; | |
200 | ||
201 | /* mpu_private */ | |
202 | static struct omap_hwmod omap54xx_mpu_private_hwmod = { | |
203 | .name = "mpu_private", | |
204 | .class = &omap54xx_mpu_bus_hwmod_class, | |
205 | .clkdm_name = "mpu_clkdm", | |
206 | .prcm = { | |
207 | .omap4 = { | |
208 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
209 | }, | |
210 | }, | |
211 | }; | |
212 | ||
213 | /* | |
214 | * 'counter' class | |
215 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock | |
216 | */ | |
217 | ||
218 | static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = { | |
219 | .rev_offs = 0x0000, | |
220 | .sysc_offs = 0x0010, | |
221 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
222 | .idlemodes = (SIDLE_FORCE | SIDLE_NO), | |
223 | .sysc_fields = &omap_hwmod_sysc_type1, | |
224 | }; | |
225 | ||
226 | static struct omap_hwmod_class omap54xx_counter_hwmod_class = { | |
227 | .name = "counter", | |
228 | .sysc = &omap54xx_counter_sysc, | |
229 | }; | |
230 | ||
231 | /* counter_32k */ | |
232 | static struct omap_hwmod omap54xx_counter_32k_hwmod = { | |
233 | .name = "counter_32k", | |
234 | .class = &omap54xx_counter_hwmod_class, | |
235 | .clkdm_name = "wkupaon_clkdm", | |
236 | .flags = HWMOD_SWSUP_SIDLE, | |
237 | .main_clk = "wkupaon_iclk_mux", | |
238 | .prcm = { | |
239 | .omap4 = { | |
240 | .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET, | |
241 | .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET, | |
242 | }, | |
243 | }, | |
244 | }; | |
245 | ||
246 | /* | |
247 | * 'dma' class | |
248 | * dma controller for data exchange between memory to memory (i.e. internal or | |
249 | * external memory) and gp peripherals to memory or memory to gp peripherals | |
250 | */ | |
251 | ||
252 | static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = { | |
253 | .rev_offs = 0x0000, | |
254 | .sysc_offs = 0x002c, | |
255 | .syss_offs = 0x0028, | |
256 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
257 | SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
258 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
259 | SYSS_HAS_RESET_STATUS), | |
260 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
261 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
262 | .sysc_fields = &omap_hwmod_sysc_type1, | |
263 | }; | |
264 | ||
265 | static struct omap_hwmod_class omap54xx_dma_hwmod_class = { | |
266 | .name = "dma", | |
267 | .sysc = &omap54xx_dma_sysc, | |
268 | }; | |
269 | ||
270 | /* dma dev_attr */ | |
271 | static struct omap_dma_dev_attr dma_dev_attr = { | |
272 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
273 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
274 | .lch_count = 32, | |
275 | }; | |
276 | ||
277 | /* dma_system */ | |
278 | static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = { | |
279 | { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START }, | |
280 | { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START }, | |
281 | { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START }, | |
282 | { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START }, | |
283 | { .irq = -1 } | |
284 | }; | |
285 | ||
286 | static struct omap_hwmod omap54xx_dma_system_hwmod = { | |
287 | .name = "dma_system", | |
288 | .class = &omap54xx_dma_hwmod_class, | |
289 | .clkdm_name = "dma_clkdm", | |
290 | .mpu_irqs = omap54xx_dma_system_irqs, | |
291 | .main_clk = "l3_iclk_div", | |
292 | .prcm = { | |
293 | .omap4 = { | |
294 | .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET, | |
295 | .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET, | |
296 | }, | |
297 | }, | |
298 | .dev_attr = &dma_dev_attr, | |
299 | }; | |
300 | ||
301 | /* | |
302 | * 'dmic' class | |
303 | * digital microphone controller | |
304 | */ | |
305 | ||
306 | static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = { | |
307 | .rev_offs = 0x0000, | |
308 | .sysc_offs = 0x0010, | |
309 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
310 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
311 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
312 | SIDLE_SMART_WKUP), | |
313 | .sysc_fields = &omap_hwmod_sysc_type2, | |
314 | }; | |
315 | ||
316 | static struct omap_hwmod_class omap54xx_dmic_hwmod_class = { | |
317 | .name = "dmic", | |
318 | .sysc = &omap54xx_dmic_sysc, | |
319 | }; | |
320 | ||
321 | /* dmic */ | |
322 | static struct omap_hwmod omap54xx_dmic_hwmod = { | |
323 | .name = "dmic", | |
324 | .class = &omap54xx_dmic_hwmod_class, | |
325 | .clkdm_name = "abe_clkdm", | |
326 | .main_clk = "dmic_gfclk", | |
327 | .prcm = { | |
328 | .omap4 = { | |
329 | .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET, | |
330 | .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET, | |
331 | .modulemode = MODULEMODE_SWCTRL, | |
332 | }, | |
333 | }, | |
334 | }; | |
335 | ||
336 | /* | |
337 | * 'emif' class | |
338 | * external memory interface no1 (wrapper) | |
339 | */ | |
340 | ||
341 | static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = { | |
342 | .rev_offs = 0x0000, | |
343 | }; | |
344 | ||
345 | static struct omap_hwmod_class omap54xx_emif_hwmod_class = { | |
346 | .name = "emif", | |
347 | .sysc = &omap54xx_emif_sysc, | |
348 | }; | |
349 | ||
350 | /* emif1 */ | |
351 | static struct omap_hwmod omap54xx_emif1_hwmod = { | |
352 | .name = "emif1", | |
353 | .class = &omap54xx_emif_hwmod_class, | |
354 | .clkdm_name = "emif_clkdm", | |
b2eb0002 | 355 | .flags = HWMOD_INIT_NO_IDLE, |
08e4830d BC |
356 | .main_clk = "dpll_core_h11x2_ck", |
357 | .prcm = { | |
358 | .omap4 = { | |
359 | .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET, | |
360 | .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET, | |
361 | .modulemode = MODULEMODE_HWCTRL, | |
362 | }, | |
363 | }, | |
364 | }; | |
365 | ||
366 | /* emif2 */ | |
367 | static struct omap_hwmod omap54xx_emif2_hwmod = { | |
368 | .name = "emif2", | |
369 | .class = &omap54xx_emif_hwmod_class, | |
370 | .clkdm_name = "emif_clkdm", | |
b2eb0002 | 371 | .flags = HWMOD_INIT_NO_IDLE, |
08e4830d BC |
372 | .main_clk = "dpll_core_h11x2_ck", |
373 | .prcm = { | |
374 | .omap4 = { | |
375 | .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET, | |
376 | .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET, | |
377 | .modulemode = MODULEMODE_HWCTRL, | |
378 | }, | |
379 | }, | |
380 | }; | |
381 | ||
382 | /* | |
383 | * 'gpio' class | |
384 | * general purpose io module | |
385 | */ | |
386 | ||
387 | static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = { | |
388 | .rev_offs = 0x0000, | |
389 | .sysc_offs = 0x0010, | |
390 | .syss_offs = 0x0114, | |
391 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
392 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
393 | SYSS_HAS_RESET_STATUS), | |
394 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
395 | SIDLE_SMART_WKUP), | |
396 | .sysc_fields = &omap_hwmod_sysc_type1, | |
397 | }; | |
398 | ||
399 | static struct omap_hwmod_class omap54xx_gpio_hwmod_class = { | |
400 | .name = "gpio", | |
401 | .sysc = &omap54xx_gpio_sysc, | |
402 | .rev = 2, | |
403 | }; | |
404 | ||
405 | /* gpio dev_attr */ | |
406 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
407 | .bank_width = 32, | |
408 | .dbck_flag = true, | |
409 | }; | |
410 | ||
411 | /* gpio1 */ | |
412 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | |
413 | { .role = "dbclk", .clk = "gpio1_dbclk" }, | |
414 | }; | |
415 | ||
416 | static struct omap_hwmod omap54xx_gpio1_hwmod = { | |
417 | .name = "gpio1", | |
418 | .class = &omap54xx_gpio_hwmod_class, | |
419 | .clkdm_name = "wkupaon_clkdm", | |
420 | .main_clk = "wkupaon_iclk_mux", | |
421 | .prcm = { | |
422 | .omap4 = { | |
423 | .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET, | |
424 | .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET, | |
425 | .modulemode = MODULEMODE_HWCTRL, | |
426 | }, | |
427 | }, | |
428 | .opt_clks = gpio1_opt_clks, | |
429 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
430 | .dev_attr = &gpio_dev_attr, | |
431 | }; | |
432 | ||
433 | /* gpio2 */ | |
434 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | |
435 | { .role = "dbclk", .clk = "gpio2_dbclk" }, | |
436 | }; | |
437 | ||
438 | static struct omap_hwmod omap54xx_gpio2_hwmod = { | |
439 | .name = "gpio2", | |
440 | .class = &omap54xx_gpio_hwmod_class, | |
441 | .clkdm_name = "l4per_clkdm", | |
442 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
443 | .main_clk = "l4_root_clk_div", | |
444 | .prcm = { | |
445 | .omap4 = { | |
446 | .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET, | |
447 | .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET, | |
448 | .modulemode = MODULEMODE_HWCTRL, | |
449 | }, | |
450 | }, | |
451 | .opt_clks = gpio2_opt_clks, | |
452 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
453 | .dev_attr = &gpio_dev_attr, | |
454 | }; | |
455 | ||
456 | /* gpio3 */ | |
457 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { | |
458 | { .role = "dbclk", .clk = "gpio3_dbclk" }, | |
459 | }; | |
460 | ||
461 | static struct omap_hwmod omap54xx_gpio3_hwmod = { | |
462 | .name = "gpio3", | |
463 | .class = &omap54xx_gpio_hwmod_class, | |
464 | .clkdm_name = "l4per_clkdm", | |
465 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
466 | .main_clk = "l4_root_clk_div", | |
467 | .prcm = { | |
468 | .omap4 = { | |
469 | .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET, | |
470 | .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET, | |
471 | .modulemode = MODULEMODE_HWCTRL, | |
472 | }, | |
473 | }, | |
474 | .opt_clks = gpio3_opt_clks, | |
475 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
476 | .dev_attr = &gpio_dev_attr, | |
477 | }; | |
478 | ||
479 | /* gpio4 */ | |
480 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { | |
481 | { .role = "dbclk", .clk = "gpio4_dbclk" }, | |
482 | }; | |
483 | ||
484 | static struct omap_hwmod omap54xx_gpio4_hwmod = { | |
485 | .name = "gpio4", | |
486 | .class = &omap54xx_gpio_hwmod_class, | |
487 | .clkdm_name = "l4per_clkdm", | |
488 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
489 | .main_clk = "l4_root_clk_div", | |
490 | .prcm = { | |
491 | .omap4 = { | |
492 | .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET, | |
493 | .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET, | |
494 | .modulemode = MODULEMODE_HWCTRL, | |
495 | }, | |
496 | }, | |
497 | .opt_clks = gpio4_opt_clks, | |
498 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
499 | .dev_attr = &gpio_dev_attr, | |
500 | }; | |
501 | ||
502 | /* gpio5 */ | |
503 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { | |
504 | { .role = "dbclk", .clk = "gpio5_dbclk" }, | |
505 | }; | |
506 | ||
507 | static struct omap_hwmod omap54xx_gpio5_hwmod = { | |
508 | .name = "gpio5", | |
509 | .class = &omap54xx_gpio_hwmod_class, | |
510 | .clkdm_name = "l4per_clkdm", | |
511 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
512 | .main_clk = "l4_root_clk_div", | |
513 | .prcm = { | |
514 | .omap4 = { | |
515 | .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET, | |
516 | .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET, | |
517 | .modulemode = MODULEMODE_HWCTRL, | |
518 | }, | |
519 | }, | |
520 | .opt_clks = gpio5_opt_clks, | |
521 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
522 | .dev_attr = &gpio_dev_attr, | |
523 | }; | |
524 | ||
525 | /* gpio6 */ | |
526 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { | |
527 | { .role = "dbclk", .clk = "gpio6_dbclk" }, | |
528 | }; | |
529 | ||
530 | static struct omap_hwmod omap54xx_gpio6_hwmod = { | |
531 | .name = "gpio6", | |
532 | .class = &omap54xx_gpio_hwmod_class, | |
533 | .clkdm_name = "l4per_clkdm", | |
534 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
535 | .main_clk = "l4_root_clk_div", | |
536 | .prcm = { | |
537 | .omap4 = { | |
538 | .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET, | |
539 | .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET, | |
540 | .modulemode = MODULEMODE_HWCTRL, | |
541 | }, | |
542 | }, | |
543 | .opt_clks = gpio6_opt_clks, | |
544 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
545 | .dev_attr = &gpio_dev_attr, | |
546 | }; | |
547 | ||
548 | /* gpio7 */ | |
549 | static struct omap_hwmod_opt_clk gpio7_opt_clks[] = { | |
550 | { .role = "dbclk", .clk = "gpio7_dbclk" }, | |
551 | }; | |
552 | ||
553 | static struct omap_hwmod omap54xx_gpio7_hwmod = { | |
554 | .name = "gpio7", | |
555 | .class = &omap54xx_gpio_hwmod_class, | |
556 | .clkdm_name = "l4per_clkdm", | |
557 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
558 | .main_clk = "l4_root_clk_div", | |
559 | .prcm = { | |
560 | .omap4 = { | |
561 | .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET, | |
562 | .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET, | |
563 | .modulemode = MODULEMODE_HWCTRL, | |
564 | }, | |
565 | }, | |
566 | .opt_clks = gpio7_opt_clks, | |
567 | .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks), | |
568 | .dev_attr = &gpio_dev_attr, | |
569 | }; | |
570 | ||
571 | /* gpio8 */ | |
572 | static struct omap_hwmod_opt_clk gpio8_opt_clks[] = { | |
573 | { .role = "dbclk", .clk = "gpio8_dbclk" }, | |
574 | }; | |
575 | ||
576 | static struct omap_hwmod omap54xx_gpio8_hwmod = { | |
577 | .name = "gpio8", | |
578 | .class = &omap54xx_gpio_hwmod_class, | |
579 | .clkdm_name = "l4per_clkdm", | |
580 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
581 | .main_clk = "l4_root_clk_div", | |
582 | .prcm = { | |
583 | .omap4 = { | |
584 | .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET, | |
585 | .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET, | |
586 | .modulemode = MODULEMODE_HWCTRL, | |
587 | }, | |
588 | }, | |
589 | .opt_clks = gpio8_opt_clks, | |
590 | .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks), | |
591 | .dev_attr = &gpio_dev_attr, | |
592 | }; | |
593 | ||
594 | /* | |
595 | * 'i2c' class | |
596 | * multimaster high-speed i2c controller | |
597 | */ | |
598 | ||
599 | static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = { | |
600 | .sysc_offs = 0x0010, | |
601 | .syss_offs = 0x0090, | |
602 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
603 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
604 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
605 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
606 | SIDLE_SMART_WKUP), | |
607 | .clockact = CLOCKACT_TEST_ICLK, | |
608 | .sysc_fields = &omap_hwmod_sysc_type1, | |
609 | }; | |
610 | ||
611 | static struct omap_hwmod_class omap54xx_i2c_hwmod_class = { | |
612 | .name = "i2c", | |
613 | .sysc = &omap54xx_i2c_sysc, | |
614 | .reset = &omap_i2c_reset, | |
615 | .rev = OMAP_I2C_IP_VERSION_2, | |
616 | }; | |
617 | ||
618 | /* i2c dev_attr */ | |
619 | static struct omap_i2c_dev_attr i2c_dev_attr = { | |
620 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, | |
621 | }; | |
622 | ||
623 | /* i2c1 */ | |
624 | static struct omap_hwmod omap54xx_i2c1_hwmod = { | |
625 | .name = "i2c1", | |
626 | .class = &omap54xx_i2c_hwmod_class, | |
627 | .clkdm_name = "l4per_clkdm", | |
628 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
629 | .main_clk = "func_96m_fclk", | |
630 | .prcm = { | |
631 | .omap4 = { | |
632 | .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET, | |
633 | .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET, | |
634 | .modulemode = MODULEMODE_SWCTRL, | |
635 | }, | |
636 | }, | |
637 | .dev_attr = &i2c_dev_attr, | |
638 | }; | |
639 | ||
640 | /* i2c2 */ | |
641 | static struct omap_hwmod omap54xx_i2c2_hwmod = { | |
642 | .name = "i2c2", | |
643 | .class = &omap54xx_i2c_hwmod_class, | |
644 | .clkdm_name = "l4per_clkdm", | |
645 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
646 | .main_clk = "func_96m_fclk", | |
647 | .prcm = { | |
648 | .omap4 = { | |
649 | .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET, | |
650 | .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET, | |
651 | .modulemode = MODULEMODE_SWCTRL, | |
652 | }, | |
653 | }, | |
654 | .dev_attr = &i2c_dev_attr, | |
655 | }; | |
656 | ||
657 | /* i2c3 */ | |
658 | static struct omap_hwmod omap54xx_i2c3_hwmod = { | |
659 | .name = "i2c3", | |
660 | .class = &omap54xx_i2c_hwmod_class, | |
661 | .clkdm_name = "l4per_clkdm", | |
662 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
663 | .main_clk = "func_96m_fclk", | |
664 | .prcm = { | |
665 | .omap4 = { | |
666 | .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET, | |
667 | .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET, | |
668 | .modulemode = MODULEMODE_SWCTRL, | |
669 | }, | |
670 | }, | |
671 | .dev_attr = &i2c_dev_attr, | |
672 | }; | |
673 | ||
674 | /* i2c4 */ | |
675 | static struct omap_hwmod omap54xx_i2c4_hwmod = { | |
676 | .name = "i2c4", | |
677 | .class = &omap54xx_i2c_hwmod_class, | |
678 | .clkdm_name = "l4per_clkdm", | |
679 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
680 | .main_clk = "func_96m_fclk", | |
681 | .prcm = { | |
682 | .omap4 = { | |
683 | .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET, | |
684 | .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET, | |
685 | .modulemode = MODULEMODE_SWCTRL, | |
686 | }, | |
687 | }, | |
688 | .dev_attr = &i2c_dev_attr, | |
689 | }; | |
690 | ||
691 | /* i2c5 */ | |
692 | static struct omap_hwmod omap54xx_i2c5_hwmod = { | |
693 | .name = "i2c5", | |
694 | .class = &omap54xx_i2c_hwmod_class, | |
695 | .clkdm_name = "l4per_clkdm", | |
696 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
697 | .main_clk = "func_96m_fclk", | |
698 | .prcm = { | |
699 | .omap4 = { | |
700 | .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET, | |
701 | .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET, | |
702 | .modulemode = MODULEMODE_SWCTRL, | |
703 | }, | |
704 | }, | |
705 | .dev_attr = &i2c_dev_attr, | |
706 | }; | |
707 | ||
708 | /* | |
709 | * 'kbd' class | |
710 | * keyboard controller | |
711 | */ | |
712 | ||
713 | static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = { | |
714 | .rev_offs = 0x0000, | |
715 | .sysc_offs = 0x0010, | |
716 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
717 | SYSC_HAS_SOFTRESET), | |
718 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
719 | .sysc_fields = &omap_hwmod_sysc_type1, | |
720 | }; | |
721 | ||
722 | static struct omap_hwmod_class omap54xx_kbd_hwmod_class = { | |
723 | .name = "kbd", | |
724 | .sysc = &omap54xx_kbd_sysc, | |
725 | }; | |
726 | ||
727 | /* kbd */ | |
728 | static struct omap_hwmod omap54xx_kbd_hwmod = { | |
729 | .name = "kbd", | |
730 | .class = &omap54xx_kbd_hwmod_class, | |
731 | .clkdm_name = "wkupaon_clkdm", | |
732 | .main_clk = "sys_32k_ck", | |
733 | .prcm = { | |
734 | .omap4 = { | |
735 | .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET, | |
736 | .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET, | |
737 | .modulemode = MODULEMODE_SWCTRL, | |
738 | }, | |
739 | }, | |
740 | }; | |
741 | ||
03ab349e SA |
742 | /* |
743 | * 'mailbox' class | |
744 | * mailbox module allowing communication between the on-chip processors using a | |
745 | * queued mailbox-interrupt mechanism. | |
746 | */ | |
747 | ||
748 | static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = { | |
749 | .rev_offs = 0x0000, | |
750 | .sysc_offs = 0x0010, | |
751 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
752 | SYSC_HAS_SOFTRESET), | |
753 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
754 | .sysc_fields = &omap_hwmod_sysc_type2, | |
755 | }; | |
756 | ||
757 | static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = { | |
758 | .name = "mailbox", | |
759 | .sysc = &omap54xx_mailbox_sysc, | |
760 | }; | |
761 | ||
762 | /* mailbox */ | |
763 | static struct omap_hwmod omap54xx_mailbox_hwmod = { | |
764 | .name = "mailbox", | |
765 | .class = &omap54xx_mailbox_hwmod_class, | |
766 | .clkdm_name = "l4cfg_clkdm", | |
767 | .prcm = { | |
768 | .omap4 = { | |
769 | .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, | |
770 | .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, | |
771 | }, | |
772 | }, | |
773 | }; | |
774 | ||
08e4830d BC |
775 | /* |
776 | * 'mcbsp' class | |
777 | * multi channel buffered serial port controller | |
778 | */ | |
779 | ||
780 | static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = { | |
781 | .sysc_offs = 0x008c, | |
782 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
783 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
784 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
785 | .sysc_fields = &omap_hwmod_sysc_type1, | |
786 | }; | |
787 | ||
788 | static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = { | |
789 | .name = "mcbsp", | |
790 | .sysc = &omap54xx_mcbsp_sysc, | |
791 | .rev = MCBSP_CONFIG_TYPE4, | |
792 | }; | |
793 | ||
794 | /* mcbsp1 */ | |
795 | static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { | |
796 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
797 | { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" }, | |
798 | }; | |
799 | ||
800 | static struct omap_hwmod omap54xx_mcbsp1_hwmod = { | |
801 | .name = "mcbsp1", | |
802 | .class = &omap54xx_mcbsp_hwmod_class, | |
803 | .clkdm_name = "abe_clkdm", | |
804 | .main_clk = "mcbsp1_gfclk", | |
805 | .prcm = { | |
806 | .omap4 = { | |
807 | .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET, | |
808 | .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET, | |
809 | .modulemode = MODULEMODE_SWCTRL, | |
810 | }, | |
811 | }, | |
812 | .opt_clks = mcbsp1_opt_clks, | |
813 | .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks), | |
814 | }; | |
815 | ||
816 | /* mcbsp2 */ | |
817 | static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { | |
818 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
819 | { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" }, | |
820 | }; | |
821 | ||
822 | static struct omap_hwmod omap54xx_mcbsp2_hwmod = { | |
823 | .name = "mcbsp2", | |
824 | .class = &omap54xx_mcbsp_hwmod_class, | |
825 | .clkdm_name = "abe_clkdm", | |
826 | .main_clk = "mcbsp2_gfclk", | |
827 | .prcm = { | |
828 | .omap4 = { | |
829 | .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET, | |
830 | .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET, | |
831 | .modulemode = MODULEMODE_SWCTRL, | |
832 | }, | |
833 | }, | |
834 | .opt_clks = mcbsp2_opt_clks, | |
835 | .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks), | |
836 | }; | |
837 | ||
838 | /* mcbsp3 */ | |
839 | static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { | |
840 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
841 | { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" }, | |
842 | }; | |
843 | ||
844 | static struct omap_hwmod omap54xx_mcbsp3_hwmod = { | |
845 | .name = "mcbsp3", | |
846 | .class = &omap54xx_mcbsp_hwmod_class, | |
847 | .clkdm_name = "abe_clkdm", | |
848 | .main_clk = "mcbsp3_gfclk", | |
849 | .prcm = { | |
850 | .omap4 = { | |
851 | .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET, | |
852 | .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET, | |
853 | .modulemode = MODULEMODE_SWCTRL, | |
854 | }, | |
855 | }, | |
856 | .opt_clks = mcbsp3_opt_clks, | |
857 | .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks), | |
858 | }; | |
859 | ||
860 | /* | |
861 | * 'mcpdm' class | |
862 | * multi channel pdm controller (proprietary interface with phoenix power | |
863 | * ic) | |
864 | */ | |
865 | ||
866 | static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = { | |
867 | .rev_offs = 0x0000, | |
868 | .sysc_offs = 0x0010, | |
869 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
870 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
871 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
872 | SIDLE_SMART_WKUP), | |
873 | .sysc_fields = &omap_hwmod_sysc_type2, | |
874 | }; | |
875 | ||
876 | static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = { | |
877 | .name = "mcpdm", | |
878 | .sysc = &omap54xx_mcpdm_sysc, | |
879 | }; | |
880 | ||
881 | /* mcpdm */ | |
882 | static struct omap_hwmod omap54xx_mcpdm_hwmod = { | |
883 | .name = "mcpdm", | |
884 | .class = &omap54xx_mcpdm_hwmod_class, | |
885 | .clkdm_name = "abe_clkdm", | |
886 | /* | |
887 | * It's suspected that the McPDM requires an off-chip main | |
888 | * functional clock, controlled via I2C. This IP block is | |
889 | * currently reset very early during boot, before I2C is | |
890 | * available, so it doesn't seem that we have any choice in | |
891 | * the kernel other than to avoid resetting it. XXX This is | |
892 | * really a hardware issue workaround: every IP block should | |
893 | * be able to source its main functional clock from either | |
894 | * on-chip or off-chip sources. McPDM seems to be the only | |
895 | * current exception. | |
896 | */ | |
897 | ||
898 | .flags = HWMOD_EXT_OPT_MAIN_CLK, | |
899 | .main_clk = "pad_clks_ck", | |
900 | .prcm = { | |
901 | .omap4 = { | |
902 | .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET, | |
903 | .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET, | |
904 | .modulemode = MODULEMODE_SWCTRL, | |
905 | }, | |
906 | }, | |
907 | }; | |
908 | ||
909 | /* | |
910 | * 'mcspi' class | |
911 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
912 | * bus | |
913 | */ | |
914 | ||
915 | static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = { | |
916 | .rev_offs = 0x0000, | |
917 | .sysc_offs = 0x0010, | |
918 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
919 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
920 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
921 | SIDLE_SMART_WKUP), | |
922 | .sysc_fields = &omap_hwmod_sysc_type2, | |
923 | }; | |
924 | ||
925 | static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = { | |
926 | .name = "mcspi", | |
927 | .sysc = &omap54xx_mcspi_sysc, | |
928 | .rev = OMAP4_MCSPI_REV, | |
929 | }; | |
930 | ||
931 | /* mcspi1 */ | |
932 | /* mcspi1 dev_attr */ | |
933 | static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { | |
934 | .num_chipselect = 4, | |
935 | }; | |
936 | ||
937 | static struct omap_hwmod omap54xx_mcspi1_hwmod = { | |
938 | .name = "mcspi1", | |
939 | .class = &omap54xx_mcspi_hwmod_class, | |
940 | .clkdm_name = "l4per_clkdm", | |
941 | .main_clk = "func_48m_fclk", | |
942 | .prcm = { | |
943 | .omap4 = { | |
944 | .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, | |
945 | .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET, | |
946 | .modulemode = MODULEMODE_SWCTRL, | |
947 | }, | |
948 | }, | |
949 | .dev_attr = &mcspi1_dev_attr, | |
950 | }; | |
951 | ||
952 | /* mcspi2 */ | |
953 | /* mcspi2 dev_attr */ | |
954 | static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { | |
955 | .num_chipselect = 2, | |
956 | }; | |
957 | ||
958 | static struct omap_hwmod omap54xx_mcspi2_hwmod = { | |
959 | .name = "mcspi2", | |
960 | .class = &omap54xx_mcspi_hwmod_class, | |
961 | .clkdm_name = "l4per_clkdm", | |
962 | .main_clk = "func_48m_fclk", | |
963 | .prcm = { | |
964 | .omap4 = { | |
965 | .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, | |
966 | .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET, | |
967 | .modulemode = MODULEMODE_SWCTRL, | |
968 | }, | |
969 | }, | |
970 | .dev_attr = &mcspi2_dev_attr, | |
971 | }; | |
972 | ||
973 | /* mcspi3 */ | |
974 | /* mcspi3 dev_attr */ | |
975 | static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { | |
976 | .num_chipselect = 2, | |
977 | }; | |
978 | ||
979 | static struct omap_hwmod omap54xx_mcspi3_hwmod = { | |
980 | .name = "mcspi3", | |
981 | .class = &omap54xx_mcspi_hwmod_class, | |
982 | .clkdm_name = "l4per_clkdm", | |
983 | .main_clk = "func_48m_fclk", | |
984 | .prcm = { | |
985 | .omap4 = { | |
986 | .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, | |
987 | .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET, | |
988 | .modulemode = MODULEMODE_SWCTRL, | |
989 | }, | |
990 | }, | |
991 | .dev_attr = &mcspi3_dev_attr, | |
992 | }; | |
993 | ||
994 | /* mcspi4 */ | |
995 | /* mcspi4 dev_attr */ | |
996 | static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { | |
997 | .num_chipselect = 1, | |
998 | }; | |
999 | ||
1000 | static struct omap_hwmod omap54xx_mcspi4_hwmod = { | |
1001 | .name = "mcspi4", | |
1002 | .class = &omap54xx_mcspi_hwmod_class, | |
1003 | .clkdm_name = "l4per_clkdm", | |
1004 | .main_clk = "func_48m_fclk", | |
1005 | .prcm = { | |
1006 | .omap4 = { | |
1007 | .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, | |
1008 | .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET, | |
1009 | .modulemode = MODULEMODE_SWCTRL, | |
1010 | }, | |
1011 | }, | |
1012 | .dev_attr = &mcspi4_dev_attr, | |
1013 | }; | |
1014 | ||
1015 | /* | |
1016 | * 'mmc' class | |
1017 | * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller | |
1018 | */ | |
1019 | ||
1020 | static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = { | |
1021 | .rev_offs = 0x0000, | |
1022 | .sysc_offs = 0x0010, | |
1023 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
1024 | SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1025 | SYSC_HAS_SOFTRESET), | |
1026 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1027 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
1028 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
1029 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1030 | }; | |
1031 | ||
1032 | static struct omap_hwmod_class omap54xx_mmc_hwmod_class = { | |
1033 | .name = "mmc", | |
1034 | .sysc = &omap54xx_mmc_sysc, | |
1035 | }; | |
1036 | ||
1037 | /* mmc1 */ | |
1038 | static struct omap_hwmod_opt_clk mmc1_opt_clks[] = { | |
1039 | { .role = "32khz_clk", .clk = "mmc1_32khz_clk" }, | |
1040 | }; | |
1041 | ||
1042 | /* mmc1 dev_attr */ | |
1043 | static struct omap_mmc_dev_attr mmc1_dev_attr = { | |
1044 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
1045 | }; | |
1046 | ||
1047 | static struct omap_hwmod omap54xx_mmc1_hwmod = { | |
1048 | .name = "mmc1", | |
1049 | .class = &omap54xx_mmc_hwmod_class, | |
1050 | .clkdm_name = "l3init_clkdm", | |
1051 | .main_clk = "mmc1_fclk", | |
1052 | .prcm = { | |
1053 | .omap4 = { | |
1054 | .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET, | |
1055 | .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET, | |
1056 | .modulemode = MODULEMODE_SWCTRL, | |
1057 | }, | |
1058 | }, | |
1059 | .opt_clks = mmc1_opt_clks, | |
1060 | .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks), | |
1061 | .dev_attr = &mmc1_dev_attr, | |
1062 | }; | |
1063 | ||
1064 | /* mmc2 */ | |
1065 | static struct omap_hwmod omap54xx_mmc2_hwmod = { | |
1066 | .name = "mmc2", | |
1067 | .class = &omap54xx_mmc_hwmod_class, | |
1068 | .clkdm_name = "l3init_clkdm", | |
1069 | .main_clk = "mmc2_fclk", | |
1070 | .prcm = { | |
1071 | .omap4 = { | |
1072 | .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET, | |
1073 | .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET, | |
1074 | .modulemode = MODULEMODE_SWCTRL, | |
1075 | }, | |
1076 | }, | |
1077 | }; | |
1078 | ||
1079 | /* mmc3 */ | |
1080 | static struct omap_hwmod omap54xx_mmc3_hwmod = { | |
1081 | .name = "mmc3", | |
1082 | .class = &omap54xx_mmc_hwmod_class, | |
1083 | .clkdm_name = "l4per_clkdm", | |
1084 | .main_clk = "func_48m_fclk", | |
1085 | .prcm = { | |
1086 | .omap4 = { | |
1087 | .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET, | |
1088 | .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET, | |
1089 | .modulemode = MODULEMODE_SWCTRL, | |
1090 | }, | |
1091 | }, | |
1092 | }; | |
1093 | ||
1094 | /* mmc4 */ | |
1095 | static struct omap_hwmod omap54xx_mmc4_hwmod = { | |
1096 | .name = "mmc4", | |
1097 | .class = &omap54xx_mmc_hwmod_class, | |
1098 | .clkdm_name = "l4per_clkdm", | |
1099 | .main_clk = "func_48m_fclk", | |
1100 | .prcm = { | |
1101 | .omap4 = { | |
1102 | .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET, | |
1103 | .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET, | |
1104 | .modulemode = MODULEMODE_SWCTRL, | |
1105 | }, | |
1106 | }, | |
1107 | }; | |
1108 | ||
1109 | /* mmc5 */ | |
1110 | static struct omap_hwmod omap54xx_mmc5_hwmod = { | |
1111 | .name = "mmc5", | |
1112 | .class = &omap54xx_mmc_hwmod_class, | |
1113 | .clkdm_name = "l4per_clkdm", | |
1114 | .main_clk = "func_96m_fclk", | |
1115 | .prcm = { | |
1116 | .omap4 = { | |
1117 | .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET, | |
1118 | .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET, | |
1119 | .modulemode = MODULEMODE_SWCTRL, | |
1120 | }, | |
1121 | }, | |
1122 | }; | |
1123 | ||
1528ed04 SA |
1124 | /* |
1125 | * 'mmu' class | |
1126 | * The memory management unit performs virtual to physical address translation | |
1127 | * for its requestors. | |
1128 | */ | |
1129 | ||
1130 | static struct omap_hwmod_class_sysconfig omap54xx_mmu_sysc = { | |
1131 | .rev_offs = 0x0000, | |
1132 | .sysc_offs = 0x0010, | |
1133 | .syss_offs = 0x0014, | |
1134 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1135 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1136 | SYSS_HAS_RESET_STATUS), | |
1137 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1138 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1139 | }; | |
1140 | ||
1141 | static struct omap_hwmod_class omap54xx_mmu_hwmod_class = { | |
1142 | .name = "mmu", | |
1143 | .sysc = &omap54xx_mmu_sysc, | |
1144 | }; | |
1145 | ||
1146 | static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets[] = { | |
1147 | { .name = "mmu_cache", .rst_shift = 1 }, | |
1148 | }; | |
1149 | ||
1150 | static struct omap_hwmod omap54xx_mmu_dsp_hwmod = { | |
1151 | .name = "mmu_dsp", | |
1152 | .class = &omap54xx_mmu_hwmod_class, | |
1153 | .clkdm_name = "dsp_clkdm", | |
1154 | .rst_lines = omap54xx_mmu_dsp_resets, | |
1155 | .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_dsp_resets), | |
1156 | .main_clk = "dpll_iva_h11x2_ck", | |
1157 | .prcm = { | |
1158 | .omap4 = { | |
1159 | .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET, | |
1160 | .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET, | |
1161 | .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET, | |
1162 | .modulemode = MODULEMODE_HWCTRL, | |
1163 | }, | |
1164 | }, | |
1165 | }; | |
1166 | ||
1167 | /* mmu ipu */ | |
1168 | static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets[] = { | |
1169 | { .name = "mmu_cache", .rst_shift = 2 }, | |
1170 | }; | |
1171 | ||
1172 | static struct omap_hwmod omap54xx_mmu_ipu_hwmod = { | |
1173 | .name = "mmu_ipu", | |
1174 | .class = &omap54xx_mmu_hwmod_class, | |
1175 | .clkdm_name = "ipu_clkdm", | |
1176 | .rst_lines = omap54xx_mmu_ipu_resets, | |
1177 | .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_ipu_resets), | |
1178 | .main_clk = "dpll_core_h22x2_ck", | |
1179 | .prcm = { | |
1180 | .omap4 = { | |
1181 | .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET, | |
1182 | .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET, | |
1183 | .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET, | |
1184 | .modulemode = MODULEMODE_HWCTRL, | |
1185 | }, | |
1186 | }, | |
1187 | }; | |
1188 | ||
08e4830d BC |
1189 | /* |
1190 | * 'mpu' class | |
1191 | * mpu sub-system | |
1192 | */ | |
1193 | ||
1194 | static struct omap_hwmod_class omap54xx_mpu_hwmod_class = { | |
1195 | .name = "mpu", | |
1196 | }; | |
1197 | ||
1198 | /* mpu */ | |
1199 | static struct omap_hwmod omap54xx_mpu_hwmod = { | |
1200 | .name = "mpu", | |
1201 | .class = &omap54xx_mpu_hwmod_class, | |
1202 | .clkdm_name = "mpu_clkdm", | |
b2eb0002 | 1203 | .flags = HWMOD_INIT_NO_IDLE, |
08e4830d BC |
1204 | .main_clk = "dpll_mpu_m2_ck", |
1205 | .prcm = { | |
1206 | .omap4 = { | |
1207 | .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET, | |
1208 | .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET, | |
1209 | }, | |
1210 | }, | |
1211 | }; | |
1212 | ||
325529d1 SA |
1213 | /* |
1214 | * 'spinlock' class | |
1215 | * spinlock provides hardware assistance for synchronizing the processes | |
1216 | * running on multiple processors | |
1217 | */ | |
1218 | ||
1219 | static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = { | |
1220 | .rev_offs = 0x0000, | |
1221 | .sysc_offs = 0x0010, | |
1222 | .syss_offs = 0x0014, | |
1223 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1224 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
1225 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1226 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1227 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1228 | }; | |
1229 | ||
1230 | static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = { | |
1231 | .name = "spinlock", | |
1232 | .sysc = &omap54xx_spinlock_sysc, | |
1233 | }; | |
1234 | ||
1235 | /* spinlock */ | |
1236 | static struct omap_hwmod omap54xx_spinlock_hwmod = { | |
1237 | .name = "spinlock", | |
1238 | .class = &omap54xx_spinlock_hwmod_class, | |
1239 | .clkdm_name = "l4cfg_clkdm", | |
1240 | .prcm = { | |
1241 | .omap4 = { | |
1242 | .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET, | |
1243 | .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET, | |
1244 | }, | |
1245 | }, | |
1246 | }; | |
1247 | ||
254f57a9 BC |
1248 | /* |
1249 | * 'ocp2scp' class | |
1250 | * bridge to transform ocp interface protocol to scp (serial control port) | |
1251 | * protocol | |
1252 | */ | |
1253 | ||
1254 | static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = { | |
1255 | .rev_offs = 0x0000, | |
1256 | .sysc_offs = 0x0010, | |
1257 | .syss_offs = 0x0014, | |
1258 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
1259 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1260 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1261 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1262 | }; | |
1263 | ||
1264 | static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = { | |
1265 | .name = "ocp2scp", | |
1266 | .sysc = &omap54xx_ocp2scp_sysc, | |
1267 | }; | |
1268 | ||
1269 | /* ocp2scp1 */ | |
1270 | static struct omap_hwmod omap54xx_ocp2scp1_hwmod = { | |
1271 | .name = "ocp2scp1", | |
1272 | .class = &omap54xx_ocp2scp_hwmod_class, | |
1273 | .clkdm_name = "l3init_clkdm", | |
1274 | .main_clk = "l4_root_clk_div", | |
1275 | .prcm = { | |
1276 | .omap4 = { | |
1277 | .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET, | |
1278 | .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET, | |
1279 | .modulemode = MODULEMODE_HWCTRL, | |
1280 | }, | |
1281 | }, | |
1282 | }; | |
1283 | ||
08e4830d BC |
1284 | /* |
1285 | * 'timer' class | |
1286 | * general purpose timer module with accurate 1ms tick | |
1287 | * This class contains several variants: ['timer_1ms', 'timer'] | |
1288 | */ | |
1289 | ||
1290 | static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = { | |
1291 | .rev_offs = 0x0000, | |
1292 | .sysc_offs = 0x0010, | |
1293 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
1294 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1295 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1296 | SIDLE_SMART_WKUP), | |
1297 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1298 | .clockact = CLOCKACT_TEST_ICLK, | |
1299 | }; | |
1300 | ||
1301 | static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = { | |
1302 | .name = "timer", | |
1303 | .sysc = &omap54xx_timer_1ms_sysc, | |
1304 | }; | |
1305 | ||
1306 | static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = { | |
1307 | .rev_offs = 0x0000, | |
1308 | .sysc_offs = 0x0010, | |
1309 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
1310 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1311 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1312 | SIDLE_SMART_WKUP), | |
1313 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1314 | }; | |
1315 | ||
1316 | static struct omap_hwmod_class omap54xx_timer_hwmod_class = { | |
1317 | .name = "timer", | |
1318 | .sysc = &omap54xx_timer_sysc, | |
1319 | }; | |
1320 | ||
1321 | /* timer1 */ | |
1322 | static struct omap_hwmod omap54xx_timer1_hwmod = { | |
1323 | .name = "timer1", | |
1324 | .class = &omap54xx_timer_1ms_hwmod_class, | |
1325 | .clkdm_name = "wkupaon_clkdm", | |
1326 | .main_clk = "timer1_gfclk_mux", | |
1327 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
1328 | .prcm = { | |
1329 | .omap4 = { | |
1330 | .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET, | |
1331 | .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET, | |
1332 | .modulemode = MODULEMODE_SWCTRL, | |
1333 | }, | |
1334 | }, | |
1335 | }; | |
1336 | ||
1337 | /* timer2 */ | |
1338 | static struct omap_hwmod omap54xx_timer2_hwmod = { | |
1339 | .name = "timer2", | |
1340 | .class = &omap54xx_timer_1ms_hwmod_class, | |
1341 | .clkdm_name = "l4per_clkdm", | |
1342 | .main_clk = "timer2_gfclk_mux", | |
1343 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
1344 | .prcm = { | |
1345 | .omap4 = { | |
1346 | .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET, | |
1347 | .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET, | |
1348 | .modulemode = MODULEMODE_SWCTRL, | |
1349 | }, | |
1350 | }, | |
1351 | }; | |
1352 | ||
1353 | /* timer3 */ | |
1354 | static struct omap_hwmod omap54xx_timer3_hwmod = { | |
1355 | .name = "timer3", | |
1356 | .class = &omap54xx_timer_hwmod_class, | |
1357 | .clkdm_name = "l4per_clkdm", | |
1358 | .main_clk = "timer3_gfclk_mux", | |
1359 | .prcm = { | |
1360 | .omap4 = { | |
1361 | .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET, | |
1362 | .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET, | |
1363 | .modulemode = MODULEMODE_SWCTRL, | |
1364 | }, | |
1365 | }, | |
1366 | }; | |
1367 | ||
1368 | /* timer4 */ | |
1369 | static struct omap_hwmod omap54xx_timer4_hwmod = { | |
1370 | .name = "timer4", | |
1371 | .class = &omap54xx_timer_hwmod_class, | |
1372 | .clkdm_name = "l4per_clkdm", | |
1373 | .main_clk = "timer4_gfclk_mux", | |
1374 | .prcm = { | |
1375 | .omap4 = { | |
1376 | .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET, | |
1377 | .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET, | |
1378 | .modulemode = MODULEMODE_SWCTRL, | |
1379 | }, | |
1380 | }, | |
1381 | }; | |
1382 | ||
1383 | /* timer5 */ | |
1384 | static struct omap_hwmod omap54xx_timer5_hwmod = { | |
1385 | .name = "timer5", | |
1386 | .class = &omap54xx_timer_hwmod_class, | |
1387 | .clkdm_name = "abe_clkdm", | |
1388 | .main_clk = "timer5_gfclk_mux", | |
1389 | .prcm = { | |
1390 | .omap4 = { | |
1391 | .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET, | |
1392 | .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET, | |
1393 | .modulemode = MODULEMODE_SWCTRL, | |
1394 | }, | |
1395 | }, | |
1396 | }; | |
1397 | ||
1398 | /* timer6 */ | |
1399 | static struct omap_hwmod omap54xx_timer6_hwmod = { | |
1400 | .name = "timer6", | |
1401 | .class = &omap54xx_timer_hwmod_class, | |
1402 | .clkdm_name = "abe_clkdm", | |
1403 | .main_clk = "timer6_gfclk_mux", | |
1404 | .prcm = { | |
1405 | .omap4 = { | |
1406 | .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET, | |
1407 | .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET, | |
1408 | .modulemode = MODULEMODE_SWCTRL, | |
1409 | }, | |
1410 | }, | |
1411 | }; | |
1412 | ||
1413 | /* timer7 */ | |
1414 | static struct omap_hwmod omap54xx_timer7_hwmod = { | |
1415 | .name = "timer7", | |
1416 | .class = &omap54xx_timer_hwmod_class, | |
1417 | .clkdm_name = "abe_clkdm", | |
1418 | .main_clk = "timer7_gfclk_mux", | |
1419 | .prcm = { | |
1420 | .omap4 = { | |
1421 | .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET, | |
1422 | .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET, | |
1423 | .modulemode = MODULEMODE_SWCTRL, | |
1424 | }, | |
1425 | }, | |
1426 | }; | |
1427 | ||
1428 | /* timer8 */ | |
1429 | static struct omap_hwmod omap54xx_timer8_hwmod = { | |
1430 | .name = "timer8", | |
1431 | .class = &omap54xx_timer_hwmod_class, | |
1432 | .clkdm_name = "abe_clkdm", | |
1433 | .main_clk = "timer8_gfclk_mux", | |
1434 | .prcm = { | |
1435 | .omap4 = { | |
1436 | .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET, | |
1437 | .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET, | |
1438 | .modulemode = MODULEMODE_SWCTRL, | |
1439 | }, | |
1440 | }, | |
1441 | }; | |
1442 | ||
1443 | /* timer9 */ | |
1444 | static struct omap_hwmod omap54xx_timer9_hwmod = { | |
1445 | .name = "timer9", | |
1446 | .class = &omap54xx_timer_hwmod_class, | |
1447 | .clkdm_name = "l4per_clkdm", | |
1448 | .main_clk = "timer9_gfclk_mux", | |
1449 | .prcm = { | |
1450 | .omap4 = { | |
1451 | .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET, | |
1452 | .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET, | |
1453 | .modulemode = MODULEMODE_SWCTRL, | |
1454 | }, | |
1455 | }, | |
1456 | }; | |
1457 | ||
1458 | /* timer10 */ | |
1459 | static struct omap_hwmod omap54xx_timer10_hwmod = { | |
1460 | .name = "timer10", | |
1461 | .class = &omap54xx_timer_1ms_hwmod_class, | |
1462 | .clkdm_name = "l4per_clkdm", | |
1463 | .main_clk = "timer10_gfclk_mux", | |
1464 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
1465 | .prcm = { | |
1466 | .omap4 = { | |
1467 | .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET, | |
1468 | .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET, | |
1469 | .modulemode = MODULEMODE_SWCTRL, | |
1470 | }, | |
1471 | }, | |
1472 | }; | |
1473 | ||
1474 | /* timer11 */ | |
1475 | static struct omap_hwmod omap54xx_timer11_hwmod = { | |
1476 | .name = "timer11", | |
1477 | .class = &omap54xx_timer_hwmod_class, | |
1478 | .clkdm_name = "l4per_clkdm", | |
1479 | .main_clk = "timer11_gfclk_mux", | |
1480 | .prcm = { | |
1481 | .omap4 = { | |
1482 | .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET, | |
1483 | .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET, | |
1484 | .modulemode = MODULEMODE_SWCTRL, | |
1485 | }, | |
1486 | }, | |
1487 | }; | |
1488 | ||
1489 | /* | |
1490 | * 'uart' class | |
1491 | * universal asynchronous receiver/transmitter (uart) | |
1492 | */ | |
1493 | ||
1494 | static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = { | |
1495 | .rev_offs = 0x0050, | |
1496 | .sysc_offs = 0x0054, | |
1497 | .syss_offs = 0x0058, | |
1498 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
1499 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1500 | SYSS_HAS_RESET_STATUS), | |
1501 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1502 | SIDLE_SMART_WKUP), | |
1503 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1504 | }; | |
1505 | ||
1506 | static struct omap_hwmod_class omap54xx_uart_hwmod_class = { | |
1507 | .name = "uart", | |
1508 | .sysc = &omap54xx_uart_sysc, | |
1509 | }; | |
1510 | ||
1511 | /* uart1 */ | |
1512 | static struct omap_hwmod omap54xx_uart1_hwmod = { | |
1513 | .name = "uart1", | |
1514 | .class = &omap54xx_uart_hwmod_class, | |
1515 | .clkdm_name = "l4per_clkdm", | |
1516 | .main_clk = "func_48m_fclk", | |
1517 | .prcm = { | |
1518 | .omap4 = { | |
1519 | .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET, | |
1520 | .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET, | |
1521 | .modulemode = MODULEMODE_SWCTRL, | |
1522 | }, | |
1523 | }, | |
1524 | }; | |
1525 | ||
1526 | /* uart2 */ | |
1527 | static struct omap_hwmod omap54xx_uart2_hwmod = { | |
1528 | .name = "uart2", | |
1529 | .class = &omap54xx_uart_hwmod_class, | |
1530 | .clkdm_name = "l4per_clkdm", | |
1531 | .main_clk = "func_48m_fclk", | |
1532 | .prcm = { | |
1533 | .omap4 = { | |
1534 | .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET, | |
1535 | .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET, | |
1536 | .modulemode = MODULEMODE_SWCTRL, | |
1537 | }, | |
1538 | }, | |
1539 | }; | |
1540 | ||
1541 | /* uart3 */ | |
1542 | static struct omap_hwmod omap54xx_uart3_hwmod = { | |
1543 | .name = "uart3", | |
1544 | .class = &omap54xx_uart_hwmod_class, | |
1545 | .clkdm_name = "l4per_clkdm", | |
7dedd346 | 1546 | .flags = DEBUG_OMAP4UART3_FLAGS, |
08e4830d BC |
1547 | .main_clk = "func_48m_fclk", |
1548 | .prcm = { | |
1549 | .omap4 = { | |
1550 | .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET, | |
1551 | .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET, | |
1552 | .modulemode = MODULEMODE_SWCTRL, | |
1553 | }, | |
1554 | }, | |
1555 | }; | |
1556 | ||
1557 | /* uart4 */ | |
1558 | static struct omap_hwmod omap54xx_uart4_hwmod = { | |
1559 | .name = "uart4", | |
1560 | .class = &omap54xx_uart_hwmod_class, | |
1561 | .clkdm_name = "l4per_clkdm", | |
7dedd346 | 1562 | .flags = DEBUG_OMAP4UART4_FLAGS, |
08e4830d BC |
1563 | .main_clk = "func_48m_fclk", |
1564 | .prcm = { | |
1565 | .omap4 = { | |
1566 | .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET, | |
1567 | .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET, | |
1568 | .modulemode = MODULEMODE_SWCTRL, | |
1569 | }, | |
1570 | }, | |
1571 | }; | |
1572 | ||
1573 | /* uart5 */ | |
1574 | static struct omap_hwmod omap54xx_uart5_hwmod = { | |
1575 | .name = "uart5", | |
1576 | .class = &omap54xx_uart_hwmod_class, | |
1577 | .clkdm_name = "l4per_clkdm", | |
1578 | .main_clk = "func_48m_fclk", | |
1579 | .prcm = { | |
1580 | .omap4 = { | |
1581 | .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET, | |
1582 | .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET, | |
1583 | .modulemode = MODULEMODE_SWCTRL, | |
1584 | }, | |
1585 | }, | |
1586 | }; | |
1587 | ||
1588 | /* uart6 */ | |
1589 | static struct omap_hwmod omap54xx_uart6_hwmod = { | |
1590 | .name = "uart6", | |
1591 | .class = &omap54xx_uart_hwmod_class, | |
1592 | .clkdm_name = "l4per_clkdm", | |
1593 | .main_clk = "func_48m_fclk", | |
1594 | .prcm = { | |
1595 | .omap4 = { | |
1596 | .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET, | |
1597 | .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET, | |
1598 | .modulemode = MODULEMODE_SWCTRL, | |
1599 | }, | |
1600 | }, | |
1601 | }; | |
1602 | ||
e01478b0 RQ |
1603 | /* |
1604 | * 'usb_host_hs' class | |
1605 | * high-speed multi-port usb host controller | |
1606 | */ | |
1607 | ||
1608 | static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = { | |
1609 | .rev_offs = 0x0000, | |
1610 | .sysc_offs = 0x0010, | |
1611 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | | |
b483a4a5 RQ |
1612 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
1613 | SYSC_HAS_RESET_STATUS), | |
e01478b0 RQ |
1614 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1615 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
1616 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
1617 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1618 | }; | |
1619 | ||
1620 | static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = { | |
1621 | .name = "usb_host_hs", | |
1622 | .sysc = &omap54xx_usb_host_hs_sysc, | |
1623 | }; | |
1624 | ||
1625 | static struct omap_hwmod omap54xx_usb_host_hs_hwmod = { | |
1626 | .name = "usb_host_hs", | |
1627 | .class = &omap54xx_usb_host_hs_hwmod_class, | |
1628 | .clkdm_name = "l3init_clkdm", | |
1629 | /* | |
1630 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
1631 | * id: i660 | |
1632 | * | |
1633 | * Description: | |
1634 | * In the following configuration : | |
1635 | * - USBHOST module is set to smart-idle mode | |
1636 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
1637 | * happens when the system is going to a low power mode : all ports | |
1638 | * have been suspended, the master part of the USBHOST module has | |
1639 | * entered the standby state, and SW has cut the functional clocks) | |
1640 | * - an USBHOST interrupt occurs before the module is able to answer | |
1641 | * idle_ack, typically a remote wakeup IRQ. | |
1642 | * Then the USB HOST module will enter a deadlock situation where it | |
1643 | * is no more accessible nor functional. | |
1644 | * | |
1645 | * Workaround: | |
1646 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
1647 | */ | |
1648 | ||
1649 | /* | |
1650 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
1651 | * Id: i571 | |
1652 | * | |
1653 | * Description: | |
1654 | * When the USBHOST module is set to smart-standby mode, and when it is | |
1655 | * ready to enter the standby state (i.e. all ports are suspended and | |
1656 | * all attached devices are in suspend mode), then it can wrongly assert | |
1657 | * the Mstandby signal too early while there are still some residual OCP | |
1658 | * transactions ongoing. If this condition occurs, the internal state | |
1659 | * machine may go to an undefined state and the USB link may be stuck | |
1660 | * upon the next resume. | |
1661 | * | |
1662 | * Workaround: | |
1663 | * Don't use smart standby; use only force standby, | |
1664 | * hence HWMOD_SWSUP_MSTANDBY | |
1665 | */ | |
1666 | ||
b483a4a5 | 1667 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
e01478b0 RQ |
1668 | .main_clk = "l3init_60m_fclk", |
1669 | .prcm = { | |
1670 | .omap4 = { | |
1671 | .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET, | |
1672 | .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET, | |
1673 | .modulemode = MODULEMODE_SWCTRL, | |
1674 | }, | |
1675 | }, | |
1676 | }; | |
1677 | ||
1678 | /* | |
1679 | * 'usb_tll_hs' class | |
1680 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
1681 | */ | |
1682 | ||
1683 | static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = { | |
1684 | .rev_offs = 0x0000, | |
1685 | .sysc_offs = 0x0010, | |
1686 | .syss_offs = 0x0014, | |
1687 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1688 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
1689 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1690 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1691 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1692 | }; | |
1693 | ||
1694 | static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = { | |
1695 | .name = "usb_tll_hs", | |
1696 | .sysc = &omap54xx_usb_tll_hs_sysc, | |
1697 | }; | |
1698 | ||
1699 | static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = { | |
1700 | .name = "usb_tll_hs", | |
1701 | .class = &omap54xx_usb_tll_hs_hwmod_class, | |
1702 | .clkdm_name = "l3init_clkdm", | |
1703 | .main_clk = "l4_root_clk_div", | |
1704 | .prcm = { | |
1705 | .omap4 = { | |
1706 | .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET, | |
1707 | .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET, | |
1708 | .modulemode = MODULEMODE_HWCTRL, | |
1709 | }, | |
1710 | }, | |
1711 | }; | |
1712 | ||
08e4830d BC |
1713 | /* |
1714 | * 'usb_otg_ss' class | |
1715 | * 2.0 super speed (usb_otg_ss) controller | |
1716 | */ | |
1717 | ||
1718 | static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = { | |
1719 | .rev_offs = 0x0000, | |
1720 | .sysc_offs = 0x0010, | |
1721 | .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE | | |
1722 | SYSC_HAS_SIDLEMODE), | |
1723 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1724 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
1725 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
1726 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1727 | }; | |
1728 | ||
1729 | static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = { | |
1730 | .name = "usb_otg_ss", | |
1731 | .sysc = &omap54xx_usb_otg_ss_sysc, | |
1732 | }; | |
1733 | ||
1734 | /* usb_otg_ss */ | |
1735 | static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = { | |
1736 | { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" }, | |
1737 | }; | |
1738 | ||
1739 | static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = { | |
1740 | .name = "usb_otg_ss", | |
1741 | .class = &omap54xx_usb_otg_ss_hwmod_class, | |
1742 | .clkdm_name = "l3init_clkdm", | |
1743 | .flags = HWMOD_SWSUP_SIDLE, | |
1744 | .main_clk = "dpll_core_h13x2_ck", | |
1745 | .prcm = { | |
1746 | .omap4 = { | |
1747 | .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET, | |
1748 | .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET, | |
1749 | .modulemode = MODULEMODE_HWCTRL, | |
1750 | }, | |
1751 | }, | |
1752 | .opt_clks = usb_otg_ss_opt_clks, | |
1753 | .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks), | |
1754 | }; | |
1755 | ||
1756 | /* | |
1757 | * 'wd_timer' class | |
1758 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
1759 | * overflow condition | |
1760 | */ | |
1761 | ||
1762 | static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = { | |
1763 | .rev_offs = 0x0000, | |
1764 | .sysc_offs = 0x0010, | |
1765 | .syss_offs = 0x0014, | |
1766 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
1767 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1768 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1769 | SIDLE_SMART_WKUP), | |
1770 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1771 | }; | |
1772 | ||
1773 | static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = { | |
1774 | .name = "wd_timer", | |
1775 | .sysc = &omap54xx_wd_timer_sysc, | |
1776 | .pre_shutdown = &omap2_wd_timer_disable, | |
1777 | }; | |
1778 | ||
1779 | /* wd_timer2 */ | |
1780 | static struct omap_hwmod omap54xx_wd_timer2_hwmod = { | |
1781 | .name = "wd_timer2", | |
1782 | .class = &omap54xx_wd_timer_hwmod_class, | |
1783 | .clkdm_name = "wkupaon_clkdm", | |
1784 | .main_clk = "sys_32k_ck", | |
1785 | .prcm = { | |
1786 | .omap4 = { | |
1787 | .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET, | |
1788 | .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET, | |
1789 | .modulemode = MODULEMODE_SWCTRL, | |
1790 | }, | |
1791 | }, | |
1792 | }; | |
1793 | ||
1794 | ||
1795 | /* | |
1796 | * Interfaces | |
1797 | */ | |
1798 | ||
1799 | /* l3_main_1 -> dmm */ | |
1800 | static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = { | |
1801 | .master = &omap54xx_l3_main_1_hwmod, | |
1802 | .slave = &omap54xx_dmm_hwmod, | |
1803 | .clk = "l3_iclk_div", | |
1804 | .user = OCP_USER_SDMA, | |
1805 | }; | |
1806 | ||
1807 | /* l3_main_3 -> l3_instr */ | |
1808 | static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = { | |
1809 | .master = &omap54xx_l3_main_3_hwmod, | |
1810 | .slave = &omap54xx_l3_instr_hwmod, | |
1811 | .clk = "l3_iclk_div", | |
1812 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1813 | }; | |
1814 | ||
1815 | /* l3_main_2 -> l3_main_1 */ | |
1816 | static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = { | |
1817 | .master = &omap54xx_l3_main_2_hwmod, | |
1818 | .slave = &omap54xx_l3_main_1_hwmod, | |
1819 | .clk = "l3_iclk_div", | |
1820 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1821 | }; | |
1822 | ||
1823 | /* l4_cfg -> l3_main_1 */ | |
1824 | static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = { | |
1825 | .master = &omap54xx_l4_cfg_hwmod, | |
1826 | .slave = &omap54xx_l3_main_1_hwmod, | |
1827 | .clk = "l3_iclk_div", | |
1828 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1829 | }; | |
1830 | ||
1528ed04 SA |
1831 | /* l4_cfg -> mmu_dsp */ |
1832 | static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = { | |
1833 | .master = &omap54xx_l4_cfg_hwmod, | |
1834 | .slave = &omap54xx_mmu_dsp_hwmod, | |
1835 | .clk = "l4_root_clk_div", | |
1836 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1837 | }; | |
1838 | ||
08e4830d BC |
1839 | /* mpu -> l3_main_1 */ |
1840 | static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = { | |
1841 | .master = &omap54xx_mpu_hwmod, | |
1842 | .slave = &omap54xx_l3_main_1_hwmod, | |
1843 | .clk = "l3_iclk_div", | |
1844 | .user = OCP_USER_MPU, | |
1845 | }; | |
1846 | ||
1847 | /* l3_main_1 -> l3_main_2 */ | |
1848 | static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = { | |
1849 | .master = &omap54xx_l3_main_1_hwmod, | |
1850 | .slave = &omap54xx_l3_main_2_hwmod, | |
1851 | .clk = "l3_iclk_div", | |
1852 | .user = OCP_USER_MPU, | |
1853 | }; | |
1854 | ||
1855 | /* l4_cfg -> l3_main_2 */ | |
1856 | static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = { | |
1857 | .master = &omap54xx_l4_cfg_hwmod, | |
1858 | .slave = &omap54xx_l3_main_2_hwmod, | |
1859 | .clk = "l3_iclk_div", | |
1860 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1861 | }; | |
1862 | ||
1528ed04 SA |
1863 | /* l3_main_2 -> mmu_ipu */ |
1864 | static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = { | |
1865 | .master = &omap54xx_l3_main_2_hwmod, | |
1866 | .slave = &omap54xx_mmu_ipu_hwmod, | |
1867 | .clk = "l3_iclk_div", | |
1868 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1869 | }; | |
1870 | ||
08e4830d BC |
1871 | /* l3_main_1 -> l3_main_3 */ |
1872 | static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = { | |
1873 | .master = &omap54xx_l3_main_1_hwmod, | |
1874 | .slave = &omap54xx_l3_main_3_hwmod, | |
1875 | .clk = "l3_iclk_div", | |
1876 | .user = OCP_USER_MPU, | |
1877 | }; | |
1878 | ||
1879 | /* l3_main_2 -> l3_main_3 */ | |
1880 | static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = { | |
1881 | .master = &omap54xx_l3_main_2_hwmod, | |
1882 | .slave = &omap54xx_l3_main_3_hwmod, | |
1883 | .clk = "l3_iclk_div", | |
1884 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1885 | }; | |
1886 | ||
1887 | /* l4_cfg -> l3_main_3 */ | |
1888 | static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = { | |
1889 | .master = &omap54xx_l4_cfg_hwmod, | |
1890 | .slave = &omap54xx_l3_main_3_hwmod, | |
1891 | .clk = "l3_iclk_div", | |
1892 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1893 | }; | |
1894 | ||
1895 | /* l3_main_1 -> l4_abe */ | |
1896 | static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = { | |
1897 | .master = &omap54xx_l3_main_1_hwmod, | |
1898 | .slave = &omap54xx_l4_abe_hwmod, | |
1899 | .clk = "abe_iclk", | |
1900 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1901 | }; | |
1902 | ||
1903 | /* mpu -> l4_abe */ | |
1904 | static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = { | |
1905 | .master = &omap54xx_mpu_hwmod, | |
1906 | .slave = &omap54xx_l4_abe_hwmod, | |
1907 | .clk = "abe_iclk", | |
1908 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1909 | }; | |
1910 | ||
1911 | /* l3_main_1 -> l4_cfg */ | |
1912 | static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = { | |
1913 | .master = &omap54xx_l3_main_1_hwmod, | |
1914 | .slave = &omap54xx_l4_cfg_hwmod, | |
1915 | .clk = "l4_root_clk_div", | |
1916 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1917 | }; | |
1918 | ||
1919 | /* l3_main_2 -> l4_per */ | |
1920 | static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = { | |
1921 | .master = &omap54xx_l3_main_2_hwmod, | |
1922 | .slave = &omap54xx_l4_per_hwmod, | |
1923 | .clk = "l4_root_clk_div", | |
1924 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1925 | }; | |
1926 | ||
1927 | /* l3_main_1 -> l4_wkup */ | |
1928 | static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = { | |
1929 | .master = &omap54xx_l3_main_1_hwmod, | |
1930 | .slave = &omap54xx_l4_wkup_hwmod, | |
1931 | .clk = "wkupaon_iclk_mux", | |
1932 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1933 | }; | |
1934 | ||
1935 | /* mpu -> mpu_private */ | |
1936 | static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = { | |
1937 | .master = &omap54xx_mpu_hwmod, | |
1938 | .slave = &omap54xx_mpu_private_hwmod, | |
1939 | .clk = "l3_iclk_div", | |
1940 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1941 | }; | |
1942 | ||
1943 | /* l4_wkup -> counter_32k */ | |
1944 | static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = { | |
1945 | .master = &omap54xx_l4_wkup_hwmod, | |
1946 | .slave = &omap54xx_counter_32k_hwmod, | |
1947 | .clk = "wkupaon_iclk_mux", | |
1948 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1949 | }; | |
1950 | ||
1951 | static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = { | |
1952 | { | |
1953 | .pa_start = 0x4a056000, | |
1954 | .pa_end = 0x4a056fff, | |
1955 | .flags = ADDR_TYPE_RT | |
1956 | }, | |
1957 | { } | |
1958 | }; | |
1959 | ||
1960 | /* l4_cfg -> dma_system */ | |
1961 | static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = { | |
1962 | .master = &omap54xx_l4_cfg_hwmod, | |
1963 | .slave = &omap54xx_dma_system_hwmod, | |
1964 | .clk = "l4_root_clk_div", | |
1965 | .addr = omap54xx_dma_system_addrs, | |
1966 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1967 | }; | |
1968 | ||
1969 | /* l4_abe -> dmic */ | |
1970 | static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = { | |
1971 | .master = &omap54xx_l4_abe_hwmod, | |
1972 | .slave = &omap54xx_dmic_hwmod, | |
1973 | .clk = "abe_iclk", | |
1974 | .user = OCP_USER_MPU, | |
1975 | }; | |
1976 | ||
1977 | /* mpu -> emif1 */ | |
1978 | static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = { | |
1979 | .master = &omap54xx_mpu_hwmod, | |
1980 | .slave = &omap54xx_emif1_hwmod, | |
1981 | .clk = "dpll_core_h11x2_ck", | |
1982 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1983 | }; | |
1984 | ||
1985 | /* mpu -> emif2 */ | |
1986 | static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = { | |
1987 | .master = &omap54xx_mpu_hwmod, | |
1988 | .slave = &omap54xx_emif2_hwmod, | |
1989 | .clk = "dpll_core_h11x2_ck", | |
1990 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1991 | }; | |
1992 | ||
1993 | /* l4_wkup -> gpio1 */ | |
1994 | static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = { | |
1995 | .master = &omap54xx_l4_wkup_hwmod, | |
1996 | .slave = &omap54xx_gpio1_hwmod, | |
1997 | .clk = "wkupaon_iclk_mux", | |
1998 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1999 | }; | |
2000 | ||
2001 | /* l4_per -> gpio2 */ | |
2002 | static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = { | |
2003 | .master = &omap54xx_l4_per_hwmod, | |
2004 | .slave = &omap54xx_gpio2_hwmod, | |
2005 | .clk = "l4_root_clk_div", | |
2006 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2007 | }; | |
2008 | ||
2009 | /* l4_per -> gpio3 */ | |
2010 | static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = { | |
2011 | .master = &omap54xx_l4_per_hwmod, | |
2012 | .slave = &omap54xx_gpio3_hwmod, | |
2013 | .clk = "l4_root_clk_div", | |
2014 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2015 | }; | |
2016 | ||
2017 | /* l4_per -> gpio4 */ | |
2018 | static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = { | |
2019 | .master = &omap54xx_l4_per_hwmod, | |
2020 | .slave = &omap54xx_gpio4_hwmod, | |
2021 | .clk = "l4_root_clk_div", | |
2022 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2023 | }; | |
2024 | ||
2025 | /* l4_per -> gpio5 */ | |
2026 | static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = { | |
2027 | .master = &omap54xx_l4_per_hwmod, | |
2028 | .slave = &omap54xx_gpio5_hwmod, | |
2029 | .clk = "l4_root_clk_div", | |
2030 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2031 | }; | |
2032 | ||
2033 | /* l4_per -> gpio6 */ | |
2034 | static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = { | |
2035 | .master = &omap54xx_l4_per_hwmod, | |
2036 | .slave = &omap54xx_gpio6_hwmod, | |
2037 | .clk = "l4_root_clk_div", | |
2038 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2039 | }; | |
2040 | ||
2041 | /* l4_per -> gpio7 */ | |
2042 | static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = { | |
2043 | .master = &omap54xx_l4_per_hwmod, | |
2044 | .slave = &omap54xx_gpio7_hwmod, | |
2045 | .clk = "l4_root_clk_div", | |
2046 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2047 | }; | |
2048 | ||
2049 | /* l4_per -> gpio8 */ | |
2050 | static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = { | |
2051 | .master = &omap54xx_l4_per_hwmod, | |
2052 | .slave = &omap54xx_gpio8_hwmod, | |
2053 | .clk = "l4_root_clk_div", | |
2054 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2055 | }; | |
2056 | ||
2057 | /* l4_per -> i2c1 */ | |
2058 | static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = { | |
2059 | .master = &omap54xx_l4_per_hwmod, | |
2060 | .slave = &omap54xx_i2c1_hwmod, | |
2061 | .clk = "l4_root_clk_div", | |
2062 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2063 | }; | |
2064 | ||
2065 | /* l4_per -> i2c2 */ | |
2066 | static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = { | |
2067 | .master = &omap54xx_l4_per_hwmod, | |
2068 | .slave = &omap54xx_i2c2_hwmod, | |
2069 | .clk = "l4_root_clk_div", | |
2070 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2071 | }; | |
2072 | ||
2073 | /* l4_per -> i2c3 */ | |
2074 | static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = { | |
2075 | .master = &omap54xx_l4_per_hwmod, | |
2076 | .slave = &omap54xx_i2c3_hwmod, | |
2077 | .clk = "l4_root_clk_div", | |
2078 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2079 | }; | |
2080 | ||
2081 | /* l4_per -> i2c4 */ | |
2082 | static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = { | |
2083 | .master = &omap54xx_l4_per_hwmod, | |
2084 | .slave = &omap54xx_i2c4_hwmod, | |
2085 | .clk = "l4_root_clk_div", | |
2086 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2087 | }; | |
2088 | ||
2089 | /* l4_per -> i2c5 */ | |
2090 | static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = { | |
2091 | .master = &omap54xx_l4_per_hwmod, | |
2092 | .slave = &omap54xx_i2c5_hwmod, | |
2093 | .clk = "l4_root_clk_div", | |
2094 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2095 | }; | |
2096 | ||
2097 | /* l4_wkup -> kbd */ | |
2098 | static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = { | |
2099 | .master = &omap54xx_l4_wkup_hwmod, | |
2100 | .slave = &omap54xx_kbd_hwmod, | |
2101 | .clk = "wkupaon_iclk_mux", | |
2102 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2103 | }; | |
2104 | ||
03ab349e SA |
2105 | /* l4_cfg -> mailbox */ |
2106 | static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = { | |
2107 | .master = &omap54xx_l4_cfg_hwmod, | |
2108 | .slave = &omap54xx_mailbox_hwmod, | |
2109 | .clk = "l4_root_clk_div", | |
2110 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2111 | }; | |
2112 | ||
08e4830d BC |
2113 | /* l4_abe -> mcbsp1 */ |
2114 | static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = { | |
2115 | .master = &omap54xx_l4_abe_hwmod, | |
2116 | .slave = &omap54xx_mcbsp1_hwmod, | |
2117 | .clk = "abe_iclk", | |
2118 | .user = OCP_USER_MPU, | |
2119 | }; | |
2120 | ||
2121 | /* l4_abe -> mcbsp2 */ | |
2122 | static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = { | |
2123 | .master = &omap54xx_l4_abe_hwmod, | |
2124 | .slave = &omap54xx_mcbsp2_hwmod, | |
2125 | .clk = "abe_iclk", | |
2126 | .user = OCP_USER_MPU, | |
2127 | }; | |
2128 | ||
2129 | /* l4_abe -> mcbsp3 */ | |
2130 | static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = { | |
2131 | .master = &omap54xx_l4_abe_hwmod, | |
2132 | .slave = &omap54xx_mcbsp3_hwmod, | |
2133 | .clk = "abe_iclk", | |
2134 | .user = OCP_USER_MPU, | |
2135 | }; | |
2136 | ||
2137 | /* l4_abe -> mcpdm */ | |
2138 | static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = { | |
2139 | .master = &omap54xx_l4_abe_hwmod, | |
2140 | .slave = &omap54xx_mcpdm_hwmod, | |
2141 | .clk = "abe_iclk", | |
2142 | .user = OCP_USER_MPU, | |
2143 | }; | |
2144 | ||
2145 | /* l4_per -> mcspi1 */ | |
2146 | static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = { | |
2147 | .master = &omap54xx_l4_per_hwmod, | |
2148 | .slave = &omap54xx_mcspi1_hwmod, | |
2149 | .clk = "l4_root_clk_div", | |
2150 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2151 | }; | |
2152 | ||
2153 | /* l4_per -> mcspi2 */ | |
2154 | static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = { | |
2155 | .master = &omap54xx_l4_per_hwmod, | |
2156 | .slave = &omap54xx_mcspi2_hwmod, | |
2157 | .clk = "l4_root_clk_div", | |
2158 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2159 | }; | |
2160 | ||
2161 | /* l4_per -> mcspi3 */ | |
2162 | static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = { | |
2163 | .master = &omap54xx_l4_per_hwmod, | |
2164 | .slave = &omap54xx_mcspi3_hwmod, | |
2165 | .clk = "l4_root_clk_div", | |
2166 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2167 | }; | |
2168 | ||
2169 | /* l4_per -> mcspi4 */ | |
2170 | static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = { | |
2171 | .master = &omap54xx_l4_per_hwmod, | |
2172 | .slave = &omap54xx_mcspi4_hwmod, | |
2173 | .clk = "l4_root_clk_div", | |
2174 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2175 | }; | |
2176 | ||
2177 | /* l4_per -> mmc1 */ | |
2178 | static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = { | |
2179 | .master = &omap54xx_l4_per_hwmod, | |
2180 | .slave = &omap54xx_mmc1_hwmod, | |
2181 | .clk = "l3_iclk_div", | |
2182 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2183 | }; | |
2184 | ||
2185 | /* l4_per -> mmc2 */ | |
2186 | static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = { | |
2187 | .master = &omap54xx_l4_per_hwmod, | |
2188 | .slave = &omap54xx_mmc2_hwmod, | |
2189 | .clk = "l3_iclk_div", | |
2190 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2191 | }; | |
2192 | ||
2193 | /* l4_per -> mmc3 */ | |
2194 | static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = { | |
2195 | .master = &omap54xx_l4_per_hwmod, | |
2196 | .slave = &omap54xx_mmc3_hwmod, | |
2197 | .clk = "l4_root_clk_div", | |
2198 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2199 | }; | |
2200 | ||
2201 | /* l4_per -> mmc4 */ | |
2202 | static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = { | |
2203 | .master = &omap54xx_l4_per_hwmod, | |
2204 | .slave = &omap54xx_mmc4_hwmod, | |
2205 | .clk = "l4_root_clk_div", | |
2206 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2207 | }; | |
2208 | ||
2209 | /* l4_per -> mmc5 */ | |
2210 | static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = { | |
2211 | .master = &omap54xx_l4_per_hwmod, | |
2212 | .slave = &omap54xx_mmc5_hwmod, | |
2213 | .clk = "l4_root_clk_div", | |
2214 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2215 | }; | |
2216 | ||
2217 | /* l4_cfg -> mpu */ | |
2218 | static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = { | |
2219 | .master = &omap54xx_l4_cfg_hwmod, | |
2220 | .slave = &omap54xx_mpu_hwmod, | |
2221 | .clk = "l4_root_clk_div", | |
2222 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2223 | }; | |
2224 | ||
325529d1 SA |
2225 | /* l4_cfg -> spinlock */ |
2226 | static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = { | |
2227 | .master = &omap54xx_l4_cfg_hwmod, | |
2228 | .slave = &omap54xx_spinlock_hwmod, | |
2229 | .clk = "l4_root_clk_div", | |
2230 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2231 | }; | |
2232 | ||
254f57a9 BC |
2233 | /* l4_cfg -> ocp2scp1 */ |
2234 | static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = { | |
2235 | .master = &omap54xx_l4_cfg_hwmod, | |
2236 | .slave = &omap54xx_ocp2scp1_hwmod, | |
2237 | .clk = "l4_root_clk_div", | |
2238 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2239 | }; | |
2240 | ||
08e4830d BC |
2241 | /* l4_wkup -> timer1 */ |
2242 | static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = { | |
2243 | .master = &omap54xx_l4_wkup_hwmod, | |
2244 | .slave = &omap54xx_timer1_hwmod, | |
2245 | .clk = "wkupaon_iclk_mux", | |
2246 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2247 | }; | |
2248 | ||
2249 | /* l4_per -> timer2 */ | |
2250 | static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = { | |
2251 | .master = &omap54xx_l4_per_hwmod, | |
2252 | .slave = &omap54xx_timer2_hwmod, | |
2253 | .clk = "l4_root_clk_div", | |
2254 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2255 | }; | |
2256 | ||
2257 | /* l4_per -> timer3 */ | |
2258 | static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = { | |
2259 | .master = &omap54xx_l4_per_hwmod, | |
2260 | .slave = &omap54xx_timer3_hwmod, | |
2261 | .clk = "l4_root_clk_div", | |
2262 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2263 | }; | |
2264 | ||
2265 | /* l4_per -> timer4 */ | |
2266 | static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = { | |
2267 | .master = &omap54xx_l4_per_hwmod, | |
2268 | .slave = &omap54xx_timer4_hwmod, | |
2269 | .clk = "l4_root_clk_div", | |
2270 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2271 | }; | |
2272 | ||
2273 | /* l4_abe -> timer5 */ | |
2274 | static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = { | |
2275 | .master = &omap54xx_l4_abe_hwmod, | |
2276 | .slave = &omap54xx_timer5_hwmod, | |
2277 | .clk = "abe_iclk", | |
2278 | .user = OCP_USER_MPU, | |
2279 | }; | |
2280 | ||
2281 | /* l4_abe -> timer6 */ | |
2282 | static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = { | |
2283 | .master = &omap54xx_l4_abe_hwmod, | |
2284 | .slave = &omap54xx_timer6_hwmod, | |
2285 | .clk = "abe_iclk", | |
2286 | .user = OCP_USER_MPU, | |
2287 | }; | |
2288 | ||
2289 | /* l4_abe -> timer7 */ | |
2290 | static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = { | |
2291 | .master = &omap54xx_l4_abe_hwmod, | |
2292 | .slave = &omap54xx_timer7_hwmod, | |
2293 | .clk = "abe_iclk", | |
2294 | .user = OCP_USER_MPU, | |
2295 | }; | |
2296 | ||
2297 | /* l4_abe -> timer8 */ | |
2298 | static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = { | |
2299 | .master = &omap54xx_l4_abe_hwmod, | |
2300 | .slave = &omap54xx_timer8_hwmod, | |
2301 | .clk = "abe_iclk", | |
2302 | .user = OCP_USER_MPU, | |
2303 | }; | |
2304 | ||
2305 | /* l4_per -> timer9 */ | |
2306 | static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = { | |
2307 | .master = &omap54xx_l4_per_hwmod, | |
2308 | .slave = &omap54xx_timer9_hwmod, | |
2309 | .clk = "l4_root_clk_div", | |
2310 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2311 | }; | |
2312 | ||
2313 | /* l4_per -> timer10 */ | |
2314 | static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = { | |
2315 | .master = &omap54xx_l4_per_hwmod, | |
2316 | .slave = &omap54xx_timer10_hwmod, | |
2317 | .clk = "l4_root_clk_div", | |
2318 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2319 | }; | |
2320 | ||
2321 | /* l4_per -> timer11 */ | |
2322 | static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = { | |
2323 | .master = &omap54xx_l4_per_hwmod, | |
2324 | .slave = &omap54xx_timer11_hwmod, | |
2325 | .clk = "l4_root_clk_div", | |
2326 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2327 | }; | |
2328 | ||
2329 | /* l4_per -> uart1 */ | |
2330 | static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = { | |
2331 | .master = &omap54xx_l4_per_hwmod, | |
2332 | .slave = &omap54xx_uart1_hwmod, | |
2333 | .clk = "l4_root_clk_div", | |
2334 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2335 | }; | |
2336 | ||
2337 | /* l4_per -> uart2 */ | |
2338 | static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = { | |
2339 | .master = &omap54xx_l4_per_hwmod, | |
2340 | .slave = &omap54xx_uart2_hwmod, | |
2341 | .clk = "l4_root_clk_div", | |
2342 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2343 | }; | |
2344 | ||
2345 | /* l4_per -> uart3 */ | |
2346 | static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = { | |
2347 | .master = &omap54xx_l4_per_hwmod, | |
2348 | .slave = &omap54xx_uart3_hwmod, | |
2349 | .clk = "l4_root_clk_div", | |
2350 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2351 | }; | |
2352 | ||
2353 | /* l4_per -> uart4 */ | |
2354 | static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = { | |
2355 | .master = &omap54xx_l4_per_hwmod, | |
2356 | .slave = &omap54xx_uart4_hwmod, | |
2357 | .clk = "l4_root_clk_div", | |
2358 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2359 | }; | |
2360 | ||
2361 | /* l4_per -> uart5 */ | |
2362 | static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = { | |
2363 | .master = &omap54xx_l4_per_hwmod, | |
2364 | .slave = &omap54xx_uart5_hwmod, | |
2365 | .clk = "l4_root_clk_div", | |
2366 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2367 | }; | |
2368 | ||
2369 | /* l4_per -> uart6 */ | |
2370 | static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = { | |
2371 | .master = &omap54xx_l4_per_hwmod, | |
2372 | .slave = &omap54xx_uart6_hwmod, | |
2373 | .clk = "l4_root_clk_div", | |
2374 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2375 | }; | |
2376 | ||
e01478b0 RQ |
2377 | /* l4_cfg -> usb_host_hs */ |
2378 | static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = { | |
2379 | .master = &omap54xx_l4_cfg_hwmod, | |
2380 | .slave = &omap54xx_usb_host_hs_hwmod, | |
2381 | .clk = "l3_iclk_div", | |
2382 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2383 | }; | |
2384 | ||
2385 | /* l4_cfg -> usb_tll_hs */ | |
2386 | static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = { | |
2387 | .master = &omap54xx_l4_cfg_hwmod, | |
2388 | .slave = &omap54xx_usb_tll_hs_hwmod, | |
2389 | .clk = "l4_root_clk_div", | |
2390 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2391 | }; | |
2392 | ||
08e4830d BC |
2393 | /* l4_cfg -> usb_otg_ss */ |
2394 | static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = { | |
2395 | .master = &omap54xx_l4_cfg_hwmod, | |
2396 | .slave = &omap54xx_usb_otg_ss_hwmod, | |
2397 | .clk = "dpll_core_h13x2_ck", | |
2398 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2399 | }; | |
2400 | ||
2401 | /* l4_wkup -> wd_timer2 */ | |
2402 | static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = { | |
2403 | .master = &omap54xx_l4_wkup_hwmod, | |
2404 | .slave = &omap54xx_wd_timer2_hwmod, | |
2405 | .clk = "wkupaon_iclk_mux", | |
2406 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2407 | }; | |
2408 | ||
2409 | static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { | |
2410 | &omap54xx_l3_main_1__dmm, | |
2411 | &omap54xx_l3_main_3__l3_instr, | |
2412 | &omap54xx_l3_main_2__l3_main_1, | |
2413 | &omap54xx_l4_cfg__l3_main_1, | |
2414 | &omap54xx_mpu__l3_main_1, | |
2415 | &omap54xx_l3_main_1__l3_main_2, | |
2416 | &omap54xx_l4_cfg__l3_main_2, | |
2417 | &omap54xx_l3_main_1__l3_main_3, | |
2418 | &omap54xx_l3_main_2__l3_main_3, | |
2419 | &omap54xx_l4_cfg__l3_main_3, | |
2420 | &omap54xx_l3_main_1__l4_abe, | |
2421 | &omap54xx_mpu__l4_abe, | |
2422 | &omap54xx_l3_main_1__l4_cfg, | |
2423 | &omap54xx_l3_main_2__l4_per, | |
2424 | &omap54xx_l3_main_1__l4_wkup, | |
2425 | &omap54xx_mpu__mpu_private, | |
2426 | &omap54xx_l4_wkup__counter_32k, | |
2427 | &omap54xx_l4_cfg__dma_system, | |
2428 | &omap54xx_l4_abe__dmic, | |
1528ed04 | 2429 | &omap54xx_l4_cfg__mmu_dsp, |
08e4830d BC |
2430 | &omap54xx_mpu__emif1, |
2431 | &omap54xx_mpu__emif2, | |
2432 | &omap54xx_l4_wkup__gpio1, | |
2433 | &omap54xx_l4_per__gpio2, | |
2434 | &omap54xx_l4_per__gpio3, | |
2435 | &omap54xx_l4_per__gpio4, | |
2436 | &omap54xx_l4_per__gpio5, | |
2437 | &omap54xx_l4_per__gpio6, | |
2438 | &omap54xx_l4_per__gpio7, | |
2439 | &omap54xx_l4_per__gpio8, | |
2440 | &omap54xx_l4_per__i2c1, | |
2441 | &omap54xx_l4_per__i2c2, | |
2442 | &omap54xx_l4_per__i2c3, | |
2443 | &omap54xx_l4_per__i2c4, | |
2444 | &omap54xx_l4_per__i2c5, | |
1528ed04 | 2445 | &omap54xx_l3_main_2__mmu_ipu, |
08e4830d | 2446 | &omap54xx_l4_wkup__kbd, |
03ab349e | 2447 | &omap54xx_l4_cfg__mailbox, |
08e4830d BC |
2448 | &omap54xx_l4_abe__mcbsp1, |
2449 | &omap54xx_l4_abe__mcbsp2, | |
2450 | &omap54xx_l4_abe__mcbsp3, | |
2451 | &omap54xx_l4_abe__mcpdm, | |
2452 | &omap54xx_l4_per__mcspi1, | |
2453 | &omap54xx_l4_per__mcspi2, | |
2454 | &omap54xx_l4_per__mcspi3, | |
2455 | &omap54xx_l4_per__mcspi4, | |
2456 | &omap54xx_l4_per__mmc1, | |
2457 | &omap54xx_l4_per__mmc2, | |
2458 | &omap54xx_l4_per__mmc3, | |
2459 | &omap54xx_l4_per__mmc4, | |
2460 | &omap54xx_l4_per__mmc5, | |
2461 | &omap54xx_l4_cfg__mpu, | |
325529d1 | 2462 | &omap54xx_l4_cfg__spinlock, |
254f57a9 | 2463 | &omap54xx_l4_cfg__ocp2scp1, |
08e4830d BC |
2464 | &omap54xx_l4_wkup__timer1, |
2465 | &omap54xx_l4_per__timer2, | |
2466 | &omap54xx_l4_per__timer3, | |
2467 | &omap54xx_l4_per__timer4, | |
2468 | &omap54xx_l4_abe__timer5, | |
2469 | &omap54xx_l4_abe__timer6, | |
2470 | &omap54xx_l4_abe__timer7, | |
2471 | &omap54xx_l4_abe__timer8, | |
2472 | &omap54xx_l4_per__timer9, | |
2473 | &omap54xx_l4_per__timer10, | |
2474 | &omap54xx_l4_per__timer11, | |
2475 | &omap54xx_l4_per__uart1, | |
2476 | &omap54xx_l4_per__uart2, | |
2477 | &omap54xx_l4_per__uart3, | |
2478 | &omap54xx_l4_per__uart4, | |
2479 | &omap54xx_l4_per__uart5, | |
2480 | &omap54xx_l4_per__uart6, | |
e01478b0 RQ |
2481 | &omap54xx_l4_cfg__usb_host_hs, |
2482 | &omap54xx_l4_cfg__usb_tll_hs, | |
08e4830d BC |
2483 | &omap54xx_l4_cfg__usb_otg_ss, |
2484 | &omap54xx_l4_wkup__wd_timer2, | |
2485 | NULL, | |
2486 | }; | |
2487 | ||
2488 | int __init omap54xx_hwmod_init(void) | |
2489 | { | |
2490 | omap_hwmod_init(); | |
2491 | return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs); | |
2492 | } |