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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_7xx_data.c
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90020c7b
A		 1/*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/io.h>
21#include <linux/platform_data/gpio-omap.h>
22#include <linux/power/smartreflex.h>
23#include <linux/i2c-omap.h>
24
25#include <linux/omap-dma.h>
26#include <linux/platform_data/spi-omap2-mcspi.h>
27#include <linux/platform_data/asoc-ti-mcbsp.h>
28#include <plat/dmtimer.h>
29
30#include "omap_hwmod.h"
31#include "omap_hwmod_common_data.h"
32#include "cm1_7xx.h"
33#include "cm2_7xx.h"
34#include "prm7xx.h"
35#include "i2c.h"
36#include "mmc.h"
37#include "wd_timer.h"
38
39/* Base offset for all DRA7XX interrupts external to MPUSS */
40#define DRA7XX_IRQ_GIC_START 32
41
42/* Base offset for all DRA7XX dma requests */
43#define DRA7XX_DMA_REQ_START 1
44
45
46/*
47 * IP blocks
48 */
49
50/*
51 * 'l3' class
52 * instance(s): l3_instr, l3_main_1, l3_main_2
53 */
54static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
55 .name = "l3",
56};
57
58/* l3_instr */
59static struct omap_hwmod dra7xx_l3_instr_hwmod = {
60 .name = "l3_instr",
61 .class = &dra7xx_l3_hwmod_class,
62 .clkdm_name = "l3instr_clkdm",
63 .prcm = {
64 .omap4 = {
65 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
66 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
67 .modulemode = MODULEMODE_HWCTRL,
68 },
69 },
70};
71
72/* l3_main_1 */
73static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
74 .name = "l3_main_1",
75 .class = &dra7xx_l3_hwmod_class,
76 .clkdm_name = "l3main1_clkdm",
77 .prcm = {
78 .omap4 = {
79 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
80 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
81 },
82 },
83};
84
85/* l3_main_2 */
86static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
87 .name = "l3_main_2",
88 .class = &dra7xx_l3_hwmod_class,
89 .clkdm_name = "l3instr_clkdm",
90 .prcm = {
91 .omap4 = {
92 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
93 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
94 .modulemode = MODULEMODE_HWCTRL,
95 },
96 },
97};
98
99/*
100 * 'l4' class
101 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
102 */
103static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
104 .name = "l4",
105};
106
107/* l4_cfg */
108static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
109 .name = "l4_cfg",
110 .class = &dra7xx_l4_hwmod_class,
111 .clkdm_name = "l4cfg_clkdm",
112 .prcm = {
113 .omap4 = {
114 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
115 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
116 },
117 },
118};
119
120/* l4_per1 */
121static struct omap_hwmod dra7xx_l4_per1_hwmod = {
122 .name = "l4_per1",
123 .class = &dra7xx_l4_hwmod_class,
124 .clkdm_name = "l4per_clkdm",
125 .prcm = {
126 .omap4 = {
127 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
128 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
129 },
130 },
131};
132
133/* l4_per2 */
134static struct omap_hwmod dra7xx_l4_per2_hwmod = {
135 .name = "l4_per2",
136 .class = &dra7xx_l4_hwmod_class,
137 .clkdm_name = "l4per2_clkdm",
138 .prcm = {
139 .omap4 = {
140 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
141 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
142 },
143 },
144};
145
146/* l4_per3 */
147static struct omap_hwmod dra7xx_l4_per3_hwmod = {
148 .name = "l4_per3",
149 .class = &dra7xx_l4_hwmod_class,
150 .clkdm_name = "l4per3_clkdm",
151 .prcm = {
152 .omap4 = {
153 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
154 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
155 },
156 },
157};
158
159/* l4_wkup */
160static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
161 .name = "l4_wkup",
162 .class = &dra7xx_l4_hwmod_class,
163 .clkdm_name = "wkupaon_clkdm",
164 .prcm = {
165 .omap4 = {
166 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
167 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
168 },
169 },
170};
171
172/*
173 * 'atl' class
174 *
175 */
176
177static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
178 .name = "atl",
179};
180
181/* atl */
182static struct omap_hwmod dra7xx_atl_hwmod = {
183 .name = "atl",
184 .class = &dra7xx_atl_hwmod_class,
185 .clkdm_name = "atl_clkdm",
186 .main_clk = "atl_gfclk_mux",
187 .prcm = {
188 .omap4 = {
189 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
190 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
191 .modulemode = MODULEMODE_SWCTRL,
192 },
193 },
194};
195
196/*
197 * 'bb2d' class
198 *
199 */
200
201static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
202 .name = "bb2d",
203};
204
205/* bb2d */
206static struct omap_hwmod dra7xx_bb2d_hwmod = {
207 .name = "bb2d",
208 .class = &dra7xx_bb2d_hwmod_class,
209 .clkdm_name = "dss_clkdm",
210 .main_clk = "dpll_core_h24x2_ck",
211 .prcm = {
212 .omap4 = {
213 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
214 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
215 .modulemode = MODULEMODE_SWCTRL,
216 },
217 },
218};
219
220/*
221 * 'counter' class
222 *
223 */
224
225static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
226 .rev_offs = 0x0000,
227 .sysc_offs = 0x0010,
228 .sysc_flags = SYSC_HAS_SIDLEMODE,
229 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
230 SIDLE_SMART_WKUP),
231 .sysc_fields = &omap_hwmod_sysc_type1,
232};
233
234static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
235 .name = "counter",
236 .sysc = &dra7xx_counter_sysc,
237};
238
239/* counter_32k */
240static struct omap_hwmod dra7xx_counter_32k_hwmod = {
241 .name = "counter_32k",
242 .class = &dra7xx_counter_hwmod_class,
243 .clkdm_name = "wkupaon_clkdm",
244 .flags = HWMOD_SWSUP_SIDLE,
245 .main_clk = "wkupaon_iclk_mux",
246 .prcm = {
247 .omap4 = {
248 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
249 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
250 },
251 },
252};
253
254/*
255 * 'ctrl_module' class
256 *
257 */
258
259static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
260 .name = "ctrl_module",
261};
262
263/* ctrl_module_wkup */
264static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
265 .name = "ctrl_module_wkup",
266 .class = &dra7xx_ctrl_module_hwmod_class,
267 .clkdm_name = "wkupaon_clkdm",
268 .prcm = {
269 .omap4 = {
270 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
271 },
272 },
273};
274
077c42f7
M		 275/*
276 * 'gmac' class
277 * cpsw/gmac sub system
278 */
279static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
280 .rev_offs = 0x0,
281 .sysc_offs = 0x8,
282 .syss_offs = 0x4,
283 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
284 SYSS_HAS_RESET_STATUS),
285 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
286 MSTANDBY_NO),
287 .sysc_fields = &omap_hwmod_sysc_type3,
288};
289
290static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
291 .name = "gmac",
292 .sysc = &dra7xx_gmac_sysc,
293};
294
295static struct omap_hwmod dra7xx_gmac_hwmod = {
296 .name = "gmac",
297 .class = &dra7xx_gmac_hwmod_class,
298 .clkdm_name = "gmac_clkdm",
299 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
300 .main_clk = "dpll_gmac_ck",
301 .mpu_rt_idx = 1,
302 .prcm = {
303 .omap4 = {
304 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
305 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
306 .modulemode = MODULEMODE_SWCTRL,
307 },
308 },
309};
310
311/*
312 * 'mdio' class
313 */
314static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
315 .name = "davinci_mdio",
316};
317
318static struct omap_hwmod dra7xx_mdio_hwmod = {
319 .name = "davinci_mdio",
320 .class = &dra7xx_mdio_hwmod_class,
321 .clkdm_name = "gmac_clkdm",
322 .main_clk = "dpll_gmac_ck",
323};
324
90020c7b
A		 325/*
326 * 'dcan' class
327 *
328 */
329
330static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
331 .name = "dcan",
332};
333
334/* dcan1 */
335static struct omap_hwmod dra7xx_dcan1_hwmod = {
336 .name = "dcan1",
337 .class = &dra7xx_dcan_hwmod_class,
338 .clkdm_name = "wkupaon_clkdm",
339 .main_clk = "dcan1_sys_clk_mux",
340 .prcm = {
341 .omap4 = {
342 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
343 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
344 .modulemode = MODULEMODE_SWCTRL,
345 },
346 },
347};
348
349/* dcan2 */
350static struct omap_hwmod dra7xx_dcan2_hwmod = {
351 .name = "dcan2",
352 .class = &dra7xx_dcan_hwmod_class,
353 .clkdm_name = "l4per2_clkdm",
354 .main_clk = "sys_clkin1",
355 .prcm = {
356 .omap4 = {
357 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
358 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
359 .modulemode = MODULEMODE_SWCTRL,
360 },
361 },
362};
363
364/*
365 * 'dma' class
366 *
367 */
368
369static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
370 .rev_offs = 0x0000,
371 .sysc_offs = 0x002c,
372 .syss_offs = 0x0028,
373 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
374 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
375 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
376 SYSS_HAS_RESET_STATUS),
377 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
378 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
379 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
380 .sysc_fields = &omap_hwmod_sysc_type1,
381};
382
383static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
384 .name = "dma",
385 .sysc = &dra7xx_dma_sysc,
386};
387
388/* dma dev_attr */
389static struct omap_dma_dev_attr dma_dev_attr = {
390 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
391 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
392 .lch_count = 32,
393};
394
395/* dma_system */
90020c7b
A		 396static struct omap_hwmod dra7xx_dma_system_hwmod = {
397 .name = "dma_system",
398 .class = &dra7xx_dma_hwmod_class,
399 .clkdm_name = "dma_clkdm",
90020c7b
A		 400 .main_clk = "l3_iclk_div",
401 .prcm = {
402 .omap4 = {
403 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
404 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
405 },
406 },
407 .dev_attr = &dma_dev_attr,
408};
409
410/*
411 * 'dss' class
412 *
413 */
414
415static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
416 .rev_offs = 0x0000,
417 .syss_offs = 0x0014,
418 .sysc_flags = SYSS_HAS_RESET_STATUS,
419};
420
421static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
422 .name = "dss",
423 .sysc = &dra7xx_dss_sysc,
424 .reset = omap_dss_reset,
425};
426
427/* dss */
428static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
429 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
430 { .dma_req = -1 }
431};
432
433static struct omap_hwmod_opt_clk dss_opt_clks[] = {
434 { .role = "dss_clk", .clk = "dss_dss_clk" },
435 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
436 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
437 { .role = "video2_clk", .clk = "dss_video2_clk" },
438 { .role = "video1_clk", .clk = "dss_video1_clk" },
439 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
440};
441
442static struct omap_hwmod dra7xx_dss_hwmod = {
443 .name = "dss_core",
444 .class = &dra7xx_dss_hwmod_class,
445 .clkdm_name = "dss_clkdm",
446 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
447 .sdma_reqs = dra7xx_dss_sdma_reqs,
448 .main_clk = "dss_dss_clk",
449 .prcm = {
450 .omap4 = {
451 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
452 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
453 .modulemode = MODULEMODE_SWCTRL,
454 },
455 },
456 .opt_clks = dss_opt_clks,
457 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
458};
459
460/*
461 * 'dispc' class
462 * display controller
463 */
464
465static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
466 .rev_offs = 0x0000,
467 .sysc_offs = 0x0010,
468 .syss_offs = 0x0014,
469 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
470 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
471 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
472 SYSS_HAS_RESET_STATUS),
473 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
474 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
475 .sysc_fields = &omap_hwmod_sysc_type1,
476};
477
478static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
479 .name = "dispc",
480 .sysc = &dra7xx_dispc_sysc,
481};
482
483/* dss_dispc */
484/* dss_dispc dev_attr */
485static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
486 .has_framedonetv_irq = 1,
487 .manager_count = 4,
488};
489
490static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
491 .name = "dss_dispc",
492 .class = &dra7xx_dispc_hwmod_class,
493 .clkdm_name = "dss_clkdm",
494 .main_clk = "dss_dss_clk",
495 .prcm = {
496 .omap4 = {
497 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
498 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
499 },
500 },
501 .dev_attr = &dss_dispc_dev_attr,
502};
503
504/*
505 * 'hdmi' class
506 * hdmi controller
507 */
508
509static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
510 .rev_offs = 0x0000,
511 .sysc_offs = 0x0010,
512 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
513 SYSC_HAS_SOFTRESET),
514 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
515 SIDLE_SMART_WKUP),
516 .sysc_fields = &omap_hwmod_sysc_type2,
517};
518
519static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
520 .name = "hdmi",
521 .sysc = &dra7xx_hdmi_sysc,
522};
523
524/* dss_hdmi */
525
526static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
527 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
528};
529
530static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
531 .name = "dss_hdmi",
532 .class = &dra7xx_hdmi_hwmod_class,
533 .clkdm_name = "dss_clkdm",
534 .main_clk = "dss_48mhz_clk",
535 .prcm = {
536 .omap4 = {
537 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
538 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
539 },
540 },
541 .opt_clks = dss_hdmi_opt_clks,
542 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
543};
544
545/*
546 * 'elm' class
547 *
548 */
549
550static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
551 .rev_offs = 0x0000,
552 .sysc_offs = 0x0010,
553 .syss_offs = 0x0014,
554 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
555 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
556 SYSS_HAS_RESET_STATUS),
557 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
558 SIDLE_SMART_WKUP),
559 .sysc_fields = &omap_hwmod_sysc_type1,
560};
561
562static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
563 .name = "elm",
564 .sysc = &dra7xx_elm_sysc,
565};
566
567/* elm */
568
569static struct omap_hwmod dra7xx_elm_hwmod = {
570 .name = "elm",
571 .class = &dra7xx_elm_hwmod_class,
572 .clkdm_name = "l4per_clkdm",
573 .main_clk = "l3_iclk_div",
574 .prcm = {
575 .omap4 = {
576 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
577 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
578 },
579 },
580};
581
582/*
583 * 'gpio' class
584 *
585 */
586
587static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
588 .rev_offs = 0x0000,
589 .sysc_offs = 0x0010,
590 .syss_offs = 0x0114,
591 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
592 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
593 SYSS_HAS_RESET_STATUS),
594 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
595 SIDLE_SMART_WKUP),
596 .sysc_fields = &omap_hwmod_sysc_type1,
597};
598
599static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
600 .name = "gpio",
601 .sysc = &dra7xx_gpio_sysc,
602 .rev = 2,
603};
604
605/* gpio dev_attr */
606static struct omap_gpio_dev_attr gpio_dev_attr = {
607 .bank_width = 32,
608 .dbck_flag = true,
609};
610
611/* gpio1 */
612static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
613 { .role = "dbclk", .clk = "gpio1_dbclk" },
614};
615
616static struct omap_hwmod dra7xx_gpio1_hwmod = {
617 .name = "gpio1",
618 .class = &dra7xx_gpio_hwmod_class,
619 .clkdm_name = "wkupaon_clkdm",
620 .main_clk = "wkupaon_iclk_mux",
621 .prcm = {
622 .omap4 = {
623 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
624 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
625 .modulemode = MODULEMODE_HWCTRL,
626 },
627 },
628 .opt_clks = gpio1_opt_clks,
629 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
630 .dev_attr = &gpio_dev_attr,
631};
632
633/* gpio2 */
634static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
635 { .role = "dbclk", .clk = "gpio2_dbclk" },
636};
637
638static struct omap_hwmod dra7xx_gpio2_hwmod = {
639 .name = "gpio2",
640 .class = &dra7xx_gpio_hwmod_class,
641 .clkdm_name = "l4per_clkdm",
642 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
643 .main_clk = "l3_iclk_div",
644 .prcm = {
645 .omap4 = {
646 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
647 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
648 .modulemode = MODULEMODE_HWCTRL,
649 },
650 },
651 .opt_clks = gpio2_opt_clks,
652 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
653 .dev_attr = &gpio_dev_attr,
654};
655
656/* gpio3 */
657static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
658 { .role = "dbclk", .clk = "gpio3_dbclk" },
659};
660
661static struct omap_hwmod dra7xx_gpio3_hwmod = {
662 .name = "gpio3",
663 .class = &dra7xx_gpio_hwmod_class,
664 .clkdm_name = "l4per_clkdm",
665 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
666 .main_clk = "l3_iclk_div",
667 .prcm = {
668 .omap4 = {
669 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
670 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
671 .modulemode = MODULEMODE_HWCTRL,
672 },
673 },
674 .opt_clks = gpio3_opt_clks,
675 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
676 .dev_attr = &gpio_dev_attr,
677};
678
679/* gpio4 */
680static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
681 { .role = "dbclk", .clk = "gpio4_dbclk" },
682};
683
684static struct omap_hwmod dra7xx_gpio4_hwmod = {
685 .name = "gpio4",
686 .class = &dra7xx_gpio_hwmod_class,
687 .clkdm_name = "l4per_clkdm",
688 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
689 .main_clk = "l3_iclk_div",
690 .prcm = {
691 .omap4 = {
692 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
693 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
694 .modulemode = MODULEMODE_HWCTRL,
695 },
696 },
697 .opt_clks = gpio4_opt_clks,
698 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
699 .dev_attr = &gpio_dev_attr,
700};
701
702/* gpio5 */
703static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
704 { .role = "dbclk", .clk = "gpio5_dbclk" },
705};
706
707static struct omap_hwmod dra7xx_gpio5_hwmod = {
708 .name = "gpio5",
709 .class = &dra7xx_gpio_hwmod_class,
710 .clkdm_name = "l4per_clkdm",
711 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
712 .main_clk = "l3_iclk_div",
713 .prcm = {
714 .omap4 = {
715 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
716 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
717 .modulemode = MODULEMODE_HWCTRL,
718 },
719 },
720 .opt_clks = gpio5_opt_clks,
721 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
722 .dev_attr = &gpio_dev_attr,
723};
724
725/* gpio6 */
726static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
727 { .role = "dbclk", .clk = "gpio6_dbclk" },
728};
729
730static struct omap_hwmod dra7xx_gpio6_hwmod = {
731 .name = "gpio6",
732 .class = &dra7xx_gpio_hwmod_class,
733 .clkdm_name = "l4per_clkdm",
734 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
735 .main_clk = "l3_iclk_div",
736 .prcm = {
737 .omap4 = {
738 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
739 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
740 .modulemode = MODULEMODE_HWCTRL,
741 },
742 },
743 .opt_clks = gpio6_opt_clks,
744 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
745 .dev_attr = &gpio_dev_attr,
746};
747
748/* gpio7 */
749static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
750 { .role = "dbclk", .clk = "gpio7_dbclk" },
751};
752
753static struct omap_hwmod dra7xx_gpio7_hwmod = {
754 .name = "gpio7",
755 .class = &dra7xx_gpio_hwmod_class,
756 .clkdm_name = "l4per_clkdm",
757 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
758 .main_clk = "l3_iclk_div",
759 .prcm = {
760 .omap4 = {
761 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
762 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
763 .modulemode = MODULEMODE_HWCTRL,
764 },
765 },
766 .opt_clks = gpio7_opt_clks,
767 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
768 .dev_attr = &gpio_dev_attr,
769};
770
771/* gpio8 */
772static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
773 { .role = "dbclk", .clk = "gpio8_dbclk" },
774};
775
776static struct omap_hwmod dra7xx_gpio8_hwmod = {
777 .name = "gpio8",
778 .class = &dra7xx_gpio_hwmod_class,
779 .clkdm_name = "l4per_clkdm",
780 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
781 .main_clk = "l3_iclk_div",
782 .prcm = {
783 .omap4 = {
784 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
785 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
786 .modulemode = MODULEMODE_HWCTRL,
787 },
788 },
789 .opt_clks = gpio8_opt_clks,
790 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
791 .dev_attr = &gpio_dev_attr,
792};
793
794/*
795 * 'gpmc' class
796 *
797 */
798
799static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
800 .rev_offs = 0x0000,
801 .sysc_offs = 0x0010,
802 .syss_offs = 0x0014,
803 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
804 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
805 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
806 SIDLE_SMART_WKUP),
807 .sysc_fields = &omap_hwmod_sysc_type1,
808};
809
810static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
811 .name = "gpmc",
812 .sysc = &dra7xx_gpmc_sysc,
813};
814
815/* gpmc */
816
817static struct omap_hwmod dra7xx_gpmc_hwmod = {
818 .name = "gpmc",
819 .class = &dra7xx_gpmc_hwmod_class,
820 .clkdm_name = "l3main1_clkdm",
821 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
822 .main_clk = "l3_iclk_div",
823 .prcm = {
824 .omap4 = {
825 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
826 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
827 .modulemode = MODULEMODE_HWCTRL,
828 },
829 },
830};
831
832/*
833 * 'hdq1w' class
834 *
835 */
836
837static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
838 .rev_offs = 0x0000,
839 .sysc_offs = 0x0014,
840 .syss_offs = 0x0018,
841 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
842 SYSS_HAS_RESET_STATUS),
843 .sysc_fields = &omap_hwmod_sysc_type1,
844};
845
846static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
847 .name = "hdq1w",
848 .sysc = &dra7xx_hdq1w_sysc,
849};
850
851/* hdq1w */
852
853static struct omap_hwmod dra7xx_hdq1w_hwmod = {
854 .name = "hdq1w",
855 .class = &dra7xx_hdq1w_hwmod_class,
856 .clkdm_name = "l4per_clkdm",
857 .flags = HWMOD_INIT_NO_RESET,
858 .main_clk = "func_12m_fclk",
859 .prcm = {
860 .omap4 = {
861 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
862 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
863 .modulemode = MODULEMODE_SWCTRL,
864 },
865 },
866};
867
868/*
869 * 'i2c' class
870 *
871 */
872
873static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
874 .sysc_offs = 0x0010,
875 .syss_offs = 0x0090,
876 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
877 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
878 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
879 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
880 SIDLE_SMART_WKUP),
881 .clockact = CLOCKACT_TEST_ICLK,
882 .sysc_fields = &omap_hwmod_sysc_type1,
883};
884
885static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
886 .name = "i2c",
887 .sysc = &dra7xx_i2c_sysc,
888 .reset = &omap_i2c_reset,
889 .rev = OMAP_I2C_IP_VERSION_2,
890};
891
892/* i2c dev_attr */
893static struct omap_i2c_dev_attr i2c_dev_attr = {
894 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
895};
896
897/* i2c1 */
898static struct omap_hwmod dra7xx_i2c1_hwmod = {
899 .name = "i2c1",
900 .class = &dra7xx_i2c_hwmod_class,
901 .clkdm_name = "l4per_clkdm",
902 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
903 .main_clk = "func_96m_fclk",
904 .prcm = {
905 .omap4 = {
906 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
907 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
908 .modulemode = MODULEMODE_SWCTRL,
909 },
910 },
911 .dev_attr = &i2c_dev_attr,
912};
913
914/* i2c2 */
915static struct omap_hwmod dra7xx_i2c2_hwmod = {
916 .name = "i2c2",
917 .class = &dra7xx_i2c_hwmod_class,
918 .clkdm_name = "l4per_clkdm",
919 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
920 .main_clk = "func_96m_fclk",
921 .prcm = {
922 .omap4 = {
923 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
924 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
925 .modulemode = MODULEMODE_SWCTRL,
926 },
927 },
928 .dev_attr = &i2c_dev_attr,
929};
930
931/* i2c3 */
932static struct omap_hwmod dra7xx_i2c3_hwmod = {
933 .name = "i2c3",
934 .class = &dra7xx_i2c_hwmod_class,
935 .clkdm_name = "l4per_clkdm",
936 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
937 .main_clk = "func_96m_fclk",
938 .prcm = {
939 .omap4 = {
940 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
941 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
942 .modulemode = MODULEMODE_SWCTRL,
943 },
944 },
945 .dev_attr = &i2c_dev_attr,
946};
947
948/* i2c4 */
949static struct omap_hwmod dra7xx_i2c4_hwmod = {
950 .name = "i2c4",
951 .class = &dra7xx_i2c_hwmod_class,
952 .clkdm_name = "l4per_clkdm",
953 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
954 .main_clk = "func_96m_fclk",
955 .prcm = {
956 .omap4 = {
957 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
958 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
959 .modulemode = MODULEMODE_SWCTRL,
960 },
961 },
962 .dev_attr = &i2c_dev_attr,
963};
964
965/* i2c5 */
966static struct omap_hwmod dra7xx_i2c5_hwmod = {
967 .name = "i2c5",
968 .class = &dra7xx_i2c_hwmod_class,
969 .clkdm_name = "ipu_clkdm",
970 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
971 .main_clk = "func_96m_fclk",
972 .prcm = {
973 .omap4 = {
974 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
975 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
976 .modulemode = MODULEMODE_SWCTRL,
977 },
978 },
979 .dev_attr = &i2c_dev_attr,
980};
981
067395d4
SA		 982/*
983 * 'mailbox' class
984 *
985 */
986
987static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
988 .rev_offs = 0x0000,
989 .sysc_offs = 0x0010,
990 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
991 SYSC_HAS_SOFTRESET),
992 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
993 .sysc_fields = &omap_hwmod_sysc_type2,
994};
995
996static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
997 .name = "mailbox",
998 .sysc = &dra7xx_mailbox_sysc,
999};
1000
1001/* mailbox1 */
1002static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1003 .name = "mailbox1",
1004 .class = &dra7xx_mailbox_hwmod_class,
1005 .clkdm_name = "l4cfg_clkdm",
1006 .prcm = {
1007 .omap4 = {
1008 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1009 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1010 },
1011 },
1012};
1013
1014/* mailbox2 */
1015static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1016 .name = "mailbox2",
1017 .class = &dra7xx_mailbox_hwmod_class,
1018 .clkdm_name = "l4cfg_clkdm",
1019 .prcm = {
1020 .omap4 = {
1021 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1022 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1023 },
1024 },
1025};
1026
1027/* mailbox3 */
1028static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1029 .name = "mailbox3",
1030 .class = &dra7xx_mailbox_hwmod_class,
1031 .clkdm_name = "l4cfg_clkdm",
1032 .prcm = {
1033 .omap4 = {
1034 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1035 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1036 },
1037 },
1038};
1039
1040/* mailbox4 */
1041static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1042 .name = "mailbox4",
1043 .class = &dra7xx_mailbox_hwmod_class,
1044 .clkdm_name = "l4cfg_clkdm",
1045 .prcm = {
1046 .omap4 = {
1047 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1048 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1049 },
1050 },
1051};
1052
1053/* mailbox5 */
1054static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1055 .name = "mailbox5",
1056 .class = &dra7xx_mailbox_hwmod_class,
1057 .clkdm_name = "l4cfg_clkdm",
1058 .prcm = {
1059 .omap4 = {
1060 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1061 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1062 },
1063 },
1064};
1065
1066/* mailbox6 */
1067static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1068 .name = "mailbox6",
1069 .class = &dra7xx_mailbox_hwmod_class,
1070 .clkdm_name = "l4cfg_clkdm",
1071 .prcm = {
1072 .omap4 = {
1073 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1074 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1075 },
1076 },
1077};
1078
1079/* mailbox7 */
1080static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1081 .name = "mailbox7",
1082 .class = &dra7xx_mailbox_hwmod_class,
1083 .clkdm_name = "l4cfg_clkdm",
1084 .prcm = {
1085 .omap4 = {
1086 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1087 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1088 },
1089 },
1090};
1091
1092/* mailbox8 */
1093static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1094 .name = "mailbox8",
1095 .class = &dra7xx_mailbox_hwmod_class,
1096 .clkdm_name = "l4cfg_clkdm",
1097 .prcm = {
1098 .omap4 = {
1099 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1100 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1101 },
1102 },
1103};
1104
1105/* mailbox9 */
1106static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1107 .name = "mailbox9",
1108 .class = &dra7xx_mailbox_hwmod_class,
1109 .clkdm_name = "l4cfg_clkdm",
1110 .prcm = {
1111 .omap4 = {
1112 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1113 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1114 },
1115 },
1116};
1117
1118/* mailbox10 */
1119static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1120 .name = "mailbox10",
1121 .class = &dra7xx_mailbox_hwmod_class,
1122 .clkdm_name = "l4cfg_clkdm",
1123 .prcm = {
1124 .omap4 = {
1125 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1126 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1127 },
1128 },
1129};
1130
1131/* mailbox11 */
1132static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1133 .name = "mailbox11",
1134 .class = &dra7xx_mailbox_hwmod_class,
1135 .clkdm_name = "l4cfg_clkdm",
1136 .prcm = {
1137 .omap4 = {
1138 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1139 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1140 },
1141 },
1142};
1143
1144/* mailbox12 */
1145static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1146 .name = "mailbox12",
1147 .class = &dra7xx_mailbox_hwmod_class,
1148 .clkdm_name = "l4cfg_clkdm",
1149 .prcm = {
1150 .omap4 = {
1151 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1152 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1153 },
1154 },
1155};
1156
1157/* mailbox13 */
1158static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1159 .name = "mailbox13",
1160 .class = &dra7xx_mailbox_hwmod_class,
1161 .clkdm_name = "l4cfg_clkdm",
1162 .prcm = {
1163 .omap4 = {
1164 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1165 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1166 },
1167 },
1168};
1169
90020c7b
A		 1170/*
1171 * 'mcspi' class
1172 *
1173 */
1174
1175static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1176 .rev_offs = 0x0000,
1177 .sysc_offs = 0x0010,
1178 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1179 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1180 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1181 SIDLE_SMART_WKUP),
1182 .sysc_fields = &omap_hwmod_sysc_type2,
1183};
1184
1185static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1186 .name = "mcspi",
1187 .sysc = &dra7xx_mcspi_sysc,
1188 .rev = OMAP4_MCSPI_REV,
1189};
1190
1191/* mcspi1 */
1192/* mcspi1 dev_attr */
1193static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1194 .num_chipselect = 4,
1195};
1196
1197static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1198 .name = "mcspi1",
1199 .class = &dra7xx_mcspi_hwmod_class,
1200 .clkdm_name = "l4per_clkdm",
1201 .main_clk = "func_48m_fclk",
1202 .prcm = {
1203 .omap4 = {
1204 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1205 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1206 .modulemode = MODULEMODE_SWCTRL,
1207 },
1208 },
1209 .dev_attr = &mcspi1_dev_attr,
1210};
1211
1212/* mcspi2 */
1213/* mcspi2 dev_attr */
1214static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1215 .num_chipselect = 2,
1216};
1217
1218static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1219 .name = "mcspi2",
1220 .class = &dra7xx_mcspi_hwmod_class,
1221 .clkdm_name = "l4per_clkdm",
1222 .main_clk = "func_48m_fclk",
1223 .prcm = {
1224 .omap4 = {
1225 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1226 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1227 .modulemode = MODULEMODE_SWCTRL,
1228 },
1229 },
1230 .dev_attr = &mcspi2_dev_attr,
1231};
1232
1233/* mcspi3 */
1234/* mcspi3 dev_attr */
1235static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1236 .num_chipselect = 2,
1237};
1238
1239static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1240 .name = "mcspi3",
1241 .class = &dra7xx_mcspi_hwmod_class,
1242 .clkdm_name = "l4per_clkdm",
1243 .main_clk = "func_48m_fclk",
1244 .prcm = {
1245 .omap4 = {
1246 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1247 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1248 .modulemode = MODULEMODE_SWCTRL,
1249 },
1250 },
1251 .dev_attr = &mcspi3_dev_attr,
1252};
1253
1254/* mcspi4 */
1255/* mcspi4 dev_attr */
1256static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1257 .num_chipselect = 1,
1258};
1259
1260static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1261 .name = "mcspi4",
1262 .class = &dra7xx_mcspi_hwmod_class,
1263 .clkdm_name = "l4per_clkdm",
1264 .main_clk = "func_48m_fclk",
1265 .prcm = {
1266 .omap4 = {
1267 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1268 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1269 .modulemode = MODULEMODE_SWCTRL,
1270 },
1271 },
1272 .dev_attr = &mcspi4_dev_attr,
1273};
1274
1275/*
1276 * 'mmc' class
1277 *
1278 */
1279
1280static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1281 .rev_offs = 0x0000,
1282 .sysc_offs = 0x0010,
1283 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1284 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1285 SYSC_HAS_SOFTRESET),
1286 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1287 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1288 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1289 .sysc_fields = &omap_hwmod_sysc_type2,
1290};
1291
1292static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1293 .name = "mmc",
1294 .sysc = &dra7xx_mmc_sysc,
1295};
1296
1297/* mmc1 */
1298static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1299 { .role = "clk32k", .clk = "mmc1_clk32k" },
1300};
1301
1302/* mmc1 dev_attr */
1303static struct omap_mmc_dev_attr mmc1_dev_attr = {
1304 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1305};
1306
1307static struct omap_hwmod dra7xx_mmc1_hwmod = {
1308 .name = "mmc1",
1309 .class = &dra7xx_mmc_hwmod_class,
1310 .clkdm_name = "l3init_clkdm",
1311 .main_clk = "mmc1_fclk_div",
1312 .prcm = {
1313 .omap4 = {
1314 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1315 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1316 .modulemode = MODULEMODE_SWCTRL,
1317 },
1318 },
1319 .opt_clks = mmc1_opt_clks,
1320 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1321 .dev_attr = &mmc1_dev_attr,
1322};
1323
1324/* mmc2 */
1325static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1326 { .role = "clk32k", .clk = "mmc2_clk32k" },
1327};
1328
1329static struct omap_hwmod dra7xx_mmc2_hwmod = {
1330 .name = "mmc2",
1331 .class = &dra7xx_mmc_hwmod_class,
1332 .clkdm_name = "l3init_clkdm",
1333 .main_clk = "mmc2_fclk_div",
1334 .prcm = {
1335 .omap4 = {
1336 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1337 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1338 .modulemode = MODULEMODE_SWCTRL,
1339 },
1340 },
1341 .opt_clks = mmc2_opt_clks,
1342 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1343};
1344
1345/* mmc3 */
1346static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1347 { .role = "clk32k", .clk = "mmc3_clk32k" },
1348};
1349
1350static struct omap_hwmod dra7xx_mmc3_hwmod = {
1351 .name = "mmc3",
1352 .class = &dra7xx_mmc_hwmod_class,
1353 .clkdm_name = "l4per_clkdm",
1354 .main_clk = "mmc3_gfclk_div",
1355 .prcm = {
1356 .omap4 = {
1357 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1358 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1359 .modulemode = MODULEMODE_SWCTRL,
1360 },
1361 },
1362 .opt_clks = mmc3_opt_clks,
1363 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1364};
1365
1366/* mmc4 */
1367static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1368 { .role = "clk32k", .clk = "mmc4_clk32k" },
1369};
1370
1371static struct omap_hwmod dra7xx_mmc4_hwmod = {
1372 .name = "mmc4",
1373 .class = &dra7xx_mmc_hwmod_class,
1374 .clkdm_name = "l4per_clkdm",
1375 .main_clk = "mmc4_gfclk_div",
1376 .prcm = {
1377 .omap4 = {
1378 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1379 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1380 .modulemode = MODULEMODE_SWCTRL,
1381 },
1382 },
1383 .opt_clks = mmc4_opt_clks,
1384 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1385};
1386
1387/*
1388 * 'mpu' class
1389 *
1390 */
1391
1392static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1393 .name = "mpu",
1394};
1395
1396/* mpu */
1397static struct omap_hwmod dra7xx_mpu_hwmod = {
1398 .name = "mpu",
1399 .class = &dra7xx_mpu_hwmod_class,
1400 .clkdm_name = "mpu_clkdm",
1401 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1402 .main_clk = "dpll_mpu_m2_ck",
1403 .prcm = {
1404 .omap4 = {
1405 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1406 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1407 },
1408 },
1409};
1410
1411/*
1412 * 'ocp2scp' class
1413 *
1414 */
1415
1416static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1417 .rev_offs = 0x0000,
1418 .sysc_offs = 0x0010,
1419 .syss_offs = 0x0014,
1420 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1421 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1422 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1423 SIDLE_SMART_WKUP),
1424 .sysc_fields = &omap_hwmod_sysc_type1,
1425};
1426
1427static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1428 .name = "ocp2scp",
1429 .sysc = &dra7xx_ocp2scp_sysc,
1430};
1431
1432/* ocp2scp1 */
1433static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1434 .name = "ocp2scp1",
1435 .class = &dra7xx_ocp2scp_hwmod_class,
1436 .clkdm_name = "l3init_clkdm",
1437 .main_clk = "l4_root_clk_div",
1438 .prcm = {
1439 .omap4 = {
1440 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1441 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1442 .modulemode = MODULEMODE_HWCTRL,
1443 },
1444 },
1445};
1446
df0d0f11
RQ		 1447/* ocp2scp3 */
1448static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1449 .name = "ocp2scp3",
1450 .class = &dra7xx_ocp2scp_hwmod_class,
1451 .clkdm_name = "l3init_clkdm",
1452 .main_clk = "l4_root_clk_div",
1453 .prcm = {
1454 .omap4 = {
1455 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1456 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1457 .modulemode = MODULEMODE_HWCTRL,
1458 },
1459 },
1460};
1461
8dd3eb71
KVA		 1462/*
1463 * 'PCIE' class
1464 *
1465 */
1466
1467static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
1468 .name = "pcie",
1469};
1470
1471/* pcie1 */
1472static struct omap_hwmod dra7xx_pcie1_hwmod = {
1473 .name = "pcie1",
1474 .class = &dra7xx_pcie_hwmod_class,
1475 .clkdm_name = "pcie_clkdm",
1476 .main_clk = "l4_root_clk_div",
1477 .prcm = {
1478 .omap4 = {
1479 .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
1480 .modulemode = MODULEMODE_SWCTRL,
1481 },
1482 },
1483};
1484
1485/* pcie2 */
1486static struct omap_hwmod dra7xx_pcie2_hwmod = {
1487 .name = "pcie2",
1488 .class = &dra7xx_pcie_hwmod_class,
1489 .clkdm_name = "pcie_clkdm",
1490 .main_clk = "l4_root_clk_div",
1491 .prcm = {
1492 .omap4 = {
1493 .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
1494 .modulemode = MODULEMODE_SWCTRL,
1495 },
1496 },
1497};
1498
70c18ef7
KVA		 1499/*
1500 * 'PCIE PHY' class
1501 *
1502 */
1503
1504static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
1505 .name = "pcie-phy",
1506};
1507
1508/* pcie1 phy */
1509static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
1510 .name = "pcie1-phy",
1511 .class = &dra7xx_pcie_phy_hwmod_class,
1512 .clkdm_name = "l3init_clkdm",
1513 .main_clk = "l4_root_clk_div",
1514 .prcm = {
1515 .omap4 = {
1516 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1517 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1518 .modulemode = MODULEMODE_SWCTRL,
1519 },
1520 },
1521};
1522
1523/* pcie2 phy */
1524static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
1525 .name = "pcie2-phy",
1526 .class = &dra7xx_pcie_phy_hwmod_class,
1527 .clkdm_name = "l3init_clkdm",
1528 .main_clk = "l4_root_clk_div",
1529 .prcm = {
1530 .omap4 = {
1531 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1532 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1533 .modulemode = MODULEMODE_SWCTRL,
1534 },
1535 },
1536};
1537
90020c7b
A		 1538/*
1539 * 'qspi' class
1540 *
1541 */
1542
1543static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1544 .sysc_offs = 0x0010,
1545 .sysc_flags = SYSC_HAS_SIDLEMODE,
1546 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1547 SIDLE_SMART_WKUP),
1548 .sysc_fields = &omap_hwmod_sysc_type2,
1549};
1550
1551static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1552 .name = "qspi",
1553 .sysc = &dra7xx_qspi_sysc,
1554};
1555
1556/* qspi */
1557static struct omap_hwmod dra7xx_qspi_hwmod = {
1558 .name = "qspi",
1559 .class = &dra7xx_qspi_hwmod_class,
1560 .clkdm_name = "l4per2_clkdm",
1561 .main_clk = "qspi_gfclk_div",
1562 .prcm = {
1563 .omap4 = {
1564 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1565 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1566 .modulemode = MODULEMODE_SWCTRL,
1567 },
1568 },
1569};
1570
c913c8a1
LV		 1571/*
1572 * 'rtcss' class
1573 *
1574 */
1575static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1576 .sysc_offs = 0x0078,
1577 .sysc_flags = SYSC_HAS_SIDLEMODE,
1578 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1579 SIDLE_SMART_WKUP),
1580 .sysc_fields = &omap_hwmod_sysc_type3,
1581};
1582
1583static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1584 .name = "rtcss",
1585 .sysc = &dra7xx_rtcss_sysc,
1586};
1587
1588/* rtcss */
1589static struct omap_hwmod dra7xx_rtcss_hwmod = {
1590 .name = "rtcss",
1591 .class = &dra7xx_rtcss_hwmod_class,
1592 .clkdm_name = "rtc_clkdm",
1593 .main_clk = "sys_32k_ck",
1594 .prcm = {
1595 .omap4 = {
1596 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1597 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1598 .modulemode = MODULEMODE_SWCTRL,
1599 },
1600 },
1601};
1602
90020c7b
A		 1603/*
1604 * 'sata' class
1605 *
1606 */
1607
1608static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1609 .sysc_offs = 0x0000,
1610 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1611 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1612 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1613 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1614 .sysc_fields = &omap_hwmod_sysc_type2,
1615};
1616
1617static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1618 .name = "sata",
1619 .sysc = &dra7xx_sata_sysc,
1620};
1621
1622/* sata */
90020c7b
A		 1623
1624static struct omap_hwmod dra7xx_sata_hwmod = {
1625 .name = "sata",
1626 .class = &dra7xx_sata_hwmod_class,
1627 .clkdm_name = "l3init_clkdm",
1628 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1629 .main_clk = "func_48m_fclk",
1ea0999e 1630 .mpu_rt_idx = 1,
90020c7b
A		 1631 .prcm = {
1632 .omap4 = {
1633 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1634 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1635 .modulemode = MODULEMODE_SWCTRL,
1636 },
1637 },
90020c7b
A		 1638};
1639
1640/*
1641 * 'smartreflex' class
1642 *
1643 */
1644
1645/* The IP is not compliant to type1 / type2 scheme */
1646static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1647 .sidle_shift = 24,
1648 .enwkup_shift = 26,
1649};
1650
1651static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1652 .sysc_offs = 0x0038,
1653 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1654 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1655 SIDLE_SMART_WKUP),
1656 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1657};
1658
1659static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1660 .name = "smartreflex",
1661 .sysc = &dra7xx_smartreflex_sysc,
1662 .rev = 2,
1663};
1664
1665/* smartreflex_core */
1666/* smartreflex_core dev_attr */
1667static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1668 .sensor_voltdm_name = "core",
1669};
1670
1671static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1672 .name = "smartreflex_core",
1673 .class = &dra7xx_smartreflex_hwmod_class,
1674 .clkdm_name = "coreaon_clkdm",
1675 .main_clk = "wkupaon_iclk_mux",
1676 .prcm = {
1677 .omap4 = {
1678 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1679 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1680 .modulemode = MODULEMODE_SWCTRL,
1681 },
1682 },
1683 .dev_attr = &smartreflex_core_dev_attr,
1684};
1685
1686/* smartreflex_mpu */
1687/* smartreflex_mpu dev_attr */
1688static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1689 .sensor_voltdm_name = "mpu",
1690};
1691
1692static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1693 .name = "smartreflex_mpu",
1694 .class = &dra7xx_smartreflex_hwmod_class,
1695 .clkdm_name = "coreaon_clkdm",
1696 .main_clk = "wkupaon_iclk_mux",
1697 .prcm = {
1698 .omap4 = {
1699 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1700 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1701 .modulemode = MODULEMODE_SWCTRL,
1702 },
1703 },
1704 .dev_attr = &smartreflex_mpu_dev_attr,
1705};
1706
1707/*
1708 * 'spinlock' class
1709 *
1710 */
1711
1712static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1713 .rev_offs = 0x0000,
1714 .sysc_offs = 0x0010,
1715 .syss_offs = 0x0014,
c317d0f2
SA		 1716 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1717 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1718 SYSS_HAS_RESET_STATUS),
1719 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
90020c7b
A		 1720 .sysc_fields = &omap_hwmod_sysc_type1,
1721};
1722
1723static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1724 .name = "spinlock",
1725 .sysc = &dra7xx_spinlock_sysc,
1726};
1727
1728/* spinlock */
1729static struct omap_hwmod dra7xx_spinlock_hwmod = {
1730 .name = "spinlock",
1731 .class = &dra7xx_spinlock_hwmod_class,
1732 .clkdm_name = "l4cfg_clkdm",
1733 .main_clk = "l3_iclk_div",
1734 .prcm = {
1735 .omap4 = {
1736 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1737 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1738 },
1739 },
1740};
1741
1742/*
1743 * 'timer' class
1744 *
1745 * This class contains several variants: ['timer_1ms', 'timer_secure',
1746 * 'timer']
1747 */
1748
1749static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1750 .rev_offs = 0x0000,
1751 .sysc_offs = 0x0010,
1752 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1753 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1754 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1755 SIDLE_SMART_WKUP),
1756 .sysc_fields = &omap_hwmod_sysc_type2,
1757};
1758
1759static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1760 .name = "timer",
1761 .sysc = &dra7xx_timer_1ms_sysc,
1762};
1763
1764static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
1765 .rev_offs = 0x0000,
1766 .sysc_offs = 0x0010,
1767 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1768 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1769 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1770 SIDLE_SMART_WKUP),
1771 .sysc_fields = &omap_hwmod_sysc_type2,
1772};
1773
1774static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
1775 .name = "timer",
1776 .sysc = &dra7xx_timer_secure_sysc,
1777};
1778
1779static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1780 .rev_offs = 0x0000,
1781 .sysc_offs = 0x0010,
1782 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1783 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1784 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1785 SIDLE_SMART_WKUP),
1786 .sysc_fields = &omap_hwmod_sysc_type2,
1787};
1788
1789static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1790 .name = "timer",
1791 .sysc = &dra7xx_timer_sysc,
1792};
1793
1794/* timer1 */
1795static struct omap_hwmod dra7xx_timer1_hwmod = {
1796 .name = "timer1",
1797 .class = &dra7xx_timer_1ms_hwmod_class,
1798 .clkdm_name = "wkupaon_clkdm",
1799 .main_clk = "timer1_gfclk_mux",
1800 .prcm = {
1801 .omap4 = {
1802 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1803 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1804 .modulemode = MODULEMODE_SWCTRL,
1805 },
1806 },
1807};
1808
1809/* timer2 */
1810static struct omap_hwmod dra7xx_timer2_hwmod = {
1811 .name = "timer2",
1812 .class = &dra7xx_timer_1ms_hwmod_class,
1813 .clkdm_name = "l4per_clkdm",
1814 .main_clk = "timer2_gfclk_mux",
1815 .prcm = {
1816 .omap4 = {
1817 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1818 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1819 .modulemode = MODULEMODE_SWCTRL,
1820 },
1821 },
1822};
1823
1824/* timer3 */
1825static struct omap_hwmod dra7xx_timer3_hwmod = {
1826 .name = "timer3",
1827 .class = &dra7xx_timer_hwmod_class,
1828 .clkdm_name = "l4per_clkdm",
1829 .main_clk = "timer3_gfclk_mux",
1830 .prcm = {
1831 .omap4 = {
1832 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1833 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1834 .modulemode = MODULEMODE_SWCTRL,
1835 },
1836 },
1837};
1838
1839/* timer4 */
1840static struct omap_hwmod dra7xx_timer4_hwmod = {
1841 .name = "timer4",
1842 .class = &dra7xx_timer_secure_hwmod_class,
1843 .clkdm_name = "l4per_clkdm",
1844 .main_clk = "timer4_gfclk_mux",
1845 .prcm = {
1846 .omap4 = {
1847 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1848 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1849 .modulemode = MODULEMODE_SWCTRL,
1850 },
1851 },
1852};
1853
1854/* timer5 */
1855static struct omap_hwmod dra7xx_timer5_hwmod = {
1856 .name = "timer5",
1857 .class = &dra7xx_timer_hwmod_class,
1858 .clkdm_name = "ipu_clkdm",
1859 .main_clk = "timer5_gfclk_mux",
1860 .prcm = {
1861 .omap4 = {
1862 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1863 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1864 .modulemode = MODULEMODE_SWCTRL,
1865 },
1866 },
1867};
1868
1869/* timer6 */
1870static struct omap_hwmod dra7xx_timer6_hwmod = {
1871 .name = "timer6",
1872 .class = &dra7xx_timer_hwmod_class,
1873 .clkdm_name = "ipu_clkdm",
1874 .main_clk = "timer6_gfclk_mux",
1875 .prcm = {
1876 .omap4 = {
1877 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1878 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1879 .modulemode = MODULEMODE_SWCTRL,
1880 },
1881 },
1882};
1883
1884/* timer7 */
1885static struct omap_hwmod dra7xx_timer7_hwmod = {
1886 .name = "timer7",
1887 .class = &dra7xx_timer_hwmod_class,
1888 .clkdm_name = "ipu_clkdm",
1889 .main_clk = "timer7_gfclk_mux",
1890 .prcm = {
1891 .omap4 = {
1892 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1893 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1894 .modulemode = MODULEMODE_SWCTRL,
1895 },
1896 },
1897};
1898
1899/* timer8 */
1900static struct omap_hwmod dra7xx_timer8_hwmod = {
1901 .name = "timer8",
1902 .class = &dra7xx_timer_hwmod_class,
1903 .clkdm_name = "ipu_clkdm",
1904 .main_clk = "timer8_gfclk_mux",
1905 .prcm = {
1906 .omap4 = {
1907 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1908 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1909 .modulemode = MODULEMODE_SWCTRL,
1910 },
1911 },
1912};
1913
1914/* timer9 */
1915static struct omap_hwmod dra7xx_timer9_hwmod = {
1916 .name = "timer9",
1917 .class = &dra7xx_timer_hwmod_class,
1918 .clkdm_name = "l4per_clkdm",
1919 .main_clk = "timer9_gfclk_mux",
1920 .prcm = {
1921 .omap4 = {
1922 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1923 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1924 .modulemode = MODULEMODE_SWCTRL,
1925 },
1926 },
1927};
1928
1929/* timer10 */
1930static struct omap_hwmod dra7xx_timer10_hwmod = {
1931 .name = "timer10",
1932 .class = &dra7xx_timer_1ms_hwmod_class,
1933 .clkdm_name = "l4per_clkdm",
1934 .main_clk = "timer10_gfclk_mux",
1935 .prcm = {
1936 .omap4 = {
1937 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1938 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1939 .modulemode = MODULEMODE_SWCTRL,
1940 },
1941 },
1942};
1943
1944/* timer11 */
1945static struct omap_hwmod dra7xx_timer11_hwmod = {
1946 .name = "timer11",
1947 .class = &dra7xx_timer_hwmod_class,
1948 .clkdm_name = "l4per_clkdm",
1949 .main_clk = "timer11_gfclk_mux",
1950 .prcm = {
1951 .omap4 = {
1952 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1953 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1954 .modulemode = MODULEMODE_SWCTRL,
1955 },
1956 },
1957};
1958
1959/*
1960 * 'uart' class
1961 *
1962 */
1963
1964static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
1965 .rev_offs = 0x0050,
1966 .sysc_offs = 0x0054,
1967 .syss_offs = 0x0058,
1968 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1969 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1970 SYSS_HAS_RESET_STATUS),
1971 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1972 SIDLE_SMART_WKUP),
1973 .sysc_fields = &omap_hwmod_sysc_type1,
1974};
1975
1976static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
1977 .name = "uart",
1978 .sysc = &dra7xx_uart_sysc,
1979};
1980
1981/* uart1 */
1982static struct omap_hwmod dra7xx_uart1_hwmod = {
1983 .name = "uart1",
1984 .class = &dra7xx_uart_hwmod_class,
1985 .clkdm_name = "l4per_clkdm",
1986 .main_clk = "uart1_gfclk_mux",
38958c15 1987 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
90020c7b
A		 1988 .prcm = {
1989 .omap4 = {
1990 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1991 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1992 .modulemode = MODULEMODE_SWCTRL,
1993 },
1994 },
1995};
1996
1997/* uart2 */
1998static struct omap_hwmod dra7xx_uart2_hwmod = {
1999 .name = "uart2",
2000 .class = &dra7xx_uart_hwmod_class,
2001 .clkdm_name = "l4per_clkdm",
2002 .main_clk = "uart2_gfclk_mux",
2003 .flags = HWMOD_SWSUP_SIDLE_ACT,
2004 .prcm = {
2005 .omap4 = {
2006 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2007 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2008 .modulemode = MODULEMODE_SWCTRL,
2009 },
2010 },
2011};
2012
2013/* uart3 */
2014static struct omap_hwmod dra7xx_uart3_hwmod = {
2015 .name = "uart3",
2016 .class = &dra7xx_uart_hwmod_class,
2017 .clkdm_name = "l4per_clkdm",
2018 .main_clk = "uart3_gfclk_mux",
2019 .flags = HWMOD_SWSUP_SIDLE_ACT,
2020 .prcm = {
2021 .omap4 = {
2022 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2023 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2024 .modulemode = MODULEMODE_SWCTRL,
2025 },
2026 },
2027};
2028
2029/* uart4 */
2030static struct omap_hwmod dra7xx_uart4_hwmod = {
2031 .name = "uart4",
2032 .class = &dra7xx_uart_hwmod_class,
2033 .clkdm_name = "l4per_clkdm",
2034 .main_clk = "uart4_gfclk_mux",
2035 .flags = HWMOD_SWSUP_SIDLE_ACT,
2036 .prcm = {
2037 .omap4 = {
2038 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2039 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2040 .modulemode = MODULEMODE_SWCTRL,
2041 },
2042 },
2043};
2044
2045/* uart5 */
2046static struct omap_hwmod dra7xx_uart5_hwmod = {
2047 .name = "uart5",
2048 .class = &dra7xx_uart_hwmod_class,
2049 .clkdm_name = "l4per_clkdm",
2050 .main_clk = "uart5_gfclk_mux",
2051 .flags = HWMOD_SWSUP_SIDLE_ACT,
2052 .prcm = {
2053 .omap4 = {
2054 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2055 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2056 .modulemode = MODULEMODE_SWCTRL,
2057 },
2058 },
2059};
2060
2061/* uart6 */
2062static struct omap_hwmod dra7xx_uart6_hwmod = {
2063 .name = "uart6",
2064 .class = &dra7xx_uart_hwmod_class,
2065 .clkdm_name = "ipu_clkdm",
2066 .main_clk = "uart6_gfclk_mux",
2067 .flags = HWMOD_SWSUP_SIDLE_ACT,
2068 .prcm = {
2069 .omap4 = {
2070 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2071 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2072 .modulemode = MODULEMODE_SWCTRL,
2073 },
2074 },
2075};
2076
2077/*
2078 * 'usb_otg_ss' class
2079 *
2080 */
2081
d904b38d
RQ		 2082static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2083 .rev_offs = 0x0000,
2084 .sysc_offs = 0x0010,
2085 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2086 SYSC_HAS_SIDLEMODE),
2087 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2088 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2089 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2090 .sysc_fields = &omap_hwmod_sysc_type2,
2091};
2092
90020c7b
A		 2093static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2094 .name = "usb_otg_ss",
d904b38d 2095 .sysc = &dra7xx_usb_otg_ss_sysc,
90020c7b
A		 2096};
2097
2098/* usb_otg_ss1 */
2099static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2100 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2101};
2102
2103static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2104 .name = "usb_otg_ss1",
2105 .class = &dra7xx_usb_otg_ss_hwmod_class,
2106 .clkdm_name = "l3init_clkdm",
2107 .main_clk = "dpll_core_h13x2_ck",
2108 .prcm = {
2109 .omap4 = {
2110 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2111 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2112 .modulemode = MODULEMODE_HWCTRL,
2113 },
2114 },
2115 .opt_clks = usb_otg_ss1_opt_clks,
2116 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2117};
2118
2119/* usb_otg_ss2 */
2120static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2121 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2122};
2123
2124static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2125 .name = "usb_otg_ss2",
2126 .class = &dra7xx_usb_otg_ss_hwmod_class,
2127 .clkdm_name = "l3init_clkdm",
2128 .main_clk = "dpll_core_h13x2_ck",
2129 .prcm = {
2130 .omap4 = {
2131 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2132 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2133 .modulemode = MODULEMODE_HWCTRL,
2134 },
2135 },
2136 .opt_clks = usb_otg_ss2_opt_clks,
2137 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2138};
2139
2140/* usb_otg_ss3 */
2141static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2142 .name = "usb_otg_ss3",
2143 .class = &dra7xx_usb_otg_ss_hwmod_class,
2144 .clkdm_name = "l3init_clkdm",
2145 .main_clk = "dpll_core_h13x2_ck",
2146 .prcm = {
2147 .omap4 = {
2148 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2149 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2150 .modulemode = MODULEMODE_HWCTRL,
2151 },
2152 },
2153};
2154
2155/* usb_otg_ss4 */
2156static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2157 .name = "usb_otg_ss4",
2158 .class = &dra7xx_usb_otg_ss_hwmod_class,
2159 .clkdm_name = "l3init_clkdm",
2160 .main_clk = "dpll_core_h13x2_ck",
2161 .prcm = {
2162 .omap4 = {
2163 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2164 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2165 .modulemode = MODULEMODE_HWCTRL,
2166 },
2167 },
2168};
2169
2170/*
2171 * 'vcp' class
2172 *
2173 */
2174
2175static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2176 .name = "vcp",
2177};
2178
2179/* vcp1 */
2180static struct omap_hwmod dra7xx_vcp1_hwmod = {
2181 .name = "vcp1",
2182 .class = &dra7xx_vcp_hwmod_class,
2183 .clkdm_name = "l3main1_clkdm",
2184 .main_clk = "l3_iclk_div",
2185 .prcm = {
2186 .omap4 = {
2187 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2188 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2189 },
2190 },
2191};
2192
2193/* vcp2 */
2194static struct omap_hwmod dra7xx_vcp2_hwmod = {
2195 .name = "vcp2",
2196 .class = &dra7xx_vcp_hwmod_class,
2197 .clkdm_name = "l3main1_clkdm",
2198 .main_clk = "l3_iclk_div",
2199 .prcm = {
2200 .omap4 = {
2201 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2202 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2203 },
2204 },
2205};
2206
2207/*
2208 * 'wd_timer' class
2209 *
2210 */
2211
2212static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2213 .rev_offs = 0x0000,
2214 .sysc_offs = 0x0010,
2215 .syss_offs = 0x0014,
2216 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2217 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2218 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2219 SIDLE_SMART_WKUP),
2220 .sysc_fields = &omap_hwmod_sysc_type1,
2221};
2222
2223static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2224 .name = "wd_timer",
2225 .sysc = &dra7xx_wd_timer_sysc,
2226 .pre_shutdown = &omap2_wd_timer_disable,
2227 .reset = &omap2_wd_timer_reset,
2228};
2229
2230/* wd_timer2 */
2231static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2232 .name = "wd_timer2",
2233 .class = &dra7xx_wd_timer_hwmod_class,
2234 .clkdm_name = "wkupaon_clkdm",
2235 .main_clk = "sys_32k_ck",
2236 .prcm = {
2237 .omap4 = {
2238 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2239 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2240 .modulemode = MODULEMODE_SWCTRL,
2241 },
2242 },
2243};
2244
2245
2246/*
2247 * Interfaces
2248 */
2249
2250/* l3_main_2 -> l3_instr */
2251static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2252 .master = &dra7xx_l3_main_2_hwmod,
2253 .slave = &dra7xx_l3_instr_hwmod,
2254 .clk = "l3_iclk_div",
2255 .user = OCP_USER_MPU | OCP_USER_SDMA,
2256};
2257
2258/* l4_cfg -> l3_main_1 */
2259static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2260 .master = &dra7xx_l4_cfg_hwmod,
2261 .slave = &dra7xx_l3_main_1_hwmod,
2262 .clk = "l3_iclk_div",
2263 .user = OCP_USER_MPU | OCP_USER_SDMA,
2264};
2265
2266/* mpu -> l3_main_1 */
2267static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2268 .master = &dra7xx_mpu_hwmod,
2269 .slave = &dra7xx_l3_main_1_hwmod,
2270 .clk = "l3_iclk_div",
2271 .user = OCP_USER_MPU,
2272};
2273
2274/* l3_main_1 -> l3_main_2 */
2275static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2276 .master = &dra7xx_l3_main_1_hwmod,
2277 .slave = &dra7xx_l3_main_2_hwmod,
2278 .clk = "l3_iclk_div",
2279 .user = OCP_USER_MPU,
2280};
2281
2282/* l4_cfg -> l3_main_2 */
2283static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2284 .master = &dra7xx_l4_cfg_hwmod,
2285 .slave = &dra7xx_l3_main_2_hwmod,
2286 .clk = "l3_iclk_div",
2287 .user = OCP_USER_MPU | OCP_USER_SDMA,
2288};
2289
2290/* l3_main_1 -> l4_cfg */
2291static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2292 .master = &dra7xx_l3_main_1_hwmod,
2293 .slave = &dra7xx_l4_cfg_hwmod,
2294 .clk = "l3_iclk_div",
2295 .user = OCP_USER_MPU | OCP_USER_SDMA,
2296};
2297
2298/* l3_main_1 -> l4_per1 */
2299static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2300 .master = &dra7xx_l3_main_1_hwmod,
2301 .slave = &dra7xx_l4_per1_hwmod,
2302 .clk = "l3_iclk_div",
2303 .user = OCP_USER_MPU | OCP_USER_SDMA,
2304};
2305
2306/* l3_main_1 -> l4_per2 */
2307static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2308 .master = &dra7xx_l3_main_1_hwmod,
2309 .slave = &dra7xx_l4_per2_hwmod,
2310 .clk = "l3_iclk_div",
2311 .user = OCP_USER_MPU | OCP_USER_SDMA,
2312};
2313
2314/* l3_main_1 -> l4_per3 */
2315static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2316 .master = &dra7xx_l3_main_1_hwmod,
2317 .slave = &dra7xx_l4_per3_hwmod,
2318 .clk = "l3_iclk_div",
2319 .user = OCP_USER_MPU | OCP_USER_SDMA,
2320};
2321
2322/* l3_main_1 -> l4_wkup */
2323static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2324 .master = &dra7xx_l3_main_1_hwmod,
2325 .slave = &dra7xx_l4_wkup_hwmod,
2326 .clk = "wkupaon_iclk_mux",
2327 .user = OCP_USER_MPU | OCP_USER_SDMA,
2328};
2329
2330/* l4_per2 -> atl */
2331static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2332 .master = &dra7xx_l4_per2_hwmod,
2333 .slave = &dra7xx_atl_hwmod,
2334 .clk = "l3_iclk_div",
2335 .user = OCP_USER_MPU | OCP_USER_SDMA,
2336};
2337
2338/* l3_main_1 -> bb2d */
2339static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2340 .master = &dra7xx_l3_main_1_hwmod,
2341 .slave = &dra7xx_bb2d_hwmod,
2342 .clk = "l3_iclk_div",
2343 .user = OCP_USER_MPU | OCP_USER_SDMA,
2344};
2345
2346/* l4_wkup -> counter_32k */
2347static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2348 .master = &dra7xx_l4_wkup_hwmod,
2349 .slave = &dra7xx_counter_32k_hwmod,
2350 .clk = "wkupaon_iclk_mux",
2351 .user = OCP_USER_MPU | OCP_USER_SDMA,
2352};
2353
2354/* l4_wkup -> ctrl_module_wkup */
2355static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2356 .master = &dra7xx_l4_wkup_hwmod,
2357 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2358 .clk = "wkupaon_iclk_mux",
2359 .user = OCP_USER_MPU | OCP_USER_SDMA,
2360};
2361
077c42f7
M		 2362static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2363 .master = &dra7xx_l4_per2_hwmod,
2364 .slave = &dra7xx_gmac_hwmod,
2365 .clk = "dpll_gmac_ck",
2366 .user = OCP_USER_MPU,
2367};
2368
2369static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2370 .master = &dra7xx_gmac_hwmod,
2371 .slave = &dra7xx_mdio_hwmod,
2372 .user = OCP_USER_MPU,
2373};
2374
90020c7b
A		 2375/* l4_wkup -> dcan1 */
2376static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2377 .master = &dra7xx_l4_wkup_hwmod,
2378 .slave = &dra7xx_dcan1_hwmod,
2379 .clk = "wkupaon_iclk_mux",
2380 .user = OCP_USER_MPU | OCP_USER_SDMA,
2381};
2382
2383/* l4_per2 -> dcan2 */
2384static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2385 .master = &dra7xx_l4_per2_hwmod,
2386 .slave = &dra7xx_dcan2_hwmod,
2387 .clk = "l3_iclk_div",
2388 .user = OCP_USER_MPU | OCP_USER_SDMA,
2389};
2390
2391static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2392 {
2393 .pa_start = 0x4a056000,
2394 .pa_end = 0x4a056fff,
2395 .flags = ADDR_TYPE_RT
2396 },
2397 { }
2398};
2399
2400/* l4_cfg -> dma_system */
2401static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2402 .master = &dra7xx_l4_cfg_hwmod,
2403 .slave = &dra7xx_dma_system_hwmod,
2404 .clk = "l3_iclk_div",
2405 .addr = dra7xx_dma_system_addrs,
2406 .user = OCP_USER_MPU | OCP_USER_SDMA,
2407};
2408
2409static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2410 {
2411 .name = "family",
2412 .pa_start = 0x58000000,
2413 .pa_end = 0x5800007f,
2414 .flags = ADDR_TYPE_RT
2415 },
2416};
2417
2418/* l3_main_1 -> dss */
2419static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2420 .master = &dra7xx_l3_main_1_hwmod,
2421 .slave = &dra7xx_dss_hwmod,
2422 .clk = "l3_iclk_div",
2423 .addr = dra7xx_dss_addrs,
2424 .user = OCP_USER_MPU | OCP_USER_SDMA,
2425};
2426
2427static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2428 {
2429 .name = "dispc",
2430 .pa_start = 0x58001000,
2431 .pa_end = 0x58001fff,
2432 .flags = ADDR_TYPE_RT
2433 },
2434};
2435
2436/* l3_main_1 -> dispc */
2437static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2438 .master = &dra7xx_l3_main_1_hwmod,
2439 .slave = &dra7xx_dss_dispc_hwmod,
2440 .clk = "l3_iclk_div",
2441 .addr = dra7xx_dss_dispc_addrs,
2442 .user = OCP_USER_MPU | OCP_USER_SDMA,
2443};
2444
2445static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2446 {
2447 .name = "hdmi_wp",
2448 .pa_start = 0x58040000,
2449 .pa_end = 0x580400ff,
2450 .flags = ADDR_TYPE_RT
2451 },
2452 { }
2453};
2454
2455/* l3_main_1 -> dispc */
2456static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2457 .master = &dra7xx_l3_main_1_hwmod,
2458 .slave = &dra7xx_dss_hdmi_hwmod,
2459 .clk = "l3_iclk_div",
2460 .addr = dra7xx_dss_hdmi_addrs,
2461 .user = OCP_USER_MPU | OCP_USER_SDMA,
2462};
2463
2464static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
2465 {
2466 .pa_start = 0x48078000,
2467 .pa_end = 0x48078fff,
2468 .flags = ADDR_TYPE_RT
2469 },
2470 { }
2471};
2472
2473/* l4_per1 -> elm */
2474static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2475 .master = &dra7xx_l4_per1_hwmod,
2476 .slave = &dra7xx_elm_hwmod,
2477 .clk = "l3_iclk_div",
2478 .addr = dra7xx_elm_addrs,
2479 .user = OCP_USER_MPU | OCP_USER_SDMA,
2480};
2481
2482/* l4_wkup -> gpio1 */
2483static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2484 .master = &dra7xx_l4_wkup_hwmod,
2485 .slave = &dra7xx_gpio1_hwmod,
2486 .clk = "wkupaon_iclk_mux",
2487 .user = OCP_USER_MPU | OCP_USER_SDMA,
2488};
2489
2490/* l4_per1 -> gpio2 */
2491static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2492 .master = &dra7xx_l4_per1_hwmod,
2493 .slave = &dra7xx_gpio2_hwmod,
2494 .clk = "l3_iclk_div",
2495 .user = OCP_USER_MPU | OCP_USER_SDMA,
2496};
2497
2498/* l4_per1 -> gpio3 */
2499static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2500 .master = &dra7xx_l4_per1_hwmod,
2501 .slave = &dra7xx_gpio3_hwmod,
2502 .clk = "l3_iclk_div",
2503 .user = OCP_USER_MPU | OCP_USER_SDMA,
2504};
2505
2506/* l4_per1 -> gpio4 */
2507static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2508 .master = &dra7xx_l4_per1_hwmod,
2509 .slave = &dra7xx_gpio4_hwmod,
2510 .clk = "l3_iclk_div",
2511 .user = OCP_USER_MPU | OCP_USER_SDMA,
2512};
2513
2514/* l4_per1 -> gpio5 */
2515static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2516 .master = &dra7xx_l4_per1_hwmod,
2517 .slave = &dra7xx_gpio5_hwmod,
2518 .clk = "l3_iclk_div",
2519 .user = OCP_USER_MPU | OCP_USER_SDMA,
2520};
2521
2522/* l4_per1 -> gpio6 */
2523static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2524 .master = &dra7xx_l4_per1_hwmod,
2525 .slave = &dra7xx_gpio6_hwmod,
2526 .clk = "l3_iclk_div",
2527 .user = OCP_USER_MPU | OCP_USER_SDMA,
2528};
2529
2530/* l4_per1 -> gpio7 */
2531static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2532 .master = &dra7xx_l4_per1_hwmod,
2533 .slave = &dra7xx_gpio7_hwmod,
2534 .clk = "l3_iclk_div",
2535 .user = OCP_USER_MPU | OCP_USER_SDMA,
2536};
2537
2538/* l4_per1 -> gpio8 */
2539static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2540 .master = &dra7xx_l4_per1_hwmod,
2541 .slave = &dra7xx_gpio8_hwmod,
2542 .clk = "l3_iclk_div",
2543 .user = OCP_USER_MPU | OCP_USER_SDMA,
2544};
2545
2546static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
2547 {
2548 .pa_start = 0x50000000,
2549 .pa_end = 0x500003ff,
2550 .flags = ADDR_TYPE_RT
2551 },
2552 { }
2553};
2554
2555/* l3_main_1 -> gpmc */
2556static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2557 .master = &dra7xx_l3_main_1_hwmod,
2558 .slave = &dra7xx_gpmc_hwmod,
2559 .clk = "l3_iclk_div",
2560 .addr = dra7xx_gpmc_addrs,
2561 .user = OCP_USER_MPU | OCP_USER_SDMA,
2562};
2563
2564static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2565 {
2566 .pa_start = 0x480b2000,
2567 .pa_end = 0x480b201f,
2568 .flags = ADDR_TYPE_RT
2569 },
2570 { }
2571};
2572
2573/* l4_per1 -> hdq1w */
2574static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2575 .master = &dra7xx_l4_per1_hwmod,
2576 .slave = &dra7xx_hdq1w_hwmod,
2577 .clk = "l3_iclk_div",
2578 .addr = dra7xx_hdq1w_addrs,
2579 .user = OCP_USER_MPU | OCP_USER_SDMA,
2580};
2581
2582/* l4_per1 -> i2c1 */
2583static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2584 .master = &dra7xx_l4_per1_hwmod,
2585 .slave = &dra7xx_i2c1_hwmod,
2586 .clk = "l3_iclk_div",
2587 .user = OCP_USER_MPU | OCP_USER_SDMA,
2588};
2589
2590/* l4_per1 -> i2c2 */
2591static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2592 .master = &dra7xx_l4_per1_hwmod,
2593 .slave = &dra7xx_i2c2_hwmod,
2594 .clk = "l3_iclk_div",
2595 .user = OCP_USER_MPU | OCP_USER_SDMA,
2596};
2597
2598/* l4_per1 -> i2c3 */
2599static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2600 .master = &dra7xx_l4_per1_hwmod,
2601 .slave = &dra7xx_i2c3_hwmod,
2602 .clk = "l3_iclk_div",
2603 .user = OCP_USER_MPU | OCP_USER_SDMA,
2604};
2605
2606/* l4_per1 -> i2c4 */
2607static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2608 .master = &dra7xx_l4_per1_hwmod,
2609 .slave = &dra7xx_i2c4_hwmod,
2610 .clk = "l3_iclk_div",
2611 .user = OCP_USER_MPU | OCP_USER_SDMA,
2612};
2613
2614/* l4_per1 -> i2c5 */
2615static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2616 .master = &dra7xx_l4_per1_hwmod,
2617 .slave = &dra7xx_i2c5_hwmod,
2618 .clk = "l3_iclk_div",
2619 .user = OCP_USER_MPU | OCP_USER_SDMA,
2620};
2621
067395d4
SA		 2622/* l4_cfg -> mailbox1 */
2623static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
2624 .master = &dra7xx_l4_cfg_hwmod,
2625 .slave = &dra7xx_mailbox1_hwmod,
2626 .clk = "l3_iclk_div",
2627 .user = OCP_USER_MPU | OCP_USER_SDMA,
2628};
2629
2630/* l4_per3 -> mailbox2 */
2631static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
2632 .master = &dra7xx_l4_per3_hwmod,
2633 .slave = &dra7xx_mailbox2_hwmod,
2634 .clk = "l3_iclk_div",
2635 .user = OCP_USER_MPU | OCP_USER_SDMA,
2636};
2637
2638/* l4_per3 -> mailbox3 */
2639static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
2640 .master = &dra7xx_l4_per3_hwmod,
2641 .slave = &dra7xx_mailbox3_hwmod,
2642 .clk = "l3_iclk_div",
2643 .user = OCP_USER_MPU | OCP_USER_SDMA,
2644};
2645
2646/* l4_per3 -> mailbox4 */
2647static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
2648 .master = &dra7xx_l4_per3_hwmod,
2649 .slave = &dra7xx_mailbox4_hwmod,
2650 .clk = "l3_iclk_div",
2651 .user = OCP_USER_MPU | OCP_USER_SDMA,
2652};
2653
2654/* l4_per3 -> mailbox5 */
2655static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
2656 .master = &dra7xx_l4_per3_hwmod,
2657 .slave = &dra7xx_mailbox5_hwmod,
2658 .clk = "l3_iclk_div",
2659 .user = OCP_USER_MPU | OCP_USER_SDMA,
2660};
2661
2662/* l4_per3 -> mailbox6 */
2663static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
2664 .master = &dra7xx_l4_per3_hwmod,
2665 .slave = &dra7xx_mailbox6_hwmod,
2666 .clk = "l3_iclk_div",
2667 .user = OCP_USER_MPU | OCP_USER_SDMA,
2668};
2669
2670/* l4_per3 -> mailbox7 */
2671static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
2672 .master = &dra7xx_l4_per3_hwmod,
2673 .slave = &dra7xx_mailbox7_hwmod,
2674 .clk = "l3_iclk_div",
2675 .user = OCP_USER_MPU | OCP_USER_SDMA,
2676};
2677
2678/* l4_per3 -> mailbox8 */
2679static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
2680 .master = &dra7xx_l4_per3_hwmod,
2681 .slave = &dra7xx_mailbox8_hwmod,
2682 .clk = "l3_iclk_div",
2683 .user = OCP_USER_MPU | OCP_USER_SDMA,
2684};
2685
2686/* l4_per3 -> mailbox9 */
2687static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
2688 .master = &dra7xx_l4_per3_hwmod,
2689 .slave = &dra7xx_mailbox9_hwmod,
2690 .clk = "l3_iclk_div",
2691 .user = OCP_USER_MPU | OCP_USER_SDMA,
2692};
2693
2694/* l4_per3 -> mailbox10 */
2695static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
2696 .master = &dra7xx_l4_per3_hwmod,
2697 .slave = &dra7xx_mailbox10_hwmod,
2698 .clk = "l3_iclk_div",
2699 .user = OCP_USER_MPU | OCP_USER_SDMA,
2700};
2701
2702/* l4_per3 -> mailbox11 */
2703static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
2704 .master = &dra7xx_l4_per3_hwmod,
2705 .slave = &dra7xx_mailbox11_hwmod,
2706 .clk = "l3_iclk_div",
2707 .user = OCP_USER_MPU | OCP_USER_SDMA,
2708};
2709
2710/* l4_per3 -> mailbox12 */
2711static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
2712 .master = &dra7xx_l4_per3_hwmod,
2713 .slave = &dra7xx_mailbox12_hwmod,
2714 .clk = "l3_iclk_div",
2715 .user = OCP_USER_MPU | OCP_USER_SDMA,
2716};
2717
2718/* l4_per3 -> mailbox13 */
2719static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
2720 .master = &dra7xx_l4_per3_hwmod,
2721 .slave = &dra7xx_mailbox13_hwmod,
2722 .clk = "l3_iclk_div",
2723 .user = OCP_USER_MPU | OCP_USER_SDMA,
2724};
2725
90020c7b
A		 2726/* l4_per1 -> mcspi1 */
2727static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2728 .master = &dra7xx_l4_per1_hwmod,
2729 .slave = &dra7xx_mcspi1_hwmod,
2730 .clk = "l3_iclk_div",
2731 .user = OCP_USER_MPU | OCP_USER_SDMA,
2732};
2733
2734/* l4_per1 -> mcspi2 */
2735static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2736 .master = &dra7xx_l4_per1_hwmod,
2737 .slave = &dra7xx_mcspi2_hwmod,
2738 .clk = "l3_iclk_div",
2739 .user = OCP_USER_MPU | OCP_USER_SDMA,
2740};
2741
2742/* l4_per1 -> mcspi3 */
2743static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2744 .master = &dra7xx_l4_per1_hwmod,
2745 .slave = &dra7xx_mcspi3_hwmod,
2746 .clk = "l3_iclk_div",
2747 .user = OCP_USER_MPU | OCP_USER_SDMA,
2748};
2749
2750/* l4_per1 -> mcspi4 */
2751static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2752 .master = &dra7xx_l4_per1_hwmod,
2753 .slave = &dra7xx_mcspi4_hwmod,
2754 .clk = "l3_iclk_div",
2755 .user = OCP_USER_MPU | OCP_USER_SDMA,
2756};
2757
2758/* l4_per1 -> mmc1 */
2759static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
2760 .master = &dra7xx_l4_per1_hwmod,
2761 .slave = &dra7xx_mmc1_hwmod,
2762 .clk = "l3_iclk_div",
2763 .user = OCP_USER_MPU | OCP_USER_SDMA,
2764};
2765
2766/* l4_per1 -> mmc2 */
2767static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
2768 .master = &dra7xx_l4_per1_hwmod,
2769 .slave = &dra7xx_mmc2_hwmod,
2770 .clk = "l3_iclk_div",
2771 .user = OCP_USER_MPU | OCP_USER_SDMA,
2772};
2773
2774/* l4_per1 -> mmc3 */
2775static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
2776 .master = &dra7xx_l4_per1_hwmod,
2777 .slave = &dra7xx_mmc3_hwmod,
2778 .clk = "l3_iclk_div",
2779 .user = OCP_USER_MPU | OCP_USER_SDMA,
2780};
2781
2782/* l4_per1 -> mmc4 */
2783static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
2784 .master = &dra7xx_l4_per1_hwmod,
2785 .slave = &dra7xx_mmc4_hwmod,
2786 .clk = "l3_iclk_div",
2787 .user = OCP_USER_MPU | OCP_USER_SDMA,
2788};
2789
2790/* l4_cfg -> mpu */
2791static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2792 .master = &dra7xx_l4_cfg_hwmod,
2793 .slave = &dra7xx_mpu_hwmod,
2794 .clk = "l3_iclk_div",
2795 .user = OCP_USER_MPU | OCP_USER_SDMA,
2796};
2797
90020c7b
A		 2798/* l4_cfg -> ocp2scp1 */
2799static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2800 .master = &dra7xx_l4_cfg_hwmod,
2801 .slave = &dra7xx_ocp2scp1_hwmod,
2802 .clk = "l4_root_clk_div",
90020c7b
A		 2803 .user = OCP_USER_MPU | OCP_USER_SDMA,
2804};
2805
df0d0f11
RQ		 2806/* l4_cfg -> ocp2scp3 */
2807static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
2808 .master = &dra7xx_l4_cfg_hwmod,
2809 .slave = &dra7xx_ocp2scp3_hwmod,
2810 .clk = "l4_root_clk_div",
2811 .user = OCP_USER_MPU | OCP_USER_SDMA,
2812};
2813
8dd3eb71
KVA		 2814/* l3_main_1 -> pcie1 */
2815static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
2816 .master = &dra7xx_l3_main_1_hwmod,
2817 .slave = &dra7xx_pcie1_hwmod,
2818 .clk = "l3_iclk_div",
2819 .user = OCP_USER_MPU | OCP_USER_SDMA,
2820};
2821
2822/* l4_cfg -> pcie1 */
2823static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
2824 .master = &dra7xx_l4_cfg_hwmod,
2825 .slave = &dra7xx_pcie1_hwmod,
2826 .clk = "l4_root_clk_div",
2827 .user = OCP_USER_MPU | OCP_USER_SDMA,
2828};
2829
2830/* l3_main_1 -> pcie2 */
2831static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
2832 .master = &dra7xx_l3_main_1_hwmod,
2833 .slave = &dra7xx_pcie2_hwmod,
2834 .clk = "l3_iclk_div",
2835 .user = OCP_USER_MPU | OCP_USER_SDMA,
2836};
2837
2838/* l4_cfg -> pcie2 */
2839static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
2840 .master = &dra7xx_l4_cfg_hwmod,
2841 .slave = &dra7xx_pcie2_hwmod,
2842 .clk = "l4_root_clk_div",
2843 .user = OCP_USER_MPU | OCP_USER_SDMA,
2844};
2845
70c18ef7
KVA		 2846/* l4_cfg -> pcie1 phy */
2847static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
2848 .master = &dra7xx_l4_cfg_hwmod,
2849 .slave = &dra7xx_pcie1_phy_hwmod,
2850 .clk = "l4_root_clk_div",
2851 .user = OCP_USER_MPU | OCP_USER_SDMA,
2852};
2853
2854/* l4_cfg -> pcie2 phy */
2855static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
2856 .master = &dra7xx_l4_cfg_hwmod,
2857 .slave = &dra7xx_pcie2_phy_hwmod,
2858 .clk = "l4_root_clk_div",
2859 .user = OCP_USER_MPU | OCP_USER_SDMA,
2860};
2861
90020c7b
A		 2862static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2863 {
2864 .pa_start = 0x4b300000,
2865 .pa_end = 0x4b30007f,
2866 .flags = ADDR_TYPE_RT
2867 },
2868 { }
2869};
2870
2871/* l3_main_1 -> qspi */
2872static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2873 .master = &dra7xx_l3_main_1_hwmod,
2874 .slave = &dra7xx_qspi_hwmod,
2875 .clk = "l3_iclk_div",
2876 .addr = dra7xx_qspi_addrs,
2877 .user = OCP_USER_MPU | OCP_USER_SDMA,
2878};
2879
c913c8a1
LV		 2880/* l4_per3 -> rtcss */
2881static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
2882 .master = &dra7xx_l4_per3_hwmod,
2883 .slave = &dra7xx_rtcss_hwmod,
2884 .clk = "l4_root_clk_div",
2885 .user = OCP_USER_MPU | OCP_USER_SDMA,
2886};
2887
90020c7b
A		 2888static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
2889 {
2890 .name = "sysc",
2891 .pa_start = 0x4a141100,
2892 .pa_end = 0x4a141107,
2893 .flags = ADDR_TYPE_RT
2894 },
2895 { }
2896};
2897
2898/* l4_cfg -> sata */
2899static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
2900 .master = &dra7xx_l4_cfg_hwmod,
2901 .slave = &dra7xx_sata_hwmod,
2902 .clk = "l3_iclk_div",
2903 .addr = dra7xx_sata_addrs,
2904 .user = OCP_USER_MPU | OCP_USER_SDMA,
2905};
2906
2907static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
2908 {
2909 .pa_start = 0x4a0dd000,
2910 .pa_end = 0x4a0dd07f,
2911 .flags = ADDR_TYPE_RT
2912 },
2913 { }
2914};
2915
2916/* l4_cfg -> smartreflex_core */
2917static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
2918 .master = &dra7xx_l4_cfg_hwmod,
2919 .slave = &dra7xx_smartreflex_core_hwmod,
2920 .clk = "l4_root_clk_div",
2921 .addr = dra7xx_smartreflex_core_addrs,
2922 .user = OCP_USER_MPU | OCP_USER_SDMA,
2923};
2924
2925static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
2926 {
2927 .pa_start = 0x4a0d9000,
2928 .pa_end = 0x4a0d907f,
2929 .flags = ADDR_TYPE_RT
2930 },
2931 { }
2932};
2933
2934/* l4_cfg -> smartreflex_mpu */
2935static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
2936 .master = &dra7xx_l4_cfg_hwmod,
2937 .slave = &dra7xx_smartreflex_mpu_hwmod,
2938 .clk = "l4_root_clk_div",
2939 .addr = dra7xx_smartreflex_mpu_addrs,
2940 .user = OCP_USER_MPU | OCP_USER_SDMA,
2941};
2942
2943static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
2944 {
2945 .pa_start = 0x4a0f6000,
2946 .pa_end = 0x4a0f6fff,
2947 .flags = ADDR_TYPE_RT
2948 },
2949 { }
2950};
2951
2952/* l4_cfg -> spinlock */
2953static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
2954 .master = &dra7xx_l4_cfg_hwmod,
2955 .slave = &dra7xx_spinlock_hwmod,
2956 .clk = "l3_iclk_div",
2957 .addr = dra7xx_spinlock_addrs,
2958 .user = OCP_USER_MPU | OCP_USER_SDMA,
2959};
2960
2961/* l4_wkup -> timer1 */
2962static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
2963 .master = &dra7xx_l4_wkup_hwmod,
2964 .slave = &dra7xx_timer1_hwmod,
2965 .clk = "wkupaon_iclk_mux",
2966 .user = OCP_USER_MPU | OCP_USER_SDMA,
2967};
2968
2969/* l4_per1 -> timer2 */
2970static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
2971 .master = &dra7xx_l4_per1_hwmod,
2972 .slave = &dra7xx_timer2_hwmod,
2973 .clk = "l3_iclk_div",
2974 .user = OCP_USER_MPU | OCP_USER_SDMA,
2975};
2976
2977/* l4_per1 -> timer3 */
2978static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
2979 .master = &dra7xx_l4_per1_hwmod,
2980 .slave = &dra7xx_timer3_hwmod,
2981 .clk = "l3_iclk_div",
2982 .user = OCP_USER_MPU | OCP_USER_SDMA,
2983};
2984
2985/* l4_per1 -> timer4 */
2986static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
2987 .master = &dra7xx_l4_per1_hwmod,
2988 .slave = &dra7xx_timer4_hwmod,
2989 .clk = "l3_iclk_div",
2990 .user = OCP_USER_MPU | OCP_USER_SDMA,
2991};
2992
2993/* l4_per3 -> timer5 */
2994static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
2995 .master = &dra7xx_l4_per3_hwmod,
2996 .slave = &dra7xx_timer5_hwmod,
2997 .clk = "l3_iclk_div",
2998 .user = OCP_USER_MPU | OCP_USER_SDMA,
2999};
3000
3001/* l4_per3 -> timer6 */
3002static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3003 .master = &dra7xx_l4_per3_hwmod,
3004 .slave = &dra7xx_timer6_hwmod,
3005 .clk = "l3_iclk_div",
3006 .user = OCP_USER_MPU | OCP_USER_SDMA,
3007};
3008
3009/* l4_per3 -> timer7 */
3010static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3011 .master = &dra7xx_l4_per3_hwmod,
3012 .slave = &dra7xx_timer7_hwmod,
3013 .clk = "l3_iclk_div",
3014 .user = OCP_USER_MPU | OCP_USER_SDMA,
3015};
3016
3017/* l4_per3 -> timer8 */
3018static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3019 .master = &dra7xx_l4_per3_hwmod,
3020 .slave = &dra7xx_timer8_hwmod,
3021 .clk = "l3_iclk_div",
3022 .user = OCP_USER_MPU | OCP_USER_SDMA,
3023};
3024
3025/* l4_per1 -> timer9 */
3026static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3027 .master = &dra7xx_l4_per1_hwmod,
3028 .slave = &dra7xx_timer9_hwmod,
3029 .clk = "l3_iclk_div",
3030 .user = OCP_USER_MPU | OCP_USER_SDMA,
3031};
3032
3033/* l4_per1 -> timer10 */
3034static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3035 .master = &dra7xx_l4_per1_hwmod,
3036 .slave = &dra7xx_timer10_hwmod,
3037 .clk = "l3_iclk_div",
3038 .user = OCP_USER_MPU | OCP_USER_SDMA,
3039};
3040
3041/* l4_per1 -> timer11 */
3042static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3043 .master = &dra7xx_l4_per1_hwmod,
3044 .slave = &dra7xx_timer11_hwmod,
3045 .clk = "l3_iclk_div",
3046 .user = OCP_USER_MPU | OCP_USER_SDMA,
3047};
3048
3049/* l4_per1 -> uart1 */
3050static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3051 .master = &dra7xx_l4_per1_hwmod,
3052 .slave = &dra7xx_uart1_hwmod,
3053 .clk = "l3_iclk_div",
3054 .user = OCP_USER_MPU | OCP_USER_SDMA,
3055};
3056
3057/* l4_per1 -> uart2 */
3058static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3059 .master = &dra7xx_l4_per1_hwmod,
3060 .slave = &dra7xx_uart2_hwmod,
3061 .clk = "l3_iclk_div",
3062 .user = OCP_USER_MPU | OCP_USER_SDMA,
3063};
3064
3065/* l4_per1 -> uart3 */
3066static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3067 .master = &dra7xx_l4_per1_hwmod,
3068 .slave = &dra7xx_uart3_hwmod,
3069 .clk = "l3_iclk_div",
3070 .user = OCP_USER_MPU | OCP_USER_SDMA,
3071};
3072
3073/* l4_per1 -> uart4 */
3074static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3075 .master = &dra7xx_l4_per1_hwmod,
3076 .slave = &dra7xx_uart4_hwmod,
3077 .clk = "l3_iclk_div",
3078 .user = OCP_USER_MPU | OCP_USER_SDMA,
3079};
3080
3081/* l4_per1 -> uart5 */
3082static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3083 .master = &dra7xx_l4_per1_hwmod,
3084 .slave = &dra7xx_uart5_hwmod,
3085 .clk = "l3_iclk_div",
3086 .user = OCP_USER_MPU | OCP_USER_SDMA,
3087};
3088
3089/* l4_per1 -> uart6 */
3090static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3091 .master = &dra7xx_l4_per1_hwmod,
3092 .slave = &dra7xx_uart6_hwmod,
3093 .clk = "l3_iclk_div",
3094 .user = OCP_USER_MPU | OCP_USER_SDMA,
3095};
3096
3097/* l4_per3 -> usb_otg_ss1 */
3098static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3099 .master = &dra7xx_l4_per3_hwmod,
3100 .slave = &dra7xx_usb_otg_ss1_hwmod,
3101 .clk = "dpll_core_h13x2_ck",
3102 .user = OCP_USER_MPU | OCP_USER_SDMA,
3103};
3104
3105/* l4_per3 -> usb_otg_ss2 */
3106static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3107 .master = &dra7xx_l4_per3_hwmod,
3108 .slave = &dra7xx_usb_otg_ss2_hwmod,
3109 .clk = "dpll_core_h13x2_ck",
3110 .user = OCP_USER_MPU | OCP_USER_SDMA,
3111};
3112
3113/* l4_per3 -> usb_otg_ss3 */
3114static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3115 .master = &dra7xx_l4_per3_hwmod,
3116 .slave = &dra7xx_usb_otg_ss3_hwmod,
3117 .clk = "dpll_core_h13x2_ck",
3118 .user = OCP_USER_MPU | OCP_USER_SDMA,
3119};
3120
3121/* l4_per3 -> usb_otg_ss4 */
3122static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3123 .master = &dra7xx_l4_per3_hwmod,
3124 .slave = &dra7xx_usb_otg_ss4_hwmod,
3125 .clk = "dpll_core_h13x2_ck",
3126 .user = OCP_USER_MPU | OCP_USER_SDMA,
3127};
3128
3129/* l3_main_1 -> vcp1 */
3130static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3131 .master = &dra7xx_l3_main_1_hwmod,
3132 .slave = &dra7xx_vcp1_hwmod,
3133 .clk = "l3_iclk_div",
3134 .user = OCP_USER_MPU | OCP_USER_SDMA,
3135};
3136
3137/* l4_per2 -> vcp1 */
3138static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3139 .master = &dra7xx_l4_per2_hwmod,
3140 .slave = &dra7xx_vcp1_hwmod,
3141 .clk = "l3_iclk_div",
3142 .user = OCP_USER_MPU | OCP_USER_SDMA,
3143};
3144
3145/* l3_main_1 -> vcp2 */
3146static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3147 .master = &dra7xx_l3_main_1_hwmod,
3148 .slave = &dra7xx_vcp2_hwmod,
3149 .clk = "l3_iclk_div",
3150 .user = OCP_USER_MPU | OCP_USER_SDMA,
3151};
3152
3153/* l4_per2 -> vcp2 */
3154static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3155 .master = &dra7xx_l4_per2_hwmod,
3156 .slave = &dra7xx_vcp2_hwmod,
3157 .clk = "l3_iclk_div",
3158 .user = OCP_USER_MPU | OCP_USER_SDMA,
3159};
3160
3161/* l4_wkup -> wd_timer2 */
3162static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3163 .master = &dra7xx_l4_wkup_hwmod,
3164 .slave = &dra7xx_wd_timer2_hwmod,
3165 .clk = "wkupaon_iclk_mux",
3166 .user = OCP_USER_MPU | OCP_USER_SDMA,
3167};
3168
3169static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3170 &dra7xx_l3_main_2__l3_instr,
3171 &dra7xx_l4_cfg__l3_main_1,
3172 &dra7xx_mpu__l3_main_1,
3173 &dra7xx_l3_main_1__l3_main_2,
3174 &dra7xx_l4_cfg__l3_main_2,
3175 &dra7xx_l3_main_1__l4_cfg,
3176 &dra7xx_l3_main_1__l4_per1,
3177 &dra7xx_l3_main_1__l4_per2,
3178 &dra7xx_l3_main_1__l4_per3,
3179 &dra7xx_l3_main_1__l4_wkup,
3180 &dra7xx_l4_per2__atl,
3181 &dra7xx_l3_main_1__bb2d,
3182 &dra7xx_l4_wkup__counter_32k,
3183 &dra7xx_l4_wkup__ctrl_module_wkup,
3184 &dra7xx_l4_wkup__dcan1,
3185 &dra7xx_l4_per2__dcan2,
077c42f7
M		 3186 &dra7xx_l4_per2__cpgmac0,
3187 &dra7xx_gmac__mdio,
90020c7b
A		 3188 &dra7xx_l4_cfg__dma_system,
3189 &dra7xx_l3_main_1__dss,
3190 &dra7xx_l3_main_1__dispc,
3191 &dra7xx_l3_main_1__hdmi,
3192 &dra7xx_l4_per1__elm,
3193 &dra7xx_l4_wkup__gpio1,
3194 &dra7xx_l4_per1__gpio2,
3195 &dra7xx_l4_per1__gpio3,
3196 &dra7xx_l4_per1__gpio4,
3197 &dra7xx_l4_per1__gpio5,
3198 &dra7xx_l4_per1__gpio6,
3199 &dra7xx_l4_per1__gpio7,
3200 &dra7xx_l4_per1__gpio8,
3201 &dra7xx_l3_main_1__gpmc,
3202 &dra7xx_l4_per1__hdq1w,
3203 &dra7xx_l4_per1__i2c1,
3204 &dra7xx_l4_per1__i2c2,
3205 &dra7xx_l4_per1__i2c3,
3206 &dra7xx_l4_per1__i2c4,
3207 &dra7xx_l4_per1__i2c5,
067395d4
SA		 3208 &dra7xx_l4_cfg__mailbox1,
3209 &dra7xx_l4_per3__mailbox2,
3210 &dra7xx_l4_per3__mailbox3,
3211 &dra7xx_l4_per3__mailbox4,
3212 &dra7xx_l4_per3__mailbox5,
3213 &dra7xx_l4_per3__mailbox6,
3214 &dra7xx_l4_per3__mailbox7,
3215 &dra7xx_l4_per3__mailbox8,
3216 &dra7xx_l4_per3__mailbox9,
3217 &dra7xx_l4_per3__mailbox10,
3218 &dra7xx_l4_per3__mailbox11,
3219 &dra7xx_l4_per3__mailbox12,
3220 &dra7xx_l4_per3__mailbox13,
90020c7b
A		 3221 &dra7xx_l4_per1__mcspi1,
3222 &dra7xx_l4_per1__mcspi2,
3223 &dra7xx_l4_per1__mcspi3,
3224 &dra7xx_l4_per1__mcspi4,
3225 &dra7xx_l4_per1__mmc1,
3226 &dra7xx_l4_per1__mmc2,
3227 &dra7xx_l4_per1__mmc3,
3228 &dra7xx_l4_per1__mmc4,
3229 &dra7xx_l4_cfg__mpu,
3230 &dra7xx_l4_cfg__ocp2scp1,
df0d0f11 3231 &dra7xx_l4_cfg__ocp2scp3,
8dd3eb71
KVA		 3232 &dra7xx_l3_main_1__pcie1,
3233 &dra7xx_l4_cfg__pcie1,
3234 &dra7xx_l3_main_1__pcie2,
3235 &dra7xx_l4_cfg__pcie2,
70c18ef7
KVA		 3236 &dra7xx_l4_cfg__pcie1_phy,
3237 &dra7xx_l4_cfg__pcie2_phy,
90020c7b 3238 &dra7xx_l3_main_1__qspi,
c913c8a1 3239 &dra7xx_l4_per3__rtcss,
90020c7b
A		 3240 &dra7xx_l4_cfg__sata,
3241 &dra7xx_l4_cfg__smartreflex_core,
3242 &dra7xx_l4_cfg__smartreflex_mpu,
3243 &dra7xx_l4_cfg__spinlock,
3244 &dra7xx_l4_wkup__timer1,
3245 &dra7xx_l4_per1__timer2,
3246 &dra7xx_l4_per1__timer3,
3247 &dra7xx_l4_per1__timer4,
3248 &dra7xx_l4_per3__timer5,
3249 &dra7xx_l4_per3__timer6,
3250 &dra7xx_l4_per3__timer7,
3251 &dra7xx_l4_per3__timer8,
3252 &dra7xx_l4_per1__timer9,
3253 &dra7xx_l4_per1__timer10,
3254 &dra7xx_l4_per1__timer11,
3255 &dra7xx_l4_per1__uart1,
3256 &dra7xx_l4_per1__uart2,
3257 &dra7xx_l4_per1__uart3,
3258 &dra7xx_l4_per1__uart4,
3259 &dra7xx_l4_per1__uart5,
3260 &dra7xx_l4_per1__uart6,
3261 &dra7xx_l4_per3__usb_otg_ss1,
3262 &dra7xx_l4_per3__usb_otg_ss2,
3263 &dra7xx_l4_per3__usb_otg_ss3,
3264 &dra7xx_l4_per3__usb_otg_ss4,
3265 &dra7xx_l3_main_1__vcp1,
3266 &dra7xx_l4_per2__vcp1,
3267 &dra7xx_l3_main_1__vcp2,
3268 &dra7xx_l4_per2__vcp2,
3269 &dra7xx_l4_wkup__wd_timer2,
3270 NULL,
3271};
3272
3273int __init dra7xx_hwmod_init(void)
3274{
3275 omap_hwmod_init();
3276 return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3277}
Linux kernel - Deliverables
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