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90020c7b A |
1 | /* |
2 | * Hardware modules present on the DRA7xx chips | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com | |
5 | * | |
6 | * Paul Walmsley | |
7 | * Benoit Cousson | |
8 | * | |
9 | * This file is automatically generated from the OMAP hardware databases. | |
10 | * We respectfully ask that any modifications to this file be coordinated | |
11 | * with the public linux-omap@vger.kernel.org mailing list and the | |
12 | * authors above to ensure that the autogeneration scripts are kept | |
13 | * up-to-date with the file contents. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
19 | ||
20 | #include <linux/io.h> | |
21 | #include <linux/platform_data/gpio-omap.h> | |
55143438 | 22 | #include <linux/platform_data/hsmmc-omap.h> |
90020c7b A |
23 | #include <linux/power/smartreflex.h> |
24 | #include <linux/i2c-omap.h> | |
25 | ||
26 | #include <linux/omap-dma.h> | |
27 | #include <linux/platform_data/spi-omap2-mcspi.h> | |
28 | #include <linux/platform_data/asoc-ti-mcbsp.h> | |
29 | #include <plat/dmtimer.h> | |
30 | ||
31 | #include "omap_hwmod.h" | |
32 | #include "omap_hwmod_common_data.h" | |
33 | #include "cm1_7xx.h" | |
34 | #include "cm2_7xx.h" | |
35 | #include "prm7xx.h" | |
36 | #include "i2c.h" | |
90020c7b | 37 | #include "wd_timer.h" |
f7f7a29b | 38 | #include "soc.h" |
90020c7b A |
39 | |
40 | /* Base offset for all DRA7XX interrupts external to MPUSS */ | |
41 | #define DRA7XX_IRQ_GIC_START 32 | |
42 | ||
43 | /* Base offset for all DRA7XX dma requests */ | |
44 | #define DRA7XX_DMA_REQ_START 1 | |
45 | ||
46 | ||
47 | /* | |
48 | * IP blocks | |
49 | */ | |
50 | ||
42121688 TV |
51 | /* |
52 | * 'dmm' class | |
53 | * instance(s): dmm | |
54 | */ | |
55 | static struct omap_hwmod_class dra7xx_dmm_hwmod_class = { | |
56 | .name = "dmm", | |
57 | }; | |
58 | ||
59 | /* dmm */ | |
60 | static struct omap_hwmod dra7xx_dmm_hwmod = { | |
61 | .name = "dmm", | |
62 | .class = &dra7xx_dmm_hwmod_class, | |
63 | .clkdm_name = "emif_clkdm", | |
64 | .prcm = { | |
65 | .omap4 = { | |
66 | .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET, | |
67 | .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET, | |
68 | }, | |
69 | }, | |
70 | }; | |
71 | ||
90020c7b A |
72 | /* |
73 | * 'l3' class | |
74 | * instance(s): l3_instr, l3_main_1, l3_main_2 | |
75 | */ | |
76 | static struct omap_hwmod_class dra7xx_l3_hwmod_class = { | |
77 | .name = "l3", | |
78 | }; | |
79 | ||
80 | /* l3_instr */ | |
81 | static struct omap_hwmod dra7xx_l3_instr_hwmod = { | |
82 | .name = "l3_instr", | |
83 | .class = &dra7xx_l3_hwmod_class, | |
84 | .clkdm_name = "l3instr_clkdm", | |
85 | .prcm = { | |
86 | .omap4 = { | |
87 | .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, | |
88 | .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, | |
89 | .modulemode = MODULEMODE_HWCTRL, | |
90 | }, | |
91 | }, | |
92 | }; | |
93 | ||
94 | /* l3_main_1 */ | |
95 | static struct omap_hwmod dra7xx_l3_main_1_hwmod = { | |
96 | .name = "l3_main_1", | |
97 | .class = &dra7xx_l3_hwmod_class, | |
98 | .clkdm_name = "l3main1_clkdm", | |
99 | .prcm = { | |
100 | .omap4 = { | |
101 | .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET, | |
102 | .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET, | |
103 | }, | |
104 | }, | |
105 | }; | |
106 | ||
107 | /* l3_main_2 */ | |
108 | static struct omap_hwmod dra7xx_l3_main_2_hwmod = { | |
109 | .name = "l3_main_2", | |
110 | .class = &dra7xx_l3_hwmod_class, | |
111 | .clkdm_name = "l3instr_clkdm", | |
112 | .prcm = { | |
113 | .omap4 = { | |
114 | .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET, | |
115 | .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET, | |
116 | .modulemode = MODULEMODE_HWCTRL, | |
117 | }, | |
118 | }, | |
119 | }; | |
120 | ||
121 | /* | |
122 | * 'l4' class | |
123 | * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup | |
124 | */ | |
125 | static struct omap_hwmod_class dra7xx_l4_hwmod_class = { | |
126 | .name = "l4", | |
127 | }; | |
128 | ||
129 | /* l4_cfg */ | |
130 | static struct omap_hwmod dra7xx_l4_cfg_hwmod = { | |
131 | .name = "l4_cfg", | |
132 | .class = &dra7xx_l4_hwmod_class, | |
133 | .clkdm_name = "l4cfg_clkdm", | |
134 | .prcm = { | |
135 | .omap4 = { | |
136 | .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, | |
137 | .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, | |
138 | }, | |
139 | }, | |
140 | }; | |
141 | ||
142 | /* l4_per1 */ | |
143 | static struct omap_hwmod dra7xx_l4_per1_hwmod = { | |
144 | .name = "l4_per1", | |
145 | .class = &dra7xx_l4_hwmod_class, | |
146 | .clkdm_name = "l4per_clkdm", | |
147 | .prcm = { | |
148 | .omap4 = { | |
149 | .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET, | |
150 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
151 | }, | |
152 | }, | |
153 | }; | |
154 | ||
155 | /* l4_per2 */ | |
156 | static struct omap_hwmod dra7xx_l4_per2_hwmod = { | |
157 | .name = "l4_per2", | |
158 | .class = &dra7xx_l4_hwmod_class, | |
159 | .clkdm_name = "l4per2_clkdm", | |
160 | .prcm = { | |
161 | .omap4 = { | |
162 | .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET, | |
163 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
164 | }, | |
165 | }, | |
166 | }; | |
167 | ||
168 | /* l4_per3 */ | |
169 | static struct omap_hwmod dra7xx_l4_per3_hwmod = { | |
170 | .name = "l4_per3", | |
171 | .class = &dra7xx_l4_hwmod_class, | |
172 | .clkdm_name = "l4per3_clkdm", | |
173 | .prcm = { | |
174 | .omap4 = { | |
175 | .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET, | |
176 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
177 | }, | |
178 | }, | |
179 | }; | |
180 | ||
181 | /* l4_wkup */ | |
182 | static struct omap_hwmod dra7xx_l4_wkup_hwmod = { | |
183 | .name = "l4_wkup", | |
184 | .class = &dra7xx_l4_hwmod_class, | |
185 | .clkdm_name = "wkupaon_clkdm", | |
186 | .prcm = { | |
187 | .omap4 = { | |
188 | .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET, | |
189 | .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET, | |
190 | }, | |
191 | }, | |
192 | }; | |
193 | ||
194 | /* | |
195 | * 'atl' class | |
196 | * | |
197 | */ | |
198 | ||
199 | static struct omap_hwmod_class dra7xx_atl_hwmod_class = { | |
200 | .name = "atl", | |
201 | }; | |
202 | ||
203 | /* atl */ | |
204 | static struct omap_hwmod dra7xx_atl_hwmod = { | |
205 | .name = "atl", | |
206 | .class = &dra7xx_atl_hwmod_class, | |
207 | .clkdm_name = "atl_clkdm", | |
208 | .main_clk = "atl_gfclk_mux", | |
209 | .prcm = { | |
210 | .omap4 = { | |
211 | .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET, | |
212 | .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET, | |
213 | .modulemode = MODULEMODE_SWCTRL, | |
214 | }, | |
215 | }, | |
216 | }; | |
217 | ||
218 | /* | |
219 | * 'bb2d' class | |
220 | * | |
221 | */ | |
222 | ||
223 | static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = { | |
224 | .name = "bb2d", | |
225 | }; | |
226 | ||
227 | /* bb2d */ | |
228 | static struct omap_hwmod dra7xx_bb2d_hwmod = { | |
229 | .name = "bb2d", | |
230 | .class = &dra7xx_bb2d_hwmod_class, | |
231 | .clkdm_name = "dss_clkdm", | |
232 | .main_clk = "dpll_core_h24x2_ck", | |
233 | .prcm = { | |
234 | .omap4 = { | |
235 | .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET, | |
236 | .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET, | |
237 | .modulemode = MODULEMODE_SWCTRL, | |
238 | }, | |
239 | }, | |
240 | }; | |
241 | ||
242 | /* | |
243 | * 'counter' class | |
244 | * | |
245 | */ | |
246 | ||
247 | static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = { | |
248 | .rev_offs = 0x0000, | |
249 | .sysc_offs = 0x0010, | |
250 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
251 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
252 | SIDLE_SMART_WKUP), | |
253 | .sysc_fields = &omap_hwmod_sysc_type1, | |
254 | }; | |
255 | ||
256 | static struct omap_hwmod_class dra7xx_counter_hwmod_class = { | |
257 | .name = "counter", | |
258 | .sysc = &dra7xx_counter_sysc, | |
259 | }; | |
260 | ||
261 | /* counter_32k */ | |
262 | static struct omap_hwmod dra7xx_counter_32k_hwmod = { | |
263 | .name = "counter_32k", | |
264 | .class = &dra7xx_counter_hwmod_class, | |
265 | .clkdm_name = "wkupaon_clkdm", | |
266 | .flags = HWMOD_SWSUP_SIDLE, | |
267 | .main_clk = "wkupaon_iclk_mux", | |
268 | .prcm = { | |
269 | .omap4 = { | |
270 | .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET, | |
271 | .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET, | |
272 | }, | |
273 | }, | |
274 | }; | |
275 | ||
276 | /* | |
277 | * 'ctrl_module' class | |
278 | * | |
279 | */ | |
280 | ||
281 | static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = { | |
282 | .name = "ctrl_module", | |
283 | }; | |
284 | ||
285 | /* ctrl_module_wkup */ | |
286 | static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = { | |
287 | .name = "ctrl_module_wkup", | |
288 | .class = &dra7xx_ctrl_module_hwmod_class, | |
289 | .clkdm_name = "wkupaon_clkdm", | |
290 | .prcm = { | |
291 | .omap4 = { | |
292 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
293 | }, | |
294 | }, | |
295 | }; | |
296 | ||
077c42f7 M |
297 | /* |
298 | * 'gmac' class | |
299 | * cpsw/gmac sub system | |
300 | */ | |
301 | static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = { | |
302 | .rev_offs = 0x0, | |
303 | .sysc_offs = 0x8, | |
304 | .syss_offs = 0x4, | |
305 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | | |
306 | SYSS_HAS_RESET_STATUS), | |
307 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | | |
308 | MSTANDBY_NO), | |
309 | .sysc_fields = &omap_hwmod_sysc_type3, | |
310 | }; | |
311 | ||
312 | static struct omap_hwmod_class dra7xx_gmac_hwmod_class = { | |
313 | .name = "gmac", | |
314 | .sysc = &dra7xx_gmac_sysc, | |
315 | }; | |
316 | ||
317 | static struct omap_hwmod dra7xx_gmac_hwmod = { | |
318 | .name = "gmac", | |
319 | .class = &dra7xx_gmac_hwmod_class, | |
320 | .clkdm_name = "gmac_clkdm", | |
321 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), | |
322 | .main_clk = "dpll_gmac_ck", | |
323 | .mpu_rt_idx = 1, | |
324 | .prcm = { | |
325 | .omap4 = { | |
326 | .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET, | |
327 | .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET, | |
328 | .modulemode = MODULEMODE_SWCTRL, | |
329 | }, | |
330 | }, | |
331 | }; | |
332 | ||
333 | /* | |
334 | * 'mdio' class | |
335 | */ | |
336 | static struct omap_hwmod_class dra7xx_mdio_hwmod_class = { | |
337 | .name = "davinci_mdio", | |
338 | }; | |
339 | ||
340 | static struct omap_hwmod dra7xx_mdio_hwmod = { | |
341 | .name = "davinci_mdio", | |
342 | .class = &dra7xx_mdio_hwmod_class, | |
343 | .clkdm_name = "gmac_clkdm", | |
344 | .main_clk = "dpll_gmac_ck", | |
345 | }; | |
346 | ||
90020c7b A |
347 | /* |
348 | * 'dcan' class | |
349 | * | |
350 | */ | |
351 | ||
352 | static struct omap_hwmod_class dra7xx_dcan_hwmod_class = { | |
353 | .name = "dcan", | |
354 | }; | |
355 | ||
356 | /* dcan1 */ | |
357 | static struct omap_hwmod dra7xx_dcan1_hwmod = { | |
358 | .name = "dcan1", | |
359 | .class = &dra7xx_dcan_hwmod_class, | |
360 | .clkdm_name = "wkupaon_clkdm", | |
361 | .main_clk = "dcan1_sys_clk_mux", | |
362 | .prcm = { | |
363 | .omap4 = { | |
364 | .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET, | |
365 | .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET, | |
366 | .modulemode = MODULEMODE_SWCTRL, | |
367 | }, | |
368 | }, | |
369 | }; | |
370 | ||
371 | /* dcan2 */ | |
372 | static struct omap_hwmod dra7xx_dcan2_hwmod = { | |
373 | .name = "dcan2", | |
374 | .class = &dra7xx_dcan_hwmod_class, | |
375 | .clkdm_name = "l4per2_clkdm", | |
376 | .main_clk = "sys_clkin1", | |
377 | .prcm = { | |
378 | .omap4 = { | |
379 | .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET, | |
380 | .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET, | |
381 | .modulemode = MODULEMODE_SWCTRL, | |
382 | }, | |
383 | }, | |
384 | }; | |
385 | ||
b05ff3c3 V |
386 | /* pwmss */ |
387 | static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = { | |
388 | .rev_offs = 0x0, | |
389 | .sysc_offs = 0x4, | |
390 | .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET, | |
391 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
392 | .sysc_fields = &omap_hwmod_sysc_type2, | |
393 | }; | |
394 | ||
395 | /* | |
396 | * epwmss class | |
397 | */ | |
398 | static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = { | |
399 | .name = "epwmss", | |
400 | .sysc = &dra7xx_epwmss_sysc, | |
401 | }; | |
402 | ||
403 | /* epwmss0 */ | |
404 | static struct omap_hwmod dra7xx_epwmss0_hwmod = { | |
405 | .name = "epwmss0", | |
406 | .class = &dra7xx_epwmss_hwmod_class, | |
407 | .clkdm_name = "l4per2_clkdm", | |
408 | .main_clk = "l4_root_clk_div", | |
409 | .prcm = { | |
410 | .omap4 = { | |
411 | .modulemode = MODULEMODE_SWCTRL, | |
412 | .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET, | |
413 | .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET, | |
414 | }, | |
415 | }, | |
416 | }; | |
417 | ||
418 | /* epwmss1 */ | |
419 | static struct omap_hwmod dra7xx_epwmss1_hwmod = { | |
420 | .name = "epwmss1", | |
421 | .class = &dra7xx_epwmss_hwmod_class, | |
422 | .clkdm_name = "l4per2_clkdm", | |
423 | .main_clk = "l4_root_clk_div", | |
424 | .prcm = { | |
425 | .omap4 = { | |
426 | .modulemode = MODULEMODE_SWCTRL, | |
427 | .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET, | |
428 | .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET, | |
429 | }, | |
430 | }, | |
431 | }; | |
432 | ||
433 | /* epwmss2 */ | |
434 | static struct omap_hwmod dra7xx_epwmss2_hwmod = { | |
435 | .name = "epwmss2", | |
436 | .class = &dra7xx_epwmss_hwmod_class, | |
437 | .clkdm_name = "l4per2_clkdm", | |
438 | .main_clk = "l4_root_clk_div", | |
439 | .prcm = { | |
440 | .omap4 = { | |
441 | .modulemode = MODULEMODE_SWCTRL, | |
442 | .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET, | |
443 | .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET, | |
444 | }, | |
445 | }, | |
446 | }; | |
447 | ||
90020c7b A |
448 | /* |
449 | * 'dma' class | |
450 | * | |
451 | */ | |
452 | ||
453 | static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = { | |
454 | .rev_offs = 0x0000, | |
455 | .sysc_offs = 0x002c, | |
456 | .syss_offs = 0x0028, | |
457 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
458 | SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
459 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
460 | SYSS_HAS_RESET_STATUS), | |
461 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
462 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
463 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
464 | .sysc_fields = &omap_hwmod_sysc_type1, | |
465 | }; | |
466 | ||
467 | static struct omap_hwmod_class dra7xx_dma_hwmod_class = { | |
468 | .name = "dma", | |
469 | .sysc = &dra7xx_dma_sysc, | |
470 | }; | |
471 | ||
472 | /* dma dev_attr */ | |
473 | static struct omap_dma_dev_attr dma_dev_attr = { | |
474 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
475 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
476 | .lch_count = 32, | |
477 | }; | |
478 | ||
479 | /* dma_system */ | |
90020c7b A |
480 | static struct omap_hwmod dra7xx_dma_system_hwmod = { |
481 | .name = "dma_system", | |
482 | .class = &dra7xx_dma_hwmod_class, | |
483 | .clkdm_name = "dma_clkdm", | |
90020c7b A |
484 | .main_clk = "l3_iclk_div", |
485 | .prcm = { | |
486 | .omap4 = { | |
487 | .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET, | |
488 | .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET, | |
489 | }, | |
490 | }, | |
491 | .dev_attr = &dma_dev_attr, | |
492 | }; | |
493 | ||
34b4182c PU |
494 | /* |
495 | * 'tpcc' class | |
496 | * | |
497 | */ | |
498 | static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = { | |
499 | .name = "tpcc", | |
500 | }; | |
501 | ||
502 | static struct omap_hwmod dra7xx_tpcc_hwmod = { | |
503 | .name = "tpcc", | |
504 | .class = &dra7xx_tpcc_hwmod_class, | |
505 | .clkdm_name = "l3main1_clkdm", | |
506 | .main_clk = "l3_iclk_div", | |
507 | .prcm = { | |
508 | .omap4 = { | |
509 | .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET, | |
510 | .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET, | |
511 | }, | |
512 | }, | |
513 | }; | |
514 | ||
515 | /* | |
516 | * 'tptc' class | |
517 | * | |
518 | */ | |
519 | static struct omap_hwmod_class dra7xx_tptc_hwmod_class = { | |
520 | .name = "tptc", | |
521 | }; | |
522 | ||
523 | /* tptc0 */ | |
524 | static struct omap_hwmod dra7xx_tptc0_hwmod = { | |
525 | .name = "tptc0", | |
526 | .class = &dra7xx_tptc_hwmod_class, | |
527 | .clkdm_name = "l3main1_clkdm", | |
528 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | |
529 | .main_clk = "l3_iclk_div", | |
530 | .prcm = { | |
531 | .omap4 = { | |
532 | .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET, | |
533 | .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET, | |
534 | .modulemode = MODULEMODE_HWCTRL, | |
535 | }, | |
536 | }, | |
537 | }; | |
538 | ||
539 | /* tptc1 */ | |
540 | static struct omap_hwmod dra7xx_tptc1_hwmod = { | |
541 | .name = "tptc1", | |
542 | .class = &dra7xx_tptc_hwmod_class, | |
543 | .clkdm_name = "l3main1_clkdm", | |
544 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | |
545 | .main_clk = "l3_iclk_div", | |
546 | .prcm = { | |
547 | .omap4 = { | |
548 | .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET, | |
549 | .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET, | |
550 | .modulemode = MODULEMODE_HWCTRL, | |
551 | }, | |
552 | }, | |
553 | }; | |
554 | ||
90020c7b A |
555 | /* |
556 | * 'dss' class | |
557 | * | |
558 | */ | |
559 | ||
560 | static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = { | |
561 | .rev_offs = 0x0000, | |
562 | .syss_offs = 0x0014, | |
563 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
564 | }; | |
565 | ||
566 | static struct omap_hwmod_class dra7xx_dss_hwmod_class = { | |
567 | .name = "dss", | |
568 | .sysc = &dra7xx_dss_sysc, | |
569 | .reset = omap_dss_reset, | |
570 | }; | |
571 | ||
572 | /* dss */ | |
573 | static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = { | |
574 | { .dma_req = 75 + DRA7XX_DMA_REQ_START }, | |
575 | { .dma_req = -1 } | |
576 | }; | |
577 | ||
578 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |
579 | { .role = "dss_clk", .clk = "dss_dss_clk" }, | |
580 | { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" }, | |
581 | { .role = "32khz_clk", .clk = "dss_32khz_clk" }, | |
582 | { .role = "video2_clk", .clk = "dss_video2_clk" }, | |
583 | { .role = "video1_clk", .clk = "dss_video1_clk" }, | |
584 | { .role = "hdmi_clk", .clk = "dss_hdmi_clk" }, | |
2d5a3c80 | 585 | { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" }, |
90020c7b A |
586 | }; |
587 | ||
588 | static struct omap_hwmod dra7xx_dss_hwmod = { | |
589 | .name = "dss_core", | |
590 | .class = &dra7xx_dss_hwmod_class, | |
591 | .clkdm_name = "dss_clkdm", | |
592 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
593 | .sdma_reqs = dra7xx_dss_sdma_reqs, | |
594 | .main_clk = "dss_dss_clk", | |
595 | .prcm = { | |
596 | .omap4 = { | |
597 | .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET, | |
598 | .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET, | |
599 | .modulemode = MODULEMODE_SWCTRL, | |
600 | }, | |
601 | }, | |
602 | .opt_clks = dss_opt_clks, | |
603 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
604 | }; | |
605 | ||
606 | /* | |
607 | * 'dispc' class | |
608 | * display controller | |
609 | */ | |
610 | ||
611 | static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = { | |
612 | .rev_offs = 0x0000, | |
613 | .sysc_offs = 0x0010, | |
614 | .syss_offs = 0x0014, | |
615 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
616 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | | |
617 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
618 | SYSS_HAS_RESET_STATUS), | |
619 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
620 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
621 | .sysc_fields = &omap_hwmod_sysc_type1, | |
622 | }; | |
623 | ||
624 | static struct omap_hwmod_class dra7xx_dispc_hwmod_class = { | |
625 | .name = "dispc", | |
626 | .sysc = &dra7xx_dispc_sysc, | |
627 | }; | |
628 | ||
629 | /* dss_dispc */ | |
630 | /* dss_dispc dev_attr */ | |
631 | static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = { | |
632 | .has_framedonetv_irq = 1, | |
633 | .manager_count = 4, | |
634 | }; | |
635 | ||
636 | static struct omap_hwmod dra7xx_dss_dispc_hwmod = { | |
637 | .name = "dss_dispc", | |
638 | .class = &dra7xx_dispc_hwmod_class, | |
639 | .clkdm_name = "dss_clkdm", | |
640 | .main_clk = "dss_dss_clk", | |
641 | .prcm = { | |
642 | .omap4 = { | |
643 | .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET, | |
644 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
645 | }, | |
646 | }, | |
647 | .dev_attr = &dss_dispc_dev_attr, | |
a3818c6d | 648 | .parent_hwmod = &dra7xx_dss_hwmod, |
90020c7b A |
649 | }; |
650 | ||
651 | /* | |
652 | * 'hdmi' class | |
653 | * hdmi controller | |
654 | */ | |
655 | ||
656 | static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = { | |
657 | .rev_offs = 0x0000, | |
658 | .sysc_offs = 0x0010, | |
659 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
660 | SYSC_HAS_SOFTRESET), | |
661 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
662 | SIDLE_SMART_WKUP), | |
663 | .sysc_fields = &omap_hwmod_sysc_type2, | |
664 | }; | |
665 | ||
666 | static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = { | |
667 | .name = "hdmi", | |
668 | .sysc = &dra7xx_hdmi_sysc, | |
669 | }; | |
670 | ||
671 | /* dss_hdmi */ | |
672 | ||
673 | static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { | |
674 | { .role = "sys_clk", .clk = "dss_hdmi_clk" }, | |
675 | }; | |
676 | ||
677 | static struct omap_hwmod dra7xx_dss_hdmi_hwmod = { | |
678 | .name = "dss_hdmi", | |
679 | .class = &dra7xx_hdmi_hwmod_class, | |
680 | .clkdm_name = "dss_clkdm", | |
681 | .main_clk = "dss_48mhz_clk", | |
682 | .prcm = { | |
683 | .omap4 = { | |
684 | .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET, | |
685 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
686 | }, | |
687 | }, | |
688 | .opt_clks = dss_hdmi_opt_clks, | |
689 | .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), | |
a3818c6d | 690 | .parent_hwmod = &dra7xx_dss_hwmod, |
90020c7b A |
691 | }; |
692 | ||
693 | /* | |
694 | * 'elm' class | |
695 | * | |
696 | */ | |
697 | ||
698 | static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = { | |
699 | .rev_offs = 0x0000, | |
700 | .sysc_offs = 0x0010, | |
701 | .syss_offs = 0x0014, | |
702 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
703 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
704 | SYSS_HAS_RESET_STATUS), | |
705 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
706 | SIDLE_SMART_WKUP), | |
707 | .sysc_fields = &omap_hwmod_sysc_type1, | |
708 | }; | |
709 | ||
710 | static struct omap_hwmod_class dra7xx_elm_hwmod_class = { | |
711 | .name = "elm", | |
712 | .sysc = &dra7xx_elm_sysc, | |
713 | }; | |
714 | ||
715 | /* elm */ | |
716 | ||
717 | static struct omap_hwmod dra7xx_elm_hwmod = { | |
718 | .name = "elm", | |
719 | .class = &dra7xx_elm_hwmod_class, | |
720 | .clkdm_name = "l4per_clkdm", | |
721 | .main_clk = "l3_iclk_div", | |
722 | .prcm = { | |
723 | .omap4 = { | |
724 | .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET, | |
725 | .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET, | |
726 | }, | |
727 | }, | |
728 | }; | |
729 | ||
730 | /* | |
731 | * 'gpio' class | |
732 | * | |
733 | */ | |
734 | ||
735 | static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = { | |
736 | .rev_offs = 0x0000, | |
737 | .sysc_offs = 0x0010, | |
738 | .syss_offs = 0x0114, | |
739 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
740 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
741 | SYSS_HAS_RESET_STATUS), | |
742 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
743 | SIDLE_SMART_WKUP), | |
744 | .sysc_fields = &omap_hwmod_sysc_type1, | |
745 | }; | |
746 | ||
747 | static struct omap_hwmod_class dra7xx_gpio_hwmod_class = { | |
748 | .name = "gpio", | |
749 | .sysc = &dra7xx_gpio_sysc, | |
750 | .rev = 2, | |
751 | }; | |
752 | ||
753 | /* gpio dev_attr */ | |
754 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
755 | .bank_width = 32, | |
756 | .dbck_flag = true, | |
757 | }; | |
758 | ||
759 | /* gpio1 */ | |
760 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | |
761 | { .role = "dbclk", .clk = "gpio1_dbclk" }, | |
762 | }; | |
763 | ||
764 | static struct omap_hwmod dra7xx_gpio1_hwmod = { | |
765 | .name = "gpio1", | |
766 | .class = &dra7xx_gpio_hwmod_class, | |
767 | .clkdm_name = "wkupaon_clkdm", | |
768 | .main_clk = "wkupaon_iclk_mux", | |
769 | .prcm = { | |
770 | .omap4 = { | |
771 | .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET, | |
772 | .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET, | |
773 | .modulemode = MODULEMODE_HWCTRL, | |
774 | }, | |
775 | }, | |
776 | .opt_clks = gpio1_opt_clks, | |
777 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
778 | .dev_attr = &gpio_dev_attr, | |
779 | }; | |
780 | ||
781 | /* gpio2 */ | |
782 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | |
783 | { .role = "dbclk", .clk = "gpio2_dbclk" }, | |
784 | }; | |
785 | ||
786 | static struct omap_hwmod dra7xx_gpio2_hwmod = { | |
787 | .name = "gpio2", | |
788 | .class = &dra7xx_gpio_hwmod_class, | |
789 | .clkdm_name = "l4per_clkdm", | |
790 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
791 | .main_clk = "l3_iclk_div", | |
792 | .prcm = { | |
793 | .omap4 = { | |
794 | .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET, | |
795 | .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET, | |
796 | .modulemode = MODULEMODE_HWCTRL, | |
797 | }, | |
798 | }, | |
799 | .opt_clks = gpio2_opt_clks, | |
800 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
801 | .dev_attr = &gpio_dev_attr, | |
802 | }; | |
803 | ||
804 | /* gpio3 */ | |
805 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { | |
806 | { .role = "dbclk", .clk = "gpio3_dbclk" }, | |
807 | }; | |
808 | ||
809 | static struct omap_hwmod dra7xx_gpio3_hwmod = { | |
810 | .name = "gpio3", | |
811 | .class = &dra7xx_gpio_hwmod_class, | |
812 | .clkdm_name = "l4per_clkdm", | |
813 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
814 | .main_clk = "l3_iclk_div", | |
815 | .prcm = { | |
816 | .omap4 = { | |
817 | .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET, | |
818 | .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET, | |
819 | .modulemode = MODULEMODE_HWCTRL, | |
820 | }, | |
821 | }, | |
822 | .opt_clks = gpio3_opt_clks, | |
823 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
824 | .dev_attr = &gpio_dev_attr, | |
825 | }; | |
826 | ||
827 | /* gpio4 */ | |
828 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { | |
829 | { .role = "dbclk", .clk = "gpio4_dbclk" }, | |
830 | }; | |
831 | ||
832 | static struct omap_hwmod dra7xx_gpio4_hwmod = { | |
833 | .name = "gpio4", | |
834 | .class = &dra7xx_gpio_hwmod_class, | |
835 | .clkdm_name = "l4per_clkdm", | |
836 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
837 | .main_clk = "l3_iclk_div", | |
838 | .prcm = { | |
839 | .omap4 = { | |
840 | .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET, | |
841 | .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET, | |
842 | .modulemode = MODULEMODE_HWCTRL, | |
843 | }, | |
844 | }, | |
845 | .opt_clks = gpio4_opt_clks, | |
846 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
847 | .dev_attr = &gpio_dev_attr, | |
848 | }; | |
849 | ||
850 | /* gpio5 */ | |
851 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { | |
852 | { .role = "dbclk", .clk = "gpio5_dbclk" }, | |
853 | }; | |
854 | ||
855 | static struct omap_hwmod dra7xx_gpio5_hwmod = { | |
856 | .name = "gpio5", | |
857 | .class = &dra7xx_gpio_hwmod_class, | |
858 | .clkdm_name = "l4per_clkdm", | |
859 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
860 | .main_clk = "l3_iclk_div", | |
861 | .prcm = { | |
862 | .omap4 = { | |
863 | .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET, | |
864 | .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET, | |
865 | .modulemode = MODULEMODE_HWCTRL, | |
866 | }, | |
867 | }, | |
868 | .opt_clks = gpio5_opt_clks, | |
869 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
870 | .dev_attr = &gpio_dev_attr, | |
871 | }; | |
872 | ||
873 | /* gpio6 */ | |
874 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { | |
875 | { .role = "dbclk", .clk = "gpio6_dbclk" }, | |
876 | }; | |
877 | ||
878 | static struct omap_hwmod dra7xx_gpio6_hwmod = { | |
879 | .name = "gpio6", | |
880 | .class = &dra7xx_gpio_hwmod_class, | |
881 | .clkdm_name = "l4per_clkdm", | |
882 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
883 | .main_clk = "l3_iclk_div", | |
884 | .prcm = { | |
885 | .omap4 = { | |
886 | .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET, | |
887 | .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET, | |
888 | .modulemode = MODULEMODE_HWCTRL, | |
889 | }, | |
890 | }, | |
891 | .opt_clks = gpio6_opt_clks, | |
892 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
893 | .dev_attr = &gpio_dev_attr, | |
894 | }; | |
895 | ||
896 | /* gpio7 */ | |
897 | static struct omap_hwmod_opt_clk gpio7_opt_clks[] = { | |
898 | { .role = "dbclk", .clk = "gpio7_dbclk" }, | |
899 | }; | |
900 | ||
901 | static struct omap_hwmod dra7xx_gpio7_hwmod = { | |
902 | .name = "gpio7", | |
903 | .class = &dra7xx_gpio_hwmod_class, | |
904 | .clkdm_name = "l4per_clkdm", | |
905 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
906 | .main_clk = "l3_iclk_div", | |
907 | .prcm = { | |
908 | .omap4 = { | |
909 | .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET, | |
910 | .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET, | |
911 | .modulemode = MODULEMODE_HWCTRL, | |
912 | }, | |
913 | }, | |
914 | .opt_clks = gpio7_opt_clks, | |
915 | .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks), | |
916 | .dev_attr = &gpio_dev_attr, | |
917 | }; | |
918 | ||
919 | /* gpio8 */ | |
920 | static struct omap_hwmod_opt_clk gpio8_opt_clks[] = { | |
921 | { .role = "dbclk", .clk = "gpio8_dbclk" }, | |
922 | }; | |
923 | ||
924 | static struct omap_hwmod dra7xx_gpio8_hwmod = { | |
925 | .name = "gpio8", | |
926 | .class = &dra7xx_gpio_hwmod_class, | |
927 | .clkdm_name = "l4per_clkdm", | |
928 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
929 | .main_clk = "l3_iclk_div", | |
930 | .prcm = { | |
931 | .omap4 = { | |
932 | .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET, | |
933 | .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET, | |
934 | .modulemode = MODULEMODE_HWCTRL, | |
935 | }, | |
936 | }, | |
937 | .opt_clks = gpio8_opt_clks, | |
938 | .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks), | |
939 | .dev_attr = &gpio_dev_attr, | |
940 | }; | |
941 | ||
942 | /* | |
943 | * 'gpmc' class | |
944 | * | |
945 | */ | |
946 | ||
947 | static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = { | |
948 | .rev_offs = 0x0000, | |
949 | .sysc_offs = 0x0010, | |
950 | .syss_offs = 0x0014, | |
951 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
952 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
91a57731 | 953 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
90020c7b A |
954 | .sysc_fields = &omap_hwmod_sysc_type1, |
955 | }; | |
956 | ||
957 | static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = { | |
958 | .name = "gpmc", | |
959 | .sysc = &dra7xx_gpmc_sysc, | |
960 | }; | |
961 | ||
962 | /* gpmc */ | |
963 | ||
964 | static struct omap_hwmod dra7xx_gpmc_hwmod = { | |
965 | .name = "gpmc", | |
966 | .class = &dra7xx_gpmc_hwmod_class, | |
967 | .clkdm_name = "l3main1_clkdm", | |
63aa945b | 968 | /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ |
91a57731 | 969 | .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, |
90020c7b A |
970 | .main_clk = "l3_iclk_div", |
971 | .prcm = { | |
972 | .omap4 = { | |
973 | .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET, | |
974 | .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET, | |
975 | .modulemode = MODULEMODE_HWCTRL, | |
976 | }, | |
977 | }, | |
978 | }; | |
979 | ||
980 | /* | |
981 | * 'hdq1w' class | |
982 | * | |
983 | */ | |
984 | ||
985 | static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = { | |
986 | .rev_offs = 0x0000, | |
987 | .sysc_offs = 0x0014, | |
988 | .syss_offs = 0x0018, | |
989 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET | | |
990 | SYSS_HAS_RESET_STATUS), | |
991 | .sysc_fields = &omap_hwmod_sysc_type1, | |
992 | }; | |
993 | ||
994 | static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = { | |
995 | .name = "hdq1w", | |
996 | .sysc = &dra7xx_hdq1w_sysc, | |
997 | }; | |
998 | ||
999 | /* hdq1w */ | |
1000 | ||
1001 | static struct omap_hwmod dra7xx_hdq1w_hwmod = { | |
1002 | .name = "hdq1w", | |
1003 | .class = &dra7xx_hdq1w_hwmod_class, | |
1004 | .clkdm_name = "l4per_clkdm", | |
1005 | .flags = HWMOD_INIT_NO_RESET, | |
1006 | .main_clk = "func_12m_fclk", | |
1007 | .prcm = { | |
1008 | .omap4 = { | |
1009 | .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, | |
1010 | .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET, | |
1011 | .modulemode = MODULEMODE_SWCTRL, | |
1012 | }, | |
1013 | }, | |
1014 | }; | |
1015 | ||
1016 | /* | |
1017 | * 'i2c' class | |
1018 | * | |
1019 | */ | |
1020 | ||
1021 | static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = { | |
1022 | .sysc_offs = 0x0010, | |
1023 | .syss_offs = 0x0090, | |
1024 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1025 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
1026 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1027 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1028 | SIDLE_SMART_WKUP), | |
1029 | .clockact = CLOCKACT_TEST_ICLK, | |
1030 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1031 | }; | |
1032 | ||
1033 | static struct omap_hwmod_class dra7xx_i2c_hwmod_class = { | |
1034 | .name = "i2c", | |
1035 | .sysc = &dra7xx_i2c_sysc, | |
1036 | .reset = &omap_i2c_reset, | |
1037 | .rev = OMAP_I2C_IP_VERSION_2, | |
1038 | }; | |
1039 | ||
1040 | /* i2c dev_attr */ | |
1041 | static struct omap_i2c_dev_attr i2c_dev_attr = { | |
1042 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, | |
1043 | }; | |
1044 | ||
1045 | /* i2c1 */ | |
1046 | static struct omap_hwmod dra7xx_i2c1_hwmod = { | |
1047 | .name = "i2c1", | |
1048 | .class = &dra7xx_i2c_hwmod_class, | |
1049 | .clkdm_name = "l4per_clkdm", | |
1050 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
1051 | .main_clk = "func_96m_fclk", | |
1052 | .prcm = { | |
1053 | .omap4 = { | |
1054 | .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET, | |
1055 | .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET, | |
1056 | .modulemode = MODULEMODE_SWCTRL, | |
1057 | }, | |
1058 | }, | |
1059 | .dev_attr = &i2c_dev_attr, | |
1060 | }; | |
1061 | ||
1062 | /* i2c2 */ | |
1063 | static struct omap_hwmod dra7xx_i2c2_hwmod = { | |
1064 | .name = "i2c2", | |
1065 | .class = &dra7xx_i2c_hwmod_class, | |
1066 | .clkdm_name = "l4per_clkdm", | |
1067 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
1068 | .main_clk = "func_96m_fclk", | |
1069 | .prcm = { | |
1070 | .omap4 = { | |
1071 | .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET, | |
1072 | .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET, | |
1073 | .modulemode = MODULEMODE_SWCTRL, | |
1074 | }, | |
1075 | }, | |
1076 | .dev_attr = &i2c_dev_attr, | |
1077 | }; | |
1078 | ||
1079 | /* i2c3 */ | |
1080 | static struct omap_hwmod dra7xx_i2c3_hwmod = { | |
1081 | .name = "i2c3", | |
1082 | .class = &dra7xx_i2c_hwmod_class, | |
1083 | .clkdm_name = "l4per_clkdm", | |
1084 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
1085 | .main_clk = "func_96m_fclk", | |
1086 | .prcm = { | |
1087 | .omap4 = { | |
1088 | .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET, | |
1089 | .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET, | |
1090 | .modulemode = MODULEMODE_SWCTRL, | |
1091 | }, | |
1092 | }, | |
1093 | .dev_attr = &i2c_dev_attr, | |
1094 | }; | |
1095 | ||
1096 | /* i2c4 */ | |
1097 | static struct omap_hwmod dra7xx_i2c4_hwmod = { | |
1098 | .name = "i2c4", | |
1099 | .class = &dra7xx_i2c_hwmod_class, | |
1100 | .clkdm_name = "l4per_clkdm", | |
1101 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
1102 | .main_clk = "func_96m_fclk", | |
1103 | .prcm = { | |
1104 | .omap4 = { | |
1105 | .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET, | |
1106 | .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET, | |
1107 | .modulemode = MODULEMODE_SWCTRL, | |
1108 | }, | |
1109 | }, | |
1110 | .dev_attr = &i2c_dev_attr, | |
1111 | }; | |
1112 | ||
1113 | /* i2c5 */ | |
1114 | static struct omap_hwmod dra7xx_i2c5_hwmod = { | |
1115 | .name = "i2c5", | |
1116 | .class = &dra7xx_i2c_hwmod_class, | |
1117 | .clkdm_name = "ipu_clkdm", | |
1118 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
1119 | .main_clk = "func_96m_fclk", | |
1120 | .prcm = { | |
1121 | .omap4 = { | |
1122 | .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET, | |
1123 | .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET, | |
1124 | .modulemode = MODULEMODE_SWCTRL, | |
1125 | }, | |
1126 | }, | |
1127 | .dev_attr = &i2c_dev_attr, | |
1128 | }; | |
1129 | ||
067395d4 SA |
1130 | /* |
1131 | * 'mailbox' class | |
1132 | * | |
1133 | */ | |
1134 | ||
1135 | static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = { | |
1136 | .rev_offs = 0x0000, | |
1137 | .sysc_offs = 0x0010, | |
1138 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1139 | SYSC_HAS_SOFTRESET), | |
1140 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1141 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1142 | }; | |
1143 | ||
1144 | static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = { | |
1145 | .name = "mailbox", | |
1146 | .sysc = &dra7xx_mailbox_sysc, | |
1147 | }; | |
1148 | ||
1149 | /* mailbox1 */ | |
1150 | static struct omap_hwmod dra7xx_mailbox1_hwmod = { | |
1151 | .name = "mailbox1", | |
1152 | .class = &dra7xx_mailbox_hwmod_class, | |
1153 | .clkdm_name = "l4cfg_clkdm", | |
1154 | .prcm = { | |
1155 | .omap4 = { | |
1156 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET, | |
1157 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET, | |
1158 | }, | |
1159 | }, | |
1160 | }; | |
1161 | ||
1162 | /* mailbox2 */ | |
1163 | static struct omap_hwmod dra7xx_mailbox2_hwmod = { | |
1164 | .name = "mailbox2", | |
1165 | .class = &dra7xx_mailbox_hwmod_class, | |
1166 | .clkdm_name = "l4cfg_clkdm", | |
1167 | .prcm = { | |
1168 | .omap4 = { | |
1169 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET, | |
1170 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET, | |
1171 | }, | |
1172 | }, | |
1173 | }; | |
1174 | ||
1175 | /* mailbox3 */ | |
1176 | static struct omap_hwmod dra7xx_mailbox3_hwmod = { | |
1177 | .name = "mailbox3", | |
1178 | .class = &dra7xx_mailbox_hwmod_class, | |
1179 | .clkdm_name = "l4cfg_clkdm", | |
1180 | .prcm = { | |
1181 | .omap4 = { | |
1182 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET, | |
1183 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET, | |
1184 | }, | |
1185 | }, | |
1186 | }; | |
1187 | ||
1188 | /* mailbox4 */ | |
1189 | static struct omap_hwmod dra7xx_mailbox4_hwmod = { | |
1190 | .name = "mailbox4", | |
1191 | .class = &dra7xx_mailbox_hwmod_class, | |
1192 | .clkdm_name = "l4cfg_clkdm", | |
1193 | .prcm = { | |
1194 | .omap4 = { | |
1195 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET, | |
1196 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET, | |
1197 | }, | |
1198 | }, | |
1199 | }; | |
1200 | ||
1201 | /* mailbox5 */ | |
1202 | static struct omap_hwmod dra7xx_mailbox5_hwmod = { | |
1203 | .name = "mailbox5", | |
1204 | .class = &dra7xx_mailbox_hwmod_class, | |
1205 | .clkdm_name = "l4cfg_clkdm", | |
1206 | .prcm = { | |
1207 | .omap4 = { | |
1208 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET, | |
1209 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET, | |
1210 | }, | |
1211 | }, | |
1212 | }; | |
1213 | ||
1214 | /* mailbox6 */ | |
1215 | static struct omap_hwmod dra7xx_mailbox6_hwmod = { | |
1216 | .name = "mailbox6", | |
1217 | .class = &dra7xx_mailbox_hwmod_class, | |
1218 | .clkdm_name = "l4cfg_clkdm", | |
1219 | .prcm = { | |
1220 | .omap4 = { | |
1221 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET, | |
1222 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET, | |
1223 | }, | |
1224 | }, | |
1225 | }; | |
1226 | ||
1227 | /* mailbox7 */ | |
1228 | static struct omap_hwmod dra7xx_mailbox7_hwmod = { | |
1229 | .name = "mailbox7", | |
1230 | .class = &dra7xx_mailbox_hwmod_class, | |
1231 | .clkdm_name = "l4cfg_clkdm", | |
1232 | .prcm = { | |
1233 | .omap4 = { | |
1234 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET, | |
1235 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET, | |
1236 | }, | |
1237 | }, | |
1238 | }; | |
1239 | ||
1240 | /* mailbox8 */ | |
1241 | static struct omap_hwmod dra7xx_mailbox8_hwmod = { | |
1242 | .name = "mailbox8", | |
1243 | .class = &dra7xx_mailbox_hwmod_class, | |
1244 | .clkdm_name = "l4cfg_clkdm", | |
1245 | .prcm = { | |
1246 | .omap4 = { | |
1247 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET, | |
1248 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET, | |
1249 | }, | |
1250 | }, | |
1251 | }; | |
1252 | ||
1253 | /* mailbox9 */ | |
1254 | static struct omap_hwmod dra7xx_mailbox9_hwmod = { | |
1255 | .name = "mailbox9", | |
1256 | .class = &dra7xx_mailbox_hwmod_class, | |
1257 | .clkdm_name = "l4cfg_clkdm", | |
1258 | .prcm = { | |
1259 | .omap4 = { | |
1260 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET, | |
1261 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET, | |
1262 | }, | |
1263 | }, | |
1264 | }; | |
1265 | ||
1266 | /* mailbox10 */ | |
1267 | static struct omap_hwmod dra7xx_mailbox10_hwmod = { | |
1268 | .name = "mailbox10", | |
1269 | .class = &dra7xx_mailbox_hwmod_class, | |
1270 | .clkdm_name = "l4cfg_clkdm", | |
1271 | .prcm = { | |
1272 | .omap4 = { | |
1273 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET, | |
1274 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET, | |
1275 | }, | |
1276 | }, | |
1277 | }; | |
1278 | ||
1279 | /* mailbox11 */ | |
1280 | static struct omap_hwmod dra7xx_mailbox11_hwmod = { | |
1281 | .name = "mailbox11", | |
1282 | .class = &dra7xx_mailbox_hwmod_class, | |
1283 | .clkdm_name = "l4cfg_clkdm", | |
1284 | .prcm = { | |
1285 | .omap4 = { | |
1286 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET, | |
1287 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET, | |
1288 | }, | |
1289 | }, | |
1290 | }; | |
1291 | ||
1292 | /* mailbox12 */ | |
1293 | static struct omap_hwmod dra7xx_mailbox12_hwmod = { | |
1294 | .name = "mailbox12", | |
1295 | .class = &dra7xx_mailbox_hwmod_class, | |
1296 | .clkdm_name = "l4cfg_clkdm", | |
1297 | .prcm = { | |
1298 | .omap4 = { | |
1299 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET, | |
1300 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET, | |
1301 | }, | |
1302 | }, | |
1303 | }; | |
1304 | ||
1305 | /* mailbox13 */ | |
1306 | static struct omap_hwmod dra7xx_mailbox13_hwmod = { | |
1307 | .name = "mailbox13", | |
1308 | .class = &dra7xx_mailbox_hwmod_class, | |
1309 | .clkdm_name = "l4cfg_clkdm", | |
1310 | .prcm = { | |
1311 | .omap4 = { | |
1312 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET, | |
1313 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET, | |
1314 | }, | |
1315 | }, | |
1316 | }; | |
1317 | ||
90020c7b A |
1318 | /* |
1319 | * 'mcspi' class | |
1320 | * | |
1321 | */ | |
1322 | ||
1323 | static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = { | |
1324 | .rev_offs = 0x0000, | |
1325 | .sysc_offs = 0x0010, | |
1326 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
1327 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1328 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1329 | SIDLE_SMART_WKUP), | |
1330 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1331 | }; | |
1332 | ||
1333 | static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = { | |
1334 | .name = "mcspi", | |
1335 | .sysc = &dra7xx_mcspi_sysc, | |
1336 | .rev = OMAP4_MCSPI_REV, | |
1337 | }; | |
1338 | ||
1339 | /* mcspi1 */ | |
1340 | /* mcspi1 dev_attr */ | |
1341 | static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { | |
1342 | .num_chipselect = 4, | |
1343 | }; | |
1344 | ||
1345 | static struct omap_hwmod dra7xx_mcspi1_hwmod = { | |
1346 | .name = "mcspi1", | |
1347 | .class = &dra7xx_mcspi_hwmod_class, | |
1348 | .clkdm_name = "l4per_clkdm", | |
1349 | .main_clk = "func_48m_fclk", | |
1350 | .prcm = { | |
1351 | .omap4 = { | |
1352 | .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, | |
1353 | .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET, | |
1354 | .modulemode = MODULEMODE_SWCTRL, | |
1355 | }, | |
1356 | }, | |
1357 | .dev_attr = &mcspi1_dev_attr, | |
1358 | }; | |
1359 | ||
1360 | /* mcspi2 */ | |
1361 | /* mcspi2 dev_attr */ | |
1362 | static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { | |
1363 | .num_chipselect = 2, | |
1364 | }; | |
1365 | ||
1366 | static struct omap_hwmod dra7xx_mcspi2_hwmod = { | |
1367 | .name = "mcspi2", | |
1368 | .class = &dra7xx_mcspi_hwmod_class, | |
1369 | .clkdm_name = "l4per_clkdm", | |
1370 | .main_clk = "func_48m_fclk", | |
1371 | .prcm = { | |
1372 | .omap4 = { | |
1373 | .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, | |
1374 | .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET, | |
1375 | .modulemode = MODULEMODE_SWCTRL, | |
1376 | }, | |
1377 | }, | |
1378 | .dev_attr = &mcspi2_dev_attr, | |
1379 | }; | |
1380 | ||
1381 | /* mcspi3 */ | |
1382 | /* mcspi3 dev_attr */ | |
1383 | static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { | |
1384 | .num_chipselect = 2, | |
1385 | }; | |
1386 | ||
1387 | static struct omap_hwmod dra7xx_mcspi3_hwmod = { | |
1388 | .name = "mcspi3", | |
1389 | .class = &dra7xx_mcspi_hwmod_class, | |
1390 | .clkdm_name = "l4per_clkdm", | |
1391 | .main_clk = "func_48m_fclk", | |
1392 | .prcm = { | |
1393 | .omap4 = { | |
1394 | .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, | |
1395 | .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET, | |
1396 | .modulemode = MODULEMODE_SWCTRL, | |
1397 | }, | |
1398 | }, | |
1399 | .dev_attr = &mcspi3_dev_attr, | |
1400 | }; | |
1401 | ||
1402 | /* mcspi4 */ | |
1403 | /* mcspi4 dev_attr */ | |
1404 | static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { | |
1405 | .num_chipselect = 1, | |
1406 | }; | |
1407 | ||
1408 | static struct omap_hwmod dra7xx_mcspi4_hwmod = { | |
1409 | .name = "mcspi4", | |
1410 | .class = &dra7xx_mcspi_hwmod_class, | |
1411 | .clkdm_name = "l4per_clkdm", | |
1412 | .main_clk = "func_48m_fclk", | |
1413 | .prcm = { | |
1414 | .omap4 = { | |
1415 | .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, | |
1416 | .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET, | |
1417 | .modulemode = MODULEMODE_SWCTRL, | |
1418 | }, | |
1419 | }, | |
1420 | .dev_attr = &mcspi4_dev_attr, | |
1421 | }; | |
1422 | ||
469689a4 PU |
1423 | /* |
1424 | * 'mcasp' class | |
1425 | * | |
1426 | */ | |
1427 | static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = { | |
1428 | .sysc_offs = 0x0004, | |
1429 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
1430 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1431 | .sysc_fields = &omap_hwmod_sysc_type3, | |
1432 | }; | |
1433 | ||
1434 | static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = { | |
1435 | .name = "mcasp", | |
1436 | .sysc = &dra7xx_mcasp_sysc, | |
1437 | }; | |
1438 | ||
9ad4d9a3 PU |
1439 | /* mcasp1 */ |
1440 | static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = { | |
1441 | { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" }, | |
1442 | { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" }, | |
1443 | }; | |
1444 | ||
1445 | static struct omap_hwmod dra7xx_mcasp1_hwmod = { | |
1446 | .name = "mcasp1", | |
1447 | .class = &dra7xx_mcasp_hwmod_class, | |
1448 | .clkdm_name = "ipu_clkdm", | |
1449 | .main_clk = "mcasp1_aux_gfclk_mux", | |
1450 | .flags = HWMOD_OPT_CLKS_NEEDED, | |
1451 | .prcm = { | |
1452 | .omap4 = { | |
1453 | .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET, | |
1454 | .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET, | |
1455 | .modulemode = MODULEMODE_SWCTRL, | |
1456 | }, | |
1457 | }, | |
1458 | .opt_clks = mcasp1_opt_clks, | |
1459 | .opt_clks_cnt = ARRAY_SIZE(mcasp1_opt_clks), | |
1460 | }; | |
1461 | ||
1462 | /* mcasp2 */ | |
1463 | static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = { | |
1464 | { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" }, | |
1465 | { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" }, | |
1466 | }; | |
1467 | ||
1468 | static struct omap_hwmod dra7xx_mcasp2_hwmod = { | |
1469 | .name = "mcasp2", | |
1470 | .class = &dra7xx_mcasp_hwmod_class, | |
1471 | .clkdm_name = "l4per2_clkdm", | |
1472 | .main_clk = "mcasp2_aux_gfclk_mux", | |
1473 | .flags = HWMOD_OPT_CLKS_NEEDED, | |
1474 | .prcm = { | |
1475 | .omap4 = { | |
1476 | .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET, | |
1477 | .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET, | |
1478 | .modulemode = MODULEMODE_SWCTRL, | |
1479 | }, | |
1480 | }, | |
1481 | .opt_clks = mcasp2_opt_clks, | |
1482 | .opt_clks_cnt = ARRAY_SIZE(mcasp2_opt_clks), | |
1483 | }; | |
1484 | ||
469689a4 PU |
1485 | /* mcasp3 */ |
1486 | static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = { | |
1487 | { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" }, | |
1488 | }; | |
1489 | ||
1490 | static struct omap_hwmod dra7xx_mcasp3_hwmod = { | |
1491 | .name = "mcasp3", | |
1492 | .class = &dra7xx_mcasp_hwmod_class, | |
1493 | .clkdm_name = "l4per2_clkdm", | |
1494 | .main_clk = "mcasp3_aux_gfclk_mux", | |
1495 | .flags = HWMOD_OPT_CLKS_NEEDED, | |
1496 | .prcm = { | |
1497 | .omap4 = { | |
1498 | .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET, | |
1499 | .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET, | |
1500 | .modulemode = MODULEMODE_SWCTRL, | |
1501 | }, | |
1502 | }, | |
1503 | .opt_clks = mcasp3_opt_clks, | |
1504 | .opt_clks_cnt = ARRAY_SIZE(mcasp3_opt_clks), | |
1505 | }; | |
1506 | ||
9ad4d9a3 PU |
1507 | /* mcasp4 */ |
1508 | static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = { | |
1509 | { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" }, | |
1510 | }; | |
1511 | ||
1512 | static struct omap_hwmod dra7xx_mcasp4_hwmod = { | |
1513 | .name = "mcasp4", | |
1514 | .class = &dra7xx_mcasp_hwmod_class, | |
1515 | .clkdm_name = "l4per2_clkdm", | |
1516 | .main_clk = "mcasp4_aux_gfclk_mux", | |
1517 | .flags = HWMOD_OPT_CLKS_NEEDED, | |
1518 | .prcm = { | |
1519 | .omap4 = { | |
1520 | .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET, | |
1521 | .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET, | |
1522 | .modulemode = MODULEMODE_SWCTRL, | |
1523 | }, | |
1524 | }, | |
1525 | .opt_clks = mcasp4_opt_clks, | |
1526 | .opt_clks_cnt = ARRAY_SIZE(mcasp4_opt_clks), | |
1527 | }; | |
1528 | ||
1529 | /* mcasp5 */ | |
1530 | static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = { | |
1531 | { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" }, | |
1532 | }; | |
1533 | ||
1534 | static struct omap_hwmod dra7xx_mcasp5_hwmod = { | |
1535 | .name = "mcasp5", | |
1536 | .class = &dra7xx_mcasp_hwmod_class, | |
1537 | .clkdm_name = "l4per2_clkdm", | |
1538 | .main_clk = "mcasp5_aux_gfclk_mux", | |
1539 | .flags = HWMOD_OPT_CLKS_NEEDED, | |
1540 | .prcm = { | |
1541 | .omap4 = { | |
1542 | .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET, | |
1543 | .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET, | |
1544 | .modulemode = MODULEMODE_SWCTRL, | |
1545 | }, | |
1546 | }, | |
1547 | .opt_clks = mcasp5_opt_clks, | |
1548 | .opt_clks_cnt = ARRAY_SIZE(mcasp5_opt_clks), | |
1549 | }; | |
1550 | ||
1551 | /* mcasp6 */ | |
1552 | static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = { | |
1553 | { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" }, | |
1554 | }; | |
1555 | ||
1556 | static struct omap_hwmod dra7xx_mcasp6_hwmod = { | |
1557 | .name = "mcasp6", | |
1558 | .class = &dra7xx_mcasp_hwmod_class, | |
1559 | .clkdm_name = "l4per2_clkdm", | |
1560 | .main_clk = "mcasp6_aux_gfclk_mux", | |
1561 | .flags = HWMOD_OPT_CLKS_NEEDED, | |
1562 | .prcm = { | |
1563 | .omap4 = { | |
1564 | .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET, | |
1565 | .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET, | |
1566 | .modulemode = MODULEMODE_SWCTRL, | |
1567 | }, | |
1568 | }, | |
1569 | .opt_clks = mcasp6_opt_clks, | |
1570 | .opt_clks_cnt = ARRAY_SIZE(mcasp6_opt_clks), | |
1571 | }; | |
1572 | ||
1573 | /* mcasp7 */ | |
1574 | static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = { | |
1575 | { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" }, | |
1576 | }; | |
1577 | ||
1578 | static struct omap_hwmod dra7xx_mcasp7_hwmod = { | |
1579 | .name = "mcasp7", | |
1580 | .class = &dra7xx_mcasp_hwmod_class, | |
1581 | .clkdm_name = "l4per2_clkdm", | |
1582 | .main_clk = "mcasp7_aux_gfclk_mux", | |
1583 | .flags = HWMOD_OPT_CLKS_NEEDED, | |
1584 | .prcm = { | |
1585 | .omap4 = { | |
1586 | .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET, | |
1587 | .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET, | |
1588 | .modulemode = MODULEMODE_SWCTRL, | |
1589 | }, | |
1590 | }, | |
1591 | .opt_clks = mcasp7_opt_clks, | |
1592 | .opt_clks_cnt = ARRAY_SIZE(mcasp7_opt_clks), | |
1593 | }; | |
1594 | ||
1595 | /* mcasp8 */ | |
1596 | static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = { | |
1597 | { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" }, | |
1598 | }; | |
1599 | ||
1600 | static struct omap_hwmod dra7xx_mcasp8_hwmod = { | |
1601 | .name = "mcasp8", | |
1602 | .class = &dra7xx_mcasp_hwmod_class, | |
1603 | .clkdm_name = "l4per2_clkdm", | |
1604 | .main_clk = "mcasp8_aux_gfclk_mux", | |
1605 | .flags = HWMOD_OPT_CLKS_NEEDED, | |
1606 | .prcm = { | |
1607 | .omap4 = { | |
1608 | .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET, | |
1609 | .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET, | |
1610 | .modulemode = MODULEMODE_SWCTRL, | |
1611 | }, | |
1612 | }, | |
1613 | .opt_clks = mcasp8_opt_clks, | |
1614 | .opt_clks_cnt = ARRAY_SIZE(mcasp8_opt_clks), | |
1615 | }; | |
1616 | ||
90020c7b A |
1617 | /* |
1618 | * 'mmc' class | |
1619 | * | |
1620 | */ | |
1621 | ||
1622 | static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = { | |
1623 | .rev_offs = 0x0000, | |
1624 | .sysc_offs = 0x0010, | |
1625 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
1626 | SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1627 | SYSC_HAS_SOFTRESET), | |
1628 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1629 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
1630 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
1631 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1632 | }; | |
1633 | ||
1634 | static struct omap_hwmod_class dra7xx_mmc_hwmod_class = { | |
1635 | .name = "mmc", | |
1636 | .sysc = &dra7xx_mmc_sysc, | |
1637 | }; | |
1638 | ||
1639 | /* mmc1 */ | |
1640 | static struct omap_hwmod_opt_clk mmc1_opt_clks[] = { | |
1641 | { .role = "clk32k", .clk = "mmc1_clk32k" }, | |
1642 | }; | |
1643 | ||
1644 | /* mmc1 dev_attr */ | |
55143438 | 1645 | static struct omap_hsmmc_dev_attr mmc1_dev_attr = { |
90020c7b A |
1646 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, |
1647 | }; | |
1648 | ||
1649 | static struct omap_hwmod dra7xx_mmc1_hwmod = { | |
1650 | .name = "mmc1", | |
1651 | .class = &dra7xx_mmc_hwmod_class, | |
1652 | .clkdm_name = "l3init_clkdm", | |
1653 | .main_clk = "mmc1_fclk_div", | |
1654 | .prcm = { | |
1655 | .omap4 = { | |
1656 | .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET, | |
1657 | .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET, | |
1658 | .modulemode = MODULEMODE_SWCTRL, | |
1659 | }, | |
1660 | }, | |
1661 | .opt_clks = mmc1_opt_clks, | |
1662 | .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks), | |
1663 | .dev_attr = &mmc1_dev_attr, | |
1664 | }; | |
1665 | ||
1666 | /* mmc2 */ | |
1667 | static struct omap_hwmod_opt_clk mmc2_opt_clks[] = { | |
1668 | { .role = "clk32k", .clk = "mmc2_clk32k" }, | |
1669 | }; | |
1670 | ||
1671 | static struct omap_hwmod dra7xx_mmc2_hwmod = { | |
1672 | .name = "mmc2", | |
1673 | .class = &dra7xx_mmc_hwmod_class, | |
1674 | .clkdm_name = "l3init_clkdm", | |
1675 | .main_clk = "mmc2_fclk_div", | |
1676 | .prcm = { | |
1677 | .omap4 = { | |
1678 | .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET, | |
1679 | .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET, | |
1680 | .modulemode = MODULEMODE_SWCTRL, | |
1681 | }, | |
1682 | }, | |
1683 | .opt_clks = mmc2_opt_clks, | |
1684 | .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks), | |
1685 | }; | |
1686 | ||
1687 | /* mmc3 */ | |
1688 | static struct omap_hwmod_opt_clk mmc3_opt_clks[] = { | |
1689 | { .role = "clk32k", .clk = "mmc3_clk32k" }, | |
1690 | }; | |
1691 | ||
1692 | static struct omap_hwmod dra7xx_mmc3_hwmod = { | |
1693 | .name = "mmc3", | |
1694 | .class = &dra7xx_mmc_hwmod_class, | |
1695 | .clkdm_name = "l4per_clkdm", | |
1696 | .main_clk = "mmc3_gfclk_div", | |
1697 | .prcm = { | |
1698 | .omap4 = { | |
1699 | .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET, | |
1700 | .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET, | |
1701 | .modulemode = MODULEMODE_SWCTRL, | |
1702 | }, | |
1703 | }, | |
1704 | .opt_clks = mmc3_opt_clks, | |
1705 | .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks), | |
1706 | }; | |
1707 | ||
1708 | /* mmc4 */ | |
1709 | static struct omap_hwmod_opt_clk mmc4_opt_clks[] = { | |
1710 | { .role = "clk32k", .clk = "mmc4_clk32k" }, | |
1711 | }; | |
1712 | ||
1713 | static struct omap_hwmod dra7xx_mmc4_hwmod = { | |
1714 | .name = "mmc4", | |
1715 | .class = &dra7xx_mmc_hwmod_class, | |
1716 | .clkdm_name = "l4per_clkdm", | |
1717 | .main_clk = "mmc4_gfclk_div", | |
1718 | .prcm = { | |
1719 | .omap4 = { | |
1720 | .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET, | |
1721 | .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET, | |
1722 | .modulemode = MODULEMODE_SWCTRL, | |
1723 | }, | |
1724 | }, | |
1725 | .opt_clks = mmc4_opt_clks, | |
1726 | .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks), | |
1727 | }; | |
1728 | ||
1729 | /* | |
1730 | * 'mpu' class | |
1731 | * | |
1732 | */ | |
1733 | ||
1734 | static struct omap_hwmod_class dra7xx_mpu_hwmod_class = { | |
1735 | .name = "mpu", | |
1736 | }; | |
1737 | ||
1738 | /* mpu */ | |
1739 | static struct omap_hwmod dra7xx_mpu_hwmod = { | |
1740 | .name = "mpu", | |
1741 | .class = &dra7xx_mpu_hwmod_class, | |
1742 | .clkdm_name = "mpu_clkdm", | |
1743 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | |
1744 | .main_clk = "dpll_mpu_m2_ck", | |
1745 | .prcm = { | |
1746 | .omap4 = { | |
1747 | .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET, | |
1748 | .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET, | |
1749 | }, | |
1750 | }, | |
1751 | }; | |
1752 | ||
1753 | /* | |
1754 | * 'ocp2scp' class | |
1755 | * | |
1756 | */ | |
1757 | ||
1758 | static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = { | |
1759 | .rev_offs = 0x0000, | |
1760 | .sysc_offs = 0x0010, | |
1761 | .syss_offs = 0x0014, | |
1762 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
1763 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
4965be1f | 1764 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
90020c7b A |
1765 | .sysc_fields = &omap_hwmod_sysc_type1, |
1766 | }; | |
1767 | ||
1768 | static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = { | |
1769 | .name = "ocp2scp", | |
1770 | .sysc = &dra7xx_ocp2scp_sysc, | |
1771 | }; | |
1772 | ||
1773 | /* ocp2scp1 */ | |
1774 | static struct omap_hwmod dra7xx_ocp2scp1_hwmod = { | |
1775 | .name = "ocp2scp1", | |
1776 | .class = &dra7xx_ocp2scp_hwmod_class, | |
1777 | .clkdm_name = "l3init_clkdm", | |
1778 | .main_clk = "l4_root_clk_div", | |
1779 | .prcm = { | |
1780 | .omap4 = { | |
1781 | .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET, | |
1782 | .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET, | |
1783 | .modulemode = MODULEMODE_HWCTRL, | |
1784 | }, | |
1785 | }, | |
1786 | }; | |
1787 | ||
df0d0f11 RQ |
1788 | /* ocp2scp3 */ |
1789 | static struct omap_hwmod dra7xx_ocp2scp3_hwmod = { | |
1790 | .name = "ocp2scp3", | |
1791 | .class = &dra7xx_ocp2scp_hwmod_class, | |
1792 | .clkdm_name = "l3init_clkdm", | |
1793 | .main_clk = "l4_root_clk_div", | |
1794 | .prcm = { | |
1795 | .omap4 = { | |
1796 | .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET, | |
1797 | .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET, | |
1798 | .modulemode = MODULEMODE_HWCTRL, | |
1799 | }, | |
1800 | }, | |
1801 | }; | |
1802 | ||
8dd3eb71 KVA |
1803 | /* |
1804 | * 'PCIE' class | |
1805 | * | |
1806 | */ | |
1807 | ||
1c96bee4 SN |
1808 | /* |
1809 | * As noted in documentation for _reset() in omap_hwmod.c, the stock reset | |
1810 | * functionality of OMAP HWMOD layer does not deassert the hardreset lines | |
1811 | * associated with an IP automatically leaving the driver to handle that | |
1812 | * by itself. This does not work for PCIeSS which needs the reset lines | |
1813 | * deasserted for the driver to start accessing registers. | |
1814 | * | |
1815 | * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset | |
1816 | * lines after asserting them. | |
1817 | */ | |
1818 | static int dra7xx_pciess_reset(struct omap_hwmod *oh) | |
1819 | { | |
1820 | int i; | |
1821 | ||
1822 | for (i = 0; i < oh->rst_lines_cnt; i++) { | |
1823 | omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name); | |
1824 | omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name); | |
1825 | } | |
1826 | ||
1827 | return 0; | |
1828 | } | |
1829 | ||
0717103e | 1830 | static struct omap_hwmod_class dra7xx_pciess_hwmod_class = { |
8dd3eb71 | 1831 | .name = "pcie", |
1c96bee4 | 1832 | .reset = dra7xx_pciess_reset, |
8dd3eb71 KVA |
1833 | }; |
1834 | ||
1835 | /* pcie1 */ | |
8fe097a3 KVA |
1836 | static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = { |
1837 | { .name = "pcie", .rst_shift = 0 }, | |
1838 | }; | |
1839 | ||
0717103e | 1840 | static struct omap_hwmod dra7xx_pciess1_hwmod = { |
8dd3eb71 | 1841 | .name = "pcie1", |
0717103e | 1842 | .class = &dra7xx_pciess_hwmod_class, |
8dd3eb71 | 1843 | .clkdm_name = "pcie_clkdm", |
8fe097a3 KVA |
1844 | .rst_lines = dra7xx_pciess1_resets, |
1845 | .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets), | |
8dd3eb71 | 1846 | .main_clk = "l4_root_clk_div", |
70c18ef7 KVA |
1847 | .prcm = { |
1848 | .omap4 = { | |
1849 | .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET, | |
8fe097a3 | 1850 | .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET, |
70c18ef7 KVA |
1851 | .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET, |
1852 | .modulemode = MODULEMODE_SWCTRL, | |
1853 | }, | |
1854 | }, | |
1855 | }; | |
1856 | ||
8fe097a3 KVA |
1857 | /* pcie2 */ |
1858 | static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = { | |
1859 | { .name = "pcie", .rst_shift = 1 }, | |
1860 | }; | |
1861 | ||
0717103e KVA |
1862 | /* pcie2 */ |
1863 | static struct omap_hwmod dra7xx_pciess2_hwmod = { | |
1864 | .name = "pcie2", | |
1865 | .class = &dra7xx_pciess_hwmod_class, | |
1866 | .clkdm_name = "pcie_clkdm", | |
8fe097a3 KVA |
1867 | .rst_lines = dra7xx_pciess2_resets, |
1868 | .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets), | |
70c18ef7 KVA |
1869 | .main_clk = "l4_root_clk_div", |
1870 | .prcm = { | |
1871 | .omap4 = { | |
1872 | .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET, | |
8fe097a3 | 1873 | .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET, |
70c18ef7 KVA |
1874 | .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET, |
1875 | .modulemode = MODULEMODE_SWCTRL, | |
1876 | }, | |
1877 | }, | |
1878 | }; | |
1879 | ||
90020c7b A |
1880 | /* |
1881 | * 'qspi' class | |
1882 | * | |
1883 | */ | |
1884 | ||
1885 | static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = { | |
1886 | .sysc_offs = 0x0010, | |
1887 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
1888 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1889 | SIDLE_SMART_WKUP), | |
1890 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1891 | }; | |
1892 | ||
1893 | static struct omap_hwmod_class dra7xx_qspi_hwmod_class = { | |
1894 | .name = "qspi", | |
1895 | .sysc = &dra7xx_qspi_sysc, | |
1896 | }; | |
1897 | ||
1898 | /* qspi */ | |
1899 | static struct omap_hwmod dra7xx_qspi_hwmod = { | |
1900 | .name = "qspi", | |
1901 | .class = &dra7xx_qspi_hwmod_class, | |
1902 | .clkdm_name = "l4per2_clkdm", | |
1903 | .main_clk = "qspi_gfclk_div", | |
1904 | .prcm = { | |
1905 | .omap4 = { | |
1906 | .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET, | |
1907 | .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET, | |
1908 | .modulemode = MODULEMODE_SWCTRL, | |
1909 | }, | |
1910 | }, | |
1911 | }; | |
1912 | ||
c913c8a1 LV |
1913 | /* |
1914 | * 'rtcss' class | |
1915 | * | |
1916 | */ | |
1917 | static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = { | |
1918 | .sysc_offs = 0x0078, | |
1919 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
1920 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1921 | SIDLE_SMART_WKUP), | |
1922 | .sysc_fields = &omap_hwmod_sysc_type3, | |
1923 | }; | |
1924 | ||
1925 | static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = { | |
1926 | .name = "rtcss", | |
1927 | .sysc = &dra7xx_rtcss_sysc, | |
d7d31b89 LV |
1928 | .unlock = &omap_hwmod_rtc_unlock, |
1929 | .lock = &omap_hwmod_rtc_lock, | |
c913c8a1 LV |
1930 | }; |
1931 | ||
1932 | /* rtcss */ | |
1933 | static struct omap_hwmod dra7xx_rtcss_hwmod = { | |
1934 | .name = "rtcss", | |
1935 | .class = &dra7xx_rtcss_hwmod_class, | |
1936 | .clkdm_name = "rtc_clkdm", | |
1937 | .main_clk = "sys_32k_ck", | |
1938 | .prcm = { | |
1939 | .omap4 = { | |
1940 | .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET, | |
1941 | .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET, | |
1942 | .modulemode = MODULEMODE_SWCTRL, | |
1943 | }, | |
1944 | }, | |
1945 | }; | |
1946 | ||
90020c7b A |
1947 | /* |
1948 | * 'sata' class | |
1949 | * | |
1950 | */ | |
1951 | ||
1952 | static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = { | |
1953 | .sysc_offs = 0x0000, | |
1954 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
1955 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1956 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
1957 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
1958 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1959 | }; | |
1960 | ||
1961 | static struct omap_hwmod_class dra7xx_sata_hwmod_class = { | |
1962 | .name = "sata", | |
1963 | .sysc = &dra7xx_sata_sysc, | |
1964 | }; | |
1965 | ||
1966 | /* sata */ | |
90020c7b A |
1967 | |
1968 | static struct omap_hwmod dra7xx_sata_hwmod = { | |
1969 | .name = "sata", | |
1970 | .class = &dra7xx_sata_hwmod_class, | |
1971 | .clkdm_name = "l3init_clkdm", | |
1972 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | |
1973 | .main_clk = "func_48m_fclk", | |
1ea0999e | 1974 | .mpu_rt_idx = 1, |
90020c7b A |
1975 | .prcm = { |
1976 | .omap4 = { | |
1977 | .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET, | |
1978 | .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET, | |
1979 | .modulemode = MODULEMODE_SWCTRL, | |
1980 | }, | |
1981 | }, | |
90020c7b A |
1982 | }; |
1983 | ||
1984 | /* | |
1985 | * 'smartreflex' class | |
1986 | * | |
1987 | */ | |
1988 | ||
1989 | /* The IP is not compliant to type1 / type2 scheme */ | |
1990 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { | |
1991 | .sidle_shift = 24, | |
1992 | .enwkup_shift = 26, | |
1993 | }; | |
1994 | ||
1995 | static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = { | |
1996 | .sysc_offs = 0x0038, | |
1997 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), | |
1998 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1999 | SIDLE_SMART_WKUP), | |
2000 | .sysc_fields = &omap_hwmod_sysc_type_smartreflex, | |
2001 | }; | |
2002 | ||
2003 | static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = { | |
2004 | .name = "smartreflex", | |
2005 | .sysc = &dra7xx_smartreflex_sysc, | |
2006 | .rev = 2, | |
2007 | }; | |
2008 | ||
2009 | /* smartreflex_core */ | |
2010 | /* smartreflex_core dev_attr */ | |
2011 | static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { | |
2012 | .sensor_voltdm_name = "core", | |
2013 | }; | |
2014 | ||
2015 | static struct omap_hwmod dra7xx_smartreflex_core_hwmod = { | |
2016 | .name = "smartreflex_core", | |
2017 | .class = &dra7xx_smartreflex_hwmod_class, | |
2018 | .clkdm_name = "coreaon_clkdm", | |
2019 | .main_clk = "wkupaon_iclk_mux", | |
2020 | .prcm = { | |
2021 | .omap4 = { | |
2022 | .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET, | |
2023 | .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET, | |
2024 | .modulemode = MODULEMODE_SWCTRL, | |
2025 | }, | |
2026 | }, | |
2027 | .dev_attr = &smartreflex_core_dev_attr, | |
2028 | }; | |
2029 | ||
2030 | /* smartreflex_mpu */ | |
2031 | /* smartreflex_mpu dev_attr */ | |
2032 | static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { | |
2033 | .sensor_voltdm_name = "mpu", | |
2034 | }; | |
2035 | ||
2036 | static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = { | |
2037 | .name = "smartreflex_mpu", | |
2038 | .class = &dra7xx_smartreflex_hwmod_class, | |
2039 | .clkdm_name = "coreaon_clkdm", | |
2040 | .main_clk = "wkupaon_iclk_mux", | |
2041 | .prcm = { | |
2042 | .omap4 = { | |
2043 | .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET, | |
2044 | .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET, | |
2045 | .modulemode = MODULEMODE_SWCTRL, | |
2046 | }, | |
2047 | }, | |
2048 | .dev_attr = &smartreflex_mpu_dev_attr, | |
2049 | }; | |
2050 | ||
2051 | /* | |
2052 | * 'spinlock' class | |
2053 | * | |
2054 | */ | |
2055 | ||
2056 | static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = { | |
2057 | .rev_offs = 0x0000, | |
2058 | .sysc_offs = 0x0010, | |
2059 | .syss_offs = 0x0014, | |
c317d0f2 SA |
2060 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
2061 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
2062 | SYSS_HAS_RESET_STATUS), | |
2063 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
90020c7b A |
2064 | .sysc_fields = &omap_hwmod_sysc_type1, |
2065 | }; | |
2066 | ||
2067 | static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = { | |
2068 | .name = "spinlock", | |
2069 | .sysc = &dra7xx_spinlock_sysc, | |
2070 | }; | |
2071 | ||
2072 | /* spinlock */ | |
2073 | static struct omap_hwmod dra7xx_spinlock_hwmod = { | |
2074 | .name = "spinlock", | |
2075 | .class = &dra7xx_spinlock_hwmod_class, | |
2076 | .clkdm_name = "l4cfg_clkdm", | |
2077 | .main_clk = "l3_iclk_div", | |
2078 | .prcm = { | |
2079 | .omap4 = { | |
2080 | .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET, | |
2081 | .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET, | |
2082 | }, | |
2083 | }, | |
2084 | }; | |
2085 | ||
2086 | /* | |
2087 | * 'timer' class | |
2088 | * | |
2089 | * This class contains several variants: ['timer_1ms', 'timer_secure', | |
2090 | * 'timer'] | |
2091 | */ | |
2092 | ||
2093 | static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = { | |
2094 | .rev_offs = 0x0000, | |
2095 | .sysc_offs = 0x0010, | |
2096 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2097 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2098 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2099 | SIDLE_SMART_WKUP), | |
2100 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2101 | }; | |
2102 | ||
2103 | static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = { | |
2104 | .name = "timer", | |
2105 | .sysc = &dra7xx_timer_1ms_sysc, | |
2106 | }; | |
2107 | ||
90020c7b A |
2108 | static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = { |
2109 | .rev_offs = 0x0000, | |
2110 | .sysc_offs = 0x0010, | |
2111 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2112 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2113 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2114 | SIDLE_SMART_WKUP), | |
2115 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2116 | }; | |
2117 | ||
2118 | static struct omap_hwmod_class dra7xx_timer_hwmod_class = { | |
2119 | .name = "timer", | |
2120 | .sysc = &dra7xx_timer_sysc, | |
2121 | }; | |
2122 | ||
2123 | /* timer1 */ | |
2124 | static struct omap_hwmod dra7xx_timer1_hwmod = { | |
2125 | .name = "timer1", | |
2126 | .class = &dra7xx_timer_1ms_hwmod_class, | |
2127 | .clkdm_name = "wkupaon_clkdm", | |
2128 | .main_clk = "timer1_gfclk_mux", | |
2129 | .prcm = { | |
2130 | .omap4 = { | |
2131 | .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET, | |
2132 | .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET, | |
2133 | .modulemode = MODULEMODE_SWCTRL, | |
2134 | }, | |
2135 | }, | |
2136 | }; | |
2137 | ||
2138 | /* timer2 */ | |
2139 | static struct omap_hwmod dra7xx_timer2_hwmod = { | |
2140 | .name = "timer2", | |
2141 | .class = &dra7xx_timer_1ms_hwmod_class, | |
2142 | .clkdm_name = "l4per_clkdm", | |
2143 | .main_clk = "timer2_gfclk_mux", | |
2144 | .prcm = { | |
2145 | .omap4 = { | |
2146 | .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET, | |
2147 | .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET, | |
2148 | .modulemode = MODULEMODE_SWCTRL, | |
2149 | }, | |
2150 | }, | |
2151 | }; | |
2152 | ||
2153 | /* timer3 */ | |
2154 | static struct omap_hwmod dra7xx_timer3_hwmod = { | |
2155 | .name = "timer3", | |
2156 | .class = &dra7xx_timer_hwmod_class, | |
2157 | .clkdm_name = "l4per_clkdm", | |
2158 | .main_clk = "timer3_gfclk_mux", | |
2159 | .prcm = { | |
2160 | .omap4 = { | |
2161 | .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET, | |
2162 | .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET, | |
2163 | .modulemode = MODULEMODE_SWCTRL, | |
2164 | }, | |
2165 | }, | |
2166 | }; | |
2167 | ||
2168 | /* timer4 */ | |
2169 | static struct omap_hwmod dra7xx_timer4_hwmod = { | |
2170 | .name = "timer4", | |
edec1786 | 2171 | .class = &dra7xx_timer_hwmod_class, |
90020c7b A |
2172 | .clkdm_name = "l4per_clkdm", |
2173 | .main_clk = "timer4_gfclk_mux", | |
2174 | .prcm = { | |
2175 | .omap4 = { | |
2176 | .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET, | |
2177 | .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET, | |
2178 | .modulemode = MODULEMODE_SWCTRL, | |
2179 | }, | |
2180 | }, | |
2181 | }; | |
2182 | ||
2183 | /* timer5 */ | |
2184 | static struct omap_hwmod dra7xx_timer5_hwmod = { | |
2185 | .name = "timer5", | |
2186 | .class = &dra7xx_timer_hwmod_class, | |
2187 | .clkdm_name = "ipu_clkdm", | |
2188 | .main_clk = "timer5_gfclk_mux", | |
2189 | .prcm = { | |
2190 | .omap4 = { | |
2191 | .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET, | |
2192 | .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET, | |
2193 | .modulemode = MODULEMODE_SWCTRL, | |
2194 | }, | |
2195 | }, | |
2196 | }; | |
2197 | ||
2198 | /* timer6 */ | |
2199 | static struct omap_hwmod dra7xx_timer6_hwmod = { | |
2200 | .name = "timer6", | |
2201 | .class = &dra7xx_timer_hwmod_class, | |
2202 | .clkdm_name = "ipu_clkdm", | |
2203 | .main_clk = "timer6_gfclk_mux", | |
2204 | .prcm = { | |
2205 | .omap4 = { | |
2206 | .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET, | |
2207 | .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET, | |
2208 | .modulemode = MODULEMODE_SWCTRL, | |
2209 | }, | |
2210 | }, | |
2211 | }; | |
2212 | ||
2213 | /* timer7 */ | |
2214 | static struct omap_hwmod dra7xx_timer7_hwmod = { | |
2215 | .name = "timer7", | |
2216 | .class = &dra7xx_timer_hwmod_class, | |
2217 | .clkdm_name = "ipu_clkdm", | |
2218 | .main_clk = "timer7_gfclk_mux", | |
2219 | .prcm = { | |
2220 | .omap4 = { | |
2221 | .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET, | |
2222 | .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET, | |
2223 | .modulemode = MODULEMODE_SWCTRL, | |
2224 | }, | |
2225 | }, | |
2226 | }; | |
2227 | ||
2228 | /* timer8 */ | |
2229 | static struct omap_hwmod dra7xx_timer8_hwmod = { | |
2230 | .name = "timer8", | |
2231 | .class = &dra7xx_timer_hwmod_class, | |
2232 | .clkdm_name = "ipu_clkdm", | |
2233 | .main_clk = "timer8_gfclk_mux", | |
2234 | .prcm = { | |
2235 | .omap4 = { | |
2236 | .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET, | |
2237 | .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET, | |
2238 | .modulemode = MODULEMODE_SWCTRL, | |
2239 | }, | |
2240 | }, | |
2241 | }; | |
2242 | ||
2243 | /* timer9 */ | |
2244 | static struct omap_hwmod dra7xx_timer9_hwmod = { | |
2245 | .name = "timer9", | |
2246 | .class = &dra7xx_timer_hwmod_class, | |
2247 | .clkdm_name = "l4per_clkdm", | |
2248 | .main_clk = "timer9_gfclk_mux", | |
2249 | .prcm = { | |
2250 | .omap4 = { | |
2251 | .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET, | |
2252 | .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET, | |
2253 | .modulemode = MODULEMODE_SWCTRL, | |
2254 | }, | |
2255 | }, | |
2256 | }; | |
2257 | ||
2258 | /* timer10 */ | |
2259 | static struct omap_hwmod dra7xx_timer10_hwmod = { | |
2260 | .name = "timer10", | |
2261 | .class = &dra7xx_timer_1ms_hwmod_class, | |
2262 | .clkdm_name = "l4per_clkdm", | |
2263 | .main_clk = "timer10_gfclk_mux", | |
2264 | .prcm = { | |
2265 | .omap4 = { | |
2266 | .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET, | |
2267 | .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET, | |
2268 | .modulemode = MODULEMODE_SWCTRL, | |
2269 | }, | |
2270 | }, | |
2271 | }; | |
2272 | ||
2273 | /* timer11 */ | |
2274 | static struct omap_hwmod dra7xx_timer11_hwmod = { | |
2275 | .name = "timer11", | |
2276 | .class = &dra7xx_timer_hwmod_class, | |
2277 | .clkdm_name = "l4per_clkdm", | |
2278 | .main_clk = "timer11_gfclk_mux", | |
2279 | .prcm = { | |
2280 | .omap4 = { | |
2281 | .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET, | |
2282 | .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET, | |
2283 | .modulemode = MODULEMODE_SWCTRL, | |
2284 | }, | |
2285 | }, | |
2286 | }; | |
2287 | ||
22d20cb4 SA |
2288 | /* timer12 */ |
2289 | static struct omap_hwmod dra7xx_timer12_hwmod = { | |
2290 | .name = "timer12", | |
2291 | .class = &dra7xx_timer_hwmod_class, | |
2292 | .clkdm_name = "wkupaon_clkdm", | |
2293 | .main_clk = "secure_32k_clk_src_ck", | |
2294 | .prcm = { | |
2295 | .omap4 = { | |
2296 | .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET, | |
2297 | .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET, | |
2298 | }, | |
2299 | }, | |
2300 | }; | |
2301 | ||
1ac964f4 SA |
2302 | /* timer13 */ |
2303 | static struct omap_hwmod dra7xx_timer13_hwmod = { | |
2304 | .name = "timer13", | |
2305 | .class = &dra7xx_timer_hwmod_class, | |
2306 | .clkdm_name = "l4per3_clkdm", | |
2307 | .main_clk = "timer13_gfclk_mux", | |
2308 | .prcm = { | |
2309 | .omap4 = { | |
2310 | .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET, | |
2311 | .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET, | |
2312 | .modulemode = MODULEMODE_SWCTRL, | |
2313 | }, | |
2314 | }, | |
2315 | }; | |
2316 | ||
2317 | /* timer14 */ | |
2318 | static struct omap_hwmod dra7xx_timer14_hwmod = { | |
2319 | .name = "timer14", | |
2320 | .class = &dra7xx_timer_hwmod_class, | |
2321 | .clkdm_name = "l4per3_clkdm", | |
2322 | .main_clk = "timer14_gfclk_mux", | |
2323 | .prcm = { | |
2324 | .omap4 = { | |
2325 | .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET, | |
2326 | .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET, | |
2327 | .modulemode = MODULEMODE_SWCTRL, | |
2328 | }, | |
2329 | }, | |
2330 | }; | |
2331 | ||
2332 | /* timer15 */ | |
2333 | static struct omap_hwmod dra7xx_timer15_hwmod = { | |
2334 | .name = "timer15", | |
2335 | .class = &dra7xx_timer_hwmod_class, | |
2336 | .clkdm_name = "l4per3_clkdm", | |
2337 | .main_clk = "timer15_gfclk_mux", | |
2338 | .prcm = { | |
2339 | .omap4 = { | |
2340 | .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET, | |
2341 | .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET, | |
2342 | .modulemode = MODULEMODE_SWCTRL, | |
2343 | }, | |
2344 | }, | |
2345 | }; | |
2346 | ||
2347 | /* timer16 */ | |
2348 | static struct omap_hwmod dra7xx_timer16_hwmod = { | |
2349 | .name = "timer16", | |
2350 | .class = &dra7xx_timer_hwmod_class, | |
2351 | .clkdm_name = "l4per3_clkdm", | |
2352 | .main_clk = "timer16_gfclk_mux", | |
2353 | .prcm = { | |
2354 | .omap4 = { | |
2355 | .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET, | |
2356 | .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET, | |
2357 | .modulemode = MODULEMODE_SWCTRL, | |
2358 | }, | |
2359 | }, | |
2360 | }; | |
2361 | ||
90020c7b A |
2362 | /* |
2363 | * 'uart' class | |
2364 | * | |
2365 | */ | |
2366 | ||
2367 | static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = { | |
2368 | .rev_offs = 0x0050, | |
2369 | .sysc_offs = 0x0054, | |
2370 | .syss_offs = 0x0058, | |
2371 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
2372 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
2373 | SYSS_HAS_RESET_STATUS), | |
2374 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2375 | SIDLE_SMART_WKUP), | |
2376 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2377 | }; | |
2378 | ||
2379 | static struct omap_hwmod_class dra7xx_uart_hwmod_class = { | |
2380 | .name = "uart", | |
2381 | .sysc = &dra7xx_uart_sysc, | |
2382 | }; | |
2383 | ||
2384 | /* uart1 */ | |
2385 | static struct omap_hwmod dra7xx_uart1_hwmod = { | |
2386 | .name = "uart1", | |
2387 | .class = &dra7xx_uart_hwmod_class, | |
2388 | .clkdm_name = "l4per_clkdm", | |
2389 | .main_clk = "uart1_gfclk_mux", | |
38958c15 | 2390 | .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS, |
90020c7b A |
2391 | .prcm = { |
2392 | .omap4 = { | |
2393 | .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET, | |
2394 | .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET, | |
2395 | .modulemode = MODULEMODE_SWCTRL, | |
2396 | }, | |
2397 | }, | |
2398 | }; | |
2399 | ||
2400 | /* uart2 */ | |
2401 | static struct omap_hwmod dra7xx_uart2_hwmod = { | |
2402 | .name = "uart2", | |
2403 | .class = &dra7xx_uart_hwmod_class, | |
2404 | .clkdm_name = "l4per_clkdm", | |
2405 | .main_clk = "uart2_gfclk_mux", | |
2406 | .flags = HWMOD_SWSUP_SIDLE_ACT, | |
2407 | .prcm = { | |
2408 | .omap4 = { | |
2409 | .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET, | |
2410 | .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET, | |
2411 | .modulemode = MODULEMODE_SWCTRL, | |
2412 | }, | |
2413 | }, | |
2414 | }; | |
2415 | ||
2416 | /* uart3 */ | |
2417 | static struct omap_hwmod dra7xx_uart3_hwmod = { | |
2418 | .name = "uart3", | |
2419 | .class = &dra7xx_uart_hwmod_class, | |
2420 | .clkdm_name = "l4per_clkdm", | |
2421 | .main_clk = "uart3_gfclk_mux", | |
1c7e36bf | 2422 | .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS, |
90020c7b A |
2423 | .prcm = { |
2424 | .omap4 = { | |
2425 | .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET, | |
2426 | .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET, | |
2427 | .modulemode = MODULEMODE_SWCTRL, | |
2428 | }, | |
2429 | }, | |
2430 | }; | |
2431 | ||
2432 | /* uart4 */ | |
2433 | static struct omap_hwmod dra7xx_uart4_hwmod = { | |
2434 | .name = "uart4", | |
2435 | .class = &dra7xx_uart_hwmod_class, | |
2436 | .clkdm_name = "l4per_clkdm", | |
2437 | .main_clk = "uart4_gfclk_mux", | |
b0340850 | 2438 | .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART4_FLAGS, |
90020c7b A |
2439 | .prcm = { |
2440 | .omap4 = { | |
2441 | .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET, | |
2442 | .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET, | |
2443 | .modulemode = MODULEMODE_SWCTRL, | |
2444 | }, | |
2445 | }, | |
2446 | }; | |
2447 | ||
2448 | /* uart5 */ | |
2449 | static struct omap_hwmod dra7xx_uart5_hwmod = { | |
2450 | .name = "uart5", | |
2451 | .class = &dra7xx_uart_hwmod_class, | |
2452 | .clkdm_name = "l4per_clkdm", | |
2453 | .main_clk = "uart5_gfclk_mux", | |
2454 | .flags = HWMOD_SWSUP_SIDLE_ACT, | |
2455 | .prcm = { | |
2456 | .omap4 = { | |
2457 | .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET, | |
2458 | .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET, | |
2459 | .modulemode = MODULEMODE_SWCTRL, | |
2460 | }, | |
2461 | }, | |
2462 | }; | |
2463 | ||
2464 | /* uart6 */ | |
2465 | static struct omap_hwmod dra7xx_uart6_hwmod = { | |
2466 | .name = "uart6", | |
2467 | .class = &dra7xx_uart_hwmod_class, | |
2468 | .clkdm_name = "ipu_clkdm", | |
2469 | .main_clk = "uart6_gfclk_mux", | |
2470 | .flags = HWMOD_SWSUP_SIDLE_ACT, | |
2471 | .prcm = { | |
2472 | .omap4 = { | |
2473 | .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET, | |
2474 | .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET, | |
2475 | .modulemode = MODULEMODE_SWCTRL, | |
2476 | }, | |
2477 | }, | |
2478 | }; | |
2479 | ||
33acc9ff A |
2480 | /* uart7 */ |
2481 | static struct omap_hwmod dra7xx_uart7_hwmod = { | |
2482 | .name = "uart7", | |
2483 | .class = &dra7xx_uart_hwmod_class, | |
2484 | .clkdm_name = "l4per2_clkdm", | |
2485 | .main_clk = "uart7_gfclk_mux", | |
2486 | .flags = HWMOD_SWSUP_SIDLE_ACT, | |
2487 | .prcm = { | |
2488 | .omap4 = { | |
2489 | .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET, | |
2490 | .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET, | |
2491 | .modulemode = MODULEMODE_SWCTRL, | |
2492 | }, | |
2493 | }, | |
2494 | }; | |
2495 | ||
2496 | /* uart8 */ | |
2497 | static struct omap_hwmod dra7xx_uart8_hwmod = { | |
2498 | .name = "uart8", | |
2499 | .class = &dra7xx_uart_hwmod_class, | |
2500 | .clkdm_name = "l4per2_clkdm", | |
2501 | .main_clk = "uart8_gfclk_mux", | |
2502 | .flags = HWMOD_SWSUP_SIDLE_ACT, | |
2503 | .prcm = { | |
2504 | .omap4 = { | |
2505 | .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET, | |
2506 | .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET, | |
2507 | .modulemode = MODULEMODE_SWCTRL, | |
2508 | }, | |
2509 | }, | |
2510 | }; | |
2511 | ||
2512 | /* uart9 */ | |
2513 | static struct omap_hwmod dra7xx_uart9_hwmod = { | |
2514 | .name = "uart9", | |
2515 | .class = &dra7xx_uart_hwmod_class, | |
2516 | .clkdm_name = "l4per2_clkdm", | |
2517 | .main_clk = "uart9_gfclk_mux", | |
2518 | .flags = HWMOD_SWSUP_SIDLE_ACT, | |
2519 | .prcm = { | |
2520 | .omap4 = { | |
2521 | .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET, | |
2522 | .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET, | |
2523 | .modulemode = MODULEMODE_SWCTRL, | |
2524 | }, | |
2525 | }, | |
2526 | }; | |
2527 | ||
2528 | /* uart10 */ | |
2529 | static struct omap_hwmod dra7xx_uart10_hwmod = { | |
2530 | .name = "uart10", | |
2531 | .class = &dra7xx_uart_hwmod_class, | |
2532 | .clkdm_name = "wkupaon_clkdm", | |
2533 | .main_clk = "uart10_gfclk_mux", | |
2534 | .flags = HWMOD_SWSUP_SIDLE_ACT, | |
2535 | .prcm = { | |
2536 | .omap4 = { | |
2537 | .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET, | |
2538 | .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET, | |
2539 | .modulemode = MODULEMODE_SWCTRL, | |
2540 | }, | |
2541 | }, | |
2542 | }; | |
2543 | ||
90020c7b A |
2544 | /* |
2545 | * 'usb_otg_ss' class | |
2546 | * | |
2547 | */ | |
2548 | ||
d904b38d RQ |
2549 | static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = { |
2550 | .rev_offs = 0x0000, | |
2551 | .sysc_offs = 0x0010, | |
2552 | .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE | | |
2553 | SYSC_HAS_SIDLEMODE), | |
2554 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2555 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
2556 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
2557 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2558 | }; | |
2559 | ||
90020c7b A |
2560 | static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = { |
2561 | .name = "usb_otg_ss", | |
d904b38d | 2562 | .sysc = &dra7xx_usb_otg_ss_sysc, |
90020c7b A |
2563 | }; |
2564 | ||
2565 | /* usb_otg_ss1 */ | |
2566 | static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = { | |
2567 | { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" }, | |
2568 | }; | |
2569 | ||
2570 | static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = { | |
2571 | .name = "usb_otg_ss1", | |
2572 | .class = &dra7xx_usb_otg_ss_hwmod_class, | |
2573 | .clkdm_name = "l3init_clkdm", | |
2574 | .main_clk = "dpll_core_h13x2_ck", | |
2575 | .prcm = { | |
2576 | .omap4 = { | |
2577 | .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET, | |
2578 | .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET, | |
2579 | .modulemode = MODULEMODE_HWCTRL, | |
2580 | }, | |
2581 | }, | |
2582 | .opt_clks = usb_otg_ss1_opt_clks, | |
2583 | .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks), | |
2584 | }; | |
2585 | ||
2586 | /* usb_otg_ss2 */ | |
2587 | static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = { | |
2588 | { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" }, | |
2589 | }; | |
2590 | ||
2591 | static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = { | |
2592 | .name = "usb_otg_ss2", | |
2593 | .class = &dra7xx_usb_otg_ss_hwmod_class, | |
2594 | .clkdm_name = "l3init_clkdm", | |
2595 | .main_clk = "dpll_core_h13x2_ck", | |
2596 | .prcm = { | |
2597 | .omap4 = { | |
2598 | .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET, | |
2599 | .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET, | |
2600 | .modulemode = MODULEMODE_HWCTRL, | |
2601 | }, | |
2602 | }, | |
2603 | .opt_clks = usb_otg_ss2_opt_clks, | |
2604 | .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks), | |
2605 | }; | |
2606 | ||
2607 | /* usb_otg_ss3 */ | |
2608 | static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = { | |
2609 | .name = "usb_otg_ss3", | |
2610 | .class = &dra7xx_usb_otg_ss_hwmod_class, | |
2611 | .clkdm_name = "l3init_clkdm", | |
2612 | .main_clk = "dpll_core_h13x2_ck", | |
2613 | .prcm = { | |
2614 | .omap4 = { | |
2615 | .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET, | |
2616 | .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET, | |
2617 | .modulemode = MODULEMODE_HWCTRL, | |
2618 | }, | |
2619 | }, | |
2620 | }; | |
2621 | ||
2622 | /* usb_otg_ss4 */ | |
2623 | static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = { | |
2624 | .name = "usb_otg_ss4", | |
2625 | .class = &dra7xx_usb_otg_ss_hwmod_class, | |
2626 | .clkdm_name = "l3init_clkdm", | |
2627 | .main_clk = "dpll_core_h13x2_ck", | |
2628 | .prcm = { | |
2629 | .omap4 = { | |
2630 | .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET, | |
2631 | .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET, | |
2632 | .modulemode = MODULEMODE_HWCTRL, | |
2633 | }, | |
2634 | }, | |
2635 | }; | |
2636 | ||
2637 | /* | |
2638 | * 'vcp' class | |
2639 | * | |
2640 | */ | |
2641 | ||
2642 | static struct omap_hwmod_class dra7xx_vcp_hwmod_class = { | |
2643 | .name = "vcp", | |
2644 | }; | |
2645 | ||
2646 | /* vcp1 */ | |
2647 | static struct omap_hwmod dra7xx_vcp1_hwmod = { | |
2648 | .name = "vcp1", | |
2649 | .class = &dra7xx_vcp_hwmod_class, | |
2650 | .clkdm_name = "l3main1_clkdm", | |
2651 | .main_clk = "l3_iclk_div", | |
2652 | .prcm = { | |
2653 | .omap4 = { | |
2654 | .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET, | |
2655 | .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET, | |
2656 | }, | |
2657 | }, | |
2658 | }; | |
2659 | ||
2660 | /* vcp2 */ | |
2661 | static struct omap_hwmod dra7xx_vcp2_hwmod = { | |
2662 | .name = "vcp2", | |
2663 | .class = &dra7xx_vcp_hwmod_class, | |
2664 | .clkdm_name = "l3main1_clkdm", | |
2665 | .main_clk = "l3_iclk_div", | |
2666 | .prcm = { | |
2667 | .omap4 = { | |
2668 | .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET, | |
2669 | .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET, | |
2670 | }, | |
2671 | }, | |
2672 | }; | |
2673 | ||
2674 | /* | |
2675 | * 'wd_timer' class | |
2676 | * | |
2677 | */ | |
2678 | ||
2679 | static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = { | |
2680 | .rev_offs = 0x0000, | |
2681 | .sysc_offs = 0x0010, | |
2682 | .syss_offs = 0x0014, | |
2683 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
2684 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
2685 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2686 | SIDLE_SMART_WKUP), | |
2687 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2688 | }; | |
2689 | ||
2690 | static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = { | |
2691 | .name = "wd_timer", | |
2692 | .sysc = &dra7xx_wd_timer_sysc, | |
2693 | .pre_shutdown = &omap2_wd_timer_disable, | |
2694 | .reset = &omap2_wd_timer_reset, | |
2695 | }; | |
2696 | ||
2697 | /* wd_timer2 */ | |
2698 | static struct omap_hwmod dra7xx_wd_timer2_hwmod = { | |
2699 | .name = "wd_timer2", | |
2700 | .class = &dra7xx_wd_timer_hwmod_class, | |
2701 | .clkdm_name = "wkupaon_clkdm", | |
2702 | .main_clk = "sys_32k_ck", | |
2703 | .prcm = { | |
2704 | .omap4 = { | |
2705 | .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET, | |
2706 | .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET, | |
2707 | .modulemode = MODULEMODE_SWCTRL, | |
2708 | }, | |
2709 | }, | |
2710 | }; | |
2711 | ||
2712 | ||
2713 | /* | |
2714 | * Interfaces | |
2715 | */ | |
2716 | ||
42121688 TV |
2717 | /* l3_main_1 -> dmm */ |
2718 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = { | |
2719 | .master = &dra7xx_l3_main_1_hwmod, | |
2720 | .slave = &dra7xx_dmm_hwmod, | |
2721 | .clk = "l3_iclk_div", | |
2722 | .user = OCP_USER_SDMA, | |
2723 | }; | |
2724 | ||
90020c7b A |
2725 | /* l3_main_2 -> l3_instr */ |
2726 | static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = { | |
2727 | .master = &dra7xx_l3_main_2_hwmod, | |
2728 | .slave = &dra7xx_l3_instr_hwmod, | |
2729 | .clk = "l3_iclk_div", | |
2730 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2731 | }; | |
2732 | ||
2733 | /* l4_cfg -> l3_main_1 */ | |
2734 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = { | |
2735 | .master = &dra7xx_l4_cfg_hwmod, | |
2736 | .slave = &dra7xx_l3_main_1_hwmod, | |
2737 | .clk = "l3_iclk_div", | |
2738 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2739 | }; | |
2740 | ||
2741 | /* mpu -> l3_main_1 */ | |
2742 | static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = { | |
2743 | .master = &dra7xx_mpu_hwmod, | |
2744 | .slave = &dra7xx_l3_main_1_hwmod, | |
2745 | .clk = "l3_iclk_div", | |
2746 | .user = OCP_USER_MPU, | |
2747 | }; | |
2748 | ||
2749 | /* l3_main_1 -> l3_main_2 */ | |
2750 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = { | |
2751 | .master = &dra7xx_l3_main_1_hwmod, | |
2752 | .slave = &dra7xx_l3_main_2_hwmod, | |
2753 | .clk = "l3_iclk_div", | |
2754 | .user = OCP_USER_MPU, | |
2755 | }; | |
2756 | ||
2757 | /* l4_cfg -> l3_main_2 */ | |
2758 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = { | |
2759 | .master = &dra7xx_l4_cfg_hwmod, | |
2760 | .slave = &dra7xx_l3_main_2_hwmod, | |
2761 | .clk = "l3_iclk_div", | |
2762 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2763 | }; | |
2764 | ||
2765 | /* l3_main_1 -> l4_cfg */ | |
2766 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = { | |
2767 | .master = &dra7xx_l3_main_1_hwmod, | |
2768 | .slave = &dra7xx_l4_cfg_hwmod, | |
2769 | .clk = "l3_iclk_div", | |
2770 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2771 | }; | |
2772 | ||
2773 | /* l3_main_1 -> l4_per1 */ | |
2774 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = { | |
2775 | .master = &dra7xx_l3_main_1_hwmod, | |
2776 | .slave = &dra7xx_l4_per1_hwmod, | |
2777 | .clk = "l3_iclk_div", | |
2778 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2779 | }; | |
2780 | ||
2781 | /* l3_main_1 -> l4_per2 */ | |
2782 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = { | |
2783 | .master = &dra7xx_l3_main_1_hwmod, | |
2784 | .slave = &dra7xx_l4_per2_hwmod, | |
2785 | .clk = "l3_iclk_div", | |
2786 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2787 | }; | |
2788 | ||
2789 | /* l3_main_1 -> l4_per3 */ | |
2790 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = { | |
2791 | .master = &dra7xx_l3_main_1_hwmod, | |
2792 | .slave = &dra7xx_l4_per3_hwmod, | |
2793 | .clk = "l3_iclk_div", | |
2794 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2795 | }; | |
2796 | ||
2797 | /* l3_main_1 -> l4_wkup */ | |
2798 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = { | |
2799 | .master = &dra7xx_l3_main_1_hwmod, | |
2800 | .slave = &dra7xx_l4_wkup_hwmod, | |
2801 | .clk = "wkupaon_iclk_mux", | |
2802 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2803 | }; | |
2804 | ||
2805 | /* l4_per2 -> atl */ | |
2806 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = { | |
2807 | .master = &dra7xx_l4_per2_hwmod, | |
2808 | .slave = &dra7xx_atl_hwmod, | |
2809 | .clk = "l3_iclk_div", | |
2810 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2811 | }; | |
2812 | ||
2813 | /* l3_main_1 -> bb2d */ | |
2814 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = { | |
2815 | .master = &dra7xx_l3_main_1_hwmod, | |
2816 | .slave = &dra7xx_bb2d_hwmod, | |
2817 | .clk = "l3_iclk_div", | |
2818 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2819 | }; | |
2820 | ||
2821 | /* l4_wkup -> counter_32k */ | |
2822 | static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = { | |
2823 | .master = &dra7xx_l4_wkup_hwmod, | |
2824 | .slave = &dra7xx_counter_32k_hwmod, | |
2825 | .clk = "wkupaon_iclk_mux", | |
2826 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2827 | }; | |
2828 | ||
2829 | /* l4_wkup -> ctrl_module_wkup */ | |
2830 | static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = { | |
2831 | .master = &dra7xx_l4_wkup_hwmod, | |
2832 | .slave = &dra7xx_ctrl_module_wkup_hwmod, | |
2833 | .clk = "wkupaon_iclk_mux", | |
2834 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2835 | }; | |
2836 | ||
077c42f7 M |
2837 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = { |
2838 | .master = &dra7xx_l4_per2_hwmod, | |
2839 | .slave = &dra7xx_gmac_hwmod, | |
2840 | .clk = "dpll_gmac_ck", | |
2841 | .user = OCP_USER_MPU, | |
2842 | }; | |
2843 | ||
2844 | static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = { | |
2845 | .master = &dra7xx_gmac_hwmod, | |
2846 | .slave = &dra7xx_mdio_hwmod, | |
2847 | .user = OCP_USER_MPU, | |
2848 | }; | |
2849 | ||
90020c7b A |
2850 | /* l4_wkup -> dcan1 */ |
2851 | static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = { | |
2852 | .master = &dra7xx_l4_wkup_hwmod, | |
2853 | .slave = &dra7xx_dcan1_hwmod, | |
2854 | .clk = "wkupaon_iclk_mux", | |
2855 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2856 | }; | |
2857 | ||
2858 | /* l4_per2 -> dcan2 */ | |
2859 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = { | |
2860 | .master = &dra7xx_l4_per2_hwmod, | |
2861 | .slave = &dra7xx_dcan2_hwmod, | |
2862 | .clk = "l3_iclk_div", | |
2863 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2864 | }; | |
2865 | ||
2866 | static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = { | |
2867 | { | |
2868 | .pa_start = 0x4a056000, | |
2869 | .pa_end = 0x4a056fff, | |
2870 | .flags = ADDR_TYPE_RT | |
2871 | }, | |
2872 | { } | |
2873 | }; | |
2874 | ||
2875 | /* l4_cfg -> dma_system */ | |
2876 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = { | |
2877 | .master = &dra7xx_l4_cfg_hwmod, | |
2878 | .slave = &dra7xx_dma_system_hwmod, | |
2879 | .clk = "l3_iclk_div", | |
2880 | .addr = dra7xx_dma_system_addrs, | |
2881 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2882 | }; | |
2883 | ||
34b4182c PU |
2884 | /* l3_main_1 -> tpcc */ |
2885 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = { | |
2886 | .master = &dra7xx_l3_main_1_hwmod, | |
2887 | .slave = &dra7xx_tpcc_hwmod, | |
2888 | .clk = "l3_iclk_div", | |
2889 | .user = OCP_USER_MPU, | |
2890 | }; | |
2891 | ||
2892 | /* l3_main_1 -> tptc0 */ | |
2893 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = { | |
2894 | .master = &dra7xx_l3_main_1_hwmod, | |
2895 | .slave = &dra7xx_tptc0_hwmod, | |
2896 | .clk = "l3_iclk_div", | |
2897 | .user = OCP_USER_MPU, | |
2898 | }; | |
2899 | ||
2900 | /* l3_main_1 -> tptc1 */ | |
2901 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = { | |
2902 | .master = &dra7xx_l3_main_1_hwmod, | |
2903 | .slave = &dra7xx_tptc1_hwmod, | |
2904 | .clk = "l3_iclk_div", | |
2905 | .user = OCP_USER_MPU, | |
2906 | }; | |
2907 | ||
90020c7b A |
2908 | static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = { |
2909 | { | |
2910 | .name = "family", | |
2911 | .pa_start = 0x58000000, | |
2912 | .pa_end = 0x5800007f, | |
2913 | .flags = ADDR_TYPE_RT | |
2914 | }, | |
2915 | }; | |
2916 | ||
2917 | /* l3_main_1 -> dss */ | |
2918 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = { | |
2919 | .master = &dra7xx_l3_main_1_hwmod, | |
2920 | .slave = &dra7xx_dss_hwmod, | |
2921 | .clk = "l3_iclk_div", | |
2922 | .addr = dra7xx_dss_addrs, | |
2923 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2924 | }; | |
2925 | ||
2926 | static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = { | |
2927 | { | |
2928 | .name = "dispc", | |
2929 | .pa_start = 0x58001000, | |
2930 | .pa_end = 0x58001fff, | |
2931 | .flags = ADDR_TYPE_RT | |
2932 | }, | |
2933 | }; | |
2934 | ||
2935 | /* l3_main_1 -> dispc */ | |
2936 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = { | |
2937 | .master = &dra7xx_l3_main_1_hwmod, | |
2938 | .slave = &dra7xx_dss_dispc_hwmod, | |
2939 | .clk = "l3_iclk_div", | |
2940 | .addr = dra7xx_dss_dispc_addrs, | |
2941 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2942 | }; | |
2943 | ||
2944 | static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = { | |
2945 | { | |
2946 | .name = "hdmi_wp", | |
2947 | .pa_start = 0x58040000, | |
2948 | .pa_end = 0x580400ff, | |
2949 | .flags = ADDR_TYPE_RT | |
2950 | }, | |
2951 | { } | |
2952 | }; | |
2953 | ||
2954 | /* l3_main_1 -> dispc */ | |
2955 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = { | |
2956 | .master = &dra7xx_l3_main_1_hwmod, | |
2957 | .slave = &dra7xx_dss_hdmi_hwmod, | |
2958 | .clk = "l3_iclk_div", | |
2959 | .addr = dra7xx_dss_hdmi_addrs, | |
2960 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2961 | }; | |
2962 | ||
9ad4d9a3 PU |
2963 | /* l4_per2 -> mcasp1 */ |
2964 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = { | |
2965 | .master = &dra7xx_l4_per2_hwmod, | |
2966 | .slave = &dra7xx_mcasp1_hwmod, | |
2967 | .clk = "l4_root_clk_div", | |
2968 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2969 | }; | |
2970 | ||
2971 | /* l3_main_1 -> mcasp1 */ | |
2972 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = { | |
2973 | .master = &dra7xx_l3_main_1_hwmod, | |
2974 | .slave = &dra7xx_mcasp1_hwmod, | |
2975 | .clk = "l3_iclk_div", | |
2976 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2977 | }; | |
2978 | ||
2979 | /* l4_per2 -> mcasp2 */ | |
2980 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = { | |
2981 | .master = &dra7xx_l4_per2_hwmod, | |
2982 | .slave = &dra7xx_mcasp2_hwmod, | |
2983 | .clk = "l4_root_clk_div", | |
2984 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2985 | }; | |
2986 | ||
2987 | /* l3_main_1 -> mcasp2 */ | |
2988 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = { | |
2989 | .master = &dra7xx_l3_main_1_hwmod, | |
2990 | .slave = &dra7xx_mcasp2_hwmod, | |
2991 | .clk = "l3_iclk_div", | |
2992 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2993 | }; | |
2994 | ||
469689a4 PU |
2995 | /* l4_per2 -> mcasp3 */ |
2996 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = { | |
2997 | .master = &dra7xx_l4_per2_hwmod, | |
2998 | .slave = &dra7xx_mcasp3_hwmod, | |
2999 | .clk = "l4_root_clk_div", | |
3000 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3001 | }; | |
3002 | ||
3003 | /* l3_main_1 -> mcasp3 */ | |
3004 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = { | |
3005 | .master = &dra7xx_l3_main_1_hwmod, | |
3006 | .slave = &dra7xx_mcasp3_hwmod, | |
3007 | .clk = "l3_iclk_div", | |
3008 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3009 | }; | |
3010 | ||
9ad4d9a3 PU |
3011 | /* l4_per2 -> mcasp4 */ |
3012 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = { | |
3013 | .master = &dra7xx_l4_per2_hwmod, | |
3014 | .slave = &dra7xx_mcasp4_hwmod, | |
3015 | .clk = "l4_root_clk_div", | |
3016 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3017 | }; | |
3018 | ||
3019 | /* l4_per2 -> mcasp5 */ | |
3020 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = { | |
3021 | .master = &dra7xx_l4_per2_hwmod, | |
3022 | .slave = &dra7xx_mcasp5_hwmod, | |
3023 | .clk = "l4_root_clk_div", | |
3024 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3025 | }; | |
3026 | ||
3027 | /* l4_per2 -> mcasp6 */ | |
3028 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = { | |
3029 | .master = &dra7xx_l4_per2_hwmod, | |
3030 | .slave = &dra7xx_mcasp6_hwmod, | |
3031 | .clk = "l4_root_clk_div", | |
3032 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3033 | }; | |
3034 | ||
3035 | /* l4_per2 -> mcasp7 */ | |
3036 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = { | |
3037 | .master = &dra7xx_l4_per2_hwmod, | |
3038 | .slave = &dra7xx_mcasp7_hwmod, | |
3039 | .clk = "l4_root_clk_div", | |
3040 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3041 | }; | |
3042 | ||
3043 | /* l4_per2 -> mcasp8 */ | |
3044 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = { | |
3045 | .master = &dra7xx_l4_per2_hwmod, | |
3046 | .slave = &dra7xx_mcasp8_hwmod, | |
3047 | .clk = "l4_root_clk_div", | |
3048 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3049 | }; | |
3050 | ||
90020c7b A |
3051 | /* l4_per1 -> elm */ |
3052 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = { | |
3053 | .master = &dra7xx_l4_per1_hwmod, | |
3054 | .slave = &dra7xx_elm_hwmod, | |
3055 | .clk = "l3_iclk_div", | |
90020c7b A |
3056 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3057 | }; | |
3058 | ||
3059 | /* l4_wkup -> gpio1 */ | |
3060 | static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = { | |
3061 | .master = &dra7xx_l4_wkup_hwmod, | |
3062 | .slave = &dra7xx_gpio1_hwmod, | |
3063 | .clk = "wkupaon_iclk_mux", | |
3064 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3065 | }; | |
3066 | ||
3067 | /* l4_per1 -> gpio2 */ | |
3068 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = { | |
3069 | .master = &dra7xx_l4_per1_hwmod, | |
3070 | .slave = &dra7xx_gpio2_hwmod, | |
3071 | .clk = "l3_iclk_div", | |
3072 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3073 | }; | |
3074 | ||
3075 | /* l4_per1 -> gpio3 */ | |
3076 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = { | |
3077 | .master = &dra7xx_l4_per1_hwmod, | |
3078 | .slave = &dra7xx_gpio3_hwmod, | |
3079 | .clk = "l3_iclk_div", | |
3080 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3081 | }; | |
3082 | ||
3083 | /* l4_per1 -> gpio4 */ | |
3084 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = { | |
3085 | .master = &dra7xx_l4_per1_hwmod, | |
3086 | .slave = &dra7xx_gpio4_hwmod, | |
3087 | .clk = "l3_iclk_div", | |
3088 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3089 | }; | |
3090 | ||
3091 | /* l4_per1 -> gpio5 */ | |
3092 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = { | |
3093 | .master = &dra7xx_l4_per1_hwmod, | |
3094 | .slave = &dra7xx_gpio5_hwmod, | |
3095 | .clk = "l3_iclk_div", | |
3096 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3097 | }; | |
3098 | ||
3099 | /* l4_per1 -> gpio6 */ | |
3100 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = { | |
3101 | .master = &dra7xx_l4_per1_hwmod, | |
3102 | .slave = &dra7xx_gpio6_hwmod, | |
3103 | .clk = "l3_iclk_div", | |
3104 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3105 | }; | |
3106 | ||
3107 | /* l4_per1 -> gpio7 */ | |
3108 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = { | |
3109 | .master = &dra7xx_l4_per1_hwmod, | |
3110 | .slave = &dra7xx_gpio7_hwmod, | |
3111 | .clk = "l3_iclk_div", | |
3112 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3113 | }; | |
3114 | ||
3115 | /* l4_per1 -> gpio8 */ | |
3116 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = { | |
3117 | .master = &dra7xx_l4_per1_hwmod, | |
3118 | .slave = &dra7xx_gpio8_hwmod, | |
3119 | .clk = "l3_iclk_div", | |
3120 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3121 | }; | |
3122 | ||
90020c7b A |
3123 | /* l3_main_1 -> gpmc */ |
3124 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = { | |
3125 | .master = &dra7xx_l3_main_1_hwmod, | |
3126 | .slave = &dra7xx_gpmc_hwmod, | |
3127 | .clk = "l3_iclk_div", | |
90020c7b A |
3128 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3129 | }; | |
3130 | ||
3131 | static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = { | |
3132 | { | |
3133 | .pa_start = 0x480b2000, | |
3134 | .pa_end = 0x480b201f, | |
3135 | .flags = ADDR_TYPE_RT | |
3136 | }, | |
3137 | { } | |
3138 | }; | |
3139 | ||
3140 | /* l4_per1 -> hdq1w */ | |
3141 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = { | |
3142 | .master = &dra7xx_l4_per1_hwmod, | |
3143 | .slave = &dra7xx_hdq1w_hwmod, | |
3144 | .clk = "l3_iclk_div", | |
3145 | .addr = dra7xx_hdq1w_addrs, | |
3146 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3147 | }; | |
3148 | ||
3149 | /* l4_per1 -> i2c1 */ | |
3150 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = { | |
3151 | .master = &dra7xx_l4_per1_hwmod, | |
3152 | .slave = &dra7xx_i2c1_hwmod, | |
3153 | .clk = "l3_iclk_div", | |
3154 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3155 | }; | |
3156 | ||
3157 | /* l4_per1 -> i2c2 */ | |
3158 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = { | |
3159 | .master = &dra7xx_l4_per1_hwmod, | |
3160 | .slave = &dra7xx_i2c2_hwmod, | |
3161 | .clk = "l3_iclk_div", | |
3162 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3163 | }; | |
3164 | ||
3165 | /* l4_per1 -> i2c3 */ | |
3166 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = { | |
3167 | .master = &dra7xx_l4_per1_hwmod, | |
3168 | .slave = &dra7xx_i2c3_hwmod, | |
3169 | .clk = "l3_iclk_div", | |
3170 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3171 | }; | |
3172 | ||
3173 | /* l4_per1 -> i2c4 */ | |
3174 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = { | |
3175 | .master = &dra7xx_l4_per1_hwmod, | |
3176 | .slave = &dra7xx_i2c4_hwmod, | |
3177 | .clk = "l3_iclk_div", | |
3178 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3179 | }; | |
3180 | ||
3181 | /* l4_per1 -> i2c5 */ | |
3182 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = { | |
3183 | .master = &dra7xx_l4_per1_hwmod, | |
3184 | .slave = &dra7xx_i2c5_hwmod, | |
3185 | .clk = "l3_iclk_div", | |
3186 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3187 | }; | |
3188 | ||
067395d4 SA |
3189 | /* l4_cfg -> mailbox1 */ |
3190 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = { | |
3191 | .master = &dra7xx_l4_cfg_hwmod, | |
3192 | .slave = &dra7xx_mailbox1_hwmod, | |
3193 | .clk = "l3_iclk_div", | |
3194 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3195 | }; | |
3196 | ||
3197 | /* l4_per3 -> mailbox2 */ | |
3198 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = { | |
3199 | .master = &dra7xx_l4_per3_hwmod, | |
3200 | .slave = &dra7xx_mailbox2_hwmod, | |
3201 | .clk = "l3_iclk_div", | |
3202 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3203 | }; | |
3204 | ||
3205 | /* l4_per3 -> mailbox3 */ | |
3206 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = { | |
3207 | .master = &dra7xx_l4_per3_hwmod, | |
3208 | .slave = &dra7xx_mailbox3_hwmod, | |
3209 | .clk = "l3_iclk_div", | |
3210 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3211 | }; | |
3212 | ||
3213 | /* l4_per3 -> mailbox4 */ | |
3214 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = { | |
3215 | .master = &dra7xx_l4_per3_hwmod, | |
3216 | .slave = &dra7xx_mailbox4_hwmod, | |
3217 | .clk = "l3_iclk_div", | |
3218 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3219 | }; | |
3220 | ||
3221 | /* l4_per3 -> mailbox5 */ | |
3222 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = { | |
3223 | .master = &dra7xx_l4_per3_hwmod, | |
3224 | .slave = &dra7xx_mailbox5_hwmod, | |
3225 | .clk = "l3_iclk_div", | |
3226 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3227 | }; | |
3228 | ||
3229 | /* l4_per3 -> mailbox6 */ | |
3230 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = { | |
3231 | .master = &dra7xx_l4_per3_hwmod, | |
3232 | .slave = &dra7xx_mailbox6_hwmod, | |
3233 | .clk = "l3_iclk_div", | |
3234 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3235 | }; | |
3236 | ||
3237 | /* l4_per3 -> mailbox7 */ | |
3238 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = { | |
3239 | .master = &dra7xx_l4_per3_hwmod, | |
3240 | .slave = &dra7xx_mailbox7_hwmod, | |
3241 | .clk = "l3_iclk_div", | |
3242 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3243 | }; | |
3244 | ||
3245 | /* l4_per3 -> mailbox8 */ | |
3246 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = { | |
3247 | .master = &dra7xx_l4_per3_hwmod, | |
3248 | .slave = &dra7xx_mailbox8_hwmod, | |
3249 | .clk = "l3_iclk_div", | |
3250 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3251 | }; | |
3252 | ||
3253 | /* l4_per3 -> mailbox9 */ | |
3254 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = { | |
3255 | .master = &dra7xx_l4_per3_hwmod, | |
3256 | .slave = &dra7xx_mailbox9_hwmod, | |
3257 | .clk = "l3_iclk_div", | |
3258 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3259 | }; | |
3260 | ||
3261 | /* l4_per3 -> mailbox10 */ | |
3262 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = { | |
3263 | .master = &dra7xx_l4_per3_hwmod, | |
3264 | .slave = &dra7xx_mailbox10_hwmod, | |
3265 | .clk = "l3_iclk_div", | |
3266 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3267 | }; | |
3268 | ||
3269 | /* l4_per3 -> mailbox11 */ | |
3270 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = { | |
3271 | .master = &dra7xx_l4_per3_hwmod, | |
3272 | .slave = &dra7xx_mailbox11_hwmod, | |
3273 | .clk = "l3_iclk_div", | |
3274 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3275 | }; | |
3276 | ||
3277 | /* l4_per3 -> mailbox12 */ | |
3278 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = { | |
3279 | .master = &dra7xx_l4_per3_hwmod, | |
3280 | .slave = &dra7xx_mailbox12_hwmod, | |
3281 | .clk = "l3_iclk_div", | |
3282 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3283 | }; | |
3284 | ||
3285 | /* l4_per3 -> mailbox13 */ | |
3286 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = { | |
3287 | .master = &dra7xx_l4_per3_hwmod, | |
3288 | .slave = &dra7xx_mailbox13_hwmod, | |
3289 | .clk = "l3_iclk_div", | |
3290 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3291 | }; | |
3292 | ||
90020c7b A |
3293 | /* l4_per1 -> mcspi1 */ |
3294 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = { | |
3295 | .master = &dra7xx_l4_per1_hwmod, | |
3296 | .slave = &dra7xx_mcspi1_hwmod, | |
3297 | .clk = "l3_iclk_div", | |
3298 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3299 | }; | |
3300 | ||
3301 | /* l4_per1 -> mcspi2 */ | |
3302 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = { | |
3303 | .master = &dra7xx_l4_per1_hwmod, | |
3304 | .slave = &dra7xx_mcspi2_hwmod, | |
3305 | .clk = "l3_iclk_div", | |
3306 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3307 | }; | |
3308 | ||
3309 | /* l4_per1 -> mcspi3 */ | |
3310 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = { | |
3311 | .master = &dra7xx_l4_per1_hwmod, | |
3312 | .slave = &dra7xx_mcspi3_hwmod, | |
3313 | .clk = "l3_iclk_div", | |
3314 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3315 | }; | |
3316 | ||
3317 | /* l4_per1 -> mcspi4 */ | |
3318 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = { | |
3319 | .master = &dra7xx_l4_per1_hwmod, | |
3320 | .slave = &dra7xx_mcspi4_hwmod, | |
3321 | .clk = "l3_iclk_div", | |
3322 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3323 | }; | |
3324 | ||
3325 | /* l4_per1 -> mmc1 */ | |
3326 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = { | |
3327 | .master = &dra7xx_l4_per1_hwmod, | |
3328 | .slave = &dra7xx_mmc1_hwmod, | |
3329 | .clk = "l3_iclk_div", | |
3330 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3331 | }; | |
3332 | ||
3333 | /* l4_per1 -> mmc2 */ | |
3334 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = { | |
3335 | .master = &dra7xx_l4_per1_hwmod, | |
3336 | .slave = &dra7xx_mmc2_hwmod, | |
3337 | .clk = "l3_iclk_div", | |
3338 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3339 | }; | |
3340 | ||
3341 | /* l4_per1 -> mmc3 */ | |
3342 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = { | |
3343 | .master = &dra7xx_l4_per1_hwmod, | |
3344 | .slave = &dra7xx_mmc3_hwmod, | |
3345 | .clk = "l3_iclk_div", | |
3346 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3347 | }; | |
3348 | ||
3349 | /* l4_per1 -> mmc4 */ | |
3350 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = { | |
3351 | .master = &dra7xx_l4_per1_hwmod, | |
3352 | .slave = &dra7xx_mmc4_hwmod, | |
3353 | .clk = "l3_iclk_div", | |
3354 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3355 | }; | |
3356 | ||
3357 | /* l4_cfg -> mpu */ | |
3358 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = { | |
3359 | .master = &dra7xx_l4_cfg_hwmod, | |
3360 | .slave = &dra7xx_mpu_hwmod, | |
3361 | .clk = "l3_iclk_div", | |
3362 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3363 | }; | |
3364 | ||
90020c7b A |
3365 | /* l4_cfg -> ocp2scp1 */ |
3366 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = { | |
3367 | .master = &dra7xx_l4_cfg_hwmod, | |
3368 | .slave = &dra7xx_ocp2scp1_hwmod, | |
3369 | .clk = "l4_root_clk_div", | |
90020c7b A |
3370 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3371 | }; | |
3372 | ||
df0d0f11 RQ |
3373 | /* l4_cfg -> ocp2scp3 */ |
3374 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = { | |
3375 | .master = &dra7xx_l4_cfg_hwmod, | |
3376 | .slave = &dra7xx_ocp2scp3_hwmod, | |
3377 | .clk = "l4_root_clk_div", | |
3378 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3379 | }; | |
3380 | ||
0717103e KVA |
3381 | /* l3_main_1 -> pciess1 */ |
3382 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = { | |
8dd3eb71 | 3383 | .master = &dra7xx_l3_main_1_hwmod, |
0717103e | 3384 | .slave = &dra7xx_pciess1_hwmod, |
8dd3eb71 KVA |
3385 | .clk = "l3_iclk_div", |
3386 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3387 | }; | |
3388 | ||
0717103e KVA |
3389 | /* l4_cfg -> pciess1 */ |
3390 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = { | |
8dd3eb71 | 3391 | .master = &dra7xx_l4_cfg_hwmod, |
0717103e | 3392 | .slave = &dra7xx_pciess1_hwmod, |
8dd3eb71 KVA |
3393 | .clk = "l4_root_clk_div", |
3394 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3395 | }; | |
3396 | ||
0717103e KVA |
3397 | /* l3_main_1 -> pciess2 */ |
3398 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = { | |
8dd3eb71 | 3399 | .master = &dra7xx_l3_main_1_hwmod, |
0717103e | 3400 | .slave = &dra7xx_pciess2_hwmod, |
8dd3eb71 KVA |
3401 | .clk = "l3_iclk_div", |
3402 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3403 | }; | |
3404 | ||
0717103e KVA |
3405 | /* l4_cfg -> pciess2 */ |
3406 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = { | |
70c18ef7 | 3407 | .master = &dra7xx_l4_cfg_hwmod, |
0717103e | 3408 | .slave = &dra7xx_pciess2_hwmod, |
70c18ef7 KVA |
3409 | .clk = "l4_root_clk_div", |
3410 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3411 | }; | |
3412 | ||
90020c7b A |
3413 | static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = { |
3414 | { | |
3415 | .pa_start = 0x4b300000, | |
3416 | .pa_end = 0x4b30007f, | |
3417 | .flags = ADDR_TYPE_RT | |
3418 | }, | |
3419 | { } | |
3420 | }; | |
3421 | ||
3422 | /* l3_main_1 -> qspi */ | |
3423 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = { | |
3424 | .master = &dra7xx_l3_main_1_hwmod, | |
3425 | .slave = &dra7xx_qspi_hwmod, | |
3426 | .clk = "l3_iclk_div", | |
3427 | .addr = dra7xx_qspi_addrs, | |
3428 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3429 | }; | |
3430 | ||
c913c8a1 LV |
3431 | /* l4_per3 -> rtcss */ |
3432 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = { | |
3433 | .master = &dra7xx_l4_per3_hwmod, | |
3434 | .slave = &dra7xx_rtcss_hwmod, | |
3435 | .clk = "l4_root_clk_div", | |
3436 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3437 | }; | |
3438 | ||
90020c7b A |
3439 | static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = { |
3440 | { | |
3441 | .name = "sysc", | |
3442 | .pa_start = 0x4a141100, | |
3443 | .pa_end = 0x4a141107, | |
3444 | .flags = ADDR_TYPE_RT | |
3445 | }, | |
3446 | { } | |
3447 | }; | |
3448 | ||
3449 | /* l4_cfg -> sata */ | |
3450 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = { | |
3451 | .master = &dra7xx_l4_cfg_hwmod, | |
3452 | .slave = &dra7xx_sata_hwmod, | |
3453 | .clk = "l3_iclk_div", | |
3454 | .addr = dra7xx_sata_addrs, | |
3455 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3456 | }; | |
3457 | ||
3458 | static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = { | |
3459 | { | |
3460 | .pa_start = 0x4a0dd000, | |
3461 | .pa_end = 0x4a0dd07f, | |
3462 | .flags = ADDR_TYPE_RT | |
3463 | }, | |
3464 | { } | |
3465 | }; | |
3466 | ||
3467 | /* l4_cfg -> smartreflex_core */ | |
3468 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = { | |
3469 | .master = &dra7xx_l4_cfg_hwmod, | |
3470 | .slave = &dra7xx_smartreflex_core_hwmod, | |
3471 | .clk = "l4_root_clk_div", | |
3472 | .addr = dra7xx_smartreflex_core_addrs, | |
3473 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3474 | }; | |
3475 | ||
3476 | static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = { | |
3477 | { | |
3478 | .pa_start = 0x4a0d9000, | |
3479 | .pa_end = 0x4a0d907f, | |
3480 | .flags = ADDR_TYPE_RT | |
3481 | }, | |
3482 | { } | |
3483 | }; | |
3484 | ||
3485 | /* l4_cfg -> smartreflex_mpu */ | |
3486 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = { | |
3487 | .master = &dra7xx_l4_cfg_hwmod, | |
3488 | .slave = &dra7xx_smartreflex_mpu_hwmod, | |
3489 | .clk = "l4_root_clk_div", | |
3490 | .addr = dra7xx_smartreflex_mpu_addrs, | |
3491 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3492 | }; | |
3493 | ||
90020c7b A |
3494 | /* l4_cfg -> spinlock */ |
3495 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = { | |
3496 | .master = &dra7xx_l4_cfg_hwmod, | |
3497 | .slave = &dra7xx_spinlock_hwmod, | |
3498 | .clk = "l3_iclk_div", | |
90020c7b A |
3499 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3500 | }; | |
3501 | ||
3502 | /* l4_wkup -> timer1 */ | |
3503 | static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = { | |
3504 | .master = &dra7xx_l4_wkup_hwmod, | |
3505 | .slave = &dra7xx_timer1_hwmod, | |
3506 | .clk = "wkupaon_iclk_mux", | |
3507 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3508 | }; | |
3509 | ||
3510 | /* l4_per1 -> timer2 */ | |
3511 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = { | |
3512 | .master = &dra7xx_l4_per1_hwmod, | |
3513 | .slave = &dra7xx_timer2_hwmod, | |
3514 | .clk = "l3_iclk_div", | |
3515 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3516 | }; | |
3517 | ||
3518 | /* l4_per1 -> timer3 */ | |
3519 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = { | |
3520 | .master = &dra7xx_l4_per1_hwmod, | |
3521 | .slave = &dra7xx_timer3_hwmod, | |
3522 | .clk = "l3_iclk_div", | |
3523 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3524 | }; | |
3525 | ||
3526 | /* l4_per1 -> timer4 */ | |
3527 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = { | |
3528 | .master = &dra7xx_l4_per1_hwmod, | |
3529 | .slave = &dra7xx_timer4_hwmod, | |
3530 | .clk = "l3_iclk_div", | |
3531 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3532 | }; | |
3533 | ||
3534 | /* l4_per3 -> timer5 */ | |
3535 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = { | |
3536 | .master = &dra7xx_l4_per3_hwmod, | |
3537 | .slave = &dra7xx_timer5_hwmod, | |
3538 | .clk = "l3_iclk_div", | |
3539 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3540 | }; | |
3541 | ||
3542 | /* l4_per3 -> timer6 */ | |
3543 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = { | |
3544 | .master = &dra7xx_l4_per3_hwmod, | |
3545 | .slave = &dra7xx_timer6_hwmod, | |
3546 | .clk = "l3_iclk_div", | |
3547 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3548 | }; | |
3549 | ||
3550 | /* l4_per3 -> timer7 */ | |
3551 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = { | |
3552 | .master = &dra7xx_l4_per3_hwmod, | |
3553 | .slave = &dra7xx_timer7_hwmod, | |
3554 | .clk = "l3_iclk_div", | |
3555 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3556 | }; | |
3557 | ||
3558 | /* l4_per3 -> timer8 */ | |
3559 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = { | |
3560 | .master = &dra7xx_l4_per3_hwmod, | |
3561 | .slave = &dra7xx_timer8_hwmod, | |
3562 | .clk = "l3_iclk_div", | |
3563 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3564 | }; | |
3565 | ||
3566 | /* l4_per1 -> timer9 */ | |
3567 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = { | |
3568 | .master = &dra7xx_l4_per1_hwmod, | |
3569 | .slave = &dra7xx_timer9_hwmod, | |
3570 | .clk = "l3_iclk_div", | |
3571 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3572 | }; | |
3573 | ||
3574 | /* l4_per1 -> timer10 */ | |
3575 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = { | |
3576 | .master = &dra7xx_l4_per1_hwmod, | |
3577 | .slave = &dra7xx_timer10_hwmod, | |
3578 | .clk = "l3_iclk_div", | |
3579 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3580 | }; | |
3581 | ||
3582 | /* l4_per1 -> timer11 */ | |
3583 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = { | |
3584 | .master = &dra7xx_l4_per1_hwmod, | |
3585 | .slave = &dra7xx_timer11_hwmod, | |
3586 | .clk = "l3_iclk_div", | |
3587 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3588 | }; | |
3589 | ||
22d20cb4 SA |
3590 | /* l4_wkup -> timer12 */ |
3591 | static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = { | |
3592 | .master = &dra7xx_l4_wkup_hwmod, | |
3593 | .slave = &dra7xx_timer12_hwmod, | |
3594 | .clk = "wkupaon_iclk_mux", | |
3595 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3596 | }; | |
3597 | ||
1ac964f4 SA |
3598 | /* l4_per3 -> timer13 */ |
3599 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = { | |
3600 | .master = &dra7xx_l4_per3_hwmod, | |
3601 | .slave = &dra7xx_timer13_hwmod, | |
3602 | .clk = "l3_iclk_div", | |
3603 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3604 | }; | |
3605 | ||
3606 | /* l4_per3 -> timer14 */ | |
3607 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = { | |
3608 | .master = &dra7xx_l4_per3_hwmod, | |
3609 | .slave = &dra7xx_timer14_hwmod, | |
3610 | .clk = "l3_iclk_div", | |
3611 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3612 | }; | |
3613 | ||
3614 | /* l4_per3 -> timer15 */ | |
3615 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = { | |
3616 | .master = &dra7xx_l4_per3_hwmod, | |
3617 | .slave = &dra7xx_timer15_hwmod, | |
3618 | .clk = "l3_iclk_div", | |
3619 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3620 | }; | |
3621 | ||
3622 | /* l4_per3 -> timer16 */ | |
3623 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = { | |
3624 | .master = &dra7xx_l4_per3_hwmod, | |
3625 | .slave = &dra7xx_timer16_hwmod, | |
3626 | .clk = "l3_iclk_div", | |
3627 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3628 | }; | |
3629 | ||
90020c7b A |
3630 | /* l4_per1 -> uart1 */ |
3631 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = { | |
3632 | .master = &dra7xx_l4_per1_hwmod, | |
3633 | .slave = &dra7xx_uart1_hwmod, | |
3634 | .clk = "l3_iclk_div", | |
3635 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3636 | }; | |
3637 | ||
3638 | /* l4_per1 -> uart2 */ | |
3639 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = { | |
3640 | .master = &dra7xx_l4_per1_hwmod, | |
3641 | .slave = &dra7xx_uart2_hwmod, | |
3642 | .clk = "l3_iclk_div", | |
3643 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3644 | }; | |
3645 | ||
3646 | /* l4_per1 -> uart3 */ | |
3647 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = { | |
3648 | .master = &dra7xx_l4_per1_hwmod, | |
3649 | .slave = &dra7xx_uart3_hwmod, | |
3650 | .clk = "l3_iclk_div", | |
3651 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3652 | }; | |
3653 | ||
3654 | /* l4_per1 -> uart4 */ | |
3655 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = { | |
3656 | .master = &dra7xx_l4_per1_hwmod, | |
3657 | .slave = &dra7xx_uart4_hwmod, | |
3658 | .clk = "l3_iclk_div", | |
3659 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3660 | }; | |
3661 | ||
3662 | /* l4_per1 -> uart5 */ | |
3663 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = { | |
3664 | .master = &dra7xx_l4_per1_hwmod, | |
3665 | .slave = &dra7xx_uart5_hwmod, | |
3666 | .clk = "l3_iclk_div", | |
3667 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3668 | }; | |
3669 | ||
3670 | /* l4_per1 -> uart6 */ | |
3671 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = { | |
3672 | .master = &dra7xx_l4_per1_hwmod, | |
3673 | .slave = &dra7xx_uart6_hwmod, | |
3674 | .clk = "l3_iclk_div", | |
3675 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3676 | }; | |
3677 | ||
33acc9ff A |
3678 | /* l4_per2 -> uart7 */ |
3679 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = { | |
3680 | .master = &dra7xx_l4_per2_hwmod, | |
3681 | .slave = &dra7xx_uart7_hwmod, | |
3682 | .clk = "l3_iclk_div", | |
3683 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3684 | }; | |
3685 | ||
3686 | /* l4_per2 -> uart8 */ | |
3687 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = { | |
3688 | .master = &dra7xx_l4_per2_hwmod, | |
3689 | .slave = &dra7xx_uart8_hwmod, | |
3690 | .clk = "l3_iclk_div", | |
3691 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3692 | }; | |
3693 | ||
3694 | /* l4_per2 -> uart9 */ | |
3695 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = { | |
3696 | .master = &dra7xx_l4_per2_hwmod, | |
3697 | .slave = &dra7xx_uart9_hwmod, | |
3698 | .clk = "l3_iclk_div", | |
3699 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3700 | }; | |
3701 | ||
3702 | /* l4_wkup -> uart10 */ | |
3703 | static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = { | |
3704 | .master = &dra7xx_l4_wkup_hwmod, | |
3705 | .slave = &dra7xx_uart10_hwmod, | |
3706 | .clk = "wkupaon_iclk_mux", | |
3707 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3708 | }; | |
3709 | ||
90020c7b A |
3710 | /* l4_per3 -> usb_otg_ss1 */ |
3711 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = { | |
3712 | .master = &dra7xx_l4_per3_hwmod, | |
3713 | .slave = &dra7xx_usb_otg_ss1_hwmod, | |
3714 | .clk = "dpll_core_h13x2_ck", | |
3715 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3716 | }; | |
3717 | ||
3718 | /* l4_per3 -> usb_otg_ss2 */ | |
3719 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = { | |
3720 | .master = &dra7xx_l4_per3_hwmod, | |
3721 | .slave = &dra7xx_usb_otg_ss2_hwmod, | |
3722 | .clk = "dpll_core_h13x2_ck", | |
3723 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3724 | }; | |
3725 | ||
3726 | /* l4_per3 -> usb_otg_ss3 */ | |
3727 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = { | |
3728 | .master = &dra7xx_l4_per3_hwmod, | |
3729 | .slave = &dra7xx_usb_otg_ss3_hwmod, | |
3730 | .clk = "dpll_core_h13x2_ck", | |
3731 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3732 | }; | |
3733 | ||
3734 | /* l4_per3 -> usb_otg_ss4 */ | |
3735 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = { | |
3736 | .master = &dra7xx_l4_per3_hwmod, | |
3737 | .slave = &dra7xx_usb_otg_ss4_hwmod, | |
3738 | .clk = "dpll_core_h13x2_ck", | |
3739 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3740 | }; | |
3741 | ||
3742 | /* l3_main_1 -> vcp1 */ | |
3743 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = { | |
3744 | .master = &dra7xx_l3_main_1_hwmod, | |
3745 | .slave = &dra7xx_vcp1_hwmod, | |
3746 | .clk = "l3_iclk_div", | |
3747 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3748 | }; | |
3749 | ||
3750 | /* l4_per2 -> vcp1 */ | |
3751 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = { | |
3752 | .master = &dra7xx_l4_per2_hwmod, | |
3753 | .slave = &dra7xx_vcp1_hwmod, | |
3754 | .clk = "l3_iclk_div", | |
3755 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3756 | }; | |
3757 | ||
3758 | /* l3_main_1 -> vcp2 */ | |
3759 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = { | |
3760 | .master = &dra7xx_l3_main_1_hwmod, | |
3761 | .slave = &dra7xx_vcp2_hwmod, | |
3762 | .clk = "l3_iclk_div", | |
3763 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3764 | }; | |
3765 | ||
3766 | /* l4_per2 -> vcp2 */ | |
3767 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = { | |
3768 | .master = &dra7xx_l4_per2_hwmod, | |
3769 | .slave = &dra7xx_vcp2_hwmod, | |
3770 | .clk = "l3_iclk_div", | |
3771 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3772 | }; | |
3773 | ||
3774 | /* l4_wkup -> wd_timer2 */ | |
3775 | static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = { | |
3776 | .master = &dra7xx_l4_wkup_hwmod, | |
3777 | .slave = &dra7xx_wd_timer2_hwmod, | |
3778 | .clk = "wkupaon_iclk_mux", | |
3779 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3780 | }; | |
3781 | ||
b05ff3c3 V |
3782 | /* l4_per2 -> epwmss0 */ |
3783 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = { | |
3784 | .master = &dra7xx_l4_per2_hwmod, | |
3785 | .slave = &dra7xx_epwmss0_hwmod, | |
3786 | .clk = "l4_root_clk_div", | |
3787 | .user = OCP_USER_MPU, | |
3788 | }; | |
3789 | ||
3790 | /* l4_per2 -> epwmss1 */ | |
3791 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = { | |
3792 | .master = &dra7xx_l4_per2_hwmod, | |
3793 | .slave = &dra7xx_epwmss1_hwmod, | |
3794 | .clk = "l4_root_clk_div", | |
3795 | .user = OCP_USER_MPU, | |
3796 | }; | |
3797 | ||
3798 | /* l4_per2 -> epwmss2 */ | |
3799 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = { | |
3800 | .master = &dra7xx_l4_per2_hwmod, | |
3801 | .slave = &dra7xx_epwmss2_hwmod, | |
3802 | .clk = "l4_root_clk_div", | |
3803 | .user = OCP_USER_MPU, | |
3804 | }; | |
3805 | ||
90020c7b | 3806 | static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { |
42121688 | 3807 | &dra7xx_l3_main_1__dmm, |
90020c7b A |
3808 | &dra7xx_l3_main_2__l3_instr, |
3809 | &dra7xx_l4_cfg__l3_main_1, | |
3810 | &dra7xx_mpu__l3_main_1, | |
3811 | &dra7xx_l3_main_1__l3_main_2, | |
3812 | &dra7xx_l4_cfg__l3_main_2, | |
3813 | &dra7xx_l3_main_1__l4_cfg, | |
3814 | &dra7xx_l3_main_1__l4_per1, | |
3815 | &dra7xx_l3_main_1__l4_per2, | |
3816 | &dra7xx_l3_main_1__l4_per3, | |
3817 | &dra7xx_l3_main_1__l4_wkup, | |
3818 | &dra7xx_l4_per2__atl, | |
3819 | &dra7xx_l3_main_1__bb2d, | |
3820 | &dra7xx_l4_wkup__counter_32k, | |
3821 | &dra7xx_l4_wkup__ctrl_module_wkup, | |
3822 | &dra7xx_l4_wkup__dcan1, | |
3823 | &dra7xx_l4_per2__dcan2, | |
077c42f7 | 3824 | &dra7xx_l4_per2__cpgmac0, |
9ad4d9a3 PU |
3825 | &dra7xx_l4_per2__mcasp1, |
3826 | &dra7xx_l3_main_1__mcasp1, | |
3827 | &dra7xx_l4_per2__mcasp2, | |
3828 | &dra7xx_l3_main_1__mcasp2, | |
469689a4 PU |
3829 | &dra7xx_l4_per2__mcasp3, |
3830 | &dra7xx_l3_main_1__mcasp3, | |
9ad4d9a3 PU |
3831 | &dra7xx_l4_per2__mcasp4, |
3832 | &dra7xx_l4_per2__mcasp5, | |
3833 | &dra7xx_l4_per2__mcasp6, | |
3834 | &dra7xx_l4_per2__mcasp7, | |
3835 | &dra7xx_l4_per2__mcasp8, | |
077c42f7 | 3836 | &dra7xx_gmac__mdio, |
90020c7b | 3837 | &dra7xx_l4_cfg__dma_system, |
34b4182c PU |
3838 | &dra7xx_l3_main_1__tpcc, |
3839 | &dra7xx_l3_main_1__tptc0, | |
3840 | &dra7xx_l3_main_1__tptc1, | |
90020c7b A |
3841 | &dra7xx_l3_main_1__dss, |
3842 | &dra7xx_l3_main_1__dispc, | |
3843 | &dra7xx_l3_main_1__hdmi, | |
3844 | &dra7xx_l4_per1__elm, | |
3845 | &dra7xx_l4_wkup__gpio1, | |
3846 | &dra7xx_l4_per1__gpio2, | |
3847 | &dra7xx_l4_per1__gpio3, | |
3848 | &dra7xx_l4_per1__gpio4, | |
3849 | &dra7xx_l4_per1__gpio5, | |
3850 | &dra7xx_l4_per1__gpio6, | |
3851 | &dra7xx_l4_per1__gpio7, | |
3852 | &dra7xx_l4_per1__gpio8, | |
3853 | &dra7xx_l3_main_1__gpmc, | |
3854 | &dra7xx_l4_per1__hdq1w, | |
3855 | &dra7xx_l4_per1__i2c1, | |
3856 | &dra7xx_l4_per1__i2c2, | |
3857 | &dra7xx_l4_per1__i2c3, | |
3858 | &dra7xx_l4_per1__i2c4, | |
3859 | &dra7xx_l4_per1__i2c5, | |
067395d4 SA |
3860 | &dra7xx_l4_cfg__mailbox1, |
3861 | &dra7xx_l4_per3__mailbox2, | |
3862 | &dra7xx_l4_per3__mailbox3, | |
3863 | &dra7xx_l4_per3__mailbox4, | |
3864 | &dra7xx_l4_per3__mailbox5, | |
3865 | &dra7xx_l4_per3__mailbox6, | |
3866 | &dra7xx_l4_per3__mailbox7, | |
3867 | &dra7xx_l4_per3__mailbox8, | |
3868 | &dra7xx_l4_per3__mailbox9, | |
3869 | &dra7xx_l4_per3__mailbox10, | |
3870 | &dra7xx_l4_per3__mailbox11, | |
3871 | &dra7xx_l4_per3__mailbox12, | |
3872 | &dra7xx_l4_per3__mailbox13, | |
90020c7b A |
3873 | &dra7xx_l4_per1__mcspi1, |
3874 | &dra7xx_l4_per1__mcspi2, | |
3875 | &dra7xx_l4_per1__mcspi3, | |
3876 | &dra7xx_l4_per1__mcspi4, | |
3877 | &dra7xx_l4_per1__mmc1, | |
3878 | &dra7xx_l4_per1__mmc2, | |
3879 | &dra7xx_l4_per1__mmc3, | |
3880 | &dra7xx_l4_per1__mmc4, | |
3881 | &dra7xx_l4_cfg__mpu, | |
3882 | &dra7xx_l4_cfg__ocp2scp1, | |
df0d0f11 | 3883 | &dra7xx_l4_cfg__ocp2scp3, |
0717103e KVA |
3884 | &dra7xx_l3_main_1__pciess1, |
3885 | &dra7xx_l4_cfg__pciess1, | |
3886 | &dra7xx_l3_main_1__pciess2, | |
3887 | &dra7xx_l4_cfg__pciess2, | |
90020c7b | 3888 | &dra7xx_l3_main_1__qspi, |
c913c8a1 | 3889 | &dra7xx_l4_per3__rtcss, |
90020c7b A |
3890 | &dra7xx_l4_cfg__sata, |
3891 | &dra7xx_l4_cfg__smartreflex_core, | |
3892 | &dra7xx_l4_cfg__smartreflex_mpu, | |
3893 | &dra7xx_l4_cfg__spinlock, | |
3894 | &dra7xx_l4_wkup__timer1, | |
3895 | &dra7xx_l4_per1__timer2, | |
3896 | &dra7xx_l4_per1__timer3, | |
3897 | &dra7xx_l4_per1__timer4, | |
3898 | &dra7xx_l4_per3__timer5, | |
3899 | &dra7xx_l4_per3__timer6, | |
3900 | &dra7xx_l4_per3__timer7, | |
3901 | &dra7xx_l4_per3__timer8, | |
3902 | &dra7xx_l4_per1__timer9, | |
3903 | &dra7xx_l4_per1__timer10, | |
3904 | &dra7xx_l4_per1__timer11, | |
1ac964f4 SA |
3905 | &dra7xx_l4_per3__timer13, |
3906 | &dra7xx_l4_per3__timer14, | |
3907 | &dra7xx_l4_per3__timer15, | |
3908 | &dra7xx_l4_per3__timer16, | |
90020c7b A |
3909 | &dra7xx_l4_per1__uart1, |
3910 | &dra7xx_l4_per1__uart2, | |
3911 | &dra7xx_l4_per1__uart3, | |
3912 | &dra7xx_l4_per1__uart4, | |
3913 | &dra7xx_l4_per1__uart5, | |
3914 | &dra7xx_l4_per1__uart6, | |
33acc9ff A |
3915 | &dra7xx_l4_per2__uart7, |
3916 | &dra7xx_l4_per2__uart8, | |
3917 | &dra7xx_l4_per2__uart9, | |
3918 | &dra7xx_l4_wkup__uart10, | |
90020c7b A |
3919 | &dra7xx_l4_per3__usb_otg_ss1, |
3920 | &dra7xx_l4_per3__usb_otg_ss2, | |
3921 | &dra7xx_l4_per3__usb_otg_ss3, | |
90020c7b A |
3922 | &dra7xx_l3_main_1__vcp1, |
3923 | &dra7xx_l4_per2__vcp1, | |
3924 | &dra7xx_l3_main_1__vcp2, | |
3925 | &dra7xx_l4_per2__vcp2, | |
3926 | &dra7xx_l4_wkup__wd_timer2, | |
b05ff3c3 V |
3927 | &dra7xx_l4_per2__epwmss0, |
3928 | &dra7xx_l4_per2__epwmss1, | |
3929 | &dra7xx_l4_per2__epwmss2, | |
90020c7b A |
3930 | NULL, |
3931 | }; | |
3932 | ||
22d20cb4 SA |
3933 | /* GP-only hwmod links */ |
3934 | static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = { | |
3935 | &dra7xx_l4_wkup__timer12, | |
3936 | NULL, | |
3937 | }; | |
3938 | ||
3939 | /* SoC variant specific hwmod links */ | |
f7f7a29b RN |
3940 | static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = { |
3941 | &dra7xx_l4_per3__usb_otg_ss4, | |
3942 | NULL, | |
3943 | }; | |
3944 | ||
3945 | static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = { | |
3946 | NULL, | |
3947 | }; | |
3948 | ||
90020c7b A |
3949 | int __init dra7xx_hwmod_init(void) |
3950 | { | |
f7f7a29b RN |
3951 | int ret; |
3952 | ||
90020c7b | 3953 | omap_hwmod_init(); |
f7f7a29b RN |
3954 | ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs); |
3955 | ||
3956 | if (!ret && soc_is_dra74x()) | |
22d20cb4 | 3957 | ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs); |
f7f7a29b | 3958 | else if (!ret && soc_is_dra72x()) |
22d20cb4 SA |
3959 | ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs); |
3960 | ||
3961 | if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP) | |
3962 | ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs); | |
f7f7a29b RN |
3963 | |
3964 | return ret; | |
90020c7b | 3965 | } |