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90020c7b A |
1 | /* |
2 | * Hardware modules present on the DRA7xx chips | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com | |
5 | * | |
6 | * Paul Walmsley | |
7 | * Benoit Cousson | |
8 | * | |
9 | * This file is automatically generated from the OMAP hardware databases. | |
10 | * We respectfully ask that any modifications to this file be coordinated | |
11 | * with the public linux-omap@vger.kernel.org mailing list and the | |
12 | * authors above to ensure that the autogeneration scripts are kept | |
13 | * up-to-date with the file contents. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
19 | ||
20 | #include <linux/io.h> | |
21 | #include <linux/platform_data/gpio-omap.h> | |
55143438 | 22 | #include <linux/platform_data/hsmmc-omap.h> |
90020c7b A |
23 | #include <linux/power/smartreflex.h> |
24 | #include <linux/i2c-omap.h> | |
25 | ||
26 | #include <linux/omap-dma.h> | |
27 | #include <linux/platform_data/spi-omap2-mcspi.h> | |
28 | #include <linux/platform_data/asoc-ti-mcbsp.h> | |
29 | #include <plat/dmtimer.h> | |
30 | ||
31 | #include "omap_hwmod.h" | |
32 | #include "omap_hwmod_common_data.h" | |
33 | #include "cm1_7xx.h" | |
34 | #include "cm2_7xx.h" | |
35 | #include "prm7xx.h" | |
36 | #include "i2c.h" | |
90020c7b | 37 | #include "wd_timer.h" |
f7f7a29b | 38 | #include "soc.h" |
90020c7b A |
39 | |
40 | /* Base offset for all DRA7XX interrupts external to MPUSS */ | |
41 | #define DRA7XX_IRQ_GIC_START 32 | |
42 | ||
43 | /* Base offset for all DRA7XX dma requests */ | |
44 | #define DRA7XX_DMA_REQ_START 1 | |
45 | ||
46 | ||
47 | /* | |
48 | * IP blocks | |
49 | */ | |
50 | ||
51 | /* | |
52 | * 'l3' class | |
53 | * instance(s): l3_instr, l3_main_1, l3_main_2 | |
54 | */ | |
55 | static struct omap_hwmod_class dra7xx_l3_hwmod_class = { | |
56 | .name = "l3", | |
57 | }; | |
58 | ||
59 | /* l3_instr */ | |
60 | static struct omap_hwmod dra7xx_l3_instr_hwmod = { | |
61 | .name = "l3_instr", | |
62 | .class = &dra7xx_l3_hwmod_class, | |
63 | .clkdm_name = "l3instr_clkdm", | |
64 | .prcm = { | |
65 | .omap4 = { | |
66 | .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, | |
67 | .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, | |
68 | .modulemode = MODULEMODE_HWCTRL, | |
69 | }, | |
70 | }, | |
71 | }; | |
72 | ||
73 | /* l3_main_1 */ | |
74 | static struct omap_hwmod dra7xx_l3_main_1_hwmod = { | |
75 | .name = "l3_main_1", | |
76 | .class = &dra7xx_l3_hwmod_class, | |
77 | .clkdm_name = "l3main1_clkdm", | |
78 | .prcm = { | |
79 | .omap4 = { | |
80 | .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET, | |
81 | .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET, | |
82 | }, | |
83 | }, | |
84 | }; | |
85 | ||
86 | /* l3_main_2 */ | |
87 | static struct omap_hwmod dra7xx_l3_main_2_hwmod = { | |
88 | .name = "l3_main_2", | |
89 | .class = &dra7xx_l3_hwmod_class, | |
90 | .clkdm_name = "l3instr_clkdm", | |
91 | .prcm = { | |
92 | .omap4 = { | |
93 | .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET, | |
94 | .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET, | |
95 | .modulemode = MODULEMODE_HWCTRL, | |
96 | }, | |
97 | }, | |
98 | }; | |
99 | ||
100 | /* | |
101 | * 'l4' class | |
102 | * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup | |
103 | */ | |
104 | static struct omap_hwmod_class dra7xx_l4_hwmod_class = { | |
105 | .name = "l4", | |
106 | }; | |
107 | ||
108 | /* l4_cfg */ | |
109 | static struct omap_hwmod dra7xx_l4_cfg_hwmod = { | |
110 | .name = "l4_cfg", | |
111 | .class = &dra7xx_l4_hwmod_class, | |
112 | .clkdm_name = "l4cfg_clkdm", | |
113 | .prcm = { | |
114 | .omap4 = { | |
115 | .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, | |
116 | .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, | |
117 | }, | |
118 | }, | |
119 | }; | |
120 | ||
121 | /* l4_per1 */ | |
122 | static struct omap_hwmod dra7xx_l4_per1_hwmod = { | |
123 | .name = "l4_per1", | |
124 | .class = &dra7xx_l4_hwmod_class, | |
125 | .clkdm_name = "l4per_clkdm", | |
126 | .prcm = { | |
127 | .omap4 = { | |
128 | .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET, | |
129 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
130 | }, | |
131 | }, | |
132 | }; | |
133 | ||
134 | /* l4_per2 */ | |
135 | static struct omap_hwmod dra7xx_l4_per2_hwmod = { | |
136 | .name = "l4_per2", | |
137 | .class = &dra7xx_l4_hwmod_class, | |
138 | .clkdm_name = "l4per2_clkdm", | |
139 | .prcm = { | |
140 | .omap4 = { | |
141 | .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET, | |
142 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
143 | }, | |
144 | }, | |
145 | }; | |
146 | ||
147 | /* l4_per3 */ | |
148 | static struct omap_hwmod dra7xx_l4_per3_hwmod = { | |
149 | .name = "l4_per3", | |
150 | .class = &dra7xx_l4_hwmod_class, | |
151 | .clkdm_name = "l4per3_clkdm", | |
152 | .prcm = { | |
153 | .omap4 = { | |
154 | .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET, | |
155 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
156 | }, | |
157 | }, | |
158 | }; | |
159 | ||
160 | /* l4_wkup */ | |
161 | static struct omap_hwmod dra7xx_l4_wkup_hwmod = { | |
162 | .name = "l4_wkup", | |
163 | .class = &dra7xx_l4_hwmod_class, | |
164 | .clkdm_name = "wkupaon_clkdm", | |
165 | .prcm = { | |
166 | .omap4 = { | |
167 | .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET, | |
168 | .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET, | |
169 | }, | |
170 | }, | |
171 | }; | |
172 | ||
173 | /* | |
174 | * 'atl' class | |
175 | * | |
176 | */ | |
177 | ||
178 | static struct omap_hwmod_class dra7xx_atl_hwmod_class = { | |
179 | .name = "atl", | |
180 | }; | |
181 | ||
182 | /* atl */ | |
183 | static struct omap_hwmod dra7xx_atl_hwmod = { | |
184 | .name = "atl", | |
185 | .class = &dra7xx_atl_hwmod_class, | |
186 | .clkdm_name = "atl_clkdm", | |
187 | .main_clk = "atl_gfclk_mux", | |
188 | .prcm = { | |
189 | .omap4 = { | |
190 | .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET, | |
191 | .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET, | |
192 | .modulemode = MODULEMODE_SWCTRL, | |
193 | }, | |
194 | }, | |
195 | }; | |
196 | ||
197 | /* | |
198 | * 'bb2d' class | |
199 | * | |
200 | */ | |
201 | ||
202 | static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = { | |
203 | .name = "bb2d", | |
204 | }; | |
205 | ||
206 | /* bb2d */ | |
207 | static struct omap_hwmod dra7xx_bb2d_hwmod = { | |
208 | .name = "bb2d", | |
209 | .class = &dra7xx_bb2d_hwmod_class, | |
210 | .clkdm_name = "dss_clkdm", | |
211 | .main_clk = "dpll_core_h24x2_ck", | |
212 | .prcm = { | |
213 | .omap4 = { | |
214 | .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET, | |
215 | .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET, | |
216 | .modulemode = MODULEMODE_SWCTRL, | |
217 | }, | |
218 | }, | |
219 | }; | |
220 | ||
221 | /* | |
222 | * 'counter' class | |
223 | * | |
224 | */ | |
225 | ||
226 | static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = { | |
227 | .rev_offs = 0x0000, | |
228 | .sysc_offs = 0x0010, | |
229 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
230 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
231 | SIDLE_SMART_WKUP), | |
232 | .sysc_fields = &omap_hwmod_sysc_type1, | |
233 | }; | |
234 | ||
235 | static struct omap_hwmod_class dra7xx_counter_hwmod_class = { | |
236 | .name = "counter", | |
237 | .sysc = &dra7xx_counter_sysc, | |
238 | }; | |
239 | ||
240 | /* counter_32k */ | |
241 | static struct omap_hwmod dra7xx_counter_32k_hwmod = { | |
242 | .name = "counter_32k", | |
243 | .class = &dra7xx_counter_hwmod_class, | |
244 | .clkdm_name = "wkupaon_clkdm", | |
245 | .flags = HWMOD_SWSUP_SIDLE, | |
246 | .main_clk = "wkupaon_iclk_mux", | |
247 | .prcm = { | |
248 | .omap4 = { | |
249 | .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET, | |
250 | .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET, | |
251 | }, | |
252 | }, | |
253 | }; | |
254 | ||
255 | /* | |
256 | * 'ctrl_module' class | |
257 | * | |
258 | */ | |
259 | ||
260 | static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = { | |
261 | .name = "ctrl_module", | |
262 | }; | |
263 | ||
264 | /* ctrl_module_wkup */ | |
265 | static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = { | |
266 | .name = "ctrl_module_wkup", | |
267 | .class = &dra7xx_ctrl_module_hwmod_class, | |
268 | .clkdm_name = "wkupaon_clkdm", | |
269 | .prcm = { | |
270 | .omap4 = { | |
271 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
272 | }, | |
273 | }, | |
274 | }; | |
275 | ||
077c42f7 M |
276 | /* |
277 | * 'gmac' class | |
278 | * cpsw/gmac sub system | |
279 | */ | |
280 | static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = { | |
281 | .rev_offs = 0x0, | |
282 | .sysc_offs = 0x8, | |
283 | .syss_offs = 0x4, | |
284 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | | |
285 | SYSS_HAS_RESET_STATUS), | |
286 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | | |
287 | MSTANDBY_NO), | |
288 | .sysc_fields = &omap_hwmod_sysc_type3, | |
289 | }; | |
290 | ||
291 | static struct omap_hwmod_class dra7xx_gmac_hwmod_class = { | |
292 | .name = "gmac", | |
293 | .sysc = &dra7xx_gmac_sysc, | |
294 | }; | |
295 | ||
296 | static struct omap_hwmod dra7xx_gmac_hwmod = { | |
297 | .name = "gmac", | |
298 | .class = &dra7xx_gmac_hwmod_class, | |
299 | .clkdm_name = "gmac_clkdm", | |
300 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), | |
301 | .main_clk = "dpll_gmac_ck", | |
302 | .mpu_rt_idx = 1, | |
303 | .prcm = { | |
304 | .omap4 = { | |
305 | .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET, | |
306 | .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET, | |
307 | .modulemode = MODULEMODE_SWCTRL, | |
308 | }, | |
309 | }, | |
310 | }; | |
311 | ||
312 | /* | |
313 | * 'mdio' class | |
314 | */ | |
315 | static struct omap_hwmod_class dra7xx_mdio_hwmod_class = { | |
316 | .name = "davinci_mdio", | |
317 | }; | |
318 | ||
319 | static struct omap_hwmod dra7xx_mdio_hwmod = { | |
320 | .name = "davinci_mdio", | |
321 | .class = &dra7xx_mdio_hwmod_class, | |
322 | .clkdm_name = "gmac_clkdm", | |
323 | .main_clk = "dpll_gmac_ck", | |
324 | }; | |
325 | ||
90020c7b A |
326 | /* |
327 | * 'dcan' class | |
328 | * | |
329 | */ | |
330 | ||
331 | static struct omap_hwmod_class dra7xx_dcan_hwmod_class = { | |
332 | .name = "dcan", | |
333 | }; | |
334 | ||
335 | /* dcan1 */ | |
336 | static struct omap_hwmod dra7xx_dcan1_hwmod = { | |
337 | .name = "dcan1", | |
338 | .class = &dra7xx_dcan_hwmod_class, | |
339 | .clkdm_name = "wkupaon_clkdm", | |
340 | .main_clk = "dcan1_sys_clk_mux", | |
341 | .prcm = { | |
342 | .omap4 = { | |
343 | .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET, | |
344 | .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET, | |
345 | .modulemode = MODULEMODE_SWCTRL, | |
346 | }, | |
347 | }, | |
348 | }; | |
349 | ||
350 | /* dcan2 */ | |
351 | static struct omap_hwmod dra7xx_dcan2_hwmod = { | |
352 | .name = "dcan2", | |
353 | .class = &dra7xx_dcan_hwmod_class, | |
354 | .clkdm_name = "l4per2_clkdm", | |
355 | .main_clk = "sys_clkin1", | |
356 | .prcm = { | |
357 | .omap4 = { | |
358 | .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET, | |
359 | .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET, | |
360 | .modulemode = MODULEMODE_SWCTRL, | |
361 | }, | |
362 | }, | |
363 | }; | |
364 | ||
365 | /* | |
366 | * 'dma' class | |
367 | * | |
368 | */ | |
369 | ||
370 | static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = { | |
371 | .rev_offs = 0x0000, | |
372 | .sysc_offs = 0x002c, | |
373 | .syss_offs = 0x0028, | |
374 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
375 | SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
376 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
377 | SYSS_HAS_RESET_STATUS), | |
378 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
379 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
380 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
381 | .sysc_fields = &omap_hwmod_sysc_type1, | |
382 | }; | |
383 | ||
384 | static struct omap_hwmod_class dra7xx_dma_hwmod_class = { | |
385 | .name = "dma", | |
386 | .sysc = &dra7xx_dma_sysc, | |
387 | }; | |
388 | ||
389 | /* dma dev_attr */ | |
390 | static struct omap_dma_dev_attr dma_dev_attr = { | |
391 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
392 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
393 | .lch_count = 32, | |
394 | }; | |
395 | ||
396 | /* dma_system */ | |
90020c7b A |
397 | static struct omap_hwmod dra7xx_dma_system_hwmod = { |
398 | .name = "dma_system", | |
399 | .class = &dra7xx_dma_hwmod_class, | |
400 | .clkdm_name = "dma_clkdm", | |
90020c7b A |
401 | .main_clk = "l3_iclk_div", |
402 | .prcm = { | |
403 | .omap4 = { | |
404 | .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET, | |
405 | .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET, | |
406 | }, | |
407 | }, | |
408 | .dev_attr = &dma_dev_attr, | |
409 | }; | |
410 | ||
411 | /* | |
412 | * 'dss' class | |
413 | * | |
414 | */ | |
415 | ||
416 | static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = { | |
417 | .rev_offs = 0x0000, | |
418 | .syss_offs = 0x0014, | |
419 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
420 | }; | |
421 | ||
422 | static struct omap_hwmod_class dra7xx_dss_hwmod_class = { | |
423 | .name = "dss", | |
424 | .sysc = &dra7xx_dss_sysc, | |
425 | .reset = omap_dss_reset, | |
426 | }; | |
427 | ||
428 | /* dss */ | |
429 | static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = { | |
430 | { .dma_req = 75 + DRA7XX_DMA_REQ_START }, | |
431 | { .dma_req = -1 } | |
432 | }; | |
433 | ||
434 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |
435 | { .role = "dss_clk", .clk = "dss_dss_clk" }, | |
436 | { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" }, | |
437 | { .role = "32khz_clk", .clk = "dss_32khz_clk" }, | |
438 | { .role = "video2_clk", .clk = "dss_video2_clk" }, | |
439 | { .role = "video1_clk", .clk = "dss_video1_clk" }, | |
440 | { .role = "hdmi_clk", .clk = "dss_hdmi_clk" }, | |
441 | }; | |
442 | ||
443 | static struct omap_hwmod dra7xx_dss_hwmod = { | |
444 | .name = "dss_core", | |
445 | .class = &dra7xx_dss_hwmod_class, | |
446 | .clkdm_name = "dss_clkdm", | |
447 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
448 | .sdma_reqs = dra7xx_dss_sdma_reqs, | |
449 | .main_clk = "dss_dss_clk", | |
450 | .prcm = { | |
451 | .omap4 = { | |
452 | .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET, | |
453 | .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET, | |
454 | .modulemode = MODULEMODE_SWCTRL, | |
455 | }, | |
456 | }, | |
457 | .opt_clks = dss_opt_clks, | |
458 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
459 | }; | |
460 | ||
461 | /* | |
462 | * 'dispc' class | |
463 | * display controller | |
464 | */ | |
465 | ||
466 | static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = { | |
467 | .rev_offs = 0x0000, | |
468 | .sysc_offs = 0x0010, | |
469 | .syss_offs = 0x0014, | |
470 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
471 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | | |
472 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
473 | SYSS_HAS_RESET_STATUS), | |
474 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
475 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
476 | .sysc_fields = &omap_hwmod_sysc_type1, | |
477 | }; | |
478 | ||
479 | static struct omap_hwmod_class dra7xx_dispc_hwmod_class = { | |
480 | .name = "dispc", | |
481 | .sysc = &dra7xx_dispc_sysc, | |
482 | }; | |
483 | ||
484 | /* dss_dispc */ | |
485 | /* dss_dispc dev_attr */ | |
486 | static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = { | |
487 | .has_framedonetv_irq = 1, | |
488 | .manager_count = 4, | |
489 | }; | |
490 | ||
491 | static struct omap_hwmod dra7xx_dss_dispc_hwmod = { | |
492 | .name = "dss_dispc", | |
493 | .class = &dra7xx_dispc_hwmod_class, | |
494 | .clkdm_name = "dss_clkdm", | |
495 | .main_clk = "dss_dss_clk", | |
496 | .prcm = { | |
497 | .omap4 = { | |
498 | .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET, | |
499 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
500 | }, | |
501 | }, | |
502 | .dev_attr = &dss_dispc_dev_attr, | |
503 | }; | |
504 | ||
505 | /* | |
506 | * 'hdmi' class | |
507 | * hdmi controller | |
508 | */ | |
509 | ||
510 | static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = { | |
511 | .rev_offs = 0x0000, | |
512 | .sysc_offs = 0x0010, | |
513 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
514 | SYSC_HAS_SOFTRESET), | |
515 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
516 | SIDLE_SMART_WKUP), | |
517 | .sysc_fields = &omap_hwmod_sysc_type2, | |
518 | }; | |
519 | ||
520 | static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = { | |
521 | .name = "hdmi", | |
522 | .sysc = &dra7xx_hdmi_sysc, | |
523 | }; | |
524 | ||
525 | /* dss_hdmi */ | |
526 | ||
527 | static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { | |
528 | { .role = "sys_clk", .clk = "dss_hdmi_clk" }, | |
529 | }; | |
530 | ||
531 | static struct omap_hwmod dra7xx_dss_hdmi_hwmod = { | |
532 | .name = "dss_hdmi", | |
533 | .class = &dra7xx_hdmi_hwmod_class, | |
534 | .clkdm_name = "dss_clkdm", | |
535 | .main_clk = "dss_48mhz_clk", | |
536 | .prcm = { | |
537 | .omap4 = { | |
538 | .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET, | |
539 | .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, | |
540 | }, | |
541 | }, | |
542 | .opt_clks = dss_hdmi_opt_clks, | |
543 | .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), | |
544 | }; | |
545 | ||
546 | /* | |
547 | * 'elm' class | |
548 | * | |
549 | */ | |
550 | ||
551 | static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = { | |
552 | .rev_offs = 0x0000, | |
553 | .sysc_offs = 0x0010, | |
554 | .syss_offs = 0x0014, | |
555 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
556 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
557 | SYSS_HAS_RESET_STATUS), | |
558 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
559 | SIDLE_SMART_WKUP), | |
560 | .sysc_fields = &omap_hwmod_sysc_type1, | |
561 | }; | |
562 | ||
563 | static struct omap_hwmod_class dra7xx_elm_hwmod_class = { | |
564 | .name = "elm", | |
565 | .sysc = &dra7xx_elm_sysc, | |
566 | }; | |
567 | ||
568 | /* elm */ | |
569 | ||
570 | static struct omap_hwmod dra7xx_elm_hwmod = { | |
571 | .name = "elm", | |
572 | .class = &dra7xx_elm_hwmod_class, | |
573 | .clkdm_name = "l4per_clkdm", | |
574 | .main_clk = "l3_iclk_div", | |
575 | .prcm = { | |
576 | .omap4 = { | |
577 | .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET, | |
578 | .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET, | |
579 | }, | |
580 | }, | |
581 | }; | |
582 | ||
583 | /* | |
584 | * 'gpio' class | |
585 | * | |
586 | */ | |
587 | ||
588 | static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = { | |
589 | .rev_offs = 0x0000, | |
590 | .sysc_offs = 0x0010, | |
591 | .syss_offs = 0x0114, | |
592 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
593 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
594 | SYSS_HAS_RESET_STATUS), | |
595 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
596 | SIDLE_SMART_WKUP), | |
597 | .sysc_fields = &omap_hwmod_sysc_type1, | |
598 | }; | |
599 | ||
600 | static struct omap_hwmod_class dra7xx_gpio_hwmod_class = { | |
601 | .name = "gpio", | |
602 | .sysc = &dra7xx_gpio_sysc, | |
603 | .rev = 2, | |
604 | }; | |
605 | ||
606 | /* gpio dev_attr */ | |
607 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
608 | .bank_width = 32, | |
609 | .dbck_flag = true, | |
610 | }; | |
611 | ||
612 | /* gpio1 */ | |
613 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | |
614 | { .role = "dbclk", .clk = "gpio1_dbclk" }, | |
615 | }; | |
616 | ||
617 | static struct omap_hwmod dra7xx_gpio1_hwmod = { | |
618 | .name = "gpio1", | |
619 | .class = &dra7xx_gpio_hwmod_class, | |
620 | .clkdm_name = "wkupaon_clkdm", | |
621 | .main_clk = "wkupaon_iclk_mux", | |
622 | .prcm = { | |
623 | .omap4 = { | |
624 | .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET, | |
625 | .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET, | |
626 | .modulemode = MODULEMODE_HWCTRL, | |
627 | }, | |
628 | }, | |
629 | .opt_clks = gpio1_opt_clks, | |
630 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
631 | .dev_attr = &gpio_dev_attr, | |
632 | }; | |
633 | ||
634 | /* gpio2 */ | |
635 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | |
636 | { .role = "dbclk", .clk = "gpio2_dbclk" }, | |
637 | }; | |
638 | ||
639 | static struct omap_hwmod dra7xx_gpio2_hwmod = { | |
640 | .name = "gpio2", | |
641 | .class = &dra7xx_gpio_hwmod_class, | |
642 | .clkdm_name = "l4per_clkdm", | |
643 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
644 | .main_clk = "l3_iclk_div", | |
645 | .prcm = { | |
646 | .omap4 = { | |
647 | .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET, | |
648 | .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET, | |
649 | .modulemode = MODULEMODE_HWCTRL, | |
650 | }, | |
651 | }, | |
652 | .opt_clks = gpio2_opt_clks, | |
653 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
654 | .dev_attr = &gpio_dev_attr, | |
655 | }; | |
656 | ||
657 | /* gpio3 */ | |
658 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { | |
659 | { .role = "dbclk", .clk = "gpio3_dbclk" }, | |
660 | }; | |
661 | ||
662 | static struct omap_hwmod dra7xx_gpio3_hwmod = { | |
663 | .name = "gpio3", | |
664 | .class = &dra7xx_gpio_hwmod_class, | |
665 | .clkdm_name = "l4per_clkdm", | |
666 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
667 | .main_clk = "l3_iclk_div", | |
668 | .prcm = { | |
669 | .omap4 = { | |
670 | .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET, | |
671 | .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET, | |
672 | .modulemode = MODULEMODE_HWCTRL, | |
673 | }, | |
674 | }, | |
675 | .opt_clks = gpio3_opt_clks, | |
676 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
677 | .dev_attr = &gpio_dev_attr, | |
678 | }; | |
679 | ||
680 | /* gpio4 */ | |
681 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { | |
682 | { .role = "dbclk", .clk = "gpio4_dbclk" }, | |
683 | }; | |
684 | ||
685 | static struct omap_hwmod dra7xx_gpio4_hwmod = { | |
686 | .name = "gpio4", | |
687 | .class = &dra7xx_gpio_hwmod_class, | |
688 | .clkdm_name = "l4per_clkdm", | |
689 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
690 | .main_clk = "l3_iclk_div", | |
691 | .prcm = { | |
692 | .omap4 = { | |
693 | .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET, | |
694 | .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET, | |
695 | .modulemode = MODULEMODE_HWCTRL, | |
696 | }, | |
697 | }, | |
698 | .opt_clks = gpio4_opt_clks, | |
699 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
700 | .dev_attr = &gpio_dev_attr, | |
701 | }; | |
702 | ||
703 | /* gpio5 */ | |
704 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { | |
705 | { .role = "dbclk", .clk = "gpio5_dbclk" }, | |
706 | }; | |
707 | ||
708 | static struct omap_hwmod dra7xx_gpio5_hwmod = { | |
709 | .name = "gpio5", | |
710 | .class = &dra7xx_gpio_hwmod_class, | |
711 | .clkdm_name = "l4per_clkdm", | |
712 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
713 | .main_clk = "l3_iclk_div", | |
714 | .prcm = { | |
715 | .omap4 = { | |
716 | .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET, | |
717 | .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET, | |
718 | .modulemode = MODULEMODE_HWCTRL, | |
719 | }, | |
720 | }, | |
721 | .opt_clks = gpio5_opt_clks, | |
722 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
723 | .dev_attr = &gpio_dev_attr, | |
724 | }; | |
725 | ||
726 | /* gpio6 */ | |
727 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { | |
728 | { .role = "dbclk", .clk = "gpio6_dbclk" }, | |
729 | }; | |
730 | ||
731 | static struct omap_hwmod dra7xx_gpio6_hwmod = { | |
732 | .name = "gpio6", | |
733 | .class = &dra7xx_gpio_hwmod_class, | |
734 | .clkdm_name = "l4per_clkdm", | |
735 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
736 | .main_clk = "l3_iclk_div", | |
737 | .prcm = { | |
738 | .omap4 = { | |
739 | .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET, | |
740 | .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET, | |
741 | .modulemode = MODULEMODE_HWCTRL, | |
742 | }, | |
743 | }, | |
744 | .opt_clks = gpio6_opt_clks, | |
745 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
746 | .dev_attr = &gpio_dev_attr, | |
747 | }; | |
748 | ||
749 | /* gpio7 */ | |
750 | static struct omap_hwmod_opt_clk gpio7_opt_clks[] = { | |
751 | { .role = "dbclk", .clk = "gpio7_dbclk" }, | |
752 | }; | |
753 | ||
754 | static struct omap_hwmod dra7xx_gpio7_hwmod = { | |
755 | .name = "gpio7", | |
756 | .class = &dra7xx_gpio_hwmod_class, | |
757 | .clkdm_name = "l4per_clkdm", | |
758 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
759 | .main_clk = "l3_iclk_div", | |
760 | .prcm = { | |
761 | .omap4 = { | |
762 | .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET, | |
763 | .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET, | |
764 | .modulemode = MODULEMODE_HWCTRL, | |
765 | }, | |
766 | }, | |
767 | .opt_clks = gpio7_opt_clks, | |
768 | .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks), | |
769 | .dev_attr = &gpio_dev_attr, | |
770 | }; | |
771 | ||
772 | /* gpio8 */ | |
773 | static struct omap_hwmod_opt_clk gpio8_opt_clks[] = { | |
774 | { .role = "dbclk", .clk = "gpio8_dbclk" }, | |
775 | }; | |
776 | ||
777 | static struct omap_hwmod dra7xx_gpio8_hwmod = { | |
778 | .name = "gpio8", | |
779 | .class = &dra7xx_gpio_hwmod_class, | |
780 | .clkdm_name = "l4per_clkdm", | |
781 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
782 | .main_clk = "l3_iclk_div", | |
783 | .prcm = { | |
784 | .omap4 = { | |
785 | .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET, | |
786 | .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET, | |
787 | .modulemode = MODULEMODE_HWCTRL, | |
788 | }, | |
789 | }, | |
790 | .opt_clks = gpio8_opt_clks, | |
791 | .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks), | |
792 | .dev_attr = &gpio_dev_attr, | |
793 | }; | |
794 | ||
795 | /* | |
796 | * 'gpmc' class | |
797 | * | |
798 | */ | |
799 | ||
800 | static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = { | |
801 | .rev_offs = 0x0000, | |
802 | .sysc_offs = 0x0010, | |
803 | .syss_offs = 0x0014, | |
804 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
805 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
806 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
807 | SIDLE_SMART_WKUP), | |
808 | .sysc_fields = &omap_hwmod_sysc_type1, | |
809 | }; | |
810 | ||
811 | static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = { | |
812 | .name = "gpmc", | |
813 | .sysc = &dra7xx_gpmc_sysc, | |
814 | }; | |
815 | ||
816 | /* gpmc */ | |
817 | ||
818 | static struct omap_hwmod dra7xx_gpmc_hwmod = { | |
819 | .name = "gpmc", | |
820 | .class = &dra7xx_gpmc_hwmod_class, | |
821 | .clkdm_name = "l3main1_clkdm", | |
556708fe K |
822 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET | |
823 | HWMOD_SWSUP_SIDLE), | |
90020c7b A |
824 | .main_clk = "l3_iclk_div", |
825 | .prcm = { | |
826 | .omap4 = { | |
827 | .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET, | |
828 | .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET, | |
829 | .modulemode = MODULEMODE_HWCTRL, | |
830 | }, | |
831 | }, | |
832 | }; | |
833 | ||
834 | /* | |
835 | * 'hdq1w' class | |
836 | * | |
837 | */ | |
838 | ||
839 | static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = { | |
840 | .rev_offs = 0x0000, | |
841 | .sysc_offs = 0x0014, | |
842 | .syss_offs = 0x0018, | |
843 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET | | |
844 | SYSS_HAS_RESET_STATUS), | |
845 | .sysc_fields = &omap_hwmod_sysc_type1, | |
846 | }; | |
847 | ||
848 | static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = { | |
849 | .name = "hdq1w", | |
850 | .sysc = &dra7xx_hdq1w_sysc, | |
851 | }; | |
852 | ||
853 | /* hdq1w */ | |
854 | ||
855 | static struct omap_hwmod dra7xx_hdq1w_hwmod = { | |
856 | .name = "hdq1w", | |
857 | .class = &dra7xx_hdq1w_hwmod_class, | |
858 | .clkdm_name = "l4per_clkdm", | |
859 | .flags = HWMOD_INIT_NO_RESET, | |
860 | .main_clk = "func_12m_fclk", | |
861 | .prcm = { | |
862 | .omap4 = { | |
863 | .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, | |
864 | .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET, | |
865 | .modulemode = MODULEMODE_SWCTRL, | |
866 | }, | |
867 | }, | |
868 | }; | |
869 | ||
870 | /* | |
871 | * 'i2c' class | |
872 | * | |
873 | */ | |
874 | ||
875 | static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = { | |
876 | .sysc_offs = 0x0010, | |
877 | .syss_offs = 0x0090, | |
878 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
879 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
880 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
881 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
882 | SIDLE_SMART_WKUP), | |
883 | .clockact = CLOCKACT_TEST_ICLK, | |
884 | .sysc_fields = &omap_hwmod_sysc_type1, | |
885 | }; | |
886 | ||
887 | static struct omap_hwmod_class dra7xx_i2c_hwmod_class = { | |
888 | .name = "i2c", | |
889 | .sysc = &dra7xx_i2c_sysc, | |
890 | .reset = &omap_i2c_reset, | |
891 | .rev = OMAP_I2C_IP_VERSION_2, | |
892 | }; | |
893 | ||
894 | /* i2c dev_attr */ | |
895 | static struct omap_i2c_dev_attr i2c_dev_attr = { | |
896 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, | |
897 | }; | |
898 | ||
899 | /* i2c1 */ | |
900 | static struct omap_hwmod dra7xx_i2c1_hwmod = { | |
901 | .name = "i2c1", | |
902 | .class = &dra7xx_i2c_hwmod_class, | |
903 | .clkdm_name = "l4per_clkdm", | |
904 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
905 | .main_clk = "func_96m_fclk", | |
906 | .prcm = { | |
907 | .omap4 = { | |
908 | .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET, | |
909 | .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET, | |
910 | .modulemode = MODULEMODE_SWCTRL, | |
911 | }, | |
912 | }, | |
913 | .dev_attr = &i2c_dev_attr, | |
914 | }; | |
915 | ||
916 | /* i2c2 */ | |
917 | static struct omap_hwmod dra7xx_i2c2_hwmod = { | |
918 | .name = "i2c2", | |
919 | .class = &dra7xx_i2c_hwmod_class, | |
920 | .clkdm_name = "l4per_clkdm", | |
921 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
922 | .main_clk = "func_96m_fclk", | |
923 | .prcm = { | |
924 | .omap4 = { | |
925 | .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET, | |
926 | .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET, | |
927 | .modulemode = MODULEMODE_SWCTRL, | |
928 | }, | |
929 | }, | |
930 | .dev_attr = &i2c_dev_attr, | |
931 | }; | |
932 | ||
933 | /* i2c3 */ | |
934 | static struct omap_hwmod dra7xx_i2c3_hwmod = { | |
935 | .name = "i2c3", | |
936 | .class = &dra7xx_i2c_hwmod_class, | |
937 | .clkdm_name = "l4per_clkdm", | |
938 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
939 | .main_clk = "func_96m_fclk", | |
940 | .prcm = { | |
941 | .omap4 = { | |
942 | .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET, | |
943 | .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET, | |
944 | .modulemode = MODULEMODE_SWCTRL, | |
945 | }, | |
946 | }, | |
947 | .dev_attr = &i2c_dev_attr, | |
948 | }; | |
949 | ||
950 | /* i2c4 */ | |
951 | static struct omap_hwmod dra7xx_i2c4_hwmod = { | |
952 | .name = "i2c4", | |
953 | .class = &dra7xx_i2c_hwmod_class, | |
954 | .clkdm_name = "l4per_clkdm", | |
955 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
956 | .main_clk = "func_96m_fclk", | |
957 | .prcm = { | |
958 | .omap4 = { | |
959 | .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET, | |
960 | .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET, | |
961 | .modulemode = MODULEMODE_SWCTRL, | |
962 | }, | |
963 | }, | |
964 | .dev_attr = &i2c_dev_attr, | |
965 | }; | |
966 | ||
967 | /* i2c5 */ | |
968 | static struct omap_hwmod dra7xx_i2c5_hwmod = { | |
969 | .name = "i2c5", | |
970 | .class = &dra7xx_i2c_hwmod_class, | |
971 | .clkdm_name = "ipu_clkdm", | |
972 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
973 | .main_clk = "func_96m_fclk", | |
974 | .prcm = { | |
975 | .omap4 = { | |
976 | .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET, | |
977 | .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET, | |
978 | .modulemode = MODULEMODE_SWCTRL, | |
979 | }, | |
980 | }, | |
981 | .dev_attr = &i2c_dev_attr, | |
982 | }; | |
983 | ||
067395d4 SA |
984 | /* |
985 | * 'mailbox' class | |
986 | * | |
987 | */ | |
988 | ||
989 | static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = { | |
990 | .rev_offs = 0x0000, | |
991 | .sysc_offs = 0x0010, | |
992 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
993 | SYSC_HAS_SOFTRESET), | |
994 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
995 | .sysc_fields = &omap_hwmod_sysc_type2, | |
996 | }; | |
997 | ||
998 | static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = { | |
999 | .name = "mailbox", | |
1000 | .sysc = &dra7xx_mailbox_sysc, | |
1001 | }; | |
1002 | ||
1003 | /* mailbox1 */ | |
1004 | static struct omap_hwmod dra7xx_mailbox1_hwmod = { | |
1005 | .name = "mailbox1", | |
1006 | .class = &dra7xx_mailbox_hwmod_class, | |
1007 | .clkdm_name = "l4cfg_clkdm", | |
1008 | .prcm = { | |
1009 | .omap4 = { | |
1010 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET, | |
1011 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET, | |
1012 | }, | |
1013 | }, | |
1014 | }; | |
1015 | ||
1016 | /* mailbox2 */ | |
1017 | static struct omap_hwmod dra7xx_mailbox2_hwmod = { | |
1018 | .name = "mailbox2", | |
1019 | .class = &dra7xx_mailbox_hwmod_class, | |
1020 | .clkdm_name = "l4cfg_clkdm", | |
1021 | .prcm = { | |
1022 | .omap4 = { | |
1023 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET, | |
1024 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET, | |
1025 | }, | |
1026 | }, | |
1027 | }; | |
1028 | ||
1029 | /* mailbox3 */ | |
1030 | static struct omap_hwmod dra7xx_mailbox3_hwmod = { | |
1031 | .name = "mailbox3", | |
1032 | .class = &dra7xx_mailbox_hwmod_class, | |
1033 | .clkdm_name = "l4cfg_clkdm", | |
1034 | .prcm = { | |
1035 | .omap4 = { | |
1036 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET, | |
1037 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET, | |
1038 | }, | |
1039 | }, | |
1040 | }; | |
1041 | ||
1042 | /* mailbox4 */ | |
1043 | static struct omap_hwmod dra7xx_mailbox4_hwmod = { | |
1044 | .name = "mailbox4", | |
1045 | .class = &dra7xx_mailbox_hwmod_class, | |
1046 | .clkdm_name = "l4cfg_clkdm", | |
1047 | .prcm = { | |
1048 | .omap4 = { | |
1049 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET, | |
1050 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET, | |
1051 | }, | |
1052 | }, | |
1053 | }; | |
1054 | ||
1055 | /* mailbox5 */ | |
1056 | static struct omap_hwmod dra7xx_mailbox5_hwmod = { | |
1057 | .name = "mailbox5", | |
1058 | .class = &dra7xx_mailbox_hwmod_class, | |
1059 | .clkdm_name = "l4cfg_clkdm", | |
1060 | .prcm = { | |
1061 | .omap4 = { | |
1062 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET, | |
1063 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET, | |
1064 | }, | |
1065 | }, | |
1066 | }; | |
1067 | ||
1068 | /* mailbox6 */ | |
1069 | static struct omap_hwmod dra7xx_mailbox6_hwmod = { | |
1070 | .name = "mailbox6", | |
1071 | .class = &dra7xx_mailbox_hwmod_class, | |
1072 | .clkdm_name = "l4cfg_clkdm", | |
1073 | .prcm = { | |
1074 | .omap4 = { | |
1075 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET, | |
1076 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET, | |
1077 | }, | |
1078 | }, | |
1079 | }; | |
1080 | ||
1081 | /* mailbox7 */ | |
1082 | static struct omap_hwmod dra7xx_mailbox7_hwmod = { | |
1083 | .name = "mailbox7", | |
1084 | .class = &dra7xx_mailbox_hwmod_class, | |
1085 | .clkdm_name = "l4cfg_clkdm", | |
1086 | .prcm = { | |
1087 | .omap4 = { | |
1088 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET, | |
1089 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET, | |
1090 | }, | |
1091 | }, | |
1092 | }; | |
1093 | ||
1094 | /* mailbox8 */ | |
1095 | static struct omap_hwmod dra7xx_mailbox8_hwmod = { | |
1096 | .name = "mailbox8", | |
1097 | .class = &dra7xx_mailbox_hwmod_class, | |
1098 | .clkdm_name = "l4cfg_clkdm", | |
1099 | .prcm = { | |
1100 | .omap4 = { | |
1101 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET, | |
1102 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET, | |
1103 | }, | |
1104 | }, | |
1105 | }; | |
1106 | ||
1107 | /* mailbox9 */ | |
1108 | static struct omap_hwmod dra7xx_mailbox9_hwmod = { | |
1109 | .name = "mailbox9", | |
1110 | .class = &dra7xx_mailbox_hwmod_class, | |
1111 | .clkdm_name = "l4cfg_clkdm", | |
1112 | .prcm = { | |
1113 | .omap4 = { | |
1114 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET, | |
1115 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET, | |
1116 | }, | |
1117 | }, | |
1118 | }; | |
1119 | ||
1120 | /* mailbox10 */ | |
1121 | static struct omap_hwmod dra7xx_mailbox10_hwmod = { | |
1122 | .name = "mailbox10", | |
1123 | .class = &dra7xx_mailbox_hwmod_class, | |
1124 | .clkdm_name = "l4cfg_clkdm", | |
1125 | .prcm = { | |
1126 | .omap4 = { | |
1127 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET, | |
1128 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET, | |
1129 | }, | |
1130 | }, | |
1131 | }; | |
1132 | ||
1133 | /* mailbox11 */ | |
1134 | static struct omap_hwmod dra7xx_mailbox11_hwmod = { | |
1135 | .name = "mailbox11", | |
1136 | .class = &dra7xx_mailbox_hwmod_class, | |
1137 | .clkdm_name = "l4cfg_clkdm", | |
1138 | .prcm = { | |
1139 | .omap4 = { | |
1140 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET, | |
1141 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET, | |
1142 | }, | |
1143 | }, | |
1144 | }; | |
1145 | ||
1146 | /* mailbox12 */ | |
1147 | static struct omap_hwmod dra7xx_mailbox12_hwmod = { | |
1148 | .name = "mailbox12", | |
1149 | .class = &dra7xx_mailbox_hwmod_class, | |
1150 | .clkdm_name = "l4cfg_clkdm", | |
1151 | .prcm = { | |
1152 | .omap4 = { | |
1153 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET, | |
1154 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET, | |
1155 | }, | |
1156 | }, | |
1157 | }; | |
1158 | ||
1159 | /* mailbox13 */ | |
1160 | static struct omap_hwmod dra7xx_mailbox13_hwmod = { | |
1161 | .name = "mailbox13", | |
1162 | .class = &dra7xx_mailbox_hwmod_class, | |
1163 | .clkdm_name = "l4cfg_clkdm", | |
1164 | .prcm = { | |
1165 | .omap4 = { | |
1166 | .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET, | |
1167 | .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET, | |
1168 | }, | |
1169 | }, | |
1170 | }; | |
1171 | ||
90020c7b A |
1172 | /* |
1173 | * 'mcspi' class | |
1174 | * | |
1175 | */ | |
1176 | ||
1177 | static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = { | |
1178 | .rev_offs = 0x0000, | |
1179 | .sysc_offs = 0x0010, | |
1180 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
1181 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1182 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1183 | SIDLE_SMART_WKUP), | |
1184 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1185 | }; | |
1186 | ||
1187 | static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = { | |
1188 | .name = "mcspi", | |
1189 | .sysc = &dra7xx_mcspi_sysc, | |
1190 | .rev = OMAP4_MCSPI_REV, | |
1191 | }; | |
1192 | ||
1193 | /* mcspi1 */ | |
1194 | /* mcspi1 dev_attr */ | |
1195 | static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { | |
1196 | .num_chipselect = 4, | |
1197 | }; | |
1198 | ||
1199 | static struct omap_hwmod dra7xx_mcspi1_hwmod = { | |
1200 | .name = "mcspi1", | |
1201 | .class = &dra7xx_mcspi_hwmod_class, | |
1202 | .clkdm_name = "l4per_clkdm", | |
1203 | .main_clk = "func_48m_fclk", | |
1204 | .prcm = { | |
1205 | .omap4 = { | |
1206 | .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, | |
1207 | .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET, | |
1208 | .modulemode = MODULEMODE_SWCTRL, | |
1209 | }, | |
1210 | }, | |
1211 | .dev_attr = &mcspi1_dev_attr, | |
1212 | }; | |
1213 | ||
1214 | /* mcspi2 */ | |
1215 | /* mcspi2 dev_attr */ | |
1216 | static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { | |
1217 | .num_chipselect = 2, | |
1218 | }; | |
1219 | ||
1220 | static struct omap_hwmod dra7xx_mcspi2_hwmod = { | |
1221 | .name = "mcspi2", | |
1222 | .class = &dra7xx_mcspi_hwmod_class, | |
1223 | .clkdm_name = "l4per_clkdm", | |
1224 | .main_clk = "func_48m_fclk", | |
1225 | .prcm = { | |
1226 | .omap4 = { | |
1227 | .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, | |
1228 | .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET, | |
1229 | .modulemode = MODULEMODE_SWCTRL, | |
1230 | }, | |
1231 | }, | |
1232 | .dev_attr = &mcspi2_dev_attr, | |
1233 | }; | |
1234 | ||
1235 | /* mcspi3 */ | |
1236 | /* mcspi3 dev_attr */ | |
1237 | static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { | |
1238 | .num_chipselect = 2, | |
1239 | }; | |
1240 | ||
1241 | static struct omap_hwmod dra7xx_mcspi3_hwmod = { | |
1242 | .name = "mcspi3", | |
1243 | .class = &dra7xx_mcspi_hwmod_class, | |
1244 | .clkdm_name = "l4per_clkdm", | |
1245 | .main_clk = "func_48m_fclk", | |
1246 | .prcm = { | |
1247 | .omap4 = { | |
1248 | .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, | |
1249 | .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET, | |
1250 | .modulemode = MODULEMODE_SWCTRL, | |
1251 | }, | |
1252 | }, | |
1253 | .dev_attr = &mcspi3_dev_attr, | |
1254 | }; | |
1255 | ||
1256 | /* mcspi4 */ | |
1257 | /* mcspi4 dev_attr */ | |
1258 | static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { | |
1259 | .num_chipselect = 1, | |
1260 | }; | |
1261 | ||
1262 | static struct omap_hwmod dra7xx_mcspi4_hwmod = { | |
1263 | .name = "mcspi4", | |
1264 | .class = &dra7xx_mcspi_hwmod_class, | |
1265 | .clkdm_name = "l4per_clkdm", | |
1266 | .main_clk = "func_48m_fclk", | |
1267 | .prcm = { | |
1268 | .omap4 = { | |
1269 | .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, | |
1270 | .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET, | |
1271 | .modulemode = MODULEMODE_SWCTRL, | |
1272 | }, | |
1273 | }, | |
1274 | .dev_attr = &mcspi4_dev_attr, | |
1275 | }; | |
1276 | ||
1277 | /* | |
1278 | * 'mmc' class | |
1279 | * | |
1280 | */ | |
1281 | ||
1282 | static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = { | |
1283 | .rev_offs = 0x0000, | |
1284 | .sysc_offs = 0x0010, | |
1285 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
1286 | SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1287 | SYSC_HAS_SOFTRESET), | |
1288 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1289 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
1290 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
1291 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1292 | }; | |
1293 | ||
1294 | static struct omap_hwmod_class dra7xx_mmc_hwmod_class = { | |
1295 | .name = "mmc", | |
1296 | .sysc = &dra7xx_mmc_sysc, | |
1297 | }; | |
1298 | ||
1299 | /* mmc1 */ | |
1300 | static struct omap_hwmod_opt_clk mmc1_opt_clks[] = { | |
1301 | { .role = "clk32k", .clk = "mmc1_clk32k" }, | |
1302 | }; | |
1303 | ||
1304 | /* mmc1 dev_attr */ | |
55143438 | 1305 | static struct omap_hsmmc_dev_attr mmc1_dev_attr = { |
90020c7b A |
1306 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, |
1307 | }; | |
1308 | ||
1309 | static struct omap_hwmod dra7xx_mmc1_hwmod = { | |
1310 | .name = "mmc1", | |
1311 | .class = &dra7xx_mmc_hwmod_class, | |
1312 | .clkdm_name = "l3init_clkdm", | |
1313 | .main_clk = "mmc1_fclk_div", | |
1314 | .prcm = { | |
1315 | .omap4 = { | |
1316 | .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET, | |
1317 | .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET, | |
1318 | .modulemode = MODULEMODE_SWCTRL, | |
1319 | }, | |
1320 | }, | |
1321 | .opt_clks = mmc1_opt_clks, | |
1322 | .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks), | |
1323 | .dev_attr = &mmc1_dev_attr, | |
1324 | }; | |
1325 | ||
1326 | /* mmc2 */ | |
1327 | static struct omap_hwmod_opt_clk mmc2_opt_clks[] = { | |
1328 | { .role = "clk32k", .clk = "mmc2_clk32k" }, | |
1329 | }; | |
1330 | ||
1331 | static struct omap_hwmod dra7xx_mmc2_hwmod = { | |
1332 | .name = "mmc2", | |
1333 | .class = &dra7xx_mmc_hwmod_class, | |
1334 | .clkdm_name = "l3init_clkdm", | |
1335 | .main_clk = "mmc2_fclk_div", | |
1336 | .prcm = { | |
1337 | .omap4 = { | |
1338 | .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET, | |
1339 | .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET, | |
1340 | .modulemode = MODULEMODE_SWCTRL, | |
1341 | }, | |
1342 | }, | |
1343 | .opt_clks = mmc2_opt_clks, | |
1344 | .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks), | |
1345 | }; | |
1346 | ||
1347 | /* mmc3 */ | |
1348 | static struct omap_hwmod_opt_clk mmc3_opt_clks[] = { | |
1349 | { .role = "clk32k", .clk = "mmc3_clk32k" }, | |
1350 | }; | |
1351 | ||
1352 | static struct omap_hwmod dra7xx_mmc3_hwmod = { | |
1353 | .name = "mmc3", | |
1354 | .class = &dra7xx_mmc_hwmod_class, | |
1355 | .clkdm_name = "l4per_clkdm", | |
1356 | .main_clk = "mmc3_gfclk_div", | |
1357 | .prcm = { | |
1358 | .omap4 = { | |
1359 | .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET, | |
1360 | .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET, | |
1361 | .modulemode = MODULEMODE_SWCTRL, | |
1362 | }, | |
1363 | }, | |
1364 | .opt_clks = mmc3_opt_clks, | |
1365 | .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks), | |
1366 | }; | |
1367 | ||
1368 | /* mmc4 */ | |
1369 | static struct omap_hwmod_opt_clk mmc4_opt_clks[] = { | |
1370 | { .role = "clk32k", .clk = "mmc4_clk32k" }, | |
1371 | }; | |
1372 | ||
1373 | static struct omap_hwmod dra7xx_mmc4_hwmod = { | |
1374 | .name = "mmc4", | |
1375 | .class = &dra7xx_mmc_hwmod_class, | |
1376 | .clkdm_name = "l4per_clkdm", | |
1377 | .main_clk = "mmc4_gfclk_div", | |
1378 | .prcm = { | |
1379 | .omap4 = { | |
1380 | .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET, | |
1381 | .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET, | |
1382 | .modulemode = MODULEMODE_SWCTRL, | |
1383 | }, | |
1384 | }, | |
1385 | .opt_clks = mmc4_opt_clks, | |
1386 | .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks), | |
1387 | }; | |
1388 | ||
1389 | /* | |
1390 | * 'mpu' class | |
1391 | * | |
1392 | */ | |
1393 | ||
1394 | static struct omap_hwmod_class dra7xx_mpu_hwmod_class = { | |
1395 | .name = "mpu", | |
1396 | }; | |
1397 | ||
1398 | /* mpu */ | |
1399 | static struct omap_hwmod dra7xx_mpu_hwmod = { | |
1400 | .name = "mpu", | |
1401 | .class = &dra7xx_mpu_hwmod_class, | |
1402 | .clkdm_name = "mpu_clkdm", | |
1403 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | |
1404 | .main_clk = "dpll_mpu_m2_ck", | |
1405 | .prcm = { | |
1406 | .omap4 = { | |
1407 | .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET, | |
1408 | .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET, | |
1409 | }, | |
1410 | }, | |
1411 | }; | |
1412 | ||
1413 | /* | |
1414 | * 'ocp2scp' class | |
1415 | * | |
1416 | */ | |
1417 | ||
1418 | static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = { | |
1419 | .rev_offs = 0x0000, | |
1420 | .sysc_offs = 0x0010, | |
1421 | .syss_offs = 0x0014, | |
1422 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
1423 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1424 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1425 | SIDLE_SMART_WKUP), | |
1426 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1427 | }; | |
1428 | ||
1429 | static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = { | |
1430 | .name = "ocp2scp", | |
1431 | .sysc = &dra7xx_ocp2scp_sysc, | |
1432 | }; | |
1433 | ||
1434 | /* ocp2scp1 */ | |
1435 | static struct omap_hwmod dra7xx_ocp2scp1_hwmod = { | |
1436 | .name = "ocp2scp1", | |
1437 | .class = &dra7xx_ocp2scp_hwmod_class, | |
1438 | .clkdm_name = "l3init_clkdm", | |
1439 | .main_clk = "l4_root_clk_div", | |
1440 | .prcm = { | |
1441 | .omap4 = { | |
1442 | .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET, | |
1443 | .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET, | |
1444 | .modulemode = MODULEMODE_HWCTRL, | |
1445 | }, | |
1446 | }, | |
1447 | }; | |
1448 | ||
df0d0f11 RQ |
1449 | /* ocp2scp3 */ |
1450 | static struct omap_hwmod dra7xx_ocp2scp3_hwmod = { | |
1451 | .name = "ocp2scp3", | |
1452 | .class = &dra7xx_ocp2scp_hwmod_class, | |
1453 | .clkdm_name = "l3init_clkdm", | |
1454 | .main_clk = "l4_root_clk_div", | |
1455 | .prcm = { | |
1456 | .omap4 = { | |
1457 | .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET, | |
1458 | .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET, | |
1459 | .modulemode = MODULEMODE_HWCTRL, | |
1460 | }, | |
1461 | }, | |
1462 | }; | |
1463 | ||
8dd3eb71 KVA |
1464 | /* |
1465 | * 'PCIE' class | |
1466 | * | |
1467 | */ | |
1468 | ||
1469 | static struct omap_hwmod_class dra7xx_pcie_hwmod_class = { | |
1470 | .name = "pcie", | |
1471 | }; | |
1472 | ||
1473 | /* pcie1 */ | |
1474 | static struct omap_hwmod dra7xx_pcie1_hwmod = { | |
1475 | .name = "pcie1", | |
1476 | .class = &dra7xx_pcie_hwmod_class, | |
1477 | .clkdm_name = "pcie_clkdm", | |
1478 | .main_clk = "l4_root_clk_div", | |
1479 | .prcm = { | |
1480 | .omap4 = { | |
1481 | .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET, | |
1482 | .modulemode = MODULEMODE_SWCTRL, | |
1483 | }, | |
1484 | }, | |
1485 | }; | |
1486 | ||
1487 | /* pcie2 */ | |
1488 | static struct omap_hwmod dra7xx_pcie2_hwmod = { | |
1489 | .name = "pcie2", | |
1490 | .class = &dra7xx_pcie_hwmod_class, | |
1491 | .clkdm_name = "pcie_clkdm", | |
1492 | .main_clk = "l4_root_clk_div", | |
1493 | .prcm = { | |
1494 | .omap4 = { | |
1495 | .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET, | |
1496 | .modulemode = MODULEMODE_SWCTRL, | |
1497 | }, | |
1498 | }, | |
1499 | }; | |
1500 | ||
70c18ef7 KVA |
1501 | /* |
1502 | * 'PCIE PHY' class | |
1503 | * | |
1504 | */ | |
1505 | ||
1506 | static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = { | |
1507 | .name = "pcie-phy", | |
1508 | }; | |
1509 | ||
1510 | /* pcie1 phy */ | |
1511 | static struct omap_hwmod dra7xx_pcie1_phy_hwmod = { | |
1512 | .name = "pcie1-phy", | |
1513 | .class = &dra7xx_pcie_phy_hwmod_class, | |
1514 | .clkdm_name = "l3init_clkdm", | |
1515 | .main_clk = "l4_root_clk_div", | |
1516 | .prcm = { | |
1517 | .omap4 = { | |
1518 | .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET, | |
1519 | .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET, | |
1520 | .modulemode = MODULEMODE_SWCTRL, | |
1521 | }, | |
1522 | }, | |
1523 | }; | |
1524 | ||
1525 | /* pcie2 phy */ | |
1526 | static struct omap_hwmod dra7xx_pcie2_phy_hwmod = { | |
1527 | .name = "pcie2-phy", | |
1528 | .class = &dra7xx_pcie_phy_hwmod_class, | |
1529 | .clkdm_name = "l3init_clkdm", | |
1530 | .main_clk = "l4_root_clk_div", | |
1531 | .prcm = { | |
1532 | .omap4 = { | |
1533 | .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET, | |
1534 | .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET, | |
1535 | .modulemode = MODULEMODE_SWCTRL, | |
1536 | }, | |
1537 | }, | |
1538 | }; | |
1539 | ||
90020c7b A |
1540 | /* |
1541 | * 'qspi' class | |
1542 | * | |
1543 | */ | |
1544 | ||
1545 | static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = { | |
1546 | .sysc_offs = 0x0010, | |
1547 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
1548 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1549 | SIDLE_SMART_WKUP), | |
1550 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1551 | }; | |
1552 | ||
1553 | static struct omap_hwmod_class dra7xx_qspi_hwmod_class = { | |
1554 | .name = "qspi", | |
1555 | .sysc = &dra7xx_qspi_sysc, | |
1556 | }; | |
1557 | ||
1558 | /* qspi */ | |
1559 | static struct omap_hwmod dra7xx_qspi_hwmod = { | |
1560 | .name = "qspi", | |
1561 | .class = &dra7xx_qspi_hwmod_class, | |
1562 | .clkdm_name = "l4per2_clkdm", | |
1563 | .main_clk = "qspi_gfclk_div", | |
1564 | .prcm = { | |
1565 | .omap4 = { | |
1566 | .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET, | |
1567 | .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET, | |
1568 | .modulemode = MODULEMODE_SWCTRL, | |
1569 | }, | |
1570 | }, | |
1571 | }; | |
1572 | ||
c913c8a1 LV |
1573 | /* |
1574 | * 'rtcss' class | |
1575 | * | |
1576 | */ | |
1577 | static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = { | |
1578 | .sysc_offs = 0x0078, | |
1579 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
1580 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1581 | SIDLE_SMART_WKUP), | |
1582 | .sysc_fields = &omap_hwmod_sysc_type3, | |
1583 | }; | |
1584 | ||
1585 | static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = { | |
1586 | .name = "rtcss", | |
1587 | .sysc = &dra7xx_rtcss_sysc, | |
1588 | }; | |
1589 | ||
1590 | /* rtcss */ | |
1591 | static struct omap_hwmod dra7xx_rtcss_hwmod = { | |
1592 | .name = "rtcss", | |
1593 | .class = &dra7xx_rtcss_hwmod_class, | |
1594 | .clkdm_name = "rtc_clkdm", | |
1595 | .main_clk = "sys_32k_ck", | |
1596 | .prcm = { | |
1597 | .omap4 = { | |
1598 | .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET, | |
1599 | .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET, | |
1600 | .modulemode = MODULEMODE_SWCTRL, | |
1601 | }, | |
1602 | }, | |
1603 | }; | |
1604 | ||
90020c7b A |
1605 | /* |
1606 | * 'sata' class | |
1607 | * | |
1608 | */ | |
1609 | ||
1610 | static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = { | |
1611 | .sysc_offs = 0x0000, | |
1612 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
1613 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1614 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
1615 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
1616 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1617 | }; | |
1618 | ||
1619 | static struct omap_hwmod_class dra7xx_sata_hwmod_class = { | |
1620 | .name = "sata", | |
1621 | .sysc = &dra7xx_sata_sysc, | |
1622 | }; | |
1623 | ||
1624 | /* sata */ | |
90020c7b A |
1625 | |
1626 | static struct omap_hwmod dra7xx_sata_hwmod = { | |
1627 | .name = "sata", | |
1628 | .class = &dra7xx_sata_hwmod_class, | |
1629 | .clkdm_name = "l3init_clkdm", | |
1630 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | |
1631 | .main_clk = "func_48m_fclk", | |
1ea0999e | 1632 | .mpu_rt_idx = 1, |
90020c7b A |
1633 | .prcm = { |
1634 | .omap4 = { | |
1635 | .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET, | |
1636 | .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET, | |
1637 | .modulemode = MODULEMODE_SWCTRL, | |
1638 | }, | |
1639 | }, | |
90020c7b A |
1640 | }; |
1641 | ||
1642 | /* | |
1643 | * 'smartreflex' class | |
1644 | * | |
1645 | */ | |
1646 | ||
1647 | /* The IP is not compliant to type1 / type2 scheme */ | |
1648 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { | |
1649 | .sidle_shift = 24, | |
1650 | .enwkup_shift = 26, | |
1651 | }; | |
1652 | ||
1653 | static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = { | |
1654 | .sysc_offs = 0x0038, | |
1655 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), | |
1656 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1657 | SIDLE_SMART_WKUP), | |
1658 | .sysc_fields = &omap_hwmod_sysc_type_smartreflex, | |
1659 | }; | |
1660 | ||
1661 | static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = { | |
1662 | .name = "smartreflex", | |
1663 | .sysc = &dra7xx_smartreflex_sysc, | |
1664 | .rev = 2, | |
1665 | }; | |
1666 | ||
1667 | /* smartreflex_core */ | |
1668 | /* smartreflex_core dev_attr */ | |
1669 | static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { | |
1670 | .sensor_voltdm_name = "core", | |
1671 | }; | |
1672 | ||
1673 | static struct omap_hwmod dra7xx_smartreflex_core_hwmod = { | |
1674 | .name = "smartreflex_core", | |
1675 | .class = &dra7xx_smartreflex_hwmod_class, | |
1676 | .clkdm_name = "coreaon_clkdm", | |
1677 | .main_clk = "wkupaon_iclk_mux", | |
1678 | .prcm = { | |
1679 | .omap4 = { | |
1680 | .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET, | |
1681 | .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET, | |
1682 | .modulemode = MODULEMODE_SWCTRL, | |
1683 | }, | |
1684 | }, | |
1685 | .dev_attr = &smartreflex_core_dev_attr, | |
1686 | }; | |
1687 | ||
1688 | /* smartreflex_mpu */ | |
1689 | /* smartreflex_mpu dev_attr */ | |
1690 | static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { | |
1691 | .sensor_voltdm_name = "mpu", | |
1692 | }; | |
1693 | ||
1694 | static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = { | |
1695 | .name = "smartreflex_mpu", | |
1696 | .class = &dra7xx_smartreflex_hwmod_class, | |
1697 | .clkdm_name = "coreaon_clkdm", | |
1698 | .main_clk = "wkupaon_iclk_mux", | |
1699 | .prcm = { | |
1700 | .omap4 = { | |
1701 | .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET, | |
1702 | .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET, | |
1703 | .modulemode = MODULEMODE_SWCTRL, | |
1704 | }, | |
1705 | }, | |
1706 | .dev_attr = &smartreflex_mpu_dev_attr, | |
1707 | }; | |
1708 | ||
1709 | /* | |
1710 | * 'spinlock' class | |
1711 | * | |
1712 | */ | |
1713 | ||
1714 | static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = { | |
1715 | .rev_offs = 0x0000, | |
1716 | .sysc_offs = 0x0010, | |
1717 | .syss_offs = 0x0014, | |
c317d0f2 SA |
1718 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
1719 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1720 | SYSS_HAS_RESET_STATUS), | |
1721 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
90020c7b A |
1722 | .sysc_fields = &omap_hwmod_sysc_type1, |
1723 | }; | |
1724 | ||
1725 | static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = { | |
1726 | .name = "spinlock", | |
1727 | .sysc = &dra7xx_spinlock_sysc, | |
1728 | }; | |
1729 | ||
1730 | /* spinlock */ | |
1731 | static struct omap_hwmod dra7xx_spinlock_hwmod = { | |
1732 | .name = "spinlock", | |
1733 | .class = &dra7xx_spinlock_hwmod_class, | |
1734 | .clkdm_name = "l4cfg_clkdm", | |
1735 | .main_clk = "l3_iclk_div", | |
1736 | .prcm = { | |
1737 | .omap4 = { | |
1738 | .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET, | |
1739 | .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET, | |
1740 | }, | |
1741 | }, | |
1742 | }; | |
1743 | ||
1744 | /* | |
1745 | * 'timer' class | |
1746 | * | |
1747 | * This class contains several variants: ['timer_1ms', 'timer_secure', | |
1748 | * 'timer'] | |
1749 | */ | |
1750 | ||
1751 | static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = { | |
1752 | .rev_offs = 0x0000, | |
1753 | .sysc_offs = 0x0010, | |
1754 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
1755 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1756 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1757 | SIDLE_SMART_WKUP), | |
1758 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1759 | }; | |
1760 | ||
1761 | static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = { | |
1762 | .name = "timer", | |
1763 | .sysc = &dra7xx_timer_1ms_sysc, | |
1764 | }; | |
1765 | ||
1766 | static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = { | |
1767 | .rev_offs = 0x0000, | |
1768 | .sysc_offs = 0x0010, | |
1769 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
1770 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1771 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1772 | SIDLE_SMART_WKUP), | |
1773 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1774 | }; | |
1775 | ||
1776 | static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = { | |
1777 | .name = "timer", | |
1778 | .sysc = &dra7xx_timer_secure_sysc, | |
1779 | }; | |
1780 | ||
1781 | static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = { | |
1782 | .rev_offs = 0x0000, | |
1783 | .sysc_offs = 0x0010, | |
1784 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
1785 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1786 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1787 | SIDLE_SMART_WKUP), | |
1788 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1789 | }; | |
1790 | ||
1791 | static struct omap_hwmod_class dra7xx_timer_hwmod_class = { | |
1792 | .name = "timer", | |
1793 | .sysc = &dra7xx_timer_sysc, | |
1794 | }; | |
1795 | ||
1796 | /* timer1 */ | |
1797 | static struct omap_hwmod dra7xx_timer1_hwmod = { | |
1798 | .name = "timer1", | |
1799 | .class = &dra7xx_timer_1ms_hwmod_class, | |
1800 | .clkdm_name = "wkupaon_clkdm", | |
1801 | .main_clk = "timer1_gfclk_mux", | |
1802 | .prcm = { | |
1803 | .omap4 = { | |
1804 | .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET, | |
1805 | .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET, | |
1806 | .modulemode = MODULEMODE_SWCTRL, | |
1807 | }, | |
1808 | }, | |
1809 | }; | |
1810 | ||
1811 | /* timer2 */ | |
1812 | static struct omap_hwmod dra7xx_timer2_hwmod = { | |
1813 | .name = "timer2", | |
1814 | .class = &dra7xx_timer_1ms_hwmod_class, | |
1815 | .clkdm_name = "l4per_clkdm", | |
1816 | .main_clk = "timer2_gfclk_mux", | |
1817 | .prcm = { | |
1818 | .omap4 = { | |
1819 | .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET, | |
1820 | .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET, | |
1821 | .modulemode = MODULEMODE_SWCTRL, | |
1822 | }, | |
1823 | }, | |
1824 | }; | |
1825 | ||
1826 | /* timer3 */ | |
1827 | static struct omap_hwmod dra7xx_timer3_hwmod = { | |
1828 | .name = "timer3", | |
1829 | .class = &dra7xx_timer_hwmod_class, | |
1830 | .clkdm_name = "l4per_clkdm", | |
1831 | .main_clk = "timer3_gfclk_mux", | |
1832 | .prcm = { | |
1833 | .omap4 = { | |
1834 | .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET, | |
1835 | .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET, | |
1836 | .modulemode = MODULEMODE_SWCTRL, | |
1837 | }, | |
1838 | }, | |
1839 | }; | |
1840 | ||
1841 | /* timer4 */ | |
1842 | static struct omap_hwmod dra7xx_timer4_hwmod = { | |
1843 | .name = "timer4", | |
1844 | .class = &dra7xx_timer_secure_hwmod_class, | |
1845 | .clkdm_name = "l4per_clkdm", | |
1846 | .main_clk = "timer4_gfclk_mux", | |
1847 | .prcm = { | |
1848 | .omap4 = { | |
1849 | .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET, | |
1850 | .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET, | |
1851 | .modulemode = MODULEMODE_SWCTRL, | |
1852 | }, | |
1853 | }, | |
1854 | }; | |
1855 | ||
1856 | /* timer5 */ | |
1857 | static struct omap_hwmod dra7xx_timer5_hwmod = { | |
1858 | .name = "timer5", | |
1859 | .class = &dra7xx_timer_hwmod_class, | |
1860 | .clkdm_name = "ipu_clkdm", | |
1861 | .main_clk = "timer5_gfclk_mux", | |
1862 | .prcm = { | |
1863 | .omap4 = { | |
1864 | .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET, | |
1865 | .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET, | |
1866 | .modulemode = MODULEMODE_SWCTRL, | |
1867 | }, | |
1868 | }, | |
1869 | }; | |
1870 | ||
1871 | /* timer6 */ | |
1872 | static struct omap_hwmod dra7xx_timer6_hwmod = { | |
1873 | .name = "timer6", | |
1874 | .class = &dra7xx_timer_hwmod_class, | |
1875 | .clkdm_name = "ipu_clkdm", | |
1876 | .main_clk = "timer6_gfclk_mux", | |
1877 | .prcm = { | |
1878 | .omap4 = { | |
1879 | .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET, | |
1880 | .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET, | |
1881 | .modulemode = MODULEMODE_SWCTRL, | |
1882 | }, | |
1883 | }, | |
1884 | }; | |
1885 | ||
1886 | /* timer7 */ | |
1887 | static struct omap_hwmod dra7xx_timer7_hwmod = { | |
1888 | .name = "timer7", | |
1889 | .class = &dra7xx_timer_hwmod_class, | |
1890 | .clkdm_name = "ipu_clkdm", | |
1891 | .main_clk = "timer7_gfclk_mux", | |
1892 | .prcm = { | |
1893 | .omap4 = { | |
1894 | .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET, | |
1895 | .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET, | |
1896 | .modulemode = MODULEMODE_SWCTRL, | |
1897 | }, | |
1898 | }, | |
1899 | }; | |
1900 | ||
1901 | /* timer8 */ | |
1902 | static struct omap_hwmod dra7xx_timer8_hwmod = { | |
1903 | .name = "timer8", | |
1904 | .class = &dra7xx_timer_hwmod_class, | |
1905 | .clkdm_name = "ipu_clkdm", | |
1906 | .main_clk = "timer8_gfclk_mux", | |
1907 | .prcm = { | |
1908 | .omap4 = { | |
1909 | .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET, | |
1910 | .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET, | |
1911 | .modulemode = MODULEMODE_SWCTRL, | |
1912 | }, | |
1913 | }, | |
1914 | }; | |
1915 | ||
1916 | /* timer9 */ | |
1917 | static struct omap_hwmod dra7xx_timer9_hwmod = { | |
1918 | .name = "timer9", | |
1919 | .class = &dra7xx_timer_hwmod_class, | |
1920 | .clkdm_name = "l4per_clkdm", | |
1921 | .main_clk = "timer9_gfclk_mux", | |
1922 | .prcm = { | |
1923 | .omap4 = { | |
1924 | .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET, | |
1925 | .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET, | |
1926 | .modulemode = MODULEMODE_SWCTRL, | |
1927 | }, | |
1928 | }, | |
1929 | }; | |
1930 | ||
1931 | /* timer10 */ | |
1932 | static struct omap_hwmod dra7xx_timer10_hwmod = { | |
1933 | .name = "timer10", | |
1934 | .class = &dra7xx_timer_1ms_hwmod_class, | |
1935 | .clkdm_name = "l4per_clkdm", | |
1936 | .main_clk = "timer10_gfclk_mux", | |
1937 | .prcm = { | |
1938 | .omap4 = { | |
1939 | .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET, | |
1940 | .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET, | |
1941 | .modulemode = MODULEMODE_SWCTRL, | |
1942 | }, | |
1943 | }, | |
1944 | }; | |
1945 | ||
1946 | /* timer11 */ | |
1947 | static struct omap_hwmod dra7xx_timer11_hwmod = { | |
1948 | .name = "timer11", | |
1949 | .class = &dra7xx_timer_hwmod_class, | |
1950 | .clkdm_name = "l4per_clkdm", | |
1951 | .main_clk = "timer11_gfclk_mux", | |
1952 | .prcm = { | |
1953 | .omap4 = { | |
1954 | .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET, | |
1955 | .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET, | |
1956 | .modulemode = MODULEMODE_SWCTRL, | |
1957 | }, | |
1958 | }, | |
1959 | }; | |
1960 | ||
1ac964f4 SA |
1961 | /* timer13 */ |
1962 | static struct omap_hwmod dra7xx_timer13_hwmod = { | |
1963 | .name = "timer13", | |
1964 | .class = &dra7xx_timer_hwmod_class, | |
1965 | .clkdm_name = "l4per3_clkdm", | |
1966 | .main_clk = "timer13_gfclk_mux", | |
1967 | .prcm = { | |
1968 | .omap4 = { | |
1969 | .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET, | |
1970 | .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET, | |
1971 | .modulemode = MODULEMODE_SWCTRL, | |
1972 | }, | |
1973 | }, | |
1974 | }; | |
1975 | ||
1976 | /* timer14 */ | |
1977 | static struct omap_hwmod dra7xx_timer14_hwmod = { | |
1978 | .name = "timer14", | |
1979 | .class = &dra7xx_timer_hwmod_class, | |
1980 | .clkdm_name = "l4per3_clkdm", | |
1981 | .main_clk = "timer14_gfclk_mux", | |
1982 | .prcm = { | |
1983 | .omap4 = { | |
1984 | .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET, | |
1985 | .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET, | |
1986 | .modulemode = MODULEMODE_SWCTRL, | |
1987 | }, | |
1988 | }, | |
1989 | }; | |
1990 | ||
1991 | /* timer15 */ | |
1992 | static struct omap_hwmod dra7xx_timer15_hwmod = { | |
1993 | .name = "timer15", | |
1994 | .class = &dra7xx_timer_hwmod_class, | |
1995 | .clkdm_name = "l4per3_clkdm", | |
1996 | .main_clk = "timer15_gfclk_mux", | |
1997 | .prcm = { | |
1998 | .omap4 = { | |
1999 | .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET, | |
2000 | .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET, | |
2001 | .modulemode = MODULEMODE_SWCTRL, | |
2002 | }, | |
2003 | }, | |
2004 | }; | |
2005 | ||
2006 | /* timer16 */ | |
2007 | static struct omap_hwmod dra7xx_timer16_hwmod = { | |
2008 | .name = "timer16", | |
2009 | .class = &dra7xx_timer_hwmod_class, | |
2010 | .clkdm_name = "l4per3_clkdm", | |
2011 | .main_clk = "timer16_gfclk_mux", | |
2012 | .prcm = { | |
2013 | .omap4 = { | |
2014 | .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET, | |
2015 | .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET, | |
2016 | .modulemode = MODULEMODE_SWCTRL, | |
2017 | }, | |
2018 | }, | |
2019 | }; | |
2020 | ||
90020c7b A |
2021 | /* |
2022 | * 'uart' class | |
2023 | * | |
2024 | */ | |
2025 | ||
2026 | static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = { | |
2027 | .rev_offs = 0x0050, | |
2028 | .sysc_offs = 0x0054, | |
2029 | .syss_offs = 0x0058, | |
2030 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
2031 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
2032 | SYSS_HAS_RESET_STATUS), | |
2033 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2034 | SIDLE_SMART_WKUP), | |
2035 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2036 | }; | |
2037 | ||
2038 | static struct omap_hwmod_class dra7xx_uart_hwmod_class = { | |
2039 | .name = "uart", | |
2040 | .sysc = &dra7xx_uart_sysc, | |
2041 | }; | |
2042 | ||
2043 | /* uart1 */ | |
2044 | static struct omap_hwmod dra7xx_uart1_hwmod = { | |
2045 | .name = "uart1", | |
2046 | .class = &dra7xx_uart_hwmod_class, | |
2047 | .clkdm_name = "l4per_clkdm", | |
2048 | .main_clk = "uart1_gfclk_mux", | |
38958c15 | 2049 | .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS, |
90020c7b A |
2050 | .prcm = { |
2051 | .omap4 = { | |
2052 | .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET, | |
2053 | .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET, | |
2054 | .modulemode = MODULEMODE_SWCTRL, | |
2055 | }, | |
2056 | }, | |
2057 | }; | |
2058 | ||
2059 | /* uart2 */ | |
2060 | static struct omap_hwmod dra7xx_uart2_hwmod = { | |
2061 | .name = "uart2", | |
2062 | .class = &dra7xx_uart_hwmod_class, | |
2063 | .clkdm_name = "l4per_clkdm", | |
2064 | .main_clk = "uart2_gfclk_mux", | |
2065 | .flags = HWMOD_SWSUP_SIDLE_ACT, | |
2066 | .prcm = { | |
2067 | .omap4 = { | |
2068 | .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET, | |
2069 | .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET, | |
2070 | .modulemode = MODULEMODE_SWCTRL, | |
2071 | }, | |
2072 | }, | |
2073 | }; | |
2074 | ||
2075 | /* uart3 */ | |
2076 | static struct omap_hwmod dra7xx_uart3_hwmod = { | |
2077 | .name = "uart3", | |
2078 | .class = &dra7xx_uart_hwmod_class, | |
2079 | .clkdm_name = "l4per_clkdm", | |
2080 | .main_clk = "uart3_gfclk_mux", | |
1c7e36bf | 2081 | .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS, |
90020c7b A |
2082 | .prcm = { |
2083 | .omap4 = { | |
2084 | .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET, | |
2085 | .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET, | |
2086 | .modulemode = MODULEMODE_SWCTRL, | |
2087 | }, | |
2088 | }, | |
2089 | }; | |
2090 | ||
2091 | /* uart4 */ | |
2092 | static struct omap_hwmod dra7xx_uart4_hwmod = { | |
2093 | .name = "uart4", | |
2094 | .class = &dra7xx_uart_hwmod_class, | |
2095 | .clkdm_name = "l4per_clkdm", | |
2096 | .main_clk = "uart4_gfclk_mux", | |
2097 | .flags = HWMOD_SWSUP_SIDLE_ACT, | |
2098 | .prcm = { | |
2099 | .omap4 = { | |
2100 | .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET, | |
2101 | .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET, | |
2102 | .modulemode = MODULEMODE_SWCTRL, | |
2103 | }, | |
2104 | }, | |
2105 | }; | |
2106 | ||
2107 | /* uart5 */ | |
2108 | static struct omap_hwmod dra7xx_uart5_hwmod = { | |
2109 | .name = "uart5", | |
2110 | .class = &dra7xx_uart_hwmod_class, | |
2111 | .clkdm_name = "l4per_clkdm", | |
2112 | .main_clk = "uart5_gfclk_mux", | |
2113 | .flags = HWMOD_SWSUP_SIDLE_ACT, | |
2114 | .prcm = { | |
2115 | .omap4 = { | |
2116 | .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET, | |
2117 | .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET, | |
2118 | .modulemode = MODULEMODE_SWCTRL, | |
2119 | }, | |
2120 | }, | |
2121 | }; | |
2122 | ||
2123 | /* uart6 */ | |
2124 | static struct omap_hwmod dra7xx_uart6_hwmod = { | |
2125 | .name = "uart6", | |
2126 | .class = &dra7xx_uart_hwmod_class, | |
2127 | .clkdm_name = "ipu_clkdm", | |
2128 | .main_clk = "uart6_gfclk_mux", | |
2129 | .flags = HWMOD_SWSUP_SIDLE_ACT, | |
2130 | .prcm = { | |
2131 | .omap4 = { | |
2132 | .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET, | |
2133 | .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET, | |
2134 | .modulemode = MODULEMODE_SWCTRL, | |
2135 | }, | |
2136 | }, | |
2137 | }; | |
2138 | ||
33acc9ff A |
2139 | /* uart7 */ |
2140 | static struct omap_hwmod dra7xx_uart7_hwmod = { | |
2141 | .name = "uart7", | |
2142 | .class = &dra7xx_uart_hwmod_class, | |
2143 | .clkdm_name = "l4per2_clkdm", | |
2144 | .main_clk = "uart7_gfclk_mux", | |
2145 | .flags = HWMOD_SWSUP_SIDLE_ACT, | |
2146 | .prcm = { | |
2147 | .omap4 = { | |
2148 | .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET, | |
2149 | .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET, | |
2150 | .modulemode = MODULEMODE_SWCTRL, | |
2151 | }, | |
2152 | }, | |
2153 | }; | |
2154 | ||
2155 | /* uart8 */ | |
2156 | static struct omap_hwmod dra7xx_uart8_hwmod = { | |
2157 | .name = "uart8", | |
2158 | .class = &dra7xx_uart_hwmod_class, | |
2159 | .clkdm_name = "l4per2_clkdm", | |
2160 | .main_clk = "uart8_gfclk_mux", | |
2161 | .flags = HWMOD_SWSUP_SIDLE_ACT, | |
2162 | .prcm = { | |
2163 | .omap4 = { | |
2164 | .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET, | |
2165 | .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET, | |
2166 | .modulemode = MODULEMODE_SWCTRL, | |
2167 | }, | |
2168 | }, | |
2169 | }; | |
2170 | ||
2171 | /* uart9 */ | |
2172 | static struct omap_hwmod dra7xx_uart9_hwmod = { | |
2173 | .name = "uart9", | |
2174 | .class = &dra7xx_uart_hwmod_class, | |
2175 | .clkdm_name = "l4per2_clkdm", | |
2176 | .main_clk = "uart9_gfclk_mux", | |
2177 | .flags = HWMOD_SWSUP_SIDLE_ACT, | |
2178 | .prcm = { | |
2179 | .omap4 = { | |
2180 | .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET, | |
2181 | .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET, | |
2182 | .modulemode = MODULEMODE_SWCTRL, | |
2183 | }, | |
2184 | }, | |
2185 | }; | |
2186 | ||
2187 | /* uart10 */ | |
2188 | static struct omap_hwmod dra7xx_uart10_hwmod = { | |
2189 | .name = "uart10", | |
2190 | .class = &dra7xx_uart_hwmod_class, | |
2191 | .clkdm_name = "wkupaon_clkdm", | |
2192 | .main_clk = "uart10_gfclk_mux", | |
2193 | .flags = HWMOD_SWSUP_SIDLE_ACT, | |
2194 | .prcm = { | |
2195 | .omap4 = { | |
2196 | .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET, | |
2197 | .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET, | |
2198 | .modulemode = MODULEMODE_SWCTRL, | |
2199 | }, | |
2200 | }, | |
2201 | }; | |
2202 | ||
90020c7b A |
2203 | /* |
2204 | * 'usb_otg_ss' class | |
2205 | * | |
2206 | */ | |
2207 | ||
d904b38d RQ |
2208 | static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = { |
2209 | .rev_offs = 0x0000, | |
2210 | .sysc_offs = 0x0010, | |
2211 | .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE | | |
2212 | SYSC_HAS_SIDLEMODE), | |
2213 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2214 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
2215 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
2216 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2217 | }; | |
2218 | ||
90020c7b A |
2219 | static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = { |
2220 | .name = "usb_otg_ss", | |
d904b38d | 2221 | .sysc = &dra7xx_usb_otg_ss_sysc, |
90020c7b A |
2222 | }; |
2223 | ||
2224 | /* usb_otg_ss1 */ | |
2225 | static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = { | |
2226 | { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" }, | |
2227 | }; | |
2228 | ||
2229 | static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = { | |
2230 | .name = "usb_otg_ss1", | |
2231 | .class = &dra7xx_usb_otg_ss_hwmod_class, | |
2232 | .clkdm_name = "l3init_clkdm", | |
2233 | .main_clk = "dpll_core_h13x2_ck", | |
2234 | .prcm = { | |
2235 | .omap4 = { | |
2236 | .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET, | |
2237 | .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET, | |
2238 | .modulemode = MODULEMODE_HWCTRL, | |
2239 | }, | |
2240 | }, | |
2241 | .opt_clks = usb_otg_ss1_opt_clks, | |
2242 | .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks), | |
2243 | }; | |
2244 | ||
2245 | /* usb_otg_ss2 */ | |
2246 | static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = { | |
2247 | { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" }, | |
2248 | }; | |
2249 | ||
2250 | static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = { | |
2251 | .name = "usb_otg_ss2", | |
2252 | .class = &dra7xx_usb_otg_ss_hwmod_class, | |
2253 | .clkdm_name = "l3init_clkdm", | |
2254 | .main_clk = "dpll_core_h13x2_ck", | |
2255 | .prcm = { | |
2256 | .omap4 = { | |
2257 | .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET, | |
2258 | .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET, | |
2259 | .modulemode = MODULEMODE_HWCTRL, | |
2260 | }, | |
2261 | }, | |
2262 | .opt_clks = usb_otg_ss2_opt_clks, | |
2263 | .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks), | |
2264 | }; | |
2265 | ||
2266 | /* usb_otg_ss3 */ | |
2267 | static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = { | |
2268 | .name = "usb_otg_ss3", | |
2269 | .class = &dra7xx_usb_otg_ss_hwmod_class, | |
2270 | .clkdm_name = "l3init_clkdm", | |
2271 | .main_clk = "dpll_core_h13x2_ck", | |
2272 | .prcm = { | |
2273 | .omap4 = { | |
2274 | .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET, | |
2275 | .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET, | |
2276 | .modulemode = MODULEMODE_HWCTRL, | |
2277 | }, | |
2278 | }, | |
2279 | }; | |
2280 | ||
2281 | /* usb_otg_ss4 */ | |
2282 | static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = { | |
2283 | .name = "usb_otg_ss4", | |
2284 | .class = &dra7xx_usb_otg_ss_hwmod_class, | |
2285 | .clkdm_name = "l3init_clkdm", | |
2286 | .main_clk = "dpll_core_h13x2_ck", | |
2287 | .prcm = { | |
2288 | .omap4 = { | |
2289 | .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET, | |
2290 | .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET, | |
2291 | .modulemode = MODULEMODE_HWCTRL, | |
2292 | }, | |
2293 | }, | |
2294 | }; | |
2295 | ||
2296 | /* | |
2297 | * 'vcp' class | |
2298 | * | |
2299 | */ | |
2300 | ||
2301 | static struct omap_hwmod_class dra7xx_vcp_hwmod_class = { | |
2302 | .name = "vcp", | |
2303 | }; | |
2304 | ||
2305 | /* vcp1 */ | |
2306 | static struct omap_hwmod dra7xx_vcp1_hwmod = { | |
2307 | .name = "vcp1", | |
2308 | .class = &dra7xx_vcp_hwmod_class, | |
2309 | .clkdm_name = "l3main1_clkdm", | |
2310 | .main_clk = "l3_iclk_div", | |
2311 | .prcm = { | |
2312 | .omap4 = { | |
2313 | .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET, | |
2314 | .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET, | |
2315 | }, | |
2316 | }, | |
2317 | }; | |
2318 | ||
2319 | /* vcp2 */ | |
2320 | static struct omap_hwmod dra7xx_vcp2_hwmod = { | |
2321 | .name = "vcp2", | |
2322 | .class = &dra7xx_vcp_hwmod_class, | |
2323 | .clkdm_name = "l3main1_clkdm", | |
2324 | .main_clk = "l3_iclk_div", | |
2325 | .prcm = { | |
2326 | .omap4 = { | |
2327 | .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET, | |
2328 | .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET, | |
2329 | }, | |
2330 | }, | |
2331 | }; | |
2332 | ||
2333 | /* | |
2334 | * 'wd_timer' class | |
2335 | * | |
2336 | */ | |
2337 | ||
2338 | static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = { | |
2339 | .rev_offs = 0x0000, | |
2340 | .sysc_offs = 0x0010, | |
2341 | .syss_offs = 0x0014, | |
2342 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
2343 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
2344 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2345 | SIDLE_SMART_WKUP), | |
2346 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2347 | }; | |
2348 | ||
2349 | static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = { | |
2350 | .name = "wd_timer", | |
2351 | .sysc = &dra7xx_wd_timer_sysc, | |
2352 | .pre_shutdown = &omap2_wd_timer_disable, | |
2353 | .reset = &omap2_wd_timer_reset, | |
2354 | }; | |
2355 | ||
2356 | /* wd_timer2 */ | |
2357 | static struct omap_hwmod dra7xx_wd_timer2_hwmod = { | |
2358 | .name = "wd_timer2", | |
2359 | .class = &dra7xx_wd_timer_hwmod_class, | |
2360 | .clkdm_name = "wkupaon_clkdm", | |
2361 | .main_clk = "sys_32k_ck", | |
2362 | .prcm = { | |
2363 | .omap4 = { | |
2364 | .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET, | |
2365 | .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET, | |
2366 | .modulemode = MODULEMODE_SWCTRL, | |
2367 | }, | |
2368 | }, | |
2369 | }; | |
2370 | ||
2371 | ||
2372 | /* | |
2373 | * Interfaces | |
2374 | */ | |
2375 | ||
2376 | /* l3_main_2 -> l3_instr */ | |
2377 | static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = { | |
2378 | .master = &dra7xx_l3_main_2_hwmod, | |
2379 | .slave = &dra7xx_l3_instr_hwmod, | |
2380 | .clk = "l3_iclk_div", | |
2381 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2382 | }; | |
2383 | ||
2384 | /* l4_cfg -> l3_main_1 */ | |
2385 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = { | |
2386 | .master = &dra7xx_l4_cfg_hwmod, | |
2387 | .slave = &dra7xx_l3_main_1_hwmod, | |
2388 | .clk = "l3_iclk_div", | |
2389 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2390 | }; | |
2391 | ||
2392 | /* mpu -> l3_main_1 */ | |
2393 | static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = { | |
2394 | .master = &dra7xx_mpu_hwmod, | |
2395 | .slave = &dra7xx_l3_main_1_hwmod, | |
2396 | .clk = "l3_iclk_div", | |
2397 | .user = OCP_USER_MPU, | |
2398 | }; | |
2399 | ||
2400 | /* l3_main_1 -> l3_main_2 */ | |
2401 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = { | |
2402 | .master = &dra7xx_l3_main_1_hwmod, | |
2403 | .slave = &dra7xx_l3_main_2_hwmod, | |
2404 | .clk = "l3_iclk_div", | |
2405 | .user = OCP_USER_MPU, | |
2406 | }; | |
2407 | ||
2408 | /* l4_cfg -> l3_main_2 */ | |
2409 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = { | |
2410 | .master = &dra7xx_l4_cfg_hwmod, | |
2411 | .slave = &dra7xx_l3_main_2_hwmod, | |
2412 | .clk = "l3_iclk_div", | |
2413 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2414 | }; | |
2415 | ||
2416 | /* l3_main_1 -> l4_cfg */ | |
2417 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = { | |
2418 | .master = &dra7xx_l3_main_1_hwmod, | |
2419 | .slave = &dra7xx_l4_cfg_hwmod, | |
2420 | .clk = "l3_iclk_div", | |
2421 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2422 | }; | |
2423 | ||
2424 | /* l3_main_1 -> l4_per1 */ | |
2425 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = { | |
2426 | .master = &dra7xx_l3_main_1_hwmod, | |
2427 | .slave = &dra7xx_l4_per1_hwmod, | |
2428 | .clk = "l3_iclk_div", | |
2429 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2430 | }; | |
2431 | ||
2432 | /* l3_main_1 -> l4_per2 */ | |
2433 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = { | |
2434 | .master = &dra7xx_l3_main_1_hwmod, | |
2435 | .slave = &dra7xx_l4_per2_hwmod, | |
2436 | .clk = "l3_iclk_div", | |
2437 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2438 | }; | |
2439 | ||
2440 | /* l3_main_1 -> l4_per3 */ | |
2441 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = { | |
2442 | .master = &dra7xx_l3_main_1_hwmod, | |
2443 | .slave = &dra7xx_l4_per3_hwmod, | |
2444 | .clk = "l3_iclk_div", | |
2445 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2446 | }; | |
2447 | ||
2448 | /* l3_main_1 -> l4_wkup */ | |
2449 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = { | |
2450 | .master = &dra7xx_l3_main_1_hwmod, | |
2451 | .slave = &dra7xx_l4_wkup_hwmod, | |
2452 | .clk = "wkupaon_iclk_mux", | |
2453 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2454 | }; | |
2455 | ||
2456 | /* l4_per2 -> atl */ | |
2457 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = { | |
2458 | .master = &dra7xx_l4_per2_hwmod, | |
2459 | .slave = &dra7xx_atl_hwmod, | |
2460 | .clk = "l3_iclk_div", | |
2461 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2462 | }; | |
2463 | ||
2464 | /* l3_main_1 -> bb2d */ | |
2465 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = { | |
2466 | .master = &dra7xx_l3_main_1_hwmod, | |
2467 | .slave = &dra7xx_bb2d_hwmod, | |
2468 | .clk = "l3_iclk_div", | |
2469 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2470 | }; | |
2471 | ||
2472 | /* l4_wkup -> counter_32k */ | |
2473 | static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = { | |
2474 | .master = &dra7xx_l4_wkup_hwmod, | |
2475 | .slave = &dra7xx_counter_32k_hwmod, | |
2476 | .clk = "wkupaon_iclk_mux", | |
2477 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2478 | }; | |
2479 | ||
2480 | /* l4_wkup -> ctrl_module_wkup */ | |
2481 | static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = { | |
2482 | .master = &dra7xx_l4_wkup_hwmod, | |
2483 | .slave = &dra7xx_ctrl_module_wkup_hwmod, | |
2484 | .clk = "wkupaon_iclk_mux", | |
2485 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2486 | }; | |
2487 | ||
077c42f7 M |
2488 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = { |
2489 | .master = &dra7xx_l4_per2_hwmod, | |
2490 | .slave = &dra7xx_gmac_hwmod, | |
2491 | .clk = "dpll_gmac_ck", | |
2492 | .user = OCP_USER_MPU, | |
2493 | }; | |
2494 | ||
2495 | static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = { | |
2496 | .master = &dra7xx_gmac_hwmod, | |
2497 | .slave = &dra7xx_mdio_hwmod, | |
2498 | .user = OCP_USER_MPU, | |
2499 | }; | |
2500 | ||
90020c7b A |
2501 | /* l4_wkup -> dcan1 */ |
2502 | static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = { | |
2503 | .master = &dra7xx_l4_wkup_hwmod, | |
2504 | .slave = &dra7xx_dcan1_hwmod, | |
2505 | .clk = "wkupaon_iclk_mux", | |
2506 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2507 | }; | |
2508 | ||
2509 | /* l4_per2 -> dcan2 */ | |
2510 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = { | |
2511 | .master = &dra7xx_l4_per2_hwmod, | |
2512 | .slave = &dra7xx_dcan2_hwmod, | |
2513 | .clk = "l3_iclk_div", | |
2514 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2515 | }; | |
2516 | ||
2517 | static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = { | |
2518 | { | |
2519 | .pa_start = 0x4a056000, | |
2520 | .pa_end = 0x4a056fff, | |
2521 | .flags = ADDR_TYPE_RT | |
2522 | }, | |
2523 | { } | |
2524 | }; | |
2525 | ||
2526 | /* l4_cfg -> dma_system */ | |
2527 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = { | |
2528 | .master = &dra7xx_l4_cfg_hwmod, | |
2529 | .slave = &dra7xx_dma_system_hwmod, | |
2530 | .clk = "l3_iclk_div", | |
2531 | .addr = dra7xx_dma_system_addrs, | |
2532 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2533 | }; | |
2534 | ||
2535 | static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = { | |
2536 | { | |
2537 | .name = "family", | |
2538 | .pa_start = 0x58000000, | |
2539 | .pa_end = 0x5800007f, | |
2540 | .flags = ADDR_TYPE_RT | |
2541 | }, | |
2542 | }; | |
2543 | ||
2544 | /* l3_main_1 -> dss */ | |
2545 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = { | |
2546 | .master = &dra7xx_l3_main_1_hwmod, | |
2547 | .slave = &dra7xx_dss_hwmod, | |
2548 | .clk = "l3_iclk_div", | |
2549 | .addr = dra7xx_dss_addrs, | |
2550 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2551 | }; | |
2552 | ||
2553 | static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = { | |
2554 | { | |
2555 | .name = "dispc", | |
2556 | .pa_start = 0x58001000, | |
2557 | .pa_end = 0x58001fff, | |
2558 | .flags = ADDR_TYPE_RT | |
2559 | }, | |
2560 | }; | |
2561 | ||
2562 | /* l3_main_1 -> dispc */ | |
2563 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = { | |
2564 | .master = &dra7xx_l3_main_1_hwmod, | |
2565 | .slave = &dra7xx_dss_dispc_hwmod, | |
2566 | .clk = "l3_iclk_div", | |
2567 | .addr = dra7xx_dss_dispc_addrs, | |
2568 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2569 | }; | |
2570 | ||
2571 | static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = { | |
2572 | { | |
2573 | .name = "hdmi_wp", | |
2574 | .pa_start = 0x58040000, | |
2575 | .pa_end = 0x580400ff, | |
2576 | .flags = ADDR_TYPE_RT | |
2577 | }, | |
2578 | { } | |
2579 | }; | |
2580 | ||
2581 | /* l3_main_1 -> dispc */ | |
2582 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = { | |
2583 | .master = &dra7xx_l3_main_1_hwmod, | |
2584 | .slave = &dra7xx_dss_hdmi_hwmod, | |
2585 | .clk = "l3_iclk_div", | |
2586 | .addr = dra7xx_dss_hdmi_addrs, | |
2587 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2588 | }; | |
2589 | ||
2590 | static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = { | |
2591 | { | |
2592 | .pa_start = 0x48078000, | |
2593 | .pa_end = 0x48078fff, | |
2594 | .flags = ADDR_TYPE_RT | |
2595 | }, | |
2596 | { } | |
2597 | }; | |
2598 | ||
2599 | /* l4_per1 -> elm */ | |
2600 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = { | |
2601 | .master = &dra7xx_l4_per1_hwmod, | |
2602 | .slave = &dra7xx_elm_hwmod, | |
2603 | .clk = "l3_iclk_div", | |
2604 | .addr = dra7xx_elm_addrs, | |
2605 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2606 | }; | |
2607 | ||
2608 | /* l4_wkup -> gpio1 */ | |
2609 | static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = { | |
2610 | .master = &dra7xx_l4_wkup_hwmod, | |
2611 | .slave = &dra7xx_gpio1_hwmod, | |
2612 | .clk = "wkupaon_iclk_mux", | |
2613 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2614 | }; | |
2615 | ||
2616 | /* l4_per1 -> gpio2 */ | |
2617 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = { | |
2618 | .master = &dra7xx_l4_per1_hwmod, | |
2619 | .slave = &dra7xx_gpio2_hwmod, | |
2620 | .clk = "l3_iclk_div", | |
2621 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2622 | }; | |
2623 | ||
2624 | /* l4_per1 -> gpio3 */ | |
2625 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = { | |
2626 | .master = &dra7xx_l4_per1_hwmod, | |
2627 | .slave = &dra7xx_gpio3_hwmod, | |
2628 | .clk = "l3_iclk_div", | |
2629 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2630 | }; | |
2631 | ||
2632 | /* l4_per1 -> gpio4 */ | |
2633 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = { | |
2634 | .master = &dra7xx_l4_per1_hwmod, | |
2635 | .slave = &dra7xx_gpio4_hwmod, | |
2636 | .clk = "l3_iclk_div", | |
2637 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2638 | }; | |
2639 | ||
2640 | /* l4_per1 -> gpio5 */ | |
2641 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = { | |
2642 | .master = &dra7xx_l4_per1_hwmod, | |
2643 | .slave = &dra7xx_gpio5_hwmod, | |
2644 | .clk = "l3_iclk_div", | |
2645 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2646 | }; | |
2647 | ||
2648 | /* l4_per1 -> gpio6 */ | |
2649 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = { | |
2650 | .master = &dra7xx_l4_per1_hwmod, | |
2651 | .slave = &dra7xx_gpio6_hwmod, | |
2652 | .clk = "l3_iclk_div", | |
2653 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2654 | }; | |
2655 | ||
2656 | /* l4_per1 -> gpio7 */ | |
2657 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = { | |
2658 | .master = &dra7xx_l4_per1_hwmod, | |
2659 | .slave = &dra7xx_gpio7_hwmod, | |
2660 | .clk = "l3_iclk_div", | |
2661 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2662 | }; | |
2663 | ||
2664 | /* l4_per1 -> gpio8 */ | |
2665 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = { | |
2666 | .master = &dra7xx_l4_per1_hwmod, | |
2667 | .slave = &dra7xx_gpio8_hwmod, | |
2668 | .clk = "l3_iclk_div", | |
2669 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2670 | }; | |
2671 | ||
2672 | static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = { | |
2673 | { | |
2674 | .pa_start = 0x50000000, | |
2675 | .pa_end = 0x500003ff, | |
2676 | .flags = ADDR_TYPE_RT | |
2677 | }, | |
2678 | { } | |
2679 | }; | |
2680 | ||
2681 | /* l3_main_1 -> gpmc */ | |
2682 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = { | |
2683 | .master = &dra7xx_l3_main_1_hwmod, | |
2684 | .slave = &dra7xx_gpmc_hwmod, | |
2685 | .clk = "l3_iclk_div", | |
2686 | .addr = dra7xx_gpmc_addrs, | |
2687 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2688 | }; | |
2689 | ||
2690 | static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = { | |
2691 | { | |
2692 | .pa_start = 0x480b2000, | |
2693 | .pa_end = 0x480b201f, | |
2694 | .flags = ADDR_TYPE_RT | |
2695 | }, | |
2696 | { } | |
2697 | }; | |
2698 | ||
2699 | /* l4_per1 -> hdq1w */ | |
2700 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = { | |
2701 | .master = &dra7xx_l4_per1_hwmod, | |
2702 | .slave = &dra7xx_hdq1w_hwmod, | |
2703 | .clk = "l3_iclk_div", | |
2704 | .addr = dra7xx_hdq1w_addrs, | |
2705 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2706 | }; | |
2707 | ||
2708 | /* l4_per1 -> i2c1 */ | |
2709 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = { | |
2710 | .master = &dra7xx_l4_per1_hwmod, | |
2711 | .slave = &dra7xx_i2c1_hwmod, | |
2712 | .clk = "l3_iclk_div", | |
2713 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2714 | }; | |
2715 | ||
2716 | /* l4_per1 -> i2c2 */ | |
2717 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = { | |
2718 | .master = &dra7xx_l4_per1_hwmod, | |
2719 | .slave = &dra7xx_i2c2_hwmod, | |
2720 | .clk = "l3_iclk_div", | |
2721 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2722 | }; | |
2723 | ||
2724 | /* l4_per1 -> i2c3 */ | |
2725 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = { | |
2726 | .master = &dra7xx_l4_per1_hwmod, | |
2727 | .slave = &dra7xx_i2c3_hwmod, | |
2728 | .clk = "l3_iclk_div", | |
2729 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2730 | }; | |
2731 | ||
2732 | /* l4_per1 -> i2c4 */ | |
2733 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = { | |
2734 | .master = &dra7xx_l4_per1_hwmod, | |
2735 | .slave = &dra7xx_i2c4_hwmod, | |
2736 | .clk = "l3_iclk_div", | |
2737 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2738 | }; | |
2739 | ||
2740 | /* l4_per1 -> i2c5 */ | |
2741 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = { | |
2742 | .master = &dra7xx_l4_per1_hwmod, | |
2743 | .slave = &dra7xx_i2c5_hwmod, | |
2744 | .clk = "l3_iclk_div", | |
2745 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2746 | }; | |
2747 | ||
067395d4 SA |
2748 | /* l4_cfg -> mailbox1 */ |
2749 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = { | |
2750 | .master = &dra7xx_l4_cfg_hwmod, | |
2751 | .slave = &dra7xx_mailbox1_hwmod, | |
2752 | .clk = "l3_iclk_div", | |
2753 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2754 | }; | |
2755 | ||
2756 | /* l4_per3 -> mailbox2 */ | |
2757 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = { | |
2758 | .master = &dra7xx_l4_per3_hwmod, | |
2759 | .slave = &dra7xx_mailbox2_hwmod, | |
2760 | .clk = "l3_iclk_div", | |
2761 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2762 | }; | |
2763 | ||
2764 | /* l4_per3 -> mailbox3 */ | |
2765 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = { | |
2766 | .master = &dra7xx_l4_per3_hwmod, | |
2767 | .slave = &dra7xx_mailbox3_hwmod, | |
2768 | .clk = "l3_iclk_div", | |
2769 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2770 | }; | |
2771 | ||
2772 | /* l4_per3 -> mailbox4 */ | |
2773 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = { | |
2774 | .master = &dra7xx_l4_per3_hwmod, | |
2775 | .slave = &dra7xx_mailbox4_hwmod, | |
2776 | .clk = "l3_iclk_div", | |
2777 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2778 | }; | |
2779 | ||
2780 | /* l4_per3 -> mailbox5 */ | |
2781 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = { | |
2782 | .master = &dra7xx_l4_per3_hwmod, | |
2783 | .slave = &dra7xx_mailbox5_hwmod, | |
2784 | .clk = "l3_iclk_div", | |
2785 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2786 | }; | |
2787 | ||
2788 | /* l4_per3 -> mailbox6 */ | |
2789 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = { | |
2790 | .master = &dra7xx_l4_per3_hwmod, | |
2791 | .slave = &dra7xx_mailbox6_hwmod, | |
2792 | .clk = "l3_iclk_div", | |
2793 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2794 | }; | |
2795 | ||
2796 | /* l4_per3 -> mailbox7 */ | |
2797 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = { | |
2798 | .master = &dra7xx_l4_per3_hwmod, | |
2799 | .slave = &dra7xx_mailbox7_hwmod, | |
2800 | .clk = "l3_iclk_div", | |
2801 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2802 | }; | |
2803 | ||
2804 | /* l4_per3 -> mailbox8 */ | |
2805 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = { | |
2806 | .master = &dra7xx_l4_per3_hwmod, | |
2807 | .slave = &dra7xx_mailbox8_hwmod, | |
2808 | .clk = "l3_iclk_div", | |
2809 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2810 | }; | |
2811 | ||
2812 | /* l4_per3 -> mailbox9 */ | |
2813 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = { | |
2814 | .master = &dra7xx_l4_per3_hwmod, | |
2815 | .slave = &dra7xx_mailbox9_hwmod, | |
2816 | .clk = "l3_iclk_div", | |
2817 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2818 | }; | |
2819 | ||
2820 | /* l4_per3 -> mailbox10 */ | |
2821 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = { | |
2822 | .master = &dra7xx_l4_per3_hwmod, | |
2823 | .slave = &dra7xx_mailbox10_hwmod, | |
2824 | .clk = "l3_iclk_div", | |
2825 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2826 | }; | |
2827 | ||
2828 | /* l4_per3 -> mailbox11 */ | |
2829 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = { | |
2830 | .master = &dra7xx_l4_per3_hwmod, | |
2831 | .slave = &dra7xx_mailbox11_hwmod, | |
2832 | .clk = "l3_iclk_div", | |
2833 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2834 | }; | |
2835 | ||
2836 | /* l4_per3 -> mailbox12 */ | |
2837 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = { | |
2838 | .master = &dra7xx_l4_per3_hwmod, | |
2839 | .slave = &dra7xx_mailbox12_hwmod, | |
2840 | .clk = "l3_iclk_div", | |
2841 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2842 | }; | |
2843 | ||
2844 | /* l4_per3 -> mailbox13 */ | |
2845 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = { | |
2846 | .master = &dra7xx_l4_per3_hwmod, | |
2847 | .slave = &dra7xx_mailbox13_hwmod, | |
2848 | .clk = "l3_iclk_div", | |
2849 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2850 | }; | |
2851 | ||
90020c7b A |
2852 | /* l4_per1 -> mcspi1 */ |
2853 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = { | |
2854 | .master = &dra7xx_l4_per1_hwmod, | |
2855 | .slave = &dra7xx_mcspi1_hwmod, | |
2856 | .clk = "l3_iclk_div", | |
2857 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2858 | }; | |
2859 | ||
2860 | /* l4_per1 -> mcspi2 */ | |
2861 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = { | |
2862 | .master = &dra7xx_l4_per1_hwmod, | |
2863 | .slave = &dra7xx_mcspi2_hwmod, | |
2864 | .clk = "l3_iclk_div", | |
2865 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2866 | }; | |
2867 | ||
2868 | /* l4_per1 -> mcspi3 */ | |
2869 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = { | |
2870 | .master = &dra7xx_l4_per1_hwmod, | |
2871 | .slave = &dra7xx_mcspi3_hwmod, | |
2872 | .clk = "l3_iclk_div", | |
2873 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2874 | }; | |
2875 | ||
2876 | /* l4_per1 -> mcspi4 */ | |
2877 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = { | |
2878 | .master = &dra7xx_l4_per1_hwmod, | |
2879 | .slave = &dra7xx_mcspi4_hwmod, | |
2880 | .clk = "l3_iclk_div", | |
2881 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2882 | }; | |
2883 | ||
2884 | /* l4_per1 -> mmc1 */ | |
2885 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = { | |
2886 | .master = &dra7xx_l4_per1_hwmod, | |
2887 | .slave = &dra7xx_mmc1_hwmod, | |
2888 | .clk = "l3_iclk_div", | |
2889 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2890 | }; | |
2891 | ||
2892 | /* l4_per1 -> mmc2 */ | |
2893 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = { | |
2894 | .master = &dra7xx_l4_per1_hwmod, | |
2895 | .slave = &dra7xx_mmc2_hwmod, | |
2896 | .clk = "l3_iclk_div", | |
2897 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2898 | }; | |
2899 | ||
2900 | /* l4_per1 -> mmc3 */ | |
2901 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = { | |
2902 | .master = &dra7xx_l4_per1_hwmod, | |
2903 | .slave = &dra7xx_mmc3_hwmod, | |
2904 | .clk = "l3_iclk_div", | |
2905 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2906 | }; | |
2907 | ||
2908 | /* l4_per1 -> mmc4 */ | |
2909 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = { | |
2910 | .master = &dra7xx_l4_per1_hwmod, | |
2911 | .slave = &dra7xx_mmc4_hwmod, | |
2912 | .clk = "l3_iclk_div", | |
2913 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2914 | }; | |
2915 | ||
2916 | /* l4_cfg -> mpu */ | |
2917 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = { | |
2918 | .master = &dra7xx_l4_cfg_hwmod, | |
2919 | .slave = &dra7xx_mpu_hwmod, | |
2920 | .clk = "l3_iclk_div", | |
2921 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2922 | }; | |
2923 | ||
90020c7b A |
2924 | /* l4_cfg -> ocp2scp1 */ |
2925 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = { | |
2926 | .master = &dra7xx_l4_cfg_hwmod, | |
2927 | .slave = &dra7xx_ocp2scp1_hwmod, | |
2928 | .clk = "l4_root_clk_div", | |
90020c7b A |
2929 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2930 | }; | |
2931 | ||
df0d0f11 RQ |
2932 | /* l4_cfg -> ocp2scp3 */ |
2933 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = { | |
2934 | .master = &dra7xx_l4_cfg_hwmod, | |
2935 | .slave = &dra7xx_ocp2scp3_hwmod, | |
2936 | .clk = "l4_root_clk_div", | |
2937 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2938 | }; | |
2939 | ||
8dd3eb71 KVA |
2940 | /* l3_main_1 -> pcie1 */ |
2941 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = { | |
2942 | .master = &dra7xx_l3_main_1_hwmod, | |
2943 | .slave = &dra7xx_pcie1_hwmod, | |
2944 | .clk = "l3_iclk_div", | |
2945 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2946 | }; | |
2947 | ||
2948 | /* l4_cfg -> pcie1 */ | |
2949 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = { | |
2950 | .master = &dra7xx_l4_cfg_hwmod, | |
2951 | .slave = &dra7xx_pcie1_hwmod, | |
2952 | .clk = "l4_root_clk_div", | |
2953 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2954 | }; | |
2955 | ||
2956 | /* l3_main_1 -> pcie2 */ | |
2957 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = { | |
2958 | .master = &dra7xx_l3_main_1_hwmod, | |
2959 | .slave = &dra7xx_pcie2_hwmod, | |
2960 | .clk = "l3_iclk_div", | |
2961 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2962 | }; | |
2963 | ||
2964 | /* l4_cfg -> pcie2 */ | |
2965 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = { | |
2966 | .master = &dra7xx_l4_cfg_hwmod, | |
2967 | .slave = &dra7xx_pcie2_hwmod, | |
2968 | .clk = "l4_root_clk_div", | |
2969 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2970 | }; | |
2971 | ||
70c18ef7 KVA |
2972 | /* l4_cfg -> pcie1 phy */ |
2973 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = { | |
2974 | .master = &dra7xx_l4_cfg_hwmod, | |
2975 | .slave = &dra7xx_pcie1_phy_hwmod, | |
2976 | .clk = "l4_root_clk_div", | |
2977 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2978 | }; | |
2979 | ||
2980 | /* l4_cfg -> pcie2 phy */ | |
2981 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = { | |
2982 | .master = &dra7xx_l4_cfg_hwmod, | |
2983 | .slave = &dra7xx_pcie2_phy_hwmod, | |
2984 | .clk = "l4_root_clk_div", | |
2985 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2986 | }; | |
2987 | ||
90020c7b A |
2988 | static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = { |
2989 | { | |
2990 | .pa_start = 0x4b300000, | |
2991 | .pa_end = 0x4b30007f, | |
2992 | .flags = ADDR_TYPE_RT | |
2993 | }, | |
2994 | { } | |
2995 | }; | |
2996 | ||
2997 | /* l3_main_1 -> qspi */ | |
2998 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = { | |
2999 | .master = &dra7xx_l3_main_1_hwmod, | |
3000 | .slave = &dra7xx_qspi_hwmod, | |
3001 | .clk = "l3_iclk_div", | |
3002 | .addr = dra7xx_qspi_addrs, | |
3003 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3004 | }; | |
3005 | ||
c913c8a1 LV |
3006 | /* l4_per3 -> rtcss */ |
3007 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = { | |
3008 | .master = &dra7xx_l4_per3_hwmod, | |
3009 | .slave = &dra7xx_rtcss_hwmod, | |
3010 | .clk = "l4_root_clk_div", | |
3011 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3012 | }; | |
3013 | ||
90020c7b A |
3014 | static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = { |
3015 | { | |
3016 | .name = "sysc", | |
3017 | .pa_start = 0x4a141100, | |
3018 | .pa_end = 0x4a141107, | |
3019 | .flags = ADDR_TYPE_RT | |
3020 | }, | |
3021 | { } | |
3022 | }; | |
3023 | ||
3024 | /* l4_cfg -> sata */ | |
3025 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = { | |
3026 | .master = &dra7xx_l4_cfg_hwmod, | |
3027 | .slave = &dra7xx_sata_hwmod, | |
3028 | .clk = "l3_iclk_div", | |
3029 | .addr = dra7xx_sata_addrs, | |
3030 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3031 | }; | |
3032 | ||
3033 | static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = { | |
3034 | { | |
3035 | .pa_start = 0x4a0dd000, | |
3036 | .pa_end = 0x4a0dd07f, | |
3037 | .flags = ADDR_TYPE_RT | |
3038 | }, | |
3039 | { } | |
3040 | }; | |
3041 | ||
3042 | /* l4_cfg -> smartreflex_core */ | |
3043 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = { | |
3044 | .master = &dra7xx_l4_cfg_hwmod, | |
3045 | .slave = &dra7xx_smartreflex_core_hwmod, | |
3046 | .clk = "l4_root_clk_div", | |
3047 | .addr = dra7xx_smartreflex_core_addrs, | |
3048 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3049 | }; | |
3050 | ||
3051 | static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = { | |
3052 | { | |
3053 | .pa_start = 0x4a0d9000, | |
3054 | .pa_end = 0x4a0d907f, | |
3055 | .flags = ADDR_TYPE_RT | |
3056 | }, | |
3057 | { } | |
3058 | }; | |
3059 | ||
3060 | /* l4_cfg -> smartreflex_mpu */ | |
3061 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = { | |
3062 | .master = &dra7xx_l4_cfg_hwmod, | |
3063 | .slave = &dra7xx_smartreflex_mpu_hwmod, | |
3064 | .clk = "l4_root_clk_div", | |
3065 | .addr = dra7xx_smartreflex_mpu_addrs, | |
3066 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3067 | }; | |
3068 | ||
3069 | static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = { | |
3070 | { | |
3071 | .pa_start = 0x4a0f6000, | |
3072 | .pa_end = 0x4a0f6fff, | |
3073 | .flags = ADDR_TYPE_RT | |
3074 | }, | |
3075 | { } | |
3076 | }; | |
3077 | ||
3078 | /* l4_cfg -> spinlock */ | |
3079 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = { | |
3080 | .master = &dra7xx_l4_cfg_hwmod, | |
3081 | .slave = &dra7xx_spinlock_hwmod, | |
3082 | .clk = "l3_iclk_div", | |
3083 | .addr = dra7xx_spinlock_addrs, | |
3084 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3085 | }; | |
3086 | ||
3087 | /* l4_wkup -> timer1 */ | |
3088 | static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = { | |
3089 | .master = &dra7xx_l4_wkup_hwmod, | |
3090 | .slave = &dra7xx_timer1_hwmod, | |
3091 | .clk = "wkupaon_iclk_mux", | |
3092 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3093 | }; | |
3094 | ||
3095 | /* l4_per1 -> timer2 */ | |
3096 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = { | |
3097 | .master = &dra7xx_l4_per1_hwmod, | |
3098 | .slave = &dra7xx_timer2_hwmod, | |
3099 | .clk = "l3_iclk_div", | |
3100 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3101 | }; | |
3102 | ||
3103 | /* l4_per1 -> timer3 */ | |
3104 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = { | |
3105 | .master = &dra7xx_l4_per1_hwmod, | |
3106 | .slave = &dra7xx_timer3_hwmod, | |
3107 | .clk = "l3_iclk_div", | |
3108 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3109 | }; | |
3110 | ||
3111 | /* l4_per1 -> timer4 */ | |
3112 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = { | |
3113 | .master = &dra7xx_l4_per1_hwmod, | |
3114 | .slave = &dra7xx_timer4_hwmod, | |
3115 | .clk = "l3_iclk_div", | |
3116 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3117 | }; | |
3118 | ||
3119 | /* l4_per3 -> timer5 */ | |
3120 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = { | |
3121 | .master = &dra7xx_l4_per3_hwmod, | |
3122 | .slave = &dra7xx_timer5_hwmod, | |
3123 | .clk = "l3_iclk_div", | |
3124 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3125 | }; | |
3126 | ||
3127 | /* l4_per3 -> timer6 */ | |
3128 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = { | |
3129 | .master = &dra7xx_l4_per3_hwmod, | |
3130 | .slave = &dra7xx_timer6_hwmod, | |
3131 | .clk = "l3_iclk_div", | |
3132 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3133 | }; | |
3134 | ||
3135 | /* l4_per3 -> timer7 */ | |
3136 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = { | |
3137 | .master = &dra7xx_l4_per3_hwmod, | |
3138 | .slave = &dra7xx_timer7_hwmod, | |
3139 | .clk = "l3_iclk_div", | |
3140 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3141 | }; | |
3142 | ||
3143 | /* l4_per3 -> timer8 */ | |
3144 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = { | |
3145 | .master = &dra7xx_l4_per3_hwmod, | |
3146 | .slave = &dra7xx_timer8_hwmod, | |
3147 | .clk = "l3_iclk_div", | |
3148 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3149 | }; | |
3150 | ||
3151 | /* l4_per1 -> timer9 */ | |
3152 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = { | |
3153 | .master = &dra7xx_l4_per1_hwmod, | |
3154 | .slave = &dra7xx_timer9_hwmod, | |
3155 | .clk = "l3_iclk_div", | |
3156 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3157 | }; | |
3158 | ||
3159 | /* l4_per1 -> timer10 */ | |
3160 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = { | |
3161 | .master = &dra7xx_l4_per1_hwmod, | |
3162 | .slave = &dra7xx_timer10_hwmod, | |
3163 | .clk = "l3_iclk_div", | |
3164 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3165 | }; | |
3166 | ||
3167 | /* l4_per1 -> timer11 */ | |
3168 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = { | |
3169 | .master = &dra7xx_l4_per1_hwmod, | |
3170 | .slave = &dra7xx_timer11_hwmod, | |
3171 | .clk = "l3_iclk_div", | |
3172 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3173 | }; | |
3174 | ||
1ac964f4 SA |
3175 | /* l4_per3 -> timer13 */ |
3176 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = { | |
3177 | .master = &dra7xx_l4_per3_hwmod, | |
3178 | .slave = &dra7xx_timer13_hwmod, | |
3179 | .clk = "l3_iclk_div", | |
3180 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3181 | }; | |
3182 | ||
3183 | /* l4_per3 -> timer14 */ | |
3184 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = { | |
3185 | .master = &dra7xx_l4_per3_hwmod, | |
3186 | .slave = &dra7xx_timer14_hwmod, | |
3187 | .clk = "l3_iclk_div", | |
3188 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3189 | }; | |
3190 | ||
3191 | /* l4_per3 -> timer15 */ | |
3192 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = { | |
3193 | .master = &dra7xx_l4_per3_hwmod, | |
3194 | .slave = &dra7xx_timer15_hwmod, | |
3195 | .clk = "l3_iclk_div", | |
3196 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3197 | }; | |
3198 | ||
3199 | /* l4_per3 -> timer16 */ | |
3200 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = { | |
3201 | .master = &dra7xx_l4_per3_hwmod, | |
3202 | .slave = &dra7xx_timer16_hwmod, | |
3203 | .clk = "l3_iclk_div", | |
3204 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3205 | }; | |
3206 | ||
90020c7b A |
3207 | /* l4_per1 -> uart1 */ |
3208 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = { | |
3209 | .master = &dra7xx_l4_per1_hwmod, | |
3210 | .slave = &dra7xx_uart1_hwmod, | |
3211 | .clk = "l3_iclk_div", | |
3212 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3213 | }; | |
3214 | ||
3215 | /* l4_per1 -> uart2 */ | |
3216 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = { | |
3217 | .master = &dra7xx_l4_per1_hwmod, | |
3218 | .slave = &dra7xx_uart2_hwmod, | |
3219 | .clk = "l3_iclk_div", | |
3220 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3221 | }; | |
3222 | ||
3223 | /* l4_per1 -> uart3 */ | |
3224 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = { | |
3225 | .master = &dra7xx_l4_per1_hwmod, | |
3226 | .slave = &dra7xx_uart3_hwmod, | |
3227 | .clk = "l3_iclk_div", | |
3228 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3229 | }; | |
3230 | ||
3231 | /* l4_per1 -> uart4 */ | |
3232 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = { | |
3233 | .master = &dra7xx_l4_per1_hwmod, | |
3234 | .slave = &dra7xx_uart4_hwmod, | |
3235 | .clk = "l3_iclk_div", | |
3236 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3237 | }; | |
3238 | ||
3239 | /* l4_per1 -> uart5 */ | |
3240 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = { | |
3241 | .master = &dra7xx_l4_per1_hwmod, | |
3242 | .slave = &dra7xx_uart5_hwmod, | |
3243 | .clk = "l3_iclk_div", | |
3244 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3245 | }; | |
3246 | ||
3247 | /* l4_per1 -> uart6 */ | |
3248 | static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = { | |
3249 | .master = &dra7xx_l4_per1_hwmod, | |
3250 | .slave = &dra7xx_uart6_hwmod, | |
3251 | .clk = "l3_iclk_div", | |
3252 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3253 | }; | |
3254 | ||
33acc9ff A |
3255 | /* l4_per2 -> uart7 */ |
3256 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = { | |
3257 | .master = &dra7xx_l4_per2_hwmod, | |
3258 | .slave = &dra7xx_uart7_hwmod, | |
3259 | .clk = "l3_iclk_div", | |
3260 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3261 | }; | |
3262 | ||
3263 | /* l4_per2 -> uart8 */ | |
3264 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = { | |
3265 | .master = &dra7xx_l4_per2_hwmod, | |
3266 | .slave = &dra7xx_uart8_hwmod, | |
3267 | .clk = "l3_iclk_div", | |
3268 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3269 | }; | |
3270 | ||
3271 | /* l4_per2 -> uart9 */ | |
3272 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = { | |
3273 | .master = &dra7xx_l4_per2_hwmod, | |
3274 | .slave = &dra7xx_uart9_hwmod, | |
3275 | .clk = "l3_iclk_div", | |
3276 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3277 | }; | |
3278 | ||
3279 | /* l4_wkup -> uart10 */ | |
3280 | static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = { | |
3281 | .master = &dra7xx_l4_wkup_hwmod, | |
3282 | .slave = &dra7xx_uart10_hwmod, | |
3283 | .clk = "wkupaon_iclk_mux", | |
3284 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3285 | }; | |
3286 | ||
90020c7b A |
3287 | /* l4_per3 -> usb_otg_ss1 */ |
3288 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = { | |
3289 | .master = &dra7xx_l4_per3_hwmod, | |
3290 | .slave = &dra7xx_usb_otg_ss1_hwmod, | |
3291 | .clk = "dpll_core_h13x2_ck", | |
3292 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3293 | }; | |
3294 | ||
3295 | /* l4_per3 -> usb_otg_ss2 */ | |
3296 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = { | |
3297 | .master = &dra7xx_l4_per3_hwmod, | |
3298 | .slave = &dra7xx_usb_otg_ss2_hwmod, | |
3299 | .clk = "dpll_core_h13x2_ck", | |
3300 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3301 | }; | |
3302 | ||
3303 | /* l4_per3 -> usb_otg_ss3 */ | |
3304 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = { | |
3305 | .master = &dra7xx_l4_per3_hwmod, | |
3306 | .slave = &dra7xx_usb_otg_ss3_hwmod, | |
3307 | .clk = "dpll_core_h13x2_ck", | |
3308 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3309 | }; | |
3310 | ||
3311 | /* l4_per3 -> usb_otg_ss4 */ | |
3312 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = { | |
3313 | .master = &dra7xx_l4_per3_hwmod, | |
3314 | .slave = &dra7xx_usb_otg_ss4_hwmod, | |
3315 | .clk = "dpll_core_h13x2_ck", | |
3316 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3317 | }; | |
3318 | ||
3319 | /* l3_main_1 -> vcp1 */ | |
3320 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = { | |
3321 | .master = &dra7xx_l3_main_1_hwmod, | |
3322 | .slave = &dra7xx_vcp1_hwmod, | |
3323 | .clk = "l3_iclk_div", | |
3324 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3325 | }; | |
3326 | ||
3327 | /* l4_per2 -> vcp1 */ | |
3328 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = { | |
3329 | .master = &dra7xx_l4_per2_hwmod, | |
3330 | .slave = &dra7xx_vcp1_hwmod, | |
3331 | .clk = "l3_iclk_div", | |
3332 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3333 | }; | |
3334 | ||
3335 | /* l3_main_1 -> vcp2 */ | |
3336 | static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = { | |
3337 | .master = &dra7xx_l3_main_1_hwmod, | |
3338 | .slave = &dra7xx_vcp2_hwmod, | |
3339 | .clk = "l3_iclk_div", | |
3340 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3341 | }; | |
3342 | ||
3343 | /* l4_per2 -> vcp2 */ | |
3344 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = { | |
3345 | .master = &dra7xx_l4_per2_hwmod, | |
3346 | .slave = &dra7xx_vcp2_hwmod, | |
3347 | .clk = "l3_iclk_div", | |
3348 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3349 | }; | |
3350 | ||
3351 | /* l4_wkup -> wd_timer2 */ | |
3352 | static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = { | |
3353 | .master = &dra7xx_l4_wkup_hwmod, | |
3354 | .slave = &dra7xx_wd_timer2_hwmod, | |
3355 | .clk = "wkupaon_iclk_mux", | |
3356 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3357 | }; | |
3358 | ||
3359 | static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { | |
3360 | &dra7xx_l3_main_2__l3_instr, | |
3361 | &dra7xx_l4_cfg__l3_main_1, | |
3362 | &dra7xx_mpu__l3_main_1, | |
3363 | &dra7xx_l3_main_1__l3_main_2, | |
3364 | &dra7xx_l4_cfg__l3_main_2, | |
3365 | &dra7xx_l3_main_1__l4_cfg, | |
3366 | &dra7xx_l3_main_1__l4_per1, | |
3367 | &dra7xx_l3_main_1__l4_per2, | |
3368 | &dra7xx_l3_main_1__l4_per3, | |
3369 | &dra7xx_l3_main_1__l4_wkup, | |
3370 | &dra7xx_l4_per2__atl, | |
3371 | &dra7xx_l3_main_1__bb2d, | |
3372 | &dra7xx_l4_wkup__counter_32k, | |
3373 | &dra7xx_l4_wkup__ctrl_module_wkup, | |
3374 | &dra7xx_l4_wkup__dcan1, | |
3375 | &dra7xx_l4_per2__dcan2, | |
077c42f7 M |
3376 | &dra7xx_l4_per2__cpgmac0, |
3377 | &dra7xx_gmac__mdio, | |
90020c7b A |
3378 | &dra7xx_l4_cfg__dma_system, |
3379 | &dra7xx_l3_main_1__dss, | |
3380 | &dra7xx_l3_main_1__dispc, | |
3381 | &dra7xx_l3_main_1__hdmi, | |
3382 | &dra7xx_l4_per1__elm, | |
3383 | &dra7xx_l4_wkup__gpio1, | |
3384 | &dra7xx_l4_per1__gpio2, | |
3385 | &dra7xx_l4_per1__gpio3, | |
3386 | &dra7xx_l4_per1__gpio4, | |
3387 | &dra7xx_l4_per1__gpio5, | |
3388 | &dra7xx_l4_per1__gpio6, | |
3389 | &dra7xx_l4_per1__gpio7, | |
3390 | &dra7xx_l4_per1__gpio8, | |
3391 | &dra7xx_l3_main_1__gpmc, | |
3392 | &dra7xx_l4_per1__hdq1w, | |
3393 | &dra7xx_l4_per1__i2c1, | |
3394 | &dra7xx_l4_per1__i2c2, | |
3395 | &dra7xx_l4_per1__i2c3, | |
3396 | &dra7xx_l4_per1__i2c4, | |
3397 | &dra7xx_l4_per1__i2c5, | |
067395d4 SA |
3398 | &dra7xx_l4_cfg__mailbox1, |
3399 | &dra7xx_l4_per3__mailbox2, | |
3400 | &dra7xx_l4_per3__mailbox3, | |
3401 | &dra7xx_l4_per3__mailbox4, | |
3402 | &dra7xx_l4_per3__mailbox5, | |
3403 | &dra7xx_l4_per3__mailbox6, | |
3404 | &dra7xx_l4_per3__mailbox7, | |
3405 | &dra7xx_l4_per3__mailbox8, | |
3406 | &dra7xx_l4_per3__mailbox9, | |
3407 | &dra7xx_l4_per3__mailbox10, | |
3408 | &dra7xx_l4_per3__mailbox11, | |
3409 | &dra7xx_l4_per3__mailbox12, | |
3410 | &dra7xx_l4_per3__mailbox13, | |
90020c7b A |
3411 | &dra7xx_l4_per1__mcspi1, |
3412 | &dra7xx_l4_per1__mcspi2, | |
3413 | &dra7xx_l4_per1__mcspi3, | |
3414 | &dra7xx_l4_per1__mcspi4, | |
3415 | &dra7xx_l4_per1__mmc1, | |
3416 | &dra7xx_l4_per1__mmc2, | |
3417 | &dra7xx_l4_per1__mmc3, | |
3418 | &dra7xx_l4_per1__mmc4, | |
3419 | &dra7xx_l4_cfg__mpu, | |
3420 | &dra7xx_l4_cfg__ocp2scp1, | |
df0d0f11 | 3421 | &dra7xx_l4_cfg__ocp2scp3, |
8dd3eb71 KVA |
3422 | &dra7xx_l3_main_1__pcie1, |
3423 | &dra7xx_l4_cfg__pcie1, | |
3424 | &dra7xx_l3_main_1__pcie2, | |
3425 | &dra7xx_l4_cfg__pcie2, | |
70c18ef7 KVA |
3426 | &dra7xx_l4_cfg__pcie1_phy, |
3427 | &dra7xx_l4_cfg__pcie2_phy, | |
90020c7b | 3428 | &dra7xx_l3_main_1__qspi, |
c913c8a1 | 3429 | &dra7xx_l4_per3__rtcss, |
90020c7b A |
3430 | &dra7xx_l4_cfg__sata, |
3431 | &dra7xx_l4_cfg__smartreflex_core, | |
3432 | &dra7xx_l4_cfg__smartreflex_mpu, | |
3433 | &dra7xx_l4_cfg__spinlock, | |
3434 | &dra7xx_l4_wkup__timer1, | |
3435 | &dra7xx_l4_per1__timer2, | |
3436 | &dra7xx_l4_per1__timer3, | |
3437 | &dra7xx_l4_per1__timer4, | |
3438 | &dra7xx_l4_per3__timer5, | |
3439 | &dra7xx_l4_per3__timer6, | |
3440 | &dra7xx_l4_per3__timer7, | |
3441 | &dra7xx_l4_per3__timer8, | |
3442 | &dra7xx_l4_per1__timer9, | |
3443 | &dra7xx_l4_per1__timer10, | |
3444 | &dra7xx_l4_per1__timer11, | |
1ac964f4 SA |
3445 | &dra7xx_l4_per3__timer13, |
3446 | &dra7xx_l4_per3__timer14, | |
3447 | &dra7xx_l4_per3__timer15, | |
3448 | &dra7xx_l4_per3__timer16, | |
90020c7b A |
3449 | &dra7xx_l4_per1__uart1, |
3450 | &dra7xx_l4_per1__uart2, | |
3451 | &dra7xx_l4_per1__uart3, | |
3452 | &dra7xx_l4_per1__uart4, | |
3453 | &dra7xx_l4_per1__uart5, | |
3454 | &dra7xx_l4_per1__uart6, | |
33acc9ff A |
3455 | &dra7xx_l4_per2__uart7, |
3456 | &dra7xx_l4_per2__uart8, | |
3457 | &dra7xx_l4_per2__uart9, | |
3458 | &dra7xx_l4_wkup__uart10, | |
90020c7b A |
3459 | &dra7xx_l4_per3__usb_otg_ss1, |
3460 | &dra7xx_l4_per3__usb_otg_ss2, | |
3461 | &dra7xx_l4_per3__usb_otg_ss3, | |
90020c7b A |
3462 | &dra7xx_l3_main_1__vcp1, |
3463 | &dra7xx_l4_per2__vcp1, | |
3464 | &dra7xx_l3_main_1__vcp2, | |
3465 | &dra7xx_l4_per2__vcp2, | |
3466 | &dra7xx_l4_wkup__wd_timer2, | |
3467 | NULL, | |
3468 | }; | |
3469 | ||
f7f7a29b RN |
3470 | static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = { |
3471 | &dra7xx_l4_per3__usb_otg_ss4, | |
3472 | NULL, | |
3473 | }; | |
3474 | ||
3475 | static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = { | |
3476 | NULL, | |
3477 | }; | |
3478 | ||
90020c7b A |
3479 | int __init dra7xx_hwmod_init(void) |
3480 | { | |
f7f7a29b RN |
3481 | int ret; |
3482 | ||
90020c7b | 3483 | omap_hwmod_init(); |
f7f7a29b RN |
3484 | ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs); |
3485 | ||
3486 | if (!ret && soc_is_dra74x()) | |
3487 | return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs); | |
3488 | else if (!ret && soc_is_dra72x()) | |
3489 | return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs); | |
3490 | ||
3491 | return ret; | |
90020c7b | 3492 | } |