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ARM: DRA7: hwmod: Add custom reset handler for PCIeSS
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_7xx_data.c
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90020c7b
A		 1/*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/io.h>
21#include <linux/platform_data/gpio-omap.h>
55143438 22#include <linux/platform_data/hsmmc-omap.h>
90020c7b
A		 23#include <linux/power/smartreflex.h>
24#include <linux/i2c-omap.h>
25
26#include <linux/omap-dma.h>
27#include <linux/platform_data/spi-omap2-mcspi.h>
28#include <linux/platform_data/asoc-ti-mcbsp.h>
29#include <plat/dmtimer.h>
30
31#include "omap_hwmod.h"
32#include "omap_hwmod_common_data.h"
33#include "cm1_7xx.h"
34#include "cm2_7xx.h"
35#include "prm7xx.h"
36#include "i2c.h"
90020c7b 37#include "wd_timer.h"
f7f7a29b 38#include "soc.h"
90020c7b
A		 39
40/* Base offset for all DRA7XX interrupts external to MPUSS */
41#define DRA7XX_IRQ_GIC_START 32
42
43/* Base offset for all DRA7XX dma requests */
44#define DRA7XX_DMA_REQ_START 1
45
46
47/*
48 * IP blocks
49 */
50
42121688
TV		 51/*
52 * 'dmm' class
53 * instance(s): dmm
54 */
55static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
56 .name = "dmm",
57};
58
59/* dmm */
60static struct omap_hwmod dra7xx_dmm_hwmod = {
61 .name = "dmm",
62 .class = &dra7xx_dmm_hwmod_class,
63 .clkdm_name = "emif_clkdm",
64 .prcm = {
65 .omap4 = {
66 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
67 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
68 },
69 },
70};
71
90020c7b
A		 72/*
73 * 'l3' class
74 * instance(s): l3_instr, l3_main_1, l3_main_2
75 */
76static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
77 .name = "l3",
78};
79
80/* l3_instr */
81static struct omap_hwmod dra7xx_l3_instr_hwmod = {
82 .name = "l3_instr",
83 .class = &dra7xx_l3_hwmod_class,
84 .clkdm_name = "l3instr_clkdm",
85 .prcm = {
86 .omap4 = {
87 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
88 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
89 .modulemode = MODULEMODE_HWCTRL,
90 },
91 },
92};
93
94/* l3_main_1 */
95static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
96 .name = "l3_main_1",
97 .class = &dra7xx_l3_hwmod_class,
98 .clkdm_name = "l3main1_clkdm",
99 .prcm = {
100 .omap4 = {
101 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
102 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
103 },
104 },
105};
106
107/* l3_main_2 */
108static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
109 .name = "l3_main_2",
110 .class = &dra7xx_l3_hwmod_class,
111 .clkdm_name = "l3instr_clkdm",
112 .prcm = {
113 .omap4 = {
114 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
115 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
116 .modulemode = MODULEMODE_HWCTRL,
117 },
118 },
119};
120
121/*
122 * 'l4' class
123 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
124 */
125static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
126 .name = "l4",
127};
128
129/* l4_cfg */
130static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
131 .name = "l4_cfg",
132 .class = &dra7xx_l4_hwmod_class,
133 .clkdm_name = "l4cfg_clkdm",
134 .prcm = {
135 .omap4 = {
136 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
137 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
138 },
139 },
140};
141
142/* l4_per1 */
143static struct omap_hwmod dra7xx_l4_per1_hwmod = {
144 .name = "l4_per1",
145 .class = &dra7xx_l4_hwmod_class,
146 .clkdm_name = "l4per_clkdm",
147 .prcm = {
148 .omap4 = {
149 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
150 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
151 },
152 },
153};
154
155/* l4_per2 */
156static struct omap_hwmod dra7xx_l4_per2_hwmod = {
157 .name = "l4_per2",
158 .class = &dra7xx_l4_hwmod_class,
159 .clkdm_name = "l4per2_clkdm",
160 .prcm = {
161 .omap4 = {
162 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
163 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
164 },
165 },
166};
167
168/* l4_per3 */
169static struct omap_hwmod dra7xx_l4_per3_hwmod = {
170 .name = "l4_per3",
171 .class = &dra7xx_l4_hwmod_class,
172 .clkdm_name = "l4per3_clkdm",
173 .prcm = {
174 .omap4 = {
175 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
176 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
177 },
178 },
179};
180
181/* l4_wkup */
182static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
183 .name = "l4_wkup",
184 .class = &dra7xx_l4_hwmod_class,
185 .clkdm_name = "wkupaon_clkdm",
186 .prcm = {
187 .omap4 = {
188 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
189 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
190 },
191 },
192};
193
194/*
195 * 'atl' class
196 *
197 */
198
199static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
200 .name = "atl",
201};
202
203/* atl */
204static struct omap_hwmod dra7xx_atl_hwmod = {
205 .name = "atl",
206 .class = &dra7xx_atl_hwmod_class,
207 .clkdm_name = "atl_clkdm",
208 .main_clk = "atl_gfclk_mux",
209 .prcm = {
210 .omap4 = {
211 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
212 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
213 .modulemode = MODULEMODE_SWCTRL,
214 },
215 },
216};
217
218/*
219 * 'bb2d' class
220 *
221 */
222
223static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
224 .name = "bb2d",
225};
226
227/* bb2d */
228static struct omap_hwmod dra7xx_bb2d_hwmod = {
229 .name = "bb2d",
230 .class = &dra7xx_bb2d_hwmod_class,
231 .clkdm_name = "dss_clkdm",
232 .main_clk = "dpll_core_h24x2_ck",
233 .prcm = {
234 .omap4 = {
235 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
236 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
237 .modulemode = MODULEMODE_SWCTRL,
238 },
239 },
240};
241
242/*
243 * 'counter' class
244 *
245 */
246
247static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
248 .rev_offs = 0x0000,
249 .sysc_offs = 0x0010,
250 .sysc_flags = SYSC_HAS_SIDLEMODE,
251 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
252 SIDLE_SMART_WKUP),
253 .sysc_fields = &omap_hwmod_sysc_type1,
254};
255
256static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
257 .name = "counter",
258 .sysc = &dra7xx_counter_sysc,
259};
260
261/* counter_32k */
262static struct omap_hwmod dra7xx_counter_32k_hwmod = {
263 .name = "counter_32k",
264 .class = &dra7xx_counter_hwmod_class,
265 .clkdm_name = "wkupaon_clkdm",
266 .flags = HWMOD_SWSUP_SIDLE,
267 .main_clk = "wkupaon_iclk_mux",
268 .prcm = {
269 .omap4 = {
270 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
271 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
272 },
273 },
274};
275
276/*
277 * 'ctrl_module' class
278 *
279 */
280
281static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
282 .name = "ctrl_module",
283};
284
285/* ctrl_module_wkup */
286static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
287 .name = "ctrl_module_wkup",
288 .class = &dra7xx_ctrl_module_hwmod_class,
289 .clkdm_name = "wkupaon_clkdm",
290 .prcm = {
291 .omap4 = {
292 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
293 },
294 },
295};
296
077c42f7
M		 297/*
298 * 'gmac' class
299 * cpsw/gmac sub system
300 */
301static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
302 .rev_offs = 0x0,
303 .sysc_offs = 0x8,
304 .syss_offs = 0x4,
305 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
306 SYSS_HAS_RESET_STATUS),
307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
308 MSTANDBY_NO),
309 .sysc_fields = &omap_hwmod_sysc_type3,
310};
311
312static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
313 .name = "gmac",
314 .sysc = &dra7xx_gmac_sysc,
315};
316
317static struct omap_hwmod dra7xx_gmac_hwmod = {
318 .name = "gmac",
319 .class = &dra7xx_gmac_hwmod_class,
320 .clkdm_name = "gmac_clkdm",
321 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
322 .main_clk = "dpll_gmac_ck",
323 .mpu_rt_idx = 1,
324 .prcm = {
325 .omap4 = {
326 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
327 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
328 .modulemode = MODULEMODE_SWCTRL,
329 },
330 },
331};
332
333/*
334 * 'mdio' class
335 */
336static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
337 .name = "davinci_mdio",
338};
339
340static struct omap_hwmod dra7xx_mdio_hwmod = {
341 .name = "davinci_mdio",
342 .class = &dra7xx_mdio_hwmod_class,
343 .clkdm_name = "gmac_clkdm",
344 .main_clk = "dpll_gmac_ck",
345};
346
90020c7b
A		 347/*
348 * 'dcan' class
349 *
350 */
351
352static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
353 .name = "dcan",
354};
355
356/* dcan1 */
357static struct omap_hwmod dra7xx_dcan1_hwmod = {
358 .name = "dcan1",
359 .class = &dra7xx_dcan_hwmod_class,
360 .clkdm_name = "wkupaon_clkdm",
361 .main_clk = "dcan1_sys_clk_mux",
362 .prcm = {
363 .omap4 = {
364 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
365 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
366 .modulemode = MODULEMODE_SWCTRL,
367 },
368 },
369};
370
371/* dcan2 */
372static struct omap_hwmod dra7xx_dcan2_hwmod = {
373 .name = "dcan2",
374 .class = &dra7xx_dcan_hwmod_class,
375 .clkdm_name = "l4per2_clkdm",
376 .main_clk = "sys_clkin1",
377 .prcm = {
378 .omap4 = {
379 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
380 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
381 .modulemode = MODULEMODE_SWCTRL,
382 },
383 },
384};
385
386/*
387 * 'dma' class
388 *
389 */
390
391static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
392 .rev_offs = 0x0000,
393 .sysc_offs = 0x002c,
394 .syss_offs = 0x0028,
395 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
396 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
397 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
398 SYSS_HAS_RESET_STATUS),
399 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
400 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
401 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
402 .sysc_fields = &omap_hwmod_sysc_type1,
403};
404
405static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
406 .name = "dma",
407 .sysc = &dra7xx_dma_sysc,
408};
409
410/* dma dev_attr */
411static struct omap_dma_dev_attr dma_dev_attr = {
412 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
413 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
414 .lch_count = 32,
415};
416
417/* dma_system */
90020c7b
A		 418static struct omap_hwmod dra7xx_dma_system_hwmod = {
419 .name = "dma_system",
420 .class = &dra7xx_dma_hwmod_class,
421 .clkdm_name = "dma_clkdm",
90020c7b
A		 422 .main_clk = "l3_iclk_div",
423 .prcm = {
424 .omap4 = {
425 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
426 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
427 },
428 },
429 .dev_attr = &dma_dev_attr,
430};
431
432/*
433 * 'dss' class
434 *
435 */
436
437static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
438 .rev_offs = 0x0000,
439 .syss_offs = 0x0014,
440 .sysc_flags = SYSS_HAS_RESET_STATUS,
441};
442
443static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
444 .name = "dss",
445 .sysc = &dra7xx_dss_sysc,
446 .reset = omap_dss_reset,
447};
448
449/* dss */
450static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
451 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
452 { .dma_req = -1 }
453};
454
455static struct omap_hwmod_opt_clk dss_opt_clks[] = {
456 { .role = "dss_clk", .clk = "dss_dss_clk" },
457 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
458 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
459 { .role = "video2_clk", .clk = "dss_video2_clk" },
460 { .role = "video1_clk", .clk = "dss_video1_clk" },
461 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
2d5a3c80 462 { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
90020c7b
A		 463};
464
465static struct omap_hwmod dra7xx_dss_hwmod = {
466 .name = "dss_core",
467 .class = &dra7xx_dss_hwmod_class,
468 .clkdm_name = "dss_clkdm",
469 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
470 .sdma_reqs = dra7xx_dss_sdma_reqs,
471 .main_clk = "dss_dss_clk",
472 .prcm = {
473 .omap4 = {
474 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
475 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
476 .modulemode = MODULEMODE_SWCTRL,
477 },
478 },
479 .opt_clks = dss_opt_clks,
480 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
481};
482
483/*
484 * 'dispc' class
485 * display controller
486 */
487
488static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
489 .rev_offs = 0x0000,
490 .sysc_offs = 0x0010,
491 .syss_offs = 0x0014,
492 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
493 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
494 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
495 SYSS_HAS_RESET_STATUS),
496 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
497 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
498 .sysc_fields = &omap_hwmod_sysc_type1,
499};
500
501static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
502 .name = "dispc",
503 .sysc = &dra7xx_dispc_sysc,
504};
505
506/* dss_dispc */
507/* dss_dispc dev_attr */
508static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
509 .has_framedonetv_irq = 1,
510 .manager_count = 4,
511};
512
513static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
514 .name = "dss_dispc",
515 .class = &dra7xx_dispc_hwmod_class,
516 .clkdm_name = "dss_clkdm",
517 .main_clk = "dss_dss_clk",
518 .prcm = {
519 .omap4 = {
520 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
521 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
522 },
523 },
524 .dev_attr = &dss_dispc_dev_attr,
a3818c6d 525 .parent_hwmod = &dra7xx_dss_hwmod,
90020c7b
A		 526};
527
528/*
529 * 'hdmi' class
530 * hdmi controller
531 */
532
533static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
534 .rev_offs = 0x0000,
535 .sysc_offs = 0x0010,
536 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
537 SYSC_HAS_SOFTRESET),
538 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
539 SIDLE_SMART_WKUP),
540 .sysc_fields = &omap_hwmod_sysc_type2,
541};
542
543static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
544 .name = "hdmi",
545 .sysc = &dra7xx_hdmi_sysc,
546};
547
548/* dss_hdmi */
549
550static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
551 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
552};
553
554static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
555 .name = "dss_hdmi",
556 .class = &dra7xx_hdmi_hwmod_class,
557 .clkdm_name = "dss_clkdm",
558 .main_clk = "dss_48mhz_clk",
559 .prcm = {
560 .omap4 = {
561 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
562 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
563 },
564 },
565 .opt_clks = dss_hdmi_opt_clks,
566 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
a3818c6d 567 .parent_hwmod = &dra7xx_dss_hwmod,
90020c7b
A		 568};
569
570/*
571 * 'elm' class
572 *
573 */
574
575static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
576 .rev_offs = 0x0000,
577 .sysc_offs = 0x0010,
578 .syss_offs = 0x0014,
579 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
580 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
581 SYSS_HAS_RESET_STATUS),
582 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
583 SIDLE_SMART_WKUP),
584 .sysc_fields = &omap_hwmod_sysc_type1,
585};
586
587static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
588 .name = "elm",
589 .sysc = &dra7xx_elm_sysc,
590};
591
592/* elm */
593
594static struct omap_hwmod dra7xx_elm_hwmod = {
595 .name = "elm",
596 .class = &dra7xx_elm_hwmod_class,
597 .clkdm_name = "l4per_clkdm",
598 .main_clk = "l3_iclk_div",
599 .prcm = {
600 .omap4 = {
601 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
602 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
603 },
604 },
605};
606
607/*
608 * 'gpio' class
609 *
610 */
611
612static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
613 .rev_offs = 0x0000,
614 .sysc_offs = 0x0010,
615 .syss_offs = 0x0114,
616 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
617 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
618 SYSS_HAS_RESET_STATUS),
619 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
620 SIDLE_SMART_WKUP),
621 .sysc_fields = &omap_hwmod_sysc_type1,
622};
623
624static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
625 .name = "gpio",
626 .sysc = &dra7xx_gpio_sysc,
627 .rev = 2,
628};
629
630/* gpio dev_attr */
631static struct omap_gpio_dev_attr gpio_dev_attr = {
632 .bank_width = 32,
633 .dbck_flag = true,
634};
635
636/* gpio1 */
637static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
638 { .role = "dbclk", .clk = "gpio1_dbclk" },
639};
640
641static struct omap_hwmod dra7xx_gpio1_hwmod = {
642 .name = "gpio1",
643 .class = &dra7xx_gpio_hwmod_class,
644 .clkdm_name = "wkupaon_clkdm",
645 .main_clk = "wkupaon_iclk_mux",
646 .prcm = {
647 .omap4 = {
648 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
649 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
650 .modulemode = MODULEMODE_HWCTRL,
651 },
652 },
653 .opt_clks = gpio1_opt_clks,
654 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
655 .dev_attr = &gpio_dev_attr,
656};
657
658/* gpio2 */
659static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
660 { .role = "dbclk", .clk = "gpio2_dbclk" },
661};
662
663static struct omap_hwmod dra7xx_gpio2_hwmod = {
664 .name = "gpio2",
665 .class = &dra7xx_gpio_hwmod_class,
666 .clkdm_name = "l4per_clkdm",
667 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
668 .main_clk = "l3_iclk_div",
669 .prcm = {
670 .omap4 = {
671 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
672 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
673 .modulemode = MODULEMODE_HWCTRL,
674 },
675 },
676 .opt_clks = gpio2_opt_clks,
677 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
678 .dev_attr = &gpio_dev_attr,
679};
680
681/* gpio3 */
682static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
683 { .role = "dbclk", .clk = "gpio3_dbclk" },
684};
685
686static struct omap_hwmod dra7xx_gpio3_hwmod = {
687 .name = "gpio3",
688 .class = &dra7xx_gpio_hwmod_class,
689 .clkdm_name = "l4per_clkdm",
690 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
691 .main_clk = "l3_iclk_div",
692 .prcm = {
693 .omap4 = {
694 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
695 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
696 .modulemode = MODULEMODE_HWCTRL,
697 },
698 },
699 .opt_clks = gpio3_opt_clks,
700 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
701 .dev_attr = &gpio_dev_attr,
702};
703
704/* gpio4 */
705static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
706 { .role = "dbclk", .clk = "gpio4_dbclk" },
707};
708
709static struct omap_hwmod dra7xx_gpio4_hwmod = {
710 .name = "gpio4",
711 .class = &dra7xx_gpio_hwmod_class,
712 .clkdm_name = "l4per_clkdm",
713 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
714 .main_clk = "l3_iclk_div",
715 .prcm = {
716 .omap4 = {
717 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
718 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
719 .modulemode = MODULEMODE_HWCTRL,
720 },
721 },
722 .opt_clks = gpio4_opt_clks,
723 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
724 .dev_attr = &gpio_dev_attr,
725};
726
727/* gpio5 */
728static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
729 { .role = "dbclk", .clk = "gpio5_dbclk" },
730};
731
732static struct omap_hwmod dra7xx_gpio5_hwmod = {
733 .name = "gpio5",
734 .class = &dra7xx_gpio_hwmod_class,
735 .clkdm_name = "l4per_clkdm",
736 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
737 .main_clk = "l3_iclk_div",
738 .prcm = {
739 .omap4 = {
740 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
741 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
742 .modulemode = MODULEMODE_HWCTRL,
743 },
744 },
745 .opt_clks = gpio5_opt_clks,
746 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
747 .dev_attr = &gpio_dev_attr,
748};
749
750/* gpio6 */
751static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
752 { .role = "dbclk", .clk = "gpio6_dbclk" },
753};
754
755static struct omap_hwmod dra7xx_gpio6_hwmod = {
756 .name = "gpio6",
757 .class = &dra7xx_gpio_hwmod_class,
758 .clkdm_name = "l4per_clkdm",
759 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
760 .main_clk = "l3_iclk_div",
761 .prcm = {
762 .omap4 = {
763 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
764 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
765 .modulemode = MODULEMODE_HWCTRL,
766 },
767 },
768 .opt_clks = gpio6_opt_clks,
769 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
770 .dev_attr = &gpio_dev_attr,
771};
772
773/* gpio7 */
774static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
775 { .role = "dbclk", .clk = "gpio7_dbclk" },
776};
777
778static struct omap_hwmod dra7xx_gpio7_hwmod = {
779 .name = "gpio7",
780 .class = &dra7xx_gpio_hwmod_class,
781 .clkdm_name = "l4per_clkdm",
782 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
783 .main_clk = "l3_iclk_div",
784 .prcm = {
785 .omap4 = {
786 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
787 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
788 .modulemode = MODULEMODE_HWCTRL,
789 },
790 },
791 .opt_clks = gpio7_opt_clks,
792 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
793 .dev_attr = &gpio_dev_attr,
794};
795
796/* gpio8 */
797static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
798 { .role = "dbclk", .clk = "gpio8_dbclk" },
799};
800
801static struct omap_hwmod dra7xx_gpio8_hwmod = {
802 .name = "gpio8",
803 .class = &dra7xx_gpio_hwmod_class,
804 .clkdm_name = "l4per_clkdm",
805 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
806 .main_clk = "l3_iclk_div",
807 .prcm = {
808 .omap4 = {
809 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
810 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
811 .modulemode = MODULEMODE_HWCTRL,
812 },
813 },
814 .opt_clks = gpio8_opt_clks,
815 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
816 .dev_attr = &gpio_dev_attr,
817};
818
819/*
820 * 'gpmc' class
821 *
822 */
823
824static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
825 .rev_offs = 0x0000,
826 .sysc_offs = 0x0010,
827 .syss_offs = 0x0014,
828 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
829 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
91a57731 830 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
90020c7b
A		 831 .sysc_fields = &omap_hwmod_sysc_type1,
832};
833
834static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
835 .name = "gpmc",
836 .sysc = &dra7xx_gpmc_sysc,
837};
838
839/* gpmc */
840
841static struct omap_hwmod dra7xx_gpmc_hwmod = {
842 .name = "gpmc",
843 .class = &dra7xx_gpmc_hwmod_class,
844 .clkdm_name = "l3main1_clkdm",
63aa945b 845 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
91a57731 846 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
90020c7b
A		 847 .main_clk = "l3_iclk_div",
848 .prcm = {
849 .omap4 = {
850 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
851 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
852 .modulemode = MODULEMODE_HWCTRL,
853 },
854 },
855};
856
857/*
858 * 'hdq1w' class
859 *
860 */
861
862static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
863 .rev_offs = 0x0000,
864 .sysc_offs = 0x0014,
865 .syss_offs = 0x0018,
866 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
867 SYSS_HAS_RESET_STATUS),
868 .sysc_fields = &omap_hwmod_sysc_type1,
869};
870
871static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
872 .name = "hdq1w",
873 .sysc = &dra7xx_hdq1w_sysc,
874};
875
876/* hdq1w */
877
878static struct omap_hwmod dra7xx_hdq1w_hwmod = {
879 .name = "hdq1w",
880 .class = &dra7xx_hdq1w_hwmod_class,
881 .clkdm_name = "l4per_clkdm",
882 .flags = HWMOD_INIT_NO_RESET,
883 .main_clk = "func_12m_fclk",
884 .prcm = {
885 .omap4 = {
886 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
887 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
888 .modulemode = MODULEMODE_SWCTRL,
889 },
890 },
891};
892
893/*
894 * 'i2c' class
895 *
896 */
897
898static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
899 .sysc_offs = 0x0010,
900 .syss_offs = 0x0090,
901 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
902 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
903 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
904 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
905 SIDLE_SMART_WKUP),
906 .clockact = CLOCKACT_TEST_ICLK,
907 .sysc_fields = &omap_hwmod_sysc_type1,
908};
909
910static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
911 .name = "i2c",
912 .sysc = &dra7xx_i2c_sysc,
913 .reset = &omap_i2c_reset,
914 .rev = OMAP_I2C_IP_VERSION_2,
915};
916
917/* i2c dev_attr */
918static struct omap_i2c_dev_attr i2c_dev_attr = {
919 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
920};
921
922/* i2c1 */
923static struct omap_hwmod dra7xx_i2c1_hwmod = {
924 .name = "i2c1",
925 .class = &dra7xx_i2c_hwmod_class,
926 .clkdm_name = "l4per_clkdm",
927 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
928 .main_clk = "func_96m_fclk",
929 .prcm = {
930 .omap4 = {
931 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
932 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
933 .modulemode = MODULEMODE_SWCTRL,
934 },
935 },
936 .dev_attr = &i2c_dev_attr,
937};
938
939/* i2c2 */
940static struct omap_hwmod dra7xx_i2c2_hwmod = {
941 .name = "i2c2",
942 .class = &dra7xx_i2c_hwmod_class,
943 .clkdm_name = "l4per_clkdm",
944 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
945 .main_clk = "func_96m_fclk",
946 .prcm = {
947 .omap4 = {
948 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
949 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
950 .modulemode = MODULEMODE_SWCTRL,
951 },
952 },
953 .dev_attr = &i2c_dev_attr,
954};
955
956/* i2c3 */
957static struct omap_hwmod dra7xx_i2c3_hwmod = {
958 .name = "i2c3",
959 .class = &dra7xx_i2c_hwmod_class,
960 .clkdm_name = "l4per_clkdm",
961 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
962 .main_clk = "func_96m_fclk",
963 .prcm = {
964 .omap4 = {
965 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
966 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
967 .modulemode = MODULEMODE_SWCTRL,
968 },
969 },
970 .dev_attr = &i2c_dev_attr,
971};
972
973/* i2c4 */
974static struct omap_hwmod dra7xx_i2c4_hwmod = {
975 .name = "i2c4",
976 .class = &dra7xx_i2c_hwmod_class,
977 .clkdm_name = "l4per_clkdm",
978 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
979 .main_clk = "func_96m_fclk",
980 .prcm = {
981 .omap4 = {
982 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
983 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
984 .modulemode = MODULEMODE_SWCTRL,
985 },
986 },
987 .dev_attr = &i2c_dev_attr,
988};
989
990/* i2c5 */
991static struct omap_hwmod dra7xx_i2c5_hwmod = {
992 .name = "i2c5",
993 .class = &dra7xx_i2c_hwmod_class,
994 .clkdm_name = "ipu_clkdm",
995 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
996 .main_clk = "func_96m_fclk",
997 .prcm = {
998 .omap4 = {
999 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1000 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1001 .modulemode = MODULEMODE_SWCTRL,
1002 },
1003 },
1004 .dev_attr = &i2c_dev_attr,
1005};
1006
067395d4
SA		 1007/*
1008 * 'mailbox' class
1009 *
1010 */
1011
1012static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1013 .rev_offs = 0x0000,
1014 .sysc_offs = 0x0010,
1015 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1016 SYSC_HAS_SOFTRESET),
1017 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1018 .sysc_fields = &omap_hwmod_sysc_type2,
1019};
1020
1021static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1022 .name = "mailbox",
1023 .sysc = &dra7xx_mailbox_sysc,
1024};
1025
1026/* mailbox1 */
1027static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1028 .name = "mailbox1",
1029 .class = &dra7xx_mailbox_hwmod_class,
1030 .clkdm_name = "l4cfg_clkdm",
1031 .prcm = {
1032 .omap4 = {
1033 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1034 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1035 },
1036 },
1037};
1038
1039/* mailbox2 */
1040static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1041 .name = "mailbox2",
1042 .class = &dra7xx_mailbox_hwmod_class,
1043 .clkdm_name = "l4cfg_clkdm",
1044 .prcm = {
1045 .omap4 = {
1046 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1047 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1048 },
1049 },
1050};
1051
1052/* mailbox3 */
1053static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1054 .name = "mailbox3",
1055 .class = &dra7xx_mailbox_hwmod_class,
1056 .clkdm_name = "l4cfg_clkdm",
1057 .prcm = {
1058 .omap4 = {
1059 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1060 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1061 },
1062 },
1063};
1064
1065/* mailbox4 */
1066static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1067 .name = "mailbox4",
1068 .class = &dra7xx_mailbox_hwmod_class,
1069 .clkdm_name = "l4cfg_clkdm",
1070 .prcm = {
1071 .omap4 = {
1072 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1073 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1074 },
1075 },
1076};
1077
1078/* mailbox5 */
1079static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1080 .name = "mailbox5",
1081 .class = &dra7xx_mailbox_hwmod_class,
1082 .clkdm_name = "l4cfg_clkdm",
1083 .prcm = {
1084 .omap4 = {
1085 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1086 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1087 },
1088 },
1089};
1090
1091/* mailbox6 */
1092static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1093 .name = "mailbox6",
1094 .class = &dra7xx_mailbox_hwmod_class,
1095 .clkdm_name = "l4cfg_clkdm",
1096 .prcm = {
1097 .omap4 = {
1098 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1099 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1100 },
1101 },
1102};
1103
1104/* mailbox7 */
1105static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1106 .name = "mailbox7",
1107 .class = &dra7xx_mailbox_hwmod_class,
1108 .clkdm_name = "l4cfg_clkdm",
1109 .prcm = {
1110 .omap4 = {
1111 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1112 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1113 },
1114 },
1115};
1116
1117/* mailbox8 */
1118static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1119 .name = "mailbox8",
1120 .class = &dra7xx_mailbox_hwmod_class,
1121 .clkdm_name = "l4cfg_clkdm",
1122 .prcm = {
1123 .omap4 = {
1124 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1125 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1126 },
1127 },
1128};
1129
1130/* mailbox9 */
1131static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1132 .name = "mailbox9",
1133 .class = &dra7xx_mailbox_hwmod_class,
1134 .clkdm_name = "l4cfg_clkdm",
1135 .prcm = {
1136 .omap4 = {
1137 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1138 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1139 },
1140 },
1141};
1142
1143/* mailbox10 */
1144static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1145 .name = "mailbox10",
1146 .class = &dra7xx_mailbox_hwmod_class,
1147 .clkdm_name = "l4cfg_clkdm",
1148 .prcm = {
1149 .omap4 = {
1150 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1151 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1152 },
1153 },
1154};
1155
1156/* mailbox11 */
1157static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1158 .name = "mailbox11",
1159 .class = &dra7xx_mailbox_hwmod_class,
1160 .clkdm_name = "l4cfg_clkdm",
1161 .prcm = {
1162 .omap4 = {
1163 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1164 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1165 },
1166 },
1167};
1168
1169/* mailbox12 */
1170static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1171 .name = "mailbox12",
1172 .class = &dra7xx_mailbox_hwmod_class,
1173 .clkdm_name = "l4cfg_clkdm",
1174 .prcm = {
1175 .omap4 = {
1176 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1177 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1178 },
1179 },
1180};
1181
1182/* mailbox13 */
1183static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1184 .name = "mailbox13",
1185 .class = &dra7xx_mailbox_hwmod_class,
1186 .clkdm_name = "l4cfg_clkdm",
1187 .prcm = {
1188 .omap4 = {
1189 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1190 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1191 },
1192 },
1193};
1194
90020c7b
A		 1195/*
1196 * 'mcspi' class
1197 *
1198 */
1199
1200static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1201 .rev_offs = 0x0000,
1202 .sysc_offs = 0x0010,
1203 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1204 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1205 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1206 SIDLE_SMART_WKUP),
1207 .sysc_fields = &omap_hwmod_sysc_type2,
1208};
1209
1210static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1211 .name = "mcspi",
1212 .sysc = &dra7xx_mcspi_sysc,
1213 .rev = OMAP4_MCSPI_REV,
1214};
1215
1216/* mcspi1 */
1217/* mcspi1 dev_attr */
1218static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1219 .num_chipselect = 4,
1220};
1221
1222static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1223 .name = "mcspi1",
1224 .class = &dra7xx_mcspi_hwmod_class,
1225 .clkdm_name = "l4per_clkdm",
1226 .main_clk = "func_48m_fclk",
1227 .prcm = {
1228 .omap4 = {
1229 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1230 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1231 .modulemode = MODULEMODE_SWCTRL,
1232 },
1233 },
1234 .dev_attr = &mcspi1_dev_attr,
1235};
1236
1237/* mcspi2 */
1238/* mcspi2 dev_attr */
1239static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1240 .num_chipselect = 2,
1241};
1242
1243static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1244 .name = "mcspi2",
1245 .class = &dra7xx_mcspi_hwmod_class,
1246 .clkdm_name = "l4per_clkdm",
1247 .main_clk = "func_48m_fclk",
1248 .prcm = {
1249 .omap4 = {
1250 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1251 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1252 .modulemode = MODULEMODE_SWCTRL,
1253 },
1254 },
1255 .dev_attr = &mcspi2_dev_attr,
1256};
1257
1258/* mcspi3 */
1259/* mcspi3 dev_attr */
1260static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1261 .num_chipselect = 2,
1262};
1263
1264static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1265 .name = "mcspi3",
1266 .class = &dra7xx_mcspi_hwmod_class,
1267 .clkdm_name = "l4per_clkdm",
1268 .main_clk = "func_48m_fclk",
1269 .prcm = {
1270 .omap4 = {
1271 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1272 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1273 .modulemode = MODULEMODE_SWCTRL,
1274 },
1275 },
1276 .dev_attr = &mcspi3_dev_attr,
1277};
1278
1279/* mcspi4 */
1280/* mcspi4 dev_attr */
1281static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1282 .num_chipselect = 1,
1283};
1284
1285static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1286 .name = "mcspi4",
1287 .class = &dra7xx_mcspi_hwmod_class,
1288 .clkdm_name = "l4per_clkdm",
1289 .main_clk = "func_48m_fclk",
1290 .prcm = {
1291 .omap4 = {
1292 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1293 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1294 .modulemode = MODULEMODE_SWCTRL,
1295 },
1296 },
1297 .dev_attr = &mcspi4_dev_attr,
1298};
1299
469689a4
PU		 1300/*
1301 * 'mcasp' class
1302 *
1303 */
1304static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1305 .sysc_offs = 0x0004,
1306 .sysc_flags = SYSC_HAS_SIDLEMODE,
1307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1308 .sysc_fields = &omap_hwmod_sysc_type3,
1309};
1310
1311static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1312 .name = "mcasp",
1313 .sysc = &dra7xx_mcasp_sysc,
1314};
1315
1316/* mcasp3 */
1317static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
1318 { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
1319};
1320
1321static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1322 .name = "mcasp3",
1323 .class = &dra7xx_mcasp_hwmod_class,
1324 .clkdm_name = "l4per2_clkdm",
1325 .main_clk = "mcasp3_aux_gfclk_mux",
1326 .flags = HWMOD_OPT_CLKS_NEEDED,
1327 .prcm = {
1328 .omap4 = {
1329 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1330 .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1331 .modulemode = MODULEMODE_SWCTRL,
1332 },
1333 },
1334 .opt_clks = mcasp3_opt_clks,
1335 .opt_clks_cnt = ARRAY_SIZE(mcasp3_opt_clks),
1336};
1337
90020c7b
A		 1338/*
1339 * 'mmc' class
1340 *
1341 */
1342
1343static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1344 .rev_offs = 0x0000,
1345 .sysc_offs = 0x0010,
1346 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1347 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1348 SYSC_HAS_SOFTRESET),
1349 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1350 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1351 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1352 .sysc_fields = &omap_hwmod_sysc_type2,
1353};
1354
1355static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1356 .name = "mmc",
1357 .sysc = &dra7xx_mmc_sysc,
1358};
1359
1360/* mmc1 */
1361static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1362 { .role = "clk32k", .clk = "mmc1_clk32k" },
1363};
1364
1365/* mmc1 dev_attr */
55143438 1366static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
90020c7b
A		 1367 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1368};
1369
1370static struct omap_hwmod dra7xx_mmc1_hwmod = {
1371 .name = "mmc1",
1372 .class = &dra7xx_mmc_hwmod_class,
1373 .clkdm_name = "l3init_clkdm",
1374 .main_clk = "mmc1_fclk_div",
1375 .prcm = {
1376 .omap4 = {
1377 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1378 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1379 .modulemode = MODULEMODE_SWCTRL,
1380 },
1381 },
1382 .opt_clks = mmc1_opt_clks,
1383 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1384 .dev_attr = &mmc1_dev_attr,
1385};
1386
1387/* mmc2 */
1388static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1389 { .role = "clk32k", .clk = "mmc2_clk32k" },
1390};
1391
1392static struct omap_hwmod dra7xx_mmc2_hwmod = {
1393 .name = "mmc2",
1394 .class = &dra7xx_mmc_hwmod_class,
1395 .clkdm_name = "l3init_clkdm",
1396 .main_clk = "mmc2_fclk_div",
1397 .prcm = {
1398 .omap4 = {
1399 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1400 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1401 .modulemode = MODULEMODE_SWCTRL,
1402 },
1403 },
1404 .opt_clks = mmc2_opt_clks,
1405 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1406};
1407
1408/* mmc3 */
1409static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1410 { .role = "clk32k", .clk = "mmc3_clk32k" },
1411};
1412
1413static struct omap_hwmod dra7xx_mmc3_hwmod = {
1414 .name = "mmc3",
1415 .class = &dra7xx_mmc_hwmod_class,
1416 .clkdm_name = "l4per_clkdm",
1417 .main_clk = "mmc3_gfclk_div",
1418 .prcm = {
1419 .omap4 = {
1420 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1421 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1422 .modulemode = MODULEMODE_SWCTRL,
1423 },
1424 },
1425 .opt_clks = mmc3_opt_clks,
1426 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1427};
1428
1429/* mmc4 */
1430static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1431 { .role = "clk32k", .clk = "mmc4_clk32k" },
1432};
1433
1434static struct omap_hwmod dra7xx_mmc4_hwmod = {
1435 .name = "mmc4",
1436 .class = &dra7xx_mmc_hwmod_class,
1437 .clkdm_name = "l4per_clkdm",
1438 .main_clk = "mmc4_gfclk_div",
1439 .prcm = {
1440 .omap4 = {
1441 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1442 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1443 .modulemode = MODULEMODE_SWCTRL,
1444 },
1445 },
1446 .opt_clks = mmc4_opt_clks,
1447 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1448};
1449
1450/*
1451 * 'mpu' class
1452 *
1453 */
1454
1455static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1456 .name = "mpu",
1457};
1458
1459/* mpu */
1460static struct omap_hwmod dra7xx_mpu_hwmod = {
1461 .name = "mpu",
1462 .class = &dra7xx_mpu_hwmod_class,
1463 .clkdm_name = "mpu_clkdm",
1464 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1465 .main_clk = "dpll_mpu_m2_ck",
1466 .prcm = {
1467 .omap4 = {
1468 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1469 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1470 },
1471 },
1472};
1473
1474/*
1475 * 'ocp2scp' class
1476 *
1477 */
1478
1479static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1480 .rev_offs = 0x0000,
1481 .sysc_offs = 0x0010,
1482 .syss_offs = 0x0014,
1483 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1484 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4965be1f 1485 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
90020c7b
A		 1486 .sysc_fields = &omap_hwmod_sysc_type1,
1487};
1488
1489static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1490 .name = "ocp2scp",
1491 .sysc = &dra7xx_ocp2scp_sysc,
1492};
1493
1494/* ocp2scp1 */
1495static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1496 .name = "ocp2scp1",
1497 .class = &dra7xx_ocp2scp_hwmod_class,
1498 .clkdm_name = "l3init_clkdm",
1499 .main_clk = "l4_root_clk_div",
1500 .prcm = {
1501 .omap4 = {
1502 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1503 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1504 .modulemode = MODULEMODE_HWCTRL,
1505 },
1506 },
1507};
1508
df0d0f11
RQ		 1509/* ocp2scp3 */
1510static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1511 .name = "ocp2scp3",
1512 .class = &dra7xx_ocp2scp_hwmod_class,
1513 .clkdm_name = "l3init_clkdm",
1514 .main_clk = "l4_root_clk_div",
1515 .prcm = {
1516 .omap4 = {
1517 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1518 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1519 .modulemode = MODULEMODE_HWCTRL,
1520 },
1521 },
1522};
1523
8dd3eb71
KVA		 1524/*
1525 * 'PCIE' class
1526 *
1527 */
1528
1c96bee4
SN		 1529/*
1530 * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
1531 * functionality of OMAP HWMOD layer does not deassert the hardreset lines
1532 * associated with an IP automatically leaving the driver to handle that
1533 * by itself. This does not work for PCIeSS which needs the reset lines
1534 * deasserted for the driver to start accessing registers.
1535 *
1536 * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
1537 * lines after asserting them.
1538 */
1539static int dra7xx_pciess_reset(struct omap_hwmod *oh)
1540{
1541 int i;
1542
1543 for (i = 0; i < oh->rst_lines_cnt; i++) {
1544 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
1545 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
1546 }
1547
1548 return 0;
1549}
1550
0717103e 1551static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
8dd3eb71 1552 .name = "pcie",
1c96bee4 1553 .reset = dra7xx_pciess_reset,
8dd3eb71
KVA		 1554};
1555
1556/* pcie1 */
8fe097a3
KVA		 1557static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
1558 { .name = "pcie", .rst_shift = 0 },
1559};
1560
0717103e 1561static struct omap_hwmod dra7xx_pciess1_hwmod = {
8dd3eb71 1562 .name = "pcie1",
0717103e 1563 .class = &dra7xx_pciess_hwmod_class,
8dd3eb71 1564 .clkdm_name = "pcie_clkdm",
8fe097a3
KVA		 1565 .rst_lines = dra7xx_pciess1_resets,
1566 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
8dd3eb71 1567 .main_clk = "l4_root_clk_div",
70c18ef7
KVA		 1568 .prcm = {
1569 .omap4 = {
1570 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
8fe097a3 1571 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
70c18ef7
KVA		 1572 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1573 .modulemode = MODULEMODE_SWCTRL,
1574 },
1575 },
1576};
1577
8fe097a3
KVA		 1578/* pcie2 */
1579static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
1580 { .name = "pcie", .rst_shift = 1 },
1581};
1582
0717103e
KVA		 1583/* pcie2 */
1584static struct omap_hwmod dra7xx_pciess2_hwmod = {
1585 .name = "pcie2",
1586 .class = &dra7xx_pciess_hwmod_class,
1587 .clkdm_name = "pcie_clkdm",
8fe097a3
KVA		 1588 .rst_lines = dra7xx_pciess2_resets,
1589 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
70c18ef7
KVA		 1590 .main_clk = "l4_root_clk_div",
1591 .prcm = {
1592 .omap4 = {
1593 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
8fe097a3 1594 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
70c18ef7
KVA		 1595 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1596 .modulemode = MODULEMODE_SWCTRL,
1597 },
1598 },
1599};
1600
90020c7b
A		 1601/*
1602 * 'qspi' class
1603 *
1604 */
1605
1606static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1607 .sysc_offs = 0x0010,
1608 .sysc_flags = SYSC_HAS_SIDLEMODE,
1609 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1610 SIDLE_SMART_WKUP),
1611 .sysc_fields = &omap_hwmod_sysc_type2,
1612};
1613
1614static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1615 .name = "qspi",
1616 .sysc = &dra7xx_qspi_sysc,
1617};
1618
1619/* qspi */
1620static struct omap_hwmod dra7xx_qspi_hwmod = {
1621 .name = "qspi",
1622 .class = &dra7xx_qspi_hwmod_class,
1623 .clkdm_name = "l4per2_clkdm",
1624 .main_clk = "qspi_gfclk_div",
1625 .prcm = {
1626 .omap4 = {
1627 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1628 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1629 .modulemode = MODULEMODE_SWCTRL,
1630 },
1631 },
1632};
1633
c913c8a1
LV		 1634/*
1635 * 'rtcss' class
1636 *
1637 */
1638static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1639 .sysc_offs = 0x0078,
1640 .sysc_flags = SYSC_HAS_SIDLEMODE,
1641 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1642 SIDLE_SMART_WKUP),
1643 .sysc_fields = &omap_hwmod_sysc_type3,
1644};
1645
1646static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1647 .name = "rtcss",
1648 .sysc = &dra7xx_rtcss_sysc,
1649};
1650
1651/* rtcss */
1652static struct omap_hwmod dra7xx_rtcss_hwmod = {
1653 .name = "rtcss",
1654 .class = &dra7xx_rtcss_hwmod_class,
1655 .clkdm_name = "rtc_clkdm",
1656 .main_clk = "sys_32k_ck",
1657 .prcm = {
1658 .omap4 = {
1659 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1660 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1661 .modulemode = MODULEMODE_SWCTRL,
1662 },
1663 },
1664};
1665
90020c7b
A		 1666/*
1667 * 'sata' class
1668 *
1669 */
1670
1671static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1672 .sysc_offs = 0x0000,
1673 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1674 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1675 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1676 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1677 .sysc_fields = &omap_hwmod_sysc_type2,
1678};
1679
1680static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1681 .name = "sata",
1682 .sysc = &dra7xx_sata_sysc,
1683};
1684
1685/* sata */
90020c7b
A		 1686
1687static struct omap_hwmod dra7xx_sata_hwmod = {
1688 .name = "sata",
1689 .class = &dra7xx_sata_hwmod_class,
1690 .clkdm_name = "l3init_clkdm",
1691 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1692 .main_clk = "func_48m_fclk",
1ea0999e 1693 .mpu_rt_idx = 1,
90020c7b
A		 1694 .prcm = {
1695 .omap4 = {
1696 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1697 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1698 .modulemode = MODULEMODE_SWCTRL,
1699 },
1700 },
90020c7b
A		 1701};
1702
1703/*
1704 * 'smartreflex' class
1705 *
1706 */
1707
1708/* The IP is not compliant to type1 / type2 scheme */
1709static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1710 .sidle_shift = 24,
1711 .enwkup_shift = 26,
1712};
1713
1714static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1715 .sysc_offs = 0x0038,
1716 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1717 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1718 SIDLE_SMART_WKUP),
1719 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1720};
1721
1722static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1723 .name = "smartreflex",
1724 .sysc = &dra7xx_smartreflex_sysc,
1725 .rev = 2,
1726};
1727
1728/* smartreflex_core */
1729/* smartreflex_core dev_attr */
1730static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1731 .sensor_voltdm_name = "core",
1732};
1733
1734static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1735 .name = "smartreflex_core",
1736 .class = &dra7xx_smartreflex_hwmod_class,
1737 .clkdm_name = "coreaon_clkdm",
1738 .main_clk = "wkupaon_iclk_mux",
1739 .prcm = {
1740 .omap4 = {
1741 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1742 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1743 .modulemode = MODULEMODE_SWCTRL,
1744 },
1745 },
1746 .dev_attr = &smartreflex_core_dev_attr,
1747};
1748
1749/* smartreflex_mpu */
1750/* smartreflex_mpu dev_attr */
1751static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1752 .sensor_voltdm_name = "mpu",
1753};
1754
1755static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1756 .name = "smartreflex_mpu",
1757 .class = &dra7xx_smartreflex_hwmod_class,
1758 .clkdm_name = "coreaon_clkdm",
1759 .main_clk = "wkupaon_iclk_mux",
1760 .prcm = {
1761 .omap4 = {
1762 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1763 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1764 .modulemode = MODULEMODE_SWCTRL,
1765 },
1766 },
1767 .dev_attr = &smartreflex_mpu_dev_attr,
1768};
1769
1770/*
1771 * 'spinlock' class
1772 *
1773 */
1774
1775static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1776 .rev_offs = 0x0000,
1777 .sysc_offs = 0x0010,
1778 .syss_offs = 0x0014,
c317d0f2
SA		 1779 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1780 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1781 SYSS_HAS_RESET_STATUS),
1782 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
90020c7b
A		 1783 .sysc_fields = &omap_hwmod_sysc_type1,
1784};
1785
1786static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1787 .name = "spinlock",
1788 .sysc = &dra7xx_spinlock_sysc,
1789};
1790
1791/* spinlock */
1792static struct omap_hwmod dra7xx_spinlock_hwmod = {
1793 .name = "spinlock",
1794 .class = &dra7xx_spinlock_hwmod_class,
1795 .clkdm_name = "l4cfg_clkdm",
1796 .main_clk = "l3_iclk_div",
1797 .prcm = {
1798 .omap4 = {
1799 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1800 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1801 },
1802 },
1803};
1804
1805/*
1806 * 'timer' class
1807 *
1808 * This class contains several variants: ['timer_1ms', 'timer_secure',
1809 * 'timer']
1810 */
1811
1812static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1813 .rev_offs = 0x0000,
1814 .sysc_offs = 0x0010,
1815 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1816 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1817 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1818 SIDLE_SMART_WKUP),
1819 .sysc_fields = &omap_hwmod_sysc_type2,
1820};
1821
1822static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1823 .name = "timer",
1824 .sysc = &dra7xx_timer_1ms_sysc,
1825};
1826
90020c7b
A		 1827static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1828 .rev_offs = 0x0000,
1829 .sysc_offs = 0x0010,
1830 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1831 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1832 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1833 SIDLE_SMART_WKUP),
1834 .sysc_fields = &omap_hwmod_sysc_type2,
1835};
1836
1837static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1838 .name = "timer",
1839 .sysc = &dra7xx_timer_sysc,
1840};
1841
1842/* timer1 */
1843static struct omap_hwmod dra7xx_timer1_hwmod = {
1844 .name = "timer1",
1845 .class = &dra7xx_timer_1ms_hwmod_class,
1846 .clkdm_name = "wkupaon_clkdm",
1847 .main_clk = "timer1_gfclk_mux",
1848 .prcm = {
1849 .omap4 = {
1850 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1851 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1852 .modulemode = MODULEMODE_SWCTRL,
1853 },
1854 },
1855};
1856
1857/* timer2 */
1858static struct omap_hwmod dra7xx_timer2_hwmod = {
1859 .name = "timer2",
1860 .class = &dra7xx_timer_1ms_hwmod_class,
1861 .clkdm_name = "l4per_clkdm",
1862 .main_clk = "timer2_gfclk_mux",
1863 .prcm = {
1864 .omap4 = {
1865 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1866 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1867 .modulemode = MODULEMODE_SWCTRL,
1868 },
1869 },
1870};
1871
1872/* timer3 */
1873static struct omap_hwmod dra7xx_timer3_hwmod = {
1874 .name = "timer3",
1875 .class = &dra7xx_timer_hwmod_class,
1876 .clkdm_name = "l4per_clkdm",
1877 .main_clk = "timer3_gfclk_mux",
1878 .prcm = {
1879 .omap4 = {
1880 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1881 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1882 .modulemode = MODULEMODE_SWCTRL,
1883 },
1884 },
1885};
1886
1887/* timer4 */
1888static struct omap_hwmod dra7xx_timer4_hwmod = {
1889 .name = "timer4",
edec1786 1890 .class = &dra7xx_timer_hwmod_class,
90020c7b
A		 1891 .clkdm_name = "l4per_clkdm",
1892 .main_clk = "timer4_gfclk_mux",
1893 .prcm = {
1894 .omap4 = {
1895 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1896 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1897 .modulemode = MODULEMODE_SWCTRL,
1898 },
1899 },
1900};
1901
1902/* timer5 */
1903static struct omap_hwmod dra7xx_timer5_hwmod = {
1904 .name = "timer5",
1905 .class = &dra7xx_timer_hwmod_class,
1906 .clkdm_name = "ipu_clkdm",
1907 .main_clk = "timer5_gfclk_mux",
1908 .prcm = {
1909 .omap4 = {
1910 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1911 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1912 .modulemode = MODULEMODE_SWCTRL,
1913 },
1914 },
1915};
1916
1917/* timer6 */
1918static struct omap_hwmod dra7xx_timer6_hwmod = {
1919 .name = "timer6",
1920 .class = &dra7xx_timer_hwmod_class,
1921 .clkdm_name = "ipu_clkdm",
1922 .main_clk = "timer6_gfclk_mux",
1923 .prcm = {
1924 .omap4 = {
1925 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1926 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1927 .modulemode = MODULEMODE_SWCTRL,
1928 },
1929 },
1930};
1931
1932/* timer7 */
1933static struct omap_hwmod dra7xx_timer7_hwmod = {
1934 .name = "timer7",
1935 .class = &dra7xx_timer_hwmod_class,
1936 .clkdm_name = "ipu_clkdm",
1937 .main_clk = "timer7_gfclk_mux",
1938 .prcm = {
1939 .omap4 = {
1940 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1941 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1942 .modulemode = MODULEMODE_SWCTRL,
1943 },
1944 },
1945};
1946
1947/* timer8 */
1948static struct omap_hwmod dra7xx_timer8_hwmod = {
1949 .name = "timer8",
1950 .class = &dra7xx_timer_hwmod_class,
1951 .clkdm_name = "ipu_clkdm",
1952 .main_clk = "timer8_gfclk_mux",
1953 .prcm = {
1954 .omap4 = {
1955 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1956 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1957 .modulemode = MODULEMODE_SWCTRL,
1958 },
1959 },
1960};
1961
1962/* timer9 */
1963static struct omap_hwmod dra7xx_timer9_hwmod = {
1964 .name = "timer9",
1965 .class = &dra7xx_timer_hwmod_class,
1966 .clkdm_name = "l4per_clkdm",
1967 .main_clk = "timer9_gfclk_mux",
1968 .prcm = {
1969 .omap4 = {
1970 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1971 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1972 .modulemode = MODULEMODE_SWCTRL,
1973 },
1974 },
1975};
1976
1977/* timer10 */
1978static struct omap_hwmod dra7xx_timer10_hwmod = {
1979 .name = "timer10",
1980 .class = &dra7xx_timer_1ms_hwmod_class,
1981 .clkdm_name = "l4per_clkdm",
1982 .main_clk = "timer10_gfclk_mux",
1983 .prcm = {
1984 .omap4 = {
1985 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1986 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1987 .modulemode = MODULEMODE_SWCTRL,
1988 },
1989 },
1990};
1991
1992/* timer11 */
1993static struct omap_hwmod dra7xx_timer11_hwmod = {
1994 .name = "timer11",
1995 .class = &dra7xx_timer_hwmod_class,
1996 .clkdm_name = "l4per_clkdm",
1997 .main_clk = "timer11_gfclk_mux",
1998 .prcm = {
1999 .omap4 = {
2000 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2001 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2002 .modulemode = MODULEMODE_SWCTRL,
2003 },
2004 },
2005};
2006
1ac964f4
SA		 2007/* timer13 */
2008static struct omap_hwmod dra7xx_timer13_hwmod = {
2009 .name = "timer13",
2010 .class = &dra7xx_timer_hwmod_class,
2011 .clkdm_name = "l4per3_clkdm",
2012 .main_clk = "timer13_gfclk_mux",
2013 .prcm = {
2014 .omap4 = {
2015 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
2016 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2017 .modulemode = MODULEMODE_SWCTRL,
2018 },
2019 },
2020};
2021
2022/* timer14 */
2023static struct omap_hwmod dra7xx_timer14_hwmod = {
2024 .name = "timer14",
2025 .class = &dra7xx_timer_hwmod_class,
2026 .clkdm_name = "l4per3_clkdm",
2027 .main_clk = "timer14_gfclk_mux",
2028 .prcm = {
2029 .omap4 = {
2030 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
2031 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2032 .modulemode = MODULEMODE_SWCTRL,
2033 },
2034 },
2035};
2036
2037/* timer15 */
2038static struct omap_hwmod dra7xx_timer15_hwmod = {
2039 .name = "timer15",
2040 .class = &dra7xx_timer_hwmod_class,
2041 .clkdm_name = "l4per3_clkdm",
2042 .main_clk = "timer15_gfclk_mux",
2043 .prcm = {
2044 .omap4 = {
2045 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2046 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2047 .modulemode = MODULEMODE_SWCTRL,
2048 },
2049 },
2050};
2051
2052/* timer16 */
2053static struct omap_hwmod dra7xx_timer16_hwmod = {
2054 .name = "timer16",
2055 .class = &dra7xx_timer_hwmod_class,
2056 .clkdm_name = "l4per3_clkdm",
2057 .main_clk = "timer16_gfclk_mux",
2058 .prcm = {
2059 .omap4 = {
2060 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2061 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2062 .modulemode = MODULEMODE_SWCTRL,
2063 },
2064 },
2065};
2066
90020c7b
A		 2067/*
2068 * 'uart' class
2069 *
2070 */
2071
2072static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2073 .rev_offs = 0x0050,
2074 .sysc_offs = 0x0054,
2075 .syss_offs = 0x0058,
2076 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2077 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2078 SYSS_HAS_RESET_STATUS),
2079 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2080 SIDLE_SMART_WKUP),
2081 .sysc_fields = &omap_hwmod_sysc_type1,
2082};
2083
2084static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2085 .name = "uart",
2086 .sysc = &dra7xx_uart_sysc,
2087};
2088
2089/* uart1 */
2090static struct omap_hwmod dra7xx_uart1_hwmod = {
2091 .name = "uart1",
2092 .class = &dra7xx_uart_hwmod_class,
2093 .clkdm_name = "l4per_clkdm",
2094 .main_clk = "uart1_gfclk_mux",
38958c15 2095 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
90020c7b
A		 2096 .prcm = {
2097 .omap4 = {
2098 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2099 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2100 .modulemode = MODULEMODE_SWCTRL,
2101 },
2102 },
2103};
2104
2105/* uart2 */
2106static struct omap_hwmod dra7xx_uart2_hwmod = {
2107 .name = "uart2",
2108 .class = &dra7xx_uart_hwmod_class,
2109 .clkdm_name = "l4per_clkdm",
2110 .main_clk = "uart2_gfclk_mux",
2111 .flags = HWMOD_SWSUP_SIDLE_ACT,
2112 .prcm = {
2113 .omap4 = {
2114 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2115 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2116 .modulemode = MODULEMODE_SWCTRL,
2117 },
2118 },
2119};
2120
2121/* uart3 */
2122static struct omap_hwmod dra7xx_uart3_hwmod = {
2123 .name = "uart3",
2124 .class = &dra7xx_uart_hwmod_class,
2125 .clkdm_name = "l4per_clkdm",
2126 .main_clk = "uart3_gfclk_mux",
1c7e36bf 2127 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
90020c7b
A		 2128 .prcm = {
2129 .omap4 = {
2130 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2131 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2132 .modulemode = MODULEMODE_SWCTRL,
2133 },
2134 },
2135};
2136
2137/* uart4 */
2138static struct omap_hwmod dra7xx_uart4_hwmod = {
2139 .name = "uart4",
2140 .class = &dra7xx_uart_hwmod_class,
2141 .clkdm_name = "l4per_clkdm",
2142 .main_clk = "uart4_gfclk_mux",
b0340850 2143 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART4_FLAGS,
90020c7b
A		 2144 .prcm = {
2145 .omap4 = {
2146 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2147 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2148 .modulemode = MODULEMODE_SWCTRL,
2149 },
2150 },
2151};
2152
2153/* uart5 */
2154static struct omap_hwmod dra7xx_uart5_hwmod = {
2155 .name = "uart5",
2156 .class = &dra7xx_uart_hwmod_class,
2157 .clkdm_name = "l4per_clkdm",
2158 .main_clk = "uart5_gfclk_mux",
2159 .flags = HWMOD_SWSUP_SIDLE_ACT,
2160 .prcm = {
2161 .omap4 = {
2162 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2163 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2164 .modulemode = MODULEMODE_SWCTRL,
2165 },
2166 },
2167};
2168
2169/* uart6 */
2170static struct omap_hwmod dra7xx_uart6_hwmod = {
2171 .name = "uart6",
2172 .class = &dra7xx_uart_hwmod_class,
2173 .clkdm_name = "ipu_clkdm",
2174 .main_clk = "uart6_gfclk_mux",
2175 .flags = HWMOD_SWSUP_SIDLE_ACT,
2176 .prcm = {
2177 .omap4 = {
2178 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2179 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2180 .modulemode = MODULEMODE_SWCTRL,
2181 },
2182 },
2183};
2184
33acc9ff
A		 2185/* uart7 */
2186static struct omap_hwmod dra7xx_uart7_hwmod = {
2187 .name = "uart7",
2188 .class = &dra7xx_uart_hwmod_class,
2189 .clkdm_name = "l4per2_clkdm",
2190 .main_clk = "uart7_gfclk_mux",
2191 .flags = HWMOD_SWSUP_SIDLE_ACT,
2192 .prcm = {
2193 .omap4 = {
2194 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2195 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2196 .modulemode = MODULEMODE_SWCTRL,
2197 },
2198 },
2199};
2200
2201/* uart8 */
2202static struct omap_hwmod dra7xx_uart8_hwmod = {
2203 .name = "uart8",
2204 .class = &dra7xx_uart_hwmod_class,
2205 .clkdm_name = "l4per2_clkdm",
2206 .main_clk = "uart8_gfclk_mux",
2207 .flags = HWMOD_SWSUP_SIDLE_ACT,
2208 .prcm = {
2209 .omap4 = {
2210 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2211 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2212 .modulemode = MODULEMODE_SWCTRL,
2213 },
2214 },
2215};
2216
2217/* uart9 */
2218static struct omap_hwmod dra7xx_uart9_hwmod = {
2219 .name = "uart9",
2220 .class = &dra7xx_uart_hwmod_class,
2221 .clkdm_name = "l4per2_clkdm",
2222 .main_clk = "uart9_gfclk_mux",
2223 .flags = HWMOD_SWSUP_SIDLE_ACT,
2224 .prcm = {
2225 .omap4 = {
2226 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2227 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2228 .modulemode = MODULEMODE_SWCTRL,
2229 },
2230 },
2231};
2232
2233/* uart10 */
2234static struct omap_hwmod dra7xx_uart10_hwmod = {
2235 .name = "uart10",
2236 .class = &dra7xx_uart_hwmod_class,
2237 .clkdm_name = "wkupaon_clkdm",
2238 .main_clk = "uart10_gfclk_mux",
2239 .flags = HWMOD_SWSUP_SIDLE_ACT,
2240 .prcm = {
2241 .omap4 = {
2242 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2243 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2244 .modulemode = MODULEMODE_SWCTRL,
2245 },
2246 },
2247};
2248
90020c7b
A		 2249/*
2250 * 'usb_otg_ss' class
2251 *
2252 */
2253
d904b38d
RQ		 2254static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2255 .rev_offs = 0x0000,
2256 .sysc_offs = 0x0010,
2257 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2258 SYSC_HAS_SIDLEMODE),
2259 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2260 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2261 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2262 .sysc_fields = &omap_hwmod_sysc_type2,
2263};
2264
90020c7b
A		 2265static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2266 .name = "usb_otg_ss",
d904b38d 2267 .sysc = &dra7xx_usb_otg_ss_sysc,
90020c7b
A		 2268};
2269
2270/* usb_otg_ss1 */
2271static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2272 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2273};
2274
2275static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2276 .name = "usb_otg_ss1",
2277 .class = &dra7xx_usb_otg_ss_hwmod_class,
2278 .clkdm_name = "l3init_clkdm",
2279 .main_clk = "dpll_core_h13x2_ck",
2280 .prcm = {
2281 .omap4 = {
2282 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2283 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2284 .modulemode = MODULEMODE_HWCTRL,
2285 },
2286 },
2287 .opt_clks = usb_otg_ss1_opt_clks,
2288 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2289};
2290
2291/* usb_otg_ss2 */
2292static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2293 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2294};
2295
2296static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2297 .name = "usb_otg_ss2",
2298 .class = &dra7xx_usb_otg_ss_hwmod_class,
2299 .clkdm_name = "l3init_clkdm",
2300 .main_clk = "dpll_core_h13x2_ck",
2301 .prcm = {
2302 .omap4 = {
2303 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2304 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2305 .modulemode = MODULEMODE_HWCTRL,
2306 },
2307 },
2308 .opt_clks = usb_otg_ss2_opt_clks,
2309 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2310};
2311
2312/* usb_otg_ss3 */
2313static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2314 .name = "usb_otg_ss3",
2315 .class = &dra7xx_usb_otg_ss_hwmod_class,
2316 .clkdm_name = "l3init_clkdm",
2317 .main_clk = "dpll_core_h13x2_ck",
2318 .prcm = {
2319 .omap4 = {
2320 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2321 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2322 .modulemode = MODULEMODE_HWCTRL,
2323 },
2324 },
2325};
2326
2327/* usb_otg_ss4 */
2328static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2329 .name = "usb_otg_ss4",
2330 .class = &dra7xx_usb_otg_ss_hwmod_class,
2331 .clkdm_name = "l3init_clkdm",
2332 .main_clk = "dpll_core_h13x2_ck",
2333 .prcm = {
2334 .omap4 = {
2335 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2336 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2337 .modulemode = MODULEMODE_HWCTRL,
2338 },
2339 },
2340};
2341
2342/*
2343 * 'vcp' class
2344 *
2345 */
2346
2347static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2348 .name = "vcp",
2349};
2350
2351/* vcp1 */
2352static struct omap_hwmod dra7xx_vcp1_hwmod = {
2353 .name = "vcp1",
2354 .class = &dra7xx_vcp_hwmod_class,
2355 .clkdm_name = "l3main1_clkdm",
2356 .main_clk = "l3_iclk_div",
2357 .prcm = {
2358 .omap4 = {
2359 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2360 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2361 },
2362 },
2363};
2364
2365/* vcp2 */
2366static struct omap_hwmod dra7xx_vcp2_hwmod = {
2367 .name = "vcp2",
2368 .class = &dra7xx_vcp_hwmod_class,
2369 .clkdm_name = "l3main1_clkdm",
2370 .main_clk = "l3_iclk_div",
2371 .prcm = {
2372 .omap4 = {
2373 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2374 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2375 },
2376 },
2377};
2378
2379/*
2380 * 'wd_timer' class
2381 *
2382 */
2383
2384static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2385 .rev_offs = 0x0000,
2386 .sysc_offs = 0x0010,
2387 .syss_offs = 0x0014,
2388 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2389 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2390 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2391 SIDLE_SMART_WKUP),
2392 .sysc_fields = &omap_hwmod_sysc_type1,
2393};
2394
2395static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2396 .name = "wd_timer",
2397 .sysc = &dra7xx_wd_timer_sysc,
2398 .pre_shutdown = &omap2_wd_timer_disable,
2399 .reset = &omap2_wd_timer_reset,
2400};
2401
2402/* wd_timer2 */
2403static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2404 .name = "wd_timer2",
2405 .class = &dra7xx_wd_timer_hwmod_class,
2406 .clkdm_name = "wkupaon_clkdm",
2407 .main_clk = "sys_32k_ck",
2408 .prcm = {
2409 .omap4 = {
2410 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2411 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2412 .modulemode = MODULEMODE_SWCTRL,
2413 },
2414 },
2415};
2416
2417
2418/*
2419 * Interfaces
2420 */
2421
42121688
TV		 2422/* l3_main_1 -> dmm */
2423static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2424 .master = &dra7xx_l3_main_1_hwmod,
2425 .slave = &dra7xx_dmm_hwmod,
2426 .clk = "l3_iclk_div",
2427 .user = OCP_USER_SDMA,
2428};
2429
90020c7b
A		 2430/* l3_main_2 -> l3_instr */
2431static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2432 .master = &dra7xx_l3_main_2_hwmod,
2433 .slave = &dra7xx_l3_instr_hwmod,
2434 .clk = "l3_iclk_div",
2435 .user = OCP_USER_MPU | OCP_USER_SDMA,
2436};
2437
2438/* l4_cfg -> l3_main_1 */
2439static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2440 .master = &dra7xx_l4_cfg_hwmod,
2441 .slave = &dra7xx_l3_main_1_hwmod,
2442 .clk = "l3_iclk_div",
2443 .user = OCP_USER_MPU | OCP_USER_SDMA,
2444};
2445
2446/* mpu -> l3_main_1 */
2447static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2448 .master = &dra7xx_mpu_hwmod,
2449 .slave = &dra7xx_l3_main_1_hwmod,
2450 .clk = "l3_iclk_div",
2451 .user = OCP_USER_MPU,
2452};
2453
2454/* l3_main_1 -> l3_main_2 */
2455static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2456 .master = &dra7xx_l3_main_1_hwmod,
2457 .slave = &dra7xx_l3_main_2_hwmod,
2458 .clk = "l3_iclk_div",
2459 .user = OCP_USER_MPU,
2460};
2461
2462/* l4_cfg -> l3_main_2 */
2463static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2464 .master = &dra7xx_l4_cfg_hwmod,
2465 .slave = &dra7xx_l3_main_2_hwmod,
2466 .clk = "l3_iclk_div",
2467 .user = OCP_USER_MPU | OCP_USER_SDMA,
2468};
2469
2470/* l3_main_1 -> l4_cfg */
2471static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2472 .master = &dra7xx_l3_main_1_hwmod,
2473 .slave = &dra7xx_l4_cfg_hwmod,
2474 .clk = "l3_iclk_div",
2475 .user = OCP_USER_MPU | OCP_USER_SDMA,
2476};
2477
2478/* l3_main_1 -> l4_per1 */
2479static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2480 .master = &dra7xx_l3_main_1_hwmod,
2481 .slave = &dra7xx_l4_per1_hwmod,
2482 .clk = "l3_iclk_div",
2483 .user = OCP_USER_MPU | OCP_USER_SDMA,
2484};
2485
2486/* l3_main_1 -> l4_per2 */
2487static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2488 .master = &dra7xx_l3_main_1_hwmod,
2489 .slave = &dra7xx_l4_per2_hwmod,
2490 .clk = "l3_iclk_div",
2491 .user = OCP_USER_MPU | OCP_USER_SDMA,
2492};
2493
2494/* l3_main_1 -> l4_per3 */
2495static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2496 .master = &dra7xx_l3_main_1_hwmod,
2497 .slave = &dra7xx_l4_per3_hwmod,
2498 .clk = "l3_iclk_div",
2499 .user = OCP_USER_MPU | OCP_USER_SDMA,
2500};
2501
2502/* l3_main_1 -> l4_wkup */
2503static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2504 .master = &dra7xx_l3_main_1_hwmod,
2505 .slave = &dra7xx_l4_wkup_hwmod,
2506 .clk = "wkupaon_iclk_mux",
2507 .user = OCP_USER_MPU | OCP_USER_SDMA,
2508};
2509
2510/* l4_per2 -> atl */
2511static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2512 .master = &dra7xx_l4_per2_hwmod,
2513 .slave = &dra7xx_atl_hwmod,
2514 .clk = "l3_iclk_div",
2515 .user = OCP_USER_MPU | OCP_USER_SDMA,
2516};
2517
2518/* l3_main_1 -> bb2d */
2519static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2520 .master = &dra7xx_l3_main_1_hwmod,
2521 .slave = &dra7xx_bb2d_hwmod,
2522 .clk = "l3_iclk_div",
2523 .user = OCP_USER_MPU | OCP_USER_SDMA,
2524};
2525
2526/* l4_wkup -> counter_32k */
2527static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2528 .master = &dra7xx_l4_wkup_hwmod,
2529 .slave = &dra7xx_counter_32k_hwmod,
2530 .clk = "wkupaon_iclk_mux",
2531 .user = OCP_USER_MPU | OCP_USER_SDMA,
2532};
2533
2534/* l4_wkup -> ctrl_module_wkup */
2535static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2536 .master = &dra7xx_l4_wkup_hwmod,
2537 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2538 .clk = "wkupaon_iclk_mux",
2539 .user = OCP_USER_MPU | OCP_USER_SDMA,
2540};
2541
077c42f7
M		 2542static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2543 .master = &dra7xx_l4_per2_hwmod,
2544 .slave = &dra7xx_gmac_hwmod,
2545 .clk = "dpll_gmac_ck",
2546 .user = OCP_USER_MPU,
2547};
2548
2549static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2550 .master = &dra7xx_gmac_hwmod,
2551 .slave = &dra7xx_mdio_hwmod,
2552 .user = OCP_USER_MPU,
2553};
2554
90020c7b
A		 2555/* l4_wkup -> dcan1 */
2556static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2557 .master = &dra7xx_l4_wkup_hwmod,
2558 .slave = &dra7xx_dcan1_hwmod,
2559 .clk = "wkupaon_iclk_mux",
2560 .user = OCP_USER_MPU | OCP_USER_SDMA,
2561};
2562
2563/* l4_per2 -> dcan2 */
2564static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2565 .master = &dra7xx_l4_per2_hwmod,
2566 .slave = &dra7xx_dcan2_hwmod,
2567 .clk = "l3_iclk_div",
2568 .user = OCP_USER_MPU | OCP_USER_SDMA,
2569};
2570
2571static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2572 {
2573 .pa_start = 0x4a056000,
2574 .pa_end = 0x4a056fff,
2575 .flags = ADDR_TYPE_RT
2576 },
2577 { }
2578};
2579
2580/* l4_cfg -> dma_system */
2581static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2582 .master = &dra7xx_l4_cfg_hwmod,
2583 .slave = &dra7xx_dma_system_hwmod,
2584 .clk = "l3_iclk_div",
2585 .addr = dra7xx_dma_system_addrs,
2586 .user = OCP_USER_MPU | OCP_USER_SDMA,
2587};
2588
2589static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2590 {
2591 .name = "family",
2592 .pa_start = 0x58000000,
2593 .pa_end = 0x5800007f,
2594 .flags = ADDR_TYPE_RT
2595 },
2596};
2597
2598/* l3_main_1 -> dss */
2599static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2600 .master = &dra7xx_l3_main_1_hwmod,
2601 .slave = &dra7xx_dss_hwmod,
2602 .clk = "l3_iclk_div",
2603 .addr = dra7xx_dss_addrs,
2604 .user = OCP_USER_MPU | OCP_USER_SDMA,
2605};
2606
2607static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2608 {
2609 .name = "dispc",
2610 .pa_start = 0x58001000,
2611 .pa_end = 0x58001fff,
2612 .flags = ADDR_TYPE_RT
2613 },
2614};
2615
2616/* l3_main_1 -> dispc */
2617static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2618 .master = &dra7xx_l3_main_1_hwmod,
2619 .slave = &dra7xx_dss_dispc_hwmod,
2620 .clk = "l3_iclk_div",
2621 .addr = dra7xx_dss_dispc_addrs,
2622 .user = OCP_USER_MPU | OCP_USER_SDMA,
2623};
2624
2625static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2626 {
2627 .name = "hdmi_wp",
2628 .pa_start = 0x58040000,
2629 .pa_end = 0x580400ff,
2630 .flags = ADDR_TYPE_RT
2631 },
2632 { }
2633};
2634
2635/* l3_main_1 -> dispc */
2636static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2637 .master = &dra7xx_l3_main_1_hwmod,
2638 .slave = &dra7xx_dss_hdmi_hwmod,
2639 .clk = "l3_iclk_div",
2640 .addr = dra7xx_dss_hdmi_addrs,
2641 .user = OCP_USER_MPU | OCP_USER_SDMA,
2642};
2643
469689a4
PU		 2644/* l4_per2 -> mcasp3 */
2645static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
2646 .master = &dra7xx_l4_per2_hwmod,
2647 .slave = &dra7xx_mcasp3_hwmod,
2648 .clk = "l4_root_clk_div",
2649 .user = OCP_USER_MPU | OCP_USER_SDMA,
2650};
2651
2652/* l3_main_1 -> mcasp3 */
2653static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
2654 .master = &dra7xx_l3_main_1_hwmod,
2655 .slave = &dra7xx_mcasp3_hwmod,
2656 .clk = "l3_iclk_div",
2657 .user = OCP_USER_MPU | OCP_USER_SDMA,
2658};
2659
90020c7b
A		 2660/* l4_per1 -> elm */
2661static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2662 .master = &dra7xx_l4_per1_hwmod,
2663 .slave = &dra7xx_elm_hwmod,
2664 .clk = "l3_iclk_div",
90020c7b
A		 2665 .user = OCP_USER_MPU | OCP_USER_SDMA,
2666};
2667
2668/* l4_wkup -> gpio1 */
2669static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2670 .master = &dra7xx_l4_wkup_hwmod,
2671 .slave = &dra7xx_gpio1_hwmod,
2672 .clk = "wkupaon_iclk_mux",
2673 .user = OCP_USER_MPU | OCP_USER_SDMA,
2674};
2675
2676/* l4_per1 -> gpio2 */
2677static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2678 .master = &dra7xx_l4_per1_hwmod,
2679 .slave = &dra7xx_gpio2_hwmod,
2680 .clk = "l3_iclk_div",
2681 .user = OCP_USER_MPU | OCP_USER_SDMA,
2682};
2683
2684/* l4_per1 -> gpio3 */
2685static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2686 .master = &dra7xx_l4_per1_hwmod,
2687 .slave = &dra7xx_gpio3_hwmod,
2688 .clk = "l3_iclk_div",
2689 .user = OCP_USER_MPU | OCP_USER_SDMA,
2690};
2691
2692/* l4_per1 -> gpio4 */
2693static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2694 .master = &dra7xx_l4_per1_hwmod,
2695 .slave = &dra7xx_gpio4_hwmod,
2696 .clk = "l3_iclk_div",
2697 .user = OCP_USER_MPU | OCP_USER_SDMA,
2698};
2699
2700/* l4_per1 -> gpio5 */
2701static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2702 .master = &dra7xx_l4_per1_hwmod,
2703 .slave = &dra7xx_gpio5_hwmod,
2704 .clk = "l3_iclk_div",
2705 .user = OCP_USER_MPU | OCP_USER_SDMA,
2706};
2707
2708/* l4_per1 -> gpio6 */
2709static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2710 .master = &dra7xx_l4_per1_hwmod,
2711 .slave = &dra7xx_gpio6_hwmod,
2712 .clk = "l3_iclk_div",
2713 .user = OCP_USER_MPU | OCP_USER_SDMA,
2714};
2715
2716/* l4_per1 -> gpio7 */
2717static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2718 .master = &dra7xx_l4_per1_hwmod,
2719 .slave = &dra7xx_gpio7_hwmod,
2720 .clk = "l3_iclk_div",
2721 .user = OCP_USER_MPU | OCP_USER_SDMA,
2722};
2723
2724/* l4_per1 -> gpio8 */
2725static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2726 .master = &dra7xx_l4_per1_hwmod,
2727 .slave = &dra7xx_gpio8_hwmod,
2728 .clk = "l3_iclk_div",
2729 .user = OCP_USER_MPU | OCP_USER_SDMA,
2730};
2731
90020c7b
A		 2732/* l3_main_1 -> gpmc */
2733static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2734 .master = &dra7xx_l3_main_1_hwmod,
2735 .slave = &dra7xx_gpmc_hwmod,
2736 .clk = "l3_iclk_div",
90020c7b
A		 2737 .user = OCP_USER_MPU | OCP_USER_SDMA,
2738};
2739
2740static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2741 {
2742 .pa_start = 0x480b2000,
2743 .pa_end = 0x480b201f,
2744 .flags = ADDR_TYPE_RT
2745 },
2746 { }
2747};
2748
2749/* l4_per1 -> hdq1w */
2750static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2751 .master = &dra7xx_l4_per1_hwmod,
2752 .slave = &dra7xx_hdq1w_hwmod,
2753 .clk = "l3_iclk_div",
2754 .addr = dra7xx_hdq1w_addrs,
2755 .user = OCP_USER_MPU | OCP_USER_SDMA,
2756};
2757
2758/* l4_per1 -> i2c1 */
2759static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2760 .master = &dra7xx_l4_per1_hwmod,
2761 .slave = &dra7xx_i2c1_hwmod,
2762 .clk = "l3_iclk_div",
2763 .user = OCP_USER_MPU | OCP_USER_SDMA,
2764};
2765
2766/* l4_per1 -> i2c2 */
2767static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2768 .master = &dra7xx_l4_per1_hwmod,
2769 .slave = &dra7xx_i2c2_hwmod,
2770 .clk = "l3_iclk_div",
2771 .user = OCP_USER_MPU | OCP_USER_SDMA,
2772};
2773
2774/* l4_per1 -> i2c3 */
2775static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2776 .master = &dra7xx_l4_per1_hwmod,
2777 .slave = &dra7xx_i2c3_hwmod,
2778 .clk = "l3_iclk_div",
2779 .user = OCP_USER_MPU | OCP_USER_SDMA,
2780};
2781
2782/* l4_per1 -> i2c4 */
2783static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2784 .master = &dra7xx_l4_per1_hwmod,
2785 .slave = &dra7xx_i2c4_hwmod,
2786 .clk = "l3_iclk_div",
2787 .user = OCP_USER_MPU | OCP_USER_SDMA,
2788};
2789
2790/* l4_per1 -> i2c5 */
2791static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2792 .master = &dra7xx_l4_per1_hwmod,
2793 .slave = &dra7xx_i2c5_hwmod,
2794 .clk = "l3_iclk_div",
2795 .user = OCP_USER_MPU | OCP_USER_SDMA,
2796};
2797
067395d4
SA		 2798/* l4_cfg -> mailbox1 */
2799static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
2800 .master = &dra7xx_l4_cfg_hwmod,
2801 .slave = &dra7xx_mailbox1_hwmod,
2802 .clk = "l3_iclk_div",
2803 .user = OCP_USER_MPU | OCP_USER_SDMA,
2804};
2805
2806/* l4_per3 -> mailbox2 */
2807static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
2808 .master = &dra7xx_l4_per3_hwmod,
2809 .slave = &dra7xx_mailbox2_hwmod,
2810 .clk = "l3_iclk_div",
2811 .user = OCP_USER_MPU | OCP_USER_SDMA,
2812};
2813
2814/* l4_per3 -> mailbox3 */
2815static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
2816 .master = &dra7xx_l4_per3_hwmod,
2817 .slave = &dra7xx_mailbox3_hwmod,
2818 .clk = "l3_iclk_div",
2819 .user = OCP_USER_MPU | OCP_USER_SDMA,
2820};
2821
2822/* l4_per3 -> mailbox4 */
2823static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
2824 .master = &dra7xx_l4_per3_hwmod,
2825 .slave = &dra7xx_mailbox4_hwmod,
2826 .clk = "l3_iclk_div",
2827 .user = OCP_USER_MPU | OCP_USER_SDMA,
2828};
2829
2830/* l4_per3 -> mailbox5 */
2831static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
2832 .master = &dra7xx_l4_per3_hwmod,
2833 .slave = &dra7xx_mailbox5_hwmod,
2834 .clk = "l3_iclk_div",
2835 .user = OCP_USER_MPU | OCP_USER_SDMA,
2836};
2837
2838/* l4_per3 -> mailbox6 */
2839static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
2840 .master = &dra7xx_l4_per3_hwmod,
2841 .slave = &dra7xx_mailbox6_hwmod,
2842 .clk = "l3_iclk_div",
2843 .user = OCP_USER_MPU | OCP_USER_SDMA,
2844};
2845
2846/* l4_per3 -> mailbox7 */
2847static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
2848 .master = &dra7xx_l4_per3_hwmod,
2849 .slave = &dra7xx_mailbox7_hwmod,
2850 .clk = "l3_iclk_div",
2851 .user = OCP_USER_MPU | OCP_USER_SDMA,
2852};
2853
2854/* l4_per3 -> mailbox8 */
2855static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
2856 .master = &dra7xx_l4_per3_hwmod,
2857 .slave = &dra7xx_mailbox8_hwmod,
2858 .clk = "l3_iclk_div",
2859 .user = OCP_USER_MPU | OCP_USER_SDMA,
2860};
2861
2862/* l4_per3 -> mailbox9 */
2863static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
2864 .master = &dra7xx_l4_per3_hwmod,
2865 .slave = &dra7xx_mailbox9_hwmod,
2866 .clk = "l3_iclk_div",
2867 .user = OCP_USER_MPU | OCP_USER_SDMA,
2868};
2869
2870/* l4_per3 -> mailbox10 */
2871static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
2872 .master = &dra7xx_l4_per3_hwmod,
2873 .slave = &dra7xx_mailbox10_hwmod,
2874 .clk = "l3_iclk_div",
2875 .user = OCP_USER_MPU | OCP_USER_SDMA,
2876};
2877
2878/* l4_per3 -> mailbox11 */
2879static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
2880 .master = &dra7xx_l4_per3_hwmod,
2881 .slave = &dra7xx_mailbox11_hwmod,
2882 .clk = "l3_iclk_div",
2883 .user = OCP_USER_MPU | OCP_USER_SDMA,
2884};
2885
2886/* l4_per3 -> mailbox12 */
2887static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
2888 .master = &dra7xx_l4_per3_hwmod,
2889 .slave = &dra7xx_mailbox12_hwmod,
2890 .clk = "l3_iclk_div",
2891 .user = OCP_USER_MPU | OCP_USER_SDMA,
2892};
2893
2894/* l4_per3 -> mailbox13 */
2895static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
2896 .master = &dra7xx_l4_per3_hwmod,
2897 .slave = &dra7xx_mailbox13_hwmod,
2898 .clk = "l3_iclk_div",
2899 .user = OCP_USER_MPU | OCP_USER_SDMA,
2900};
2901
90020c7b
A		 2902/* l4_per1 -> mcspi1 */
2903static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2904 .master = &dra7xx_l4_per1_hwmod,
2905 .slave = &dra7xx_mcspi1_hwmod,
2906 .clk = "l3_iclk_div",
2907 .user = OCP_USER_MPU | OCP_USER_SDMA,
2908};
2909
2910/* l4_per1 -> mcspi2 */
2911static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2912 .master = &dra7xx_l4_per1_hwmod,
2913 .slave = &dra7xx_mcspi2_hwmod,
2914 .clk = "l3_iclk_div",
2915 .user = OCP_USER_MPU | OCP_USER_SDMA,
2916};
2917
2918/* l4_per1 -> mcspi3 */
2919static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2920 .master = &dra7xx_l4_per1_hwmod,
2921 .slave = &dra7xx_mcspi3_hwmod,
2922 .clk = "l3_iclk_div",
2923 .user = OCP_USER_MPU | OCP_USER_SDMA,
2924};
2925
2926/* l4_per1 -> mcspi4 */
2927static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2928 .master = &dra7xx_l4_per1_hwmod,
2929 .slave = &dra7xx_mcspi4_hwmod,
2930 .clk = "l3_iclk_div",
2931 .user = OCP_USER_MPU | OCP_USER_SDMA,
2932};
2933
2934/* l4_per1 -> mmc1 */
2935static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
2936 .master = &dra7xx_l4_per1_hwmod,
2937 .slave = &dra7xx_mmc1_hwmod,
2938 .clk = "l3_iclk_div",
2939 .user = OCP_USER_MPU | OCP_USER_SDMA,
2940};
2941
2942/* l4_per1 -> mmc2 */
2943static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
2944 .master = &dra7xx_l4_per1_hwmod,
2945 .slave = &dra7xx_mmc2_hwmod,
2946 .clk = "l3_iclk_div",
2947 .user = OCP_USER_MPU | OCP_USER_SDMA,
2948};
2949
2950/* l4_per1 -> mmc3 */
2951static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
2952 .master = &dra7xx_l4_per1_hwmod,
2953 .slave = &dra7xx_mmc3_hwmod,
2954 .clk = "l3_iclk_div",
2955 .user = OCP_USER_MPU | OCP_USER_SDMA,
2956};
2957
2958/* l4_per1 -> mmc4 */
2959static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
2960 .master = &dra7xx_l4_per1_hwmod,
2961 .slave = &dra7xx_mmc4_hwmod,
2962 .clk = "l3_iclk_div",
2963 .user = OCP_USER_MPU | OCP_USER_SDMA,
2964};
2965
2966/* l4_cfg -> mpu */
2967static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2968 .master = &dra7xx_l4_cfg_hwmod,
2969 .slave = &dra7xx_mpu_hwmod,
2970 .clk = "l3_iclk_div",
2971 .user = OCP_USER_MPU | OCP_USER_SDMA,
2972};
2973
90020c7b
A		 2974/* l4_cfg -> ocp2scp1 */
2975static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2976 .master = &dra7xx_l4_cfg_hwmod,
2977 .slave = &dra7xx_ocp2scp1_hwmod,
2978 .clk = "l4_root_clk_div",
90020c7b
A		 2979 .user = OCP_USER_MPU | OCP_USER_SDMA,
2980};
2981
df0d0f11
RQ		 2982/* l4_cfg -> ocp2scp3 */
2983static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
2984 .master = &dra7xx_l4_cfg_hwmod,
2985 .slave = &dra7xx_ocp2scp3_hwmod,
2986 .clk = "l4_root_clk_div",
2987 .user = OCP_USER_MPU | OCP_USER_SDMA,
2988};
2989
0717103e
KVA		 2990/* l3_main_1 -> pciess1 */
2991static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
8dd3eb71 2992 .master = &dra7xx_l3_main_1_hwmod,
0717103e 2993 .slave = &dra7xx_pciess1_hwmod,
8dd3eb71
KVA		 2994 .clk = "l3_iclk_div",
2995 .user = OCP_USER_MPU | OCP_USER_SDMA,
2996};
2997
0717103e
KVA		 2998/* l4_cfg -> pciess1 */
2999static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
8dd3eb71 3000 .master = &dra7xx_l4_cfg_hwmod,
0717103e 3001 .slave = &dra7xx_pciess1_hwmod,
8dd3eb71
KVA		 3002 .clk = "l4_root_clk_div",
3003 .user = OCP_USER_MPU | OCP_USER_SDMA,
3004};
3005
0717103e
KVA		 3006/* l3_main_1 -> pciess2 */
3007static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
8dd3eb71 3008 .master = &dra7xx_l3_main_1_hwmod,
0717103e 3009 .slave = &dra7xx_pciess2_hwmod,
8dd3eb71
KVA		 3010 .clk = "l3_iclk_div",
3011 .user = OCP_USER_MPU | OCP_USER_SDMA,
3012};
3013
0717103e
KVA		 3014/* l4_cfg -> pciess2 */
3015static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
70c18ef7 3016 .master = &dra7xx_l4_cfg_hwmod,
0717103e 3017 .slave = &dra7xx_pciess2_hwmod,
70c18ef7
KVA		 3018 .clk = "l4_root_clk_div",
3019 .user = OCP_USER_MPU | OCP_USER_SDMA,
3020};
3021
90020c7b
A		 3022static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
3023 {
3024 .pa_start = 0x4b300000,
3025 .pa_end = 0x4b30007f,
3026 .flags = ADDR_TYPE_RT
3027 },
3028 { }
3029};
3030
3031/* l3_main_1 -> qspi */
3032static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
3033 .master = &dra7xx_l3_main_1_hwmod,
3034 .slave = &dra7xx_qspi_hwmod,
3035 .clk = "l3_iclk_div",
3036 .addr = dra7xx_qspi_addrs,
3037 .user = OCP_USER_MPU | OCP_USER_SDMA,
3038};
3039
c913c8a1
LV		 3040/* l4_per3 -> rtcss */
3041static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
3042 .master = &dra7xx_l4_per3_hwmod,
3043 .slave = &dra7xx_rtcss_hwmod,
3044 .clk = "l4_root_clk_div",
3045 .user = OCP_USER_MPU | OCP_USER_SDMA,
3046};
3047
90020c7b
A		 3048static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
3049 {
3050 .name = "sysc",
3051 .pa_start = 0x4a141100,
3052 .pa_end = 0x4a141107,
3053 .flags = ADDR_TYPE_RT
3054 },
3055 { }
3056};
3057
3058/* l4_cfg -> sata */
3059static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
3060 .master = &dra7xx_l4_cfg_hwmod,
3061 .slave = &dra7xx_sata_hwmod,
3062 .clk = "l3_iclk_div",
3063 .addr = dra7xx_sata_addrs,
3064 .user = OCP_USER_MPU | OCP_USER_SDMA,
3065};
3066
3067static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
3068 {
3069 .pa_start = 0x4a0dd000,
3070 .pa_end = 0x4a0dd07f,
3071 .flags = ADDR_TYPE_RT
3072 },
3073 { }
3074};
3075
3076/* l4_cfg -> smartreflex_core */
3077static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3078 .master = &dra7xx_l4_cfg_hwmod,
3079 .slave = &dra7xx_smartreflex_core_hwmod,
3080 .clk = "l4_root_clk_div",
3081 .addr = dra7xx_smartreflex_core_addrs,
3082 .user = OCP_USER_MPU | OCP_USER_SDMA,
3083};
3084
3085static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
3086 {
3087 .pa_start = 0x4a0d9000,
3088 .pa_end = 0x4a0d907f,
3089 .flags = ADDR_TYPE_RT
3090 },
3091 { }
3092};
3093
3094/* l4_cfg -> smartreflex_mpu */
3095static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3096 .master = &dra7xx_l4_cfg_hwmod,
3097 .slave = &dra7xx_smartreflex_mpu_hwmod,
3098 .clk = "l4_root_clk_div",
3099 .addr = dra7xx_smartreflex_mpu_addrs,
3100 .user = OCP_USER_MPU | OCP_USER_SDMA,
3101};
3102
90020c7b
A		 3103/* l4_cfg -> spinlock */
3104static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3105 .master = &dra7xx_l4_cfg_hwmod,
3106 .slave = &dra7xx_spinlock_hwmod,
3107 .clk = "l3_iclk_div",
90020c7b
A		 3108 .user = OCP_USER_MPU | OCP_USER_SDMA,
3109};
3110
3111/* l4_wkup -> timer1 */
3112static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3113 .master = &dra7xx_l4_wkup_hwmod,
3114 .slave = &dra7xx_timer1_hwmod,
3115 .clk = "wkupaon_iclk_mux",
3116 .user = OCP_USER_MPU | OCP_USER_SDMA,
3117};
3118
3119/* l4_per1 -> timer2 */
3120static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3121 .master = &dra7xx_l4_per1_hwmod,
3122 .slave = &dra7xx_timer2_hwmod,
3123 .clk = "l3_iclk_div",
3124 .user = OCP_USER_MPU | OCP_USER_SDMA,
3125};
3126
3127/* l4_per1 -> timer3 */
3128static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3129 .master = &dra7xx_l4_per1_hwmod,
3130 .slave = &dra7xx_timer3_hwmod,
3131 .clk = "l3_iclk_div",
3132 .user = OCP_USER_MPU | OCP_USER_SDMA,
3133};
3134
3135/* l4_per1 -> timer4 */
3136static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3137 .master = &dra7xx_l4_per1_hwmod,
3138 .slave = &dra7xx_timer4_hwmod,
3139 .clk = "l3_iclk_div",
3140 .user = OCP_USER_MPU | OCP_USER_SDMA,
3141};
3142
3143/* l4_per3 -> timer5 */
3144static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3145 .master = &dra7xx_l4_per3_hwmod,
3146 .slave = &dra7xx_timer5_hwmod,
3147 .clk = "l3_iclk_div",
3148 .user = OCP_USER_MPU | OCP_USER_SDMA,
3149};
3150
3151/* l4_per3 -> timer6 */
3152static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3153 .master = &dra7xx_l4_per3_hwmod,
3154 .slave = &dra7xx_timer6_hwmod,
3155 .clk = "l3_iclk_div",
3156 .user = OCP_USER_MPU | OCP_USER_SDMA,
3157};
3158
3159/* l4_per3 -> timer7 */
3160static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3161 .master = &dra7xx_l4_per3_hwmod,
3162 .slave = &dra7xx_timer7_hwmod,
3163 .clk = "l3_iclk_div",
3164 .user = OCP_USER_MPU | OCP_USER_SDMA,
3165};
3166
3167/* l4_per3 -> timer8 */
3168static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3169 .master = &dra7xx_l4_per3_hwmod,
3170 .slave = &dra7xx_timer8_hwmod,
3171 .clk = "l3_iclk_div",
3172 .user = OCP_USER_MPU | OCP_USER_SDMA,
3173};
3174
3175/* l4_per1 -> timer9 */
3176static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3177 .master = &dra7xx_l4_per1_hwmod,
3178 .slave = &dra7xx_timer9_hwmod,
3179 .clk = "l3_iclk_div",
3180 .user = OCP_USER_MPU | OCP_USER_SDMA,
3181};
3182
3183/* l4_per1 -> timer10 */
3184static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3185 .master = &dra7xx_l4_per1_hwmod,
3186 .slave = &dra7xx_timer10_hwmod,
3187 .clk = "l3_iclk_div",
3188 .user = OCP_USER_MPU | OCP_USER_SDMA,
3189};
3190
3191/* l4_per1 -> timer11 */
3192static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3193 .master = &dra7xx_l4_per1_hwmod,
3194 .slave = &dra7xx_timer11_hwmod,
3195 .clk = "l3_iclk_div",
3196 .user = OCP_USER_MPU | OCP_USER_SDMA,
3197};
3198
1ac964f4
SA		 3199/* l4_per3 -> timer13 */
3200static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3201 .master = &dra7xx_l4_per3_hwmod,
3202 .slave = &dra7xx_timer13_hwmod,
3203 .clk = "l3_iclk_div",
3204 .user = OCP_USER_MPU | OCP_USER_SDMA,
3205};
3206
3207/* l4_per3 -> timer14 */
3208static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3209 .master = &dra7xx_l4_per3_hwmod,
3210 .slave = &dra7xx_timer14_hwmod,
3211 .clk = "l3_iclk_div",
3212 .user = OCP_USER_MPU | OCP_USER_SDMA,
3213};
3214
3215/* l4_per3 -> timer15 */
3216static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3217 .master = &dra7xx_l4_per3_hwmod,
3218 .slave = &dra7xx_timer15_hwmod,
3219 .clk = "l3_iclk_div",
3220 .user = OCP_USER_MPU | OCP_USER_SDMA,
3221};
3222
3223/* l4_per3 -> timer16 */
3224static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3225 .master = &dra7xx_l4_per3_hwmod,
3226 .slave = &dra7xx_timer16_hwmod,
3227 .clk = "l3_iclk_div",
3228 .user = OCP_USER_MPU | OCP_USER_SDMA,
3229};
3230
90020c7b
A		 3231/* l4_per1 -> uart1 */
3232static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3233 .master = &dra7xx_l4_per1_hwmod,
3234 .slave = &dra7xx_uart1_hwmod,
3235 .clk = "l3_iclk_div",
3236 .user = OCP_USER_MPU | OCP_USER_SDMA,
3237};
3238
3239/* l4_per1 -> uart2 */
3240static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3241 .master = &dra7xx_l4_per1_hwmod,
3242 .slave = &dra7xx_uart2_hwmod,
3243 .clk = "l3_iclk_div",
3244 .user = OCP_USER_MPU | OCP_USER_SDMA,
3245};
3246
3247/* l4_per1 -> uart3 */
3248static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3249 .master = &dra7xx_l4_per1_hwmod,
3250 .slave = &dra7xx_uart3_hwmod,
3251 .clk = "l3_iclk_div",
3252 .user = OCP_USER_MPU | OCP_USER_SDMA,
3253};
3254
3255/* l4_per1 -> uart4 */
3256static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3257 .master = &dra7xx_l4_per1_hwmod,
3258 .slave = &dra7xx_uart4_hwmod,
3259 .clk = "l3_iclk_div",
3260 .user = OCP_USER_MPU | OCP_USER_SDMA,
3261};
3262
3263/* l4_per1 -> uart5 */
3264static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3265 .master = &dra7xx_l4_per1_hwmod,
3266 .slave = &dra7xx_uart5_hwmod,
3267 .clk = "l3_iclk_div",
3268 .user = OCP_USER_MPU | OCP_USER_SDMA,
3269};
3270
3271/* l4_per1 -> uart6 */
3272static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3273 .master = &dra7xx_l4_per1_hwmod,
3274 .slave = &dra7xx_uart6_hwmod,
3275 .clk = "l3_iclk_div",
3276 .user = OCP_USER_MPU | OCP_USER_SDMA,
3277};
3278
33acc9ff
A		 3279/* l4_per2 -> uart7 */
3280static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3281 .master = &dra7xx_l4_per2_hwmod,
3282 .slave = &dra7xx_uart7_hwmod,
3283 .clk = "l3_iclk_div",
3284 .user = OCP_USER_MPU | OCP_USER_SDMA,
3285};
3286
3287/* l4_per2 -> uart8 */
3288static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3289 .master = &dra7xx_l4_per2_hwmod,
3290 .slave = &dra7xx_uart8_hwmod,
3291 .clk = "l3_iclk_div",
3292 .user = OCP_USER_MPU | OCP_USER_SDMA,
3293};
3294
3295/* l4_per2 -> uart9 */
3296static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3297 .master = &dra7xx_l4_per2_hwmod,
3298 .slave = &dra7xx_uart9_hwmod,
3299 .clk = "l3_iclk_div",
3300 .user = OCP_USER_MPU | OCP_USER_SDMA,
3301};
3302
3303/* l4_wkup -> uart10 */
3304static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3305 .master = &dra7xx_l4_wkup_hwmod,
3306 .slave = &dra7xx_uart10_hwmod,
3307 .clk = "wkupaon_iclk_mux",
3308 .user = OCP_USER_MPU | OCP_USER_SDMA,
3309};
3310
90020c7b
A		 3311/* l4_per3 -> usb_otg_ss1 */
3312static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3313 .master = &dra7xx_l4_per3_hwmod,
3314 .slave = &dra7xx_usb_otg_ss1_hwmod,
3315 .clk = "dpll_core_h13x2_ck",
3316 .user = OCP_USER_MPU | OCP_USER_SDMA,
3317};
3318
3319/* l4_per3 -> usb_otg_ss2 */
3320static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3321 .master = &dra7xx_l4_per3_hwmod,
3322 .slave = &dra7xx_usb_otg_ss2_hwmod,
3323 .clk = "dpll_core_h13x2_ck",
3324 .user = OCP_USER_MPU | OCP_USER_SDMA,
3325};
3326
3327/* l4_per3 -> usb_otg_ss3 */
3328static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3329 .master = &dra7xx_l4_per3_hwmod,
3330 .slave = &dra7xx_usb_otg_ss3_hwmod,
3331 .clk = "dpll_core_h13x2_ck",
3332 .user = OCP_USER_MPU | OCP_USER_SDMA,
3333};
3334
3335/* l4_per3 -> usb_otg_ss4 */
3336static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3337 .master = &dra7xx_l4_per3_hwmod,
3338 .slave = &dra7xx_usb_otg_ss4_hwmod,
3339 .clk = "dpll_core_h13x2_ck",
3340 .user = OCP_USER_MPU | OCP_USER_SDMA,
3341};
3342
3343/* l3_main_1 -> vcp1 */
3344static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3345 .master = &dra7xx_l3_main_1_hwmod,
3346 .slave = &dra7xx_vcp1_hwmod,
3347 .clk = "l3_iclk_div",
3348 .user = OCP_USER_MPU | OCP_USER_SDMA,
3349};
3350
3351/* l4_per2 -> vcp1 */
3352static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3353 .master = &dra7xx_l4_per2_hwmod,
3354 .slave = &dra7xx_vcp1_hwmod,
3355 .clk = "l3_iclk_div",
3356 .user = OCP_USER_MPU | OCP_USER_SDMA,
3357};
3358
3359/* l3_main_1 -> vcp2 */
3360static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3361 .master = &dra7xx_l3_main_1_hwmod,
3362 .slave = &dra7xx_vcp2_hwmod,
3363 .clk = "l3_iclk_div",
3364 .user = OCP_USER_MPU | OCP_USER_SDMA,
3365};
3366
3367/* l4_per2 -> vcp2 */
3368static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3369 .master = &dra7xx_l4_per2_hwmod,
3370 .slave = &dra7xx_vcp2_hwmod,
3371 .clk = "l3_iclk_div",
3372 .user = OCP_USER_MPU | OCP_USER_SDMA,
3373};
3374
3375/* l4_wkup -> wd_timer2 */
3376static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3377 .master = &dra7xx_l4_wkup_hwmod,
3378 .slave = &dra7xx_wd_timer2_hwmod,
3379 .clk = "wkupaon_iclk_mux",
3380 .user = OCP_USER_MPU | OCP_USER_SDMA,
3381};
3382
3383static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
42121688 3384 &dra7xx_l3_main_1__dmm,
90020c7b
A		 3385 &dra7xx_l3_main_2__l3_instr,
3386 &dra7xx_l4_cfg__l3_main_1,
3387 &dra7xx_mpu__l3_main_1,
3388 &dra7xx_l3_main_1__l3_main_2,
3389 &dra7xx_l4_cfg__l3_main_2,
3390 &dra7xx_l3_main_1__l4_cfg,
3391 &dra7xx_l3_main_1__l4_per1,
3392 &dra7xx_l3_main_1__l4_per2,
3393 &dra7xx_l3_main_1__l4_per3,
3394 &dra7xx_l3_main_1__l4_wkup,
3395 &dra7xx_l4_per2__atl,
3396 &dra7xx_l3_main_1__bb2d,
3397 &dra7xx_l4_wkup__counter_32k,
3398 &dra7xx_l4_wkup__ctrl_module_wkup,
3399 &dra7xx_l4_wkup__dcan1,
3400 &dra7xx_l4_per2__dcan2,
077c42f7 3401 &dra7xx_l4_per2__cpgmac0,
469689a4
PU		 3402 &dra7xx_l4_per2__mcasp3,
3403 &dra7xx_l3_main_1__mcasp3,
077c42f7 3404 &dra7xx_gmac__mdio,
90020c7b
A		 3405 &dra7xx_l4_cfg__dma_system,
3406 &dra7xx_l3_main_1__dss,
3407 &dra7xx_l3_main_1__dispc,
3408 &dra7xx_l3_main_1__hdmi,
3409 &dra7xx_l4_per1__elm,
3410 &dra7xx_l4_wkup__gpio1,
3411 &dra7xx_l4_per1__gpio2,
3412 &dra7xx_l4_per1__gpio3,
3413 &dra7xx_l4_per1__gpio4,
3414 &dra7xx_l4_per1__gpio5,
3415 &dra7xx_l4_per1__gpio6,
3416 &dra7xx_l4_per1__gpio7,
3417 &dra7xx_l4_per1__gpio8,
3418 &dra7xx_l3_main_1__gpmc,
3419 &dra7xx_l4_per1__hdq1w,
3420 &dra7xx_l4_per1__i2c1,
3421 &dra7xx_l4_per1__i2c2,
3422 &dra7xx_l4_per1__i2c3,
3423 &dra7xx_l4_per1__i2c4,
3424 &dra7xx_l4_per1__i2c5,
067395d4
SA		 3425 &dra7xx_l4_cfg__mailbox1,
3426 &dra7xx_l4_per3__mailbox2,
3427 &dra7xx_l4_per3__mailbox3,
3428 &dra7xx_l4_per3__mailbox4,
3429 &dra7xx_l4_per3__mailbox5,
3430 &dra7xx_l4_per3__mailbox6,
3431 &dra7xx_l4_per3__mailbox7,
3432 &dra7xx_l4_per3__mailbox8,
3433 &dra7xx_l4_per3__mailbox9,
3434 &dra7xx_l4_per3__mailbox10,
3435 &dra7xx_l4_per3__mailbox11,
3436 &dra7xx_l4_per3__mailbox12,
3437 &dra7xx_l4_per3__mailbox13,
90020c7b
A		 3438 &dra7xx_l4_per1__mcspi1,
3439 &dra7xx_l4_per1__mcspi2,
3440 &dra7xx_l4_per1__mcspi3,
3441 &dra7xx_l4_per1__mcspi4,
3442 &dra7xx_l4_per1__mmc1,
3443 &dra7xx_l4_per1__mmc2,
3444 &dra7xx_l4_per1__mmc3,
3445 &dra7xx_l4_per1__mmc4,
3446 &dra7xx_l4_cfg__mpu,
3447 &dra7xx_l4_cfg__ocp2scp1,
df0d0f11 3448 &dra7xx_l4_cfg__ocp2scp3,
0717103e
KVA		 3449 &dra7xx_l3_main_1__pciess1,
3450 &dra7xx_l4_cfg__pciess1,
3451 &dra7xx_l3_main_1__pciess2,
3452 &dra7xx_l4_cfg__pciess2,
90020c7b 3453 &dra7xx_l3_main_1__qspi,
c913c8a1 3454 &dra7xx_l4_per3__rtcss,
90020c7b
A		 3455 &dra7xx_l4_cfg__sata,
3456 &dra7xx_l4_cfg__smartreflex_core,
3457 &dra7xx_l4_cfg__smartreflex_mpu,
3458 &dra7xx_l4_cfg__spinlock,
3459 &dra7xx_l4_wkup__timer1,
3460 &dra7xx_l4_per1__timer2,
3461 &dra7xx_l4_per1__timer3,
3462 &dra7xx_l4_per1__timer4,
3463 &dra7xx_l4_per3__timer5,
3464 &dra7xx_l4_per3__timer6,
3465 &dra7xx_l4_per3__timer7,
3466 &dra7xx_l4_per3__timer8,
3467 &dra7xx_l4_per1__timer9,
3468 &dra7xx_l4_per1__timer10,
3469 &dra7xx_l4_per1__timer11,
1ac964f4
SA		 3470 &dra7xx_l4_per3__timer13,
3471 &dra7xx_l4_per3__timer14,
3472 &dra7xx_l4_per3__timer15,
3473 &dra7xx_l4_per3__timer16,
90020c7b
A		 3474 &dra7xx_l4_per1__uart1,
3475 &dra7xx_l4_per1__uart2,
3476 &dra7xx_l4_per1__uart3,
3477 &dra7xx_l4_per1__uart4,
3478 &dra7xx_l4_per1__uart5,
3479 &dra7xx_l4_per1__uart6,
33acc9ff
A		 3480 &dra7xx_l4_per2__uart7,
3481 &dra7xx_l4_per2__uart8,
3482 &dra7xx_l4_per2__uart9,
3483 &dra7xx_l4_wkup__uart10,
90020c7b
A		 3484 &dra7xx_l4_per3__usb_otg_ss1,
3485 &dra7xx_l4_per3__usb_otg_ss2,
3486 &dra7xx_l4_per3__usb_otg_ss3,
90020c7b
A		 3487 &dra7xx_l3_main_1__vcp1,
3488 &dra7xx_l4_per2__vcp1,
3489 &dra7xx_l3_main_1__vcp2,
3490 &dra7xx_l4_per2__vcp2,
3491 &dra7xx_l4_wkup__wd_timer2,
3492 NULL,
3493};
3494
f7f7a29b
RN		 3495static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3496 &dra7xx_l4_per3__usb_otg_ss4,
3497 NULL,
3498};
3499
3500static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3501 NULL,
3502};
3503
90020c7b
A		 3504int __init dra7xx_hwmod_init(void)
3505{
f7f7a29b
RN		 3506 int ret;
3507
90020c7b 3508 omap_hwmod_init();
f7f7a29b
RN		 3509 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3510
3511 if (!ret && soc_is_dra74x())
3512 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3513 else if (!ret && soc_is_dra72x())
3514 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
3515
3516 return ret;
90020c7b 3517}
Linux kernel - Deliverables
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