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ARM: DRA7: hwmod: add DMM hwmod description
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_7xx_data.c
CommitLineData
90020c7b
A		 1/*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/io.h>
21#include <linux/platform_data/gpio-omap.h>
55143438 22#include <linux/platform_data/hsmmc-omap.h>
90020c7b
A		 23#include <linux/power/smartreflex.h>
24#include <linux/i2c-omap.h>
25
26#include <linux/omap-dma.h>
27#include <linux/platform_data/spi-omap2-mcspi.h>
28#include <linux/platform_data/asoc-ti-mcbsp.h>
29#include <plat/dmtimer.h>
30
31#include "omap_hwmod.h"
32#include "omap_hwmod_common_data.h"
33#include "cm1_7xx.h"
34#include "cm2_7xx.h"
35#include "prm7xx.h"
36#include "i2c.h"
90020c7b 37#include "wd_timer.h"
f7f7a29b 38#include "soc.h"
90020c7b
A		 39
40/* Base offset for all DRA7XX interrupts external to MPUSS */
41#define DRA7XX_IRQ_GIC_START 32
42
43/* Base offset for all DRA7XX dma requests */
44#define DRA7XX_DMA_REQ_START 1
45
46
47/*
48 * IP blocks
49 */
50
42121688
TV		 51/*
52 * 'dmm' class
53 * instance(s): dmm
54 */
55static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
56 .name = "dmm",
57};
58
59/* dmm */
60static struct omap_hwmod dra7xx_dmm_hwmod = {
61 .name = "dmm",
62 .class = &dra7xx_dmm_hwmod_class,
63 .clkdm_name = "emif_clkdm",
64 .prcm = {
65 .omap4 = {
66 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
67 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
68 },
69 },
70};
71
90020c7b
A		 72/*
73 * 'l3' class
74 * instance(s): l3_instr, l3_main_1, l3_main_2
75 */
76static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
77 .name = "l3",
78};
79
80/* l3_instr */
81static struct omap_hwmod dra7xx_l3_instr_hwmod = {
82 .name = "l3_instr",
83 .class = &dra7xx_l3_hwmod_class,
84 .clkdm_name = "l3instr_clkdm",
85 .prcm = {
86 .omap4 = {
87 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
88 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
89 .modulemode = MODULEMODE_HWCTRL,
90 },
91 },
92};
93
94/* l3_main_1 */
95static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
96 .name = "l3_main_1",
97 .class = &dra7xx_l3_hwmod_class,
98 .clkdm_name = "l3main1_clkdm",
99 .prcm = {
100 .omap4 = {
101 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
102 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
103 },
104 },
105};
106
107/* l3_main_2 */
108static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
109 .name = "l3_main_2",
110 .class = &dra7xx_l3_hwmod_class,
111 .clkdm_name = "l3instr_clkdm",
112 .prcm = {
113 .omap4 = {
114 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
115 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
116 .modulemode = MODULEMODE_HWCTRL,
117 },
118 },
119};
120
121/*
122 * 'l4' class
123 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
124 */
125static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
126 .name = "l4",
127};
128
129/* l4_cfg */
130static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
131 .name = "l4_cfg",
132 .class = &dra7xx_l4_hwmod_class,
133 .clkdm_name = "l4cfg_clkdm",
134 .prcm = {
135 .omap4 = {
136 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
137 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
138 },
139 },
140};
141
142/* l4_per1 */
143static struct omap_hwmod dra7xx_l4_per1_hwmod = {
144 .name = "l4_per1",
145 .class = &dra7xx_l4_hwmod_class,
146 .clkdm_name = "l4per_clkdm",
147 .prcm = {
148 .omap4 = {
149 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
150 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
151 },
152 },
153};
154
155/* l4_per2 */
156static struct omap_hwmod dra7xx_l4_per2_hwmod = {
157 .name = "l4_per2",
158 .class = &dra7xx_l4_hwmod_class,
159 .clkdm_name = "l4per2_clkdm",
160 .prcm = {
161 .omap4 = {
162 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
163 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
164 },
165 },
166};
167
168/* l4_per3 */
169static struct omap_hwmod dra7xx_l4_per3_hwmod = {
170 .name = "l4_per3",
171 .class = &dra7xx_l4_hwmod_class,
172 .clkdm_name = "l4per3_clkdm",
173 .prcm = {
174 .omap4 = {
175 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
176 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
177 },
178 },
179};
180
181/* l4_wkup */
182static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
183 .name = "l4_wkup",
184 .class = &dra7xx_l4_hwmod_class,
185 .clkdm_name = "wkupaon_clkdm",
186 .prcm = {
187 .omap4 = {
188 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
189 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
190 },
191 },
192};
193
194/*
195 * 'atl' class
196 *
197 */
198
199static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
200 .name = "atl",
201};
202
203/* atl */
204static struct omap_hwmod dra7xx_atl_hwmod = {
205 .name = "atl",
206 .class = &dra7xx_atl_hwmod_class,
207 .clkdm_name = "atl_clkdm",
208 .main_clk = "atl_gfclk_mux",
209 .prcm = {
210 .omap4 = {
211 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
212 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
213 .modulemode = MODULEMODE_SWCTRL,
214 },
215 },
216};
217
218/*
219 * 'bb2d' class
220 *
221 */
222
223static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
224 .name = "bb2d",
225};
226
227/* bb2d */
228static struct omap_hwmod dra7xx_bb2d_hwmod = {
229 .name = "bb2d",
230 .class = &dra7xx_bb2d_hwmod_class,
231 .clkdm_name = "dss_clkdm",
232 .main_clk = "dpll_core_h24x2_ck",
233 .prcm = {
234 .omap4 = {
235 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
236 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
237 .modulemode = MODULEMODE_SWCTRL,
238 },
239 },
240};
241
242/*
243 * 'counter' class
244 *
245 */
246
247static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
248 .rev_offs = 0x0000,
249 .sysc_offs = 0x0010,
250 .sysc_flags = SYSC_HAS_SIDLEMODE,
251 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
252 SIDLE_SMART_WKUP),
253 .sysc_fields = &omap_hwmod_sysc_type1,
254};
255
256static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
257 .name = "counter",
258 .sysc = &dra7xx_counter_sysc,
259};
260
261/* counter_32k */
262static struct omap_hwmod dra7xx_counter_32k_hwmod = {
263 .name = "counter_32k",
264 .class = &dra7xx_counter_hwmod_class,
265 .clkdm_name = "wkupaon_clkdm",
266 .flags = HWMOD_SWSUP_SIDLE,
267 .main_clk = "wkupaon_iclk_mux",
268 .prcm = {
269 .omap4 = {
270 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
271 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
272 },
273 },
274};
275
276/*
277 * 'ctrl_module' class
278 *
279 */
280
281static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
282 .name = "ctrl_module",
283};
284
285/* ctrl_module_wkup */
286static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
287 .name = "ctrl_module_wkup",
288 .class = &dra7xx_ctrl_module_hwmod_class,
289 .clkdm_name = "wkupaon_clkdm",
290 .prcm = {
291 .omap4 = {
292 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
293 },
294 },
295};
296
077c42f7
M		 297/*
298 * 'gmac' class
299 * cpsw/gmac sub system
300 */
301static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
302 .rev_offs = 0x0,
303 .sysc_offs = 0x8,
304 .syss_offs = 0x4,
305 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
306 SYSS_HAS_RESET_STATUS),
307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
308 MSTANDBY_NO),
309 .sysc_fields = &omap_hwmod_sysc_type3,
310};
311
312static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
313 .name = "gmac",
314 .sysc = &dra7xx_gmac_sysc,
315};
316
317static struct omap_hwmod dra7xx_gmac_hwmod = {
318 .name = "gmac",
319 .class = &dra7xx_gmac_hwmod_class,
320 .clkdm_name = "gmac_clkdm",
321 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
322 .main_clk = "dpll_gmac_ck",
323 .mpu_rt_idx = 1,
324 .prcm = {
325 .omap4 = {
326 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
327 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
328 .modulemode = MODULEMODE_SWCTRL,
329 },
330 },
331};
332
333/*
334 * 'mdio' class
335 */
336static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
337 .name = "davinci_mdio",
338};
339
340static struct omap_hwmod dra7xx_mdio_hwmod = {
341 .name = "davinci_mdio",
342 .class = &dra7xx_mdio_hwmod_class,
343 .clkdm_name = "gmac_clkdm",
344 .main_clk = "dpll_gmac_ck",
345};
346
90020c7b
A		 347/*
348 * 'dcan' class
349 *
350 */
351
352static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
353 .name = "dcan",
354};
355
356/* dcan1 */
357static struct omap_hwmod dra7xx_dcan1_hwmod = {
358 .name = "dcan1",
359 .class = &dra7xx_dcan_hwmod_class,
360 .clkdm_name = "wkupaon_clkdm",
361 .main_clk = "dcan1_sys_clk_mux",
362 .prcm = {
363 .omap4 = {
364 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
365 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
366 .modulemode = MODULEMODE_SWCTRL,
367 },
368 },
369};
370
371/* dcan2 */
372static struct omap_hwmod dra7xx_dcan2_hwmod = {
373 .name = "dcan2",
374 .class = &dra7xx_dcan_hwmod_class,
375 .clkdm_name = "l4per2_clkdm",
376 .main_clk = "sys_clkin1",
377 .prcm = {
378 .omap4 = {
379 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
380 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
381 .modulemode = MODULEMODE_SWCTRL,
382 },
383 },
384};
385
386/*
387 * 'dma' class
388 *
389 */
390
391static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
392 .rev_offs = 0x0000,
393 .sysc_offs = 0x002c,
394 .syss_offs = 0x0028,
395 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
396 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
397 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
398 SYSS_HAS_RESET_STATUS),
399 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
400 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
401 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
402 .sysc_fields = &omap_hwmod_sysc_type1,
403};
404
405static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
406 .name = "dma",
407 .sysc = &dra7xx_dma_sysc,
408};
409
410/* dma dev_attr */
411static struct omap_dma_dev_attr dma_dev_attr = {
412 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
413 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
414 .lch_count = 32,
415};
416
417/* dma_system */
90020c7b
A		 418static struct omap_hwmod dra7xx_dma_system_hwmod = {
419 .name = "dma_system",
420 .class = &dra7xx_dma_hwmod_class,
421 .clkdm_name = "dma_clkdm",
90020c7b
A		 422 .main_clk = "l3_iclk_div",
423 .prcm = {
424 .omap4 = {
425 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
426 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
427 },
428 },
429 .dev_attr = &dma_dev_attr,
430};
431
432/*
433 * 'dss' class
434 *
435 */
436
437static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
438 .rev_offs = 0x0000,
439 .syss_offs = 0x0014,
440 .sysc_flags = SYSS_HAS_RESET_STATUS,
441};
442
443static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
444 .name = "dss",
445 .sysc = &dra7xx_dss_sysc,
446 .reset = omap_dss_reset,
447};
448
449/* dss */
450static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
451 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
452 { .dma_req = -1 }
453};
454
455static struct omap_hwmod_opt_clk dss_opt_clks[] = {
456 { .role = "dss_clk", .clk = "dss_dss_clk" },
457 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
458 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
459 { .role = "video2_clk", .clk = "dss_video2_clk" },
460 { .role = "video1_clk", .clk = "dss_video1_clk" },
461 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
2d5a3c80 462 { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
90020c7b
A		 463};
464
465static struct omap_hwmod dra7xx_dss_hwmod = {
466 .name = "dss_core",
467 .class = &dra7xx_dss_hwmod_class,
468 .clkdm_name = "dss_clkdm",
469 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
470 .sdma_reqs = dra7xx_dss_sdma_reqs,
471 .main_clk = "dss_dss_clk",
472 .prcm = {
473 .omap4 = {
474 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
475 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
476 .modulemode = MODULEMODE_SWCTRL,
477 },
478 },
479 .opt_clks = dss_opt_clks,
480 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
481};
482
483/*
484 * 'dispc' class
485 * display controller
486 */
487
488static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
489 .rev_offs = 0x0000,
490 .sysc_offs = 0x0010,
491 .syss_offs = 0x0014,
492 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
493 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
494 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
495 SYSS_HAS_RESET_STATUS),
496 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
497 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
498 .sysc_fields = &omap_hwmod_sysc_type1,
499};
500
501static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
502 .name = "dispc",
503 .sysc = &dra7xx_dispc_sysc,
504};
505
506/* dss_dispc */
507/* dss_dispc dev_attr */
508static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
509 .has_framedonetv_irq = 1,
510 .manager_count = 4,
511};
512
513static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
514 .name = "dss_dispc",
515 .class = &dra7xx_dispc_hwmod_class,
516 .clkdm_name = "dss_clkdm",
517 .main_clk = "dss_dss_clk",
518 .prcm = {
519 .omap4 = {
520 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
521 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
522 },
523 },
524 .dev_attr = &dss_dispc_dev_attr,
525};
526
527/*
528 * 'hdmi' class
529 * hdmi controller
530 */
531
532static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
533 .rev_offs = 0x0000,
534 .sysc_offs = 0x0010,
535 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
536 SYSC_HAS_SOFTRESET),
537 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
538 SIDLE_SMART_WKUP),
539 .sysc_fields = &omap_hwmod_sysc_type2,
540};
541
542static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
543 .name = "hdmi",
544 .sysc = &dra7xx_hdmi_sysc,
545};
546
547/* dss_hdmi */
548
549static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
550 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
551};
552
553static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
554 .name = "dss_hdmi",
555 .class = &dra7xx_hdmi_hwmod_class,
556 .clkdm_name = "dss_clkdm",
557 .main_clk = "dss_48mhz_clk",
558 .prcm = {
559 .omap4 = {
560 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
561 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
562 },
563 },
564 .opt_clks = dss_hdmi_opt_clks,
565 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
566};
567
568/*
569 * 'elm' class
570 *
571 */
572
573static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
574 .rev_offs = 0x0000,
575 .sysc_offs = 0x0010,
576 .syss_offs = 0x0014,
577 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
578 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
579 SYSS_HAS_RESET_STATUS),
580 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
581 SIDLE_SMART_WKUP),
582 .sysc_fields = &omap_hwmod_sysc_type1,
583};
584
585static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
586 .name = "elm",
587 .sysc = &dra7xx_elm_sysc,
588};
589
590/* elm */
591
592static struct omap_hwmod dra7xx_elm_hwmod = {
593 .name = "elm",
594 .class = &dra7xx_elm_hwmod_class,
595 .clkdm_name = "l4per_clkdm",
596 .main_clk = "l3_iclk_div",
597 .prcm = {
598 .omap4 = {
599 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
600 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
601 },
602 },
603};
604
605/*
606 * 'gpio' class
607 *
608 */
609
610static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
611 .rev_offs = 0x0000,
612 .sysc_offs = 0x0010,
613 .syss_offs = 0x0114,
614 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
615 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
616 SYSS_HAS_RESET_STATUS),
617 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
618 SIDLE_SMART_WKUP),
619 .sysc_fields = &omap_hwmod_sysc_type1,
620};
621
622static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
623 .name = "gpio",
624 .sysc = &dra7xx_gpio_sysc,
625 .rev = 2,
626};
627
628/* gpio dev_attr */
629static struct omap_gpio_dev_attr gpio_dev_attr = {
630 .bank_width = 32,
631 .dbck_flag = true,
632};
633
634/* gpio1 */
635static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
636 { .role = "dbclk", .clk = "gpio1_dbclk" },
637};
638
639static struct omap_hwmod dra7xx_gpio1_hwmod = {
640 .name = "gpio1",
641 .class = &dra7xx_gpio_hwmod_class,
642 .clkdm_name = "wkupaon_clkdm",
643 .main_clk = "wkupaon_iclk_mux",
644 .prcm = {
645 .omap4 = {
646 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
647 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
648 .modulemode = MODULEMODE_HWCTRL,
649 },
650 },
651 .opt_clks = gpio1_opt_clks,
652 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
653 .dev_attr = &gpio_dev_attr,
654};
655
656/* gpio2 */
657static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
658 { .role = "dbclk", .clk = "gpio2_dbclk" },
659};
660
661static struct omap_hwmod dra7xx_gpio2_hwmod = {
662 .name = "gpio2",
663 .class = &dra7xx_gpio_hwmod_class,
664 .clkdm_name = "l4per_clkdm",
665 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
666 .main_clk = "l3_iclk_div",
667 .prcm = {
668 .omap4 = {
669 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
670 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
671 .modulemode = MODULEMODE_HWCTRL,
672 },
673 },
674 .opt_clks = gpio2_opt_clks,
675 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
676 .dev_attr = &gpio_dev_attr,
677};
678
679/* gpio3 */
680static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
681 { .role = "dbclk", .clk = "gpio3_dbclk" },
682};
683
684static struct omap_hwmod dra7xx_gpio3_hwmod = {
685 .name = "gpio3",
686 .class = &dra7xx_gpio_hwmod_class,
687 .clkdm_name = "l4per_clkdm",
688 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
689 .main_clk = "l3_iclk_div",
690 .prcm = {
691 .omap4 = {
692 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
693 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
694 .modulemode = MODULEMODE_HWCTRL,
695 },
696 },
697 .opt_clks = gpio3_opt_clks,
698 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
699 .dev_attr = &gpio_dev_attr,
700};
701
702/* gpio4 */
703static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
704 { .role = "dbclk", .clk = "gpio4_dbclk" },
705};
706
707static struct omap_hwmod dra7xx_gpio4_hwmod = {
708 .name = "gpio4",
709 .class = &dra7xx_gpio_hwmod_class,
710 .clkdm_name = "l4per_clkdm",
711 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
712 .main_clk = "l3_iclk_div",
713 .prcm = {
714 .omap4 = {
715 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
716 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
717 .modulemode = MODULEMODE_HWCTRL,
718 },
719 },
720 .opt_clks = gpio4_opt_clks,
721 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
722 .dev_attr = &gpio_dev_attr,
723};
724
725/* gpio5 */
726static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
727 { .role = "dbclk", .clk = "gpio5_dbclk" },
728};
729
730static struct omap_hwmod dra7xx_gpio5_hwmod = {
731 .name = "gpio5",
732 .class = &dra7xx_gpio_hwmod_class,
733 .clkdm_name = "l4per_clkdm",
734 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
735 .main_clk = "l3_iclk_div",
736 .prcm = {
737 .omap4 = {
738 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
739 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
740 .modulemode = MODULEMODE_HWCTRL,
741 },
742 },
743 .opt_clks = gpio5_opt_clks,
744 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
745 .dev_attr = &gpio_dev_attr,
746};
747
748/* gpio6 */
749static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
750 { .role = "dbclk", .clk = "gpio6_dbclk" },
751};
752
753static struct omap_hwmod dra7xx_gpio6_hwmod = {
754 .name = "gpio6",
755 .class = &dra7xx_gpio_hwmod_class,
756 .clkdm_name = "l4per_clkdm",
757 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
758 .main_clk = "l3_iclk_div",
759 .prcm = {
760 .omap4 = {
761 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
762 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
763 .modulemode = MODULEMODE_HWCTRL,
764 },
765 },
766 .opt_clks = gpio6_opt_clks,
767 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
768 .dev_attr = &gpio_dev_attr,
769};
770
771/* gpio7 */
772static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
773 { .role = "dbclk", .clk = "gpio7_dbclk" },
774};
775
776static struct omap_hwmod dra7xx_gpio7_hwmod = {
777 .name = "gpio7",
778 .class = &dra7xx_gpio_hwmod_class,
779 .clkdm_name = "l4per_clkdm",
780 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
781 .main_clk = "l3_iclk_div",
782 .prcm = {
783 .omap4 = {
784 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
785 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
786 .modulemode = MODULEMODE_HWCTRL,
787 },
788 },
789 .opt_clks = gpio7_opt_clks,
790 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
791 .dev_attr = &gpio_dev_attr,
792};
793
794/* gpio8 */
795static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
796 { .role = "dbclk", .clk = "gpio8_dbclk" },
797};
798
799static struct omap_hwmod dra7xx_gpio8_hwmod = {
800 .name = "gpio8",
801 .class = &dra7xx_gpio_hwmod_class,
802 .clkdm_name = "l4per_clkdm",
803 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
804 .main_clk = "l3_iclk_div",
805 .prcm = {
806 .omap4 = {
807 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
808 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
809 .modulemode = MODULEMODE_HWCTRL,
810 },
811 },
812 .opt_clks = gpio8_opt_clks,
813 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
814 .dev_attr = &gpio_dev_attr,
815};
816
817/*
818 * 'gpmc' class
819 *
820 */
821
822static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
823 .rev_offs = 0x0000,
824 .sysc_offs = 0x0010,
825 .syss_offs = 0x0014,
826 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
827 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
828 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
829 SIDLE_SMART_WKUP),
830 .sysc_fields = &omap_hwmod_sysc_type1,
831};
832
833static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
834 .name = "gpmc",
835 .sysc = &dra7xx_gpmc_sysc,
836};
837
838/* gpmc */
839
840static struct omap_hwmod dra7xx_gpmc_hwmod = {
841 .name = "gpmc",
842 .class = &dra7xx_gpmc_hwmod_class,
843 .clkdm_name = "l3main1_clkdm",
556708fe
K		 844 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
845 HWMOD_SWSUP_SIDLE),
90020c7b
A		 846 .main_clk = "l3_iclk_div",
847 .prcm = {
848 .omap4 = {
849 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
850 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
851 .modulemode = MODULEMODE_HWCTRL,
852 },
853 },
854};
855
856/*
857 * 'hdq1w' class
858 *
859 */
860
861static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
862 .rev_offs = 0x0000,
863 .sysc_offs = 0x0014,
864 .syss_offs = 0x0018,
865 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
866 SYSS_HAS_RESET_STATUS),
867 .sysc_fields = &omap_hwmod_sysc_type1,
868};
869
870static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
871 .name = "hdq1w",
872 .sysc = &dra7xx_hdq1w_sysc,
873};
874
875/* hdq1w */
876
877static struct omap_hwmod dra7xx_hdq1w_hwmod = {
878 .name = "hdq1w",
879 .class = &dra7xx_hdq1w_hwmod_class,
880 .clkdm_name = "l4per_clkdm",
881 .flags = HWMOD_INIT_NO_RESET,
882 .main_clk = "func_12m_fclk",
883 .prcm = {
884 .omap4 = {
885 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
886 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
887 .modulemode = MODULEMODE_SWCTRL,
888 },
889 },
890};
891
892/*
893 * 'i2c' class
894 *
895 */
896
897static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
898 .sysc_offs = 0x0010,
899 .syss_offs = 0x0090,
900 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
901 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
902 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
903 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
904 SIDLE_SMART_WKUP),
905 .clockact = CLOCKACT_TEST_ICLK,
906 .sysc_fields = &omap_hwmod_sysc_type1,
907};
908
909static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
910 .name = "i2c",
911 .sysc = &dra7xx_i2c_sysc,
912 .reset = &omap_i2c_reset,
913 .rev = OMAP_I2C_IP_VERSION_2,
914};
915
916/* i2c dev_attr */
917static struct omap_i2c_dev_attr i2c_dev_attr = {
918 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
919};
920
921/* i2c1 */
922static struct omap_hwmod dra7xx_i2c1_hwmod = {
923 .name = "i2c1",
924 .class = &dra7xx_i2c_hwmod_class,
925 .clkdm_name = "l4per_clkdm",
926 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
927 .main_clk = "func_96m_fclk",
928 .prcm = {
929 .omap4 = {
930 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
931 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
932 .modulemode = MODULEMODE_SWCTRL,
933 },
934 },
935 .dev_attr = &i2c_dev_attr,
936};
937
938/* i2c2 */
939static struct omap_hwmod dra7xx_i2c2_hwmod = {
940 .name = "i2c2",
941 .class = &dra7xx_i2c_hwmod_class,
942 .clkdm_name = "l4per_clkdm",
943 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
944 .main_clk = "func_96m_fclk",
945 .prcm = {
946 .omap4 = {
947 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
948 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
949 .modulemode = MODULEMODE_SWCTRL,
950 },
951 },
952 .dev_attr = &i2c_dev_attr,
953};
954
955/* i2c3 */
956static struct omap_hwmod dra7xx_i2c3_hwmod = {
957 .name = "i2c3",
958 .class = &dra7xx_i2c_hwmod_class,
959 .clkdm_name = "l4per_clkdm",
960 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
961 .main_clk = "func_96m_fclk",
962 .prcm = {
963 .omap4 = {
964 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
965 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
966 .modulemode = MODULEMODE_SWCTRL,
967 },
968 },
969 .dev_attr = &i2c_dev_attr,
970};
971
972/* i2c4 */
973static struct omap_hwmod dra7xx_i2c4_hwmod = {
974 .name = "i2c4",
975 .class = &dra7xx_i2c_hwmod_class,
976 .clkdm_name = "l4per_clkdm",
977 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
978 .main_clk = "func_96m_fclk",
979 .prcm = {
980 .omap4 = {
981 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
982 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
983 .modulemode = MODULEMODE_SWCTRL,
984 },
985 },
986 .dev_attr = &i2c_dev_attr,
987};
988
989/* i2c5 */
990static struct omap_hwmod dra7xx_i2c5_hwmod = {
991 .name = "i2c5",
992 .class = &dra7xx_i2c_hwmod_class,
993 .clkdm_name = "ipu_clkdm",
994 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
995 .main_clk = "func_96m_fclk",
996 .prcm = {
997 .omap4 = {
998 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
999 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1000 .modulemode = MODULEMODE_SWCTRL,
1001 },
1002 },
1003 .dev_attr = &i2c_dev_attr,
1004};
1005
067395d4
SA		 1006/*
1007 * 'mailbox' class
1008 *
1009 */
1010
1011static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1012 .rev_offs = 0x0000,
1013 .sysc_offs = 0x0010,
1014 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1015 SYSC_HAS_SOFTRESET),
1016 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1017 .sysc_fields = &omap_hwmod_sysc_type2,
1018};
1019
1020static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1021 .name = "mailbox",
1022 .sysc = &dra7xx_mailbox_sysc,
1023};
1024
1025/* mailbox1 */
1026static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1027 .name = "mailbox1",
1028 .class = &dra7xx_mailbox_hwmod_class,
1029 .clkdm_name = "l4cfg_clkdm",
1030 .prcm = {
1031 .omap4 = {
1032 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1033 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1034 },
1035 },
1036};
1037
1038/* mailbox2 */
1039static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1040 .name = "mailbox2",
1041 .class = &dra7xx_mailbox_hwmod_class,
1042 .clkdm_name = "l4cfg_clkdm",
1043 .prcm = {
1044 .omap4 = {
1045 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1046 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1047 },
1048 },
1049};
1050
1051/* mailbox3 */
1052static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1053 .name = "mailbox3",
1054 .class = &dra7xx_mailbox_hwmod_class,
1055 .clkdm_name = "l4cfg_clkdm",
1056 .prcm = {
1057 .omap4 = {
1058 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1059 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1060 },
1061 },
1062};
1063
1064/* mailbox4 */
1065static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1066 .name = "mailbox4",
1067 .class = &dra7xx_mailbox_hwmod_class,
1068 .clkdm_name = "l4cfg_clkdm",
1069 .prcm = {
1070 .omap4 = {
1071 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1072 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1073 },
1074 },
1075};
1076
1077/* mailbox5 */
1078static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1079 .name = "mailbox5",
1080 .class = &dra7xx_mailbox_hwmod_class,
1081 .clkdm_name = "l4cfg_clkdm",
1082 .prcm = {
1083 .omap4 = {
1084 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1085 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1086 },
1087 },
1088};
1089
1090/* mailbox6 */
1091static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1092 .name = "mailbox6",
1093 .class = &dra7xx_mailbox_hwmod_class,
1094 .clkdm_name = "l4cfg_clkdm",
1095 .prcm = {
1096 .omap4 = {
1097 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1098 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1099 },
1100 },
1101};
1102
1103/* mailbox7 */
1104static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1105 .name = "mailbox7",
1106 .class = &dra7xx_mailbox_hwmod_class,
1107 .clkdm_name = "l4cfg_clkdm",
1108 .prcm = {
1109 .omap4 = {
1110 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1111 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1112 },
1113 },
1114};
1115
1116/* mailbox8 */
1117static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1118 .name = "mailbox8",
1119 .class = &dra7xx_mailbox_hwmod_class,
1120 .clkdm_name = "l4cfg_clkdm",
1121 .prcm = {
1122 .omap4 = {
1123 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1124 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1125 },
1126 },
1127};
1128
1129/* mailbox9 */
1130static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1131 .name = "mailbox9",
1132 .class = &dra7xx_mailbox_hwmod_class,
1133 .clkdm_name = "l4cfg_clkdm",
1134 .prcm = {
1135 .omap4 = {
1136 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1137 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1138 },
1139 },
1140};
1141
1142/* mailbox10 */
1143static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1144 .name = "mailbox10",
1145 .class = &dra7xx_mailbox_hwmod_class,
1146 .clkdm_name = "l4cfg_clkdm",
1147 .prcm = {
1148 .omap4 = {
1149 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1150 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1151 },
1152 },
1153};
1154
1155/* mailbox11 */
1156static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1157 .name = "mailbox11",
1158 .class = &dra7xx_mailbox_hwmod_class,
1159 .clkdm_name = "l4cfg_clkdm",
1160 .prcm = {
1161 .omap4 = {
1162 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1163 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1164 },
1165 },
1166};
1167
1168/* mailbox12 */
1169static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1170 .name = "mailbox12",
1171 .class = &dra7xx_mailbox_hwmod_class,
1172 .clkdm_name = "l4cfg_clkdm",
1173 .prcm = {
1174 .omap4 = {
1175 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1176 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1177 },
1178 },
1179};
1180
1181/* mailbox13 */
1182static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1183 .name = "mailbox13",
1184 .class = &dra7xx_mailbox_hwmod_class,
1185 .clkdm_name = "l4cfg_clkdm",
1186 .prcm = {
1187 .omap4 = {
1188 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1189 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1190 },
1191 },
1192};
1193
90020c7b
A		 1194/*
1195 * 'mcspi' class
1196 *
1197 */
1198
1199static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1200 .rev_offs = 0x0000,
1201 .sysc_offs = 0x0010,
1202 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1203 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1204 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1205 SIDLE_SMART_WKUP),
1206 .sysc_fields = &omap_hwmod_sysc_type2,
1207};
1208
1209static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1210 .name = "mcspi",
1211 .sysc = &dra7xx_mcspi_sysc,
1212 .rev = OMAP4_MCSPI_REV,
1213};
1214
1215/* mcspi1 */
1216/* mcspi1 dev_attr */
1217static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1218 .num_chipselect = 4,
1219};
1220
1221static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1222 .name = "mcspi1",
1223 .class = &dra7xx_mcspi_hwmod_class,
1224 .clkdm_name = "l4per_clkdm",
1225 .main_clk = "func_48m_fclk",
1226 .prcm = {
1227 .omap4 = {
1228 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1229 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1230 .modulemode = MODULEMODE_SWCTRL,
1231 },
1232 },
1233 .dev_attr = &mcspi1_dev_attr,
1234};
1235
1236/* mcspi2 */
1237/* mcspi2 dev_attr */
1238static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1239 .num_chipselect = 2,
1240};
1241
1242static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1243 .name = "mcspi2",
1244 .class = &dra7xx_mcspi_hwmod_class,
1245 .clkdm_name = "l4per_clkdm",
1246 .main_clk = "func_48m_fclk",
1247 .prcm = {
1248 .omap4 = {
1249 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1250 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1251 .modulemode = MODULEMODE_SWCTRL,
1252 },
1253 },
1254 .dev_attr = &mcspi2_dev_attr,
1255};
1256
1257/* mcspi3 */
1258/* mcspi3 dev_attr */
1259static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1260 .num_chipselect = 2,
1261};
1262
1263static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1264 .name = "mcspi3",
1265 .class = &dra7xx_mcspi_hwmod_class,
1266 .clkdm_name = "l4per_clkdm",
1267 .main_clk = "func_48m_fclk",
1268 .prcm = {
1269 .omap4 = {
1270 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1271 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1272 .modulemode = MODULEMODE_SWCTRL,
1273 },
1274 },
1275 .dev_attr = &mcspi3_dev_attr,
1276};
1277
1278/* mcspi4 */
1279/* mcspi4 dev_attr */
1280static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1281 .num_chipselect = 1,
1282};
1283
1284static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1285 .name = "mcspi4",
1286 .class = &dra7xx_mcspi_hwmod_class,
1287 .clkdm_name = "l4per_clkdm",
1288 .main_clk = "func_48m_fclk",
1289 .prcm = {
1290 .omap4 = {
1291 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1292 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1293 .modulemode = MODULEMODE_SWCTRL,
1294 },
1295 },
1296 .dev_attr = &mcspi4_dev_attr,
1297};
1298
1299/*
1300 * 'mmc' class
1301 *
1302 */
1303
1304static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1305 .rev_offs = 0x0000,
1306 .sysc_offs = 0x0010,
1307 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1308 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1309 SYSC_HAS_SOFTRESET),
1310 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1311 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1312 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1313 .sysc_fields = &omap_hwmod_sysc_type2,
1314};
1315
1316static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1317 .name = "mmc",
1318 .sysc = &dra7xx_mmc_sysc,
1319};
1320
1321/* mmc1 */
1322static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1323 { .role = "clk32k", .clk = "mmc1_clk32k" },
1324};
1325
1326/* mmc1 dev_attr */
55143438 1327static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
90020c7b
A		 1328 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1329};
1330
1331static struct omap_hwmod dra7xx_mmc1_hwmod = {
1332 .name = "mmc1",
1333 .class = &dra7xx_mmc_hwmod_class,
1334 .clkdm_name = "l3init_clkdm",
1335 .main_clk = "mmc1_fclk_div",
1336 .prcm = {
1337 .omap4 = {
1338 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1339 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1340 .modulemode = MODULEMODE_SWCTRL,
1341 },
1342 },
1343 .opt_clks = mmc1_opt_clks,
1344 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1345 .dev_attr = &mmc1_dev_attr,
1346};
1347
1348/* mmc2 */
1349static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1350 { .role = "clk32k", .clk = "mmc2_clk32k" },
1351};
1352
1353static struct omap_hwmod dra7xx_mmc2_hwmod = {
1354 .name = "mmc2",
1355 .class = &dra7xx_mmc_hwmod_class,
1356 .clkdm_name = "l3init_clkdm",
1357 .main_clk = "mmc2_fclk_div",
1358 .prcm = {
1359 .omap4 = {
1360 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1361 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1362 .modulemode = MODULEMODE_SWCTRL,
1363 },
1364 },
1365 .opt_clks = mmc2_opt_clks,
1366 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1367};
1368
1369/* mmc3 */
1370static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1371 { .role = "clk32k", .clk = "mmc3_clk32k" },
1372};
1373
1374static struct omap_hwmod dra7xx_mmc3_hwmod = {
1375 .name = "mmc3",
1376 .class = &dra7xx_mmc_hwmod_class,
1377 .clkdm_name = "l4per_clkdm",
1378 .main_clk = "mmc3_gfclk_div",
1379 .prcm = {
1380 .omap4 = {
1381 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1382 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1383 .modulemode = MODULEMODE_SWCTRL,
1384 },
1385 },
1386 .opt_clks = mmc3_opt_clks,
1387 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1388};
1389
1390/* mmc4 */
1391static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1392 { .role = "clk32k", .clk = "mmc4_clk32k" },
1393};
1394
1395static struct omap_hwmod dra7xx_mmc4_hwmod = {
1396 .name = "mmc4",
1397 .class = &dra7xx_mmc_hwmod_class,
1398 .clkdm_name = "l4per_clkdm",
1399 .main_clk = "mmc4_gfclk_div",
1400 .prcm = {
1401 .omap4 = {
1402 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1403 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1404 .modulemode = MODULEMODE_SWCTRL,
1405 },
1406 },
1407 .opt_clks = mmc4_opt_clks,
1408 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1409};
1410
1411/*
1412 * 'mpu' class
1413 *
1414 */
1415
1416static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1417 .name = "mpu",
1418};
1419
1420/* mpu */
1421static struct omap_hwmod dra7xx_mpu_hwmod = {
1422 .name = "mpu",
1423 .class = &dra7xx_mpu_hwmod_class,
1424 .clkdm_name = "mpu_clkdm",
1425 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1426 .main_clk = "dpll_mpu_m2_ck",
1427 .prcm = {
1428 .omap4 = {
1429 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1430 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1431 },
1432 },
1433};
1434
1435/*
1436 * 'ocp2scp' class
1437 *
1438 */
1439
1440static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1441 .rev_offs = 0x0000,
1442 .sysc_offs = 0x0010,
1443 .syss_offs = 0x0014,
1444 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1445 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1446 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1447 SIDLE_SMART_WKUP),
1448 .sysc_fields = &omap_hwmod_sysc_type1,
1449};
1450
1451static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1452 .name = "ocp2scp",
1453 .sysc = &dra7xx_ocp2scp_sysc,
1454};
1455
1456/* ocp2scp1 */
1457static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1458 .name = "ocp2scp1",
1459 .class = &dra7xx_ocp2scp_hwmod_class,
1460 .clkdm_name = "l3init_clkdm",
1461 .main_clk = "l4_root_clk_div",
1462 .prcm = {
1463 .omap4 = {
1464 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1465 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1466 .modulemode = MODULEMODE_HWCTRL,
1467 },
1468 },
1469};
1470
df0d0f11
RQ		 1471/* ocp2scp3 */
1472static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1473 .name = "ocp2scp3",
1474 .class = &dra7xx_ocp2scp_hwmod_class,
1475 .clkdm_name = "l3init_clkdm",
1476 .main_clk = "l4_root_clk_div",
1477 .prcm = {
1478 .omap4 = {
1479 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1480 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1481 .modulemode = MODULEMODE_HWCTRL,
1482 },
1483 },
1484};
1485
8dd3eb71
KVA		 1486/*
1487 * 'PCIE' class
1488 *
1489 */
1490
0717103e 1491static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
8dd3eb71
KVA		 1492 .name = "pcie",
1493};
1494
1495/* pcie1 */
0717103e 1496static struct omap_hwmod dra7xx_pciess1_hwmod = {
8dd3eb71 1497 .name = "pcie1",
0717103e 1498 .class = &dra7xx_pciess_hwmod_class,
8dd3eb71
KVA		 1499 .clkdm_name = "pcie_clkdm",
1500 .main_clk = "l4_root_clk_div",
70c18ef7
KVA		 1501 .prcm = {
1502 .omap4 = {
1503 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1504 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1505 .modulemode = MODULEMODE_SWCTRL,
1506 },
1507 },
1508};
1509
0717103e
KVA		 1510/* pcie2 */
1511static struct omap_hwmod dra7xx_pciess2_hwmod = {
1512 .name = "pcie2",
1513 .class = &dra7xx_pciess_hwmod_class,
1514 .clkdm_name = "pcie_clkdm",
70c18ef7
KVA		 1515 .main_clk = "l4_root_clk_div",
1516 .prcm = {
1517 .omap4 = {
1518 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1519 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1520 .modulemode = MODULEMODE_SWCTRL,
1521 },
1522 },
1523};
1524
90020c7b
A		 1525/*
1526 * 'qspi' class
1527 *
1528 */
1529
1530static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1531 .sysc_offs = 0x0010,
1532 .sysc_flags = SYSC_HAS_SIDLEMODE,
1533 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1534 SIDLE_SMART_WKUP),
1535 .sysc_fields = &omap_hwmod_sysc_type2,
1536};
1537
1538static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1539 .name = "qspi",
1540 .sysc = &dra7xx_qspi_sysc,
1541};
1542
1543/* qspi */
1544static struct omap_hwmod dra7xx_qspi_hwmod = {
1545 .name = "qspi",
1546 .class = &dra7xx_qspi_hwmod_class,
1547 .clkdm_name = "l4per2_clkdm",
1548 .main_clk = "qspi_gfclk_div",
1549 .prcm = {
1550 .omap4 = {
1551 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1552 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1553 .modulemode = MODULEMODE_SWCTRL,
1554 },
1555 },
1556};
1557
c913c8a1
LV		 1558/*
1559 * 'rtcss' class
1560 *
1561 */
1562static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1563 .sysc_offs = 0x0078,
1564 .sysc_flags = SYSC_HAS_SIDLEMODE,
1565 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1566 SIDLE_SMART_WKUP),
1567 .sysc_fields = &omap_hwmod_sysc_type3,
1568};
1569
1570static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1571 .name = "rtcss",
1572 .sysc = &dra7xx_rtcss_sysc,
1573};
1574
1575/* rtcss */
1576static struct omap_hwmod dra7xx_rtcss_hwmod = {
1577 .name = "rtcss",
1578 .class = &dra7xx_rtcss_hwmod_class,
1579 .clkdm_name = "rtc_clkdm",
1580 .main_clk = "sys_32k_ck",
1581 .prcm = {
1582 .omap4 = {
1583 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1584 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1585 .modulemode = MODULEMODE_SWCTRL,
1586 },
1587 },
1588};
1589
90020c7b
A		 1590/*
1591 * 'sata' class
1592 *
1593 */
1594
1595static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1596 .sysc_offs = 0x0000,
1597 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1598 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1599 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1600 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1601 .sysc_fields = &omap_hwmod_sysc_type2,
1602};
1603
1604static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1605 .name = "sata",
1606 .sysc = &dra7xx_sata_sysc,
1607};
1608
1609/* sata */
90020c7b
A		 1610
1611static struct omap_hwmod dra7xx_sata_hwmod = {
1612 .name = "sata",
1613 .class = &dra7xx_sata_hwmod_class,
1614 .clkdm_name = "l3init_clkdm",
1615 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1616 .main_clk = "func_48m_fclk",
1ea0999e 1617 .mpu_rt_idx = 1,
90020c7b
A		 1618 .prcm = {
1619 .omap4 = {
1620 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1621 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1622 .modulemode = MODULEMODE_SWCTRL,
1623 },
1624 },
90020c7b
A		 1625};
1626
1627/*
1628 * 'smartreflex' class
1629 *
1630 */
1631
1632/* The IP is not compliant to type1 / type2 scheme */
1633static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1634 .sidle_shift = 24,
1635 .enwkup_shift = 26,
1636};
1637
1638static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1639 .sysc_offs = 0x0038,
1640 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1641 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1642 SIDLE_SMART_WKUP),
1643 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1644};
1645
1646static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1647 .name = "smartreflex",
1648 .sysc = &dra7xx_smartreflex_sysc,
1649 .rev = 2,
1650};
1651
1652/* smartreflex_core */
1653/* smartreflex_core dev_attr */
1654static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1655 .sensor_voltdm_name = "core",
1656};
1657
1658static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1659 .name = "smartreflex_core",
1660 .class = &dra7xx_smartreflex_hwmod_class,
1661 .clkdm_name = "coreaon_clkdm",
1662 .main_clk = "wkupaon_iclk_mux",
1663 .prcm = {
1664 .omap4 = {
1665 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1666 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1667 .modulemode = MODULEMODE_SWCTRL,
1668 },
1669 },
1670 .dev_attr = &smartreflex_core_dev_attr,
1671};
1672
1673/* smartreflex_mpu */
1674/* smartreflex_mpu dev_attr */
1675static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1676 .sensor_voltdm_name = "mpu",
1677};
1678
1679static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1680 .name = "smartreflex_mpu",
1681 .class = &dra7xx_smartreflex_hwmod_class,
1682 .clkdm_name = "coreaon_clkdm",
1683 .main_clk = "wkupaon_iclk_mux",
1684 .prcm = {
1685 .omap4 = {
1686 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1687 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1688 .modulemode = MODULEMODE_SWCTRL,
1689 },
1690 },
1691 .dev_attr = &smartreflex_mpu_dev_attr,
1692};
1693
1694/*
1695 * 'spinlock' class
1696 *
1697 */
1698
1699static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1700 .rev_offs = 0x0000,
1701 .sysc_offs = 0x0010,
1702 .syss_offs = 0x0014,
c317d0f2
SA		 1703 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1704 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1705 SYSS_HAS_RESET_STATUS),
1706 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
90020c7b
A		 1707 .sysc_fields = &omap_hwmod_sysc_type1,
1708};
1709
1710static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1711 .name = "spinlock",
1712 .sysc = &dra7xx_spinlock_sysc,
1713};
1714
1715/* spinlock */
1716static struct omap_hwmod dra7xx_spinlock_hwmod = {
1717 .name = "spinlock",
1718 .class = &dra7xx_spinlock_hwmod_class,
1719 .clkdm_name = "l4cfg_clkdm",
1720 .main_clk = "l3_iclk_div",
1721 .prcm = {
1722 .omap4 = {
1723 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1724 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1725 },
1726 },
1727};
1728
1729/*
1730 * 'timer' class
1731 *
1732 * This class contains several variants: ['timer_1ms', 'timer_secure',
1733 * 'timer']
1734 */
1735
1736static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1737 .rev_offs = 0x0000,
1738 .sysc_offs = 0x0010,
1739 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1740 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1741 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1742 SIDLE_SMART_WKUP),
1743 .sysc_fields = &omap_hwmod_sysc_type2,
1744};
1745
1746static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1747 .name = "timer",
1748 .sysc = &dra7xx_timer_1ms_sysc,
1749};
1750
90020c7b
A		 1751static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1752 .rev_offs = 0x0000,
1753 .sysc_offs = 0x0010,
1754 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1755 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1756 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1757 SIDLE_SMART_WKUP),
1758 .sysc_fields = &omap_hwmod_sysc_type2,
1759};
1760
1761static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1762 .name = "timer",
1763 .sysc = &dra7xx_timer_sysc,
1764};
1765
1766/* timer1 */
1767static struct omap_hwmod dra7xx_timer1_hwmod = {
1768 .name = "timer1",
1769 .class = &dra7xx_timer_1ms_hwmod_class,
1770 .clkdm_name = "wkupaon_clkdm",
1771 .main_clk = "timer1_gfclk_mux",
1772 .prcm = {
1773 .omap4 = {
1774 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1775 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1776 .modulemode = MODULEMODE_SWCTRL,
1777 },
1778 },
1779};
1780
1781/* timer2 */
1782static struct omap_hwmod dra7xx_timer2_hwmod = {
1783 .name = "timer2",
1784 .class = &dra7xx_timer_1ms_hwmod_class,
1785 .clkdm_name = "l4per_clkdm",
1786 .main_clk = "timer2_gfclk_mux",
1787 .prcm = {
1788 .omap4 = {
1789 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1790 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1791 .modulemode = MODULEMODE_SWCTRL,
1792 },
1793 },
1794};
1795
1796/* timer3 */
1797static struct omap_hwmod dra7xx_timer3_hwmod = {
1798 .name = "timer3",
1799 .class = &dra7xx_timer_hwmod_class,
1800 .clkdm_name = "l4per_clkdm",
1801 .main_clk = "timer3_gfclk_mux",
1802 .prcm = {
1803 .omap4 = {
1804 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1805 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1806 .modulemode = MODULEMODE_SWCTRL,
1807 },
1808 },
1809};
1810
1811/* timer4 */
1812static struct omap_hwmod dra7xx_timer4_hwmod = {
1813 .name = "timer4",
edec1786 1814 .class = &dra7xx_timer_hwmod_class,
90020c7b
A		 1815 .clkdm_name = "l4per_clkdm",
1816 .main_clk = "timer4_gfclk_mux",
1817 .prcm = {
1818 .omap4 = {
1819 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1820 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1821 .modulemode = MODULEMODE_SWCTRL,
1822 },
1823 },
1824};
1825
1826/* timer5 */
1827static struct omap_hwmod dra7xx_timer5_hwmod = {
1828 .name = "timer5",
1829 .class = &dra7xx_timer_hwmod_class,
1830 .clkdm_name = "ipu_clkdm",
1831 .main_clk = "timer5_gfclk_mux",
1832 .prcm = {
1833 .omap4 = {
1834 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1835 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1836 .modulemode = MODULEMODE_SWCTRL,
1837 },
1838 },
1839};
1840
1841/* timer6 */
1842static struct omap_hwmod dra7xx_timer6_hwmod = {
1843 .name = "timer6",
1844 .class = &dra7xx_timer_hwmod_class,
1845 .clkdm_name = "ipu_clkdm",
1846 .main_clk = "timer6_gfclk_mux",
1847 .prcm = {
1848 .omap4 = {
1849 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1850 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1851 .modulemode = MODULEMODE_SWCTRL,
1852 },
1853 },
1854};
1855
1856/* timer7 */
1857static struct omap_hwmod dra7xx_timer7_hwmod = {
1858 .name = "timer7",
1859 .class = &dra7xx_timer_hwmod_class,
1860 .clkdm_name = "ipu_clkdm",
1861 .main_clk = "timer7_gfclk_mux",
1862 .prcm = {
1863 .omap4 = {
1864 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1865 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1866 .modulemode = MODULEMODE_SWCTRL,
1867 },
1868 },
1869};
1870
1871/* timer8 */
1872static struct omap_hwmod dra7xx_timer8_hwmod = {
1873 .name = "timer8",
1874 .class = &dra7xx_timer_hwmod_class,
1875 .clkdm_name = "ipu_clkdm",
1876 .main_clk = "timer8_gfclk_mux",
1877 .prcm = {
1878 .omap4 = {
1879 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1880 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1881 .modulemode = MODULEMODE_SWCTRL,
1882 },
1883 },
1884};
1885
1886/* timer9 */
1887static struct omap_hwmod dra7xx_timer9_hwmod = {
1888 .name = "timer9",
1889 .class = &dra7xx_timer_hwmod_class,
1890 .clkdm_name = "l4per_clkdm",
1891 .main_clk = "timer9_gfclk_mux",
1892 .prcm = {
1893 .omap4 = {
1894 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1895 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1896 .modulemode = MODULEMODE_SWCTRL,
1897 },
1898 },
1899};
1900
1901/* timer10 */
1902static struct omap_hwmod dra7xx_timer10_hwmod = {
1903 .name = "timer10",
1904 .class = &dra7xx_timer_1ms_hwmod_class,
1905 .clkdm_name = "l4per_clkdm",
1906 .main_clk = "timer10_gfclk_mux",
1907 .prcm = {
1908 .omap4 = {
1909 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1910 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1911 .modulemode = MODULEMODE_SWCTRL,
1912 },
1913 },
1914};
1915
1916/* timer11 */
1917static struct omap_hwmod dra7xx_timer11_hwmod = {
1918 .name = "timer11",
1919 .class = &dra7xx_timer_hwmod_class,
1920 .clkdm_name = "l4per_clkdm",
1921 .main_clk = "timer11_gfclk_mux",
1922 .prcm = {
1923 .omap4 = {
1924 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1925 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1926 .modulemode = MODULEMODE_SWCTRL,
1927 },
1928 },
1929};
1930
1ac964f4
SA		 1931/* timer13 */
1932static struct omap_hwmod dra7xx_timer13_hwmod = {
1933 .name = "timer13",
1934 .class = &dra7xx_timer_hwmod_class,
1935 .clkdm_name = "l4per3_clkdm",
1936 .main_clk = "timer13_gfclk_mux",
1937 .prcm = {
1938 .omap4 = {
1939 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
1940 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
1941 .modulemode = MODULEMODE_SWCTRL,
1942 },
1943 },
1944};
1945
1946/* timer14 */
1947static struct omap_hwmod dra7xx_timer14_hwmod = {
1948 .name = "timer14",
1949 .class = &dra7xx_timer_hwmod_class,
1950 .clkdm_name = "l4per3_clkdm",
1951 .main_clk = "timer14_gfclk_mux",
1952 .prcm = {
1953 .omap4 = {
1954 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
1955 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
1956 .modulemode = MODULEMODE_SWCTRL,
1957 },
1958 },
1959};
1960
1961/* timer15 */
1962static struct omap_hwmod dra7xx_timer15_hwmod = {
1963 .name = "timer15",
1964 .class = &dra7xx_timer_hwmod_class,
1965 .clkdm_name = "l4per3_clkdm",
1966 .main_clk = "timer15_gfclk_mux",
1967 .prcm = {
1968 .omap4 = {
1969 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
1970 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
1971 .modulemode = MODULEMODE_SWCTRL,
1972 },
1973 },
1974};
1975
1976/* timer16 */
1977static struct omap_hwmod dra7xx_timer16_hwmod = {
1978 .name = "timer16",
1979 .class = &dra7xx_timer_hwmod_class,
1980 .clkdm_name = "l4per3_clkdm",
1981 .main_clk = "timer16_gfclk_mux",
1982 .prcm = {
1983 .omap4 = {
1984 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
1985 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
1986 .modulemode = MODULEMODE_SWCTRL,
1987 },
1988 },
1989};
1990
90020c7b
A		 1991/*
1992 * 'uart' class
1993 *
1994 */
1995
1996static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
1997 .rev_offs = 0x0050,
1998 .sysc_offs = 0x0054,
1999 .syss_offs = 0x0058,
2000 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2001 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2002 SYSS_HAS_RESET_STATUS),
2003 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2004 SIDLE_SMART_WKUP),
2005 .sysc_fields = &omap_hwmod_sysc_type1,
2006};
2007
2008static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2009 .name = "uart",
2010 .sysc = &dra7xx_uart_sysc,
2011};
2012
2013/* uart1 */
2014static struct omap_hwmod dra7xx_uart1_hwmod = {
2015 .name = "uart1",
2016 .class = &dra7xx_uart_hwmod_class,
2017 .clkdm_name = "l4per_clkdm",
2018 .main_clk = "uart1_gfclk_mux",
38958c15 2019 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
90020c7b
A		 2020 .prcm = {
2021 .omap4 = {
2022 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2023 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2024 .modulemode = MODULEMODE_SWCTRL,
2025 },
2026 },
2027};
2028
2029/* uart2 */
2030static struct omap_hwmod dra7xx_uart2_hwmod = {
2031 .name = "uart2",
2032 .class = &dra7xx_uart_hwmod_class,
2033 .clkdm_name = "l4per_clkdm",
2034 .main_clk = "uart2_gfclk_mux",
2035 .flags = HWMOD_SWSUP_SIDLE_ACT,
2036 .prcm = {
2037 .omap4 = {
2038 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2039 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2040 .modulemode = MODULEMODE_SWCTRL,
2041 },
2042 },
2043};
2044
2045/* uart3 */
2046static struct omap_hwmod dra7xx_uart3_hwmod = {
2047 .name = "uart3",
2048 .class = &dra7xx_uart_hwmod_class,
2049 .clkdm_name = "l4per_clkdm",
2050 .main_clk = "uart3_gfclk_mux",
1c7e36bf 2051 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
90020c7b
A		 2052 .prcm = {
2053 .omap4 = {
2054 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2055 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2056 .modulemode = MODULEMODE_SWCTRL,
2057 },
2058 },
2059};
2060
2061/* uart4 */
2062static struct omap_hwmod dra7xx_uart4_hwmod = {
2063 .name = "uart4",
2064 .class = &dra7xx_uart_hwmod_class,
2065 .clkdm_name = "l4per_clkdm",
2066 .main_clk = "uart4_gfclk_mux",
2067 .flags = HWMOD_SWSUP_SIDLE_ACT,
2068 .prcm = {
2069 .omap4 = {
2070 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2071 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2072 .modulemode = MODULEMODE_SWCTRL,
2073 },
2074 },
2075};
2076
2077/* uart5 */
2078static struct omap_hwmod dra7xx_uart5_hwmod = {
2079 .name = "uart5",
2080 .class = &dra7xx_uart_hwmod_class,
2081 .clkdm_name = "l4per_clkdm",
2082 .main_clk = "uart5_gfclk_mux",
2083 .flags = HWMOD_SWSUP_SIDLE_ACT,
2084 .prcm = {
2085 .omap4 = {
2086 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2087 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2088 .modulemode = MODULEMODE_SWCTRL,
2089 },
2090 },
2091};
2092
2093/* uart6 */
2094static struct omap_hwmod dra7xx_uart6_hwmod = {
2095 .name = "uart6",
2096 .class = &dra7xx_uart_hwmod_class,
2097 .clkdm_name = "ipu_clkdm",
2098 .main_clk = "uart6_gfclk_mux",
2099 .flags = HWMOD_SWSUP_SIDLE_ACT,
2100 .prcm = {
2101 .omap4 = {
2102 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2103 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2104 .modulemode = MODULEMODE_SWCTRL,
2105 },
2106 },
2107};
2108
33acc9ff
A		 2109/* uart7 */
2110static struct omap_hwmod dra7xx_uart7_hwmod = {
2111 .name = "uart7",
2112 .class = &dra7xx_uart_hwmod_class,
2113 .clkdm_name = "l4per2_clkdm",
2114 .main_clk = "uart7_gfclk_mux",
2115 .flags = HWMOD_SWSUP_SIDLE_ACT,
2116 .prcm = {
2117 .omap4 = {
2118 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2119 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2120 .modulemode = MODULEMODE_SWCTRL,
2121 },
2122 },
2123};
2124
2125/* uart8 */
2126static struct omap_hwmod dra7xx_uart8_hwmod = {
2127 .name = "uart8",
2128 .class = &dra7xx_uart_hwmod_class,
2129 .clkdm_name = "l4per2_clkdm",
2130 .main_clk = "uart8_gfclk_mux",
2131 .flags = HWMOD_SWSUP_SIDLE_ACT,
2132 .prcm = {
2133 .omap4 = {
2134 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2135 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2136 .modulemode = MODULEMODE_SWCTRL,
2137 },
2138 },
2139};
2140
2141/* uart9 */
2142static struct omap_hwmod dra7xx_uart9_hwmod = {
2143 .name = "uart9",
2144 .class = &dra7xx_uart_hwmod_class,
2145 .clkdm_name = "l4per2_clkdm",
2146 .main_clk = "uart9_gfclk_mux",
2147 .flags = HWMOD_SWSUP_SIDLE_ACT,
2148 .prcm = {
2149 .omap4 = {
2150 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2151 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2152 .modulemode = MODULEMODE_SWCTRL,
2153 },
2154 },
2155};
2156
2157/* uart10 */
2158static struct omap_hwmod dra7xx_uart10_hwmod = {
2159 .name = "uart10",
2160 .class = &dra7xx_uart_hwmod_class,
2161 .clkdm_name = "wkupaon_clkdm",
2162 .main_clk = "uart10_gfclk_mux",
2163 .flags = HWMOD_SWSUP_SIDLE_ACT,
2164 .prcm = {
2165 .omap4 = {
2166 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2167 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2168 .modulemode = MODULEMODE_SWCTRL,
2169 },
2170 },
2171};
2172
90020c7b
A		 2173/*
2174 * 'usb_otg_ss' class
2175 *
2176 */
2177
d904b38d
RQ		 2178static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2179 .rev_offs = 0x0000,
2180 .sysc_offs = 0x0010,
2181 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2182 SYSC_HAS_SIDLEMODE),
2183 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2184 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2185 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2186 .sysc_fields = &omap_hwmod_sysc_type2,
2187};
2188
90020c7b
A		 2189static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2190 .name = "usb_otg_ss",
d904b38d 2191 .sysc = &dra7xx_usb_otg_ss_sysc,
90020c7b
A		 2192};
2193
2194/* usb_otg_ss1 */
2195static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2196 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2197};
2198
2199static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2200 .name = "usb_otg_ss1",
2201 .class = &dra7xx_usb_otg_ss_hwmod_class,
2202 .clkdm_name = "l3init_clkdm",
2203 .main_clk = "dpll_core_h13x2_ck",
2204 .prcm = {
2205 .omap4 = {
2206 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2207 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2208 .modulemode = MODULEMODE_HWCTRL,
2209 },
2210 },
2211 .opt_clks = usb_otg_ss1_opt_clks,
2212 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2213};
2214
2215/* usb_otg_ss2 */
2216static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2217 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2218};
2219
2220static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2221 .name = "usb_otg_ss2",
2222 .class = &dra7xx_usb_otg_ss_hwmod_class,
2223 .clkdm_name = "l3init_clkdm",
2224 .main_clk = "dpll_core_h13x2_ck",
2225 .prcm = {
2226 .omap4 = {
2227 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2228 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2229 .modulemode = MODULEMODE_HWCTRL,
2230 },
2231 },
2232 .opt_clks = usb_otg_ss2_opt_clks,
2233 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2234};
2235
2236/* usb_otg_ss3 */
2237static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2238 .name = "usb_otg_ss3",
2239 .class = &dra7xx_usb_otg_ss_hwmod_class,
2240 .clkdm_name = "l3init_clkdm",
2241 .main_clk = "dpll_core_h13x2_ck",
2242 .prcm = {
2243 .omap4 = {
2244 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2245 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2246 .modulemode = MODULEMODE_HWCTRL,
2247 },
2248 },
2249};
2250
2251/* usb_otg_ss4 */
2252static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2253 .name = "usb_otg_ss4",
2254 .class = &dra7xx_usb_otg_ss_hwmod_class,
2255 .clkdm_name = "l3init_clkdm",
2256 .main_clk = "dpll_core_h13x2_ck",
2257 .prcm = {
2258 .omap4 = {
2259 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2260 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2261 .modulemode = MODULEMODE_HWCTRL,
2262 },
2263 },
2264};
2265
2266/*
2267 * 'vcp' class
2268 *
2269 */
2270
2271static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2272 .name = "vcp",
2273};
2274
2275/* vcp1 */
2276static struct omap_hwmod dra7xx_vcp1_hwmod = {
2277 .name = "vcp1",
2278 .class = &dra7xx_vcp_hwmod_class,
2279 .clkdm_name = "l3main1_clkdm",
2280 .main_clk = "l3_iclk_div",
2281 .prcm = {
2282 .omap4 = {
2283 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2284 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2285 },
2286 },
2287};
2288
2289/* vcp2 */
2290static struct omap_hwmod dra7xx_vcp2_hwmod = {
2291 .name = "vcp2",
2292 .class = &dra7xx_vcp_hwmod_class,
2293 .clkdm_name = "l3main1_clkdm",
2294 .main_clk = "l3_iclk_div",
2295 .prcm = {
2296 .omap4 = {
2297 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2298 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2299 },
2300 },
2301};
2302
2303/*
2304 * 'wd_timer' class
2305 *
2306 */
2307
2308static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2309 .rev_offs = 0x0000,
2310 .sysc_offs = 0x0010,
2311 .syss_offs = 0x0014,
2312 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2313 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2314 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2315 SIDLE_SMART_WKUP),
2316 .sysc_fields = &omap_hwmod_sysc_type1,
2317};
2318
2319static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2320 .name = "wd_timer",
2321 .sysc = &dra7xx_wd_timer_sysc,
2322 .pre_shutdown = &omap2_wd_timer_disable,
2323 .reset = &omap2_wd_timer_reset,
2324};
2325
2326/* wd_timer2 */
2327static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2328 .name = "wd_timer2",
2329 .class = &dra7xx_wd_timer_hwmod_class,
2330 .clkdm_name = "wkupaon_clkdm",
2331 .main_clk = "sys_32k_ck",
2332 .prcm = {
2333 .omap4 = {
2334 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2335 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2336 .modulemode = MODULEMODE_SWCTRL,
2337 },
2338 },
2339};
2340
2341
2342/*
2343 * Interfaces
2344 */
2345
42121688
TV		 2346/* l3_main_1 -> dmm */
2347static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2348 .master = &dra7xx_l3_main_1_hwmod,
2349 .slave = &dra7xx_dmm_hwmod,
2350 .clk = "l3_iclk_div",
2351 .user = OCP_USER_SDMA,
2352};
2353
90020c7b
A		 2354/* l3_main_2 -> l3_instr */
2355static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2356 .master = &dra7xx_l3_main_2_hwmod,
2357 .slave = &dra7xx_l3_instr_hwmod,
2358 .clk = "l3_iclk_div",
2359 .user = OCP_USER_MPU | OCP_USER_SDMA,
2360};
2361
2362/* l4_cfg -> l3_main_1 */
2363static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2364 .master = &dra7xx_l4_cfg_hwmod,
2365 .slave = &dra7xx_l3_main_1_hwmod,
2366 .clk = "l3_iclk_div",
2367 .user = OCP_USER_MPU | OCP_USER_SDMA,
2368};
2369
2370/* mpu -> l3_main_1 */
2371static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2372 .master = &dra7xx_mpu_hwmod,
2373 .slave = &dra7xx_l3_main_1_hwmod,
2374 .clk = "l3_iclk_div",
2375 .user = OCP_USER_MPU,
2376};
2377
2378/* l3_main_1 -> l3_main_2 */
2379static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2380 .master = &dra7xx_l3_main_1_hwmod,
2381 .slave = &dra7xx_l3_main_2_hwmod,
2382 .clk = "l3_iclk_div",
2383 .user = OCP_USER_MPU,
2384};
2385
2386/* l4_cfg -> l3_main_2 */
2387static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2388 .master = &dra7xx_l4_cfg_hwmod,
2389 .slave = &dra7xx_l3_main_2_hwmod,
2390 .clk = "l3_iclk_div",
2391 .user = OCP_USER_MPU | OCP_USER_SDMA,
2392};
2393
2394/* l3_main_1 -> l4_cfg */
2395static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2396 .master = &dra7xx_l3_main_1_hwmod,
2397 .slave = &dra7xx_l4_cfg_hwmod,
2398 .clk = "l3_iclk_div",
2399 .user = OCP_USER_MPU | OCP_USER_SDMA,
2400};
2401
2402/* l3_main_1 -> l4_per1 */
2403static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2404 .master = &dra7xx_l3_main_1_hwmod,
2405 .slave = &dra7xx_l4_per1_hwmod,
2406 .clk = "l3_iclk_div",
2407 .user = OCP_USER_MPU | OCP_USER_SDMA,
2408};
2409
2410/* l3_main_1 -> l4_per2 */
2411static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2412 .master = &dra7xx_l3_main_1_hwmod,
2413 .slave = &dra7xx_l4_per2_hwmod,
2414 .clk = "l3_iclk_div",
2415 .user = OCP_USER_MPU | OCP_USER_SDMA,
2416};
2417
2418/* l3_main_1 -> l4_per3 */
2419static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2420 .master = &dra7xx_l3_main_1_hwmod,
2421 .slave = &dra7xx_l4_per3_hwmod,
2422 .clk = "l3_iclk_div",
2423 .user = OCP_USER_MPU | OCP_USER_SDMA,
2424};
2425
2426/* l3_main_1 -> l4_wkup */
2427static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2428 .master = &dra7xx_l3_main_1_hwmod,
2429 .slave = &dra7xx_l4_wkup_hwmod,
2430 .clk = "wkupaon_iclk_mux",
2431 .user = OCP_USER_MPU | OCP_USER_SDMA,
2432};
2433
2434/* l4_per2 -> atl */
2435static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2436 .master = &dra7xx_l4_per2_hwmod,
2437 .slave = &dra7xx_atl_hwmod,
2438 .clk = "l3_iclk_div",
2439 .user = OCP_USER_MPU | OCP_USER_SDMA,
2440};
2441
2442/* l3_main_1 -> bb2d */
2443static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2444 .master = &dra7xx_l3_main_1_hwmod,
2445 .slave = &dra7xx_bb2d_hwmod,
2446 .clk = "l3_iclk_div",
2447 .user = OCP_USER_MPU | OCP_USER_SDMA,
2448};
2449
2450/* l4_wkup -> counter_32k */
2451static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2452 .master = &dra7xx_l4_wkup_hwmod,
2453 .slave = &dra7xx_counter_32k_hwmod,
2454 .clk = "wkupaon_iclk_mux",
2455 .user = OCP_USER_MPU | OCP_USER_SDMA,
2456};
2457
2458/* l4_wkup -> ctrl_module_wkup */
2459static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2460 .master = &dra7xx_l4_wkup_hwmod,
2461 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2462 .clk = "wkupaon_iclk_mux",
2463 .user = OCP_USER_MPU | OCP_USER_SDMA,
2464};
2465
077c42f7
M		 2466static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2467 .master = &dra7xx_l4_per2_hwmod,
2468 .slave = &dra7xx_gmac_hwmod,
2469 .clk = "dpll_gmac_ck",
2470 .user = OCP_USER_MPU,
2471};
2472
2473static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2474 .master = &dra7xx_gmac_hwmod,
2475 .slave = &dra7xx_mdio_hwmod,
2476 .user = OCP_USER_MPU,
2477};
2478
90020c7b
A		 2479/* l4_wkup -> dcan1 */
2480static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2481 .master = &dra7xx_l4_wkup_hwmod,
2482 .slave = &dra7xx_dcan1_hwmod,
2483 .clk = "wkupaon_iclk_mux",
2484 .user = OCP_USER_MPU | OCP_USER_SDMA,
2485};
2486
2487/* l4_per2 -> dcan2 */
2488static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2489 .master = &dra7xx_l4_per2_hwmod,
2490 .slave = &dra7xx_dcan2_hwmod,
2491 .clk = "l3_iclk_div",
2492 .user = OCP_USER_MPU | OCP_USER_SDMA,
2493};
2494
2495static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2496 {
2497 .pa_start = 0x4a056000,
2498 .pa_end = 0x4a056fff,
2499 .flags = ADDR_TYPE_RT
2500 },
2501 { }
2502};
2503
2504/* l4_cfg -> dma_system */
2505static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2506 .master = &dra7xx_l4_cfg_hwmod,
2507 .slave = &dra7xx_dma_system_hwmod,
2508 .clk = "l3_iclk_div",
2509 .addr = dra7xx_dma_system_addrs,
2510 .user = OCP_USER_MPU | OCP_USER_SDMA,
2511};
2512
2513static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2514 {
2515 .name = "family",
2516 .pa_start = 0x58000000,
2517 .pa_end = 0x5800007f,
2518 .flags = ADDR_TYPE_RT
2519 },
2520};
2521
2522/* l3_main_1 -> dss */
2523static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2524 .master = &dra7xx_l3_main_1_hwmod,
2525 .slave = &dra7xx_dss_hwmod,
2526 .clk = "l3_iclk_div",
2527 .addr = dra7xx_dss_addrs,
2528 .user = OCP_USER_MPU | OCP_USER_SDMA,
2529};
2530
2531static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2532 {
2533 .name = "dispc",
2534 .pa_start = 0x58001000,
2535 .pa_end = 0x58001fff,
2536 .flags = ADDR_TYPE_RT
2537 },
2538};
2539
2540/* l3_main_1 -> dispc */
2541static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2542 .master = &dra7xx_l3_main_1_hwmod,
2543 .slave = &dra7xx_dss_dispc_hwmod,
2544 .clk = "l3_iclk_div",
2545 .addr = dra7xx_dss_dispc_addrs,
2546 .user = OCP_USER_MPU | OCP_USER_SDMA,
2547};
2548
2549static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2550 {
2551 .name = "hdmi_wp",
2552 .pa_start = 0x58040000,
2553 .pa_end = 0x580400ff,
2554 .flags = ADDR_TYPE_RT
2555 },
2556 { }
2557};
2558
2559/* l3_main_1 -> dispc */
2560static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2561 .master = &dra7xx_l3_main_1_hwmod,
2562 .slave = &dra7xx_dss_hdmi_hwmod,
2563 .clk = "l3_iclk_div",
2564 .addr = dra7xx_dss_hdmi_addrs,
2565 .user = OCP_USER_MPU | OCP_USER_SDMA,
2566};
2567
2568static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
2569 {
2570 .pa_start = 0x48078000,
2571 .pa_end = 0x48078fff,
2572 .flags = ADDR_TYPE_RT
2573 },
2574 { }
2575};
2576
2577/* l4_per1 -> elm */
2578static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2579 .master = &dra7xx_l4_per1_hwmod,
2580 .slave = &dra7xx_elm_hwmod,
2581 .clk = "l3_iclk_div",
2582 .addr = dra7xx_elm_addrs,
2583 .user = OCP_USER_MPU | OCP_USER_SDMA,
2584};
2585
2586/* l4_wkup -> gpio1 */
2587static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2588 .master = &dra7xx_l4_wkup_hwmod,
2589 .slave = &dra7xx_gpio1_hwmod,
2590 .clk = "wkupaon_iclk_mux",
2591 .user = OCP_USER_MPU | OCP_USER_SDMA,
2592};
2593
2594/* l4_per1 -> gpio2 */
2595static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2596 .master = &dra7xx_l4_per1_hwmod,
2597 .slave = &dra7xx_gpio2_hwmod,
2598 .clk = "l3_iclk_div",
2599 .user = OCP_USER_MPU | OCP_USER_SDMA,
2600};
2601
2602/* l4_per1 -> gpio3 */
2603static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2604 .master = &dra7xx_l4_per1_hwmod,
2605 .slave = &dra7xx_gpio3_hwmod,
2606 .clk = "l3_iclk_div",
2607 .user = OCP_USER_MPU | OCP_USER_SDMA,
2608};
2609
2610/* l4_per1 -> gpio4 */
2611static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2612 .master = &dra7xx_l4_per1_hwmod,
2613 .slave = &dra7xx_gpio4_hwmod,
2614 .clk = "l3_iclk_div",
2615 .user = OCP_USER_MPU | OCP_USER_SDMA,
2616};
2617
2618/* l4_per1 -> gpio5 */
2619static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2620 .master = &dra7xx_l4_per1_hwmod,
2621 .slave = &dra7xx_gpio5_hwmod,
2622 .clk = "l3_iclk_div",
2623 .user = OCP_USER_MPU | OCP_USER_SDMA,
2624};
2625
2626/* l4_per1 -> gpio6 */
2627static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2628 .master = &dra7xx_l4_per1_hwmod,
2629 .slave = &dra7xx_gpio6_hwmod,
2630 .clk = "l3_iclk_div",
2631 .user = OCP_USER_MPU | OCP_USER_SDMA,
2632};
2633
2634/* l4_per1 -> gpio7 */
2635static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2636 .master = &dra7xx_l4_per1_hwmod,
2637 .slave = &dra7xx_gpio7_hwmod,
2638 .clk = "l3_iclk_div",
2639 .user = OCP_USER_MPU | OCP_USER_SDMA,
2640};
2641
2642/* l4_per1 -> gpio8 */
2643static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2644 .master = &dra7xx_l4_per1_hwmod,
2645 .slave = &dra7xx_gpio8_hwmod,
2646 .clk = "l3_iclk_div",
2647 .user = OCP_USER_MPU | OCP_USER_SDMA,
2648};
2649
2650static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
2651 {
2652 .pa_start = 0x50000000,
2653 .pa_end = 0x500003ff,
2654 .flags = ADDR_TYPE_RT
2655 },
2656 { }
2657};
2658
2659/* l3_main_1 -> gpmc */
2660static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2661 .master = &dra7xx_l3_main_1_hwmod,
2662 .slave = &dra7xx_gpmc_hwmod,
2663 .clk = "l3_iclk_div",
2664 .addr = dra7xx_gpmc_addrs,
2665 .user = OCP_USER_MPU | OCP_USER_SDMA,
2666};
2667
2668static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2669 {
2670 .pa_start = 0x480b2000,
2671 .pa_end = 0x480b201f,
2672 .flags = ADDR_TYPE_RT
2673 },
2674 { }
2675};
2676
2677/* l4_per1 -> hdq1w */
2678static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2679 .master = &dra7xx_l4_per1_hwmod,
2680 .slave = &dra7xx_hdq1w_hwmod,
2681 .clk = "l3_iclk_div",
2682 .addr = dra7xx_hdq1w_addrs,
2683 .user = OCP_USER_MPU | OCP_USER_SDMA,
2684};
2685
2686/* l4_per1 -> i2c1 */
2687static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2688 .master = &dra7xx_l4_per1_hwmod,
2689 .slave = &dra7xx_i2c1_hwmod,
2690 .clk = "l3_iclk_div",
2691 .user = OCP_USER_MPU | OCP_USER_SDMA,
2692};
2693
2694/* l4_per1 -> i2c2 */
2695static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2696 .master = &dra7xx_l4_per1_hwmod,
2697 .slave = &dra7xx_i2c2_hwmod,
2698 .clk = "l3_iclk_div",
2699 .user = OCP_USER_MPU | OCP_USER_SDMA,
2700};
2701
2702/* l4_per1 -> i2c3 */
2703static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2704 .master = &dra7xx_l4_per1_hwmod,
2705 .slave = &dra7xx_i2c3_hwmod,
2706 .clk = "l3_iclk_div",
2707 .user = OCP_USER_MPU | OCP_USER_SDMA,
2708};
2709
2710/* l4_per1 -> i2c4 */
2711static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2712 .master = &dra7xx_l4_per1_hwmod,
2713 .slave = &dra7xx_i2c4_hwmod,
2714 .clk = "l3_iclk_div",
2715 .user = OCP_USER_MPU | OCP_USER_SDMA,
2716};
2717
2718/* l4_per1 -> i2c5 */
2719static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2720 .master = &dra7xx_l4_per1_hwmod,
2721 .slave = &dra7xx_i2c5_hwmod,
2722 .clk = "l3_iclk_div",
2723 .user = OCP_USER_MPU | OCP_USER_SDMA,
2724};
2725
067395d4
SA		 2726/* l4_cfg -> mailbox1 */
2727static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
2728 .master = &dra7xx_l4_cfg_hwmod,
2729 .slave = &dra7xx_mailbox1_hwmod,
2730 .clk = "l3_iclk_div",
2731 .user = OCP_USER_MPU | OCP_USER_SDMA,
2732};
2733
2734/* l4_per3 -> mailbox2 */
2735static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
2736 .master = &dra7xx_l4_per3_hwmod,
2737 .slave = &dra7xx_mailbox2_hwmod,
2738 .clk = "l3_iclk_div",
2739 .user = OCP_USER_MPU | OCP_USER_SDMA,
2740};
2741
2742/* l4_per3 -> mailbox3 */
2743static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
2744 .master = &dra7xx_l4_per3_hwmod,
2745 .slave = &dra7xx_mailbox3_hwmod,
2746 .clk = "l3_iclk_div",
2747 .user = OCP_USER_MPU | OCP_USER_SDMA,
2748};
2749
2750/* l4_per3 -> mailbox4 */
2751static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
2752 .master = &dra7xx_l4_per3_hwmod,
2753 .slave = &dra7xx_mailbox4_hwmod,
2754 .clk = "l3_iclk_div",
2755 .user = OCP_USER_MPU | OCP_USER_SDMA,
2756};
2757
2758/* l4_per3 -> mailbox5 */
2759static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
2760 .master = &dra7xx_l4_per3_hwmod,
2761 .slave = &dra7xx_mailbox5_hwmod,
2762 .clk = "l3_iclk_div",
2763 .user = OCP_USER_MPU | OCP_USER_SDMA,
2764};
2765
2766/* l4_per3 -> mailbox6 */
2767static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
2768 .master = &dra7xx_l4_per3_hwmod,
2769 .slave = &dra7xx_mailbox6_hwmod,
2770 .clk = "l3_iclk_div",
2771 .user = OCP_USER_MPU | OCP_USER_SDMA,
2772};
2773
2774/* l4_per3 -> mailbox7 */
2775static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
2776 .master = &dra7xx_l4_per3_hwmod,
2777 .slave = &dra7xx_mailbox7_hwmod,
2778 .clk = "l3_iclk_div",
2779 .user = OCP_USER_MPU | OCP_USER_SDMA,
2780};
2781
2782/* l4_per3 -> mailbox8 */
2783static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
2784 .master = &dra7xx_l4_per3_hwmod,
2785 .slave = &dra7xx_mailbox8_hwmod,
2786 .clk = "l3_iclk_div",
2787 .user = OCP_USER_MPU | OCP_USER_SDMA,
2788};
2789
2790/* l4_per3 -> mailbox9 */
2791static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
2792 .master = &dra7xx_l4_per3_hwmod,
2793 .slave = &dra7xx_mailbox9_hwmod,
2794 .clk = "l3_iclk_div",
2795 .user = OCP_USER_MPU | OCP_USER_SDMA,
2796};
2797
2798/* l4_per3 -> mailbox10 */
2799static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
2800 .master = &dra7xx_l4_per3_hwmod,
2801 .slave = &dra7xx_mailbox10_hwmod,
2802 .clk = "l3_iclk_div",
2803 .user = OCP_USER_MPU | OCP_USER_SDMA,
2804};
2805
2806/* l4_per3 -> mailbox11 */
2807static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
2808 .master = &dra7xx_l4_per3_hwmod,
2809 .slave = &dra7xx_mailbox11_hwmod,
2810 .clk = "l3_iclk_div",
2811 .user = OCP_USER_MPU | OCP_USER_SDMA,
2812};
2813
2814/* l4_per3 -> mailbox12 */
2815static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
2816 .master = &dra7xx_l4_per3_hwmod,
2817 .slave = &dra7xx_mailbox12_hwmod,
2818 .clk = "l3_iclk_div",
2819 .user = OCP_USER_MPU | OCP_USER_SDMA,
2820};
2821
2822/* l4_per3 -> mailbox13 */
2823static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
2824 .master = &dra7xx_l4_per3_hwmod,
2825 .slave = &dra7xx_mailbox13_hwmod,
2826 .clk = "l3_iclk_div",
2827 .user = OCP_USER_MPU | OCP_USER_SDMA,
2828};
2829
90020c7b
A		 2830/* l4_per1 -> mcspi1 */
2831static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2832 .master = &dra7xx_l4_per1_hwmod,
2833 .slave = &dra7xx_mcspi1_hwmod,
2834 .clk = "l3_iclk_div",
2835 .user = OCP_USER_MPU | OCP_USER_SDMA,
2836};
2837
2838/* l4_per1 -> mcspi2 */
2839static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2840 .master = &dra7xx_l4_per1_hwmod,
2841 .slave = &dra7xx_mcspi2_hwmod,
2842 .clk = "l3_iclk_div",
2843 .user = OCP_USER_MPU | OCP_USER_SDMA,
2844};
2845
2846/* l4_per1 -> mcspi3 */
2847static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2848 .master = &dra7xx_l4_per1_hwmod,
2849 .slave = &dra7xx_mcspi3_hwmod,
2850 .clk = "l3_iclk_div",
2851 .user = OCP_USER_MPU | OCP_USER_SDMA,
2852};
2853
2854/* l4_per1 -> mcspi4 */
2855static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2856 .master = &dra7xx_l4_per1_hwmod,
2857 .slave = &dra7xx_mcspi4_hwmod,
2858 .clk = "l3_iclk_div",
2859 .user = OCP_USER_MPU | OCP_USER_SDMA,
2860};
2861
2862/* l4_per1 -> mmc1 */
2863static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
2864 .master = &dra7xx_l4_per1_hwmod,
2865 .slave = &dra7xx_mmc1_hwmod,
2866 .clk = "l3_iclk_div",
2867 .user = OCP_USER_MPU | OCP_USER_SDMA,
2868};
2869
2870/* l4_per1 -> mmc2 */
2871static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
2872 .master = &dra7xx_l4_per1_hwmod,
2873 .slave = &dra7xx_mmc2_hwmod,
2874 .clk = "l3_iclk_div",
2875 .user = OCP_USER_MPU | OCP_USER_SDMA,
2876};
2877
2878/* l4_per1 -> mmc3 */
2879static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
2880 .master = &dra7xx_l4_per1_hwmod,
2881 .slave = &dra7xx_mmc3_hwmod,
2882 .clk = "l3_iclk_div",
2883 .user = OCP_USER_MPU | OCP_USER_SDMA,
2884};
2885
2886/* l4_per1 -> mmc4 */
2887static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
2888 .master = &dra7xx_l4_per1_hwmod,
2889 .slave = &dra7xx_mmc4_hwmod,
2890 .clk = "l3_iclk_div",
2891 .user = OCP_USER_MPU | OCP_USER_SDMA,
2892};
2893
2894/* l4_cfg -> mpu */
2895static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2896 .master = &dra7xx_l4_cfg_hwmod,
2897 .slave = &dra7xx_mpu_hwmod,
2898 .clk = "l3_iclk_div",
2899 .user = OCP_USER_MPU | OCP_USER_SDMA,
2900};
2901
90020c7b
A		 2902/* l4_cfg -> ocp2scp1 */
2903static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2904 .master = &dra7xx_l4_cfg_hwmod,
2905 .slave = &dra7xx_ocp2scp1_hwmod,
2906 .clk = "l4_root_clk_div",
90020c7b
A		 2907 .user = OCP_USER_MPU | OCP_USER_SDMA,
2908};
2909
df0d0f11
RQ		 2910/* l4_cfg -> ocp2scp3 */
2911static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
2912 .master = &dra7xx_l4_cfg_hwmod,
2913 .slave = &dra7xx_ocp2scp3_hwmod,
2914 .clk = "l4_root_clk_div",
2915 .user = OCP_USER_MPU | OCP_USER_SDMA,
2916};
2917
0717103e
KVA		 2918/* l3_main_1 -> pciess1 */
2919static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
8dd3eb71 2920 .master = &dra7xx_l3_main_1_hwmod,
0717103e 2921 .slave = &dra7xx_pciess1_hwmod,
8dd3eb71
KVA		 2922 .clk = "l3_iclk_div",
2923 .user = OCP_USER_MPU | OCP_USER_SDMA,
2924};
2925
0717103e
KVA		 2926/* l4_cfg -> pciess1 */
2927static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
8dd3eb71 2928 .master = &dra7xx_l4_cfg_hwmod,
0717103e 2929 .slave = &dra7xx_pciess1_hwmod,
8dd3eb71
KVA		 2930 .clk = "l4_root_clk_div",
2931 .user = OCP_USER_MPU | OCP_USER_SDMA,
2932};
2933
0717103e
KVA		 2934/* l3_main_1 -> pciess2 */
2935static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
8dd3eb71 2936 .master = &dra7xx_l3_main_1_hwmod,
0717103e 2937 .slave = &dra7xx_pciess2_hwmod,
8dd3eb71
KVA		 2938 .clk = "l3_iclk_div",
2939 .user = OCP_USER_MPU | OCP_USER_SDMA,
2940};
2941
0717103e
KVA		 2942/* l4_cfg -> pciess2 */
2943static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
70c18ef7 2944 .master = &dra7xx_l4_cfg_hwmod,
0717103e 2945 .slave = &dra7xx_pciess2_hwmod,
70c18ef7
KVA		 2946 .clk = "l4_root_clk_div",
2947 .user = OCP_USER_MPU | OCP_USER_SDMA,
2948};
2949
90020c7b
A		 2950static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2951 {
2952 .pa_start = 0x4b300000,
2953 .pa_end = 0x4b30007f,
2954 .flags = ADDR_TYPE_RT
2955 },
2956 { }
2957};
2958
2959/* l3_main_1 -> qspi */
2960static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2961 .master = &dra7xx_l3_main_1_hwmod,
2962 .slave = &dra7xx_qspi_hwmod,
2963 .clk = "l3_iclk_div",
2964 .addr = dra7xx_qspi_addrs,
2965 .user = OCP_USER_MPU | OCP_USER_SDMA,
2966};
2967
c913c8a1
LV		 2968/* l4_per3 -> rtcss */
2969static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
2970 .master = &dra7xx_l4_per3_hwmod,
2971 .slave = &dra7xx_rtcss_hwmod,
2972 .clk = "l4_root_clk_div",
2973 .user = OCP_USER_MPU | OCP_USER_SDMA,
2974};
2975
90020c7b
A		 2976static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
2977 {
2978 .name = "sysc",
2979 .pa_start = 0x4a141100,
2980 .pa_end = 0x4a141107,
2981 .flags = ADDR_TYPE_RT
2982 },
2983 { }
2984};
2985
2986/* l4_cfg -> sata */
2987static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
2988 .master = &dra7xx_l4_cfg_hwmod,
2989 .slave = &dra7xx_sata_hwmod,
2990 .clk = "l3_iclk_div",
2991 .addr = dra7xx_sata_addrs,
2992 .user = OCP_USER_MPU | OCP_USER_SDMA,
2993};
2994
2995static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
2996 {
2997 .pa_start = 0x4a0dd000,
2998 .pa_end = 0x4a0dd07f,
2999 .flags = ADDR_TYPE_RT
3000 },
3001 { }
3002};
3003
3004/* l4_cfg -> smartreflex_core */
3005static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3006 .master = &dra7xx_l4_cfg_hwmod,
3007 .slave = &dra7xx_smartreflex_core_hwmod,
3008 .clk = "l4_root_clk_div",
3009 .addr = dra7xx_smartreflex_core_addrs,
3010 .user = OCP_USER_MPU | OCP_USER_SDMA,
3011};
3012
3013static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
3014 {
3015 .pa_start = 0x4a0d9000,
3016 .pa_end = 0x4a0d907f,
3017 .flags = ADDR_TYPE_RT
3018 },
3019 { }
3020};
3021
3022/* l4_cfg -> smartreflex_mpu */
3023static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3024 .master = &dra7xx_l4_cfg_hwmod,
3025 .slave = &dra7xx_smartreflex_mpu_hwmod,
3026 .clk = "l4_root_clk_div",
3027 .addr = dra7xx_smartreflex_mpu_addrs,
3028 .user = OCP_USER_MPU | OCP_USER_SDMA,
3029};
3030
3031static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
3032 {
3033 .pa_start = 0x4a0f6000,
3034 .pa_end = 0x4a0f6fff,
3035 .flags = ADDR_TYPE_RT
3036 },
3037 { }
3038};
3039
3040/* l4_cfg -> spinlock */
3041static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3042 .master = &dra7xx_l4_cfg_hwmod,
3043 .slave = &dra7xx_spinlock_hwmod,
3044 .clk = "l3_iclk_div",
3045 .addr = dra7xx_spinlock_addrs,
3046 .user = OCP_USER_MPU | OCP_USER_SDMA,
3047};
3048
3049/* l4_wkup -> timer1 */
3050static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3051 .master = &dra7xx_l4_wkup_hwmod,
3052 .slave = &dra7xx_timer1_hwmod,
3053 .clk = "wkupaon_iclk_mux",
3054 .user = OCP_USER_MPU | OCP_USER_SDMA,
3055};
3056
3057/* l4_per1 -> timer2 */
3058static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3059 .master = &dra7xx_l4_per1_hwmod,
3060 .slave = &dra7xx_timer2_hwmod,
3061 .clk = "l3_iclk_div",
3062 .user = OCP_USER_MPU | OCP_USER_SDMA,
3063};
3064
3065/* l4_per1 -> timer3 */
3066static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3067 .master = &dra7xx_l4_per1_hwmod,
3068 .slave = &dra7xx_timer3_hwmod,
3069 .clk = "l3_iclk_div",
3070 .user = OCP_USER_MPU | OCP_USER_SDMA,
3071};
3072
3073/* l4_per1 -> timer4 */
3074static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3075 .master = &dra7xx_l4_per1_hwmod,
3076 .slave = &dra7xx_timer4_hwmod,
3077 .clk = "l3_iclk_div",
3078 .user = OCP_USER_MPU | OCP_USER_SDMA,
3079};
3080
3081/* l4_per3 -> timer5 */
3082static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3083 .master = &dra7xx_l4_per3_hwmod,
3084 .slave = &dra7xx_timer5_hwmod,
3085 .clk = "l3_iclk_div",
3086 .user = OCP_USER_MPU | OCP_USER_SDMA,
3087};
3088
3089/* l4_per3 -> timer6 */
3090static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3091 .master = &dra7xx_l4_per3_hwmod,
3092 .slave = &dra7xx_timer6_hwmod,
3093 .clk = "l3_iclk_div",
3094 .user = OCP_USER_MPU | OCP_USER_SDMA,
3095};
3096
3097/* l4_per3 -> timer7 */
3098static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3099 .master = &dra7xx_l4_per3_hwmod,
3100 .slave = &dra7xx_timer7_hwmod,
3101 .clk = "l3_iclk_div",
3102 .user = OCP_USER_MPU | OCP_USER_SDMA,
3103};
3104
3105/* l4_per3 -> timer8 */
3106static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3107 .master = &dra7xx_l4_per3_hwmod,
3108 .slave = &dra7xx_timer8_hwmod,
3109 .clk = "l3_iclk_div",
3110 .user = OCP_USER_MPU | OCP_USER_SDMA,
3111};
3112
3113/* l4_per1 -> timer9 */
3114static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3115 .master = &dra7xx_l4_per1_hwmod,
3116 .slave = &dra7xx_timer9_hwmod,
3117 .clk = "l3_iclk_div",
3118 .user = OCP_USER_MPU | OCP_USER_SDMA,
3119};
3120
3121/* l4_per1 -> timer10 */
3122static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3123 .master = &dra7xx_l4_per1_hwmod,
3124 .slave = &dra7xx_timer10_hwmod,
3125 .clk = "l3_iclk_div",
3126 .user = OCP_USER_MPU | OCP_USER_SDMA,
3127};
3128
3129/* l4_per1 -> timer11 */
3130static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3131 .master = &dra7xx_l4_per1_hwmod,
3132 .slave = &dra7xx_timer11_hwmod,
3133 .clk = "l3_iclk_div",
3134 .user = OCP_USER_MPU | OCP_USER_SDMA,
3135};
3136
1ac964f4
SA		 3137/* l4_per3 -> timer13 */
3138static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3139 .master = &dra7xx_l4_per3_hwmod,
3140 .slave = &dra7xx_timer13_hwmod,
3141 .clk = "l3_iclk_div",
3142 .user = OCP_USER_MPU | OCP_USER_SDMA,
3143};
3144
3145/* l4_per3 -> timer14 */
3146static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3147 .master = &dra7xx_l4_per3_hwmod,
3148 .slave = &dra7xx_timer14_hwmod,
3149 .clk = "l3_iclk_div",
3150 .user = OCP_USER_MPU | OCP_USER_SDMA,
3151};
3152
3153/* l4_per3 -> timer15 */
3154static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3155 .master = &dra7xx_l4_per3_hwmod,
3156 .slave = &dra7xx_timer15_hwmod,
3157 .clk = "l3_iclk_div",
3158 .user = OCP_USER_MPU | OCP_USER_SDMA,
3159};
3160
3161/* l4_per3 -> timer16 */
3162static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3163 .master = &dra7xx_l4_per3_hwmod,
3164 .slave = &dra7xx_timer16_hwmod,
3165 .clk = "l3_iclk_div",
3166 .user = OCP_USER_MPU | OCP_USER_SDMA,
3167};
3168
90020c7b
A		 3169/* l4_per1 -> uart1 */
3170static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3171 .master = &dra7xx_l4_per1_hwmod,
3172 .slave = &dra7xx_uart1_hwmod,
3173 .clk = "l3_iclk_div",
3174 .user = OCP_USER_MPU | OCP_USER_SDMA,
3175};
3176
3177/* l4_per1 -> uart2 */
3178static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3179 .master = &dra7xx_l4_per1_hwmod,
3180 .slave = &dra7xx_uart2_hwmod,
3181 .clk = "l3_iclk_div",
3182 .user = OCP_USER_MPU | OCP_USER_SDMA,
3183};
3184
3185/* l4_per1 -> uart3 */
3186static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3187 .master = &dra7xx_l4_per1_hwmod,
3188 .slave = &dra7xx_uart3_hwmod,
3189 .clk = "l3_iclk_div",
3190 .user = OCP_USER_MPU | OCP_USER_SDMA,
3191};
3192
3193/* l4_per1 -> uart4 */
3194static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3195 .master = &dra7xx_l4_per1_hwmod,
3196 .slave = &dra7xx_uart4_hwmod,
3197 .clk = "l3_iclk_div",
3198 .user = OCP_USER_MPU | OCP_USER_SDMA,
3199};
3200
3201/* l4_per1 -> uart5 */
3202static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3203 .master = &dra7xx_l4_per1_hwmod,
3204 .slave = &dra7xx_uart5_hwmod,
3205 .clk = "l3_iclk_div",
3206 .user = OCP_USER_MPU | OCP_USER_SDMA,
3207};
3208
3209/* l4_per1 -> uart6 */
3210static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3211 .master = &dra7xx_l4_per1_hwmod,
3212 .slave = &dra7xx_uart6_hwmod,
3213 .clk = "l3_iclk_div",
3214 .user = OCP_USER_MPU | OCP_USER_SDMA,
3215};
3216
33acc9ff
A		 3217/* l4_per2 -> uart7 */
3218static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3219 .master = &dra7xx_l4_per2_hwmod,
3220 .slave = &dra7xx_uart7_hwmod,
3221 .clk = "l3_iclk_div",
3222 .user = OCP_USER_MPU | OCP_USER_SDMA,
3223};
3224
3225/* l4_per2 -> uart8 */
3226static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3227 .master = &dra7xx_l4_per2_hwmod,
3228 .slave = &dra7xx_uart8_hwmod,
3229 .clk = "l3_iclk_div",
3230 .user = OCP_USER_MPU | OCP_USER_SDMA,
3231};
3232
3233/* l4_per2 -> uart9 */
3234static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3235 .master = &dra7xx_l4_per2_hwmod,
3236 .slave = &dra7xx_uart9_hwmod,
3237 .clk = "l3_iclk_div",
3238 .user = OCP_USER_MPU | OCP_USER_SDMA,
3239};
3240
3241/* l4_wkup -> uart10 */
3242static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3243 .master = &dra7xx_l4_wkup_hwmod,
3244 .slave = &dra7xx_uart10_hwmod,
3245 .clk = "wkupaon_iclk_mux",
3246 .user = OCP_USER_MPU | OCP_USER_SDMA,
3247};
3248
90020c7b
A		 3249/* l4_per3 -> usb_otg_ss1 */
3250static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3251 .master = &dra7xx_l4_per3_hwmod,
3252 .slave = &dra7xx_usb_otg_ss1_hwmod,
3253 .clk = "dpll_core_h13x2_ck",
3254 .user = OCP_USER_MPU | OCP_USER_SDMA,
3255};
3256
3257/* l4_per3 -> usb_otg_ss2 */
3258static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3259 .master = &dra7xx_l4_per3_hwmod,
3260 .slave = &dra7xx_usb_otg_ss2_hwmod,
3261 .clk = "dpll_core_h13x2_ck",
3262 .user = OCP_USER_MPU | OCP_USER_SDMA,
3263};
3264
3265/* l4_per3 -> usb_otg_ss3 */
3266static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3267 .master = &dra7xx_l4_per3_hwmod,
3268 .slave = &dra7xx_usb_otg_ss3_hwmod,
3269 .clk = "dpll_core_h13x2_ck",
3270 .user = OCP_USER_MPU | OCP_USER_SDMA,
3271};
3272
3273/* l4_per3 -> usb_otg_ss4 */
3274static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3275 .master = &dra7xx_l4_per3_hwmod,
3276 .slave = &dra7xx_usb_otg_ss4_hwmod,
3277 .clk = "dpll_core_h13x2_ck",
3278 .user = OCP_USER_MPU | OCP_USER_SDMA,
3279};
3280
3281/* l3_main_1 -> vcp1 */
3282static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3283 .master = &dra7xx_l3_main_1_hwmod,
3284 .slave = &dra7xx_vcp1_hwmod,
3285 .clk = "l3_iclk_div",
3286 .user = OCP_USER_MPU | OCP_USER_SDMA,
3287};
3288
3289/* l4_per2 -> vcp1 */
3290static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3291 .master = &dra7xx_l4_per2_hwmod,
3292 .slave = &dra7xx_vcp1_hwmod,
3293 .clk = "l3_iclk_div",
3294 .user = OCP_USER_MPU | OCP_USER_SDMA,
3295};
3296
3297/* l3_main_1 -> vcp2 */
3298static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3299 .master = &dra7xx_l3_main_1_hwmod,
3300 .slave = &dra7xx_vcp2_hwmod,
3301 .clk = "l3_iclk_div",
3302 .user = OCP_USER_MPU | OCP_USER_SDMA,
3303};
3304
3305/* l4_per2 -> vcp2 */
3306static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3307 .master = &dra7xx_l4_per2_hwmod,
3308 .slave = &dra7xx_vcp2_hwmod,
3309 .clk = "l3_iclk_div",
3310 .user = OCP_USER_MPU | OCP_USER_SDMA,
3311};
3312
3313/* l4_wkup -> wd_timer2 */
3314static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3315 .master = &dra7xx_l4_wkup_hwmod,
3316 .slave = &dra7xx_wd_timer2_hwmod,
3317 .clk = "wkupaon_iclk_mux",
3318 .user = OCP_USER_MPU | OCP_USER_SDMA,
3319};
3320
3321static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
42121688 3322 &dra7xx_l3_main_1__dmm,
90020c7b
A		 3323 &dra7xx_l3_main_2__l3_instr,
3324 &dra7xx_l4_cfg__l3_main_1,
3325 &dra7xx_mpu__l3_main_1,
3326 &dra7xx_l3_main_1__l3_main_2,
3327 &dra7xx_l4_cfg__l3_main_2,
3328 &dra7xx_l3_main_1__l4_cfg,
3329 &dra7xx_l3_main_1__l4_per1,
3330 &dra7xx_l3_main_1__l4_per2,
3331 &dra7xx_l3_main_1__l4_per3,
3332 &dra7xx_l3_main_1__l4_wkup,
3333 &dra7xx_l4_per2__atl,
3334 &dra7xx_l3_main_1__bb2d,
3335 &dra7xx_l4_wkup__counter_32k,
3336 &dra7xx_l4_wkup__ctrl_module_wkup,
3337 &dra7xx_l4_wkup__dcan1,
3338 &dra7xx_l4_per2__dcan2,
077c42f7
M		 3339 &dra7xx_l4_per2__cpgmac0,
3340 &dra7xx_gmac__mdio,
90020c7b
A		 3341 &dra7xx_l4_cfg__dma_system,
3342 &dra7xx_l3_main_1__dss,
3343 &dra7xx_l3_main_1__dispc,
3344 &dra7xx_l3_main_1__hdmi,
3345 &dra7xx_l4_per1__elm,
3346 &dra7xx_l4_wkup__gpio1,
3347 &dra7xx_l4_per1__gpio2,
3348 &dra7xx_l4_per1__gpio3,
3349 &dra7xx_l4_per1__gpio4,
3350 &dra7xx_l4_per1__gpio5,
3351 &dra7xx_l4_per1__gpio6,
3352 &dra7xx_l4_per1__gpio7,
3353 &dra7xx_l4_per1__gpio8,
3354 &dra7xx_l3_main_1__gpmc,
3355 &dra7xx_l4_per1__hdq1w,
3356 &dra7xx_l4_per1__i2c1,
3357 &dra7xx_l4_per1__i2c2,
3358 &dra7xx_l4_per1__i2c3,
3359 &dra7xx_l4_per1__i2c4,
3360 &dra7xx_l4_per1__i2c5,
067395d4
SA		 3361 &dra7xx_l4_cfg__mailbox1,
3362 &dra7xx_l4_per3__mailbox2,
3363 &dra7xx_l4_per3__mailbox3,
3364 &dra7xx_l4_per3__mailbox4,
3365 &dra7xx_l4_per3__mailbox5,
3366 &dra7xx_l4_per3__mailbox6,
3367 &dra7xx_l4_per3__mailbox7,
3368 &dra7xx_l4_per3__mailbox8,
3369 &dra7xx_l4_per3__mailbox9,
3370 &dra7xx_l4_per3__mailbox10,
3371 &dra7xx_l4_per3__mailbox11,
3372 &dra7xx_l4_per3__mailbox12,
3373 &dra7xx_l4_per3__mailbox13,
90020c7b
A		 3374 &dra7xx_l4_per1__mcspi1,
3375 &dra7xx_l4_per1__mcspi2,
3376 &dra7xx_l4_per1__mcspi3,
3377 &dra7xx_l4_per1__mcspi4,
3378 &dra7xx_l4_per1__mmc1,
3379 &dra7xx_l4_per1__mmc2,
3380 &dra7xx_l4_per1__mmc3,
3381 &dra7xx_l4_per1__mmc4,
3382 &dra7xx_l4_cfg__mpu,
3383 &dra7xx_l4_cfg__ocp2scp1,
df0d0f11 3384 &dra7xx_l4_cfg__ocp2scp3,
0717103e
KVA		 3385 &dra7xx_l3_main_1__pciess1,
3386 &dra7xx_l4_cfg__pciess1,
3387 &dra7xx_l3_main_1__pciess2,
3388 &dra7xx_l4_cfg__pciess2,
90020c7b 3389 &dra7xx_l3_main_1__qspi,
c913c8a1 3390 &dra7xx_l4_per3__rtcss,
90020c7b
A		 3391 &dra7xx_l4_cfg__sata,
3392 &dra7xx_l4_cfg__smartreflex_core,
3393 &dra7xx_l4_cfg__smartreflex_mpu,
3394 &dra7xx_l4_cfg__spinlock,
3395 &dra7xx_l4_wkup__timer1,
3396 &dra7xx_l4_per1__timer2,
3397 &dra7xx_l4_per1__timer3,
3398 &dra7xx_l4_per1__timer4,
3399 &dra7xx_l4_per3__timer5,
3400 &dra7xx_l4_per3__timer6,
3401 &dra7xx_l4_per3__timer7,
3402 &dra7xx_l4_per3__timer8,
3403 &dra7xx_l4_per1__timer9,
3404 &dra7xx_l4_per1__timer10,
3405 &dra7xx_l4_per1__timer11,
1ac964f4
SA		 3406 &dra7xx_l4_per3__timer13,
3407 &dra7xx_l4_per3__timer14,
3408 &dra7xx_l4_per3__timer15,
3409 &dra7xx_l4_per3__timer16,
90020c7b
A		 3410 &dra7xx_l4_per1__uart1,
3411 &dra7xx_l4_per1__uart2,
3412 &dra7xx_l4_per1__uart3,
3413 &dra7xx_l4_per1__uart4,
3414 &dra7xx_l4_per1__uart5,
3415 &dra7xx_l4_per1__uart6,
33acc9ff
A		 3416 &dra7xx_l4_per2__uart7,
3417 &dra7xx_l4_per2__uart8,
3418 &dra7xx_l4_per2__uart9,
3419 &dra7xx_l4_wkup__uart10,
90020c7b
A		 3420 &dra7xx_l4_per3__usb_otg_ss1,
3421 &dra7xx_l4_per3__usb_otg_ss2,
3422 &dra7xx_l4_per3__usb_otg_ss3,
90020c7b
A		 3423 &dra7xx_l3_main_1__vcp1,
3424 &dra7xx_l4_per2__vcp1,
3425 &dra7xx_l3_main_1__vcp2,
3426 &dra7xx_l4_per2__vcp2,
3427 &dra7xx_l4_wkup__wd_timer2,
3428 NULL,
3429};
3430
f7f7a29b
RN		 3431static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3432 &dra7xx_l4_per3__usb_otg_ss4,
3433 NULL,
3434};
3435
3436static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3437 NULL,
3438};
3439
90020c7b
A		 3440int __init dra7xx_hwmod_init(void)
3441{
f7f7a29b
RN		 3442 int ret;
3443
90020c7b 3444 omap_hwmod_init();
f7f7a29b
RN		 3445 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3446
3447 if (!ret && soc_is_dra74x())
3448 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3449 else if (!ret && soc_is_dra72x())
3450 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
3451
3452 return ret;
90020c7b 3453}
Linux kernel - Deliverables
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