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ARM: DRA7: hwmod: Fix OCP2SCP sysconfig
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_7xx_data.c
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90020c7b
A		 1/*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/io.h>
21#include <linux/platform_data/gpio-omap.h>
55143438 22#include <linux/platform_data/hsmmc-omap.h>
90020c7b
A		 23#include <linux/power/smartreflex.h>
24#include <linux/i2c-omap.h>
25
26#include <linux/omap-dma.h>
27#include <linux/platform_data/spi-omap2-mcspi.h>
28#include <linux/platform_data/asoc-ti-mcbsp.h>
29#include <plat/dmtimer.h>
30
31#include "omap_hwmod.h"
32#include "omap_hwmod_common_data.h"
33#include "cm1_7xx.h"
34#include "cm2_7xx.h"
35#include "prm7xx.h"
36#include "i2c.h"
90020c7b 37#include "wd_timer.h"
f7f7a29b 38#include "soc.h"
90020c7b
A		 39
40/* Base offset for all DRA7XX interrupts external to MPUSS */
41#define DRA7XX_IRQ_GIC_START 32
42
43/* Base offset for all DRA7XX dma requests */
44#define DRA7XX_DMA_REQ_START 1
45
46
47/*
48 * IP blocks
49 */
50
42121688
TV		 51/*
52 * 'dmm' class
53 * instance(s): dmm
54 */
55static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
56 .name = "dmm",
57};
58
59/* dmm */
60static struct omap_hwmod dra7xx_dmm_hwmod = {
61 .name = "dmm",
62 .class = &dra7xx_dmm_hwmod_class,
63 .clkdm_name = "emif_clkdm",
64 .prcm = {
65 .omap4 = {
66 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
67 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
68 },
69 },
70};
71
90020c7b
A		 72/*
73 * 'l3' class
74 * instance(s): l3_instr, l3_main_1, l3_main_2
75 */
76static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
77 .name = "l3",
78};
79
80/* l3_instr */
81static struct omap_hwmod dra7xx_l3_instr_hwmod = {
82 .name = "l3_instr",
83 .class = &dra7xx_l3_hwmod_class,
84 .clkdm_name = "l3instr_clkdm",
85 .prcm = {
86 .omap4 = {
87 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
88 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
89 .modulemode = MODULEMODE_HWCTRL,
90 },
91 },
92};
93
94/* l3_main_1 */
95static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
96 .name = "l3_main_1",
97 .class = &dra7xx_l3_hwmod_class,
98 .clkdm_name = "l3main1_clkdm",
99 .prcm = {
100 .omap4 = {
101 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
102 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
103 },
104 },
105};
106
107/* l3_main_2 */
108static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
109 .name = "l3_main_2",
110 .class = &dra7xx_l3_hwmod_class,
111 .clkdm_name = "l3instr_clkdm",
112 .prcm = {
113 .omap4 = {
114 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
115 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
116 .modulemode = MODULEMODE_HWCTRL,
117 },
118 },
119};
120
121/*
122 * 'l4' class
123 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
124 */
125static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
126 .name = "l4",
127};
128
129/* l4_cfg */
130static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
131 .name = "l4_cfg",
132 .class = &dra7xx_l4_hwmod_class,
133 .clkdm_name = "l4cfg_clkdm",
134 .prcm = {
135 .omap4 = {
136 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
137 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
138 },
139 },
140};
141
142/* l4_per1 */
143static struct omap_hwmod dra7xx_l4_per1_hwmod = {
144 .name = "l4_per1",
145 .class = &dra7xx_l4_hwmod_class,
146 .clkdm_name = "l4per_clkdm",
147 .prcm = {
148 .omap4 = {
149 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
150 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
151 },
152 },
153};
154
155/* l4_per2 */
156static struct omap_hwmod dra7xx_l4_per2_hwmod = {
157 .name = "l4_per2",
158 .class = &dra7xx_l4_hwmod_class,
159 .clkdm_name = "l4per2_clkdm",
160 .prcm = {
161 .omap4 = {
162 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
163 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
164 },
165 },
166};
167
168/* l4_per3 */
169static struct omap_hwmod dra7xx_l4_per3_hwmod = {
170 .name = "l4_per3",
171 .class = &dra7xx_l4_hwmod_class,
172 .clkdm_name = "l4per3_clkdm",
173 .prcm = {
174 .omap4 = {
175 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
176 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
177 },
178 },
179};
180
181/* l4_wkup */
182static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
183 .name = "l4_wkup",
184 .class = &dra7xx_l4_hwmod_class,
185 .clkdm_name = "wkupaon_clkdm",
186 .prcm = {
187 .omap4 = {
188 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
189 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
190 },
191 },
192};
193
194/*
195 * 'atl' class
196 *
197 */
198
199static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
200 .name = "atl",
201};
202
203/* atl */
204static struct omap_hwmod dra7xx_atl_hwmod = {
205 .name = "atl",
206 .class = &dra7xx_atl_hwmod_class,
207 .clkdm_name = "atl_clkdm",
208 .main_clk = "atl_gfclk_mux",
209 .prcm = {
210 .omap4 = {
211 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
212 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
213 .modulemode = MODULEMODE_SWCTRL,
214 },
215 },
216};
217
218/*
219 * 'bb2d' class
220 *
221 */
222
223static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
224 .name = "bb2d",
225};
226
227/* bb2d */
228static struct omap_hwmod dra7xx_bb2d_hwmod = {
229 .name = "bb2d",
230 .class = &dra7xx_bb2d_hwmod_class,
231 .clkdm_name = "dss_clkdm",
232 .main_clk = "dpll_core_h24x2_ck",
233 .prcm = {
234 .omap4 = {
235 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
236 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
237 .modulemode = MODULEMODE_SWCTRL,
238 },
239 },
240};
241
242/*
243 * 'counter' class
244 *
245 */
246
247static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
248 .rev_offs = 0x0000,
249 .sysc_offs = 0x0010,
250 .sysc_flags = SYSC_HAS_SIDLEMODE,
251 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
252 SIDLE_SMART_WKUP),
253 .sysc_fields = &omap_hwmod_sysc_type1,
254};
255
256static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
257 .name = "counter",
258 .sysc = &dra7xx_counter_sysc,
259};
260
261/* counter_32k */
262static struct omap_hwmod dra7xx_counter_32k_hwmod = {
263 .name = "counter_32k",
264 .class = &dra7xx_counter_hwmod_class,
265 .clkdm_name = "wkupaon_clkdm",
266 .flags = HWMOD_SWSUP_SIDLE,
267 .main_clk = "wkupaon_iclk_mux",
268 .prcm = {
269 .omap4 = {
270 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
271 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
272 },
273 },
274};
275
276/*
277 * 'ctrl_module' class
278 *
279 */
280
281static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
282 .name = "ctrl_module",
283};
284
285/* ctrl_module_wkup */
286static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
287 .name = "ctrl_module_wkup",
288 .class = &dra7xx_ctrl_module_hwmod_class,
289 .clkdm_name = "wkupaon_clkdm",
290 .prcm = {
291 .omap4 = {
292 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
293 },
294 },
295};
296
077c42f7
M		 297/*
298 * 'gmac' class
299 * cpsw/gmac sub system
300 */
301static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
302 .rev_offs = 0x0,
303 .sysc_offs = 0x8,
304 .syss_offs = 0x4,
305 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
306 SYSS_HAS_RESET_STATUS),
307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
308 MSTANDBY_NO),
309 .sysc_fields = &omap_hwmod_sysc_type3,
310};
311
312static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
313 .name = "gmac",
314 .sysc = &dra7xx_gmac_sysc,
315};
316
317static struct omap_hwmod dra7xx_gmac_hwmod = {
318 .name = "gmac",
319 .class = &dra7xx_gmac_hwmod_class,
320 .clkdm_name = "gmac_clkdm",
321 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
322 .main_clk = "dpll_gmac_ck",
323 .mpu_rt_idx = 1,
324 .prcm = {
325 .omap4 = {
326 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
327 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
328 .modulemode = MODULEMODE_SWCTRL,
329 },
330 },
331};
332
333/*
334 * 'mdio' class
335 */
336static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
337 .name = "davinci_mdio",
338};
339
340static struct omap_hwmod dra7xx_mdio_hwmod = {
341 .name = "davinci_mdio",
342 .class = &dra7xx_mdio_hwmod_class,
343 .clkdm_name = "gmac_clkdm",
344 .main_clk = "dpll_gmac_ck",
345};
346
90020c7b
A		 347/*
348 * 'dcan' class
349 *
350 */
351
352static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
353 .name = "dcan",
354};
355
356/* dcan1 */
357static struct omap_hwmod dra7xx_dcan1_hwmod = {
358 .name = "dcan1",
359 .class = &dra7xx_dcan_hwmod_class,
360 .clkdm_name = "wkupaon_clkdm",
361 .main_clk = "dcan1_sys_clk_mux",
362 .prcm = {
363 .omap4 = {
364 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
365 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
366 .modulemode = MODULEMODE_SWCTRL,
367 },
368 },
369};
370
371/* dcan2 */
372static struct omap_hwmod dra7xx_dcan2_hwmod = {
373 .name = "dcan2",
374 .class = &dra7xx_dcan_hwmod_class,
375 .clkdm_name = "l4per2_clkdm",
376 .main_clk = "sys_clkin1",
377 .prcm = {
378 .omap4 = {
379 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
380 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
381 .modulemode = MODULEMODE_SWCTRL,
382 },
383 },
384};
385
386/*
387 * 'dma' class
388 *
389 */
390
391static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
392 .rev_offs = 0x0000,
393 .sysc_offs = 0x002c,
394 .syss_offs = 0x0028,
395 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
396 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
397 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
398 SYSS_HAS_RESET_STATUS),
399 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
400 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
401 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
402 .sysc_fields = &omap_hwmod_sysc_type1,
403};
404
405static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
406 .name = "dma",
407 .sysc = &dra7xx_dma_sysc,
408};
409
410/* dma dev_attr */
411static struct omap_dma_dev_attr dma_dev_attr = {
412 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
413 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
414 .lch_count = 32,
415};
416
417/* dma_system */
90020c7b
A		 418static struct omap_hwmod dra7xx_dma_system_hwmod = {
419 .name = "dma_system",
420 .class = &dra7xx_dma_hwmod_class,
421 .clkdm_name = "dma_clkdm",
90020c7b
A		 422 .main_clk = "l3_iclk_div",
423 .prcm = {
424 .omap4 = {
425 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
426 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
427 },
428 },
429 .dev_attr = &dma_dev_attr,
430};
431
432/*
433 * 'dss' class
434 *
435 */
436
437static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
438 .rev_offs = 0x0000,
439 .syss_offs = 0x0014,
440 .sysc_flags = SYSS_HAS_RESET_STATUS,
441};
442
443static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
444 .name = "dss",
445 .sysc = &dra7xx_dss_sysc,
446 .reset = omap_dss_reset,
447};
448
449/* dss */
450static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
451 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
452 { .dma_req = -1 }
453};
454
455static struct omap_hwmod_opt_clk dss_opt_clks[] = {
456 { .role = "dss_clk", .clk = "dss_dss_clk" },
457 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
458 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
459 { .role = "video2_clk", .clk = "dss_video2_clk" },
460 { .role = "video1_clk", .clk = "dss_video1_clk" },
461 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
2d5a3c80 462 { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
90020c7b
A		 463};
464
465static struct omap_hwmod dra7xx_dss_hwmod = {
466 .name = "dss_core",
467 .class = &dra7xx_dss_hwmod_class,
468 .clkdm_name = "dss_clkdm",
469 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
470 .sdma_reqs = dra7xx_dss_sdma_reqs,
471 .main_clk = "dss_dss_clk",
472 .prcm = {
473 .omap4 = {
474 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
475 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
476 .modulemode = MODULEMODE_SWCTRL,
477 },
478 },
479 .opt_clks = dss_opt_clks,
480 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
481};
482
483/*
484 * 'dispc' class
485 * display controller
486 */
487
488static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
489 .rev_offs = 0x0000,
490 .sysc_offs = 0x0010,
491 .syss_offs = 0x0014,
492 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
493 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
494 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
495 SYSS_HAS_RESET_STATUS),
496 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
497 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
498 .sysc_fields = &omap_hwmod_sysc_type1,
499};
500
501static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
502 .name = "dispc",
503 .sysc = &dra7xx_dispc_sysc,
504};
505
506/* dss_dispc */
507/* dss_dispc dev_attr */
508static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
509 .has_framedonetv_irq = 1,
510 .manager_count = 4,
511};
512
513static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
514 .name = "dss_dispc",
515 .class = &dra7xx_dispc_hwmod_class,
516 .clkdm_name = "dss_clkdm",
517 .main_clk = "dss_dss_clk",
518 .prcm = {
519 .omap4 = {
520 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
521 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
522 },
523 },
524 .dev_attr = &dss_dispc_dev_attr,
a3818c6d 525 .parent_hwmod = &dra7xx_dss_hwmod,
90020c7b
A		 526};
527
528/*
529 * 'hdmi' class
530 * hdmi controller
531 */
532
533static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
534 .rev_offs = 0x0000,
535 .sysc_offs = 0x0010,
536 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
537 SYSC_HAS_SOFTRESET),
538 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
539 SIDLE_SMART_WKUP),
540 .sysc_fields = &omap_hwmod_sysc_type2,
541};
542
543static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
544 .name = "hdmi",
545 .sysc = &dra7xx_hdmi_sysc,
546};
547
548/* dss_hdmi */
549
550static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
551 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
552};
553
554static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
555 .name = "dss_hdmi",
556 .class = &dra7xx_hdmi_hwmod_class,
557 .clkdm_name = "dss_clkdm",
558 .main_clk = "dss_48mhz_clk",
559 .prcm = {
560 .omap4 = {
561 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
562 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
563 },
564 },
565 .opt_clks = dss_hdmi_opt_clks,
566 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
a3818c6d 567 .parent_hwmod = &dra7xx_dss_hwmod,
90020c7b
A		 568};
569
570/*
571 * 'elm' class
572 *
573 */
574
575static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
576 .rev_offs = 0x0000,
577 .sysc_offs = 0x0010,
578 .syss_offs = 0x0014,
579 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
580 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
581 SYSS_HAS_RESET_STATUS),
582 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
583 SIDLE_SMART_WKUP),
584 .sysc_fields = &omap_hwmod_sysc_type1,
585};
586
587static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
588 .name = "elm",
589 .sysc = &dra7xx_elm_sysc,
590};
591
592/* elm */
593
594static struct omap_hwmod dra7xx_elm_hwmod = {
595 .name = "elm",
596 .class = &dra7xx_elm_hwmod_class,
597 .clkdm_name = "l4per_clkdm",
598 .main_clk = "l3_iclk_div",
599 .prcm = {
600 .omap4 = {
601 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
602 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
603 },
604 },
605};
606
607/*
608 * 'gpio' class
609 *
610 */
611
612static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
613 .rev_offs = 0x0000,
614 .sysc_offs = 0x0010,
615 .syss_offs = 0x0114,
616 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
617 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
618 SYSS_HAS_RESET_STATUS),
619 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
620 SIDLE_SMART_WKUP),
621 .sysc_fields = &omap_hwmod_sysc_type1,
622};
623
624static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
625 .name = "gpio",
626 .sysc = &dra7xx_gpio_sysc,
627 .rev = 2,
628};
629
630/* gpio dev_attr */
631static struct omap_gpio_dev_attr gpio_dev_attr = {
632 .bank_width = 32,
633 .dbck_flag = true,
634};
635
636/* gpio1 */
637static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
638 { .role = "dbclk", .clk = "gpio1_dbclk" },
639};
640
641static struct omap_hwmod dra7xx_gpio1_hwmod = {
642 .name = "gpio1",
643 .class = &dra7xx_gpio_hwmod_class,
644 .clkdm_name = "wkupaon_clkdm",
645 .main_clk = "wkupaon_iclk_mux",
646 .prcm = {
647 .omap4 = {
648 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
649 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
650 .modulemode = MODULEMODE_HWCTRL,
651 },
652 },
653 .opt_clks = gpio1_opt_clks,
654 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
655 .dev_attr = &gpio_dev_attr,
656};
657
658/* gpio2 */
659static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
660 { .role = "dbclk", .clk = "gpio2_dbclk" },
661};
662
663static struct omap_hwmod dra7xx_gpio2_hwmod = {
664 .name = "gpio2",
665 .class = &dra7xx_gpio_hwmod_class,
666 .clkdm_name = "l4per_clkdm",
667 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
668 .main_clk = "l3_iclk_div",
669 .prcm = {
670 .omap4 = {
671 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
672 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
673 .modulemode = MODULEMODE_HWCTRL,
674 },
675 },
676 .opt_clks = gpio2_opt_clks,
677 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
678 .dev_attr = &gpio_dev_attr,
679};
680
681/* gpio3 */
682static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
683 { .role = "dbclk", .clk = "gpio3_dbclk" },
684};
685
686static struct omap_hwmod dra7xx_gpio3_hwmod = {
687 .name = "gpio3",
688 .class = &dra7xx_gpio_hwmod_class,
689 .clkdm_name = "l4per_clkdm",
690 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
691 .main_clk = "l3_iclk_div",
692 .prcm = {
693 .omap4 = {
694 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
695 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
696 .modulemode = MODULEMODE_HWCTRL,
697 },
698 },
699 .opt_clks = gpio3_opt_clks,
700 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
701 .dev_attr = &gpio_dev_attr,
702};
703
704/* gpio4 */
705static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
706 { .role = "dbclk", .clk = "gpio4_dbclk" },
707};
708
709static struct omap_hwmod dra7xx_gpio4_hwmod = {
710 .name = "gpio4",
711 .class = &dra7xx_gpio_hwmod_class,
712 .clkdm_name = "l4per_clkdm",
713 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
714 .main_clk = "l3_iclk_div",
715 .prcm = {
716 .omap4 = {
717 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
718 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
719 .modulemode = MODULEMODE_HWCTRL,
720 },
721 },
722 .opt_clks = gpio4_opt_clks,
723 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
724 .dev_attr = &gpio_dev_attr,
725};
726
727/* gpio5 */
728static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
729 { .role = "dbclk", .clk = "gpio5_dbclk" },
730};
731
732static struct omap_hwmod dra7xx_gpio5_hwmod = {
733 .name = "gpio5",
734 .class = &dra7xx_gpio_hwmod_class,
735 .clkdm_name = "l4per_clkdm",
736 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
737 .main_clk = "l3_iclk_div",
738 .prcm = {
739 .omap4 = {
740 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
741 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
742 .modulemode = MODULEMODE_HWCTRL,
743 },
744 },
745 .opt_clks = gpio5_opt_clks,
746 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
747 .dev_attr = &gpio_dev_attr,
748};
749
750/* gpio6 */
751static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
752 { .role = "dbclk", .clk = "gpio6_dbclk" },
753};
754
755static struct omap_hwmod dra7xx_gpio6_hwmod = {
756 .name = "gpio6",
757 .class = &dra7xx_gpio_hwmod_class,
758 .clkdm_name = "l4per_clkdm",
759 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
760 .main_clk = "l3_iclk_div",
761 .prcm = {
762 .omap4 = {
763 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
764 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
765 .modulemode = MODULEMODE_HWCTRL,
766 },
767 },
768 .opt_clks = gpio6_opt_clks,
769 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
770 .dev_attr = &gpio_dev_attr,
771};
772
773/* gpio7 */
774static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
775 { .role = "dbclk", .clk = "gpio7_dbclk" },
776};
777
778static struct omap_hwmod dra7xx_gpio7_hwmod = {
779 .name = "gpio7",
780 .class = &dra7xx_gpio_hwmod_class,
781 .clkdm_name = "l4per_clkdm",
782 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
783 .main_clk = "l3_iclk_div",
784 .prcm = {
785 .omap4 = {
786 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
787 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
788 .modulemode = MODULEMODE_HWCTRL,
789 },
790 },
791 .opt_clks = gpio7_opt_clks,
792 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
793 .dev_attr = &gpio_dev_attr,
794};
795
796/* gpio8 */
797static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
798 { .role = "dbclk", .clk = "gpio8_dbclk" },
799};
800
801static struct omap_hwmod dra7xx_gpio8_hwmod = {
802 .name = "gpio8",
803 .class = &dra7xx_gpio_hwmod_class,
804 .clkdm_name = "l4per_clkdm",
805 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
806 .main_clk = "l3_iclk_div",
807 .prcm = {
808 .omap4 = {
809 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
810 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
811 .modulemode = MODULEMODE_HWCTRL,
812 },
813 },
814 .opt_clks = gpio8_opt_clks,
815 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
816 .dev_attr = &gpio_dev_attr,
817};
818
819/*
820 * 'gpmc' class
821 *
822 */
823
824static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
825 .rev_offs = 0x0000,
826 .sysc_offs = 0x0010,
827 .syss_offs = 0x0014,
828 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
829 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
91a57731 830 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
90020c7b
A		 831 .sysc_fields = &omap_hwmod_sysc_type1,
832};
833
834static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
835 .name = "gpmc",
836 .sysc = &dra7xx_gpmc_sysc,
837};
838
839/* gpmc */
840
841static struct omap_hwmod dra7xx_gpmc_hwmod = {
842 .name = "gpmc",
843 .class = &dra7xx_gpmc_hwmod_class,
844 .clkdm_name = "l3main1_clkdm",
63aa945b 845 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
91a57731 846 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
90020c7b
A		 847 .main_clk = "l3_iclk_div",
848 .prcm = {
849 .omap4 = {
850 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
851 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
852 .modulemode = MODULEMODE_HWCTRL,
853 },
854 },
855};
856
857/*
858 * 'hdq1w' class
859 *
860 */
861
862static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
863 .rev_offs = 0x0000,
864 .sysc_offs = 0x0014,
865 .syss_offs = 0x0018,
866 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
867 SYSS_HAS_RESET_STATUS),
868 .sysc_fields = &omap_hwmod_sysc_type1,
869};
870
871static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
872 .name = "hdq1w",
873 .sysc = &dra7xx_hdq1w_sysc,
874};
875
876/* hdq1w */
877
878static struct omap_hwmod dra7xx_hdq1w_hwmod = {
879 .name = "hdq1w",
880 .class = &dra7xx_hdq1w_hwmod_class,
881 .clkdm_name = "l4per_clkdm",
882 .flags = HWMOD_INIT_NO_RESET,
883 .main_clk = "func_12m_fclk",
884 .prcm = {
885 .omap4 = {
886 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
887 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
888 .modulemode = MODULEMODE_SWCTRL,
889 },
890 },
891};
892
893/*
894 * 'i2c' class
895 *
896 */
897
898static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
899 .sysc_offs = 0x0010,
900 .syss_offs = 0x0090,
901 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
902 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
903 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
904 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
905 SIDLE_SMART_WKUP),
906 .clockact = CLOCKACT_TEST_ICLK,
907 .sysc_fields = &omap_hwmod_sysc_type1,
908};
909
910static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
911 .name = "i2c",
912 .sysc = &dra7xx_i2c_sysc,
913 .reset = &omap_i2c_reset,
914 .rev = OMAP_I2C_IP_VERSION_2,
915};
916
917/* i2c dev_attr */
918static struct omap_i2c_dev_attr i2c_dev_attr = {
919 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
920};
921
922/* i2c1 */
923static struct omap_hwmod dra7xx_i2c1_hwmod = {
924 .name = "i2c1",
925 .class = &dra7xx_i2c_hwmod_class,
926 .clkdm_name = "l4per_clkdm",
927 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
928 .main_clk = "func_96m_fclk",
929 .prcm = {
930 .omap4 = {
931 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
932 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
933 .modulemode = MODULEMODE_SWCTRL,
934 },
935 },
936 .dev_attr = &i2c_dev_attr,
937};
938
939/* i2c2 */
940static struct omap_hwmod dra7xx_i2c2_hwmod = {
941 .name = "i2c2",
942 .class = &dra7xx_i2c_hwmod_class,
943 .clkdm_name = "l4per_clkdm",
944 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
945 .main_clk = "func_96m_fclk",
946 .prcm = {
947 .omap4 = {
948 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
949 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
950 .modulemode = MODULEMODE_SWCTRL,
951 },
952 },
953 .dev_attr = &i2c_dev_attr,
954};
955
956/* i2c3 */
957static struct omap_hwmod dra7xx_i2c3_hwmod = {
958 .name = "i2c3",
959 .class = &dra7xx_i2c_hwmod_class,
960 .clkdm_name = "l4per_clkdm",
961 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
962 .main_clk = "func_96m_fclk",
963 .prcm = {
964 .omap4 = {
965 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
966 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
967 .modulemode = MODULEMODE_SWCTRL,
968 },
969 },
970 .dev_attr = &i2c_dev_attr,
971};
972
973/* i2c4 */
974static struct omap_hwmod dra7xx_i2c4_hwmod = {
975 .name = "i2c4",
976 .class = &dra7xx_i2c_hwmod_class,
977 .clkdm_name = "l4per_clkdm",
978 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
979 .main_clk = "func_96m_fclk",
980 .prcm = {
981 .omap4 = {
982 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
983 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
984 .modulemode = MODULEMODE_SWCTRL,
985 },
986 },
987 .dev_attr = &i2c_dev_attr,
988};
989
990/* i2c5 */
991static struct omap_hwmod dra7xx_i2c5_hwmod = {
992 .name = "i2c5",
993 .class = &dra7xx_i2c_hwmod_class,
994 .clkdm_name = "ipu_clkdm",
995 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
996 .main_clk = "func_96m_fclk",
997 .prcm = {
998 .omap4 = {
999 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1000 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1001 .modulemode = MODULEMODE_SWCTRL,
1002 },
1003 },
1004 .dev_attr = &i2c_dev_attr,
1005};
1006
067395d4
SA		 1007/*
1008 * 'mailbox' class
1009 *
1010 */
1011
1012static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1013 .rev_offs = 0x0000,
1014 .sysc_offs = 0x0010,
1015 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1016 SYSC_HAS_SOFTRESET),
1017 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1018 .sysc_fields = &omap_hwmod_sysc_type2,
1019};
1020
1021static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1022 .name = "mailbox",
1023 .sysc = &dra7xx_mailbox_sysc,
1024};
1025
1026/* mailbox1 */
1027static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1028 .name = "mailbox1",
1029 .class = &dra7xx_mailbox_hwmod_class,
1030 .clkdm_name = "l4cfg_clkdm",
1031 .prcm = {
1032 .omap4 = {
1033 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1034 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1035 },
1036 },
1037};
1038
1039/* mailbox2 */
1040static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1041 .name = "mailbox2",
1042 .class = &dra7xx_mailbox_hwmod_class,
1043 .clkdm_name = "l4cfg_clkdm",
1044 .prcm = {
1045 .omap4 = {
1046 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1047 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1048 },
1049 },
1050};
1051
1052/* mailbox3 */
1053static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1054 .name = "mailbox3",
1055 .class = &dra7xx_mailbox_hwmod_class,
1056 .clkdm_name = "l4cfg_clkdm",
1057 .prcm = {
1058 .omap4 = {
1059 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1060 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1061 },
1062 },
1063};
1064
1065/* mailbox4 */
1066static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1067 .name = "mailbox4",
1068 .class = &dra7xx_mailbox_hwmod_class,
1069 .clkdm_name = "l4cfg_clkdm",
1070 .prcm = {
1071 .omap4 = {
1072 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1073 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1074 },
1075 },
1076};
1077
1078/* mailbox5 */
1079static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1080 .name = "mailbox5",
1081 .class = &dra7xx_mailbox_hwmod_class,
1082 .clkdm_name = "l4cfg_clkdm",
1083 .prcm = {
1084 .omap4 = {
1085 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1086 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1087 },
1088 },
1089};
1090
1091/* mailbox6 */
1092static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1093 .name = "mailbox6",
1094 .class = &dra7xx_mailbox_hwmod_class,
1095 .clkdm_name = "l4cfg_clkdm",
1096 .prcm = {
1097 .omap4 = {
1098 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1099 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1100 },
1101 },
1102};
1103
1104/* mailbox7 */
1105static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1106 .name = "mailbox7",
1107 .class = &dra7xx_mailbox_hwmod_class,
1108 .clkdm_name = "l4cfg_clkdm",
1109 .prcm = {
1110 .omap4 = {
1111 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1112 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1113 },
1114 },
1115};
1116
1117/* mailbox8 */
1118static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1119 .name = "mailbox8",
1120 .class = &dra7xx_mailbox_hwmod_class,
1121 .clkdm_name = "l4cfg_clkdm",
1122 .prcm = {
1123 .omap4 = {
1124 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1125 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1126 },
1127 },
1128};
1129
1130/* mailbox9 */
1131static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1132 .name = "mailbox9",
1133 .class = &dra7xx_mailbox_hwmod_class,
1134 .clkdm_name = "l4cfg_clkdm",
1135 .prcm = {
1136 .omap4 = {
1137 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1138 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1139 },
1140 },
1141};
1142
1143/* mailbox10 */
1144static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1145 .name = "mailbox10",
1146 .class = &dra7xx_mailbox_hwmod_class,
1147 .clkdm_name = "l4cfg_clkdm",
1148 .prcm = {
1149 .omap4 = {
1150 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1151 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1152 },
1153 },
1154};
1155
1156/* mailbox11 */
1157static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1158 .name = "mailbox11",
1159 .class = &dra7xx_mailbox_hwmod_class,
1160 .clkdm_name = "l4cfg_clkdm",
1161 .prcm = {
1162 .omap4 = {
1163 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1164 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1165 },
1166 },
1167};
1168
1169/* mailbox12 */
1170static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1171 .name = "mailbox12",
1172 .class = &dra7xx_mailbox_hwmod_class,
1173 .clkdm_name = "l4cfg_clkdm",
1174 .prcm = {
1175 .omap4 = {
1176 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1177 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1178 },
1179 },
1180};
1181
1182/* mailbox13 */
1183static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1184 .name = "mailbox13",
1185 .class = &dra7xx_mailbox_hwmod_class,
1186 .clkdm_name = "l4cfg_clkdm",
1187 .prcm = {
1188 .omap4 = {
1189 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1190 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1191 },
1192 },
1193};
1194
90020c7b
A		 1195/*
1196 * 'mcspi' class
1197 *
1198 */
1199
1200static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1201 .rev_offs = 0x0000,
1202 .sysc_offs = 0x0010,
1203 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1204 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1205 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1206 SIDLE_SMART_WKUP),
1207 .sysc_fields = &omap_hwmod_sysc_type2,
1208};
1209
1210static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1211 .name = "mcspi",
1212 .sysc = &dra7xx_mcspi_sysc,
1213 .rev = OMAP4_MCSPI_REV,
1214};
1215
1216/* mcspi1 */
1217/* mcspi1 dev_attr */
1218static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1219 .num_chipselect = 4,
1220};
1221
1222static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1223 .name = "mcspi1",
1224 .class = &dra7xx_mcspi_hwmod_class,
1225 .clkdm_name = "l4per_clkdm",
1226 .main_clk = "func_48m_fclk",
1227 .prcm = {
1228 .omap4 = {
1229 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1230 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1231 .modulemode = MODULEMODE_SWCTRL,
1232 },
1233 },
1234 .dev_attr = &mcspi1_dev_attr,
1235};
1236
1237/* mcspi2 */
1238/* mcspi2 dev_attr */
1239static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1240 .num_chipselect = 2,
1241};
1242
1243static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1244 .name = "mcspi2",
1245 .class = &dra7xx_mcspi_hwmod_class,
1246 .clkdm_name = "l4per_clkdm",
1247 .main_clk = "func_48m_fclk",
1248 .prcm = {
1249 .omap4 = {
1250 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1251 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1252 .modulemode = MODULEMODE_SWCTRL,
1253 },
1254 },
1255 .dev_attr = &mcspi2_dev_attr,
1256};
1257
1258/* mcspi3 */
1259/* mcspi3 dev_attr */
1260static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1261 .num_chipselect = 2,
1262};
1263
1264static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1265 .name = "mcspi3",
1266 .class = &dra7xx_mcspi_hwmod_class,
1267 .clkdm_name = "l4per_clkdm",
1268 .main_clk = "func_48m_fclk",
1269 .prcm = {
1270 .omap4 = {
1271 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1272 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1273 .modulemode = MODULEMODE_SWCTRL,
1274 },
1275 },
1276 .dev_attr = &mcspi3_dev_attr,
1277};
1278
1279/* mcspi4 */
1280/* mcspi4 dev_attr */
1281static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1282 .num_chipselect = 1,
1283};
1284
1285static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1286 .name = "mcspi4",
1287 .class = &dra7xx_mcspi_hwmod_class,
1288 .clkdm_name = "l4per_clkdm",
1289 .main_clk = "func_48m_fclk",
1290 .prcm = {
1291 .omap4 = {
1292 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1293 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1294 .modulemode = MODULEMODE_SWCTRL,
1295 },
1296 },
1297 .dev_attr = &mcspi4_dev_attr,
1298};
1299
469689a4
PU		 1300/*
1301 * 'mcasp' class
1302 *
1303 */
1304static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1305 .sysc_offs = 0x0004,
1306 .sysc_flags = SYSC_HAS_SIDLEMODE,
1307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1308 .sysc_fields = &omap_hwmod_sysc_type3,
1309};
1310
1311static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1312 .name = "mcasp",
1313 .sysc = &dra7xx_mcasp_sysc,
1314};
1315
1316/* mcasp3 */
1317static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
1318 { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
1319};
1320
1321static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1322 .name = "mcasp3",
1323 .class = &dra7xx_mcasp_hwmod_class,
1324 .clkdm_name = "l4per2_clkdm",
1325 .main_clk = "mcasp3_aux_gfclk_mux",
1326 .flags = HWMOD_OPT_CLKS_NEEDED,
1327 .prcm = {
1328 .omap4 = {
1329 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1330 .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1331 .modulemode = MODULEMODE_SWCTRL,
1332 },
1333 },
1334 .opt_clks = mcasp3_opt_clks,
1335 .opt_clks_cnt = ARRAY_SIZE(mcasp3_opt_clks),
1336};
1337
90020c7b
A		 1338/*
1339 * 'mmc' class
1340 *
1341 */
1342
1343static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1344 .rev_offs = 0x0000,
1345 .sysc_offs = 0x0010,
1346 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1347 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1348 SYSC_HAS_SOFTRESET),
1349 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1350 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1351 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1352 .sysc_fields = &omap_hwmod_sysc_type2,
1353};
1354
1355static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1356 .name = "mmc",
1357 .sysc = &dra7xx_mmc_sysc,
1358};
1359
1360/* mmc1 */
1361static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1362 { .role = "clk32k", .clk = "mmc1_clk32k" },
1363};
1364
1365/* mmc1 dev_attr */
55143438 1366static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
90020c7b
A		 1367 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1368};
1369
1370static struct omap_hwmod dra7xx_mmc1_hwmod = {
1371 .name = "mmc1",
1372 .class = &dra7xx_mmc_hwmod_class,
1373 .clkdm_name = "l3init_clkdm",
1374 .main_clk = "mmc1_fclk_div",
1375 .prcm = {
1376 .omap4 = {
1377 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1378 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1379 .modulemode = MODULEMODE_SWCTRL,
1380 },
1381 },
1382 .opt_clks = mmc1_opt_clks,
1383 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1384 .dev_attr = &mmc1_dev_attr,
1385};
1386
1387/* mmc2 */
1388static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1389 { .role = "clk32k", .clk = "mmc2_clk32k" },
1390};
1391
1392static struct omap_hwmod dra7xx_mmc2_hwmod = {
1393 .name = "mmc2",
1394 .class = &dra7xx_mmc_hwmod_class,
1395 .clkdm_name = "l3init_clkdm",
1396 .main_clk = "mmc2_fclk_div",
1397 .prcm = {
1398 .omap4 = {
1399 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1400 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1401 .modulemode = MODULEMODE_SWCTRL,
1402 },
1403 },
1404 .opt_clks = mmc2_opt_clks,
1405 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1406};
1407
1408/* mmc3 */
1409static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1410 { .role = "clk32k", .clk = "mmc3_clk32k" },
1411};
1412
1413static struct omap_hwmod dra7xx_mmc3_hwmod = {
1414 .name = "mmc3",
1415 .class = &dra7xx_mmc_hwmod_class,
1416 .clkdm_name = "l4per_clkdm",
1417 .main_clk = "mmc3_gfclk_div",
1418 .prcm = {
1419 .omap4 = {
1420 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1421 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1422 .modulemode = MODULEMODE_SWCTRL,
1423 },
1424 },
1425 .opt_clks = mmc3_opt_clks,
1426 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1427};
1428
1429/* mmc4 */
1430static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1431 { .role = "clk32k", .clk = "mmc4_clk32k" },
1432};
1433
1434static struct omap_hwmod dra7xx_mmc4_hwmod = {
1435 .name = "mmc4",
1436 .class = &dra7xx_mmc_hwmod_class,
1437 .clkdm_name = "l4per_clkdm",
1438 .main_clk = "mmc4_gfclk_div",
1439 .prcm = {
1440 .omap4 = {
1441 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1442 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1443 .modulemode = MODULEMODE_SWCTRL,
1444 },
1445 },
1446 .opt_clks = mmc4_opt_clks,
1447 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1448};
1449
1450/*
1451 * 'mpu' class
1452 *
1453 */
1454
1455static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1456 .name = "mpu",
1457};
1458
1459/* mpu */
1460static struct omap_hwmod dra7xx_mpu_hwmod = {
1461 .name = "mpu",
1462 .class = &dra7xx_mpu_hwmod_class,
1463 .clkdm_name = "mpu_clkdm",
1464 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1465 .main_clk = "dpll_mpu_m2_ck",
1466 .prcm = {
1467 .omap4 = {
1468 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1469 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1470 },
1471 },
1472};
1473
1474/*
1475 * 'ocp2scp' class
1476 *
1477 */
1478
1479static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1480 .rev_offs = 0x0000,
1481 .sysc_offs = 0x0010,
1482 .syss_offs = 0x0014,
1483 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1484 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4965be1f 1485 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
90020c7b
A		 1486 .sysc_fields = &omap_hwmod_sysc_type1,
1487};
1488
1489static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1490 .name = "ocp2scp",
1491 .sysc = &dra7xx_ocp2scp_sysc,
1492};
1493
1494/* ocp2scp1 */
1495static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1496 .name = "ocp2scp1",
1497 .class = &dra7xx_ocp2scp_hwmod_class,
1498 .clkdm_name = "l3init_clkdm",
1499 .main_clk = "l4_root_clk_div",
1500 .prcm = {
1501 .omap4 = {
1502 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1503 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1504 .modulemode = MODULEMODE_HWCTRL,
1505 },
1506 },
1507};
1508
df0d0f11
RQ		 1509/* ocp2scp3 */
1510static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1511 .name = "ocp2scp3",
1512 .class = &dra7xx_ocp2scp_hwmod_class,
1513 .clkdm_name = "l3init_clkdm",
1514 .main_clk = "l4_root_clk_div",
1515 .prcm = {
1516 .omap4 = {
1517 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1518 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1519 .modulemode = MODULEMODE_HWCTRL,
1520 },
1521 },
1522};
1523
8dd3eb71
KVA		 1524/*
1525 * 'PCIE' class
1526 *
1527 */
1528
0717103e 1529static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
8dd3eb71
KVA		 1530 .name = "pcie",
1531};
1532
1533/* pcie1 */
0717103e 1534static struct omap_hwmod dra7xx_pciess1_hwmod = {
8dd3eb71 1535 .name = "pcie1",
0717103e 1536 .class = &dra7xx_pciess_hwmod_class,
8dd3eb71
KVA		 1537 .clkdm_name = "pcie_clkdm",
1538 .main_clk = "l4_root_clk_div",
70c18ef7
KVA		 1539 .prcm = {
1540 .omap4 = {
1541 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1542 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1543 .modulemode = MODULEMODE_SWCTRL,
1544 },
1545 },
1546};
1547
0717103e
KVA		 1548/* pcie2 */
1549static struct omap_hwmod dra7xx_pciess2_hwmod = {
1550 .name = "pcie2",
1551 .class = &dra7xx_pciess_hwmod_class,
1552 .clkdm_name = "pcie_clkdm",
70c18ef7
KVA		 1553 .main_clk = "l4_root_clk_div",
1554 .prcm = {
1555 .omap4 = {
1556 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1557 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1558 .modulemode = MODULEMODE_SWCTRL,
1559 },
1560 },
1561};
1562
90020c7b
A		 1563/*
1564 * 'qspi' class
1565 *
1566 */
1567
1568static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1569 .sysc_offs = 0x0010,
1570 .sysc_flags = SYSC_HAS_SIDLEMODE,
1571 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1572 SIDLE_SMART_WKUP),
1573 .sysc_fields = &omap_hwmod_sysc_type2,
1574};
1575
1576static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1577 .name = "qspi",
1578 .sysc = &dra7xx_qspi_sysc,
1579};
1580
1581/* qspi */
1582static struct omap_hwmod dra7xx_qspi_hwmod = {
1583 .name = "qspi",
1584 .class = &dra7xx_qspi_hwmod_class,
1585 .clkdm_name = "l4per2_clkdm",
1586 .main_clk = "qspi_gfclk_div",
1587 .prcm = {
1588 .omap4 = {
1589 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1590 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1591 .modulemode = MODULEMODE_SWCTRL,
1592 },
1593 },
1594};
1595
c913c8a1
LV		 1596/*
1597 * 'rtcss' class
1598 *
1599 */
1600static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1601 .sysc_offs = 0x0078,
1602 .sysc_flags = SYSC_HAS_SIDLEMODE,
1603 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1604 SIDLE_SMART_WKUP),
1605 .sysc_fields = &omap_hwmod_sysc_type3,
1606};
1607
1608static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1609 .name = "rtcss",
1610 .sysc = &dra7xx_rtcss_sysc,
1611};
1612
1613/* rtcss */
1614static struct omap_hwmod dra7xx_rtcss_hwmod = {
1615 .name = "rtcss",
1616 .class = &dra7xx_rtcss_hwmod_class,
1617 .clkdm_name = "rtc_clkdm",
1618 .main_clk = "sys_32k_ck",
1619 .prcm = {
1620 .omap4 = {
1621 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1622 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1623 .modulemode = MODULEMODE_SWCTRL,
1624 },
1625 },
1626};
1627
90020c7b
A		 1628/*
1629 * 'sata' class
1630 *
1631 */
1632
1633static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1634 .sysc_offs = 0x0000,
1635 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1636 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1637 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1638 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1639 .sysc_fields = &omap_hwmod_sysc_type2,
1640};
1641
1642static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1643 .name = "sata",
1644 .sysc = &dra7xx_sata_sysc,
1645};
1646
1647/* sata */
90020c7b
A		 1648
1649static struct omap_hwmod dra7xx_sata_hwmod = {
1650 .name = "sata",
1651 .class = &dra7xx_sata_hwmod_class,
1652 .clkdm_name = "l3init_clkdm",
1653 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1654 .main_clk = "func_48m_fclk",
1ea0999e 1655 .mpu_rt_idx = 1,
90020c7b
A		 1656 .prcm = {
1657 .omap4 = {
1658 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1659 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1660 .modulemode = MODULEMODE_SWCTRL,
1661 },
1662 },
90020c7b
A		 1663};
1664
1665/*
1666 * 'smartreflex' class
1667 *
1668 */
1669
1670/* The IP is not compliant to type1 / type2 scheme */
1671static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1672 .sidle_shift = 24,
1673 .enwkup_shift = 26,
1674};
1675
1676static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1677 .sysc_offs = 0x0038,
1678 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1679 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1680 SIDLE_SMART_WKUP),
1681 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1682};
1683
1684static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1685 .name = "smartreflex",
1686 .sysc = &dra7xx_smartreflex_sysc,
1687 .rev = 2,
1688};
1689
1690/* smartreflex_core */
1691/* smartreflex_core dev_attr */
1692static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1693 .sensor_voltdm_name = "core",
1694};
1695
1696static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1697 .name = "smartreflex_core",
1698 .class = &dra7xx_smartreflex_hwmod_class,
1699 .clkdm_name = "coreaon_clkdm",
1700 .main_clk = "wkupaon_iclk_mux",
1701 .prcm = {
1702 .omap4 = {
1703 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1704 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1705 .modulemode = MODULEMODE_SWCTRL,
1706 },
1707 },
1708 .dev_attr = &smartreflex_core_dev_attr,
1709};
1710
1711/* smartreflex_mpu */
1712/* smartreflex_mpu dev_attr */
1713static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1714 .sensor_voltdm_name = "mpu",
1715};
1716
1717static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1718 .name = "smartreflex_mpu",
1719 .class = &dra7xx_smartreflex_hwmod_class,
1720 .clkdm_name = "coreaon_clkdm",
1721 .main_clk = "wkupaon_iclk_mux",
1722 .prcm = {
1723 .omap4 = {
1724 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1725 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1726 .modulemode = MODULEMODE_SWCTRL,
1727 },
1728 },
1729 .dev_attr = &smartreflex_mpu_dev_attr,
1730};
1731
1732/*
1733 * 'spinlock' class
1734 *
1735 */
1736
1737static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1738 .rev_offs = 0x0000,
1739 .sysc_offs = 0x0010,
1740 .syss_offs = 0x0014,
c317d0f2
SA		 1741 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1742 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1743 SYSS_HAS_RESET_STATUS),
1744 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
90020c7b
A		 1745 .sysc_fields = &omap_hwmod_sysc_type1,
1746};
1747
1748static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1749 .name = "spinlock",
1750 .sysc = &dra7xx_spinlock_sysc,
1751};
1752
1753/* spinlock */
1754static struct omap_hwmod dra7xx_spinlock_hwmod = {
1755 .name = "spinlock",
1756 .class = &dra7xx_spinlock_hwmod_class,
1757 .clkdm_name = "l4cfg_clkdm",
1758 .main_clk = "l3_iclk_div",
1759 .prcm = {
1760 .omap4 = {
1761 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1762 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1763 },
1764 },
1765};
1766
1767/*
1768 * 'timer' class
1769 *
1770 * This class contains several variants: ['timer_1ms', 'timer_secure',
1771 * 'timer']
1772 */
1773
1774static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1775 .rev_offs = 0x0000,
1776 .sysc_offs = 0x0010,
1777 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1778 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1779 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1780 SIDLE_SMART_WKUP),
1781 .sysc_fields = &omap_hwmod_sysc_type2,
1782};
1783
1784static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1785 .name = "timer",
1786 .sysc = &dra7xx_timer_1ms_sysc,
1787};
1788
90020c7b
A		 1789static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1790 .rev_offs = 0x0000,
1791 .sysc_offs = 0x0010,
1792 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1793 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1794 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1795 SIDLE_SMART_WKUP),
1796 .sysc_fields = &omap_hwmod_sysc_type2,
1797};
1798
1799static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1800 .name = "timer",
1801 .sysc = &dra7xx_timer_sysc,
1802};
1803
1804/* timer1 */
1805static struct omap_hwmod dra7xx_timer1_hwmod = {
1806 .name = "timer1",
1807 .class = &dra7xx_timer_1ms_hwmod_class,
1808 .clkdm_name = "wkupaon_clkdm",
1809 .main_clk = "timer1_gfclk_mux",
1810 .prcm = {
1811 .omap4 = {
1812 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1813 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1814 .modulemode = MODULEMODE_SWCTRL,
1815 },
1816 },
1817};
1818
1819/* timer2 */
1820static struct omap_hwmod dra7xx_timer2_hwmod = {
1821 .name = "timer2",
1822 .class = &dra7xx_timer_1ms_hwmod_class,
1823 .clkdm_name = "l4per_clkdm",
1824 .main_clk = "timer2_gfclk_mux",
1825 .prcm = {
1826 .omap4 = {
1827 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1828 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1829 .modulemode = MODULEMODE_SWCTRL,
1830 },
1831 },
1832};
1833
1834/* timer3 */
1835static struct omap_hwmod dra7xx_timer3_hwmod = {
1836 .name = "timer3",
1837 .class = &dra7xx_timer_hwmod_class,
1838 .clkdm_name = "l4per_clkdm",
1839 .main_clk = "timer3_gfclk_mux",
1840 .prcm = {
1841 .omap4 = {
1842 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1843 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1844 .modulemode = MODULEMODE_SWCTRL,
1845 },
1846 },
1847};
1848
1849/* timer4 */
1850static struct omap_hwmod dra7xx_timer4_hwmod = {
1851 .name = "timer4",
edec1786 1852 .class = &dra7xx_timer_hwmod_class,
90020c7b
A		 1853 .clkdm_name = "l4per_clkdm",
1854 .main_clk = "timer4_gfclk_mux",
1855 .prcm = {
1856 .omap4 = {
1857 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1858 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1859 .modulemode = MODULEMODE_SWCTRL,
1860 },
1861 },
1862};
1863
1864/* timer5 */
1865static struct omap_hwmod dra7xx_timer5_hwmod = {
1866 .name = "timer5",
1867 .class = &dra7xx_timer_hwmod_class,
1868 .clkdm_name = "ipu_clkdm",
1869 .main_clk = "timer5_gfclk_mux",
1870 .prcm = {
1871 .omap4 = {
1872 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1873 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1874 .modulemode = MODULEMODE_SWCTRL,
1875 },
1876 },
1877};
1878
1879/* timer6 */
1880static struct omap_hwmod dra7xx_timer6_hwmod = {
1881 .name = "timer6",
1882 .class = &dra7xx_timer_hwmod_class,
1883 .clkdm_name = "ipu_clkdm",
1884 .main_clk = "timer6_gfclk_mux",
1885 .prcm = {
1886 .omap4 = {
1887 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1888 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1889 .modulemode = MODULEMODE_SWCTRL,
1890 },
1891 },
1892};
1893
1894/* timer7 */
1895static struct omap_hwmod dra7xx_timer7_hwmod = {
1896 .name = "timer7",
1897 .class = &dra7xx_timer_hwmod_class,
1898 .clkdm_name = "ipu_clkdm",
1899 .main_clk = "timer7_gfclk_mux",
1900 .prcm = {
1901 .omap4 = {
1902 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1903 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1904 .modulemode = MODULEMODE_SWCTRL,
1905 },
1906 },
1907};
1908
1909/* timer8 */
1910static struct omap_hwmod dra7xx_timer8_hwmod = {
1911 .name = "timer8",
1912 .class = &dra7xx_timer_hwmod_class,
1913 .clkdm_name = "ipu_clkdm",
1914 .main_clk = "timer8_gfclk_mux",
1915 .prcm = {
1916 .omap4 = {
1917 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1918 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1919 .modulemode = MODULEMODE_SWCTRL,
1920 },
1921 },
1922};
1923
1924/* timer9 */
1925static struct omap_hwmod dra7xx_timer9_hwmod = {
1926 .name = "timer9",
1927 .class = &dra7xx_timer_hwmod_class,
1928 .clkdm_name = "l4per_clkdm",
1929 .main_clk = "timer9_gfclk_mux",
1930 .prcm = {
1931 .omap4 = {
1932 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1933 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1934 .modulemode = MODULEMODE_SWCTRL,
1935 },
1936 },
1937};
1938
1939/* timer10 */
1940static struct omap_hwmod dra7xx_timer10_hwmod = {
1941 .name = "timer10",
1942 .class = &dra7xx_timer_1ms_hwmod_class,
1943 .clkdm_name = "l4per_clkdm",
1944 .main_clk = "timer10_gfclk_mux",
1945 .prcm = {
1946 .omap4 = {
1947 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1948 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1949 .modulemode = MODULEMODE_SWCTRL,
1950 },
1951 },
1952};
1953
1954/* timer11 */
1955static struct omap_hwmod dra7xx_timer11_hwmod = {
1956 .name = "timer11",
1957 .class = &dra7xx_timer_hwmod_class,
1958 .clkdm_name = "l4per_clkdm",
1959 .main_clk = "timer11_gfclk_mux",
1960 .prcm = {
1961 .omap4 = {
1962 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1963 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1964 .modulemode = MODULEMODE_SWCTRL,
1965 },
1966 },
1967};
1968
1ac964f4
SA		 1969/* timer13 */
1970static struct omap_hwmod dra7xx_timer13_hwmod = {
1971 .name = "timer13",
1972 .class = &dra7xx_timer_hwmod_class,
1973 .clkdm_name = "l4per3_clkdm",
1974 .main_clk = "timer13_gfclk_mux",
1975 .prcm = {
1976 .omap4 = {
1977 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
1978 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
1979 .modulemode = MODULEMODE_SWCTRL,
1980 },
1981 },
1982};
1983
1984/* timer14 */
1985static struct omap_hwmod dra7xx_timer14_hwmod = {
1986 .name = "timer14",
1987 .class = &dra7xx_timer_hwmod_class,
1988 .clkdm_name = "l4per3_clkdm",
1989 .main_clk = "timer14_gfclk_mux",
1990 .prcm = {
1991 .omap4 = {
1992 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
1993 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
1994 .modulemode = MODULEMODE_SWCTRL,
1995 },
1996 },
1997};
1998
1999/* timer15 */
2000static struct omap_hwmod dra7xx_timer15_hwmod = {
2001 .name = "timer15",
2002 .class = &dra7xx_timer_hwmod_class,
2003 .clkdm_name = "l4per3_clkdm",
2004 .main_clk = "timer15_gfclk_mux",
2005 .prcm = {
2006 .omap4 = {
2007 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2008 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2009 .modulemode = MODULEMODE_SWCTRL,
2010 },
2011 },
2012};
2013
2014/* timer16 */
2015static struct omap_hwmod dra7xx_timer16_hwmod = {
2016 .name = "timer16",
2017 .class = &dra7xx_timer_hwmod_class,
2018 .clkdm_name = "l4per3_clkdm",
2019 .main_clk = "timer16_gfclk_mux",
2020 .prcm = {
2021 .omap4 = {
2022 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2023 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2024 .modulemode = MODULEMODE_SWCTRL,
2025 },
2026 },
2027};
2028
90020c7b
A		 2029/*
2030 * 'uart' class
2031 *
2032 */
2033
2034static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2035 .rev_offs = 0x0050,
2036 .sysc_offs = 0x0054,
2037 .syss_offs = 0x0058,
2038 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2039 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2040 SYSS_HAS_RESET_STATUS),
2041 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2042 SIDLE_SMART_WKUP),
2043 .sysc_fields = &omap_hwmod_sysc_type1,
2044};
2045
2046static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2047 .name = "uart",
2048 .sysc = &dra7xx_uart_sysc,
2049};
2050
2051/* uart1 */
2052static struct omap_hwmod dra7xx_uart1_hwmod = {
2053 .name = "uart1",
2054 .class = &dra7xx_uart_hwmod_class,
2055 .clkdm_name = "l4per_clkdm",
2056 .main_clk = "uart1_gfclk_mux",
38958c15 2057 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
90020c7b
A		 2058 .prcm = {
2059 .omap4 = {
2060 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2061 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2062 .modulemode = MODULEMODE_SWCTRL,
2063 },
2064 },
2065};
2066
2067/* uart2 */
2068static struct omap_hwmod dra7xx_uart2_hwmod = {
2069 .name = "uart2",
2070 .class = &dra7xx_uart_hwmod_class,
2071 .clkdm_name = "l4per_clkdm",
2072 .main_clk = "uart2_gfclk_mux",
2073 .flags = HWMOD_SWSUP_SIDLE_ACT,
2074 .prcm = {
2075 .omap4 = {
2076 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2077 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2078 .modulemode = MODULEMODE_SWCTRL,
2079 },
2080 },
2081};
2082
2083/* uart3 */
2084static struct omap_hwmod dra7xx_uart3_hwmod = {
2085 .name = "uart3",
2086 .class = &dra7xx_uart_hwmod_class,
2087 .clkdm_name = "l4per_clkdm",
2088 .main_clk = "uart3_gfclk_mux",
1c7e36bf 2089 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
90020c7b
A		 2090 .prcm = {
2091 .omap4 = {
2092 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2093 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2094 .modulemode = MODULEMODE_SWCTRL,
2095 },
2096 },
2097};
2098
2099/* uart4 */
2100static struct omap_hwmod dra7xx_uart4_hwmod = {
2101 .name = "uart4",
2102 .class = &dra7xx_uart_hwmod_class,
2103 .clkdm_name = "l4per_clkdm",
2104 .main_clk = "uart4_gfclk_mux",
b0340850 2105 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART4_FLAGS,
90020c7b
A		 2106 .prcm = {
2107 .omap4 = {
2108 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2109 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2110 .modulemode = MODULEMODE_SWCTRL,
2111 },
2112 },
2113};
2114
2115/* uart5 */
2116static struct omap_hwmod dra7xx_uart5_hwmod = {
2117 .name = "uart5",
2118 .class = &dra7xx_uart_hwmod_class,
2119 .clkdm_name = "l4per_clkdm",
2120 .main_clk = "uart5_gfclk_mux",
2121 .flags = HWMOD_SWSUP_SIDLE_ACT,
2122 .prcm = {
2123 .omap4 = {
2124 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2125 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2126 .modulemode = MODULEMODE_SWCTRL,
2127 },
2128 },
2129};
2130
2131/* uart6 */
2132static struct omap_hwmod dra7xx_uart6_hwmod = {
2133 .name = "uart6",
2134 .class = &dra7xx_uart_hwmod_class,
2135 .clkdm_name = "ipu_clkdm",
2136 .main_clk = "uart6_gfclk_mux",
2137 .flags = HWMOD_SWSUP_SIDLE_ACT,
2138 .prcm = {
2139 .omap4 = {
2140 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2141 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2142 .modulemode = MODULEMODE_SWCTRL,
2143 },
2144 },
2145};
2146
33acc9ff
A		 2147/* uart7 */
2148static struct omap_hwmod dra7xx_uart7_hwmod = {
2149 .name = "uart7",
2150 .class = &dra7xx_uart_hwmod_class,
2151 .clkdm_name = "l4per2_clkdm",
2152 .main_clk = "uart7_gfclk_mux",
2153 .flags = HWMOD_SWSUP_SIDLE_ACT,
2154 .prcm = {
2155 .omap4 = {
2156 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2157 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2158 .modulemode = MODULEMODE_SWCTRL,
2159 },
2160 },
2161};
2162
2163/* uart8 */
2164static struct omap_hwmod dra7xx_uart8_hwmod = {
2165 .name = "uart8",
2166 .class = &dra7xx_uart_hwmod_class,
2167 .clkdm_name = "l4per2_clkdm",
2168 .main_clk = "uart8_gfclk_mux",
2169 .flags = HWMOD_SWSUP_SIDLE_ACT,
2170 .prcm = {
2171 .omap4 = {
2172 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2173 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2174 .modulemode = MODULEMODE_SWCTRL,
2175 },
2176 },
2177};
2178
2179/* uart9 */
2180static struct omap_hwmod dra7xx_uart9_hwmod = {
2181 .name = "uart9",
2182 .class = &dra7xx_uart_hwmod_class,
2183 .clkdm_name = "l4per2_clkdm",
2184 .main_clk = "uart9_gfclk_mux",
2185 .flags = HWMOD_SWSUP_SIDLE_ACT,
2186 .prcm = {
2187 .omap4 = {
2188 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2189 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2190 .modulemode = MODULEMODE_SWCTRL,
2191 },
2192 },
2193};
2194
2195/* uart10 */
2196static struct omap_hwmod dra7xx_uart10_hwmod = {
2197 .name = "uart10",
2198 .class = &dra7xx_uart_hwmod_class,
2199 .clkdm_name = "wkupaon_clkdm",
2200 .main_clk = "uart10_gfclk_mux",
2201 .flags = HWMOD_SWSUP_SIDLE_ACT,
2202 .prcm = {
2203 .omap4 = {
2204 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2205 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2206 .modulemode = MODULEMODE_SWCTRL,
2207 },
2208 },
2209};
2210
90020c7b
A		 2211/*
2212 * 'usb_otg_ss' class
2213 *
2214 */
2215
d904b38d
RQ		 2216static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2217 .rev_offs = 0x0000,
2218 .sysc_offs = 0x0010,
2219 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2220 SYSC_HAS_SIDLEMODE),
2221 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2222 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2223 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2224 .sysc_fields = &omap_hwmod_sysc_type2,
2225};
2226
90020c7b
A		 2227static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2228 .name = "usb_otg_ss",
d904b38d 2229 .sysc = &dra7xx_usb_otg_ss_sysc,
90020c7b
A		 2230};
2231
2232/* usb_otg_ss1 */
2233static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2234 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2235};
2236
2237static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2238 .name = "usb_otg_ss1",
2239 .class = &dra7xx_usb_otg_ss_hwmod_class,
2240 .clkdm_name = "l3init_clkdm",
2241 .main_clk = "dpll_core_h13x2_ck",
2242 .prcm = {
2243 .omap4 = {
2244 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2245 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2246 .modulemode = MODULEMODE_HWCTRL,
2247 },
2248 },
2249 .opt_clks = usb_otg_ss1_opt_clks,
2250 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2251};
2252
2253/* usb_otg_ss2 */
2254static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2255 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2256};
2257
2258static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2259 .name = "usb_otg_ss2",
2260 .class = &dra7xx_usb_otg_ss_hwmod_class,
2261 .clkdm_name = "l3init_clkdm",
2262 .main_clk = "dpll_core_h13x2_ck",
2263 .prcm = {
2264 .omap4 = {
2265 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2266 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2267 .modulemode = MODULEMODE_HWCTRL,
2268 },
2269 },
2270 .opt_clks = usb_otg_ss2_opt_clks,
2271 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2272};
2273
2274/* usb_otg_ss3 */
2275static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2276 .name = "usb_otg_ss3",
2277 .class = &dra7xx_usb_otg_ss_hwmod_class,
2278 .clkdm_name = "l3init_clkdm",
2279 .main_clk = "dpll_core_h13x2_ck",
2280 .prcm = {
2281 .omap4 = {
2282 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2283 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2284 .modulemode = MODULEMODE_HWCTRL,
2285 },
2286 },
2287};
2288
2289/* usb_otg_ss4 */
2290static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2291 .name = "usb_otg_ss4",
2292 .class = &dra7xx_usb_otg_ss_hwmod_class,
2293 .clkdm_name = "l3init_clkdm",
2294 .main_clk = "dpll_core_h13x2_ck",
2295 .prcm = {
2296 .omap4 = {
2297 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2298 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2299 .modulemode = MODULEMODE_HWCTRL,
2300 },
2301 },
2302};
2303
2304/*
2305 * 'vcp' class
2306 *
2307 */
2308
2309static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2310 .name = "vcp",
2311};
2312
2313/* vcp1 */
2314static struct omap_hwmod dra7xx_vcp1_hwmod = {
2315 .name = "vcp1",
2316 .class = &dra7xx_vcp_hwmod_class,
2317 .clkdm_name = "l3main1_clkdm",
2318 .main_clk = "l3_iclk_div",
2319 .prcm = {
2320 .omap4 = {
2321 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2322 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2323 },
2324 },
2325};
2326
2327/* vcp2 */
2328static struct omap_hwmod dra7xx_vcp2_hwmod = {
2329 .name = "vcp2",
2330 .class = &dra7xx_vcp_hwmod_class,
2331 .clkdm_name = "l3main1_clkdm",
2332 .main_clk = "l3_iclk_div",
2333 .prcm = {
2334 .omap4 = {
2335 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2336 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2337 },
2338 },
2339};
2340
2341/*
2342 * 'wd_timer' class
2343 *
2344 */
2345
2346static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2347 .rev_offs = 0x0000,
2348 .sysc_offs = 0x0010,
2349 .syss_offs = 0x0014,
2350 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2351 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2352 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2353 SIDLE_SMART_WKUP),
2354 .sysc_fields = &omap_hwmod_sysc_type1,
2355};
2356
2357static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2358 .name = "wd_timer",
2359 .sysc = &dra7xx_wd_timer_sysc,
2360 .pre_shutdown = &omap2_wd_timer_disable,
2361 .reset = &omap2_wd_timer_reset,
2362};
2363
2364/* wd_timer2 */
2365static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2366 .name = "wd_timer2",
2367 .class = &dra7xx_wd_timer_hwmod_class,
2368 .clkdm_name = "wkupaon_clkdm",
2369 .main_clk = "sys_32k_ck",
2370 .prcm = {
2371 .omap4 = {
2372 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2373 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2374 .modulemode = MODULEMODE_SWCTRL,
2375 },
2376 },
2377};
2378
2379
2380/*
2381 * Interfaces
2382 */
2383
42121688
TV		 2384/* l3_main_1 -> dmm */
2385static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2386 .master = &dra7xx_l3_main_1_hwmod,
2387 .slave = &dra7xx_dmm_hwmod,
2388 .clk = "l3_iclk_div",
2389 .user = OCP_USER_SDMA,
2390};
2391
90020c7b
A		 2392/* l3_main_2 -> l3_instr */
2393static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2394 .master = &dra7xx_l3_main_2_hwmod,
2395 .slave = &dra7xx_l3_instr_hwmod,
2396 .clk = "l3_iclk_div",
2397 .user = OCP_USER_MPU | OCP_USER_SDMA,
2398};
2399
2400/* l4_cfg -> l3_main_1 */
2401static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2402 .master = &dra7xx_l4_cfg_hwmod,
2403 .slave = &dra7xx_l3_main_1_hwmod,
2404 .clk = "l3_iclk_div",
2405 .user = OCP_USER_MPU | OCP_USER_SDMA,
2406};
2407
2408/* mpu -> l3_main_1 */
2409static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2410 .master = &dra7xx_mpu_hwmod,
2411 .slave = &dra7xx_l3_main_1_hwmod,
2412 .clk = "l3_iclk_div",
2413 .user = OCP_USER_MPU,
2414};
2415
2416/* l3_main_1 -> l3_main_2 */
2417static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2418 .master = &dra7xx_l3_main_1_hwmod,
2419 .slave = &dra7xx_l3_main_2_hwmod,
2420 .clk = "l3_iclk_div",
2421 .user = OCP_USER_MPU,
2422};
2423
2424/* l4_cfg -> l3_main_2 */
2425static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2426 .master = &dra7xx_l4_cfg_hwmod,
2427 .slave = &dra7xx_l3_main_2_hwmod,
2428 .clk = "l3_iclk_div",
2429 .user = OCP_USER_MPU | OCP_USER_SDMA,
2430};
2431
2432/* l3_main_1 -> l4_cfg */
2433static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2434 .master = &dra7xx_l3_main_1_hwmod,
2435 .slave = &dra7xx_l4_cfg_hwmod,
2436 .clk = "l3_iclk_div",
2437 .user = OCP_USER_MPU | OCP_USER_SDMA,
2438};
2439
2440/* l3_main_1 -> l4_per1 */
2441static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2442 .master = &dra7xx_l3_main_1_hwmod,
2443 .slave = &dra7xx_l4_per1_hwmod,
2444 .clk = "l3_iclk_div",
2445 .user = OCP_USER_MPU | OCP_USER_SDMA,
2446};
2447
2448/* l3_main_1 -> l4_per2 */
2449static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2450 .master = &dra7xx_l3_main_1_hwmod,
2451 .slave = &dra7xx_l4_per2_hwmod,
2452 .clk = "l3_iclk_div",
2453 .user = OCP_USER_MPU | OCP_USER_SDMA,
2454};
2455
2456/* l3_main_1 -> l4_per3 */
2457static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2458 .master = &dra7xx_l3_main_1_hwmod,
2459 .slave = &dra7xx_l4_per3_hwmod,
2460 .clk = "l3_iclk_div",
2461 .user = OCP_USER_MPU | OCP_USER_SDMA,
2462};
2463
2464/* l3_main_1 -> l4_wkup */
2465static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2466 .master = &dra7xx_l3_main_1_hwmod,
2467 .slave = &dra7xx_l4_wkup_hwmod,
2468 .clk = "wkupaon_iclk_mux",
2469 .user = OCP_USER_MPU | OCP_USER_SDMA,
2470};
2471
2472/* l4_per2 -> atl */
2473static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2474 .master = &dra7xx_l4_per2_hwmod,
2475 .slave = &dra7xx_atl_hwmod,
2476 .clk = "l3_iclk_div",
2477 .user = OCP_USER_MPU | OCP_USER_SDMA,
2478};
2479
2480/* l3_main_1 -> bb2d */
2481static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2482 .master = &dra7xx_l3_main_1_hwmod,
2483 .slave = &dra7xx_bb2d_hwmod,
2484 .clk = "l3_iclk_div",
2485 .user = OCP_USER_MPU | OCP_USER_SDMA,
2486};
2487
2488/* l4_wkup -> counter_32k */
2489static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2490 .master = &dra7xx_l4_wkup_hwmod,
2491 .slave = &dra7xx_counter_32k_hwmod,
2492 .clk = "wkupaon_iclk_mux",
2493 .user = OCP_USER_MPU | OCP_USER_SDMA,
2494};
2495
2496/* l4_wkup -> ctrl_module_wkup */
2497static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2498 .master = &dra7xx_l4_wkup_hwmod,
2499 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2500 .clk = "wkupaon_iclk_mux",
2501 .user = OCP_USER_MPU | OCP_USER_SDMA,
2502};
2503
077c42f7
M		 2504static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2505 .master = &dra7xx_l4_per2_hwmod,
2506 .slave = &dra7xx_gmac_hwmod,
2507 .clk = "dpll_gmac_ck",
2508 .user = OCP_USER_MPU,
2509};
2510
2511static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2512 .master = &dra7xx_gmac_hwmod,
2513 .slave = &dra7xx_mdio_hwmod,
2514 .user = OCP_USER_MPU,
2515};
2516
90020c7b
A		 2517/* l4_wkup -> dcan1 */
2518static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2519 .master = &dra7xx_l4_wkup_hwmod,
2520 .slave = &dra7xx_dcan1_hwmod,
2521 .clk = "wkupaon_iclk_mux",
2522 .user = OCP_USER_MPU | OCP_USER_SDMA,
2523};
2524
2525/* l4_per2 -> dcan2 */
2526static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2527 .master = &dra7xx_l4_per2_hwmod,
2528 .slave = &dra7xx_dcan2_hwmod,
2529 .clk = "l3_iclk_div",
2530 .user = OCP_USER_MPU | OCP_USER_SDMA,
2531};
2532
2533static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2534 {
2535 .pa_start = 0x4a056000,
2536 .pa_end = 0x4a056fff,
2537 .flags = ADDR_TYPE_RT
2538 },
2539 { }
2540};
2541
2542/* l4_cfg -> dma_system */
2543static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2544 .master = &dra7xx_l4_cfg_hwmod,
2545 .slave = &dra7xx_dma_system_hwmod,
2546 .clk = "l3_iclk_div",
2547 .addr = dra7xx_dma_system_addrs,
2548 .user = OCP_USER_MPU | OCP_USER_SDMA,
2549};
2550
2551static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2552 {
2553 .name = "family",
2554 .pa_start = 0x58000000,
2555 .pa_end = 0x5800007f,
2556 .flags = ADDR_TYPE_RT
2557 },
2558};
2559
2560/* l3_main_1 -> dss */
2561static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2562 .master = &dra7xx_l3_main_1_hwmod,
2563 .slave = &dra7xx_dss_hwmod,
2564 .clk = "l3_iclk_div",
2565 .addr = dra7xx_dss_addrs,
2566 .user = OCP_USER_MPU | OCP_USER_SDMA,
2567};
2568
2569static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2570 {
2571 .name = "dispc",
2572 .pa_start = 0x58001000,
2573 .pa_end = 0x58001fff,
2574 .flags = ADDR_TYPE_RT
2575 },
2576};
2577
2578/* l3_main_1 -> dispc */
2579static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2580 .master = &dra7xx_l3_main_1_hwmod,
2581 .slave = &dra7xx_dss_dispc_hwmod,
2582 .clk = "l3_iclk_div",
2583 .addr = dra7xx_dss_dispc_addrs,
2584 .user = OCP_USER_MPU | OCP_USER_SDMA,
2585};
2586
2587static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2588 {
2589 .name = "hdmi_wp",
2590 .pa_start = 0x58040000,
2591 .pa_end = 0x580400ff,
2592 .flags = ADDR_TYPE_RT
2593 },
2594 { }
2595};
2596
2597/* l3_main_1 -> dispc */
2598static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2599 .master = &dra7xx_l3_main_1_hwmod,
2600 .slave = &dra7xx_dss_hdmi_hwmod,
2601 .clk = "l3_iclk_div",
2602 .addr = dra7xx_dss_hdmi_addrs,
2603 .user = OCP_USER_MPU | OCP_USER_SDMA,
2604};
2605
469689a4
PU		 2606/* l4_per2 -> mcasp3 */
2607static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
2608 .master = &dra7xx_l4_per2_hwmod,
2609 .slave = &dra7xx_mcasp3_hwmod,
2610 .clk = "l4_root_clk_div",
2611 .user = OCP_USER_MPU | OCP_USER_SDMA,
2612};
2613
2614/* l3_main_1 -> mcasp3 */
2615static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
2616 .master = &dra7xx_l3_main_1_hwmod,
2617 .slave = &dra7xx_mcasp3_hwmod,
2618 .clk = "l3_iclk_div",
2619 .user = OCP_USER_MPU | OCP_USER_SDMA,
2620};
2621
90020c7b
A		 2622/* l4_per1 -> elm */
2623static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2624 .master = &dra7xx_l4_per1_hwmod,
2625 .slave = &dra7xx_elm_hwmod,
2626 .clk = "l3_iclk_div",
90020c7b
A		 2627 .user = OCP_USER_MPU | OCP_USER_SDMA,
2628};
2629
2630/* l4_wkup -> gpio1 */
2631static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2632 .master = &dra7xx_l4_wkup_hwmod,
2633 .slave = &dra7xx_gpio1_hwmod,
2634 .clk = "wkupaon_iclk_mux",
2635 .user = OCP_USER_MPU | OCP_USER_SDMA,
2636};
2637
2638/* l4_per1 -> gpio2 */
2639static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2640 .master = &dra7xx_l4_per1_hwmod,
2641 .slave = &dra7xx_gpio2_hwmod,
2642 .clk = "l3_iclk_div",
2643 .user = OCP_USER_MPU | OCP_USER_SDMA,
2644};
2645
2646/* l4_per1 -> gpio3 */
2647static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2648 .master = &dra7xx_l4_per1_hwmod,
2649 .slave = &dra7xx_gpio3_hwmod,
2650 .clk = "l3_iclk_div",
2651 .user = OCP_USER_MPU | OCP_USER_SDMA,
2652};
2653
2654/* l4_per1 -> gpio4 */
2655static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2656 .master = &dra7xx_l4_per1_hwmod,
2657 .slave = &dra7xx_gpio4_hwmod,
2658 .clk = "l3_iclk_div",
2659 .user = OCP_USER_MPU | OCP_USER_SDMA,
2660};
2661
2662/* l4_per1 -> gpio5 */
2663static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2664 .master = &dra7xx_l4_per1_hwmod,
2665 .slave = &dra7xx_gpio5_hwmod,
2666 .clk = "l3_iclk_div",
2667 .user = OCP_USER_MPU | OCP_USER_SDMA,
2668};
2669
2670/* l4_per1 -> gpio6 */
2671static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2672 .master = &dra7xx_l4_per1_hwmod,
2673 .slave = &dra7xx_gpio6_hwmod,
2674 .clk = "l3_iclk_div",
2675 .user = OCP_USER_MPU | OCP_USER_SDMA,
2676};
2677
2678/* l4_per1 -> gpio7 */
2679static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2680 .master = &dra7xx_l4_per1_hwmod,
2681 .slave = &dra7xx_gpio7_hwmod,
2682 .clk = "l3_iclk_div",
2683 .user = OCP_USER_MPU | OCP_USER_SDMA,
2684};
2685
2686/* l4_per1 -> gpio8 */
2687static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2688 .master = &dra7xx_l4_per1_hwmod,
2689 .slave = &dra7xx_gpio8_hwmod,
2690 .clk = "l3_iclk_div",
2691 .user = OCP_USER_MPU | OCP_USER_SDMA,
2692};
2693
90020c7b
A		 2694/* l3_main_1 -> gpmc */
2695static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2696 .master = &dra7xx_l3_main_1_hwmod,
2697 .slave = &dra7xx_gpmc_hwmod,
2698 .clk = "l3_iclk_div",
90020c7b
A		 2699 .user = OCP_USER_MPU | OCP_USER_SDMA,
2700};
2701
2702static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2703 {
2704 .pa_start = 0x480b2000,
2705 .pa_end = 0x480b201f,
2706 .flags = ADDR_TYPE_RT
2707 },
2708 { }
2709};
2710
2711/* l4_per1 -> hdq1w */
2712static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2713 .master = &dra7xx_l4_per1_hwmod,
2714 .slave = &dra7xx_hdq1w_hwmod,
2715 .clk = "l3_iclk_div",
2716 .addr = dra7xx_hdq1w_addrs,
2717 .user = OCP_USER_MPU | OCP_USER_SDMA,
2718};
2719
2720/* l4_per1 -> i2c1 */
2721static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2722 .master = &dra7xx_l4_per1_hwmod,
2723 .slave = &dra7xx_i2c1_hwmod,
2724 .clk = "l3_iclk_div",
2725 .user = OCP_USER_MPU | OCP_USER_SDMA,
2726};
2727
2728/* l4_per1 -> i2c2 */
2729static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2730 .master = &dra7xx_l4_per1_hwmod,
2731 .slave = &dra7xx_i2c2_hwmod,
2732 .clk = "l3_iclk_div",
2733 .user = OCP_USER_MPU | OCP_USER_SDMA,
2734};
2735
2736/* l4_per1 -> i2c3 */
2737static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2738 .master = &dra7xx_l4_per1_hwmod,
2739 .slave = &dra7xx_i2c3_hwmod,
2740 .clk = "l3_iclk_div",
2741 .user = OCP_USER_MPU | OCP_USER_SDMA,
2742};
2743
2744/* l4_per1 -> i2c4 */
2745static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2746 .master = &dra7xx_l4_per1_hwmod,
2747 .slave = &dra7xx_i2c4_hwmod,
2748 .clk = "l3_iclk_div",
2749 .user = OCP_USER_MPU | OCP_USER_SDMA,
2750};
2751
2752/* l4_per1 -> i2c5 */
2753static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2754 .master = &dra7xx_l4_per1_hwmod,
2755 .slave = &dra7xx_i2c5_hwmod,
2756 .clk = "l3_iclk_div",
2757 .user = OCP_USER_MPU | OCP_USER_SDMA,
2758};
2759
067395d4
SA		 2760/* l4_cfg -> mailbox1 */
2761static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
2762 .master = &dra7xx_l4_cfg_hwmod,
2763 .slave = &dra7xx_mailbox1_hwmod,
2764 .clk = "l3_iclk_div",
2765 .user = OCP_USER_MPU | OCP_USER_SDMA,
2766};
2767
2768/* l4_per3 -> mailbox2 */
2769static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
2770 .master = &dra7xx_l4_per3_hwmod,
2771 .slave = &dra7xx_mailbox2_hwmod,
2772 .clk = "l3_iclk_div",
2773 .user = OCP_USER_MPU | OCP_USER_SDMA,
2774};
2775
2776/* l4_per3 -> mailbox3 */
2777static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
2778 .master = &dra7xx_l4_per3_hwmod,
2779 .slave = &dra7xx_mailbox3_hwmod,
2780 .clk = "l3_iclk_div",
2781 .user = OCP_USER_MPU | OCP_USER_SDMA,
2782};
2783
2784/* l4_per3 -> mailbox4 */
2785static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
2786 .master = &dra7xx_l4_per3_hwmod,
2787 .slave = &dra7xx_mailbox4_hwmod,
2788 .clk = "l3_iclk_div",
2789 .user = OCP_USER_MPU | OCP_USER_SDMA,
2790};
2791
2792/* l4_per3 -> mailbox5 */
2793static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
2794 .master = &dra7xx_l4_per3_hwmod,
2795 .slave = &dra7xx_mailbox5_hwmod,
2796 .clk = "l3_iclk_div",
2797 .user = OCP_USER_MPU | OCP_USER_SDMA,
2798};
2799
2800/* l4_per3 -> mailbox6 */
2801static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
2802 .master = &dra7xx_l4_per3_hwmod,
2803 .slave = &dra7xx_mailbox6_hwmod,
2804 .clk = "l3_iclk_div",
2805 .user = OCP_USER_MPU | OCP_USER_SDMA,
2806};
2807
2808/* l4_per3 -> mailbox7 */
2809static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
2810 .master = &dra7xx_l4_per3_hwmod,
2811 .slave = &dra7xx_mailbox7_hwmod,
2812 .clk = "l3_iclk_div",
2813 .user = OCP_USER_MPU | OCP_USER_SDMA,
2814};
2815
2816/* l4_per3 -> mailbox8 */
2817static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
2818 .master = &dra7xx_l4_per3_hwmod,
2819 .slave = &dra7xx_mailbox8_hwmod,
2820 .clk = "l3_iclk_div",
2821 .user = OCP_USER_MPU | OCP_USER_SDMA,
2822};
2823
2824/* l4_per3 -> mailbox9 */
2825static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
2826 .master = &dra7xx_l4_per3_hwmod,
2827 .slave = &dra7xx_mailbox9_hwmod,
2828 .clk = "l3_iclk_div",
2829 .user = OCP_USER_MPU | OCP_USER_SDMA,
2830};
2831
2832/* l4_per3 -> mailbox10 */
2833static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
2834 .master = &dra7xx_l4_per3_hwmod,
2835 .slave = &dra7xx_mailbox10_hwmod,
2836 .clk = "l3_iclk_div",
2837 .user = OCP_USER_MPU | OCP_USER_SDMA,
2838};
2839
2840/* l4_per3 -> mailbox11 */
2841static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
2842 .master = &dra7xx_l4_per3_hwmod,
2843 .slave = &dra7xx_mailbox11_hwmod,
2844 .clk = "l3_iclk_div",
2845 .user = OCP_USER_MPU | OCP_USER_SDMA,
2846};
2847
2848/* l4_per3 -> mailbox12 */
2849static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
2850 .master = &dra7xx_l4_per3_hwmod,
2851 .slave = &dra7xx_mailbox12_hwmod,
2852 .clk = "l3_iclk_div",
2853 .user = OCP_USER_MPU | OCP_USER_SDMA,
2854};
2855
2856/* l4_per3 -> mailbox13 */
2857static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
2858 .master = &dra7xx_l4_per3_hwmod,
2859 .slave = &dra7xx_mailbox13_hwmod,
2860 .clk = "l3_iclk_div",
2861 .user = OCP_USER_MPU | OCP_USER_SDMA,
2862};
2863
90020c7b
A		 2864/* l4_per1 -> mcspi1 */
2865static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2866 .master = &dra7xx_l4_per1_hwmod,
2867 .slave = &dra7xx_mcspi1_hwmod,
2868 .clk = "l3_iclk_div",
2869 .user = OCP_USER_MPU | OCP_USER_SDMA,
2870};
2871
2872/* l4_per1 -> mcspi2 */
2873static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2874 .master = &dra7xx_l4_per1_hwmod,
2875 .slave = &dra7xx_mcspi2_hwmod,
2876 .clk = "l3_iclk_div",
2877 .user = OCP_USER_MPU | OCP_USER_SDMA,
2878};
2879
2880/* l4_per1 -> mcspi3 */
2881static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2882 .master = &dra7xx_l4_per1_hwmod,
2883 .slave = &dra7xx_mcspi3_hwmod,
2884 .clk = "l3_iclk_div",
2885 .user = OCP_USER_MPU | OCP_USER_SDMA,
2886};
2887
2888/* l4_per1 -> mcspi4 */
2889static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2890 .master = &dra7xx_l4_per1_hwmod,
2891 .slave = &dra7xx_mcspi4_hwmod,
2892 .clk = "l3_iclk_div",
2893 .user = OCP_USER_MPU | OCP_USER_SDMA,
2894};
2895
2896/* l4_per1 -> mmc1 */
2897static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
2898 .master = &dra7xx_l4_per1_hwmod,
2899 .slave = &dra7xx_mmc1_hwmod,
2900 .clk = "l3_iclk_div",
2901 .user = OCP_USER_MPU | OCP_USER_SDMA,
2902};
2903
2904/* l4_per1 -> mmc2 */
2905static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
2906 .master = &dra7xx_l4_per1_hwmod,
2907 .slave = &dra7xx_mmc2_hwmod,
2908 .clk = "l3_iclk_div",
2909 .user = OCP_USER_MPU | OCP_USER_SDMA,
2910};
2911
2912/* l4_per1 -> mmc3 */
2913static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
2914 .master = &dra7xx_l4_per1_hwmod,
2915 .slave = &dra7xx_mmc3_hwmod,
2916 .clk = "l3_iclk_div",
2917 .user = OCP_USER_MPU | OCP_USER_SDMA,
2918};
2919
2920/* l4_per1 -> mmc4 */
2921static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
2922 .master = &dra7xx_l4_per1_hwmod,
2923 .slave = &dra7xx_mmc4_hwmod,
2924 .clk = "l3_iclk_div",
2925 .user = OCP_USER_MPU | OCP_USER_SDMA,
2926};
2927
2928/* l4_cfg -> mpu */
2929static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2930 .master = &dra7xx_l4_cfg_hwmod,
2931 .slave = &dra7xx_mpu_hwmod,
2932 .clk = "l3_iclk_div",
2933 .user = OCP_USER_MPU | OCP_USER_SDMA,
2934};
2935
90020c7b
A		 2936/* l4_cfg -> ocp2scp1 */
2937static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2938 .master = &dra7xx_l4_cfg_hwmod,
2939 .slave = &dra7xx_ocp2scp1_hwmod,
2940 .clk = "l4_root_clk_div",
90020c7b
A		 2941 .user = OCP_USER_MPU | OCP_USER_SDMA,
2942};
2943
df0d0f11
RQ		 2944/* l4_cfg -> ocp2scp3 */
2945static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
2946 .master = &dra7xx_l4_cfg_hwmod,
2947 .slave = &dra7xx_ocp2scp3_hwmod,
2948 .clk = "l4_root_clk_div",
2949 .user = OCP_USER_MPU | OCP_USER_SDMA,
2950};
2951
0717103e
KVA		 2952/* l3_main_1 -> pciess1 */
2953static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
8dd3eb71 2954 .master = &dra7xx_l3_main_1_hwmod,
0717103e 2955 .slave = &dra7xx_pciess1_hwmod,
8dd3eb71
KVA		 2956 .clk = "l3_iclk_div",
2957 .user = OCP_USER_MPU | OCP_USER_SDMA,
2958};
2959
0717103e
KVA		 2960/* l4_cfg -> pciess1 */
2961static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
8dd3eb71 2962 .master = &dra7xx_l4_cfg_hwmod,
0717103e 2963 .slave = &dra7xx_pciess1_hwmod,
8dd3eb71
KVA		 2964 .clk = "l4_root_clk_div",
2965 .user = OCP_USER_MPU | OCP_USER_SDMA,
2966};
2967
0717103e
KVA		 2968/* l3_main_1 -> pciess2 */
2969static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
8dd3eb71 2970 .master = &dra7xx_l3_main_1_hwmod,
0717103e 2971 .slave = &dra7xx_pciess2_hwmod,
8dd3eb71
KVA		 2972 .clk = "l3_iclk_div",
2973 .user = OCP_USER_MPU | OCP_USER_SDMA,
2974};
2975
0717103e
KVA		 2976/* l4_cfg -> pciess2 */
2977static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
70c18ef7 2978 .master = &dra7xx_l4_cfg_hwmod,
0717103e 2979 .slave = &dra7xx_pciess2_hwmod,
70c18ef7
KVA		 2980 .clk = "l4_root_clk_div",
2981 .user = OCP_USER_MPU | OCP_USER_SDMA,
2982};
2983
90020c7b
A		 2984static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2985 {
2986 .pa_start = 0x4b300000,
2987 .pa_end = 0x4b30007f,
2988 .flags = ADDR_TYPE_RT
2989 },
2990 { }
2991};
2992
2993/* l3_main_1 -> qspi */
2994static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2995 .master = &dra7xx_l3_main_1_hwmod,
2996 .slave = &dra7xx_qspi_hwmod,
2997 .clk = "l3_iclk_div",
2998 .addr = dra7xx_qspi_addrs,
2999 .user = OCP_USER_MPU | OCP_USER_SDMA,
3000};
3001
c913c8a1
LV		 3002/* l4_per3 -> rtcss */
3003static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
3004 .master = &dra7xx_l4_per3_hwmod,
3005 .slave = &dra7xx_rtcss_hwmod,
3006 .clk = "l4_root_clk_div",
3007 .user = OCP_USER_MPU | OCP_USER_SDMA,
3008};
3009
90020c7b
A		 3010static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
3011 {
3012 .name = "sysc",
3013 .pa_start = 0x4a141100,
3014 .pa_end = 0x4a141107,
3015 .flags = ADDR_TYPE_RT
3016 },
3017 { }
3018};
3019
3020/* l4_cfg -> sata */
3021static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
3022 .master = &dra7xx_l4_cfg_hwmod,
3023 .slave = &dra7xx_sata_hwmod,
3024 .clk = "l3_iclk_div",
3025 .addr = dra7xx_sata_addrs,
3026 .user = OCP_USER_MPU | OCP_USER_SDMA,
3027};
3028
3029static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
3030 {
3031 .pa_start = 0x4a0dd000,
3032 .pa_end = 0x4a0dd07f,
3033 .flags = ADDR_TYPE_RT
3034 },
3035 { }
3036};
3037
3038/* l4_cfg -> smartreflex_core */
3039static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3040 .master = &dra7xx_l4_cfg_hwmod,
3041 .slave = &dra7xx_smartreflex_core_hwmod,
3042 .clk = "l4_root_clk_div",
3043 .addr = dra7xx_smartreflex_core_addrs,
3044 .user = OCP_USER_MPU | OCP_USER_SDMA,
3045};
3046
3047static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
3048 {
3049 .pa_start = 0x4a0d9000,
3050 .pa_end = 0x4a0d907f,
3051 .flags = ADDR_TYPE_RT
3052 },
3053 { }
3054};
3055
3056/* l4_cfg -> smartreflex_mpu */
3057static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3058 .master = &dra7xx_l4_cfg_hwmod,
3059 .slave = &dra7xx_smartreflex_mpu_hwmod,
3060 .clk = "l4_root_clk_div",
3061 .addr = dra7xx_smartreflex_mpu_addrs,
3062 .user = OCP_USER_MPU | OCP_USER_SDMA,
3063};
3064
90020c7b
A		 3065/* l4_cfg -> spinlock */
3066static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3067 .master = &dra7xx_l4_cfg_hwmod,
3068 .slave = &dra7xx_spinlock_hwmod,
3069 .clk = "l3_iclk_div",
90020c7b
A		 3070 .user = OCP_USER_MPU | OCP_USER_SDMA,
3071};
3072
3073/* l4_wkup -> timer1 */
3074static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3075 .master = &dra7xx_l4_wkup_hwmod,
3076 .slave = &dra7xx_timer1_hwmod,
3077 .clk = "wkupaon_iclk_mux",
3078 .user = OCP_USER_MPU | OCP_USER_SDMA,
3079};
3080
3081/* l4_per1 -> timer2 */
3082static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3083 .master = &dra7xx_l4_per1_hwmod,
3084 .slave = &dra7xx_timer2_hwmod,
3085 .clk = "l3_iclk_div",
3086 .user = OCP_USER_MPU | OCP_USER_SDMA,
3087};
3088
3089/* l4_per1 -> timer3 */
3090static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3091 .master = &dra7xx_l4_per1_hwmod,
3092 .slave = &dra7xx_timer3_hwmod,
3093 .clk = "l3_iclk_div",
3094 .user = OCP_USER_MPU | OCP_USER_SDMA,
3095};
3096
3097/* l4_per1 -> timer4 */
3098static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3099 .master = &dra7xx_l4_per1_hwmod,
3100 .slave = &dra7xx_timer4_hwmod,
3101 .clk = "l3_iclk_div",
3102 .user = OCP_USER_MPU | OCP_USER_SDMA,
3103};
3104
3105/* l4_per3 -> timer5 */
3106static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3107 .master = &dra7xx_l4_per3_hwmod,
3108 .slave = &dra7xx_timer5_hwmod,
3109 .clk = "l3_iclk_div",
3110 .user = OCP_USER_MPU | OCP_USER_SDMA,
3111};
3112
3113/* l4_per3 -> timer6 */
3114static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3115 .master = &dra7xx_l4_per3_hwmod,
3116 .slave = &dra7xx_timer6_hwmod,
3117 .clk = "l3_iclk_div",
3118 .user = OCP_USER_MPU | OCP_USER_SDMA,
3119};
3120
3121/* l4_per3 -> timer7 */
3122static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3123 .master = &dra7xx_l4_per3_hwmod,
3124 .slave = &dra7xx_timer7_hwmod,
3125 .clk = "l3_iclk_div",
3126 .user = OCP_USER_MPU | OCP_USER_SDMA,
3127};
3128
3129/* l4_per3 -> timer8 */
3130static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3131 .master = &dra7xx_l4_per3_hwmod,
3132 .slave = &dra7xx_timer8_hwmod,
3133 .clk = "l3_iclk_div",
3134 .user = OCP_USER_MPU | OCP_USER_SDMA,
3135};
3136
3137/* l4_per1 -> timer9 */
3138static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3139 .master = &dra7xx_l4_per1_hwmod,
3140 .slave = &dra7xx_timer9_hwmod,
3141 .clk = "l3_iclk_div",
3142 .user = OCP_USER_MPU | OCP_USER_SDMA,
3143};
3144
3145/* l4_per1 -> timer10 */
3146static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3147 .master = &dra7xx_l4_per1_hwmod,
3148 .slave = &dra7xx_timer10_hwmod,
3149 .clk = "l3_iclk_div",
3150 .user = OCP_USER_MPU | OCP_USER_SDMA,
3151};
3152
3153/* l4_per1 -> timer11 */
3154static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3155 .master = &dra7xx_l4_per1_hwmod,
3156 .slave = &dra7xx_timer11_hwmod,
3157 .clk = "l3_iclk_div",
3158 .user = OCP_USER_MPU | OCP_USER_SDMA,
3159};
3160
1ac964f4
SA		 3161/* l4_per3 -> timer13 */
3162static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3163 .master = &dra7xx_l4_per3_hwmod,
3164 .slave = &dra7xx_timer13_hwmod,
3165 .clk = "l3_iclk_div",
3166 .user = OCP_USER_MPU | OCP_USER_SDMA,
3167};
3168
3169/* l4_per3 -> timer14 */
3170static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3171 .master = &dra7xx_l4_per3_hwmod,
3172 .slave = &dra7xx_timer14_hwmod,
3173 .clk = "l3_iclk_div",
3174 .user = OCP_USER_MPU | OCP_USER_SDMA,
3175};
3176
3177/* l4_per3 -> timer15 */
3178static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3179 .master = &dra7xx_l4_per3_hwmod,
3180 .slave = &dra7xx_timer15_hwmod,
3181 .clk = "l3_iclk_div",
3182 .user = OCP_USER_MPU | OCP_USER_SDMA,
3183};
3184
3185/* l4_per3 -> timer16 */
3186static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3187 .master = &dra7xx_l4_per3_hwmod,
3188 .slave = &dra7xx_timer16_hwmod,
3189 .clk = "l3_iclk_div",
3190 .user = OCP_USER_MPU | OCP_USER_SDMA,
3191};
3192
90020c7b
A		 3193/* l4_per1 -> uart1 */
3194static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3195 .master = &dra7xx_l4_per1_hwmod,
3196 .slave = &dra7xx_uart1_hwmod,
3197 .clk = "l3_iclk_div",
3198 .user = OCP_USER_MPU | OCP_USER_SDMA,
3199};
3200
3201/* l4_per1 -> uart2 */
3202static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3203 .master = &dra7xx_l4_per1_hwmod,
3204 .slave = &dra7xx_uart2_hwmod,
3205 .clk = "l3_iclk_div",
3206 .user = OCP_USER_MPU | OCP_USER_SDMA,
3207};
3208
3209/* l4_per1 -> uart3 */
3210static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3211 .master = &dra7xx_l4_per1_hwmod,
3212 .slave = &dra7xx_uart3_hwmod,
3213 .clk = "l3_iclk_div",
3214 .user = OCP_USER_MPU | OCP_USER_SDMA,
3215};
3216
3217/* l4_per1 -> uart4 */
3218static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3219 .master = &dra7xx_l4_per1_hwmod,
3220 .slave = &dra7xx_uart4_hwmod,
3221 .clk = "l3_iclk_div",
3222 .user = OCP_USER_MPU | OCP_USER_SDMA,
3223};
3224
3225/* l4_per1 -> uart5 */
3226static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3227 .master = &dra7xx_l4_per1_hwmod,
3228 .slave = &dra7xx_uart5_hwmod,
3229 .clk = "l3_iclk_div",
3230 .user = OCP_USER_MPU | OCP_USER_SDMA,
3231};
3232
3233/* l4_per1 -> uart6 */
3234static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3235 .master = &dra7xx_l4_per1_hwmod,
3236 .slave = &dra7xx_uart6_hwmod,
3237 .clk = "l3_iclk_div",
3238 .user = OCP_USER_MPU | OCP_USER_SDMA,
3239};
3240
33acc9ff
A		 3241/* l4_per2 -> uart7 */
3242static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3243 .master = &dra7xx_l4_per2_hwmod,
3244 .slave = &dra7xx_uart7_hwmod,
3245 .clk = "l3_iclk_div",
3246 .user = OCP_USER_MPU | OCP_USER_SDMA,
3247};
3248
3249/* l4_per2 -> uart8 */
3250static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3251 .master = &dra7xx_l4_per2_hwmod,
3252 .slave = &dra7xx_uart8_hwmod,
3253 .clk = "l3_iclk_div",
3254 .user = OCP_USER_MPU | OCP_USER_SDMA,
3255};
3256
3257/* l4_per2 -> uart9 */
3258static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3259 .master = &dra7xx_l4_per2_hwmod,
3260 .slave = &dra7xx_uart9_hwmod,
3261 .clk = "l3_iclk_div",
3262 .user = OCP_USER_MPU | OCP_USER_SDMA,
3263};
3264
3265/* l4_wkup -> uart10 */
3266static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3267 .master = &dra7xx_l4_wkup_hwmod,
3268 .slave = &dra7xx_uart10_hwmod,
3269 .clk = "wkupaon_iclk_mux",
3270 .user = OCP_USER_MPU | OCP_USER_SDMA,
3271};
3272
90020c7b
A		 3273/* l4_per3 -> usb_otg_ss1 */
3274static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3275 .master = &dra7xx_l4_per3_hwmod,
3276 .slave = &dra7xx_usb_otg_ss1_hwmod,
3277 .clk = "dpll_core_h13x2_ck",
3278 .user = OCP_USER_MPU | OCP_USER_SDMA,
3279};
3280
3281/* l4_per3 -> usb_otg_ss2 */
3282static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3283 .master = &dra7xx_l4_per3_hwmod,
3284 .slave = &dra7xx_usb_otg_ss2_hwmod,
3285 .clk = "dpll_core_h13x2_ck",
3286 .user = OCP_USER_MPU | OCP_USER_SDMA,
3287};
3288
3289/* l4_per3 -> usb_otg_ss3 */
3290static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3291 .master = &dra7xx_l4_per3_hwmod,
3292 .slave = &dra7xx_usb_otg_ss3_hwmod,
3293 .clk = "dpll_core_h13x2_ck",
3294 .user = OCP_USER_MPU | OCP_USER_SDMA,
3295};
3296
3297/* l4_per3 -> usb_otg_ss4 */
3298static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3299 .master = &dra7xx_l4_per3_hwmod,
3300 .slave = &dra7xx_usb_otg_ss4_hwmod,
3301 .clk = "dpll_core_h13x2_ck",
3302 .user = OCP_USER_MPU | OCP_USER_SDMA,
3303};
3304
3305/* l3_main_1 -> vcp1 */
3306static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3307 .master = &dra7xx_l3_main_1_hwmod,
3308 .slave = &dra7xx_vcp1_hwmod,
3309 .clk = "l3_iclk_div",
3310 .user = OCP_USER_MPU | OCP_USER_SDMA,
3311};
3312
3313/* l4_per2 -> vcp1 */
3314static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3315 .master = &dra7xx_l4_per2_hwmod,
3316 .slave = &dra7xx_vcp1_hwmod,
3317 .clk = "l3_iclk_div",
3318 .user = OCP_USER_MPU | OCP_USER_SDMA,
3319};
3320
3321/* l3_main_1 -> vcp2 */
3322static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3323 .master = &dra7xx_l3_main_1_hwmod,
3324 .slave = &dra7xx_vcp2_hwmod,
3325 .clk = "l3_iclk_div",
3326 .user = OCP_USER_MPU | OCP_USER_SDMA,
3327};
3328
3329/* l4_per2 -> vcp2 */
3330static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3331 .master = &dra7xx_l4_per2_hwmod,
3332 .slave = &dra7xx_vcp2_hwmod,
3333 .clk = "l3_iclk_div",
3334 .user = OCP_USER_MPU | OCP_USER_SDMA,
3335};
3336
3337/* l4_wkup -> wd_timer2 */
3338static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3339 .master = &dra7xx_l4_wkup_hwmod,
3340 .slave = &dra7xx_wd_timer2_hwmod,
3341 .clk = "wkupaon_iclk_mux",
3342 .user = OCP_USER_MPU | OCP_USER_SDMA,
3343};
3344
3345static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
42121688 3346 &dra7xx_l3_main_1__dmm,
90020c7b
A		 3347 &dra7xx_l3_main_2__l3_instr,
3348 &dra7xx_l4_cfg__l3_main_1,
3349 &dra7xx_mpu__l3_main_1,
3350 &dra7xx_l3_main_1__l3_main_2,
3351 &dra7xx_l4_cfg__l3_main_2,
3352 &dra7xx_l3_main_1__l4_cfg,
3353 &dra7xx_l3_main_1__l4_per1,
3354 &dra7xx_l3_main_1__l4_per2,
3355 &dra7xx_l3_main_1__l4_per3,
3356 &dra7xx_l3_main_1__l4_wkup,
3357 &dra7xx_l4_per2__atl,
3358 &dra7xx_l3_main_1__bb2d,
3359 &dra7xx_l4_wkup__counter_32k,
3360 &dra7xx_l4_wkup__ctrl_module_wkup,
3361 &dra7xx_l4_wkup__dcan1,
3362 &dra7xx_l4_per2__dcan2,
077c42f7 3363 &dra7xx_l4_per2__cpgmac0,
469689a4
PU		 3364 &dra7xx_l4_per2__mcasp3,
3365 &dra7xx_l3_main_1__mcasp3,
077c42f7 3366 &dra7xx_gmac__mdio,
90020c7b
A		 3367 &dra7xx_l4_cfg__dma_system,
3368 &dra7xx_l3_main_1__dss,
3369 &dra7xx_l3_main_1__dispc,
3370 &dra7xx_l3_main_1__hdmi,
3371 &dra7xx_l4_per1__elm,
3372 &dra7xx_l4_wkup__gpio1,
3373 &dra7xx_l4_per1__gpio2,
3374 &dra7xx_l4_per1__gpio3,
3375 &dra7xx_l4_per1__gpio4,
3376 &dra7xx_l4_per1__gpio5,
3377 &dra7xx_l4_per1__gpio6,
3378 &dra7xx_l4_per1__gpio7,
3379 &dra7xx_l4_per1__gpio8,
3380 &dra7xx_l3_main_1__gpmc,
3381 &dra7xx_l4_per1__hdq1w,
3382 &dra7xx_l4_per1__i2c1,
3383 &dra7xx_l4_per1__i2c2,
3384 &dra7xx_l4_per1__i2c3,
3385 &dra7xx_l4_per1__i2c4,
3386 &dra7xx_l4_per1__i2c5,
067395d4
SA		 3387 &dra7xx_l4_cfg__mailbox1,
3388 &dra7xx_l4_per3__mailbox2,
3389 &dra7xx_l4_per3__mailbox3,
3390 &dra7xx_l4_per3__mailbox4,
3391 &dra7xx_l4_per3__mailbox5,
3392 &dra7xx_l4_per3__mailbox6,
3393 &dra7xx_l4_per3__mailbox7,
3394 &dra7xx_l4_per3__mailbox8,
3395 &dra7xx_l4_per3__mailbox9,
3396 &dra7xx_l4_per3__mailbox10,
3397 &dra7xx_l4_per3__mailbox11,
3398 &dra7xx_l4_per3__mailbox12,
3399 &dra7xx_l4_per3__mailbox13,
90020c7b
A		 3400 &dra7xx_l4_per1__mcspi1,
3401 &dra7xx_l4_per1__mcspi2,
3402 &dra7xx_l4_per1__mcspi3,
3403 &dra7xx_l4_per1__mcspi4,
3404 &dra7xx_l4_per1__mmc1,
3405 &dra7xx_l4_per1__mmc2,
3406 &dra7xx_l4_per1__mmc3,
3407 &dra7xx_l4_per1__mmc4,
3408 &dra7xx_l4_cfg__mpu,
3409 &dra7xx_l4_cfg__ocp2scp1,
df0d0f11 3410 &dra7xx_l4_cfg__ocp2scp3,
0717103e
KVA		 3411 &dra7xx_l3_main_1__pciess1,
3412 &dra7xx_l4_cfg__pciess1,
3413 &dra7xx_l3_main_1__pciess2,
3414 &dra7xx_l4_cfg__pciess2,
90020c7b 3415 &dra7xx_l3_main_1__qspi,
c913c8a1 3416 &dra7xx_l4_per3__rtcss,
90020c7b
A		 3417 &dra7xx_l4_cfg__sata,
3418 &dra7xx_l4_cfg__smartreflex_core,
3419 &dra7xx_l4_cfg__smartreflex_mpu,
3420 &dra7xx_l4_cfg__spinlock,
3421 &dra7xx_l4_wkup__timer1,
3422 &dra7xx_l4_per1__timer2,
3423 &dra7xx_l4_per1__timer3,
3424 &dra7xx_l4_per1__timer4,
3425 &dra7xx_l4_per3__timer5,
3426 &dra7xx_l4_per3__timer6,
3427 &dra7xx_l4_per3__timer7,
3428 &dra7xx_l4_per3__timer8,
3429 &dra7xx_l4_per1__timer9,
3430 &dra7xx_l4_per1__timer10,
3431 &dra7xx_l4_per1__timer11,
1ac964f4
SA		 3432 &dra7xx_l4_per3__timer13,
3433 &dra7xx_l4_per3__timer14,
3434 &dra7xx_l4_per3__timer15,
3435 &dra7xx_l4_per3__timer16,
90020c7b
A		 3436 &dra7xx_l4_per1__uart1,
3437 &dra7xx_l4_per1__uart2,
3438 &dra7xx_l4_per1__uart3,
3439 &dra7xx_l4_per1__uart4,
3440 &dra7xx_l4_per1__uart5,
3441 &dra7xx_l4_per1__uart6,
33acc9ff
A		 3442 &dra7xx_l4_per2__uart7,
3443 &dra7xx_l4_per2__uart8,
3444 &dra7xx_l4_per2__uart9,
3445 &dra7xx_l4_wkup__uart10,
90020c7b
A		 3446 &dra7xx_l4_per3__usb_otg_ss1,
3447 &dra7xx_l4_per3__usb_otg_ss2,
3448 &dra7xx_l4_per3__usb_otg_ss3,
90020c7b
A		 3449 &dra7xx_l3_main_1__vcp1,
3450 &dra7xx_l4_per2__vcp1,
3451 &dra7xx_l3_main_1__vcp2,
3452 &dra7xx_l4_per2__vcp2,
3453 &dra7xx_l4_wkup__wd_timer2,
3454 NULL,
3455};
3456
f7f7a29b
RN		 3457static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3458 &dra7xx_l4_per3__usb_otg_ss4,
3459 NULL,
3460};
3461
3462static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3463 NULL,
3464};
3465
90020c7b
A		 3466int __init dra7xx_hwmod_init(void)
3467{
f7f7a29b
RN		 3468 int ret;
3469
90020c7b 3470 omap_hwmod_init();
f7f7a29b
RN		 3471 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3472
3473 if (!ret && soc_is_dra74x())
3474 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3475 else if (!ret && soc_is_dra72x())
3476 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
3477
3478 return ret;
90020c7b 3479}
Linux kernel - Deliverables
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