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arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_7xx_data.c
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90020c7b
A		 1/*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/io.h>
21#include <linux/platform_data/gpio-omap.h>
22#include <linux/power/smartreflex.h>
23#include <linux/i2c-omap.h>
24
25#include <linux/omap-dma.h>
26#include <linux/platform_data/spi-omap2-mcspi.h>
27#include <linux/platform_data/asoc-ti-mcbsp.h>
28#include <plat/dmtimer.h>
29
30#include "omap_hwmod.h"
31#include "omap_hwmod_common_data.h"
32#include "cm1_7xx.h"
33#include "cm2_7xx.h"
34#include "prm7xx.h"
35#include "i2c.h"
36#include "mmc.h"
37#include "wd_timer.h"
38
39/* Base offset for all DRA7XX interrupts external to MPUSS */
40#define DRA7XX_IRQ_GIC_START 32
41
42/* Base offset for all DRA7XX dma requests */
43#define DRA7XX_DMA_REQ_START 1
44
45
46/*
47 * IP blocks
48 */
49
50/*
51 * 'l3' class
52 * instance(s): l3_instr, l3_main_1, l3_main_2
53 */
54static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
55 .name = "l3",
56};
57
58/* l3_instr */
59static struct omap_hwmod dra7xx_l3_instr_hwmod = {
60 .name = "l3_instr",
61 .class = &dra7xx_l3_hwmod_class,
62 .clkdm_name = "l3instr_clkdm",
63 .prcm = {
64 .omap4 = {
65 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
66 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
67 .modulemode = MODULEMODE_HWCTRL,
68 },
69 },
70};
71
72/* l3_main_1 */
73static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
74 .name = "l3_main_1",
75 .class = &dra7xx_l3_hwmod_class,
76 .clkdm_name = "l3main1_clkdm",
77 .prcm = {
78 .omap4 = {
79 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
80 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
81 },
82 },
83};
84
85/* l3_main_2 */
86static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
87 .name = "l3_main_2",
88 .class = &dra7xx_l3_hwmod_class,
89 .clkdm_name = "l3instr_clkdm",
90 .prcm = {
91 .omap4 = {
92 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
93 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
94 .modulemode = MODULEMODE_HWCTRL,
95 },
96 },
97};
98
99/*
100 * 'l4' class
101 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
102 */
103static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
104 .name = "l4",
105};
106
107/* l4_cfg */
108static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
109 .name = "l4_cfg",
110 .class = &dra7xx_l4_hwmod_class,
111 .clkdm_name = "l4cfg_clkdm",
112 .prcm = {
113 .omap4 = {
114 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
115 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
116 },
117 },
118};
119
120/* l4_per1 */
121static struct omap_hwmod dra7xx_l4_per1_hwmod = {
122 .name = "l4_per1",
123 .class = &dra7xx_l4_hwmod_class,
124 .clkdm_name = "l4per_clkdm",
125 .prcm = {
126 .omap4 = {
127 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
128 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
129 },
130 },
131};
132
133/* l4_per2 */
134static struct omap_hwmod dra7xx_l4_per2_hwmod = {
135 .name = "l4_per2",
136 .class = &dra7xx_l4_hwmod_class,
137 .clkdm_name = "l4per2_clkdm",
138 .prcm = {
139 .omap4 = {
140 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
141 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
142 },
143 },
144};
145
146/* l4_per3 */
147static struct omap_hwmod dra7xx_l4_per3_hwmod = {
148 .name = "l4_per3",
149 .class = &dra7xx_l4_hwmod_class,
150 .clkdm_name = "l4per3_clkdm",
151 .prcm = {
152 .omap4 = {
153 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
154 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
155 },
156 },
157};
158
159/* l4_wkup */
160static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
161 .name = "l4_wkup",
162 .class = &dra7xx_l4_hwmod_class,
163 .clkdm_name = "wkupaon_clkdm",
164 .prcm = {
165 .omap4 = {
166 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
167 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
168 },
169 },
170};
171
172/*
173 * 'atl' class
174 *
175 */
176
177static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
178 .name = "atl",
179};
180
181/* atl */
182static struct omap_hwmod dra7xx_atl_hwmod = {
183 .name = "atl",
184 .class = &dra7xx_atl_hwmod_class,
185 .clkdm_name = "atl_clkdm",
186 .main_clk = "atl_gfclk_mux",
187 .prcm = {
188 .omap4 = {
189 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
190 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
191 .modulemode = MODULEMODE_SWCTRL,
192 },
193 },
194};
195
196/*
197 * 'bb2d' class
198 *
199 */
200
201static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
202 .name = "bb2d",
203};
204
205/* bb2d */
206static struct omap_hwmod dra7xx_bb2d_hwmod = {
207 .name = "bb2d",
208 .class = &dra7xx_bb2d_hwmod_class,
209 .clkdm_name = "dss_clkdm",
210 .main_clk = "dpll_core_h24x2_ck",
211 .prcm = {
212 .omap4 = {
213 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
214 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
215 .modulemode = MODULEMODE_SWCTRL,
216 },
217 },
218};
219
220/*
221 * 'counter' class
222 *
223 */
224
225static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
226 .rev_offs = 0x0000,
227 .sysc_offs = 0x0010,
228 .sysc_flags = SYSC_HAS_SIDLEMODE,
229 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
230 SIDLE_SMART_WKUP),
231 .sysc_fields = &omap_hwmod_sysc_type1,
232};
233
234static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
235 .name = "counter",
236 .sysc = &dra7xx_counter_sysc,
237};
238
239/* counter_32k */
240static struct omap_hwmod dra7xx_counter_32k_hwmod = {
241 .name = "counter_32k",
242 .class = &dra7xx_counter_hwmod_class,
243 .clkdm_name = "wkupaon_clkdm",
244 .flags = HWMOD_SWSUP_SIDLE,
245 .main_clk = "wkupaon_iclk_mux",
246 .prcm = {
247 .omap4 = {
248 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
249 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
250 },
251 },
252};
253
254/*
255 * 'ctrl_module' class
256 *
257 */
258
259static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
260 .name = "ctrl_module",
261};
262
263/* ctrl_module_wkup */
264static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
265 .name = "ctrl_module_wkup",
266 .class = &dra7xx_ctrl_module_hwmod_class,
267 .clkdm_name = "wkupaon_clkdm",
268 .prcm = {
269 .omap4 = {
270 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
271 },
272 },
273};
274
275/*
276 * 'dcan' class
277 *
278 */
279
280static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
281 .name = "dcan",
282};
283
284/* dcan1 */
285static struct omap_hwmod dra7xx_dcan1_hwmod = {
286 .name = "dcan1",
287 .class = &dra7xx_dcan_hwmod_class,
288 .clkdm_name = "wkupaon_clkdm",
289 .main_clk = "dcan1_sys_clk_mux",
290 .prcm = {
291 .omap4 = {
292 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
293 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
294 .modulemode = MODULEMODE_SWCTRL,
295 },
296 },
297};
298
299/* dcan2 */
300static struct omap_hwmod dra7xx_dcan2_hwmod = {
301 .name = "dcan2",
302 .class = &dra7xx_dcan_hwmod_class,
303 .clkdm_name = "l4per2_clkdm",
304 .main_clk = "sys_clkin1",
305 .prcm = {
306 .omap4 = {
307 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
308 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
309 .modulemode = MODULEMODE_SWCTRL,
310 },
311 },
312};
313
314/*
315 * 'dma' class
316 *
317 */
318
319static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
320 .rev_offs = 0x0000,
321 .sysc_offs = 0x002c,
322 .syss_offs = 0x0028,
323 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
324 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
325 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
326 SYSS_HAS_RESET_STATUS),
327 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
328 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
329 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
330 .sysc_fields = &omap_hwmod_sysc_type1,
331};
332
333static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
334 .name = "dma",
335 .sysc = &dra7xx_dma_sysc,
336};
337
338/* dma dev_attr */
339static struct omap_dma_dev_attr dma_dev_attr = {
340 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
341 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
342 .lch_count = 32,
343};
344
345/* dma_system */
346static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = {
347 { .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START },
348 { .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START },
349 { .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START },
350 { .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START },
351 { .irq = -1 }
352};
353
354static struct omap_hwmod dra7xx_dma_system_hwmod = {
355 .name = "dma_system",
356 .class = &dra7xx_dma_hwmod_class,
357 .clkdm_name = "dma_clkdm",
358 .mpu_irqs = dra7xx_dma_system_irqs,
359 .main_clk = "l3_iclk_div",
360 .prcm = {
361 .omap4 = {
362 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
363 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
364 },
365 },
366 .dev_attr = &dma_dev_attr,
367};
368
369/*
370 * 'dss' class
371 *
372 */
373
374static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
375 .rev_offs = 0x0000,
376 .syss_offs = 0x0014,
377 .sysc_flags = SYSS_HAS_RESET_STATUS,
378};
379
380static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
381 .name = "dss",
382 .sysc = &dra7xx_dss_sysc,
383 .reset = omap_dss_reset,
384};
385
386/* dss */
387static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
388 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
389 { .dma_req = -1 }
390};
391
392static struct omap_hwmod_opt_clk dss_opt_clks[] = {
393 { .role = "dss_clk", .clk = "dss_dss_clk" },
394 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
395 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
396 { .role = "video2_clk", .clk = "dss_video2_clk" },
397 { .role = "video1_clk", .clk = "dss_video1_clk" },
398 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
399};
400
401static struct omap_hwmod dra7xx_dss_hwmod = {
402 .name = "dss_core",
403 .class = &dra7xx_dss_hwmod_class,
404 .clkdm_name = "dss_clkdm",
405 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
406 .sdma_reqs = dra7xx_dss_sdma_reqs,
407 .main_clk = "dss_dss_clk",
408 .prcm = {
409 .omap4 = {
410 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
411 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
412 .modulemode = MODULEMODE_SWCTRL,
413 },
414 },
415 .opt_clks = dss_opt_clks,
416 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
417};
418
419/*
420 * 'dispc' class
421 * display controller
422 */
423
424static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
425 .rev_offs = 0x0000,
426 .sysc_offs = 0x0010,
427 .syss_offs = 0x0014,
428 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
429 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
430 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
431 SYSS_HAS_RESET_STATUS),
432 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
433 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
434 .sysc_fields = &omap_hwmod_sysc_type1,
435};
436
437static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
438 .name = "dispc",
439 .sysc = &dra7xx_dispc_sysc,
440};
441
442/* dss_dispc */
443/* dss_dispc dev_attr */
444static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
445 .has_framedonetv_irq = 1,
446 .manager_count = 4,
447};
448
449static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
450 .name = "dss_dispc",
451 .class = &dra7xx_dispc_hwmod_class,
452 .clkdm_name = "dss_clkdm",
453 .main_clk = "dss_dss_clk",
454 .prcm = {
455 .omap4 = {
456 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
457 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
458 },
459 },
460 .dev_attr = &dss_dispc_dev_attr,
461};
462
463/*
464 * 'hdmi' class
465 * hdmi controller
466 */
467
468static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
469 .rev_offs = 0x0000,
470 .sysc_offs = 0x0010,
471 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
472 SYSC_HAS_SOFTRESET),
473 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
474 SIDLE_SMART_WKUP),
475 .sysc_fields = &omap_hwmod_sysc_type2,
476};
477
478static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
479 .name = "hdmi",
480 .sysc = &dra7xx_hdmi_sysc,
481};
482
483/* dss_hdmi */
484
485static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
486 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
487};
488
489static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
490 .name = "dss_hdmi",
491 .class = &dra7xx_hdmi_hwmod_class,
492 .clkdm_name = "dss_clkdm",
493 .main_clk = "dss_48mhz_clk",
494 .prcm = {
495 .omap4 = {
496 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
497 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
498 },
499 },
500 .opt_clks = dss_hdmi_opt_clks,
501 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
502};
503
504/*
505 * 'elm' class
506 *
507 */
508
509static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
510 .rev_offs = 0x0000,
511 .sysc_offs = 0x0010,
512 .syss_offs = 0x0014,
513 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
514 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
515 SYSS_HAS_RESET_STATUS),
516 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
517 SIDLE_SMART_WKUP),
518 .sysc_fields = &omap_hwmod_sysc_type1,
519};
520
521static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
522 .name = "elm",
523 .sysc = &dra7xx_elm_sysc,
524};
525
526/* elm */
527
528static struct omap_hwmod dra7xx_elm_hwmod = {
529 .name = "elm",
530 .class = &dra7xx_elm_hwmod_class,
531 .clkdm_name = "l4per_clkdm",
532 .main_clk = "l3_iclk_div",
533 .prcm = {
534 .omap4 = {
535 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
536 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
537 },
538 },
539};
540
541/*
542 * 'gpio' class
543 *
544 */
545
546static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
547 .rev_offs = 0x0000,
548 .sysc_offs = 0x0010,
549 .syss_offs = 0x0114,
550 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
551 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
552 SYSS_HAS_RESET_STATUS),
553 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
554 SIDLE_SMART_WKUP),
555 .sysc_fields = &omap_hwmod_sysc_type1,
556};
557
558static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
559 .name = "gpio",
560 .sysc = &dra7xx_gpio_sysc,
561 .rev = 2,
562};
563
564/* gpio dev_attr */
565static struct omap_gpio_dev_attr gpio_dev_attr = {
566 .bank_width = 32,
567 .dbck_flag = true,
568};
569
570/* gpio1 */
571static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
572 { .role = "dbclk", .clk = "gpio1_dbclk" },
573};
574
575static struct omap_hwmod dra7xx_gpio1_hwmod = {
576 .name = "gpio1",
577 .class = &dra7xx_gpio_hwmod_class,
578 .clkdm_name = "wkupaon_clkdm",
579 .main_clk = "wkupaon_iclk_mux",
580 .prcm = {
581 .omap4 = {
582 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
583 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
584 .modulemode = MODULEMODE_HWCTRL,
585 },
586 },
587 .opt_clks = gpio1_opt_clks,
588 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
589 .dev_attr = &gpio_dev_attr,
590};
591
592/* gpio2 */
593static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
594 { .role = "dbclk", .clk = "gpio2_dbclk" },
595};
596
597static struct omap_hwmod dra7xx_gpio2_hwmod = {
598 .name = "gpio2",
599 .class = &dra7xx_gpio_hwmod_class,
600 .clkdm_name = "l4per_clkdm",
601 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
602 .main_clk = "l3_iclk_div",
603 .prcm = {
604 .omap4 = {
605 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
606 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
607 .modulemode = MODULEMODE_HWCTRL,
608 },
609 },
610 .opt_clks = gpio2_opt_clks,
611 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
612 .dev_attr = &gpio_dev_attr,
613};
614
615/* gpio3 */
616static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
617 { .role = "dbclk", .clk = "gpio3_dbclk" },
618};
619
620static struct omap_hwmod dra7xx_gpio3_hwmod = {
621 .name = "gpio3",
622 .class = &dra7xx_gpio_hwmod_class,
623 .clkdm_name = "l4per_clkdm",
624 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
625 .main_clk = "l3_iclk_div",
626 .prcm = {
627 .omap4 = {
628 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
629 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
630 .modulemode = MODULEMODE_HWCTRL,
631 },
632 },
633 .opt_clks = gpio3_opt_clks,
634 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
635 .dev_attr = &gpio_dev_attr,
636};
637
638/* gpio4 */
639static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
640 { .role = "dbclk", .clk = "gpio4_dbclk" },
641};
642
643static struct omap_hwmod dra7xx_gpio4_hwmod = {
644 .name = "gpio4",
645 .class = &dra7xx_gpio_hwmod_class,
646 .clkdm_name = "l4per_clkdm",
647 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
648 .main_clk = "l3_iclk_div",
649 .prcm = {
650 .omap4 = {
651 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
652 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
653 .modulemode = MODULEMODE_HWCTRL,
654 },
655 },
656 .opt_clks = gpio4_opt_clks,
657 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
658 .dev_attr = &gpio_dev_attr,
659};
660
661/* gpio5 */
662static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
663 { .role = "dbclk", .clk = "gpio5_dbclk" },
664};
665
666static struct omap_hwmod dra7xx_gpio5_hwmod = {
667 .name = "gpio5",
668 .class = &dra7xx_gpio_hwmod_class,
669 .clkdm_name = "l4per_clkdm",
670 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
671 .main_clk = "l3_iclk_div",
672 .prcm = {
673 .omap4 = {
674 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
675 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
676 .modulemode = MODULEMODE_HWCTRL,
677 },
678 },
679 .opt_clks = gpio5_opt_clks,
680 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
681 .dev_attr = &gpio_dev_attr,
682};
683
684/* gpio6 */
685static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
686 { .role = "dbclk", .clk = "gpio6_dbclk" },
687};
688
689static struct omap_hwmod dra7xx_gpio6_hwmod = {
690 .name = "gpio6",
691 .class = &dra7xx_gpio_hwmod_class,
692 .clkdm_name = "l4per_clkdm",
693 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
694 .main_clk = "l3_iclk_div",
695 .prcm = {
696 .omap4 = {
697 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
698 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
699 .modulemode = MODULEMODE_HWCTRL,
700 },
701 },
702 .opt_clks = gpio6_opt_clks,
703 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
704 .dev_attr = &gpio_dev_attr,
705};
706
707/* gpio7 */
708static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
709 { .role = "dbclk", .clk = "gpio7_dbclk" },
710};
711
712static struct omap_hwmod dra7xx_gpio7_hwmod = {
713 .name = "gpio7",
714 .class = &dra7xx_gpio_hwmod_class,
715 .clkdm_name = "l4per_clkdm",
716 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
717 .main_clk = "l3_iclk_div",
718 .prcm = {
719 .omap4 = {
720 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
721 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
722 .modulemode = MODULEMODE_HWCTRL,
723 },
724 },
725 .opt_clks = gpio7_opt_clks,
726 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
727 .dev_attr = &gpio_dev_attr,
728};
729
730/* gpio8 */
731static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
732 { .role = "dbclk", .clk = "gpio8_dbclk" },
733};
734
735static struct omap_hwmod dra7xx_gpio8_hwmod = {
736 .name = "gpio8",
737 .class = &dra7xx_gpio_hwmod_class,
738 .clkdm_name = "l4per_clkdm",
739 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
740 .main_clk = "l3_iclk_div",
741 .prcm = {
742 .omap4 = {
743 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
744 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
745 .modulemode = MODULEMODE_HWCTRL,
746 },
747 },
748 .opt_clks = gpio8_opt_clks,
749 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
750 .dev_attr = &gpio_dev_attr,
751};
752
753/*
754 * 'gpmc' class
755 *
756 */
757
758static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
759 .rev_offs = 0x0000,
760 .sysc_offs = 0x0010,
761 .syss_offs = 0x0014,
762 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
763 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
764 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
765 SIDLE_SMART_WKUP),
766 .sysc_fields = &omap_hwmod_sysc_type1,
767};
768
769static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
770 .name = "gpmc",
771 .sysc = &dra7xx_gpmc_sysc,
772};
773
774/* gpmc */
775
776static struct omap_hwmod dra7xx_gpmc_hwmod = {
777 .name = "gpmc",
778 .class = &dra7xx_gpmc_hwmod_class,
779 .clkdm_name = "l3main1_clkdm",
780 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
781 .main_clk = "l3_iclk_div",
782 .prcm = {
783 .omap4 = {
784 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
785 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
786 .modulemode = MODULEMODE_HWCTRL,
787 },
788 },
789};
790
791/*
792 * 'hdq1w' class
793 *
794 */
795
796static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
797 .rev_offs = 0x0000,
798 .sysc_offs = 0x0014,
799 .syss_offs = 0x0018,
800 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
801 SYSS_HAS_RESET_STATUS),
802 .sysc_fields = &omap_hwmod_sysc_type1,
803};
804
805static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
806 .name = "hdq1w",
807 .sysc = &dra7xx_hdq1w_sysc,
808};
809
810/* hdq1w */
811
812static struct omap_hwmod dra7xx_hdq1w_hwmod = {
813 .name = "hdq1w",
814 .class = &dra7xx_hdq1w_hwmod_class,
815 .clkdm_name = "l4per_clkdm",
816 .flags = HWMOD_INIT_NO_RESET,
817 .main_clk = "func_12m_fclk",
818 .prcm = {
819 .omap4 = {
820 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
821 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
822 .modulemode = MODULEMODE_SWCTRL,
823 },
824 },
825};
826
827/*
828 * 'i2c' class
829 *
830 */
831
832static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
833 .sysc_offs = 0x0010,
834 .syss_offs = 0x0090,
835 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
836 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
837 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
838 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
839 SIDLE_SMART_WKUP),
840 .clockact = CLOCKACT_TEST_ICLK,
841 .sysc_fields = &omap_hwmod_sysc_type1,
842};
843
844static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
845 .name = "i2c",
846 .sysc = &dra7xx_i2c_sysc,
847 .reset = &omap_i2c_reset,
848 .rev = OMAP_I2C_IP_VERSION_2,
849};
850
851/* i2c dev_attr */
852static struct omap_i2c_dev_attr i2c_dev_attr = {
853 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
854};
855
856/* i2c1 */
857static struct omap_hwmod dra7xx_i2c1_hwmod = {
858 .name = "i2c1",
859 .class = &dra7xx_i2c_hwmod_class,
860 .clkdm_name = "l4per_clkdm",
861 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
862 .main_clk = "func_96m_fclk",
863 .prcm = {
864 .omap4 = {
865 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
866 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
867 .modulemode = MODULEMODE_SWCTRL,
868 },
869 },
870 .dev_attr = &i2c_dev_attr,
871};
872
873/* i2c2 */
874static struct omap_hwmod dra7xx_i2c2_hwmod = {
875 .name = "i2c2",
876 .class = &dra7xx_i2c_hwmod_class,
877 .clkdm_name = "l4per_clkdm",
878 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
879 .main_clk = "func_96m_fclk",
880 .prcm = {
881 .omap4 = {
882 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
883 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
884 .modulemode = MODULEMODE_SWCTRL,
885 },
886 },
887 .dev_attr = &i2c_dev_attr,
888};
889
890/* i2c3 */
891static struct omap_hwmod dra7xx_i2c3_hwmod = {
892 .name = "i2c3",
893 .class = &dra7xx_i2c_hwmod_class,
894 .clkdm_name = "l4per_clkdm",
895 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
896 .main_clk = "func_96m_fclk",
897 .prcm = {
898 .omap4 = {
899 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
900 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
901 .modulemode = MODULEMODE_SWCTRL,
902 },
903 },
904 .dev_attr = &i2c_dev_attr,
905};
906
907/* i2c4 */
908static struct omap_hwmod dra7xx_i2c4_hwmod = {
909 .name = "i2c4",
910 .class = &dra7xx_i2c_hwmod_class,
911 .clkdm_name = "l4per_clkdm",
912 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
913 .main_clk = "func_96m_fclk",
914 .prcm = {
915 .omap4 = {
916 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
917 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
918 .modulemode = MODULEMODE_SWCTRL,
919 },
920 },
921 .dev_attr = &i2c_dev_attr,
922};
923
924/* i2c5 */
925static struct omap_hwmod dra7xx_i2c5_hwmod = {
926 .name = "i2c5",
927 .class = &dra7xx_i2c_hwmod_class,
928 .clkdm_name = "ipu_clkdm",
929 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
930 .main_clk = "func_96m_fclk",
931 .prcm = {
932 .omap4 = {
933 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
934 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
935 .modulemode = MODULEMODE_SWCTRL,
936 },
937 },
938 .dev_attr = &i2c_dev_attr,
939};
940
941/*
942 * 'mcspi' class
943 *
944 */
945
946static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
947 .rev_offs = 0x0000,
948 .sysc_offs = 0x0010,
949 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
950 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
951 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
952 SIDLE_SMART_WKUP),
953 .sysc_fields = &omap_hwmod_sysc_type2,
954};
955
956static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
957 .name = "mcspi",
958 .sysc = &dra7xx_mcspi_sysc,
959 .rev = OMAP4_MCSPI_REV,
960};
961
962/* mcspi1 */
963/* mcspi1 dev_attr */
964static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
965 .num_chipselect = 4,
966};
967
968static struct omap_hwmod dra7xx_mcspi1_hwmod = {
969 .name = "mcspi1",
970 .class = &dra7xx_mcspi_hwmod_class,
971 .clkdm_name = "l4per_clkdm",
972 .main_clk = "func_48m_fclk",
973 .prcm = {
974 .omap4 = {
975 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
976 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
977 .modulemode = MODULEMODE_SWCTRL,
978 },
979 },
980 .dev_attr = &mcspi1_dev_attr,
981};
982
983/* mcspi2 */
984/* mcspi2 dev_attr */
985static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
986 .num_chipselect = 2,
987};
988
989static struct omap_hwmod dra7xx_mcspi2_hwmod = {
990 .name = "mcspi2",
991 .class = &dra7xx_mcspi_hwmod_class,
992 .clkdm_name = "l4per_clkdm",
993 .main_clk = "func_48m_fclk",
994 .prcm = {
995 .omap4 = {
996 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
997 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
998 .modulemode = MODULEMODE_SWCTRL,
999 },
1000 },
1001 .dev_attr = &mcspi2_dev_attr,
1002};
1003
1004/* mcspi3 */
1005/* mcspi3 dev_attr */
1006static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1007 .num_chipselect = 2,
1008};
1009
1010static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1011 .name = "mcspi3",
1012 .class = &dra7xx_mcspi_hwmod_class,
1013 .clkdm_name = "l4per_clkdm",
1014 .main_clk = "func_48m_fclk",
1015 .prcm = {
1016 .omap4 = {
1017 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1018 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1019 .modulemode = MODULEMODE_SWCTRL,
1020 },
1021 },
1022 .dev_attr = &mcspi3_dev_attr,
1023};
1024
1025/* mcspi4 */
1026/* mcspi4 dev_attr */
1027static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1028 .num_chipselect = 1,
1029};
1030
1031static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1032 .name = "mcspi4",
1033 .class = &dra7xx_mcspi_hwmod_class,
1034 .clkdm_name = "l4per_clkdm",
1035 .main_clk = "func_48m_fclk",
1036 .prcm = {
1037 .omap4 = {
1038 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1039 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1040 .modulemode = MODULEMODE_SWCTRL,
1041 },
1042 },
1043 .dev_attr = &mcspi4_dev_attr,
1044};
1045
1046/*
1047 * 'mmc' class
1048 *
1049 */
1050
1051static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1052 .rev_offs = 0x0000,
1053 .sysc_offs = 0x0010,
1054 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1055 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1056 SYSC_HAS_SOFTRESET),
1057 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1058 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1059 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1060 .sysc_fields = &omap_hwmod_sysc_type2,
1061};
1062
1063static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1064 .name = "mmc",
1065 .sysc = &dra7xx_mmc_sysc,
1066};
1067
1068/* mmc1 */
1069static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1070 { .role = "clk32k", .clk = "mmc1_clk32k" },
1071};
1072
1073/* mmc1 dev_attr */
1074static struct omap_mmc_dev_attr mmc1_dev_attr = {
1075 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1076};
1077
1078static struct omap_hwmod dra7xx_mmc1_hwmod = {
1079 .name = "mmc1",
1080 .class = &dra7xx_mmc_hwmod_class,
1081 .clkdm_name = "l3init_clkdm",
1082 .main_clk = "mmc1_fclk_div",
1083 .prcm = {
1084 .omap4 = {
1085 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1086 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1087 .modulemode = MODULEMODE_SWCTRL,
1088 },
1089 },
1090 .opt_clks = mmc1_opt_clks,
1091 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1092 .dev_attr = &mmc1_dev_attr,
1093};
1094
1095/* mmc2 */
1096static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1097 { .role = "clk32k", .clk = "mmc2_clk32k" },
1098};
1099
1100static struct omap_hwmod dra7xx_mmc2_hwmod = {
1101 .name = "mmc2",
1102 .class = &dra7xx_mmc_hwmod_class,
1103 .clkdm_name = "l3init_clkdm",
1104 .main_clk = "mmc2_fclk_div",
1105 .prcm = {
1106 .omap4 = {
1107 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1108 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1109 .modulemode = MODULEMODE_SWCTRL,
1110 },
1111 },
1112 .opt_clks = mmc2_opt_clks,
1113 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1114};
1115
1116/* mmc3 */
1117static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1118 { .role = "clk32k", .clk = "mmc3_clk32k" },
1119};
1120
1121static struct omap_hwmod dra7xx_mmc3_hwmod = {
1122 .name = "mmc3",
1123 .class = &dra7xx_mmc_hwmod_class,
1124 .clkdm_name = "l4per_clkdm",
1125 .main_clk = "mmc3_gfclk_div",
1126 .prcm = {
1127 .omap4 = {
1128 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1129 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1130 .modulemode = MODULEMODE_SWCTRL,
1131 },
1132 },
1133 .opt_clks = mmc3_opt_clks,
1134 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1135};
1136
1137/* mmc4 */
1138static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1139 { .role = "clk32k", .clk = "mmc4_clk32k" },
1140};
1141
1142static struct omap_hwmod dra7xx_mmc4_hwmod = {
1143 .name = "mmc4",
1144 .class = &dra7xx_mmc_hwmod_class,
1145 .clkdm_name = "l4per_clkdm",
1146 .main_clk = "mmc4_gfclk_div",
1147 .prcm = {
1148 .omap4 = {
1149 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1150 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1151 .modulemode = MODULEMODE_SWCTRL,
1152 },
1153 },
1154 .opt_clks = mmc4_opt_clks,
1155 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1156};
1157
1158/*
1159 * 'mpu' class
1160 *
1161 */
1162
1163static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1164 .name = "mpu",
1165};
1166
1167/* mpu */
1168static struct omap_hwmod dra7xx_mpu_hwmod = {
1169 .name = "mpu",
1170 .class = &dra7xx_mpu_hwmod_class,
1171 .clkdm_name = "mpu_clkdm",
1172 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1173 .main_clk = "dpll_mpu_m2_ck",
1174 .prcm = {
1175 .omap4 = {
1176 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1177 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1178 },
1179 },
1180};
1181
1182/*
1183 * 'ocp2scp' class
1184 *
1185 */
1186
1187static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1188 .rev_offs = 0x0000,
1189 .sysc_offs = 0x0010,
1190 .syss_offs = 0x0014,
1191 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1192 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1193 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1194 SIDLE_SMART_WKUP),
1195 .sysc_fields = &omap_hwmod_sysc_type1,
1196};
1197
1198static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1199 .name = "ocp2scp",
1200 .sysc = &dra7xx_ocp2scp_sysc,
1201};
1202
1203/* ocp2scp1 */
1204static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1205 .name = "ocp2scp1",
1206 .class = &dra7xx_ocp2scp_hwmod_class,
1207 .clkdm_name = "l3init_clkdm",
1208 .main_clk = "l4_root_clk_div",
1209 .prcm = {
1210 .omap4 = {
1211 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1212 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1213 .modulemode = MODULEMODE_HWCTRL,
1214 },
1215 },
1216};
1217
df0d0f11
RQ		 1218/* ocp2scp3 */
1219static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1220 .name = "ocp2scp3",
1221 .class = &dra7xx_ocp2scp_hwmod_class,
1222 .clkdm_name = "l3init_clkdm",
1223 .main_clk = "l4_root_clk_div",
1224 .prcm = {
1225 .omap4 = {
1226 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1227 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1228 .modulemode = MODULEMODE_HWCTRL,
1229 },
1230 },
1231};
1232
8dd3eb71
KVA		 1233/*
1234 * 'PCIE' class
1235 *
1236 */
1237
1238static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
1239 .name = "pcie",
1240};
1241
1242/* pcie1 */
1243static struct omap_hwmod dra7xx_pcie1_hwmod = {
1244 .name = "pcie1",
1245 .class = &dra7xx_pcie_hwmod_class,
1246 .clkdm_name = "pcie_clkdm",
1247 .main_clk = "l4_root_clk_div",
1248 .prcm = {
1249 .omap4 = {
1250 .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
1251 .modulemode = MODULEMODE_SWCTRL,
1252 },
1253 },
1254};
1255
1256/* pcie2 */
1257static struct omap_hwmod dra7xx_pcie2_hwmod = {
1258 .name = "pcie2",
1259 .class = &dra7xx_pcie_hwmod_class,
1260 .clkdm_name = "pcie_clkdm",
1261 .main_clk = "l4_root_clk_div",
1262 .prcm = {
1263 .omap4 = {
1264 .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
1265 .modulemode = MODULEMODE_SWCTRL,
1266 },
1267 },
1268};
1269
70c18ef7
KVA		 1270/*
1271 * 'PCIE PHY' class
1272 *
1273 */
1274
1275static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
1276 .name = "pcie-phy",
1277};
1278
1279/* pcie1 phy */
1280static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
1281 .name = "pcie1-phy",
1282 .class = &dra7xx_pcie_phy_hwmod_class,
1283 .clkdm_name = "l3init_clkdm",
1284 .main_clk = "l4_root_clk_div",
1285 .prcm = {
1286 .omap4 = {
1287 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1288 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1289 .modulemode = MODULEMODE_SWCTRL,
1290 },
1291 },
1292};
1293
1294/* pcie2 phy */
1295static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
1296 .name = "pcie2-phy",
1297 .class = &dra7xx_pcie_phy_hwmod_class,
1298 .clkdm_name = "l3init_clkdm",
1299 .main_clk = "l4_root_clk_div",
1300 .prcm = {
1301 .omap4 = {
1302 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1303 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1304 .modulemode = MODULEMODE_SWCTRL,
1305 },
1306 },
1307};
1308
90020c7b
A		 1309/*
1310 * 'qspi' class
1311 *
1312 */
1313
1314static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1315 .sysc_offs = 0x0010,
1316 .sysc_flags = SYSC_HAS_SIDLEMODE,
1317 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1318 SIDLE_SMART_WKUP),
1319 .sysc_fields = &omap_hwmod_sysc_type2,
1320};
1321
1322static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1323 .name = "qspi",
1324 .sysc = &dra7xx_qspi_sysc,
1325};
1326
1327/* qspi */
1328static struct omap_hwmod dra7xx_qspi_hwmod = {
1329 .name = "qspi",
1330 .class = &dra7xx_qspi_hwmod_class,
1331 .clkdm_name = "l4per2_clkdm",
1332 .main_clk = "qspi_gfclk_div",
1333 .prcm = {
1334 .omap4 = {
1335 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1336 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1337 .modulemode = MODULEMODE_SWCTRL,
1338 },
1339 },
1340};
1341
1342/*
1343 * 'sata' class
1344 *
1345 */
1346
1347static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1348 .sysc_offs = 0x0000,
1349 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1350 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1351 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1352 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1353 .sysc_fields = &omap_hwmod_sysc_type2,
1354};
1355
1356static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1357 .name = "sata",
1358 .sysc = &dra7xx_sata_sysc,
1359};
1360
1361/* sata */
1362static struct omap_hwmod_opt_clk sata_opt_clks[] = {
1363 { .role = "ref_clk", .clk = "sata_ref_clk" },
1364};
1365
1366static struct omap_hwmod dra7xx_sata_hwmod = {
1367 .name = "sata",
1368 .class = &dra7xx_sata_hwmod_class,
1369 .clkdm_name = "l3init_clkdm",
1370 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1371 .main_clk = "func_48m_fclk",
1372 .prcm = {
1373 .omap4 = {
1374 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1375 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1376 .modulemode = MODULEMODE_SWCTRL,
1377 },
1378 },
1379 .opt_clks = sata_opt_clks,
1380 .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
1381};
1382
1383/*
1384 * 'smartreflex' class
1385 *
1386 */
1387
1388/* The IP is not compliant to type1 / type2 scheme */
1389static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1390 .sidle_shift = 24,
1391 .enwkup_shift = 26,
1392};
1393
1394static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1395 .sysc_offs = 0x0038,
1396 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1397 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1398 SIDLE_SMART_WKUP),
1399 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1400};
1401
1402static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1403 .name = "smartreflex",
1404 .sysc = &dra7xx_smartreflex_sysc,
1405 .rev = 2,
1406};
1407
1408/* smartreflex_core */
1409/* smartreflex_core dev_attr */
1410static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1411 .sensor_voltdm_name = "core",
1412};
1413
1414static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1415 .name = "smartreflex_core",
1416 .class = &dra7xx_smartreflex_hwmod_class,
1417 .clkdm_name = "coreaon_clkdm",
1418 .main_clk = "wkupaon_iclk_mux",
1419 .prcm = {
1420 .omap4 = {
1421 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1422 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1423 .modulemode = MODULEMODE_SWCTRL,
1424 },
1425 },
1426 .dev_attr = &smartreflex_core_dev_attr,
1427};
1428
1429/* smartreflex_mpu */
1430/* smartreflex_mpu dev_attr */
1431static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1432 .sensor_voltdm_name = "mpu",
1433};
1434
1435static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1436 .name = "smartreflex_mpu",
1437 .class = &dra7xx_smartreflex_hwmod_class,
1438 .clkdm_name = "coreaon_clkdm",
1439 .main_clk = "wkupaon_iclk_mux",
1440 .prcm = {
1441 .omap4 = {
1442 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1443 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1444 .modulemode = MODULEMODE_SWCTRL,
1445 },
1446 },
1447 .dev_attr = &smartreflex_mpu_dev_attr,
1448};
1449
1450/*
1451 * 'spinlock' class
1452 *
1453 */
1454
1455static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1456 .rev_offs = 0x0000,
1457 .sysc_offs = 0x0010,
1458 .syss_offs = 0x0014,
c317d0f2
SA		 1459 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1460 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1461 SYSS_HAS_RESET_STATUS),
1462 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
90020c7b
A		 1463 .sysc_fields = &omap_hwmod_sysc_type1,
1464};
1465
1466static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1467 .name = "spinlock",
1468 .sysc = &dra7xx_spinlock_sysc,
1469};
1470
1471/* spinlock */
1472static struct omap_hwmod dra7xx_spinlock_hwmod = {
1473 .name = "spinlock",
1474 .class = &dra7xx_spinlock_hwmod_class,
1475 .clkdm_name = "l4cfg_clkdm",
1476 .main_clk = "l3_iclk_div",
1477 .prcm = {
1478 .omap4 = {
1479 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1480 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1481 },
1482 },
1483};
1484
1485/*
1486 * 'timer' class
1487 *
1488 * This class contains several variants: ['timer_1ms', 'timer_secure',
1489 * 'timer']
1490 */
1491
1492static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1493 .rev_offs = 0x0000,
1494 .sysc_offs = 0x0010,
1495 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1496 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1497 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1498 SIDLE_SMART_WKUP),
1499 .sysc_fields = &omap_hwmod_sysc_type2,
1500};
1501
1502static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1503 .name = "timer",
1504 .sysc = &dra7xx_timer_1ms_sysc,
1505};
1506
1507static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
1508 .rev_offs = 0x0000,
1509 .sysc_offs = 0x0010,
1510 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1511 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1512 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1513 SIDLE_SMART_WKUP),
1514 .sysc_fields = &omap_hwmod_sysc_type2,
1515};
1516
1517static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
1518 .name = "timer",
1519 .sysc = &dra7xx_timer_secure_sysc,
1520};
1521
1522static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1523 .rev_offs = 0x0000,
1524 .sysc_offs = 0x0010,
1525 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1526 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1527 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1528 SIDLE_SMART_WKUP),
1529 .sysc_fields = &omap_hwmod_sysc_type2,
1530};
1531
1532static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1533 .name = "timer",
1534 .sysc = &dra7xx_timer_sysc,
1535};
1536
1537/* timer1 */
1538static struct omap_hwmod dra7xx_timer1_hwmod = {
1539 .name = "timer1",
1540 .class = &dra7xx_timer_1ms_hwmod_class,
1541 .clkdm_name = "wkupaon_clkdm",
1542 .main_clk = "timer1_gfclk_mux",
1543 .prcm = {
1544 .omap4 = {
1545 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1546 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1547 .modulemode = MODULEMODE_SWCTRL,
1548 },
1549 },
1550};
1551
1552/* timer2 */
1553static struct omap_hwmod dra7xx_timer2_hwmod = {
1554 .name = "timer2",
1555 .class = &dra7xx_timer_1ms_hwmod_class,
1556 .clkdm_name = "l4per_clkdm",
1557 .main_clk = "timer2_gfclk_mux",
1558 .prcm = {
1559 .omap4 = {
1560 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1561 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1562 .modulemode = MODULEMODE_SWCTRL,
1563 },
1564 },
1565};
1566
1567/* timer3 */
1568static struct omap_hwmod dra7xx_timer3_hwmod = {
1569 .name = "timer3",
1570 .class = &dra7xx_timer_hwmod_class,
1571 .clkdm_name = "l4per_clkdm",
1572 .main_clk = "timer3_gfclk_mux",
1573 .prcm = {
1574 .omap4 = {
1575 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1576 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1577 .modulemode = MODULEMODE_SWCTRL,
1578 },
1579 },
1580};
1581
1582/* timer4 */
1583static struct omap_hwmod dra7xx_timer4_hwmod = {
1584 .name = "timer4",
1585 .class = &dra7xx_timer_secure_hwmod_class,
1586 .clkdm_name = "l4per_clkdm",
1587 .main_clk = "timer4_gfclk_mux",
1588 .prcm = {
1589 .omap4 = {
1590 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1591 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1592 .modulemode = MODULEMODE_SWCTRL,
1593 },
1594 },
1595};
1596
1597/* timer5 */
1598static struct omap_hwmod dra7xx_timer5_hwmod = {
1599 .name = "timer5",
1600 .class = &dra7xx_timer_hwmod_class,
1601 .clkdm_name = "ipu_clkdm",
1602 .main_clk = "timer5_gfclk_mux",
1603 .prcm = {
1604 .omap4 = {
1605 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1606 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1607 .modulemode = MODULEMODE_SWCTRL,
1608 },
1609 },
1610};
1611
1612/* timer6 */
1613static struct omap_hwmod dra7xx_timer6_hwmod = {
1614 .name = "timer6",
1615 .class = &dra7xx_timer_hwmod_class,
1616 .clkdm_name = "ipu_clkdm",
1617 .main_clk = "timer6_gfclk_mux",
1618 .prcm = {
1619 .omap4 = {
1620 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1621 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1622 .modulemode = MODULEMODE_SWCTRL,
1623 },
1624 },
1625};
1626
1627/* timer7 */
1628static struct omap_hwmod dra7xx_timer7_hwmod = {
1629 .name = "timer7",
1630 .class = &dra7xx_timer_hwmod_class,
1631 .clkdm_name = "ipu_clkdm",
1632 .main_clk = "timer7_gfclk_mux",
1633 .prcm = {
1634 .omap4 = {
1635 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1636 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1637 .modulemode = MODULEMODE_SWCTRL,
1638 },
1639 },
1640};
1641
1642/* timer8 */
1643static struct omap_hwmod dra7xx_timer8_hwmod = {
1644 .name = "timer8",
1645 .class = &dra7xx_timer_hwmod_class,
1646 .clkdm_name = "ipu_clkdm",
1647 .main_clk = "timer8_gfclk_mux",
1648 .prcm = {
1649 .omap4 = {
1650 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1651 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1652 .modulemode = MODULEMODE_SWCTRL,
1653 },
1654 },
1655};
1656
1657/* timer9 */
1658static struct omap_hwmod dra7xx_timer9_hwmod = {
1659 .name = "timer9",
1660 .class = &dra7xx_timer_hwmod_class,
1661 .clkdm_name = "l4per_clkdm",
1662 .main_clk = "timer9_gfclk_mux",
1663 .prcm = {
1664 .omap4 = {
1665 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1666 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1667 .modulemode = MODULEMODE_SWCTRL,
1668 },
1669 },
1670};
1671
1672/* timer10 */
1673static struct omap_hwmod dra7xx_timer10_hwmod = {
1674 .name = "timer10",
1675 .class = &dra7xx_timer_1ms_hwmod_class,
1676 .clkdm_name = "l4per_clkdm",
1677 .main_clk = "timer10_gfclk_mux",
1678 .prcm = {
1679 .omap4 = {
1680 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1681 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1682 .modulemode = MODULEMODE_SWCTRL,
1683 },
1684 },
1685};
1686
1687/* timer11 */
1688static struct omap_hwmod dra7xx_timer11_hwmod = {
1689 .name = "timer11",
1690 .class = &dra7xx_timer_hwmod_class,
1691 .clkdm_name = "l4per_clkdm",
1692 .main_clk = "timer11_gfclk_mux",
1693 .prcm = {
1694 .omap4 = {
1695 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1696 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1697 .modulemode = MODULEMODE_SWCTRL,
1698 },
1699 },
1700};
1701
1702/*
1703 * 'uart' class
1704 *
1705 */
1706
1707static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
1708 .rev_offs = 0x0050,
1709 .sysc_offs = 0x0054,
1710 .syss_offs = 0x0058,
1711 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1712 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1713 SYSS_HAS_RESET_STATUS),
1714 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1715 SIDLE_SMART_WKUP),
1716 .sysc_fields = &omap_hwmod_sysc_type1,
1717};
1718
1719static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
1720 .name = "uart",
1721 .sysc = &dra7xx_uart_sysc,
1722};
1723
1724/* uart1 */
1725static struct omap_hwmod dra7xx_uart1_hwmod = {
1726 .name = "uart1",
1727 .class = &dra7xx_uart_hwmod_class,
1728 .clkdm_name = "l4per_clkdm",
1729 .main_clk = "uart1_gfclk_mux",
38958c15 1730 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
90020c7b
A		 1731 .prcm = {
1732 .omap4 = {
1733 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1734 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1735 .modulemode = MODULEMODE_SWCTRL,
1736 },
1737 },
1738};
1739
1740/* uart2 */
1741static struct omap_hwmod dra7xx_uart2_hwmod = {
1742 .name = "uart2",
1743 .class = &dra7xx_uart_hwmod_class,
1744 .clkdm_name = "l4per_clkdm",
1745 .main_clk = "uart2_gfclk_mux",
1746 .flags = HWMOD_SWSUP_SIDLE_ACT,
1747 .prcm = {
1748 .omap4 = {
1749 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1750 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1751 .modulemode = MODULEMODE_SWCTRL,
1752 },
1753 },
1754};
1755
1756/* uart3 */
1757static struct omap_hwmod dra7xx_uart3_hwmod = {
1758 .name = "uart3",
1759 .class = &dra7xx_uart_hwmod_class,
1760 .clkdm_name = "l4per_clkdm",
1761 .main_clk = "uart3_gfclk_mux",
1762 .flags = HWMOD_SWSUP_SIDLE_ACT,
1763 .prcm = {
1764 .omap4 = {
1765 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1766 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1767 .modulemode = MODULEMODE_SWCTRL,
1768 },
1769 },
1770};
1771
1772/* uart4 */
1773static struct omap_hwmod dra7xx_uart4_hwmod = {
1774 .name = "uart4",
1775 .class = &dra7xx_uart_hwmod_class,
1776 .clkdm_name = "l4per_clkdm",
1777 .main_clk = "uart4_gfclk_mux",
1778 .flags = HWMOD_SWSUP_SIDLE_ACT,
1779 .prcm = {
1780 .omap4 = {
1781 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1782 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1783 .modulemode = MODULEMODE_SWCTRL,
1784 },
1785 },
1786};
1787
1788/* uart5 */
1789static struct omap_hwmod dra7xx_uart5_hwmod = {
1790 .name = "uart5",
1791 .class = &dra7xx_uart_hwmod_class,
1792 .clkdm_name = "l4per_clkdm",
1793 .main_clk = "uart5_gfclk_mux",
1794 .flags = HWMOD_SWSUP_SIDLE_ACT,
1795 .prcm = {
1796 .omap4 = {
1797 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1798 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1799 .modulemode = MODULEMODE_SWCTRL,
1800 },
1801 },
1802};
1803
1804/* uart6 */
1805static struct omap_hwmod dra7xx_uart6_hwmod = {
1806 .name = "uart6",
1807 .class = &dra7xx_uart_hwmod_class,
1808 .clkdm_name = "ipu_clkdm",
1809 .main_clk = "uart6_gfclk_mux",
1810 .flags = HWMOD_SWSUP_SIDLE_ACT,
1811 .prcm = {
1812 .omap4 = {
1813 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
1814 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
1815 .modulemode = MODULEMODE_SWCTRL,
1816 },
1817 },
1818};
1819
1820/*
1821 * 'usb_otg_ss' class
1822 *
1823 */
1824
1825static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
1826 .name = "usb_otg_ss",
1827};
1828
1829/* usb_otg_ss1 */
1830static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
1831 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
1832};
1833
1834static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
1835 .name = "usb_otg_ss1",
1836 .class = &dra7xx_usb_otg_ss_hwmod_class,
1837 .clkdm_name = "l3init_clkdm",
1838 .main_clk = "dpll_core_h13x2_ck",
1839 .prcm = {
1840 .omap4 = {
1841 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
1842 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
1843 .modulemode = MODULEMODE_HWCTRL,
1844 },
1845 },
1846 .opt_clks = usb_otg_ss1_opt_clks,
1847 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
1848};
1849
1850/* usb_otg_ss2 */
1851static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
1852 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
1853};
1854
1855static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
1856 .name = "usb_otg_ss2",
1857 .class = &dra7xx_usb_otg_ss_hwmod_class,
1858 .clkdm_name = "l3init_clkdm",
1859 .main_clk = "dpll_core_h13x2_ck",
1860 .prcm = {
1861 .omap4 = {
1862 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
1863 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
1864 .modulemode = MODULEMODE_HWCTRL,
1865 },
1866 },
1867 .opt_clks = usb_otg_ss2_opt_clks,
1868 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
1869};
1870
1871/* usb_otg_ss3 */
1872static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
1873 .name = "usb_otg_ss3",
1874 .class = &dra7xx_usb_otg_ss_hwmod_class,
1875 .clkdm_name = "l3init_clkdm",
1876 .main_clk = "dpll_core_h13x2_ck",
1877 .prcm = {
1878 .omap4 = {
1879 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
1880 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
1881 .modulemode = MODULEMODE_HWCTRL,
1882 },
1883 },
1884};
1885
1886/* usb_otg_ss4 */
1887static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
1888 .name = "usb_otg_ss4",
1889 .class = &dra7xx_usb_otg_ss_hwmod_class,
1890 .clkdm_name = "l3init_clkdm",
1891 .main_clk = "dpll_core_h13x2_ck",
1892 .prcm = {
1893 .omap4 = {
1894 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
1895 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
1896 .modulemode = MODULEMODE_HWCTRL,
1897 },
1898 },
1899};
1900
1901/*
1902 * 'vcp' class
1903 *
1904 */
1905
1906static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
1907 .name = "vcp",
1908};
1909
1910/* vcp1 */
1911static struct omap_hwmod dra7xx_vcp1_hwmod = {
1912 .name = "vcp1",
1913 .class = &dra7xx_vcp_hwmod_class,
1914 .clkdm_name = "l3main1_clkdm",
1915 .main_clk = "l3_iclk_div",
1916 .prcm = {
1917 .omap4 = {
1918 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
1919 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
1920 },
1921 },
1922};
1923
1924/* vcp2 */
1925static struct omap_hwmod dra7xx_vcp2_hwmod = {
1926 .name = "vcp2",
1927 .class = &dra7xx_vcp_hwmod_class,
1928 .clkdm_name = "l3main1_clkdm",
1929 .main_clk = "l3_iclk_div",
1930 .prcm = {
1931 .omap4 = {
1932 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
1933 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
1934 },
1935 },
1936};
1937
1938/*
1939 * 'wd_timer' class
1940 *
1941 */
1942
1943static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
1944 .rev_offs = 0x0000,
1945 .sysc_offs = 0x0010,
1946 .syss_offs = 0x0014,
1947 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1948 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1949 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1950 SIDLE_SMART_WKUP),
1951 .sysc_fields = &omap_hwmod_sysc_type1,
1952};
1953
1954static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
1955 .name = "wd_timer",
1956 .sysc = &dra7xx_wd_timer_sysc,
1957 .pre_shutdown = &omap2_wd_timer_disable,
1958 .reset = &omap2_wd_timer_reset,
1959};
1960
1961/* wd_timer2 */
1962static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
1963 .name = "wd_timer2",
1964 .class = &dra7xx_wd_timer_hwmod_class,
1965 .clkdm_name = "wkupaon_clkdm",
1966 .main_clk = "sys_32k_ck",
1967 .prcm = {
1968 .omap4 = {
1969 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
1970 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
1971 .modulemode = MODULEMODE_SWCTRL,
1972 },
1973 },
1974};
1975
1976
1977/*
1978 * Interfaces
1979 */
1980
1981/* l3_main_2 -> l3_instr */
1982static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
1983 .master = &dra7xx_l3_main_2_hwmod,
1984 .slave = &dra7xx_l3_instr_hwmod,
1985 .clk = "l3_iclk_div",
1986 .user = OCP_USER_MPU | OCP_USER_SDMA,
1987};
1988
1989/* l4_cfg -> l3_main_1 */
1990static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
1991 .master = &dra7xx_l4_cfg_hwmod,
1992 .slave = &dra7xx_l3_main_1_hwmod,
1993 .clk = "l3_iclk_div",
1994 .user = OCP_USER_MPU | OCP_USER_SDMA,
1995};
1996
1997/* mpu -> l3_main_1 */
1998static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
1999 .master = &dra7xx_mpu_hwmod,
2000 .slave = &dra7xx_l3_main_1_hwmod,
2001 .clk = "l3_iclk_div",
2002 .user = OCP_USER_MPU,
2003};
2004
2005/* l3_main_1 -> l3_main_2 */
2006static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2007 .master = &dra7xx_l3_main_1_hwmod,
2008 .slave = &dra7xx_l3_main_2_hwmod,
2009 .clk = "l3_iclk_div",
2010 .user = OCP_USER_MPU,
2011};
2012
2013/* l4_cfg -> l3_main_2 */
2014static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2015 .master = &dra7xx_l4_cfg_hwmod,
2016 .slave = &dra7xx_l3_main_2_hwmod,
2017 .clk = "l3_iclk_div",
2018 .user = OCP_USER_MPU | OCP_USER_SDMA,
2019};
2020
2021/* l3_main_1 -> l4_cfg */
2022static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2023 .master = &dra7xx_l3_main_1_hwmod,
2024 .slave = &dra7xx_l4_cfg_hwmod,
2025 .clk = "l3_iclk_div",
2026 .user = OCP_USER_MPU | OCP_USER_SDMA,
2027};
2028
2029/* l3_main_1 -> l4_per1 */
2030static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2031 .master = &dra7xx_l3_main_1_hwmod,
2032 .slave = &dra7xx_l4_per1_hwmod,
2033 .clk = "l3_iclk_div",
2034 .user = OCP_USER_MPU | OCP_USER_SDMA,
2035};
2036
2037/* l3_main_1 -> l4_per2 */
2038static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2039 .master = &dra7xx_l3_main_1_hwmod,
2040 .slave = &dra7xx_l4_per2_hwmod,
2041 .clk = "l3_iclk_div",
2042 .user = OCP_USER_MPU | OCP_USER_SDMA,
2043};
2044
2045/* l3_main_1 -> l4_per3 */
2046static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2047 .master = &dra7xx_l3_main_1_hwmod,
2048 .slave = &dra7xx_l4_per3_hwmod,
2049 .clk = "l3_iclk_div",
2050 .user = OCP_USER_MPU | OCP_USER_SDMA,
2051};
2052
2053/* l3_main_1 -> l4_wkup */
2054static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2055 .master = &dra7xx_l3_main_1_hwmod,
2056 .slave = &dra7xx_l4_wkup_hwmod,
2057 .clk = "wkupaon_iclk_mux",
2058 .user = OCP_USER_MPU | OCP_USER_SDMA,
2059};
2060
2061/* l4_per2 -> atl */
2062static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2063 .master = &dra7xx_l4_per2_hwmod,
2064 .slave = &dra7xx_atl_hwmod,
2065 .clk = "l3_iclk_div",
2066 .user = OCP_USER_MPU | OCP_USER_SDMA,
2067};
2068
2069/* l3_main_1 -> bb2d */
2070static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2071 .master = &dra7xx_l3_main_1_hwmod,
2072 .slave = &dra7xx_bb2d_hwmod,
2073 .clk = "l3_iclk_div",
2074 .user = OCP_USER_MPU | OCP_USER_SDMA,
2075};
2076
2077/* l4_wkup -> counter_32k */
2078static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2079 .master = &dra7xx_l4_wkup_hwmod,
2080 .slave = &dra7xx_counter_32k_hwmod,
2081 .clk = "wkupaon_iclk_mux",
2082 .user = OCP_USER_MPU | OCP_USER_SDMA,
2083};
2084
2085/* l4_wkup -> ctrl_module_wkup */
2086static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2087 .master = &dra7xx_l4_wkup_hwmod,
2088 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2089 .clk = "wkupaon_iclk_mux",
2090 .user = OCP_USER_MPU | OCP_USER_SDMA,
2091};
2092
2093/* l4_wkup -> dcan1 */
2094static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2095 .master = &dra7xx_l4_wkup_hwmod,
2096 .slave = &dra7xx_dcan1_hwmod,
2097 .clk = "wkupaon_iclk_mux",
2098 .user = OCP_USER_MPU | OCP_USER_SDMA,
2099};
2100
2101/* l4_per2 -> dcan2 */
2102static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2103 .master = &dra7xx_l4_per2_hwmod,
2104 .slave = &dra7xx_dcan2_hwmod,
2105 .clk = "l3_iclk_div",
2106 .user = OCP_USER_MPU | OCP_USER_SDMA,
2107};
2108
2109static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2110 {
2111 .pa_start = 0x4a056000,
2112 .pa_end = 0x4a056fff,
2113 .flags = ADDR_TYPE_RT
2114 },
2115 { }
2116};
2117
2118/* l4_cfg -> dma_system */
2119static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2120 .master = &dra7xx_l4_cfg_hwmod,
2121 .slave = &dra7xx_dma_system_hwmod,
2122 .clk = "l3_iclk_div",
2123 .addr = dra7xx_dma_system_addrs,
2124 .user = OCP_USER_MPU | OCP_USER_SDMA,
2125};
2126
2127static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2128 {
2129 .name = "family",
2130 .pa_start = 0x58000000,
2131 .pa_end = 0x5800007f,
2132 .flags = ADDR_TYPE_RT
2133 },
2134};
2135
2136/* l3_main_1 -> dss */
2137static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2138 .master = &dra7xx_l3_main_1_hwmod,
2139 .slave = &dra7xx_dss_hwmod,
2140 .clk = "l3_iclk_div",
2141 .addr = dra7xx_dss_addrs,
2142 .user = OCP_USER_MPU | OCP_USER_SDMA,
2143};
2144
2145static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2146 {
2147 .name = "dispc",
2148 .pa_start = 0x58001000,
2149 .pa_end = 0x58001fff,
2150 .flags = ADDR_TYPE_RT
2151 },
2152};
2153
2154/* l3_main_1 -> dispc */
2155static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2156 .master = &dra7xx_l3_main_1_hwmod,
2157 .slave = &dra7xx_dss_dispc_hwmod,
2158 .clk = "l3_iclk_div",
2159 .addr = dra7xx_dss_dispc_addrs,
2160 .user = OCP_USER_MPU | OCP_USER_SDMA,
2161};
2162
2163static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2164 {
2165 .name = "hdmi_wp",
2166 .pa_start = 0x58040000,
2167 .pa_end = 0x580400ff,
2168 .flags = ADDR_TYPE_RT
2169 },
2170 { }
2171};
2172
2173/* l3_main_1 -> dispc */
2174static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2175 .master = &dra7xx_l3_main_1_hwmod,
2176 .slave = &dra7xx_dss_hdmi_hwmod,
2177 .clk = "l3_iclk_div",
2178 .addr = dra7xx_dss_hdmi_addrs,
2179 .user = OCP_USER_MPU | OCP_USER_SDMA,
2180};
2181
2182static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
2183 {
2184 .pa_start = 0x48078000,
2185 .pa_end = 0x48078fff,
2186 .flags = ADDR_TYPE_RT
2187 },
2188 { }
2189};
2190
2191/* l4_per1 -> elm */
2192static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2193 .master = &dra7xx_l4_per1_hwmod,
2194 .slave = &dra7xx_elm_hwmod,
2195 .clk = "l3_iclk_div",
2196 .addr = dra7xx_elm_addrs,
2197 .user = OCP_USER_MPU | OCP_USER_SDMA,
2198};
2199
2200/* l4_wkup -> gpio1 */
2201static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2202 .master = &dra7xx_l4_wkup_hwmod,
2203 .slave = &dra7xx_gpio1_hwmod,
2204 .clk = "wkupaon_iclk_mux",
2205 .user = OCP_USER_MPU | OCP_USER_SDMA,
2206};
2207
2208/* l4_per1 -> gpio2 */
2209static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2210 .master = &dra7xx_l4_per1_hwmod,
2211 .slave = &dra7xx_gpio2_hwmod,
2212 .clk = "l3_iclk_div",
2213 .user = OCP_USER_MPU | OCP_USER_SDMA,
2214};
2215
2216/* l4_per1 -> gpio3 */
2217static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2218 .master = &dra7xx_l4_per1_hwmod,
2219 .slave = &dra7xx_gpio3_hwmod,
2220 .clk = "l3_iclk_div",
2221 .user = OCP_USER_MPU | OCP_USER_SDMA,
2222};
2223
2224/* l4_per1 -> gpio4 */
2225static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2226 .master = &dra7xx_l4_per1_hwmod,
2227 .slave = &dra7xx_gpio4_hwmod,
2228 .clk = "l3_iclk_div",
2229 .user = OCP_USER_MPU | OCP_USER_SDMA,
2230};
2231
2232/* l4_per1 -> gpio5 */
2233static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2234 .master = &dra7xx_l4_per1_hwmod,
2235 .slave = &dra7xx_gpio5_hwmod,
2236 .clk = "l3_iclk_div",
2237 .user = OCP_USER_MPU | OCP_USER_SDMA,
2238};
2239
2240/* l4_per1 -> gpio6 */
2241static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2242 .master = &dra7xx_l4_per1_hwmod,
2243 .slave = &dra7xx_gpio6_hwmod,
2244 .clk = "l3_iclk_div",
2245 .user = OCP_USER_MPU | OCP_USER_SDMA,
2246};
2247
2248/* l4_per1 -> gpio7 */
2249static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2250 .master = &dra7xx_l4_per1_hwmod,
2251 .slave = &dra7xx_gpio7_hwmod,
2252 .clk = "l3_iclk_div",
2253 .user = OCP_USER_MPU | OCP_USER_SDMA,
2254};
2255
2256/* l4_per1 -> gpio8 */
2257static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2258 .master = &dra7xx_l4_per1_hwmod,
2259 .slave = &dra7xx_gpio8_hwmod,
2260 .clk = "l3_iclk_div",
2261 .user = OCP_USER_MPU | OCP_USER_SDMA,
2262};
2263
2264static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
2265 {
2266 .pa_start = 0x50000000,
2267 .pa_end = 0x500003ff,
2268 .flags = ADDR_TYPE_RT
2269 },
2270 { }
2271};
2272
2273/* l3_main_1 -> gpmc */
2274static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2275 .master = &dra7xx_l3_main_1_hwmod,
2276 .slave = &dra7xx_gpmc_hwmod,
2277 .clk = "l3_iclk_div",
2278 .addr = dra7xx_gpmc_addrs,
2279 .user = OCP_USER_MPU | OCP_USER_SDMA,
2280};
2281
2282static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2283 {
2284 .pa_start = 0x480b2000,
2285 .pa_end = 0x480b201f,
2286 .flags = ADDR_TYPE_RT
2287 },
2288 { }
2289};
2290
2291/* l4_per1 -> hdq1w */
2292static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2293 .master = &dra7xx_l4_per1_hwmod,
2294 .slave = &dra7xx_hdq1w_hwmod,
2295 .clk = "l3_iclk_div",
2296 .addr = dra7xx_hdq1w_addrs,
2297 .user = OCP_USER_MPU | OCP_USER_SDMA,
2298};
2299
2300/* l4_per1 -> i2c1 */
2301static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2302 .master = &dra7xx_l4_per1_hwmod,
2303 .slave = &dra7xx_i2c1_hwmod,
2304 .clk = "l3_iclk_div",
2305 .user = OCP_USER_MPU | OCP_USER_SDMA,
2306};
2307
2308/* l4_per1 -> i2c2 */
2309static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2310 .master = &dra7xx_l4_per1_hwmod,
2311 .slave = &dra7xx_i2c2_hwmod,
2312 .clk = "l3_iclk_div",
2313 .user = OCP_USER_MPU | OCP_USER_SDMA,
2314};
2315
2316/* l4_per1 -> i2c3 */
2317static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2318 .master = &dra7xx_l4_per1_hwmod,
2319 .slave = &dra7xx_i2c3_hwmod,
2320 .clk = "l3_iclk_div",
2321 .user = OCP_USER_MPU | OCP_USER_SDMA,
2322};
2323
2324/* l4_per1 -> i2c4 */
2325static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2326 .master = &dra7xx_l4_per1_hwmod,
2327 .slave = &dra7xx_i2c4_hwmod,
2328 .clk = "l3_iclk_div",
2329 .user = OCP_USER_MPU | OCP_USER_SDMA,
2330};
2331
2332/* l4_per1 -> i2c5 */
2333static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2334 .master = &dra7xx_l4_per1_hwmod,
2335 .slave = &dra7xx_i2c5_hwmod,
2336 .clk = "l3_iclk_div",
2337 .user = OCP_USER_MPU | OCP_USER_SDMA,
2338};
2339
2340/* l4_per1 -> mcspi1 */
2341static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2342 .master = &dra7xx_l4_per1_hwmod,
2343 .slave = &dra7xx_mcspi1_hwmod,
2344 .clk = "l3_iclk_div",
2345 .user = OCP_USER_MPU | OCP_USER_SDMA,
2346};
2347
2348/* l4_per1 -> mcspi2 */
2349static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2350 .master = &dra7xx_l4_per1_hwmod,
2351 .slave = &dra7xx_mcspi2_hwmod,
2352 .clk = "l3_iclk_div",
2353 .user = OCP_USER_MPU | OCP_USER_SDMA,
2354};
2355
2356/* l4_per1 -> mcspi3 */
2357static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2358 .master = &dra7xx_l4_per1_hwmod,
2359 .slave = &dra7xx_mcspi3_hwmod,
2360 .clk = "l3_iclk_div",
2361 .user = OCP_USER_MPU | OCP_USER_SDMA,
2362};
2363
2364/* l4_per1 -> mcspi4 */
2365static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2366 .master = &dra7xx_l4_per1_hwmod,
2367 .slave = &dra7xx_mcspi4_hwmod,
2368 .clk = "l3_iclk_div",
2369 .user = OCP_USER_MPU | OCP_USER_SDMA,
2370};
2371
2372/* l4_per1 -> mmc1 */
2373static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
2374 .master = &dra7xx_l4_per1_hwmod,
2375 .slave = &dra7xx_mmc1_hwmod,
2376 .clk = "l3_iclk_div",
2377 .user = OCP_USER_MPU | OCP_USER_SDMA,
2378};
2379
2380/* l4_per1 -> mmc2 */
2381static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
2382 .master = &dra7xx_l4_per1_hwmod,
2383 .slave = &dra7xx_mmc2_hwmod,
2384 .clk = "l3_iclk_div",
2385 .user = OCP_USER_MPU | OCP_USER_SDMA,
2386};
2387
2388/* l4_per1 -> mmc3 */
2389static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
2390 .master = &dra7xx_l4_per1_hwmod,
2391 .slave = &dra7xx_mmc3_hwmod,
2392 .clk = "l3_iclk_div",
2393 .user = OCP_USER_MPU | OCP_USER_SDMA,
2394};
2395
2396/* l4_per1 -> mmc4 */
2397static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
2398 .master = &dra7xx_l4_per1_hwmod,
2399 .slave = &dra7xx_mmc4_hwmod,
2400 .clk = "l3_iclk_div",
2401 .user = OCP_USER_MPU | OCP_USER_SDMA,
2402};
2403
2404/* l4_cfg -> mpu */
2405static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2406 .master = &dra7xx_l4_cfg_hwmod,
2407 .slave = &dra7xx_mpu_hwmod,
2408 .clk = "l3_iclk_div",
2409 .user = OCP_USER_MPU | OCP_USER_SDMA,
2410};
2411
90020c7b
A		 2412/* l4_cfg -> ocp2scp1 */
2413static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2414 .master = &dra7xx_l4_cfg_hwmod,
2415 .slave = &dra7xx_ocp2scp1_hwmod,
2416 .clk = "l4_root_clk_div",
90020c7b
A		 2417 .user = OCP_USER_MPU | OCP_USER_SDMA,
2418};
2419
df0d0f11
RQ		 2420/* l4_cfg -> ocp2scp3 */
2421static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
2422 .master = &dra7xx_l4_cfg_hwmod,
2423 .slave = &dra7xx_ocp2scp3_hwmod,
2424 .clk = "l4_root_clk_div",
2425 .user = OCP_USER_MPU | OCP_USER_SDMA,
2426};
2427
8dd3eb71
KVA		 2428/* l3_main_1 -> pcie1 */
2429static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
2430 .master = &dra7xx_l3_main_1_hwmod,
2431 .slave = &dra7xx_pcie1_hwmod,
2432 .clk = "l3_iclk_div",
2433 .user = OCP_USER_MPU | OCP_USER_SDMA,
2434};
2435
2436/* l4_cfg -> pcie1 */
2437static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
2438 .master = &dra7xx_l4_cfg_hwmod,
2439 .slave = &dra7xx_pcie1_hwmod,
2440 .clk = "l4_root_clk_div",
2441 .user = OCP_USER_MPU | OCP_USER_SDMA,
2442};
2443
2444/* l3_main_1 -> pcie2 */
2445static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
2446 .master = &dra7xx_l3_main_1_hwmod,
2447 .slave = &dra7xx_pcie2_hwmod,
2448 .clk = "l3_iclk_div",
2449 .user = OCP_USER_MPU | OCP_USER_SDMA,
2450};
2451
2452/* l4_cfg -> pcie2 */
2453static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
2454 .master = &dra7xx_l4_cfg_hwmod,
2455 .slave = &dra7xx_pcie2_hwmod,
2456 .clk = "l4_root_clk_div",
2457 .user = OCP_USER_MPU | OCP_USER_SDMA,
2458};
2459
70c18ef7
KVA		 2460/* l4_cfg -> pcie1 phy */
2461static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
2462 .master = &dra7xx_l4_cfg_hwmod,
2463 .slave = &dra7xx_pcie1_phy_hwmod,
2464 .clk = "l4_root_clk_div",
2465 .user = OCP_USER_MPU | OCP_USER_SDMA,
2466};
2467
2468/* l4_cfg -> pcie2 phy */
2469static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
2470 .master = &dra7xx_l4_cfg_hwmod,
2471 .slave = &dra7xx_pcie2_phy_hwmod,
2472 .clk = "l4_root_clk_div",
2473 .user = OCP_USER_MPU | OCP_USER_SDMA,
2474};
2475
90020c7b
A		 2476static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2477 {
2478 .pa_start = 0x4b300000,
2479 .pa_end = 0x4b30007f,
2480 .flags = ADDR_TYPE_RT
2481 },
2482 { }
2483};
2484
2485/* l3_main_1 -> qspi */
2486static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2487 .master = &dra7xx_l3_main_1_hwmod,
2488 .slave = &dra7xx_qspi_hwmod,
2489 .clk = "l3_iclk_div",
2490 .addr = dra7xx_qspi_addrs,
2491 .user = OCP_USER_MPU | OCP_USER_SDMA,
2492};
2493
2494static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
2495 {
2496 .name = "sysc",
2497 .pa_start = 0x4a141100,
2498 .pa_end = 0x4a141107,
2499 .flags = ADDR_TYPE_RT
2500 },
2501 { }
2502};
2503
2504/* l4_cfg -> sata */
2505static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
2506 .master = &dra7xx_l4_cfg_hwmod,
2507 .slave = &dra7xx_sata_hwmod,
2508 .clk = "l3_iclk_div",
2509 .addr = dra7xx_sata_addrs,
2510 .user = OCP_USER_MPU | OCP_USER_SDMA,
2511};
2512
2513static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
2514 {
2515 .pa_start = 0x4a0dd000,
2516 .pa_end = 0x4a0dd07f,
2517 .flags = ADDR_TYPE_RT
2518 },
2519 { }
2520};
2521
2522/* l4_cfg -> smartreflex_core */
2523static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
2524 .master = &dra7xx_l4_cfg_hwmod,
2525 .slave = &dra7xx_smartreflex_core_hwmod,
2526 .clk = "l4_root_clk_div",
2527 .addr = dra7xx_smartreflex_core_addrs,
2528 .user = OCP_USER_MPU | OCP_USER_SDMA,
2529};
2530
2531static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
2532 {
2533 .pa_start = 0x4a0d9000,
2534 .pa_end = 0x4a0d907f,
2535 .flags = ADDR_TYPE_RT
2536 },
2537 { }
2538};
2539
2540/* l4_cfg -> smartreflex_mpu */
2541static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
2542 .master = &dra7xx_l4_cfg_hwmod,
2543 .slave = &dra7xx_smartreflex_mpu_hwmod,
2544 .clk = "l4_root_clk_div",
2545 .addr = dra7xx_smartreflex_mpu_addrs,
2546 .user = OCP_USER_MPU | OCP_USER_SDMA,
2547};
2548
2549static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
2550 {
2551 .pa_start = 0x4a0f6000,
2552 .pa_end = 0x4a0f6fff,
2553 .flags = ADDR_TYPE_RT
2554 },
2555 { }
2556};
2557
2558/* l4_cfg -> spinlock */
2559static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
2560 .master = &dra7xx_l4_cfg_hwmod,
2561 .slave = &dra7xx_spinlock_hwmod,
2562 .clk = "l3_iclk_div",
2563 .addr = dra7xx_spinlock_addrs,
2564 .user = OCP_USER_MPU | OCP_USER_SDMA,
2565};
2566
2567/* l4_wkup -> timer1 */
2568static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
2569 .master = &dra7xx_l4_wkup_hwmod,
2570 .slave = &dra7xx_timer1_hwmod,
2571 .clk = "wkupaon_iclk_mux",
2572 .user = OCP_USER_MPU | OCP_USER_SDMA,
2573};
2574
2575/* l4_per1 -> timer2 */
2576static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
2577 .master = &dra7xx_l4_per1_hwmod,
2578 .slave = &dra7xx_timer2_hwmod,
2579 .clk = "l3_iclk_div",
2580 .user = OCP_USER_MPU | OCP_USER_SDMA,
2581};
2582
2583/* l4_per1 -> timer3 */
2584static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
2585 .master = &dra7xx_l4_per1_hwmod,
2586 .slave = &dra7xx_timer3_hwmod,
2587 .clk = "l3_iclk_div",
2588 .user = OCP_USER_MPU | OCP_USER_SDMA,
2589};
2590
2591/* l4_per1 -> timer4 */
2592static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
2593 .master = &dra7xx_l4_per1_hwmod,
2594 .slave = &dra7xx_timer4_hwmod,
2595 .clk = "l3_iclk_div",
2596 .user = OCP_USER_MPU | OCP_USER_SDMA,
2597};
2598
2599/* l4_per3 -> timer5 */
2600static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
2601 .master = &dra7xx_l4_per3_hwmod,
2602 .slave = &dra7xx_timer5_hwmod,
2603 .clk = "l3_iclk_div",
2604 .user = OCP_USER_MPU | OCP_USER_SDMA,
2605};
2606
2607/* l4_per3 -> timer6 */
2608static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
2609 .master = &dra7xx_l4_per3_hwmod,
2610 .slave = &dra7xx_timer6_hwmod,
2611 .clk = "l3_iclk_div",
2612 .user = OCP_USER_MPU | OCP_USER_SDMA,
2613};
2614
2615/* l4_per3 -> timer7 */
2616static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
2617 .master = &dra7xx_l4_per3_hwmod,
2618 .slave = &dra7xx_timer7_hwmod,
2619 .clk = "l3_iclk_div",
2620 .user = OCP_USER_MPU | OCP_USER_SDMA,
2621};
2622
2623/* l4_per3 -> timer8 */
2624static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
2625 .master = &dra7xx_l4_per3_hwmod,
2626 .slave = &dra7xx_timer8_hwmod,
2627 .clk = "l3_iclk_div",
2628 .user = OCP_USER_MPU | OCP_USER_SDMA,
2629};
2630
2631/* l4_per1 -> timer9 */
2632static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
2633 .master = &dra7xx_l4_per1_hwmod,
2634 .slave = &dra7xx_timer9_hwmod,
2635 .clk = "l3_iclk_div",
2636 .user = OCP_USER_MPU | OCP_USER_SDMA,
2637};
2638
2639/* l4_per1 -> timer10 */
2640static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
2641 .master = &dra7xx_l4_per1_hwmod,
2642 .slave = &dra7xx_timer10_hwmod,
2643 .clk = "l3_iclk_div",
2644 .user = OCP_USER_MPU | OCP_USER_SDMA,
2645};
2646
2647/* l4_per1 -> timer11 */
2648static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
2649 .master = &dra7xx_l4_per1_hwmod,
2650 .slave = &dra7xx_timer11_hwmod,
2651 .clk = "l3_iclk_div",
2652 .user = OCP_USER_MPU | OCP_USER_SDMA,
2653};
2654
2655/* l4_per1 -> uart1 */
2656static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
2657 .master = &dra7xx_l4_per1_hwmod,
2658 .slave = &dra7xx_uart1_hwmod,
2659 .clk = "l3_iclk_div",
2660 .user = OCP_USER_MPU | OCP_USER_SDMA,
2661};
2662
2663/* l4_per1 -> uart2 */
2664static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
2665 .master = &dra7xx_l4_per1_hwmod,
2666 .slave = &dra7xx_uart2_hwmod,
2667 .clk = "l3_iclk_div",
2668 .user = OCP_USER_MPU | OCP_USER_SDMA,
2669};
2670
2671/* l4_per1 -> uart3 */
2672static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
2673 .master = &dra7xx_l4_per1_hwmod,
2674 .slave = &dra7xx_uart3_hwmod,
2675 .clk = "l3_iclk_div",
2676 .user = OCP_USER_MPU | OCP_USER_SDMA,
2677};
2678
2679/* l4_per1 -> uart4 */
2680static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
2681 .master = &dra7xx_l4_per1_hwmod,
2682 .slave = &dra7xx_uart4_hwmod,
2683 .clk = "l3_iclk_div",
2684 .user = OCP_USER_MPU | OCP_USER_SDMA,
2685};
2686
2687/* l4_per1 -> uart5 */
2688static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
2689 .master = &dra7xx_l4_per1_hwmod,
2690 .slave = &dra7xx_uart5_hwmod,
2691 .clk = "l3_iclk_div",
2692 .user = OCP_USER_MPU | OCP_USER_SDMA,
2693};
2694
2695/* l4_per1 -> uart6 */
2696static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
2697 .master = &dra7xx_l4_per1_hwmod,
2698 .slave = &dra7xx_uart6_hwmod,
2699 .clk = "l3_iclk_div",
2700 .user = OCP_USER_MPU | OCP_USER_SDMA,
2701};
2702
2703/* l4_per3 -> usb_otg_ss1 */
2704static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
2705 .master = &dra7xx_l4_per3_hwmod,
2706 .slave = &dra7xx_usb_otg_ss1_hwmod,
2707 .clk = "dpll_core_h13x2_ck",
2708 .user = OCP_USER_MPU | OCP_USER_SDMA,
2709};
2710
2711/* l4_per3 -> usb_otg_ss2 */
2712static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
2713 .master = &dra7xx_l4_per3_hwmod,
2714 .slave = &dra7xx_usb_otg_ss2_hwmod,
2715 .clk = "dpll_core_h13x2_ck",
2716 .user = OCP_USER_MPU | OCP_USER_SDMA,
2717};
2718
2719/* l4_per3 -> usb_otg_ss3 */
2720static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
2721 .master = &dra7xx_l4_per3_hwmod,
2722 .slave = &dra7xx_usb_otg_ss3_hwmod,
2723 .clk = "dpll_core_h13x2_ck",
2724 .user = OCP_USER_MPU | OCP_USER_SDMA,
2725};
2726
2727/* l4_per3 -> usb_otg_ss4 */
2728static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
2729 .master = &dra7xx_l4_per3_hwmod,
2730 .slave = &dra7xx_usb_otg_ss4_hwmod,
2731 .clk = "dpll_core_h13x2_ck",
2732 .user = OCP_USER_MPU | OCP_USER_SDMA,
2733};
2734
2735/* l3_main_1 -> vcp1 */
2736static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
2737 .master = &dra7xx_l3_main_1_hwmod,
2738 .slave = &dra7xx_vcp1_hwmod,
2739 .clk = "l3_iclk_div",
2740 .user = OCP_USER_MPU | OCP_USER_SDMA,
2741};
2742
2743/* l4_per2 -> vcp1 */
2744static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
2745 .master = &dra7xx_l4_per2_hwmod,
2746 .slave = &dra7xx_vcp1_hwmod,
2747 .clk = "l3_iclk_div",
2748 .user = OCP_USER_MPU | OCP_USER_SDMA,
2749};
2750
2751/* l3_main_1 -> vcp2 */
2752static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
2753 .master = &dra7xx_l3_main_1_hwmod,
2754 .slave = &dra7xx_vcp2_hwmod,
2755 .clk = "l3_iclk_div",
2756 .user = OCP_USER_MPU | OCP_USER_SDMA,
2757};
2758
2759/* l4_per2 -> vcp2 */
2760static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
2761 .master = &dra7xx_l4_per2_hwmod,
2762 .slave = &dra7xx_vcp2_hwmod,
2763 .clk = "l3_iclk_div",
2764 .user = OCP_USER_MPU | OCP_USER_SDMA,
2765};
2766
2767/* l4_wkup -> wd_timer2 */
2768static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
2769 .master = &dra7xx_l4_wkup_hwmod,
2770 .slave = &dra7xx_wd_timer2_hwmod,
2771 .clk = "wkupaon_iclk_mux",
2772 .user = OCP_USER_MPU | OCP_USER_SDMA,
2773};
2774
2775static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
2776 &dra7xx_l3_main_2__l3_instr,
2777 &dra7xx_l4_cfg__l3_main_1,
2778 &dra7xx_mpu__l3_main_1,
2779 &dra7xx_l3_main_1__l3_main_2,
2780 &dra7xx_l4_cfg__l3_main_2,
2781 &dra7xx_l3_main_1__l4_cfg,
2782 &dra7xx_l3_main_1__l4_per1,
2783 &dra7xx_l3_main_1__l4_per2,
2784 &dra7xx_l3_main_1__l4_per3,
2785 &dra7xx_l3_main_1__l4_wkup,
2786 &dra7xx_l4_per2__atl,
2787 &dra7xx_l3_main_1__bb2d,
2788 &dra7xx_l4_wkup__counter_32k,
2789 &dra7xx_l4_wkup__ctrl_module_wkup,
2790 &dra7xx_l4_wkup__dcan1,
2791 &dra7xx_l4_per2__dcan2,
2792 &dra7xx_l4_cfg__dma_system,
2793 &dra7xx_l3_main_1__dss,
2794 &dra7xx_l3_main_1__dispc,
2795 &dra7xx_l3_main_1__hdmi,
2796 &dra7xx_l4_per1__elm,
2797 &dra7xx_l4_wkup__gpio1,
2798 &dra7xx_l4_per1__gpio2,
2799 &dra7xx_l4_per1__gpio3,
2800 &dra7xx_l4_per1__gpio4,
2801 &dra7xx_l4_per1__gpio5,
2802 &dra7xx_l4_per1__gpio6,
2803 &dra7xx_l4_per1__gpio7,
2804 &dra7xx_l4_per1__gpio8,
2805 &dra7xx_l3_main_1__gpmc,
2806 &dra7xx_l4_per1__hdq1w,
2807 &dra7xx_l4_per1__i2c1,
2808 &dra7xx_l4_per1__i2c2,
2809 &dra7xx_l4_per1__i2c3,
2810 &dra7xx_l4_per1__i2c4,
2811 &dra7xx_l4_per1__i2c5,
2812 &dra7xx_l4_per1__mcspi1,
2813 &dra7xx_l4_per1__mcspi2,
2814 &dra7xx_l4_per1__mcspi3,
2815 &dra7xx_l4_per1__mcspi4,
2816 &dra7xx_l4_per1__mmc1,
2817 &dra7xx_l4_per1__mmc2,
2818 &dra7xx_l4_per1__mmc3,
2819 &dra7xx_l4_per1__mmc4,
2820 &dra7xx_l4_cfg__mpu,
2821 &dra7xx_l4_cfg__ocp2scp1,
df0d0f11 2822 &dra7xx_l4_cfg__ocp2scp3,
8dd3eb71
KVA		 2823 &dra7xx_l3_main_1__pcie1,
2824 &dra7xx_l4_cfg__pcie1,
2825 &dra7xx_l3_main_1__pcie2,
2826 &dra7xx_l4_cfg__pcie2,
70c18ef7
KVA		 2827 &dra7xx_l4_cfg__pcie1_phy,
2828 &dra7xx_l4_cfg__pcie2_phy,
90020c7b
A		 2829 &dra7xx_l3_main_1__qspi,
2830 &dra7xx_l4_cfg__sata,
2831 &dra7xx_l4_cfg__smartreflex_core,
2832 &dra7xx_l4_cfg__smartreflex_mpu,
2833 &dra7xx_l4_cfg__spinlock,
2834 &dra7xx_l4_wkup__timer1,
2835 &dra7xx_l4_per1__timer2,
2836 &dra7xx_l4_per1__timer3,
2837 &dra7xx_l4_per1__timer4,
2838 &dra7xx_l4_per3__timer5,
2839 &dra7xx_l4_per3__timer6,
2840 &dra7xx_l4_per3__timer7,
2841 &dra7xx_l4_per3__timer8,
2842 &dra7xx_l4_per1__timer9,
2843 &dra7xx_l4_per1__timer10,
2844 &dra7xx_l4_per1__timer11,
2845 &dra7xx_l4_per1__uart1,
2846 &dra7xx_l4_per1__uart2,
2847 &dra7xx_l4_per1__uart3,
2848 &dra7xx_l4_per1__uart4,
2849 &dra7xx_l4_per1__uart5,
2850 &dra7xx_l4_per1__uart6,
2851 &dra7xx_l4_per3__usb_otg_ss1,
2852 &dra7xx_l4_per3__usb_otg_ss2,
2853 &dra7xx_l4_per3__usb_otg_ss3,
2854 &dra7xx_l4_per3__usb_otg_ss4,
2855 &dra7xx_l3_main_1__vcp1,
2856 &dra7xx_l4_per2__vcp1,
2857 &dra7xx_l3_main_1__vcp2,
2858 &dra7xx_l4_per2__vcp2,
2859 &dra7xx_l4_wkup__wd_timer2,
2860 NULL,
2861};
2862
2863int __init dra7xx_hwmod_init(void)
2864{
2865 omap_hwmod_init();
2866 return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
2867}
Linux kernel - Deliverables
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