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Linux 4.1-rc4
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_7xx_data.c
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90020c7b
A		 1/*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/io.h>
21#include <linux/platform_data/gpio-omap.h>
55143438 22#include <linux/platform_data/hsmmc-omap.h>
90020c7b
A		 23#include <linux/power/smartreflex.h>
24#include <linux/i2c-omap.h>
25
26#include <linux/omap-dma.h>
27#include <linux/platform_data/spi-omap2-mcspi.h>
28#include <linux/platform_data/asoc-ti-mcbsp.h>
29#include <plat/dmtimer.h>
30
31#include "omap_hwmod.h"
32#include "omap_hwmod_common_data.h"
33#include "cm1_7xx.h"
34#include "cm2_7xx.h"
35#include "prm7xx.h"
36#include "i2c.h"
90020c7b 37#include "wd_timer.h"
f7f7a29b 38#include "soc.h"
90020c7b
A		 39
40/* Base offset for all DRA7XX interrupts external to MPUSS */
41#define DRA7XX_IRQ_GIC_START 32
42
43/* Base offset for all DRA7XX dma requests */
44#define DRA7XX_DMA_REQ_START 1
45
46
47/*
48 * IP blocks
49 */
50
51/*
52 * 'l3' class
53 * instance(s): l3_instr, l3_main_1, l3_main_2
54 */
55static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
56 .name = "l3",
57};
58
59/* l3_instr */
60static struct omap_hwmod dra7xx_l3_instr_hwmod = {
61 .name = "l3_instr",
62 .class = &dra7xx_l3_hwmod_class,
63 .clkdm_name = "l3instr_clkdm",
64 .prcm = {
65 .omap4 = {
66 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
67 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
68 .modulemode = MODULEMODE_HWCTRL,
69 },
70 },
71};
72
73/* l3_main_1 */
74static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
75 .name = "l3_main_1",
76 .class = &dra7xx_l3_hwmod_class,
77 .clkdm_name = "l3main1_clkdm",
78 .prcm = {
79 .omap4 = {
80 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
81 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
82 },
83 },
84};
85
86/* l3_main_2 */
87static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
88 .name = "l3_main_2",
89 .class = &dra7xx_l3_hwmod_class,
90 .clkdm_name = "l3instr_clkdm",
91 .prcm = {
92 .omap4 = {
93 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
94 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
95 .modulemode = MODULEMODE_HWCTRL,
96 },
97 },
98};
99
100/*
101 * 'l4' class
102 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
103 */
104static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
105 .name = "l4",
106};
107
108/* l4_cfg */
109static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
110 .name = "l4_cfg",
111 .class = &dra7xx_l4_hwmod_class,
112 .clkdm_name = "l4cfg_clkdm",
113 .prcm = {
114 .omap4 = {
115 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
116 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
117 },
118 },
119};
120
121/* l4_per1 */
122static struct omap_hwmod dra7xx_l4_per1_hwmod = {
123 .name = "l4_per1",
124 .class = &dra7xx_l4_hwmod_class,
125 .clkdm_name = "l4per_clkdm",
126 .prcm = {
127 .omap4 = {
128 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
129 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
130 },
131 },
132};
133
134/* l4_per2 */
135static struct omap_hwmod dra7xx_l4_per2_hwmod = {
136 .name = "l4_per2",
137 .class = &dra7xx_l4_hwmod_class,
138 .clkdm_name = "l4per2_clkdm",
139 .prcm = {
140 .omap4 = {
141 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
142 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
143 },
144 },
145};
146
147/* l4_per3 */
148static struct omap_hwmod dra7xx_l4_per3_hwmod = {
149 .name = "l4_per3",
150 .class = &dra7xx_l4_hwmod_class,
151 .clkdm_name = "l4per3_clkdm",
152 .prcm = {
153 .omap4 = {
154 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
155 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
156 },
157 },
158};
159
160/* l4_wkup */
161static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
162 .name = "l4_wkup",
163 .class = &dra7xx_l4_hwmod_class,
164 .clkdm_name = "wkupaon_clkdm",
165 .prcm = {
166 .omap4 = {
167 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
168 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
169 },
170 },
171};
172
173/*
174 * 'atl' class
175 *
176 */
177
178static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
179 .name = "atl",
180};
181
182/* atl */
183static struct omap_hwmod dra7xx_atl_hwmod = {
184 .name = "atl",
185 .class = &dra7xx_atl_hwmod_class,
186 .clkdm_name = "atl_clkdm",
187 .main_clk = "atl_gfclk_mux",
188 .prcm = {
189 .omap4 = {
190 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
191 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
192 .modulemode = MODULEMODE_SWCTRL,
193 },
194 },
195};
196
197/*
198 * 'bb2d' class
199 *
200 */
201
202static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
203 .name = "bb2d",
204};
205
206/* bb2d */
207static struct omap_hwmod dra7xx_bb2d_hwmod = {
208 .name = "bb2d",
209 .class = &dra7xx_bb2d_hwmod_class,
210 .clkdm_name = "dss_clkdm",
211 .main_clk = "dpll_core_h24x2_ck",
212 .prcm = {
213 .omap4 = {
214 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
215 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
216 .modulemode = MODULEMODE_SWCTRL,
217 },
218 },
219};
220
221/*
222 * 'counter' class
223 *
224 */
225
226static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
227 .rev_offs = 0x0000,
228 .sysc_offs = 0x0010,
229 .sysc_flags = SYSC_HAS_SIDLEMODE,
230 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
231 SIDLE_SMART_WKUP),
232 .sysc_fields = &omap_hwmod_sysc_type1,
233};
234
235static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
236 .name = "counter",
237 .sysc = &dra7xx_counter_sysc,
238};
239
240/* counter_32k */
241static struct omap_hwmod dra7xx_counter_32k_hwmod = {
242 .name = "counter_32k",
243 .class = &dra7xx_counter_hwmod_class,
244 .clkdm_name = "wkupaon_clkdm",
245 .flags = HWMOD_SWSUP_SIDLE,
246 .main_clk = "wkupaon_iclk_mux",
247 .prcm = {
248 .omap4 = {
249 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
250 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
251 },
252 },
253};
254
255/*
256 * 'ctrl_module' class
257 *
258 */
259
260static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
261 .name = "ctrl_module",
262};
263
264/* ctrl_module_wkup */
265static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
266 .name = "ctrl_module_wkup",
267 .class = &dra7xx_ctrl_module_hwmod_class,
268 .clkdm_name = "wkupaon_clkdm",
269 .prcm = {
270 .omap4 = {
271 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
272 },
273 },
274};
275
077c42f7
M		 276/*
277 * 'gmac' class
278 * cpsw/gmac sub system
279 */
280static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
281 .rev_offs = 0x0,
282 .sysc_offs = 0x8,
283 .syss_offs = 0x4,
284 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
285 SYSS_HAS_RESET_STATUS),
286 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
287 MSTANDBY_NO),
288 .sysc_fields = &omap_hwmod_sysc_type3,
289};
290
291static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
292 .name = "gmac",
293 .sysc = &dra7xx_gmac_sysc,
294};
295
296static struct omap_hwmod dra7xx_gmac_hwmod = {
297 .name = "gmac",
298 .class = &dra7xx_gmac_hwmod_class,
299 .clkdm_name = "gmac_clkdm",
300 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
301 .main_clk = "dpll_gmac_ck",
302 .mpu_rt_idx = 1,
303 .prcm = {
304 .omap4 = {
305 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
306 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
307 .modulemode = MODULEMODE_SWCTRL,
308 },
309 },
310};
311
312/*
313 * 'mdio' class
314 */
315static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
316 .name = "davinci_mdio",
317};
318
319static struct omap_hwmod dra7xx_mdio_hwmod = {
320 .name = "davinci_mdio",
321 .class = &dra7xx_mdio_hwmod_class,
322 .clkdm_name = "gmac_clkdm",
323 .main_clk = "dpll_gmac_ck",
324};
325
90020c7b
A		 326/*
327 * 'dcan' class
328 *
329 */
330
331static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
332 .name = "dcan",
333};
334
335/* dcan1 */
336static struct omap_hwmod dra7xx_dcan1_hwmod = {
337 .name = "dcan1",
338 .class = &dra7xx_dcan_hwmod_class,
339 .clkdm_name = "wkupaon_clkdm",
340 .main_clk = "dcan1_sys_clk_mux",
341 .prcm = {
342 .omap4 = {
343 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
344 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
345 .modulemode = MODULEMODE_SWCTRL,
346 },
347 },
348};
349
350/* dcan2 */
351static struct omap_hwmod dra7xx_dcan2_hwmod = {
352 .name = "dcan2",
353 .class = &dra7xx_dcan_hwmod_class,
354 .clkdm_name = "l4per2_clkdm",
355 .main_clk = "sys_clkin1",
356 .prcm = {
357 .omap4 = {
358 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
359 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
360 .modulemode = MODULEMODE_SWCTRL,
361 },
362 },
363};
364
365/*
366 * 'dma' class
367 *
368 */
369
370static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
371 .rev_offs = 0x0000,
372 .sysc_offs = 0x002c,
373 .syss_offs = 0x0028,
374 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
375 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
376 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
377 SYSS_HAS_RESET_STATUS),
378 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
379 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
380 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
381 .sysc_fields = &omap_hwmod_sysc_type1,
382};
383
384static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
385 .name = "dma",
386 .sysc = &dra7xx_dma_sysc,
387};
388
389/* dma dev_attr */
390static struct omap_dma_dev_attr dma_dev_attr = {
391 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
392 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
393 .lch_count = 32,
394};
395
396/* dma_system */
90020c7b
A		 397static struct omap_hwmod dra7xx_dma_system_hwmod = {
398 .name = "dma_system",
399 .class = &dra7xx_dma_hwmod_class,
400 .clkdm_name = "dma_clkdm",
90020c7b
A		 401 .main_clk = "l3_iclk_div",
402 .prcm = {
403 .omap4 = {
404 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
405 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
406 },
407 },
408 .dev_attr = &dma_dev_attr,
409};
410
411/*
412 * 'dss' class
413 *
414 */
415
416static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
417 .rev_offs = 0x0000,
418 .syss_offs = 0x0014,
419 .sysc_flags = SYSS_HAS_RESET_STATUS,
420};
421
422static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
423 .name = "dss",
424 .sysc = &dra7xx_dss_sysc,
425 .reset = omap_dss_reset,
426};
427
428/* dss */
429static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
430 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
431 { .dma_req = -1 }
432};
433
434static struct omap_hwmod_opt_clk dss_opt_clks[] = {
435 { .role = "dss_clk", .clk = "dss_dss_clk" },
436 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
437 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
438 { .role = "video2_clk", .clk = "dss_video2_clk" },
439 { .role = "video1_clk", .clk = "dss_video1_clk" },
440 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
441};
442
443static struct omap_hwmod dra7xx_dss_hwmod = {
444 .name = "dss_core",
445 .class = &dra7xx_dss_hwmod_class,
446 .clkdm_name = "dss_clkdm",
447 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
448 .sdma_reqs = dra7xx_dss_sdma_reqs,
449 .main_clk = "dss_dss_clk",
450 .prcm = {
451 .omap4 = {
452 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
453 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
454 .modulemode = MODULEMODE_SWCTRL,
455 },
456 },
457 .opt_clks = dss_opt_clks,
458 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
459};
460
461/*
462 * 'dispc' class
463 * display controller
464 */
465
466static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
467 .rev_offs = 0x0000,
468 .sysc_offs = 0x0010,
469 .syss_offs = 0x0014,
470 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
471 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
472 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
473 SYSS_HAS_RESET_STATUS),
474 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
475 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
476 .sysc_fields = &omap_hwmod_sysc_type1,
477};
478
479static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
480 .name = "dispc",
481 .sysc = &dra7xx_dispc_sysc,
482};
483
484/* dss_dispc */
485/* dss_dispc dev_attr */
486static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
487 .has_framedonetv_irq = 1,
488 .manager_count = 4,
489};
490
491static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
492 .name = "dss_dispc",
493 .class = &dra7xx_dispc_hwmod_class,
494 .clkdm_name = "dss_clkdm",
495 .main_clk = "dss_dss_clk",
496 .prcm = {
497 .omap4 = {
498 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
499 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
500 },
501 },
502 .dev_attr = &dss_dispc_dev_attr,
503};
504
505/*
506 * 'hdmi' class
507 * hdmi controller
508 */
509
510static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
511 .rev_offs = 0x0000,
512 .sysc_offs = 0x0010,
513 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
514 SYSC_HAS_SOFTRESET),
515 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
516 SIDLE_SMART_WKUP),
517 .sysc_fields = &omap_hwmod_sysc_type2,
518};
519
520static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
521 .name = "hdmi",
522 .sysc = &dra7xx_hdmi_sysc,
523};
524
525/* dss_hdmi */
526
527static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
528 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
529};
530
531static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
532 .name = "dss_hdmi",
533 .class = &dra7xx_hdmi_hwmod_class,
534 .clkdm_name = "dss_clkdm",
535 .main_clk = "dss_48mhz_clk",
536 .prcm = {
537 .omap4 = {
538 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
539 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
540 },
541 },
542 .opt_clks = dss_hdmi_opt_clks,
543 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
544};
545
546/*
547 * 'elm' class
548 *
549 */
550
551static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
552 .rev_offs = 0x0000,
553 .sysc_offs = 0x0010,
554 .syss_offs = 0x0014,
555 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
556 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
557 SYSS_HAS_RESET_STATUS),
558 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
559 SIDLE_SMART_WKUP),
560 .sysc_fields = &omap_hwmod_sysc_type1,
561};
562
563static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
564 .name = "elm",
565 .sysc = &dra7xx_elm_sysc,
566};
567
568/* elm */
569
570static struct omap_hwmod dra7xx_elm_hwmod = {
571 .name = "elm",
572 .class = &dra7xx_elm_hwmod_class,
573 .clkdm_name = "l4per_clkdm",
574 .main_clk = "l3_iclk_div",
575 .prcm = {
576 .omap4 = {
577 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
578 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
579 },
580 },
581};
582
583/*
584 * 'gpio' class
585 *
586 */
587
588static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
589 .rev_offs = 0x0000,
590 .sysc_offs = 0x0010,
591 .syss_offs = 0x0114,
592 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
593 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
594 SYSS_HAS_RESET_STATUS),
595 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
596 SIDLE_SMART_WKUP),
597 .sysc_fields = &omap_hwmod_sysc_type1,
598};
599
600static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
601 .name = "gpio",
602 .sysc = &dra7xx_gpio_sysc,
603 .rev = 2,
604};
605
606/* gpio dev_attr */
607static struct omap_gpio_dev_attr gpio_dev_attr = {
608 .bank_width = 32,
609 .dbck_flag = true,
610};
611
612/* gpio1 */
613static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
614 { .role = "dbclk", .clk = "gpio1_dbclk" },
615};
616
617static struct omap_hwmod dra7xx_gpio1_hwmod = {
618 .name = "gpio1",
619 .class = &dra7xx_gpio_hwmod_class,
620 .clkdm_name = "wkupaon_clkdm",
621 .main_clk = "wkupaon_iclk_mux",
622 .prcm = {
623 .omap4 = {
624 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
625 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
626 .modulemode = MODULEMODE_HWCTRL,
627 },
628 },
629 .opt_clks = gpio1_opt_clks,
630 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
631 .dev_attr = &gpio_dev_attr,
632};
633
634/* gpio2 */
635static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
636 { .role = "dbclk", .clk = "gpio2_dbclk" },
637};
638
639static struct omap_hwmod dra7xx_gpio2_hwmod = {
640 .name = "gpio2",
641 .class = &dra7xx_gpio_hwmod_class,
642 .clkdm_name = "l4per_clkdm",
643 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
644 .main_clk = "l3_iclk_div",
645 .prcm = {
646 .omap4 = {
647 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
648 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
649 .modulemode = MODULEMODE_HWCTRL,
650 },
651 },
652 .opt_clks = gpio2_opt_clks,
653 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
654 .dev_attr = &gpio_dev_attr,
655};
656
657/* gpio3 */
658static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
659 { .role = "dbclk", .clk = "gpio3_dbclk" },
660};
661
662static struct omap_hwmod dra7xx_gpio3_hwmod = {
663 .name = "gpio3",
664 .class = &dra7xx_gpio_hwmod_class,
665 .clkdm_name = "l4per_clkdm",
666 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
667 .main_clk = "l3_iclk_div",
668 .prcm = {
669 .omap4 = {
670 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
671 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
672 .modulemode = MODULEMODE_HWCTRL,
673 },
674 },
675 .opt_clks = gpio3_opt_clks,
676 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
677 .dev_attr = &gpio_dev_attr,
678};
679
680/* gpio4 */
681static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
682 { .role = "dbclk", .clk = "gpio4_dbclk" },
683};
684
685static struct omap_hwmod dra7xx_gpio4_hwmod = {
686 .name = "gpio4",
687 .class = &dra7xx_gpio_hwmod_class,
688 .clkdm_name = "l4per_clkdm",
689 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
690 .main_clk = "l3_iclk_div",
691 .prcm = {
692 .omap4 = {
693 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
694 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
695 .modulemode = MODULEMODE_HWCTRL,
696 },
697 },
698 .opt_clks = gpio4_opt_clks,
699 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
700 .dev_attr = &gpio_dev_attr,
701};
702
703/* gpio5 */
704static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
705 { .role = "dbclk", .clk = "gpio5_dbclk" },
706};
707
708static struct omap_hwmod dra7xx_gpio5_hwmod = {
709 .name = "gpio5",
710 .class = &dra7xx_gpio_hwmod_class,
711 .clkdm_name = "l4per_clkdm",
712 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
713 .main_clk = "l3_iclk_div",
714 .prcm = {
715 .omap4 = {
716 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
717 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
718 .modulemode = MODULEMODE_HWCTRL,
719 },
720 },
721 .opt_clks = gpio5_opt_clks,
722 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
723 .dev_attr = &gpio_dev_attr,
724};
725
726/* gpio6 */
727static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
728 { .role = "dbclk", .clk = "gpio6_dbclk" },
729};
730
731static struct omap_hwmod dra7xx_gpio6_hwmod = {
732 .name = "gpio6",
733 .class = &dra7xx_gpio_hwmod_class,
734 .clkdm_name = "l4per_clkdm",
735 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
736 .main_clk = "l3_iclk_div",
737 .prcm = {
738 .omap4 = {
739 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
740 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
741 .modulemode = MODULEMODE_HWCTRL,
742 },
743 },
744 .opt_clks = gpio6_opt_clks,
745 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
746 .dev_attr = &gpio_dev_attr,
747};
748
749/* gpio7 */
750static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
751 { .role = "dbclk", .clk = "gpio7_dbclk" },
752};
753
754static struct omap_hwmod dra7xx_gpio7_hwmod = {
755 .name = "gpio7",
756 .class = &dra7xx_gpio_hwmod_class,
757 .clkdm_name = "l4per_clkdm",
758 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
759 .main_clk = "l3_iclk_div",
760 .prcm = {
761 .omap4 = {
762 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
763 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
764 .modulemode = MODULEMODE_HWCTRL,
765 },
766 },
767 .opt_clks = gpio7_opt_clks,
768 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
769 .dev_attr = &gpio_dev_attr,
770};
771
772/* gpio8 */
773static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
774 { .role = "dbclk", .clk = "gpio8_dbclk" },
775};
776
777static struct omap_hwmod dra7xx_gpio8_hwmod = {
778 .name = "gpio8",
779 .class = &dra7xx_gpio_hwmod_class,
780 .clkdm_name = "l4per_clkdm",
781 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
782 .main_clk = "l3_iclk_div",
783 .prcm = {
784 .omap4 = {
785 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
786 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
787 .modulemode = MODULEMODE_HWCTRL,
788 },
789 },
790 .opt_clks = gpio8_opt_clks,
791 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
792 .dev_attr = &gpio_dev_attr,
793};
794
795/*
796 * 'gpmc' class
797 *
798 */
799
800static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
801 .rev_offs = 0x0000,
802 .sysc_offs = 0x0010,
803 .syss_offs = 0x0014,
804 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
805 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
806 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
807 SIDLE_SMART_WKUP),
808 .sysc_fields = &omap_hwmod_sysc_type1,
809};
810
811static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
812 .name = "gpmc",
813 .sysc = &dra7xx_gpmc_sysc,
814};
815
816/* gpmc */
817
818static struct omap_hwmod dra7xx_gpmc_hwmod = {
819 .name = "gpmc",
820 .class = &dra7xx_gpmc_hwmod_class,
821 .clkdm_name = "l3main1_clkdm",
556708fe
K		 822 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
823 HWMOD_SWSUP_SIDLE),
90020c7b
A		 824 .main_clk = "l3_iclk_div",
825 .prcm = {
826 .omap4 = {
827 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
828 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
829 .modulemode = MODULEMODE_HWCTRL,
830 },
831 },
832};
833
834/*
835 * 'hdq1w' class
836 *
837 */
838
839static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
840 .rev_offs = 0x0000,
841 .sysc_offs = 0x0014,
842 .syss_offs = 0x0018,
843 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
844 SYSS_HAS_RESET_STATUS),
845 .sysc_fields = &omap_hwmod_sysc_type1,
846};
847
848static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
849 .name = "hdq1w",
850 .sysc = &dra7xx_hdq1w_sysc,
851};
852
853/* hdq1w */
854
855static struct omap_hwmod dra7xx_hdq1w_hwmod = {
856 .name = "hdq1w",
857 .class = &dra7xx_hdq1w_hwmod_class,
858 .clkdm_name = "l4per_clkdm",
859 .flags = HWMOD_INIT_NO_RESET,
860 .main_clk = "func_12m_fclk",
861 .prcm = {
862 .omap4 = {
863 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
864 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
865 .modulemode = MODULEMODE_SWCTRL,
866 },
867 },
868};
869
870/*
871 * 'i2c' class
872 *
873 */
874
875static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
876 .sysc_offs = 0x0010,
877 .syss_offs = 0x0090,
878 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
879 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
880 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
881 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
882 SIDLE_SMART_WKUP),
883 .clockact = CLOCKACT_TEST_ICLK,
884 .sysc_fields = &omap_hwmod_sysc_type1,
885};
886
887static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
888 .name = "i2c",
889 .sysc = &dra7xx_i2c_sysc,
890 .reset = &omap_i2c_reset,
891 .rev = OMAP_I2C_IP_VERSION_2,
892};
893
894/* i2c dev_attr */
895static struct omap_i2c_dev_attr i2c_dev_attr = {
896 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
897};
898
899/* i2c1 */
900static struct omap_hwmod dra7xx_i2c1_hwmod = {
901 .name = "i2c1",
902 .class = &dra7xx_i2c_hwmod_class,
903 .clkdm_name = "l4per_clkdm",
904 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
905 .main_clk = "func_96m_fclk",
906 .prcm = {
907 .omap4 = {
908 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
909 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
910 .modulemode = MODULEMODE_SWCTRL,
911 },
912 },
913 .dev_attr = &i2c_dev_attr,
914};
915
916/* i2c2 */
917static struct omap_hwmod dra7xx_i2c2_hwmod = {
918 .name = "i2c2",
919 .class = &dra7xx_i2c_hwmod_class,
920 .clkdm_name = "l4per_clkdm",
921 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
922 .main_clk = "func_96m_fclk",
923 .prcm = {
924 .omap4 = {
925 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
926 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
927 .modulemode = MODULEMODE_SWCTRL,
928 },
929 },
930 .dev_attr = &i2c_dev_attr,
931};
932
933/* i2c3 */
934static struct omap_hwmod dra7xx_i2c3_hwmod = {
935 .name = "i2c3",
936 .class = &dra7xx_i2c_hwmod_class,
937 .clkdm_name = "l4per_clkdm",
938 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
939 .main_clk = "func_96m_fclk",
940 .prcm = {
941 .omap4 = {
942 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
943 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
944 .modulemode = MODULEMODE_SWCTRL,
945 },
946 },
947 .dev_attr = &i2c_dev_attr,
948};
949
950/* i2c4 */
951static struct omap_hwmod dra7xx_i2c4_hwmod = {
952 .name = "i2c4",
953 .class = &dra7xx_i2c_hwmod_class,
954 .clkdm_name = "l4per_clkdm",
955 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
956 .main_clk = "func_96m_fclk",
957 .prcm = {
958 .omap4 = {
959 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
960 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
961 .modulemode = MODULEMODE_SWCTRL,
962 },
963 },
964 .dev_attr = &i2c_dev_attr,
965};
966
967/* i2c5 */
968static struct omap_hwmod dra7xx_i2c5_hwmod = {
969 .name = "i2c5",
970 .class = &dra7xx_i2c_hwmod_class,
971 .clkdm_name = "ipu_clkdm",
972 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
973 .main_clk = "func_96m_fclk",
974 .prcm = {
975 .omap4 = {
976 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
977 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
978 .modulemode = MODULEMODE_SWCTRL,
979 },
980 },
981 .dev_attr = &i2c_dev_attr,
982};
983
067395d4
SA		 984/*
985 * 'mailbox' class
986 *
987 */
988
989static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
990 .rev_offs = 0x0000,
991 .sysc_offs = 0x0010,
992 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
993 SYSC_HAS_SOFTRESET),
994 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
995 .sysc_fields = &omap_hwmod_sysc_type2,
996};
997
998static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
999 .name = "mailbox",
1000 .sysc = &dra7xx_mailbox_sysc,
1001};
1002
1003/* mailbox1 */
1004static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1005 .name = "mailbox1",
1006 .class = &dra7xx_mailbox_hwmod_class,
1007 .clkdm_name = "l4cfg_clkdm",
1008 .prcm = {
1009 .omap4 = {
1010 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1011 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1012 },
1013 },
1014};
1015
1016/* mailbox2 */
1017static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1018 .name = "mailbox2",
1019 .class = &dra7xx_mailbox_hwmod_class,
1020 .clkdm_name = "l4cfg_clkdm",
1021 .prcm = {
1022 .omap4 = {
1023 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1024 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1025 },
1026 },
1027};
1028
1029/* mailbox3 */
1030static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1031 .name = "mailbox3",
1032 .class = &dra7xx_mailbox_hwmod_class,
1033 .clkdm_name = "l4cfg_clkdm",
1034 .prcm = {
1035 .omap4 = {
1036 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1037 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1038 },
1039 },
1040};
1041
1042/* mailbox4 */
1043static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1044 .name = "mailbox4",
1045 .class = &dra7xx_mailbox_hwmod_class,
1046 .clkdm_name = "l4cfg_clkdm",
1047 .prcm = {
1048 .omap4 = {
1049 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1050 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1051 },
1052 },
1053};
1054
1055/* mailbox5 */
1056static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1057 .name = "mailbox5",
1058 .class = &dra7xx_mailbox_hwmod_class,
1059 .clkdm_name = "l4cfg_clkdm",
1060 .prcm = {
1061 .omap4 = {
1062 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1063 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1064 },
1065 },
1066};
1067
1068/* mailbox6 */
1069static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1070 .name = "mailbox6",
1071 .class = &dra7xx_mailbox_hwmod_class,
1072 .clkdm_name = "l4cfg_clkdm",
1073 .prcm = {
1074 .omap4 = {
1075 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1076 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1077 },
1078 },
1079};
1080
1081/* mailbox7 */
1082static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1083 .name = "mailbox7",
1084 .class = &dra7xx_mailbox_hwmod_class,
1085 .clkdm_name = "l4cfg_clkdm",
1086 .prcm = {
1087 .omap4 = {
1088 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1089 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1090 },
1091 },
1092};
1093
1094/* mailbox8 */
1095static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1096 .name = "mailbox8",
1097 .class = &dra7xx_mailbox_hwmod_class,
1098 .clkdm_name = "l4cfg_clkdm",
1099 .prcm = {
1100 .omap4 = {
1101 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1102 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1103 },
1104 },
1105};
1106
1107/* mailbox9 */
1108static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1109 .name = "mailbox9",
1110 .class = &dra7xx_mailbox_hwmod_class,
1111 .clkdm_name = "l4cfg_clkdm",
1112 .prcm = {
1113 .omap4 = {
1114 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1115 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1116 },
1117 },
1118};
1119
1120/* mailbox10 */
1121static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1122 .name = "mailbox10",
1123 .class = &dra7xx_mailbox_hwmod_class,
1124 .clkdm_name = "l4cfg_clkdm",
1125 .prcm = {
1126 .omap4 = {
1127 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1128 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1129 },
1130 },
1131};
1132
1133/* mailbox11 */
1134static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1135 .name = "mailbox11",
1136 .class = &dra7xx_mailbox_hwmod_class,
1137 .clkdm_name = "l4cfg_clkdm",
1138 .prcm = {
1139 .omap4 = {
1140 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1141 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1142 },
1143 },
1144};
1145
1146/* mailbox12 */
1147static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1148 .name = "mailbox12",
1149 .class = &dra7xx_mailbox_hwmod_class,
1150 .clkdm_name = "l4cfg_clkdm",
1151 .prcm = {
1152 .omap4 = {
1153 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1154 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1155 },
1156 },
1157};
1158
1159/* mailbox13 */
1160static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1161 .name = "mailbox13",
1162 .class = &dra7xx_mailbox_hwmod_class,
1163 .clkdm_name = "l4cfg_clkdm",
1164 .prcm = {
1165 .omap4 = {
1166 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1167 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1168 },
1169 },
1170};
1171
90020c7b
A		 1172/*
1173 * 'mcspi' class
1174 *
1175 */
1176
1177static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1178 .rev_offs = 0x0000,
1179 .sysc_offs = 0x0010,
1180 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1181 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1182 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1183 SIDLE_SMART_WKUP),
1184 .sysc_fields = &omap_hwmod_sysc_type2,
1185};
1186
1187static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1188 .name = "mcspi",
1189 .sysc = &dra7xx_mcspi_sysc,
1190 .rev = OMAP4_MCSPI_REV,
1191};
1192
1193/* mcspi1 */
1194/* mcspi1 dev_attr */
1195static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1196 .num_chipselect = 4,
1197};
1198
1199static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1200 .name = "mcspi1",
1201 .class = &dra7xx_mcspi_hwmod_class,
1202 .clkdm_name = "l4per_clkdm",
1203 .main_clk = "func_48m_fclk",
1204 .prcm = {
1205 .omap4 = {
1206 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1207 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1208 .modulemode = MODULEMODE_SWCTRL,
1209 },
1210 },
1211 .dev_attr = &mcspi1_dev_attr,
1212};
1213
1214/* mcspi2 */
1215/* mcspi2 dev_attr */
1216static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1217 .num_chipselect = 2,
1218};
1219
1220static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1221 .name = "mcspi2",
1222 .class = &dra7xx_mcspi_hwmod_class,
1223 .clkdm_name = "l4per_clkdm",
1224 .main_clk = "func_48m_fclk",
1225 .prcm = {
1226 .omap4 = {
1227 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1228 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1229 .modulemode = MODULEMODE_SWCTRL,
1230 },
1231 },
1232 .dev_attr = &mcspi2_dev_attr,
1233};
1234
1235/* mcspi3 */
1236/* mcspi3 dev_attr */
1237static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1238 .num_chipselect = 2,
1239};
1240
1241static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1242 .name = "mcspi3",
1243 .class = &dra7xx_mcspi_hwmod_class,
1244 .clkdm_name = "l4per_clkdm",
1245 .main_clk = "func_48m_fclk",
1246 .prcm = {
1247 .omap4 = {
1248 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1249 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1250 .modulemode = MODULEMODE_SWCTRL,
1251 },
1252 },
1253 .dev_attr = &mcspi3_dev_attr,
1254};
1255
1256/* mcspi4 */
1257/* mcspi4 dev_attr */
1258static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1259 .num_chipselect = 1,
1260};
1261
1262static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1263 .name = "mcspi4",
1264 .class = &dra7xx_mcspi_hwmod_class,
1265 .clkdm_name = "l4per_clkdm",
1266 .main_clk = "func_48m_fclk",
1267 .prcm = {
1268 .omap4 = {
1269 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1270 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1271 .modulemode = MODULEMODE_SWCTRL,
1272 },
1273 },
1274 .dev_attr = &mcspi4_dev_attr,
1275};
1276
1277/*
1278 * 'mmc' class
1279 *
1280 */
1281
1282static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1283 .rev_offs = 0x0000,
1284 .sysc_offs = 0x0010,
1285 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1286 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1287 SYSC_HAS_SOFTRESET),
1288 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1289 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1290 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1291 .sysc_fields = &omap_hwmod_sysc_type2,
1292};
1293
1294static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1295 .name = "mmc",
1296 .sysc = &dra7xx_mmc_sysc,
1297};
1298
1299/* mmc1 */
1300static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1301 { .role = "clk32k", .clk = "mmc1_clk32k" },
1302};
1303
1304/* mmc1 dev_attr */
55143438 1305static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
90020c7b
A		 1306 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1307};
1308
1309static struct omap_hwmod dra7xx_mmc1_hwmod = {
1310 .name = "mmc1",
1311 .class = &dra7xx_mmc_hwmod_class,
1312 .clkdm_name = "l3init_clkdm",
1313 .main_clk = "mmc1_fclk_div",
1314 .prcm = {
1315 .omap4 = {
1316 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1317 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1318 .modulemode = MODULEMODE_SWCTRL,
1319 },
1320 },
1321 .opt_clks = mmc1_opt_clks,
1322 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1323 .dev_attr = &mmc1_dev_attr,
1324};
1325
1326/* mmc2 */
1327static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1328 { .role = "clk32k", .clk = "mmc2_clk32k" },
1329};
1330
1331static struct omap_hwmod dra7xx_mmc2_hwmod = {
1332 .name = "mmc2",
1333 .class = &dra7xx_mmc_hwmod_class,
1334 .clkdm_name = "l3init_clkdm",
1335 .main_clk = "mmc2_fclk_div",
1336 .prcm = {
1337 .omap4 = {
1338 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1339 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1340 .modulemode = MODULEMODE_SWCTRL,
1341 },
1342 },
1343 .opt_clks = mmc2_opt_clks,
1344 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1345};
1346
1347/* mmc3 */
1348static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1349 { .role = "clk32k", .clk = "mmc3_clk32k" },
1350};
1351
1352static struct omap_hwmod dra7xx_mmc3_hwmod = {
1353 .name = "mmc3",
1354 .class = &dra7xx_mmc_hwmod_class,
1355 .clkdm_name = "l4per_clkdm",
1356 .main_clk = "mmc3_gfclk_div",
1357 .prcm = {
1358 .omap4 = {
1359 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1360 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1361 .modulemode = MODULEMODE_SWCTRL,
1362 },
1363 },
1364 .opt_clks = mmc3_opt_clks,
1365 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1366};
1367
1368/* mmc4 */
1369static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1370 { .role = "clk32k", .clk = "mmc4_clk32k" },
1371};
1372
1373static struct omap_hwmod dra7xx_mmc4_hwmod = {
1374 .name = "mmc4",
1375 .class = &dra7xx_mmc_hwmod_class,
1376 .clkdm_name = "l4per_clkdm",
1377 .main_clk = "mmc4_gfclk_div",
1378 .prcm = {
1379 .omap4 = {
1380 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1381 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1382 .modulemode = MODULEMODE_SWCTRL,
1383 },
1384 },
1385 .opt_clks = mmc4_opt_clks,
1386 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1387};
1388
1389/*
1390 * 'mpu' class
1391 *
1392 */
1393
1394static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1395 .name = "mpu",
1396};
1397
1398/* mpu */
1399static struct omap_hwmod dra7xx_mpu_hwmod = {
1400 .name = "mpu",
1401 .class = &dra7xx_mpu_hwmod_class,
1402 .clkdm_name = "mpu_clkdm",
1403 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1404 .main_clk = "dpll_mpu_m2_ck",
1405 .prcm = {
1406 .omap4 = {
1407 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1408 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1409 },
1410 },
1411};
1412
1413/*
1414 * 'ocp2scp' class
1415 *
1416 */
1417
1418static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1419 .rev_offs = 0x0000,
1420 .sysc_offs = 0x0010,
1421 .syss_offs = 0x0014,
1422 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1423 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1424 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1425 SIDLE_SMART_WKUP),
1426 .sysc_fields = &omap_hwmod_sysc_type1,
1427};
1428
1429static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1430 .name = "ocp2scp",
1431 .sysc = &dra7xx_ocp2scp_sysc,
1432};
1433
1434/* ocp2scp1 */
1435static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1436 .name = "ocp2scp1",
1437 .class = &dra7xx_ocp2scp_hwmod_class,
1438 .clkdm_name = "l3init_clkdm",
1439 .main_clk = "l4_root_clk_div",
1440 .prcm = {
1441 .omap4 = {
1442 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1443 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1444 .modulemode = MODULEMODE_HWCTRL,
1445 },
1446 },
1447};
1448
df0d0f11
RQ		 1449/* ocp2scp3 */
1450static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1451 .name = "ocp2scp3",
1452 .class = &dra7xx_ocp2scp_hwmod_class,
1453 .clkdm_name = "l3init_clkdm",
1454 .main_clk = "l4_root_clk_div",
1455 .prcm = {
1456 .omap4 = {
1457 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1458 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1459 .modulemode = MODULEMODE_HWCTRL,
1460 },
1461 },
1462};
1463
8dd3eb71
KVA		 1464/*
1465 * 'PCIE' class
1466 *
1467 */
1468
0717103e 1469static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
8dd3eb71
KVA		 1470 .name = "pcie",
1471};
1472
1473/* pcie1 */
0717103e 1474static struct omap_hwmod dra7xx_pciess1_hwmod = {
8dd3eb71 1475 .name = "pcie1",
0717103e 1476 .class = &dra7xx_pciess_hwmod_class,
8dd3eb71
KVA		 1477 .clkdm_name = "pcie_clkdm",
1478 .main_clk = "l4_root_clk_div",
70c18ef7
KVA		 1479 .prcm = {
1480 .omap4 = {
1481 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1482 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1483 .modulemode = MODULEMODE_SWCTRL,
1484 },
1485 },
1486};
1487
0717103e
KVA		 1488/* pcie2 */
1489static struct omap_hwmod dra7xx_pciess2_hwmod = {
1490 .name = "pcie2",
1491 .class = &dra7xx_pciess_hwmod_class,
1492 .clkdm_name = "pcie_clkdm",
70c18ef7
KVA		 1493 .main_clk = "l4_root_clk_div",
1494 .prcm = {
1495 .omap4 = {
1496 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1497 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1498 .modulemode = MODULEMODE_SWCTRL,
1499 },
1500 },
1501};
1502
90020c7b
A		 1503/*
1504 * 'qspi' class
1505 *
1506 */
1507
1508static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1509 .sysc_offs = 0x0010,
1510 .sysc_flags = SYSC_HAS_SIDLEMODE,
1511 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1512 SIDLE_SMART_WKUP),
1513 .sysc_fields = &omap_hwmod_sysc_type2,
1514};
1515
1516static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1517 .name = "qspi",
1518 .sysc = &dra7xx_qspi_sysc,
1519};
1520
1521/* qspi */
1522static struct omap_hwmod dra7xx_qspi_hwmod = {
1523 .name = "qspi",
1524 .class = &dra7xx_qspi_hwmod_class,
1525 .clkdm_name = "l4per2_clkdm",
1526 .main_clk = "qspi_gfclk_div",
1527 .prcm = {
1528 .omap4 = {
1529 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1530 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1531 .modulemode = MODULEMODE_SWCTRL,
1532 },
1533 },
1534};
1535
c913c8a1
LV		 1536/*
1537 * 'rtcss' class
1538 *
1539 */
1540static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1541 .sysc_offs = 0x0078,
1542 .sysc_flags = SYSC_HAS_SIDLEMODE,
1543 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1544 SIDLE_SMART_WKUP),
1545 .sysc_fields = &omap_hwmod_sysc_type3,
1546};
1547
1548static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1549 .name = "rtcss",
1550 .sysc = &dra7xx_rtcss_sysc,
1551};
1552
1553/* rtcss */
1554static struct omap_hwmod dra7xx_rtcss_hwmod = {
1555 .name = "rtcss",
1556 .class = &dra7xx_rtcss_hwmod_class,
1557 .clkdm_name = "rtc_clkdm",
1558 .main_clk = "sys_32k_ck",
1559 .prcm = {
1560 .omap4 = {
1561 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1562 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1563 .modulemode = MODULEMODE_SWCTRL,
1564 },
1565 },
1566};
1567
90020c7b
A		 1568/*
1569 * 'sata' class
1570 *
1571 */
1572
1573static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1574 .sysc_offs = 0x0000,
1575 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1576 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1577 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1578 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1579 .sysc_fields = &omap_hwmod_sysc_type2,
1580};
1581
1582static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1583 .name = "sata",
1584 .sysc = &dra7xx_sata_sysc,
1585};
1586
1587/* sata */
90020c7b
A		 1588
1589static struct omap_hwmod dra7xx_sata_hwmod = {
1590 .name = "sata",
1591 .class = &dra7xx_sata_hwmod_class,
1592 .clkdm_name = "l3init_clkdm",
1593 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1594 .main_clk = "func_48m_fclk",
1ea0999e 1595 .mpu_rt_idx = 1,
90020c7b
A		 1596 .prcm = {
1597 .omap4 = {
1598 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1599 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1600 .modulemode = MODULEMODE_SWCTRL,
1601 },
1602 },
90020c7b
A		 1603};
1604
1605/*
1606 * 'smartreflex' class
1607 *
1608 */
1609
1610/* The IP is not compliant to type1 / type2 scheme */
1611static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1612 .sidle_shift = 24,
1613 .enwkup_shift = 26,
1614};
1615
1616static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1617 .sysc_offs = 0x0038,
1618 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1619 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1620 SIDLE_SMART_WKUP),
1621 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1622};
1623
1624static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1625 .name = "smartreflex",
1626 .sysc = &dra7xx_smartreflex_sysc,
1627 .rev = 2,
1628};
1629
1630/* smartreflex_core */
1631/* smartreflex_core dev_attr */
1632static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1633 .sensor_voltdm_name = "core",
1634};
1635
1636static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1637 .name = "smartreflex_core",
1638 .class = &dra7xx_smartreflex_hwmod_class,
1639 .clkdm_name = "coreaon_clkdm",
1640 .main_clk = "wkupaon_iclk_mux",
1641 .prcm = {
1642 .omap4 = {
1643 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1644 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1645 .modulemode = MODULEMODE_SWCTRL,
1646 },
1647 },
1648 .dev_attr = &smartreflex_core_dev_attr,
1649};
1650
1651/* smartreflex_mpu */
1652/* smartreflex_mpu dev_attr */
1653static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1654 .sensor_voltdm_name = "mpu",
1655};
1656
1657static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1658 .name = "smartreflex_mpu",
1659 .class = &dra7xx_smartreflex_hwmod_class,
1660 .clkdm_name = "coreaon_clkdm",
1661 .main_clk = "wkupaon_iclk_mux",
1662 .prcm = {
1663 .omap4 = {
1664 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1665 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1666 .modulemode = MODULEMODE_SWCTRL,
1667 },
1668 },
1669 .dev_attr = &smartreflex_mpu_dev_attr,
1670};
1671
1672/*
1673 * 'spinlock' class
1674 *
1675 */
1676
1677static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1678 .rev_offs = 0x0000,
1679 .sysc_offs = 0x0010,
1680 .syss_offs = 0x0014,
c317d0f2
SA		 1681 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1682 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1683 SYSS_HAS_RESET_STATUS),
1684 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
90020c7b
A		 1685 .sysc_fields = &omap_hwmod_sysc_type1,
1686};
1687
1688static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1689 .name = "spinlock",
1690 .sysc = &dra7xx_spinlock_sysc,
1691};
1692
1693/* spinlock */
1694static struct omap_hwmod dra7xx_spinlock_hwmod = {
1695 .name = "spinlock",
1696 .class = &dra7xx_spinlock_hwmod_class,
1697 .clkdm_name = "l4cfg_clkdm",
1698 .main_clk = "l3_iclk_div",
1699 .prcm = {
1700 .omap4 = {
1701 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1702 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1703 },
1704 },
1705};
1706
1707/*
1708 * 'timer' class
1709 *
1710 * This class contains several variants: ['timer_1ms', 'timer_secure',
1711 * 'timer']
1712 */
1713
1714static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1715 .rev_offs = 0x0000,
1716 .sysc_offs = 0x0010,
1717 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1718 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1719 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1720 SIDLE_SMART_WKUP),
1721 .sysc_fields = &omap_hwmod_sysc_type2,
1722};
1723
1724static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1725 .name = "timer",
1726 .sysc = &dra7xx_timer_1ms_sysc,
1727};
1728
90020c7b
A		 1729static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1730 .rev_offs = 0x0000,
1731 .sysc_offs = 0x0010,
1732 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1733 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1734 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1735 SIDLE_SMART_WKUP),
1736 .sysc_fields = &omap_hwmod_sysc_type2,
1737};
1738
1739static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1740 .name = "timer",
1741 .sysc = &dra7xx_timer_sysc,
1742};
1743
1744/* timer1 */
1745static struct omap_hwmod dra7xx_timer1_hwmod = {
1746 .name = "timer1",
1747 .class = &dra7xx_timer_1ms_hwmod_class,
1748 .clkdm_name = "wkupaon_clkdm",
1749 .main_clk = "timer1_gfclk_mux",
1750 .prcm = {
1751 .omap4 = {
1752 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1753 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1754 .modulemode = MODULEMODE_SWCTRL,
1755 },
1756 },
1757};
1758
1759/* timer2 */
1760static struct omap_hwmod dra7xx_timer2_hwmod = {
1761 .name = "timer2",
1762 .class = &dra7xx_timer_1ms_hwmod_class,
1763 .clkdm_name = "l4per_clkdm",
1764 .main_clk = "timer2_gfclk_mux",
1765 .prcm = {
1766 .omap4 = {
1767 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1768 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1769 .modulemode = MODULEMODE_SWCTRL,
1770 },
1771 },
1772};
1773
1774/* timer3 */
1775static struct omap_hwmod dra7xx_timer3_hwmod = {
1776 .name = "timer3",
1777 .class = &dra7xx_timer_hwmod_class,
1778 .clkdm_name = "l4per_clkdm",
1779 .main_clk = "timer3_gfclk_mux",
1780 .prcm = {
1781 .omap4 = {
1782 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1783 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1784 .modulemode = MODULEMODE_SWCTRL,
1785 },
1786 },
1787};
1788
1789/* timer4 */
1790static struct omap_hwmod dra7xx_timer4_hwmod = {
1791 .name = "timer4",
edec1786 1792 .class = &dra7xx_timer_hwmod_class,
90020c7b
A		 1793 .clkdm_name = "l4per_clkdm",
1794 .main_clk = "timer4_gfclk_mux",
1795 .prcm = {
1796 .omap4 = {
1797 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1798 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1799 .modulemode = MODULEMODE_SWCTRL,
1800 },
1801 },
1802};
1803
1804/* timer5 */
1805static struct omap_hwmod dra7xx_timer5_hwmod = {
1806 .name = "timer5",
1807 .class = &dra7xx_timer_hwmod_class,
1808 .clkdm_name = "ipu_clkdm",
1809 .main_clk = "timer5_gfclk_mux",
1810 .prcm = {
1811 .omap4 = {
1812 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1813 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1814 .modulemode = MODULEMODE_SWCTRL,
1815 },
1816 },
1817};
1818
1819/* timer6 */
1820static struct omap_hwmod dra7xx_timer6_hwmod = {
1821 .name = "timer6",
1822 .class = &dra7xx_timer_hwmod_class,
1823 .clkdm_name = "ipu_clkdm",
1824 .main_clk = "timer6_gfclk_mux",
1825 .prcm = {
1826 .omap4 = {
1827 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1828 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1829 .modulemode = MODULEMODE_SWCTRL,
1830 },
1831 },
1832};
1833
1834/* timer7 */
1835static struct omap_hwmod dra7xx_timer7_hwmod = {
1836 .name = "timer7",
1837 .class = &dra7xx_timer_hwmod_class,
1838 .clkdm_name = "ipu_clkdm",
1839 .main_clk = "timer7_gfclk_mux",
1840 .prcm = {
1841 .omap4 = {
1842 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1843 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1844 .modulemode = MODULEMODE_SWCTRL,
1845 },
1846 },
1847};
1848
1849/* timer8 */
1850static struct omap_hwmod dra7xx_timer8_hwmod = {
1851 .name = "timer8",
1852 .class = &dra7xx_timer_hwmod_class,
1853 .clkdm_name = "ipu_clkdm",
1854 .main_clk = "timer8_gfclk_mux",
1855 .prcm = {
1856 .omap4 = {
1857 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1858 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1859 .modulemode = MODULEMODE_SWCTRL,
1860 },
1861 },
1862};
1863
1864/* timer9 */
1865static struct omap_hwmod dra7xx_timer9_hwmod = {
1866 .name = "timer9",
1867 .class = &dra7xx_timer_hwmod_class,
1868 .clkdm_name = "l4per_clkdm",
1869 .main_clk = "timer9_gfclk_mux",
1870 .prcm = {
1871 .omap4 = {
1872 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1873 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1874 .modulemode = MODULEMODE_SWCTRL,
1875 },
1876 },
1877};
1878
1879/* timer10 */
1880static struct omap_hwmod dra7xx_timer10_hwmod = {
1881 .name = "timer10",
1882 .class = &dra7xx_timer_1ms_hwmod_class,
1883 .clkdm_name = "l4per_clkdm",
1884 .main_clk = "timer10_gfclk_mux",
1885 .prcm = {
1886 .omap4 = {
1887 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1888 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1889 .modulemode = MODULEMODE_SWCTRL,
1890 },
1891 },
1892};
1893
1894/* timer11 */
1895static struct omap_hwmod dra7xx_timer11_hwmod = {
1896 .name = "timer11",
1897 .class = &dra7xx_timer_hwmod_class,
1898 .clkdm_name = "l4per_clkdm",
1899 .main_clk = "timer11_gfclk_mux",
1900 .prcm = {
1901 .omap4 = {
1902 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1903 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1904 .modulemode = MODULEMODE_SWCTRL,
1905 },
1906 },
1907};
1908
1ac964f4
SA		 1909/* timer13 */
1910static struct omap_hwmod dra7xx_timer13_hwmod = {
1911 .name = "timer13",
1912 .class = &dra7xx_timer_hwmod_class,
1913 .clkdm_name = "l4per3_clkdm",
1914 .main_clk = "timer13_gfclk_mux",
1915 .prcm = {
1916 .omap4 = {
1917 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
1918 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
1919 .modulemode = MODULEMODE_SWCTRL,
1920 },
1921 },
1922};
1923
1924/* timer14 */
1925static struct omap_hwmod dra7xx_timer14_hwmod = {
1926 .name = "timer14",
1927 .class = &dra7xx_timer_hwmod_class,
1928 .clkdm_name = "l4per3_clkdm",
1929 .main_clk = "timer14_gfclk_mux",
1930 .prcm = {
1931 .omap4 = {
1932 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
1933 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
1934 .modulemode = MODULEMODE_SWCTRL,
1935 },
1936 },
1937};
1938
1939/* timer15 */
1940static struct omap_hwmod dra7xx_timer15_hwmod = {
1941 .name = "timer15",
1942 .class = &dra7xx_timer_hwmod_class,
1943 .clkdm_name = "l4per3_clkdm",
1944 .main_clk = "timer15_gfclk_mux",
1945 .prcm = {
1946 .omap4 = {
1947 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
1948 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
1949 .modulemode = MODULEMODE_SWCTRL,
1950 },
1951 },
1952};
1953
1954/* timer16 */
1955static struct omap_hwmod dra7xx_timer16_hwmod = {
1956 .name = "timer16",
1957 .class = &dra7xx_timer_hwmod_class,
1958 .clkdm_name = "l4per3_clkdm",
1959 .main_clk = "timer16_gfclk_mux",
1960 .prcm = {
1961 .omap4 = {
1962 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
1963 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
1964 .modulemode = MODULEMODE_SWCTRL,
1965 },
1966 },
1967};
1968
90020c7b
A		 1969/*
1970 * 'uart' class
1971 *
1972 */
1973
1974static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
1975 .rev_offs = 0x0050,
1976 .sysc_offs = 0x0054,
1977 .syss_offs = 0x0058,
1978 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1979 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1980 SYSS_HAS_RESET_STATUS),
1981 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1982 SIDLE_SMART_WKUP),
1983 .sysc_fields = &omap_hwmod_sysc_type1,
1984};
1985
1986static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
1987 .name = "uart",
1988 .sysc = &dra7xx_uart_sysc,
1989};
1990
1991/* uart1 */
1992static struct omap_hwmod dra7xx_uart1_hwmod = {
1993 .name = "uart1",
1994 .class = &dra7xx_uart_hwmod_class,
1995 .clkdm_name = "l4per_clkdm",
1996 .main_clk = "uart1_gfclk_mux",
38958c15 1997 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
90020c7b
A		 1998 .prcm = {
1999 .omap4 = {
2000 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2001 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2002 .modulemode = MODULEMODE_SWCTRL,
2003 },
2004 },
2005};
2006
2007/* uart2 */
2008static struct omap_hwmod dra7xx_uart2_hwmod = {
2009 .name = "uart2",
2010 .class = &dra7xx_uart_hwmod_class,
2011 .clkdm_name = "l4per_clkdm",
2012 .main_clk = "uart2_gfclk_mux",
2013 .flags = HWMOD_SWSUP_SIDLE_ACT,
2014 .prcm = {
2015 .omap4 = {
2016 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2017 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2018 .modulemode = MODULEMODE_SWCTRL,
2019 },
2020 },
2021};
2022
2023/* uart3 */
2024static struct omap_hwmod dra7xx_uart3_hwmod = {
2025 .name = "uart3",
2026 .class = &dra7xx_uart_hwmod_class,
2027 .clkdm_name = "l4per_clkdm",
2028 .main_clk = "uart3_gfclk_mux",
1c7e36bf 2029 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
90020c7b
A		 2030 .prcm = {
2031 .omap4 = {
2032 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2033 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2034 .modulemode = MODULEMODE_SWCTRL,
2035 },
2036 },
2037};
2038
2039/* uart4 */
2040static struct omap_hwmod dra7xx_uart4_hwmod = {
2041 .name = "uart4",
2042 .class = &dra7xx_uart_hwmod_class,
2043 .clkdm_name = "l4per_clkdm",
2044 .main_clk = "uart4_gfclk_mux",
2045 .flags = HWMOD_SWSUP_SIDLE_ACT,
2046 .prcm = {
2047 .omap4 = {
2048 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2049 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2050 .modulemode = MODULEMODE_SWCTRL,
2051 },
2052 },
2053};
2054
2055/* uart5 */
2056static struct omap_hwmod dra7xx_uart5_hwmod = {
2057 .name = "uart5",
2058 .class = &dra7xx_uart_hwmod_class,
2059 .clkdm_name = "l4per_clkdm",
2060 .main_clk = "uart5_gfclk_mux",
2061 .flags = HWMOD_SWSUP_SIDLE_ACT,
2062 .prcm = {
2063 .omap4 = {
2064 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2065 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2066 .modulemode = MODULEMODE_SWCTRL,
2067 },
2068 },
2069};
2070
2071/* uart6 */
2072static struct omap_hwmod dra7xx_uart6_hwmod = {
2073 .name = "uart6",
2074 .class = &dra7xx_uart_hwmod_class,
2075 .clkdm_name = "ipu_clkdm",
2076 .main_clk = "uart6_gfclk_mux",
2077 .flags = HWMOD_SWSUP_SIDLE_ACT,
2078 .prcm = {
2079 .omap4 = {
2080 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2081 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2082 .modulemode = MODULEMODE_SWCTRL,
2083 },
2084 },
2085};
2086
33acc9ff
A		 2087/* uart7 */
2088static struct omap_hwmod dra7xx_uart7_hwmod = {
2089 .name = "uart7",
2090 .class = &dra7xx_uart_hwmod_class,
2091 .clkdm_name = "l4per2_clkdm",
2092 .main_clk = "uart7_gfclk_mux",
2093 .flags = HWMOD_SWSUP_SIDLE_ACT,
2094 .prcm = {
2095 .omap4 = {
2096 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2097 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2098 .modulemode = MODULEMODE_SWCTRL,
2099 },
2100 },
2101};
2102
2103/* uart8 */
2104static struct omap_hwmod dra7xx_uart8_hwmod = {
2105 .name = "uart8",
2106 .class = &dra7xx_uart_hwmod_class,
2107 .clkdm_name = "l4per2_clkdm",
2108 .main_clk = "uart8_gfclk_mux",
2109 .flags = HWMOD_SWSUP_SIDLE_ACT,
2110 .prcm = {
2111 .omap4 = {
2112 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2113 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2114 .modulemode = MODULEMODE_SWCTRL,
2115 },
2116 },
2117};
2118
2119/* uart9 */
2120static struct omap_hwmod dra7xx_uart9_hwmod = {
2121 .name = "uart9",
2122 .class = &dra7xx_uart_hwmod_class,
2123 .clkdm_name = "l4per2_clkdm",
2124 .main_clk = "uart9_gfclk_mux",
2125 .flags = HWMOD_SWSUP_SIDLE_ACT,
2126 .prcm = {
2127 .omap4 = {
2128 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2129 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2130 .modulemode = MODULEMODE_SWCTRL,
2131 },
2132 },
2133};
2134
2135/* uart10 */
2136static struct omap_hwmod dra7xx_uart10_hwmod = {
2137 .name = "uart10",
2138 .class = &dra7xx_uart_hwmod_class,
2139 .clkdm_name = "wkupaon_clkdm",
2140 .main_clk = "uart10_gfclk_mux",
2141 .flags = HWMOD_SWSUP_SIDLE_ACT,
2142 .prcm = {
2143 .omap4 = {
2144 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2145 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2146 .modulemode = MODULEMODE_SWCTRL,
2147 },
2148 },
2149};
2150
90020c7b
A		 2151/*
2152 * 'usb_otg_ss' class
2153 *
2154 */
2155
d904b38d
RQ		 2156static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2157 .rev_offs = 0x0000,
2158 .sysc_offs = 0x0010,
2159 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2160 SYSC_HAS_SIDLEMODE),
2161 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2162 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2163 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2164 .sysc_fields = &omap_hwmod_sysc_type2,
2165};
2166
90020c7b
A		 2167static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2168 .name = "usb_otg_ss",
d904b38d 2169 .sysc = &dra7xx_usb_otg_ss_sysc,
90020c7b
A		 2170};
2171
2172/* usb_otg_ss1 */
2173static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2174 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2175};
2176
2177static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2178 .name = "usb_otg_ss1",
2179 .class = &dra7xx_usb_otg_ss_hwmod_class,
2180 .clkdm_name = "l3init_clkdm",
2181 .main_clk = "dpll_core_h13x2_ck",
2182 .prcm = {
2183 .omap4 = {
2184 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2185 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2186 .modulemode = MODULEMODE_HWCTRL,
2187 },
2188 },
2189 .opt_clks = usb_otg_ss1_opt_clks,
2190 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2191};
2192
2193/* usb_otg_ss2 */
2194static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2195 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2196};
2197
2198static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2199 .name = "usb_otg_ss2",
2200 .class = &dra7xx_usb_otg_ss_hwmod_class,
2201 .clkdm_name = "l3init_clkdm",
2202 .main_clk = "dpll_core_h13x2_ck",
2203 .prcm = {
2204 .omap4 = {
2205 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2206 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2207 .modulemode = MODULEMODE_HWCTRL,
2208 },
2209 },
2210 .opt_clks = usb_otg_ss2_opt_clks,
2211 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2212};
2213
2214/* usb_otg_ss3 */
2215static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2216 .name = "usb_otg_ss3",
2217 .class = &dra7xx_usb_otg_ss_hwmod_class,
2218 .clkdm_name = "l3init_clkdm",
2219 .main_clk = "dpll_core_h13x2_ck",
2220 .prcm = {
2221 .omap4 = {
2222 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2223 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2224 .modulemode = MODULEMODE_HWCTRL,
2225 },
2226 },
2227};
2228
2229/* usb_otg_ss4 */
2230static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2231 .name = "usb_otg_ss4",
2232 .class = &dra7xx_usb_otg_ss_hwmod_class,
2233 .clkdm_name = "l3init_clkdm",
2234 .main_clk = "dpll_core_h13x2_ck",
2235 .prcm = {
2236 .omap4 = {
2237 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2238 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2239 .modulemode = MODULEMODE_HWCTRL,
2240 },
2241 },
2242};
2243
2244/*
2245 * 'vcp' class
2246 *
2247 */
2248
2249static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2250 .name = "vcp",
2251};
2252
2253/* vcp1 */
2254static struct omap_hwmod dra7xx_vcp1_hwmod = {
2255 .name = "vcp1",
2256 .class = &dra7xx_vcp_hwmod_class,
2257 .clkdm_name = "l3main1_clkdm",
2258 .main_clk = "l3_iclk_div",
2259 .prcm = {
2260 .omap4 = {
2261 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2262 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2263 },
2264 },
2265};
2266
2267/* vcp2 */
2268static struct omap_hwmod dra7xx_vcp2_hwmod = {
2269 .name = "vcp2",
2270 .class = &dra7xx_vcp_hwmod_class,
2271 .clkdm_name = "l3main1_clkdm",
2272 .main_clk = "l3_iclk_div",
2273 .prcm = {
2274 .omap4 = {
2275 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2276 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2277 },
2278 },
2279};
2280
2281/*
2282 * 'wd_timer' class
2283 *
2284 */
2285
2286static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2287 .rev_offs = 0x0000,
2288 .sysc_offs = 0x0010,
2289 .syss_offs = 0x0014,
2290 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2291 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2292 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2293 SIDLE_SMART_WKUP),
2294 .sysc_fields = &omap_hwmod_sysc_type1,
2295};
2296
2297static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2298 .name = "wd_timer",
2299 .sysc = &dra7xx_wd_timer_sysc,
2300 .pre_shutdown = &omap2_wd_timer_disable,
2301 .reset = &omap2_wd_timer_reset,
2302};
2303
2304/* wd_timer2 */
2305static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2306 .name = "wd_timer2",
2307 .class = &dra7xx_wd_timer_hwmod_class,
2308 .clkdm_name = "wkupaon_clkdm",
2309 .main_clk = "sys_32k_ck",
2310 .prcm = {
2311 .omap4 = {
2312 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2313 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2314 .modulemode = MODULEMODE_SWCTRL,
2315 },
2316 },
2317};
2318
2319
2320/*
2321 * Interfaces
2322 */
2323
2324/* l3_main_2 -> l3_instr */
2325static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2326 .master = &dra7xx_l3_main_2_hwmod,
2327 .slave = &dra7xx_l3_instr_hwmod,
2328 .clk = "l3_iclk_div",
2329 .user = OCP_USER_MPU | OCP_USER_SDMA,
2330};
2331
2332/* l4_cfg -> l3_main_1 */
2333static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2334 .master = &dra7xx_l4_cfg_hwmod,
2335 .slave = &dra7xx_l3_main_1_hwmod,
2336 .clk = "l3_iclk_div",
2337 .user = OCP_USER_MPU | OCP_USER_SDMA,
2338};
2339
2340/* mpu -> l3_main_1 */
2341static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2342 .master = &dra7xx_mpu_hwmod,
2343 .slave = &dra7xx_l3_main_1_hwmod,
2344 .clk = "l3_iclk_div",
2345 .user = OCP_USER_MPU,
2346};
2347
2348/* l3_main_1 -> l3_main_2 */
2349static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2350 .master = &dra7xx_l3_main_1_hwmod,
2351 .slave = &dra7xx_l3_main_2_hwmod,
2352 .clk = "l3_iclk_div",
2353 .user = OCP_USER_MPU,
2354};
2355
2356/* l4_cfg -> l3_main_2 */
2357static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2358 .master = &dra7xx_l4_cfg_hwmod,
2359 .slave = &dra7xx_l3_main_2_hwmod,
2360 .clk = "l3_iclk_div",
2361 .user = OCP_USER_MPU | OCP_USER_SDMA,
2362};
2363
2364/* l3_main_1 -> l4_cfg */
2365static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2366 .master = &dra7xx_l3_main_1_hwmod,
2367 .slave = &dra7xx_l4_cfg_hwmod,
2368 .clk = "l3_iclk_div",
2369 .user = OCP_USER_MPU | OCP_USER_SDMA,
2370};
2371
2372/* l3_main_1 -> l4_per1 */
2373static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2374 .master = &dra7xx_l3_main_1_hwmod,
2375 .slave = &dra7xx_l4_per1_hwmod,
2376 .clk = "l3_iclk_div",
2377 .user = OCP_USER_MPU | OCP_USER_SDMA,
2378};
2379
2380/* l3_main_1 -> l4_per2 */
2381static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2382 .master = &dra7xx_l3_main_1_hwmod,
2383 .slave = &dra7xx_l4_per2_hwmod,
2384 .clk = "l3_iclk_div",
2385 .user = OCP_USER_MPU | OCP_USER_SDMA,
2386};
2387
2388/* l3_main_1 -> l4_per3 */
2389static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2390 .master = &dra7xx_l3_main_1_hwmod,
2391 .slave = &dra7xx_l4_per3_hwmod,
2392 .clk = "l3_iclk_div",
2393 .user = OCP_USER_MPU | OCP_USER_SDMA,
2394};
2395
2396/* l3_main_1 -> l4_wkup */
2397static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2398 .master = &dra7xx_l3_main_1_hwmod,
2399 .slave = &dra7xx_l4_wkup_hwmod,
2400 .clk = "wkupaon_iclk_mux",
2401 .user = OCP_USER_MPU | OCP_USER_SDMA,
2402};
2403
2404/* l4_per2 -> atl */
2405static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2406 .master = &dra7xx_l4_per2_hwmod,
2407 .slave = &dra7xx_atl_hwmod,
2408 .clk = "l3_iclk_div",
2409 .user = OCP_USER_MPU | OCP_USER_SDMA,
2410};
2411
2412/* l3_main_1 -> bb2d */
2413static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2414 .master = &dra7xx_l3_main_1_hwmod,
2415 .slave = &dra7xx_bb2d_hwmod,
2416 .clk = "l3_iclk_div",
2417 .user = OCP_USER_MPU | OCP_USER_SDMA,
2418};
2419
2420/* l4_wkup -> counter_32k */
2421static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2422 .master = &dra7xx_l4_wkup_hwmod,
2423 .slave = &dra7xx_counter_32k_hwmod,
2424 .clk = "wkupaon_iclk_mux",
2425 .user = OCP_USER_MPU | OCP_USER_SDMA,
2426};
2427
2428/* l4_wkup -> ctrl_module_wkup */
2429static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2430 .master = &dra7xx_l4_wkup_hwmod,
2431 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2432 .clk = "wkupaon_iclk_mux",
2433 .user = OCP_USER_MPU | OCP_USER_SDMA,
2434};
2435
077c42f7
M		 2436static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2437 .master = &dra7xx_l4_per2_hwmod,
2438 .slave = &dra7xx_gmac_hwmod,
2439 .clk = "dpll_gmac_ck",
2440 .user = OCP_USER_MPU,
2441};
2442
2443static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2444 .master = &dra7xx_gmac_hwmod,
2445 .slave = &dra7xx_mdio_hwmod,
2446 .user = OCP_USER_MPU,
2447};
2448
90020c7b
A		 2449/* l4_wkup -> dcan1 */
2450static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2451 .master = &dra7xx_l4_wkup_hwmod,
2452 .slave = &dra7xx_dcan1_hwmod,
2453 .clk = "wkupaon_iclk_mux",
2454 .user = OCP_USER_MPU | OCP_USER_SDMA,
2455};
2456
2457/* l4_per2 -> dcan2 */
2458static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2459 .master = &dra7xx_l4_per2_hwmod,
2460 .slave = &dra7xx_dcan2_hwmod,
2461 .clk = "l3_iclk_div",
2462 .user = OCP_USER_MPU | OCP_USER_SDMA,
2463};
2464
2465static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2466 {
2467 .pa_start = 0x4a056000,
2468 .pa_end = 0x4a056fff,
2469 .flags = ADDR_TYPE_RT
2470 },
2471 { }
2472};
2473
2474/* l4_cfg -> dma_system */
2475static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2476 .master = &dra7xx_l4_cfg_hwmod,
2477 .slave = &dra7xx_dma_system_hwmod,
2478 .clk = "l3_iclk_div",
2479 .addr = dra7xx_dma_system_addrs,
2480 .user = OCP_USER_MPU | OCP_USER_SDMA,
2481};
2482
2483static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2484 {
2485 .name = "family",
2486 .pa_start = 0x58000000,
2487 .pa_end = 0x5800007f,
2488 .flags = ADDR_TYPE_RT
2489 },
2490};
2491
2492/* l3_main_1 -> dss */
2493static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2494 .master = &dra7xx_l3_main_1_hwmod,
2495 .slave = &dra7xx_dss_hwmod,
2496 .clk = "l3_iclk_div",
2497 .addr = dra7xx_dss_addrs,
2498 .user = OCP_USER_MPU | OCP_USER_SDMA,
2499};
2500
2501static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2502 {
2503 .name = "dispc",
2504 .pa_start = 0x58001000,
2505 .pa_end = 0x58001fff,
2506 .flags = ADDR_TYPE_RT
2507 },
2508};
2509
2510/* l3_main_1 -> dispc */
2511static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2512 .master = &dra7xx_l3_main_1_hwmod,
2513 .slave = &dra7xx_dss_dispc_hwmod,
2514 .clk = "l3_iclk_div",
2515 .addr = dra7xx_dss_dispc_addrs,
2516 .user = OCP_USER_MPU | OCP_USER_SDMA,
2517};
2518
2519static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2520 {
2521 .name = "hdmi_wp",
2522 .pa_start = 0x58040000,
2523 .pa_end = 0x580400ff,
2524 .flags = ADDR_TYPE_RT
2525 },
2526 { }
2527};
2528
2529/* l3_main_1 -> dispc */
2530static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2531 .master = &dra7xx_l3_main_1_hwmod,
2532 .slave = &dra7xx_dss_hdmi_hwmod,
2533 .clk = "l3_iclk_div",
2534 .addr = dra7xx_dss_hdmi_addrs,
2535 .user = OCP_USER_MPU | OCP_USER_SDMA,
2536};
2537
2538static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
2539 {
2540 .pa_start = 0x48078000,
2541 .pa_end = 0x48078fff,
2542 .flags = ADDR_TYPE_RT
2543 },
2544 { }
2545};
2546
2547/* l4_per1 -> elm */
2548static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2549 .master = &dra7xx_l4_per1_hwmod,
2550 .slave = &dra7xx_elm_hwmod,
2551 .clk = "l3_iclk_div",
2552 .addr = dra7xx_elm_addrs,
2553 .user = OCP_USER_MPU | OCP_USER_SDMA,
2554};
2555
2556/* l4_wkup -> gpio1 */
2557static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2558 .master = &dra7xx_l4_wkup_hwmod,
2559 .slave = &dra7xx_gpio1_hwmod,
2560 .clk = "wkupaon_iclk_mux",
2561 .user = OCP_USER_MPU | OCP_USER_SDMA,
2562};
2563
2564/* l4_per1 -> gpio2 */
2565static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2566 .master = &dra7xx_l4_per1_hwmod,
2567 .slave = &dra7xx_gpio2_hwmod,
2568 .clk = "l3_iclk_div",
2569 .user = OCP_USER_MPU | OCP_USER_SDMA,
2570};
2571
2572/* l4_per1 -> gpio3 */
2573static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2574 .master = &dra7xx_l4_per1_hwmod,
2575 .slave = &dra7xx_gpio3_hwmod,
2576 .clk = "l3_iclk_div",
2577 .user = OCP_USER_MPU | OCP_USER_SDMA,
2578};
2579
2580/* l4_per1 -> gpio4 */
2581static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2582 .master = &dra7xx_l4_per1_hwmod,
2583 .slave = &dra7xx_gpio4_hwmod,
2584 .clk = "l3_iclk_div",
2585 .user = OCP_USER_MPU | OCP_USER_SDMA,
2586};
2587
2588/* l4_per1 -> gpio5 */
2589static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2590 .master = &dra7xx_l4_per1_hwmod,
2591 .slave = &dra7xx_gpio5_hwmod,
2592 .clk = "l3_iclk_div",
2593 .user = OCP_USER_MPU | OCP_USER_SDMA,
2594};
2595
2596/* l4_per1 -> gpio6 */
2597static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2598 .master = &dra7xx_l4_per1_hwmod,
2599 .slave = &dra7xx_gpio6_hwmod,
2600 .clk = "l3_iclk_div",
2601 .user = OCP_USER_MPU | OCP_USER_SDMA,
2602};
2603
2604/* l4_per1 -> gpio7 */
2605static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2606 .master = &dra7xx_l4_per1_hwmod,
2607 .slave = &dra7xx_gpio7_hwmod,
2608 .clk = "l3_iclk_div",
2609 .user = OCP_USER_MPU | OCP_USER_SDMA,
2610};
2611
2612/* l4_per1 -> gpio8 */
2613static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2614 .master = &dra7xx_l4_per1_hwmod,
2615 .slave = &dra7xx_gpio8_hwmod,
2616 .clk = "l3_iclk_div",
2617 .user = OCP_USER_MPU | OCP_USER_SDMA,
2618};
2619
2620static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
2621 {
2622 .pa_start = 0x50000000,
2623 .pa_end = 0x500003ff,
2624 .flags = ADDR_TYPE_RT
2625 },
2626 { }
2627};
2628
2629/* l3_main_1 -> gpmc */
2630static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2631 .master = &dra7xx_l3_main_1_hwmod,
2632 .slave = &dra7xx_gpmc_hwmod,
2633 .clk = "l3_iclk_div",
2634 .addr = dra7xx_gpmc_addrs,
2635 .user = OCP_USER_MPU | OCP_USER_SDMA,
2636};
2637
2638static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2639 {
2640 .pa_start = 0x480b2000,
2641 .pa_end = 0x480b201f,
2642 .flags = ADDR_TYPE_RT
2643 },
2644 { }
2645};
2646
2647/* l4_per1 -> hdq1w */
2648static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2649 .master = &dra7xx_l4_per1_hwmod,
2650 .slave = &dra7xx_hdq1w_hwmod,
2651 .clk = "l3_iclk_div",
2652 .addr = dra7xx_hdq1w_addrs,
2653 .user = OCP_USER_MPU | OCP_USER_SDMA,
2654};
2655
2656/* l4_per1 -> i2c1 */
2657static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2658 .master = &dra7xx_l4_per1_hwmod,
2659 .slave = &dra7xx_i2c1_hwmod,
2660 .clk = "l3_iclk_div",
2661 .user = OCP_USER_MPU | OCP_USER_SDMA,
2662};
2663
2664/* l4_per1 -> i2c2 */
2665static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2666 .master = &dra7xx_l4_per1_hwmod,
2667 .slave = &dra7xx_i2c2_hwmod,
2668 .clk = "l3_iclk_div",
2669 .user = OCP_USER_MPU | OCP_USER_SDMA,
2670};
2671
2672/* l4_per1 -> i2c3 */
2673static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2674 .master = &dra7xx_l4_per1_hwmod,
2675 .slave = &dra7xx_i2c3_hwmod,
2676 .clk = "l3_iclk_div",
2677 .user = OCP_USER_MPU | OCP_USER_SDMA,
2678};
2679
2680/* l4_per1 -> i2c4 */
2681static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2682 .master = &dra7xx_l4_per1_hwmod,
2683 .slave = &dra7xx_i2c4_hwmod,
2684 .clk = "l3_iclk_div",
2685 .user = OCP_USER_MPU | OCP_USER_SDMA,
2686};
2687
2688/* l4_per1 -> i2c5 */
2689static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2690 .master = &dra7xx_l4_per1_hwmod,
2691 .slave = &dra7xx_i2c5_hwmod,
2692 .clk = "l3_iclk_div",
2693 .user = OCP_USER_MPU | OCP_USER_SDMA,
2694};
2695
067395d4
SA		 2696/* l4_cfg -> mailbox1 */
2697static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
2698 .master = &dra7xx_l4_cfg_hwmod,
2699 .slave = &dra7xx_mailbox1_hwmod,
2700 .clk = "l3_iclk_div",
2701 .user = OCP_USER_MPU | OCP_USER_SDMA,
2702};
2703
2704/* l4_per3 -> mailbox2 */
2705static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
2706 .master = &dra7xx_l4_per3_hwmod,
2707 .slave = &dra7xx_mailbox2_hwmod,
2708 .clk = "l3_iclk_div",
2709 .user = OCP_USER_MPU | OCP_USER_SDMA,
2710};
2711
2712/* l4_per3 -> mailbox3 */
2713static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
2714 .master = &dra7xx_l4_per3_hwmod,
2715 .slave = &dra7xx_mailbox3_hwmod,
2716 .clk = "l3_iclk_div",
2717 .user = OCP_USER_MPU | OCP_USER_SDMA,
2718};
2719
2720/* l4_per3 -> mailbox4 */
2721static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
2722 .master = &dra7xx_l4_per3_hwmod,
2723 .slave = &dra7xx_mailbox4_hwmod,
2724 .clk = "l3_iclk_div",
2725 .user = OCP_USER_MPU | OCP_USER_SDMA,
2726};
2727
2728/* l4_per3 -> mailbox5 */
2729static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
2730 .master = &dra7xx_l4_per3_hwmod,
2731 .slave = &dra7xx_mailbox5_hwmod,
2732 .clk = "l3_iclk_div",
2733 .user = OCP_USER_MPU | OCP_USER_SDMA,
2734};
2735
2736/* l4_per3 -> mailbox6 */
2737static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
2738 .master = &dra7xx_l4_per3_hwmod,
2739 .slave = &dra7xx_mailbox6_hwmod,
2740 .clk = "l3_iclk_div",
2741 .user = OCP_USER_MPU | OCP_USER_SDMA,
2742};
2743
2744/* l4_per3 -> mailbox7 */
2745static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
2746 .master = &dra7xx_l4_per3_hwmod,
2747 .slave = &dra7xx_mailbox7_hwmod,
2748 .clk = "l3_iclk_div",
2749 .user = OCP_USER_MPU | OCP_USER_SDMA,
2750};
2751
2752/* l4_per3 -> mailbox8 */
2753static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
2754 .master = &dra7xx_l4_per3_hwmod,
2755 .slave = &dra7xx_mailbox8_hwmod,
2756 .clk = "l3_iclk_div",
2757 .user = OCP_USER_MPU | OCP_USER_SDMA,
2758};
2759
2760/* l4_per3 -> mailbox9 */
2761static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
2762 .master = &dra7xx_l4_per3_hwmod,
2763 .slave = &dra7xx_mailbox9_hwmod,
2764 .clk = "l3_iclk_div",
2765 .user = OCP_USER_MPU | OCP_USER_SDMA,
2766};
2767
2768/* l4_per3 -> mailbox10 */
2769static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
2770 .master = &dra7xx_l4_per3_hwmod,
2771 .slave = &dra7xx_mailbox10_hwmod,
2772 .clk = "l3_iclk_div",
2773 .user = OCP_USER_MPU | OCP_USER_SDMA,
2774};
2775
2776/* l4_per3 -> mailbox11 */
2777static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
2778 .master = &dra7xx_l4_per3_hwmod,
2779 .slave = &dra7xx_mailbox11_hwmod,
2780 .clk = "l3_iclk_div",
2781 .user = OCP_USER_MPU | OCP_USER_SDMA,
2782};
2783
2784/* l4_per3 -> mailbox12 */
2785static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
2786 .master = &dra7xx_l4_per3_hwmod,
2787 .slave = &dra7xx_mailbox12_hwmod,
2788 .clk = "l3_iclk_div",
2789 .user = OCP_USER_MPU | OCP_USER_SDMA,
2790};
2791
2792/* l4_per3 -> mailbox13 */
2793static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
2794 .master = &dra7xx_l4_per3_hwmod,
2795 .slave = &dra7xx_mailbox13_hwmod,
2796 .clk = "l3_iclk_div",
2797 .user = OCP_USER_MPU | OCP_USER_SDMA,
2798};
2799
90020c7b
A		 2800/* l4_per1 -> mcspi1 */
2801static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2802 .master = &dra7xx_l4_per1_hwmod,
2803 .slave = &dra7xx_mcspi1_hwmod,
2804 .clk = "l3_iclk_div",
2805 .user = OCP_USER_MPU | OCP_USER_SDMA,
2806};
2807
2808/* l4_per1 -> mcspi2 */
2809static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2810 .master = &dra7xx_l4_per1_hwmod,
2811 .slave = &dra7xx_mcspi2_hwmod,
2812 .clk = "l3_iclk_div",
2813 .user = OCP_USER_MPU | OCP_USER_SDMA,
2814};
2815
2816/* l4_per1 -> mcspi3 */
2817static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2818 .master = &dra7xx_l4_per1_hwmod,
2819 .slave = &dra7xx_mcspi3_hwmod,
2820 .clk = "l3_iclk_div",
2821 .user = OCP_USER_MPU | OCP_USER_SDMA,
2822};
2823
2824/* l4_per1 -> mcspi4 */
2825static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2826 .master = &dra7xx_l4_per1_hwmod,
2827 .slave = &dra7xx_mcspi4_hwmod,
2828 .clk = "l3_iclk_div",
2829 .user = OCP_USER_MPU | OCP_USER_SDMA,
2830};
2831
2832/* l4_per1 -> mmc1 */
2833static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
2834 .master = &dra7xx_l4_per1_hwmod,
2835 .slave = &dra7xx_mmc1_hwmod,
2836 .clk = "l3_iclk_div",
2837 .user = OCP_USER_MPU | OCP_USER_SDMA,
2838};
2839
2840/* l4_per1 -> mmc2 */
2841static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
2842 .master = &dra7xx_l4_per1_hwmod,
2843 .slave = &dra7xx_mmc2_hwmod,
2844 .clk = "l3_iclk_div",
2845 .user = OCP_USER_MPU | OCP_USER_SDMA,
2846};
2847
2848/* l4_per1 -> mmc3 */
2849static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
2850 .master = &dra7xx_l4_per1_hwmod,
2851 .slave = &dra7xx_mmc3_hwmod,
2852 .clk = "l3_iclk_div",
2853 .user = OCP_USER_MPU | OCP_USER_SDMA,
2854};
2855
2856/* l4_per1 -> mmc4 */
2857static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
2858 .master = &dra7xx_l4_per1_hwmod,
2859 .slave = &dra7xx_mmc4_hwmod,
2860 .clk = "l3_iclk_div",
2861 .user = OCP_USER_MPU | OCP_USER_SDMA,
2862};
2863
2864/* l4_cfg -> mpu */
2865static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2866 .master = &dra7xx_l4_cfg_hwmod,
2867 .slave = &dra7xx_mpu_hwmod,
2868 .clk = "l3_iclk_div",
2869 .user = OCP_USER_MPU | OCP_USER_SDMA,
2870};
2871
90020c7b
A		 2872/* l4_cfg -> ocp2scp1 */
2873static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2874 .master = &dra7xx_l4_cfg_hwmod,
2875 .slave = &dra7xx_ocp2scp1_hwmod,
2876 .clk = "l4_root_clk_div",
90020c7b
A		 2877 .user = OCP_USER_MPU | OCP_USER_SDMA,
2878};
2879
df0d0f11
RQ		 2880/* l4_cfg -> ocp2scp3 */
2881static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
2882 .master = &dra7xx_l4_cfg_hwmod,
2883 .slave = &dra7xx_ocp2scp3_hwmod,
2884 .clk = "l4_root_clk_div",
2885 .user = OCP_USER_MPU | OCP_USER_SDMA,
2886};
2887
0717103e
KVA		 2888/* l3_main_1 -> pciess1 */
2889static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
8dd3eb71 2890 .master = &dra7xx_l3_main_1_hwmod,
0717103e 2891 .slave = &dra7xx_pciess1_hwmod,
8dd3eb71
KVA		 2892 .clk = "l3_iclk_div",
2893 .user = OCP_USER_MPU | OCP_USER_SDMA,
2894};
2895
0717103e
KVA		 2896/* l4_cfg -> pciess1 */
2897static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
8dd3eb71 2898 .master = &dra7xx_l4_cfg_hwmod,
0717103e 2899 .slave = &dra7xx_pciess1_hwmod,
8dd3eb71
KVA		 2900 .clk = "l4_root_clk_div",
2901 .user = OCP_USER_MPU | OCP_USER_SDMA,
2902};
2903
0717103e
KVA		 2904/* l3_main_1 -> pciess2 */
2905static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
8dd3eb71 2906 .master = &dra7xx_l3_main_1_hwmod,
0717103e 2907 .slave = &dra7xx_pciess2_hwmod,
8dd3eb71
KVA		 2908 .clk = "l3_iclk_div",
2909 .user = OCP_USER_MPU | OCP_USER_SDMA,
2910};
2911
0717103e
KVA		 2912/* l4_cfg -> pciess2 */
2913static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
70c18ef7 2914 .master = &dra7xx_l4_cfg_hwmod,
0717103e 2915 .slave = &dra7xx_pciess2_hwmod,
70c18ef7
KVA		 2916 .clk = "l4_root_clk_div",
2917 .user = OCP_USER_MPU | OCP_USER_SDMA,
2918};
2919
90020c7b
A		 2920static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2921 {
2922 .pa_start = 0x4b300000,
2923 .pa_end = 0x4b30007f,
2924 .flags = ADDR_TYPE_RT
2925 },
2926 { }
2927};
2928
2929/* l3_main_1 -> qspi */
2930static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2931 .master = &dra7xx_l3_main_1_hwmod,
2932 .slave = &dra7xx_qspi_hwmod,
2933 .clk = "l3_iclk_div",
2934 .addr = dra7xx_qspi_addrs,
2935 .user = OCP_USER_MPU | OCP_USER_SDMA,
2936};
2937
c913c8a1
LV		 2938/* l4_per3 -> rtcss */
2939static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
2940 .master = &dra7xx_l4_per3_hwmod,
2941 .slave = &dra7xx_rtcss_hwmod,
2942 .clk = "l4_root_clk_div",
2943 .user = OCP_USER_MPU | OCP_USER_SDMA,
2944};
2945
90020c7b
A		 2946static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
2947 {
2948 .name = "sysc",
2949 .pa_start = 0x4a141100,
2950 .pa_end = 0x4a141107,
2951 .flags = ADDR_TYPE_RT
2952 },
2953 { }
2954};
2955
2956/* l4_cfg -> sata */
2957static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
2958 .master = &dra7xx_l4_cfg_hwmod,
2959 .slave = &dra7xx_sata_hwmod,
2960 .clk = "l3_iclk_div",
2961 .addr = dra7xx_sata_addrs,
2962 .user = OCP_USER_MPU | OCP_USER_SDMA,
2963};
2964
2965static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
2966 {
2967 .pa_start = 0x4a0dd000,
2968 .pa_end = 0x4a0dd07f,
2969 .flags = ADDR_TYPE_RT
2970 },
2971 { }
2972};
2973
2974/* l4_cfg -> smartreflex_core */
2975static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
2976 .master = &dra7xx_l4_cfg_hwmod,
2977 .slave = &dra7xx_smartreflex_core_hwmod,
2978 .clk = "l4_root_clk_div",
2979 .addr = dra7xx_smartreflex_core_addrs,
2980 .user = OCP_USER_MPU | OCP_USER_SDMA,
2981};
2982
2983static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
2984 {
2985 .pa_start = 0x4a0d9000,
2986 .pa_end = 0x4a0d907f,
2987 .flags = ADDR_TYPE_RT
2988 },
2989 { }
2990};
2991
2992/* l4_cfg -> smartreflex_mpu */
2993static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
2994 .master = &dra7xx_l4_cfg_hwmod,
2995 .slave = &dra7xx_smartreflex_mpu_hwmod,
2996 .clk = "l4_root_clk_div",
2997 .addr = dra7xx_smartreflex_mpu_addrs,
2998 .user = OCP_USER_MPU | OCP_USER_SDMA,
2999};
3000
3001static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
3002 {
3003 .pa_start = 0x4a0f6000,
3004 .pa_end = 0x4a0f6fff,
3005 .flags = ADDR_TYPE_RT
3006 },
3007 { }
3008};
3009
3010/* l4_cfg -> spinlock */
3011static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3012 .master = &dra7xx_l4_cfg_hwmod,
3013 .slave = &dra7xx_spinlock_hwmod,
3014 .clk = "l3_iclk_div",
3015 .addr = dra7xx_spinlock_addrs,
3016 .user = OCP_USER_MPU | OCP_USER_SDMA,
3017};
3018
3019/* l4_wkup -> timer1 */
3020static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3021 .master = &dra7xx_l4_wkup_hwmod,
3022 .slave = &dra7xx_timer1_hwmod,
3023 .clk = "wkupaon_iclk_mux",
3024 .user = OCP_USER_MPU | OCP_USER_SDMA,
3025};
3026
3027/* l4_per1 -> timer2 */
3028static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3029 .master = &dra7xx_l4_per1_hwmod,
3030 .slave = &dra7xx_timer2_hwmod,
3031 .clk = "l3_iclk_div",
3032 .user = OCP_USER_MPU | OCP_USER_SDMA,
3033};
3034
3035/* l4_per1 -> timer3 */
3036static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3037 .master = &dra7xx_l4_per1_hwmod,
3038 .slave = &dra7xx_timer3_hwmod,
3039 .clk = "l3_iclk_div",
3040 .user = OCP_USER_MPU | OCP_USER_SDMA,
3041};
3042
3043/* l4_per1 -> timer4 */
3044static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3045 .master = &dra7xx_l4_per1_hwmod,
3046 .slave = &dra7xx_timer4_hwmod,
3047 .clk = "l3_iclk_div",
3048 .user = OCP_USER_MPU | OCP_USER_SDMA,
3049};
3050
3051/* l4_per3 -> timer5 */
3052static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3053 .master = &dra7xx_l4_per3_hwmod,
3054 .slave = &dra7xx_timer5_hwmod,
3055 .clk = "l3_iclk_div",
3056 .user = OCP_USER_MPU | OCP_USER_SDMA,
3057};
3058
3059/* l4_per3 -> timer6 */
3060static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3061 .master = &dra7xx_l4_per3_hwmod,
3062 .slave = &dra7xx_timer6_hwmod,
3063 .clk = "l3_iclk_div",
3064 .user = OCP_USER_MPU | OCP_USER_SDMA,
3065};
3066
3067/* l4_per3 -> timer7 */
3068static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3069 .master = &dra7xx_l4_per3_hwmod,
3070 .slave = &dra7xx_timer7_hwmod,
3071 .clk = "l3_iclk_div",
3072 .user = OCP_USER_MPU | OCP_USER_SDMA,
3073};
3074
3075/* l4_per3 -> timer8 */
3076static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3077 .master = &dra7xx_l4_per3_hwmod,
3078 .slave = &dra7xx_timer8_hwmod,
3079 .clk = "l3_iclk_div",
3080 .user = OCP_USER_MPU | OCP_USER_SDMA,
3081};
3082
3083/* l4_per1 -> timer9 */
3084static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3085 .master = &dra7xx_l4_per1_hwmod,
3086 .slave = &dra7xx_timer9_hwmod,
3087 .clk = "l3_iclk_div",
3088 .user = OCP_USER_MPU | OCP_USER_SDMA,
3089};
3090
3091/* l4_per1 -> timer10 */
3092static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3093 .master = &dra7xx_l4_per1_hwmod,
3094 .slave = &dra7xx_timer10_hwmod,
3095 .clk = "l3_iclk_div",
3096 .user = OCP_USER_MPU | OCP_USER_SDMA,
3097};
3098
3099/* l4_per1 -> timer11 */
3100static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3101 .master = &dra7xx_l4_per1_hwmod,
3102 .slave = &dra7xx_timer11_hwmod,
3103 .clk = "l3_iclk_div",
3104 .user = OCP_USER_MPU | OCP_USER_SDMA,
3105};
3106
1ac964f4
SA		 3107/* l4_per3 -> timer13 */
3108static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3109 .master = &dra7xx_l4_per3_hwmod,
3110 .slave = &dra7xx_timer13_hwmod,
3111 .clk = "l3_iclk_div",
3112 .user = OCP_USER_MPU | OCP_USER_SDMA,
3113};
3114
3115/* l4_per3 -> timer14 */
3116static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3117 .master = &dra7xx_l4_per3_hwmod,
3118 .slave = &dra7xx_timer14_hwmod,
3119 .clk = "l3_iclk_div",
3120 .user = OCP_USER_MPU | OCP_USER_SDMA,
3121};
3122
3123/* l4_per3 -> timer15 */
3124static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3125 .master = &dra7xx_l4_per3_hwmod,
3126 .slave = &dra7xx_timer15_hwmod,
3127 .clk = "l3_iclk_div",
3128 .user = OCP_USER_MPU | OCP_USER_SDMA,
3129};
3130
3131/* l4_per3 -> timer16 */
3132static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3133 .master = &dra7xx_l4_per3_hwmod,
3134 .slave = &dra7xx_timer16_hwmod,
3135 .clk = "l3_iclk_div",
3136 .user = OCP_USER_MPU | OCP_USER_SDMA,
3137};
3138
90020c7b
A		 3139/* l4_per1 -> uart1 */
3140static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3141 .master = &dra7xx_l4_per1_hwmod,
3142 .slave = &dra7xx_uart1_hwmod,
3143 .clk = "l3_iclk_div",
3144 .user = OCP_USER_MPU | OCP_USER_SDMA,
3145};
3146
3147/* l4_per1 -> uart2 */
3148static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3149 .master = &dra7xx_l4_per1_hwmod,
3150 .slave = &dra7xx_uart2_hwmod,
3151 .clk = "l3_iclk_div",
3152 .user = OCP_USER_MPU | OCP_USER_SDMA,
3153};
3154
3155/* l4_per1 -> uart3 */
3156static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3157 .master = &dra7xx_l4_per1_hwmod,
3158 .slave = &dra7xx_uart3_hwmod,
3159 .clk = "l3_iclk_div",
3160 .user = OCP_USER_MPU | OCP_USER_SDMA,
3161};
3162
3163/* l4_per1 -> uart4 */
3164static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3165 .master = &dra7xx_l4_per1_hwmod,
3166 .slave = &dra7xx_uart4_hwmod,
3167 .clk = "l3_iclk_div",
3168 .user = OCP_USER_MPU | OCP_USER_SDMA,
3169};
3170
3171/* l4_per1 -> uart5 */
3172static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3173 .master = &dra7xx_l4_per1_hwmod,
3174 .slave = &dra7xx_uart5_hwmod,
3175 .clk = "l3_iclk_div",
3176 .user = OCP_USER_MPU | OCP_USER_SDMA,
3177};
3178
3179/* l4_per1 -> uart6 */
3180static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3181 .master = &dra7xx_l4_per1_hwmod,
3182 .slave = &dra7xx_uart6_hwmod,
3183 .clk = "l3_iclk_div",
3184 .user = OCP_USER_MPU | OCP_USER_SDMA,
3185};
3186
33acc9ff
A		 3187/* l4_per2 -> uart7 */
3188static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3189 .master = &dra7xx_l4_per2_hwmod,
3190 .slave = &dra7xx_uart7_hwmod,
3191 .clk = "l3_iclk_div",
3192 .user = OCP_USER_MPU | OCP_USER_SDMA,
3193};
3194
3195/* l4_per2 -> uart8 */
3196static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3197 .master = &dra7xx_l4_per2_hwmod,
3198 .slave = &dra7xx_uart8_hwmod,
3199 .clk = "l3_iclk_div",
3200 .user = OCP_USER_MPU | OCP_USER_SDMA,
3201};
3202
3203/* l4_per2 -> uart9 */
3204static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3205 .master = &dra7xx_l4_per2_hwmod,
3206 .slave = &dra7xx_uart9_hwmod,
3207 .clk = "l3_iclk_div",
3208 .user = OCP_USER_MPU | OCP_USER_SDMA,
3209};
3210
3211/* l4_wkup -> uart10 */
3212static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3213 .master = &dra7xx_l4_wkup_hwmod,
3214 .slave = &dra7xx_uart10_hwmod,
3215 .clk = "wkupaon_iclk_mux",
3216 .user = OCP_USER_MPU | OCP_USER_SDMA,
3217};
3218
90020c7b
A		 3219/* l4_per3 -> usb_otg_ss1 */
3220static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3221 .master = &dra7xx_l4_per3_hwmod,
3222 .slave = &dra7xx_usb_otg_ss1_hwmod,
3223 .clk = "dpll_core_h13x2_ck",
3224 .user = OCP_USER_MPU | OCP_USER_SDMA,
3225};
3226
3227/* l4_per3 -> usb_otg_ss2 */
3228static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3229 .master = &dra7xx_l4_per3_hwmod,
3230 .slave = &dra7xx_usb_otg_ss2_hwmod,
3231 .clk = "dpll_core_h13x2_ck",
3232 .user = OCP_USER_MPU | OCP_USER_SDMA,
3233};
3234
3235/* l4_per3 -> usb_otg_ss3 */
3236static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3237 .master = &dra7xx_l4_per3_hwmod,
3238 .slave = &dra7xx_usb_otg_ss3_hwmod,
3239 .clk = "dpll_core_h13x2_ck",
3240 .user = OCP_USER_MPU | OCP_USER_SDMA,
3241};
3242
3243/* l4_per3 -> usb_otg_ss4 */
3244static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3245 .master = &dra7xx_l4_per3_hwmod,
3246 .slave = &dra7xx_usb_otg_ss4_hwmod,
3247 .clk = "dpll_core_h13x2_ck",
3248 .user = OCP_USER_MPU | OCP_USER_SDMA,
3249};
3250
3251/* l3_main_1 -> vcp1 */
3252static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3253 .master = &dra7xx_l3_main_1_hwmod,
3254 .slave = &dra7xx_vcp1_hwmod,
3255 .clk = "l3_iclk_div",
3256 .user = OCP_USER_MPU | OCP_USER_SDMA,
3257};
3258
3259/* l4_per2 -> vcp1 */
3260static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3261 .master = &dra7xx_l4_per2_hwmod,
3262 .slave = &dra7xx_vcp1_hwmod,
3263 .clk = "l3_iclk_div",
3264 .user = OCP_USER_MPU | OCP_USER_SDMA,
3265};
3266
3267/* l3_main_1 -> vcp2 */
3268static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3269 .master = &dra7xx_l3_main_1_hwmod,
3270 .slave = &dra7xx_vcp2_hwmod,
3271 .clk = "l3_iclk_div",
3272 .user = OCP_USER_MPU | OCP_USER_SDMA,
3273};
3274
3275/* l4_per2 -> vcp2 */
3276static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3277 .master = &dra7xx_l4_per2_hwmod,
3278 .slave = &dra7xx_vcp2_hwmod,
3279 .clk = "l3_iclk_div",
3280 .user = OCP_USER_MPU | OCP_USER_SDMA,
3281};
3282
3283/* l4_wkup -> wd_timer2 */
3284static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3285 .master = &dra7xx_l4_wkup_hwmod,
3286 .slave = &dra7xx_wd_timer2_hwmod,
3287 .clk = "wkupaon_iclk_mux",
3288 .user = OCP_USER_MPU | OCP_USER_SDMA,
3289};
3290
3291static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3292 &dra7xx_l3_main_2__l3_instr,
3293 &dra7xx_l4_cfg__l3_main_1,
3294 &dra7xx_mpu__l3_main_1,
3295 &dra7xx_l3_main_1__l3_main_2,
3296 &dra7xx_l4_cfg__l3_main_2,
3297 &dra7xx_l3_main_1__l4_cfg,
3298 &dra7xx_l3_main_1__l4_per1,
3299 &dra7xx_l3_main_1__l4_per2,
3300 &dra7xx_l3_main_1__l4_per3,
3301 &dra7xx_l3_main_1__l4_wkup,
3302 &dra7xx_l4_per2__atl,
3303 &dra7xx_l3_main_1__bb2d,
3304 &dra7xx_l4_wkup__counter_32k,
3305 &dra7xx_l4_wkup__ctrl_module_wkup,
3306 &dra7xx_l4_wkup__dcan1,
3307 &dra7xx_l4_per2__dcan2,
077c42f7
M		 3308 &dra7xx_l4_per2__cpgmac0,
3309 &dra7xx_gmac__mdio,
90020c7b
A		 3310 &dra7xx_l4_cfg__dma_system,
3311 &dra7xx_l3_main_1__dss,
3312 &dra7xx_l3_main_1__dispc,
3313 &dra7xx_l3_main_1__hdmi,
3314 &dra7xx_l4_per1__elm,
3315 &dra7xx_l4_wkup__gpio1,
3316 &dra7xx_l4_per1__gpio2,
3317 &dra7xx_l4_per1__gpio3,
3318 &dra7xx_l4_per1__gpio4,
3319 &dra7xx_l4_per1__gpio5,
3320 &dra7xx_l4_per1__gpio6,
3321 &dra7xx_l4_per1__gpio7,
3322 &dra7xx_l4_per1__gpio8,
3323 &dra7xx_l3_main_1__gpmc,
3324 &dra7xx_l4_per1__hdq1w,
3325 &dra7xx_l4_per1__i2c1,
3326 &dra7xx_l4_per1__i2c2,
3327 &dra7xx_l4_per1__i2c3,
3328 &dra7xx_l4_per1__i2c4,
3329 &dra7xx_l4_per1__i2c5,
067395d4
SA		 3330 &dra7xx_l4_cfg__mailbox1,
3331 &dra7xx_l4_per3__mailbox2,
3332 &dra7xx_l4_per3__mailbox3,
3333 &dra7xx_l4_per3__mailbox4,
3334 &dra7xx_l4_per3__mailbox5,
3335 &dra7xx_l4_per3__mailbox6,
3336 &dra7xx_l4_per3__mailbox7,
3337 &dra7xx_l4_per3__mailbox8,
3338 &dra7xx_l4_per3__mailbox9,
3339 &dra7xx_l4_per3__mailbox10,
3340 &dra7xx_l4_per3__mailbox11,
3341 &dra7xx_l4_per3__mailbox12,
3342 &dra7xx_l4_per3__mailbox13,
90020c7b
A		 3343 &dra7xx_l4_per1__mcspi1,
3344 &dra7xx_l4_per1__mcspi2,
3345 &dra7xx_l4_per1__mcspi3,
3346 &dra7xx_l4_per1__mcspi4,
3347 &dra7xx_l4_per1__mmc1,
3348 &dra7xx_l4_per1__mmc2,
3349 &dra7xx_l4_per1__mmc3,
3350 &dra7xx_l4_per1__mmc4,
3351 &dra7xx_l4_cfg__mpu,
3352 &dra7xx_l4_cfg__ocp2scp1,
df0d0f11 3353 &dra7xx_l4_cfg__ocp2scp3,
0717103e
KVA		 3354 &dra7xx_l3_main_1__pciess1,
3355 &dra7xx_l4_cfg__pciess1,
3356 &dra7xx_l3_main_1__pciess2,
3357 &dra7xx_l4_cfg__pciess2,
90020c7b 3358 &dra7xx_l3_main_1__qspi,
c913c8a1 3359 &dra7xx_l4_per3__rtcss,
90020c7b
A		 3360 &dra7xx_l4_cfg__sata,
3361 &dra7xx_l4_cfg__smartreflex_core,
3362 &dra7xx_l4_cfg__smartreflex_mpu,
3363 &dra7xx_l4_cfg__spinlock,
3364 &dra7xx_l4_wkup__timer1,
3365 &dra7xx_l4_per1__timer2,
3366 &dra7xx_l4_per1__timer3,
3367 &dra7xx_l4_per1__timer4,
3368 &dra7xx_l4_per3__timer5,
3369 &dra7xx_l4_per3__timer6,
3370 &dra7xx_l4_per3__timer7,
3371 &dra7xx_l4_per3__timer8,
3372 &dra7xx_l4_per1__timer9,
3373 &dra7xx_l4_per1__timer10,
3374 &dra7xx_l4_per1__timer11,
1ac964f4
SA		 3375 &dra7xx_l4_per3__timer13,
3376 &dra7xx_l4_per3__timer14,
3377 &dra7xx_l4_per3__timer15,
3378 &dra7xx_l4_per3__timer16,
90020c7b
A		 3379 &dra7xx_l4_per1__uart1,
3380 &dra7xx_l4_per1__uart2,
3381 &dra7xx_l4_per1__uart3,
3382 &dra7xx_l4_per1__uart4,
3383 &dra7xx_l4_per1__uart5,
3384 &dra7xx_l4_per1__uart6,
33acc9ff
A		 3385 &dra7xx_l4_per2__uart7,
3386 &dra7xx_l4_per2__uart8,
3387 &dra7xx_l4_per2__uart9,
3388 &dra7xx_l4_wkup__uart10,
90020c7b
A		 3389 &dra7xx_l4_per3__usb_otg_ss1,
3390 &dra7xx_l4_per3__usb_otg_ss2,
3391 &dra7xx_l4_per3__usb_otg_ss3,
90020c7b
A		 3392 &dra7xx_l3_main_1__vcp1,
3393 &dra7xx_l4_per2__vcp1,
3394 &dra7xx_l3_main_1__vcp2,
3395 &dra7xx_l4_per2__vcp2,
3396 &dra7xx_l4_wkup__wd_timer2,
3397 NULL,
3398};
3399
f7f7a29b
RN		 3400static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3401 &dra7xx_l4_per3__usb_otg_ss4,
3402 NULL,
3403};
3404
3405static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3406 NULL,
3407};
3408
90020c7b
A		 3409int __init dra7xx_hwmod_init(void)
3410{
f7f7a29b
RN		 3411 int ret;
3412
90020c7b 3413 omap_hwmod_init();
f7f7a29b
RN		 3414 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3415
3416 if (!ret && soc_is_dra74x())
3417 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3418 else if (!ret && soc_is_dra72x())
3419 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
3420
3421 return ret;
90020c7b 3422}
Linux kernel - Deliverables
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