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4d38bd12 TL |
1 | /* |
2 | * DM81xx hwmod data. | |
3 | * | |
4 | * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ | |
5 | * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/ | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation version 2. | |
10 | * | |
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
12 | * kind, whether express or implied; without even the implied warranty | |
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/platform_data/gpio-omap.h> | |
19 | #include <linux/platform_data/hsmmc-omap.h> | |
20 | #include <linux/platform_data/spi-omap2-mcspi.h> | |
21 | #include <plat/dmtimer.h> | |
22 | ||
23 | #include "omap_hwmod_common_data.h" | |
24 | #include "cm81xx.h" | |
25 | #include "ti81xx.h" | |
26 | #include "wd_timer.h" | |
27 | ||
28 | /* | |
29 | * DM816X hardware modules integration data | |
30 | * | |
31 | * Note: This is incomplete and at present, not generated from h/w database. | |
32 | */ | |
33 | ||
34 | /* | |
7e1b11d1 TL |
35 | * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS" |
36 | * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400. | |
4d38bd12 | 37 | */ |
7e1b11d1 TL |
38 | #define DM81XX_CM_ALWON_MCASP0_CLKCTRL 0x140 |
39 | #define DM81XX_CM_ALWON_MCASP1_CLKCTRL 0x144 | |
40 | #define DM81XX_CM_ALWON_MCASP2_CLKCTRL 0x148 | |
41 | #define DM81XX_CM_ALWON_MCBSP_CLKCTRL 0x14c | |
42 | #define DM81XX_CM_ALWON_UART_0_CLKCTRL 0x150 | |
43 | #define DM81XX_CM_ALWON_UART_1_CLKCTRL 0x154 | |
44 | #define DM81XX_CM_ALWON_UART_2_CLKCTRL 0x158 | |
45 | #define DM81XX_CM_ALWON_GPIO_0_CLKCTRL 0x15c | |
46 | #define DM81XX_CM_ALWON_GPIO_1_CLKCTRL 0x160 | |
47 | #define DM81XX_CM_ALWON_I2C_0_CLKCTRL 0x164 | |
48 | #define DM81XX_CM_ALWON_I2C_1_CLKCTRL 0x168 | |
49 | #define DM81XX_CM_ALWON_WDTIMER_CLKCTRL 0x18c | |
50 | #define DM81XX_CM_ALWON_SPI_CLKCTRL 0x190 | |
51 | #define DM81XX_CM_ALWON_MAILBOX_CLKCTRL 0x194 | |
52 | #define DM81XX_CM_ALWON_SPINBOX_CLKCTRL 0x198 | |
53 | #define DM81XX_CM_ALWON_MMUDATA_CLKCTRL 0x19c | |
54 | #define DM81XX_CM_ALWON_MMUCFG_CLKCTRL 0x1a8 | |
55 | #define DM81XX_CM_ALWON_CONTROL_CLKCTRL 0x1c4 | |
56 | #define DM81XX_CM_ALWON_GPMC_CLKCTRL 0x1d0 | |
57 | #define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL 0x1d4 | |
58 | #define DM81XX_CM_ALWON_L3_CLKCTRL 0x1e4 | |
59 | #define DM81XX_CM_ALWON_L4HS_CLKCTRL 0x1e8 | |
60 | #define DM81XX_CM_ALWON_L4LS_CLKCTRL 0x1ec | |
61 | #define DM81XX_CM_ALWON_RTC_CLKCTRL 0x1f0 | |
62 | #define DM81XX_CM_ALWON_TPCC_CLKCTRL 0x1f4 | |
63 | #define DM81XX_CM_ALWON_TPTC0_CLKCTRL 0x1f8 | |
64 | #define DM81XX_CM_ALWON_TPTC1_CLKCTRL 0x1fc | |
65 | #define DM81XX_CM_ALWON_TPTC2_CLKCTRL 0x200 | |
66 | #define DM81XX_CM_ALWON_TPTC3_CLKCTRL 0x204 | |
67 | ||
68 | /* Registers specific to dm814x */ | |
69 | #define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL 0x16c | |
70 | #define DM814X_CM_ALWON_ATL_CLKCTRL 0x170 | |
71 | #define DM814X_CM_ALWON_MLB_CLKCTRL 0x174 | |
72 | #define DM814X_CM_ALWON_PATA_CLKCTRL 0x178 | |
73 | #define DM814X_CM_ALWON_UART_3_CLKCTRL 0x180 | |
74 | #define DM814X_CM_ALWON_UART_4_CLKCTRL 0x184 | |
75 | #define DM814X_CM_ALWON_UART_5_CLKCTRL 0x188 | |
76 | #define DM814X_CM_ALWON_OCM_0_CLKCTRL 0x1b4 | |
77 | #define DM814X_CM_ALWON_VCP_CLKCTRL 0x1b8 | |
78 | #define DM814X_CM_ALWON_MPU_CLKCTRL 0x1dc | |
79 | #define DM814X_CM_ALWON_DEBUGSS_CLKCTRL 0x1e0 | |
80 | #define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL 0x218 | |
81 | #define DM814X_CM_ALWON_MMCHS_0_CLKCTRL 0x21c | |
82 | #define DM814X_CM_ALWON_MMCHS_1_CLKCTRL 0x220 | |
83 | #define DM814X_CM_ALWON_MMCHS_2_CLKCTRL 0x224 | |
84 | #define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL 0x228 | |
85 | ||
86 | /* Registers specific to dm816x */ | |
4d38bd12 | 87 | #define DM816X_DM_ALWON_BASE 0x1400 |
4d38bd12 TL |
88 | #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE) |
89 | #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE) | |
90 | #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE) | |
91 | #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE) | |
92 | #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE) | |
93 | #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE) | |
94 | #define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE) | |
4d38bd12 TL |
95 | #define DM816X_CM_ALWON_SDIO_CLKCTRL (0x15b0 - DM816X_DM_ALWON_BASE) |
96 | #define DM816X_CM_ALWON_OCMC_0_CLKCTRL (0x15b4 - DM816X_DM_ALWON_BASE) | |
97 | #define DM816X_CM_ALWON_OCMC_1_CLKCTRL (0x15b8 - DM816X_DM_ALWON_BASE) | |
4d38bd12 TL |
98 | #define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE) |
99 | #define DM816X_CM_ALWON_MPU_CLKCTRL (0x15dc - DM816X_DM_ALWON_BASE) | |
4d38bd12 TL |
100 | #define DM816X_CM_ALWON_SR_0_CLKCTRL (0x1608 - DM816X_DM_ALWON_BASE) |
101 | #define DM816X_CM_ALWON_SR_1_CLKCTRL (0x160c - DM816X_DM_ALWON_BASE) | |
102 | ||
103 | /* | |
104 | * The default .clkctrl_offs field is offset from CM_DEFAULT, that's | |
105 | * TRM 18.7.6 CM_DEFAULT device register values minus 0x500 | |
106 | */ | |
f53850b5 TL |
107 | #define DM81XX_CM_DEFAULT_OFFSET 0x500 |
108 | #define DM81XX_CM_DEFAULT_USB_CLKCTRL (0x558 - DM81XX_CM_DEFAULT_OFFSET) | |
4d38bd12 TL |
109 | |
110 | /* L3 Interconnect entries clocked at 125, 250 and 500MHz */ | |
7e1b11d1 | 111 | static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = { |
4d38bd12 TL |
112 | .name = "alwon_l3_slow", |
113 | .clkdm_name = "alwon_l3s_clkdm", | |
114 | .class = &l3_hwmod_class, | |
115 | .flags = HWMOD_NO_IDLEST, | |
116 | }; | |
117 | ||
7e1b11d1 | 118 | static struct omap_hwmod dm81xx_default_l3_slow_hwmod = { |
4d38bd12 TL |
119 | .name = "default_l3_slow", |
120 | .clkdm_name = "default_l3_slow_clkdm", | |
121 | .class = &l3_hwmod_class, | |
122 | .flags = HWMOD_NO_IDLEST, | |
123 | }; | |
124 | ||
7e1b11d1 | 125 | static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = { |
4d38bd12 TL |
126 | .name = "l3_med", |
127 | .clkdm_name = "alwon_l3_med_clkdm", | |
128 | .class = &l3_hwmod_class, | |
129 | .flags = HWMOD_NO_IDLEST, | |
130 | }; | |
131 | ||
7e1b11d1 | 132 | static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = { |
4d38bd12 TL |
133 | .name = "l3_fast", |
134 | .clkdm_name = "alwon_l3_fast_clkdm", | |
135 | .class = &l3_hwmod_class, | |
136 | .flags = HWMOD_NO_IDLEST, | |
137 | }; | |
138 | ||
139 | /* | |
140 | * L4 standard peripherals, see TRM table 1-12 for devices using this. | |
141 | * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock. | |
142 | */ | |
7e1b11d1 | 143 | static struct omap_hwmod dm81xx_l4_ls_hwmod = { |
4d38bd12 TL |
144 | .name = "l4_ls", |
145 | .clkdm_name = "alwon_l3s_clkdm", | |
146 | .class = &l4_hwmod_class, | |
29f5b34c | 147 | .flags = HWMOD_NO_IDLEST, |
4d38bd12 TL |
148 | }; |
149 | ||
150 | /* | |
151 | * L4 high-speed peripherals. For devices using this, please see the TRM | |
152 | * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM | |
153 | * table 1-73 for devices using 250MHz SYSCLK5 clock. | |
154 | */ | |
7e1b11d1 | 155 | static struct omap_hwmod dm81xx_l4_hs_hwmod = { |
4d38bd12 TL |
156 | .name = "l4_hs", |
157 | .clkdm_name = "alwon_l3_med_clkdm", | |
158 | .class = &l4_hwmod_class, | |
29f5b34c | 159 | .flags = HWMOD_NO_IDLEST, |
4d38bd12 TL |
160 | }; |
161 | ||
162 | /* L3 slow -> L4 ls peripheral interface running at 125MHz */ | |
7e1b11d1 TL |
163 | static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = { |
164 | .master = &dm81xx_alwon_l3_slow_hwmod, | |
165 | .slave = &dm81xx_l4_ls_hwmod, | |
4d38bd12 TL |
166 | .user = OCP_USER_MPU, |
167 | }; | |
168 | ||
169 | /* L3 med -> L4 fast peripheral interface running at 250MHz */ | |
7e1b11d1 TL |
170 | static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = { |
171 | .master = &dm81xx_alwon_l3_med_hwmod, | |
172 | .slave = &dm81xx_l4_hs_hwmod, | |
4d38bd12 TL |
173 | .user = OCP_USER_MPU, |
174 | }; | |
175 | ||
176 | /* MPU */ | |
0f3ccb24 TL |
177 | static struct omap_hwmod dm814x_mpu_hwmod = { |
178 | .name = "mpu", | |
179 | .clkdm_name = "alwon_l3s_clkdm", | |
180 | .class = &mpu_hwmod_class, | |
181 | .flags = HWMOD_INIT_NO_IDLE, | |
182 | .main_clk = "mpu_ck", | |
183 | .prcm = { | |
184 | .omap4 = { | |
185 | .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL, | |
186 | .modulemode = MODULEMODE_SWCTRL, | |
187 | }, | |
188 | }, | |
189 | }; | |
190 | ||
191 | static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = { | |
192 | .master = &dm814x_mpu_hwmod, | |
193 | .slave = &dm81xx_alwon_l3_slow_hwmod, | |
194 | .user = OCP_USER_MPU, | |
195 | }; | |
196 | ||
197 | /* L3 med peripheral interface running at 200MHz */ | |
198 | static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = { | |
199 | .master = &dm814x_mpu_hwmod, | |
200 | .slave = &dm81xx_alwon_l3_med_hwmod, | |
201 | .user = OCP_USER_MPU, | |
202 | }; | |
203 | ||
4d38bd12 TL |
204 | static struct omap_hwmod dm816x_mpu_hwmod = { |
205 | .name = "mpu", | |
206 | .clkdm_name = "alwon_mpu_clkdm", | |
207 | .class = &mpu_hwmod_class, | |
208 | .flags = HWMOD_INIT_NO_IDLE, | |
209 | .main_clk = "mpu_ck", | |
210 | .prcm = { | |
211 | .omap4 = { | |
212 | .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL, | |
213 | .modulemode = MODULEMODE_SWCTRL, | |
214 | }, | |
215 | }, | |
216 | }; | |
217 | ||
218 | static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = { | |
219 | .master = &dm816x_mpu_hwmod, | |
7e1b11d1 | 220 | .slave = &dm81xx_alwon_l3_slow_hwmod, |
4d38bd12 TL |
221 | .user = OCP_USER_MPU, |
222 | }; | |
223 | ||
224 | /* L3 med peripheral interface running at 250MHz */ | |
225 | static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = { | |
226 | .master = &dm816x_mpu_hwmod, | |
7e1b11d1 | 227 | .slave = &dm81xx_alwon_l3_med_hwmod, |
4d38bd12 TL |
228 | .user = OCP_USER_MPU, |
229 | }; | |
230 | ||
231 | /* UART common */ | |
232 | static struct omap_hwmod_class_sysconfig uart_sysc = { | |
233 | .rev_offs = 0x50, | |
234 | .sysc_offs = 0x54, | |
235 | .syss_offs = 0x58, | |
236 | .sysc_flags = SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
237 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
238 | SYSS_HAS_RESET_STATUS, | |
239 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
240 | MSTANDBY_SMART_WKUP, | |
241 | .sysc_fields = &omap_hwmod_sysc_type1, | |
242 | }; | |
243 | ||
244 | static struct omap_hwmod_class uart_class = { | |
245 | .name = "uart", | |
246 | .sysc = &uart_sysc, | |
247 | }; | |
248 | ||
7e1b11d1 | 249 | static struct omap_hwmod dm81xx_uart1_hwmod = { |
4d38bd12 TL |
250 | .name = "uart1", |
251 | .clkdm_name = "alwon_l3s_clkdm", | |
252 | .main_clk = "sysclk10_ck", | |
253 | .prcm = { | |
254 | .omap4 = { | |
7e1b11d1 | 255 | .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL, |
4d38bd12 TL |
256 | .modulemode = MODULEMODE_SWCTRL, |
257 | }, | |
258 | }, | |
259 | .class = &uart_class, | |
260 | .flags = DEBUG_TI81XXUART1_FLAGS, | |
261 | }; | |
262 | ||
7e1b11d1 TL |
263 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = { |
264 | .master = &dm81xx_l4_ls_hwmod, | |
265 | .slave = &dm81xx_uart1_hwmod, | |
4d38bd12 TL |
266 | .clk = "sysclk6_ck", |
267 | .user = OCP_USER_MPU, | |
268 | }; | |
269 | ||
7e1b11d1 | 270 | static struct omap_hwmod dm81xx_uart2_hwmod = { |
4d38bd12 TL |
271 | .name = "uart2", |
272 | .clkdm_name = "alwon_l3s_clkdm", | |
273 | .main_clk = "sysclk10_ck", | |
274 | .prcm = { | |
275 | .omap4 = { | |
7e1b11d1 | 276 | .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL, |
4d38bd12 TL |
277 | .modulemode = MODULEMODE_SWCTRL, |
278 | }, | |
279 | }, | |
280 | .class = &uart_class, | |
281 | .flags = DEBUG_TI81XXUART2_FLAGS, | |
282 | }; | |
283 | ||
7e1b11d1 TL |
284 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = { |
285 | .master = &dm81xx_l4_ls_hwmod, | |
286 | .slave = &dm81xx_uart2_hwmod, | |
4d38bd12 TL |
287 | .clk = "sysclk6_ck", |
288 | .user = OCP_USER_MPU, | |
289 | }; | |
290 | ||
7e1b11d1 | 291 | static struct omap_hwmod dm81xx_uart3_hwmod = { |
4d38bd12 TL |
292 | .name = "uart3", |
293 | .clkdm_name = "alwon_l3s_clkdm", | |
294 | .main_clk = "sysclk10_ck", | |
295 | .prcm = { | |
296 | .omap4 = { | |
7e1b11d1 | 297 | .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL, |
4d38bd12 TL |
298 | .modulemode = MODULEMODE_SWCTRL, |
299 | }, | |
300 | }, | |
301 | .class = &uart_class, | |
302 | .flags = DEBUG_TI81XXUART3_FLAGS, | |
303 | }; | |
304 | ||
7e1b11d1 TL |
305 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = { |
306 | .master = &dm81xx_l4_ls_hwmod, | |
307 | .slave = &dm81xx_uart3_hwmod, | |
4d38bd12 TL |
308 | .clk = "sysclk6_ck", |
309 | .user = OCP_USER_MPU, | |
310 | }; | |
311 | ||
312 | static struct omap_hwmod_class_sysconfig wd_timer_sysc = { | |
313 | .rev_offs = 0x0, | |
314 | .sysc_offs = 0x10, | |
315 | .syss_offs = 0x14, | |
316 | .sysc_flags = SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | | |
317 | SYSS_HAS_RESET_STATUS, | |
318 | .sysc_fields = &omap_hwmod_sysc_type1, | |
319 | }; | |
320 | ||
321 | static struct omap_hwmod_class wd_timer_class = { | |
322 | .name = "wd_timer", | |
323 | .sysc = &wd_timer_sysc, | |
324 | .pre_shutdown = &omap2_wd_timer_disable, | |
325 | .reset = &omap2_wd_timer_reset, | |
326 | }; | |
327 | ||
7e1b11d1 | 328 | static struct omap_hwmod dm81xx_wd_timer_hwmod = { |
4d38bd12 TL |
329 | .name = "wd_timer", |
330 | .clkdm_name = "alwon_l3s_clkdm", | |
331 | .main_clk = "sysclk18_ck", | |
332 | .flags = HWMOD_NO_IDLEST, | |
333 | .prcm = { | |
334 | .omap4 = { | |
7e1b11d1 | 335 | .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL, |
4d38bd12 TL |
336 | .modulemode = MODULEMODE_SWCTRL, |
337 | }, | |
338 | }, | |
339 | .class = &wd_timer_class, | |
340 | }; | |
341 | ||
7e1b11d1 TL |
342 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = { |
343 | .master = &dm81xx_l4_ls_hwmod, | |
344 | .slave = &dm81xx_wd_timer_hwmod, | |
4d38bd12 TL |
345 | .clk = "sysclk6_ck", |
346 | .user = OCP_USER_MPU, | |
347 | }; | |
348 | ||
349 | /* I2C common */ | |
350 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
351 | .rev_offs = 0x0, | |
352 | .sysc_offs = 0x10, | |
353 | .syss_offs = 0x90, | |
354 | .sysc_flags = SYSC_HAS_SIDLEMODE | | |
355 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
356 | SYSC_HAS_AUTOIDLE, | |
357 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, | |
358 | .sysc_fields = &omap_hwmod_sysc_type1, | |
359 | }; | |
360 | ||
361 | static struct omap_hwmod_class i2c_class = { | |
362 | .name = "i2c", | |
363 | .sysc = &i2c_sysc, | |
364 | }; | |
365 | ||
366 | static struct omap_hwmod dm81xx_i2c1_hwmod = { | |
367 | .name = "i2c1", | |
368 | .clkdm_name = "alwon_l3s_clkdm", | |
369 | .main_clk = "sysclk10_ck", | |
370 | .prcm = { | |
371 | .omap4 = { | |
7e1b11d1 | 372 | .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL, |
4d38bd12 TL |
373 | .modulemode = MODULEMODE_SWCTRL, |
374 | }, | |
375 | }, | |
376 | .class = &i2c_class, | |
377 | }; | |
378 | ||
7e1b11d1 TL |
379 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = { |
380 | .master = &dm81xx_l4_ls_hwmod, | |
4d38bd12 TL |
381 | .slave = &dm81xx_i2c1_hwmod, |
382 | .clk = "sysclk6_ck", | |
383 | .user = OCP_USER_MPU, | |
384 | }; | |
385 | ||
7e1b11d1 | 386 | static struct omap_hwmod dm81xx_i2c2_hwmod = { |
4d38bd12 TL |
387 | .name = "i2c2", |
388 | .clkdm_name = "alwon_l3s_clkdm", | |
389 | .main_clk = "sysclk10_ck", | |
390 | .prcm = { | |
391 | .omap4 = { | |
7e1b11d1 | 392 | .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL, |
4d38bd12 TL |
393 | .modulemode = MODULEMODE_SWCTRL, |
394 | }, | |
395 | }, | |
396 | .class = &i2c_class, | |
397 | }; | |
398 | ||
399 | static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = { | |
400 | .rev_offs = 0x0000, | |
401 | .sysc_offs = 0x0010, | |
402 | .syss_offs = 0x0014, | |
403 | .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
404 | SYSC_HAS_SOFTRESET | | |
405 | SYSS_HAS_RESET_STATUS, | |
406 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, | |
407 | .sysc_fields = &omap_hwmod_sysc_type1, | |
408 | }; | |
409 | ||
7e1b11d1 TL |
410 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = { |
411 | .master = &dm81xx_l4_ls_hwmod, | |
412 | .slave = &dm81xx_i2c2_hwmod, | |
4d38bd12 TL |
413 | .clk = "sysclk6_ck", |
414 | .user = OCP_USER_MPU, | |
415 | }; | |
416 | ||
417 | static struct omap_hwmod_class dm81xx_elm_hwmod_class = { | |
418 | .name = "elm", | |
419 | .sysc = &dm81xx_elm_sysc, | |
420 | }; | |
421 | ||
422 | static struct omap_hwmod dm81xx_elm_hwmod = { | |
423 | .name = "elm", | |
424 | .clkdm_name = "alwon_l3s_clkdm", | |
425 | .class = &dm81xx_elm_hwmod_class, | |
426 | .main_clk = "sysclk6_ck", | |
427 | }; | |
428 | ||
429 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = { | |
7e1b11d1 | 430 | .master = &dm81xx_l4_ls_hwmod, |
4d38bd12 TL |
431 | .slave = &dm81xx_elm_hwmod, |
432 | .user = OCP_USER_MPU, | |
433 | }; | |
434 | ||
435 | static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = { | |
436 | .rev_offs = 0x0000, | |
437 | .sysc_offs = 0x0010, | |
438 | .syss_offs = 0x0114, | |
439 | .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
440 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
441 | SYSS_HAS_RESET_STATUS, | |
442 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
443 | SIDLE_SMART_WKUP, | |
444 | .sysc_fields = &omap_hwmod_sysc_type1, | |
445 | }; | |
446 | ||
447 | static struct omap_hwmod_class dm81xx_gpio_hwmod_class = { | |
448 | .name = "gpio", | |
449 | .sysc = &dm81xx_gpio_sysc, | |
450 | .rev = 2, | |
451 | }; | |
452 | ||
453 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
454 | .bank_width = 32, | |
455 | .dbck_flag = true, | |
456 | }; | |
457 | ||
458 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | |
459 | { .role = "dbclk", .clk = "sysclk18_ck" }, | |
460 | }; | |
461 | ||
462 | static struct omap_hwmod dm81xx_gpio1_hwmod = { | |
463 | .name = "gpio1", | |
464 | .clkdm_name = "alwon_l3s_clkdm", | |
465 | .class = &dm81xx_gpio_hwmod_class, | |
466 | .main_clk = "sysclk6_ck", | |
467 | .prcm = { | |
468 | .omap4 = { | |
7e1b11d1 | 469 | .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL, |
4d38bd12 TL |
470 | .modulemode = MODULEMODE_SWCTRL, |
471 | }, | |
472 | }, | |
473 | .opt_clks = gpio1_opt_clks, | |
474 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
475 | .dev_attr = &gpio_dev_attr, | |
476 | }; | |
477 | ||
478 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = { | |
7e1b11d1 | 479 | .master = &dm81xx_l4_ls_hwmod, |
4d38bd12 TL |
480 | .slave = &dm81xx_gpio1_hwmod, |
481 | .user = OCP_USER_MPU, | |
482 | }; | |
483 | ||
484 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | |
485 | { .role = "dbclk", .clk = "sysclk18_ck" }, | |
486 | }; | |
487 | ||
488 | static struct omap_hwmod dm81xx_gpio2_hwmod = { | |
489 | .name = "gpio2", | |
490 | .clkdm_name = "alwon_l3s_clkdm", | |
491 | .class = &dm81xx_gpio_hwmod_class, | |
492 | .main_clk = "sysclk6_ck", | |
493 | .prcm = { | |
494 | .omap4 = { | |
7e1b11d1 | 495 | .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL, |
4d38bd12 TL |
496 | .modulemode = MODULEMODE_SWCTRL, |
497 | }, | |
498 | }, | |
499 | .opt_clks = gpio2_opt_clks, | |
500 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
501 | .dev_attr = &gpio_dev_attr, | |
502 | }; | |
503 | ||
504 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = { | |
7e1b11d1 | 505 | .master = &dm81xx_l4_ls_hwmod, |
4d38bd12 TL |
506 | .slave = &dm81xx_gpio2_hwmod, |
507 | .user = OCP_USER_MPU, | |
508 | }; | |
509 | ||
510 | static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = { | |
511 | .rev_offs = 0x0, | |
512 | .sysc_offs = 0x10, | |
513 | .syss_offs = 0x14, | |
514 | .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
515 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, | |
516 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, | |
517 | .sysc_fields = &omap_hwmod_sysc_type1, | |
518 | }; | |
519 | ||
520 | static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = { | |
521 | .name = "gpmc", | |
522 | .sysc = &dm81xx_gpmc_sysc, | |
523 | }; | |
524 | ||
525 | static struct omap_hwmod dm81xx_gpmc_hwmod = { | |
526 | .name = "gpmc", | |
527 | .clkdm_name = "alwon_l3s_clkdm", | |
528 | .class = &dm81xx_gpmc_hwmod_class, | |
529 | .main_clk = "sysclk6_ck", | |
63aa945b TL |
530 | /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ |
531 | .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, | |
4d38bd12 TL |
532 | .prcm = { |
533 | .omap4 = { | |
7e1b11d1 | 534 | .clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL, |
4d38bd12 TL |
535 | .modulemode = MODULEMODE_SWCTRL, |
536 | }, | |
537 | }, | |
538 | }; | |
539 | ||
f734a9b3 | 540 | static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = { |
7e1b11d1 | 541 | .master = &dm81xx_alwon_l3_slow_hwmod, |
4d38bd12 TL |
542 | .slave = &dm81xx_gpmc_hwmod, |
543 | .user = OCP_USER_MPU, | |
544 | }; | |
545 | ||
546 | static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = { | |
547 | .rev_offs = 0x0, | |
548 | .sysc_offs = 0x10, | |
549 | .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | | |
550 | SYSC_HAS_SOFTRESET, | |
551 | .idlemodes = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART, | |
552 | .sysc_fields = &omap_hwmod_sysc_type2, | |
553 | }; | |
554 | ||
555 | static struct omap_hwmod_class dm81xx_usbotg_class = { | |
556 | .name = "usbotg", | |
557 | .sysc = &dm81xx_usbhsotg_sysc, | |
558 | }; | |
559 | ||
f53850b5 TL |
560 | static struct omap_hwmod dm814x_usbss_hwmod = { |
561 | .name = "usb_otg_hs", | |
562 | .clkdm_name = "default_l3_slow_clkdm", | |
563 | .main_clk = "pll260dcoclkldo", /* 481c5260.adpll.dcoclkldo */ | |
564 | .prcm = { | |
565 | .omap4 = { | |
566 | .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL, | |
567 | .modulemode = MODULEMODE_SWCTRL, | |
568 | }, | |
569 | }, | |
570 | .class = &dm81xx_usbotg_class, | |
571 | }; | |
572 | ||
573 | static struct omap_hwmod_ocp_if dm814x_default_l3_slow__usbss = { | |
574 | .master = &dm81xx_default_l3_slow_hwmod, | |
575 | .slave = &dm814x_usbss_hwmod, | |
576 | .clk = "sysclk6_ck", | |
577 | .user = OCP_USER_MPU, | |
578 | }; | |
579 | ||
580 | static struct omap_hwmod dm816x_usbss_hwmod = { | |
4d38bd12 TL |
581 | .name = "usb_otg_hs", |
582 | .clkdm_name = "default_l3_slow_clkdm", | |
583 | .main_clk = "sysclk6_ck", | |
584 | .prcm = { | |
585 | .omap4 = { | |
f53850b5 | 586 | .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL, |
4d38bd12 TL |
587 | .modulemode = MODULEMODE_SWCTRL, |
588 | }, | |
589 | }, | |
590 | .class = &dm81xx_usbotg_class, | |
591 | }; | |
592 | ||
f53850b5 | 593 | static struct omap_hwmod_ocp_if dm816x_default_l3_slow__usbss = { |
7e1b11d1 | 594 | .master = &dm81xx_default_l3_slow_hwmod, |
f53850b5 | 595 | .slave = &dm816x_usbss_hwmod, |
4d38bd12 TL |
596 | .clk = "sysclk6_ck", |
597 | .user = OCP_USER_MPU, | |
598 | }; | |
599 | ||
600 | static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = { | |
601 | .rev_offs = 0x0000, | |
602 | .sysc_offs = 0x0010, | |
603 | .syss_offs = 0x0014, | |
604 | .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET, | |
605 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
606 | SIDLE_SMART_WKUP, | |
607 | .sysc_fields = &omap_hwmod_sysc_type2, | |
608 | }; | |
609 | ||
610 | static struct omap_hwmod_class dm816x_timer_hwmod_class = { | |
611 | .name = "timer", | |
612 | .sysc = &dm816x_timer_sysc, | |
613 | }; | |
614 | ||
615 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
616 | .timer_capability = OMAP_TIMER_ALWON, | |
617 | }; | |
618 | ||
0f3ccb24 TL |
619 | static struct omap_hwmod dm814x_timer1_hwmod = { |
620 | .name = "timer1", | |
621 | .clkdm_name = "alwon_l3s_clkdm", | |
cb4db038 | 622 | .main_clk = "timer1_fck", |
0f3ccb24 TL |
623 | .dev_attr = &capability_alwon_dev_attr, |
624 | .class = &dm816x_timer_hwmod_class, | |
625 | .flags = HWMOD_NO_IDLEST, | |
626 | }; | |
627 | ||
628 | static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = { | |
629 | .master = &dm81xx_l4_ls_hwmod, | |
630 | .slave = &dm814x_timer1_hwmod, | |
cb4db038 | 631 | .clk = "timer1_fck", |
0f3ccb24 TL |
632 | .user = OCP_USER_MPU, |
633 | }; | |
634 | ||
4d38bd12 TL |
635 | static struct omap_hwmod dm816x_timer1_hwmod = { |
636 | .name = "timer1", | |
637 | .clkdm_name = "alwon_l3s_clkdm", | |
638 | .main_clk = "timer1_fck", | |
639 | .prcm = { | |
640 | .omap4 = { | |
641 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL, | |
642 | .modulemode = MODULEMODE_SWCTRL, | |
643 | }, | |
644 | }, | |
645 | .dev_attr = &capability_alwon_dev_attr, | |
646 | .class = &dm816x_timer_hwmod_class, | |
647 | }; | |
648 | ||
649 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = { | |
7e1b11d1 | 650 | .master = &dm81xx_l4_ls_hwmod, |
4d38bd12 TL |
651 | .slave = &dm816x_timer1_hwmod, |
652 | .clk = "sysclk6_ck", | |
653 | .user = OCP_USER_MPU, | |
654 | }; | |
655 | ||
0f3ccb24 TL |
656 | static struct omap_hwmod dm814x_timer2_hwmod = { |
657 | .name = "timer2", | |
658 | .clkdm_name = "alwon_l3s_clkdm", | |
cb4db038 | 659 | .main_clk = "timer2_fck", |
0f3ccb24 TL |
660 | .dev_attr = &capability_alwon_dev_attr, |
661 | .class = &dm816x_timer_hwmod_class, | |
662 | .flags = HWMOD_NO_IDLEST, | |
663 | }; | |
664 | ||
665 | static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = { | |
666 | .master = &dm81xx_l4_ls_hwmod, | |
667 | .slave = &dm814x_timer2_hwmod, | |
cb4db038 | 668 | .clk = "timer2_fck", |
0f3ccb24 TL |
669 | .user = OCP_USER_MPU, |
670 | }; | |
671 | ||
4d38bd12 TL |
672 | static struct omap_hwmod dm816x_timer2_hwmod = { |
673 | .name = "timer2", | |
674 | .clkdm_name = "alwon_l3s_clkdm", | |
675 | .main_clk = "timer2_fck", | |
676 | .prcm = { | |
677 | .omap4 = { | |
678 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL, | |
679 | .modulemode = MODULEMODE_SWCTRL, | |
680 | }, | |
681 | }, | |
682 | .dev_attr = &capability_alwon_dev_attr, | |
683 | .class = &dm816x_timer_hwmod_class, | |
684 | }; | |
685 | ||
686 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = { | |
7e1b11d1 | 687 | .master = &dm81xx_l4_ls_hwmod, |
4d38bd12 TL |
688 | .slave = &dm816x_timer2_hwmod, |
689 | .clk = "sysclk6_ck", | |
690 | .user = OCP_USER_MPU, | |
691 | }; | |
692 | ||
693 | static struct omap_hwmod dm816x_timer3_hwmod = { | |
694 | .name = "timer3", | |
695 | .clkdm_name = "alwon_l3s_clkdm", | |
696 | .main_clk = "timer3_fck", | |
697 | .prcm = { | |
698 | .omap4 = { | |
699 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL, | |
700 | .modulemode = MODULEMODE_SWCTRL, | |
701 | }, | |
702 | }, | |
703 | .dev_attr = &capability_alwon_dev_attr, | |
704 | .class = &dm816x_timer_hwmod_class, | |
705 | }; | |
706 | ||
707 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = { | |
7e1b11d1 | 708 | .master = &dm81xx_l4_ls_hwmod, |
4d38bd12 TL |
709 | .slave = &dm816x_timer3_hwmod, |
710 | .clk = "sysclk6_ck", | |
711 | .user = OCP_USER_MPU, | |
712 | }; | |
713 | ||
714 | static struct omap_hwmod dm816x_timer4_hwmod = { | |
715 | .name = "timer4", | |
716 | .clkdm_name = "alwon_l3s_clkdm", | |
717 | .main_clk = "timer4_fck", | |
718 | .prcm = { | |
719 | .omap4 = { | |
720 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL, | |
721 | .modulemode = MODULEMODE_SWCTRL, | |
722 | }, | |
723 | }, | |
724 | .dev_attr = &capability_alwon_dev_attr, | |
725 | .class = &dm816x_timer_hwmod_class, | |
726 | }; | |
727 | ||
728 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = { | |
7e1b11d1 | 729 | .master = &dm81xx_l4_ls_hwmod, |
4d38bd12 TL |
730 | .slave = &dm816x_timer4_hwmod, |
731 | .clk = "sysclk6_ck", | |
732 | .user = OCP_USER_MPU, | |
733 | }; | |
734 | ||
735 | static struct omap_hwmod dm816x_timer5_hwmod = { | |
736 | .name = "timer5", | |
737 | .clkdm_name = "alwon_l3s_clkdm", | |
738 | .main_clk = "timer5_fck", | |
739 | .prcm = { | |
740 | .omap4 = { | |
741 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL, | |
742 | .modulemode = MODULEMODE_SWCTRL, | |
743 | }, | |
744 | }, | |
745 | .dev_attr = &capability_alwon_dev_attr, | |
746 | .class = &dm816x_timer_hwmod_class, | |
747 | }; | |
748 | ||
749 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = { | |
7e1b11d1 | 750 | .master = &dm81xx_l4_ls_hwmod, |
4d38bd12 TL |
751 | .slave = &dm816x_timer5_hwmod, |
752 | .clk = "sysclk6_ck", | |
753 | .user = OCP_USER_MPU, | |
754 | }; | |
755 | ||
756 | static struct omap_hwmod dm816x_timer6_hwmod = { | |
757 | .name = "timer6", | |
758 | .clkdm_name = "alwon_l3s_clkdm", | |
759 | .main_clk = "timer6_fck", | |
760 | .prcm = { | |
761 | .omap4 = { | |
762 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL, | |
763 | .modulemode = MODULEMODE_SWCTRL, | |
764 | }, | |
765 | }, | |
766 | .dev_attr = &capability_alwon_dev_attr, | |
767 | .class = &dm816x_timer_hwmod_class, | |
768 | }; | |
769 | ||
770 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = { | |
7e1b11d1 | 771 | .master = &dm81xx_l4_ls_hwmod, |
4d38bd12 TL |
772 | .slave = &dm816x_timer6_hwmod, |
773 | .clk = "sysclk6_ck", | |
774 | .user = OCP_USER_MPU, | |
775 | }; | |
776 | ||
777 | static struct omap_hwmod dm816x_timer7_hwmod = { | |
778 | .name = "timer7", | |
779 | .clkdm_name = "alwon_l3s_clkdm", | |
780 | .main_clk = "timer7_fck", | |
781 | .prcm = { | |
782 | .omap4 = { | |
783 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL, | |
784 | .modulemode = MODULEMODE_SWCTRL, | |
785 | }, | |
786 | }, | |
787 | .dev_attr = &capability_alwon_dev_attr, | |
788 | .class = &dm816x_timer_hwmod_class, | |
789 | }; | |
790 | ||
791 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = { | |
7e1b11d1 | 792 | .master = &dm81xx_l4_ls_hwmod, |
4d38bd12 TL |
793 | .slave = &dm816x_timer7_hwmod, |
794 | .clk = "sysclk6_ck", | |
795 | .user = OCP_USER_MPU, | |
796 | }; | |
797 | ||
0f3ccb24 TL |
798 | /* CPSW on dm814x */ |
799 | static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = { | |
800 | .rev_offs = 0x0, | |
801 | .sysc_offs = 0x8, | |
802 | .syss_offs = 0x4, | |
803 | .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | | |
804 | SYSS_HAS_RESET_STATUS, | |
805 | .idlemodes = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | | |
806 | MSTANDBY_NO, | |
807 | .sysc_fields = &omap_hwmod_sysc_type3, | |
808 | }; | |
809 | ||
810 | static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = { | |
811 | .name = "cpgmac0", | |
812 | .sysc = &dm814x_cpgmac_sysc, | |
813 | }; | |
814 | ||
24da741c | 815 | static struct omap_hwmod dm814x_cpgmac0_hwmod = { |
0f3ccb24 TL |
816 | .name = "cpgmac0", |
817 | .class = &dm814x_cpgmac0_hwmod_class, | |
818 | .clkdm_name = "alwon_ethernet_clkdm", | |
819 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | |
820 | .main_clk = "cpsw_125mhz_gclk", | |
821 | .prcm = { | |
822 | .omap4 = { | |
823 | .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL, | |
824 | .modulemode = MODULEMODE_SWCTRL, | |
825 | }, | |
826 | }, | |
827 | }; | |
828 | ||
829 | static struct omap_hwmod_class dm814x_mdio_hwmod_class = { | |
830 | .name = "davinci_mdio", | |
831 | }; | |
832 | ||
24da741c | 833 | static struct omap_hwmod dm814x_mdio_hwmod = { |
0f3ccb24 TL |
834 | .name = "davinci_mdio", |
835 | .class = &dm814x_mdio_hwmod_class, | |
836 | .clkdm_name = "alwon_ethernet_clkdm", | |
837 | .main_clk = "cpsw_125mhz_gclk", | |
838 | }; | |
839 | ||
840 | static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = { | |
841 | .master = &dm81xx_l4_hs_hwmod, | |
842 | .slave = &dm814x_cpgmac0_hwmod, | |
843 | .clk = "cpsw_125mhz_gclk", | |
844 | .user = OCP_USER_MPU, | |
845 | }; | |
846 | ||
24da741c | 847 | static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = { |
0f3ccb24 TL |
848 | .master = &dm814x_cpgmac0_hwmod, |
849 | .slave = &dm814x_mdio_hwmod, | |
850 | .user = OCP_USER_MPU, | |
851 | .flags = HWMOD_NO_IDLEST, | |
852 | }; | |
853 | ||
4d38bd12 TL |
854 | /* EMAC Ethernet */ |
855 | static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = { | |
856 | .rev_offs = 0x0, | |
857 | .sysc_offs = 0x4, | |
858 | .sysc_flags = SYSC_HAS_SOFTRESET, | |
859 | .sysc_fields = &omap_hwmod_sysc_type2, | |
860 | }; | |
861 | ||
862 | static struct omap_hwmod_class dm816x_emac_hwmod_class = { | |
863 | .name = "emac", | |
864 | .sysc = &dm816x_emac_sysc, | |
865 | }; | |
866 | ||
867 | /* | |
868 | * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate | |
869 | * driver probed before EMAC0, we let MDIO do the clock idling. | |
870 | */ | |
871 | static struct omap_hwmod dm816x_emac0_hwmod = { | |
872 | .name = "emac0", | |
873 | .clkdm_name = "alwon_ethernet_clkdm", | |
874 | .class = &dm816x_emac_hwmod_class, | |
29f5b34c | 875 | .flags = HWMOD_NO_IDLEST, |
4d38bd12 TL |
876 | }; |
877 | ||
7e1b11d1 TL |
878 | static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = { |
879 | .master = &dm81xx_l4_hs_hwmod, | |
4d38bd12 TL |
880 | .slave = &dm816x_emac0_hwmod, |
881 | .clk = "sysclk5_ck", | |
882 | .user = OCP_USER_MPU, | |
883 | }; | |
884 | ||
7e1b11d1 | 885 | static struct omap_hwmod_class dm81xx_mdio_hwmod_class = { |
4d38bd12 TL |
886 | .name = "davinci_mdio", |
887 | .sysc = &dm816x_emac_sysc, | |
888 | }; | |
889 | ||
24da741c | 890 | static struct omap_hwmod dm81xx_emac0_mdio_hwmod = { |
4d38bd12 | 891 | .name = "davinci_mdio", |
7e1b11d1 | 892 | .class = &dm81xx_mdio_hwmod_class, |
4d38bd12 TL |
893 | .clkdm_name = "alwon_ethernet_clkdm", |
894 | .main_clk = "sysclk24_ck", | |
895 | .flags = HWMOD_NO_IDLEST, | |
896 | /* | |
897 | * REVISIT: This should be moved to the emac0_hwmod | |
898 | * once we have a better way to handle device slaves. | |
899 | */ | |
900 | .prcm = { | |
901 | .omap4 = { | |
7e1b11d1 | 902 | .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL, |
4d38bd12 TL |
903 | .modulemode = MODULEMODE_SWCTRL, |
904 | }, | |
905 | }, | |
906 | }; | |
907 | ||
24da741c | 908 | static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = { |
7e1b11d1 TL |
909 | .master = &dm81xx_l4_hs_hwmod, |
910 | .slave = &dm81xx_emac0_mdio_hwmod, | |
4d38bd12 TL |
911 | .user = OCP_USER_MPU, |
912 | }; | |
913 | ||
914 | static struct omap_hwmod dm816x_emac1_hwmod = { | |
915 | .name = "emac1", | |
916 | .clkdm_name = "alwon_ethernet_clkdm", | |
917 | .main_clk = "sysclk24_ck", | |
918 | .flags = HWMOD_NO_IDLEST, | |
919 | .prcm = { | |
920 | .omap4 = { | |
921 | .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL, | |
922 | .modulemode = MODULEMODE_SWCTRL, | |
923 | }, | |
924 | }, | |
925 | .class = &dm816x_emac_hwmod_class, | |
926 | }; | |
927 | ||
928 | static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = { | |
7e1b11d1 | 929 | .master = &dm81xx_l4_hs_hwmod, |
4d38bd12 TL |
930 | .slave = &dm816x_emac1_hwmod, |
931 | .clk = "sysclk5_ck", | |
932 | .user = OCP_USER_MPU, | |
933 | }; | |
934 | ||
c757fda8 | 935 | static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = { |
4d38bd12 TL |
936 | .rev_offs = 0x0, |
937 | .sysc_offs = 0x110, | |
938 | .syss_offs = 0x114, | |
939 | .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
940 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
941 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, | |
942 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, | |
943 | .sysc_fields = &omap_hwmod_sysc_type1, | |
944 | }; | |
945 | ||
c757fda8 | 946 | static struct omap_hwmod_class dm81xx_mmc_class = { |
4d38bd12 | 947 | .name = "mmc", |
c757fda8 | 948 | .sysc = &dm81xx_mmc_sysc, |
4d38bd12 TL |
949 | }; |
950 | ||
c757fda8 | 951 | static struct omap_hwmod_opt_clk dm81xx_mmc_opt_clks[] = { |
4d38bd12 TL |
952 | { .role = "dbck", .clk = "sysclk18_ck", }, |
953 | }; | |
954 | ||
c757fda8 TL |
955 | static struct omap_hsmmc_dev_attr mmc_dev_attr = { |
956 | }; | |
957 | ||
958 | static struct omap_hwmod dm814x_mmc1_hwmod = { | |
959 | .name = "mmc1", | |
960 | .clkdm_name = "alwon_l3s_clkdm", | |
961 | .opt_clks = dm81xx_mmc_opt_clks, | |
962 | .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), | |
963 | .main_clk = "sysclk8_ck", | |
964 | .prcm = { | |
965 | .omap4 = { | |
966 | .clkctrl_offs = DM814X_CM_ALWON_MMCHS_0_CLKCTRL, | |
967 | .modulemode = MODULEMODE_SWCTRL, | |
968 | }, | |
969 | }, | |
970 | .dev_attr = &mmc_dev_attr, | |
971 | .class = &dm81xx_mmc_class, | |
972 | }; | |
973 | ||
974 | static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc1 = { | |
975 | .master = &dm81xx_l4_ls_hwmod, | |
976 | .slave = &dm814x_mmc1_hwmod, | |
977 | .clk = "sysclk6_ck", | |
978 | .user = OCP_USER_MPU, | |
979 | .flags = OMAP_FIREWALL_L4 | |
980 | }; | |
981 | ||
982 | static struct omap_hwmod dm814x_mmc2_hwmod = { | |
983 | .name = "mmc2", | |
984 | .clkdm_name = "alwon_l3s_clkdm", | |
985 | .opt_clks = dm81xx_mmc_opt_clks, | |
986 | .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), | |
987 | .main_clk = "sysclk8_ck", | |
988 | .prcm = { | |
989 | .omap4 = { | |
990 | .clkctrl_offs = DM814X_CM_ALWON_MMCHS_1_CLKCTRL, | |
991 | .modulemode = MODULEMODE_SWCTRL, | |
992 | }, | |
993 | }, | |
994 | .dev_attr = &mmc_dev_attr, | |
995 | .class = &dm81xx_mmc_class, | |
996 | }; | |
997 | ||
998 | static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc2 = { | |
999 | .master = &dm81xx_l4_ls_hwmod, | |
1000 | .slave = &dm814x_mmc2_hwmod, | |
1001 | .clk = "sysclk6_ck", | |
1002 | .user = OCP_USER_MPU, | |
1003 | .flags = OMAP_FIREWALL_L4 | |
1004 | }; | |
1005 | ||
1006 | static struct omap_hwmod dm814x_mmc3_hwmod = { | |
1007 | .name = "mmc3", | |
1008 | .clkdm_name = "alwon_l3_med_clkdm", | |
1009 | .opt_clks = dm81xx_mmc_opt_clks, | |
1010 | .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), | |
1011 | .main_clk = "sysclk8_ck", | |
1012 | .prcm = { | |
1013 | .omap4 = { | |
1014 | .clkctrl_offs = DM814X_CM_ALWON_MMCHS_2_CLKCTRL, | |
1015 | .modulemode = MODULEMODE_SWCTRL, | |
1016 | }, | |
1017 | }, | |
1018 | .dev_attr = &mmc_dev_attr, | |
1019 | .class = &dm81xx_mmc_class, | |
1020 | }; | |
1021 | ||
1022 | static struct omap_hwmod_ocp_if dm814x_alwon_l3_med__mmc3 = { | |
1023 | .master = &dm81xx_alwon_l3_med_hwmod, | |
1024 | .slave = &dm814x_mmc3_hwmod, | |
1025 | .clk = "sysclk4_ck", | |
1026 | .user = OCP_USER_MPU, | |
4d38bd12 TL |
1027 | }; |
1028 | ||
1029 | static struct omap_hwmod dm816x_mmc1_hwmod = { | |
1030 | .name = "mmc1", | |
1031 | .clkdm_name = "alwon_l3s_clkdm", | |
c757fda8 TL |
1032 | .opt_clks = dm81xx_mmc_opt_clks, |
1033 | .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), | |
4d38bd12 TL |
1034 | .main_clk = "sysclk10_ck", |
1035 | .prcm = { | |
1036 | .omap4 = { | |
1037 | .clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL, | |
1038 | .modulemode = MODULEMODE_SWCTRL, | |
1039 | }, | |
1040 | }, | |
c757fda8 TL |
1041 | .dev_attr = &mmc_dev_attr, |
1042 | .class = &dm81xx_mmc_class, | |
4d38bd12 TL |
1043 | }; |
1044 | ||
1045 | static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = { | |
7e1b11d1 | 1046 | .master = &dm81xx_l4_ls_hwmod, |
4d38bd12 TL |
1047 | .slave = &dm816x_mmc1_hwmod, |
1048 | .clk = "sysclk6_ck", | |
1049 | .user = OCP_USER_MPU, | |
1050 | .flags = OMAP_FIREWALL_L4 | |
1051 | }; | |
1052 | ||
1053 | static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = { | |
1054 | .rev_offs = 0x0, | |
1055 | .sysc_offs = 0x110, | |
1056 | .syss_offs = 0x114, | |
1057 | .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1058 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1059 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, | |
1060 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, | |
1061 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1062 | }; | |
1063 | ||
1064 | static struct omap_hwmod_class dm816x_mcspi_class = { | |
1065 | .name = "mcspi", | |
1066 | .sysc = &dm816x_mcspi_sysc, | |
1067 | .rev = OMAP3_MCSPI_REV, | |
1068 | }; | |
1069 | ||
1070 | static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = { | |
1071 | .num_chipselect = 4, | |
1072 | }; | |
1073 | ||
7e1b11d1 | 1074 | static struct omap_hwmod dm81xx_mcspi1_hwmod = { |
4d38bd12 TL |
1075 | .name = "mcspi1", |
1076 | .clkdm_name = "alwon_l3s_clkdm", | |
1077 | .main_clk = "sysclk10_ck", | |
1078 | .prcm = { | |
1079 | .omap4 = { | |
7e1b11d1 | 1080 | .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL, |
4d38bd12 TL |
1081 | .modulemode = MODULEMODE_SWCTRL, |
1082 | }, | |
1083 | }, | |
1084 | .class = &dm816x_mcspi_class, | |
1085 | .dev_attr = &dm816x_mcspi1_dev_attr, | |
1086 | }; | |
1087 | ||
7e1b11d1 TL |
1088 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = { |
1089 | .master = &dm81xx_l4_ls_hwmod, | |
1090 | .slave = &dm81xx_mcspi1_hwmod, | |
4d38bd12 TL |
1091 | .clk = "sysclk6_ck", |
1092 | .user = OCP_USER_MPU, | |
1093 | }; | |
1094 | ||
7e1b11d1 | 1095 | static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = { |
4d38bd12 TL |
1096 | .rev_offs = 0x000, |
1097 | .sysc_offs = 0x010, | |
1098 | .syss_offs = 0x014, | |
1099 | .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1100 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE, | |
1101 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, | |
1102 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1103 | }; | |
1104 | ||
7e1b11d1 | 1105 | static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = { |
4d38bd12 | 1106 | .name = "mailbox", |
7e1b11d1 | 1107 | .sysc = &dm81xx_mailbox_sysc, |
4d38bd12 TL |
1108 | }; |
1109 | ||
7e1b11d1 | 1110 | static struct omap_hwmod dm81xx_mailbox_hwmod = { |
4d38bd12 TL |
1111 | .name = "mailbox", |
1112 | .clkdm_name = "alwon_l3s_clkdm", | |
7e1b11d1 | 1113 | .class = &dm81xx_mailbox_hwmod_class, |
4d38bd12 TL |
1114 | .main_clk = "sysclk6_ck", |
1115 | .prcm = { | |
1116 | .omap4 = { | |
7e1b11d1 | 1117 | .clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL, |
4d38bd12 TL |
1118 | .modulemode = MODULEMODE_SWCTRL, |
1119 | }, | |
1120 | }, | |
1121 | }; | |
1122 | ||
7e1b11d1 TL |
1123 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = { |
1124 | .master = &dm81xx_l4_ls_hwmod, | |
1125 | .slave = &dm81xx_mailbox_hwmod, | |
4d38bd12 TL |
1126 | .user = OCP_USER_MPU, |
1127 | }; | |
1128 | ||
1539569b NA |
1129 | static struct omap_hwmod_class_sysconfig dm81xx_spinbox_sysc = { |
1130 | .rev_offs = 0x000, | |
1131 | .sysc_offs = 0x010, | |
1132 | .syss_offs = 0x014, | |
1133 | .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1134 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE, | |
1135 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, | |
1136 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1137 | }; | |
1138 | ||
1139 | static struct omap_hwmod_class dm81xx_spinbox_hwmod_class = { | |
1140 | .name = "spinbox", | |
1141 | .sysc = &dm81xx_spinbox_sysc, | |
1142 | }; | |
1143 | ||
1144 | static struct omap_hwmod dm81xx_spinbox_hwmod = { | |
1145 | .name = "spinbox", | |
1146 | .clkdm_name = "alwon_l3s_clkdm", | |
1147 | .class = &dm81xx_spinbox_hwmod_class, | |
1148 | .main_clk = "sysclk6_ck", | |
1149 | .prcm = { | |
1150 | .omap4 = { | |
1151 | .clkctrl_offs = DM81XX_CM_ALWON_SPINBOX_CLKCTRL, | |
1152 | .modulemode = MODULEMODE_SWCTRL, | |
1153 | }, | |
1154 | }, | |
1155 | }; | |
1156 | ||
1157 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = { | |
1158 | .master = &dm81xx_l4_ls_hwmod, | |
1159 | .slave = &dm81xx_spinbox_hwmod, | |
1160 | .user = OCP_USER_MPU, | |
1161 | }; | |
1162 | ||
7e1b11d1 | 1163 | static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = { |
4d38bd12 TL |
1164 | .name = "tpcc", |
1165 | }; | |
1166 | ||
24da741c | 1167 | static struct omap_hwmod dm81xx_tpcc_hwmod = { |
4d38bd12 | 1168 | .name = "tpcc", |
7e1b11d1 | 1169 | .class = &dm81xx_tpcc_hwmod_class, |
4d38bd12 TL |
1170 | .clkdm_name = "alwon_l3s_clkdm", |
1171 | .main_clk = "sysclk4_ck", | |
1172 | .prcm = { | |
1173 | .omap4 = { | |
7e1b11d1 | 1174 | .clkctrl_offs = DM81XX_CM_ALWON_TPCC_CLKCTRL, |
4d38bd12 TL |
1175 | .modulemode = MODULEMODE_SWCTRL, |
1176 | }, | |
1177 | }, | |
1178 | }; | |
1179 | ||
24da741c | 1180 | static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = { |
7e1b11d1 TL |
1181 | .master = &dm81xx_alwon_l3_fast_hwmod, |
1182 | .slave = &dm81xx_tpcc_hwmod, | |
4d38bd12 TL |
1183 | .clk = "sysclk4_ck", |
1184 | .user = OCP_USER_MPU, | |
1185 | }; | |
1186 | ||
7e1b11d1 | 1187 | static struct omap_hwmod_addr_space dm81xx_tptc0_addr_space[] = { |
4d38bd12 TL |
1188 | { |
1189 | .pa_start = 0x49800000, | |
1190 | .pa_end = 0x49800000 + SZ_8K - 1, | |
1191 | .flags = ADDR_TYPE_RT, | |
1192 | }, | |
1193 | { }, | |
1194 | }; | |
1195 | ||
7e1b11d1 | 1196 | static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = { |
4d38bd12 TL |
1197 | .name = "tptc0", |
1198 | }; | |
1199 | ||
24da741c | 1200 | static struct omap_hwmod dm81xx_tptc0_hwmod = { |
4d38bd12 | 1201 | .name = "tptc0", |
7e1b11d1 | 1202 | .class = &dm81xx_tptc0_hwmod_class, |
4d38bd12 TL |
1203 | .clkdm_name = "alwon_l3s_clkdm", |
1204 | .main_clk = "sysclk4_ck", | |
1205 | .prcm = { | |
1206 | .omap4 = { | |
7e1b11d1 | 1207 | .clkctrl_offs = DM81XX_CM_ALWON_TPTC0_CLKCTRL, |
4d38bd12 TL |
1208 | .modulemode = MODULEMODE_SWCTRL, |
1209 | }, | |
1210 | }, | |
1211 | }; | |
1212 | ||
24da741c | 1213 | static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = { |
7e1b11d1 TL |
1214 | .master = &dm81xx_alwon_l3_fast_hwmod, |
1215 | .slave = &dm81xx_tptc0_hwmod, | |
4d38bd12 | 1216 | .clk = "sysclk4_ck", |
7e1b11d1 | 1217 | .addr = dm81xx_tptc0_addr_space, |
4d38bd12 TL |
1218 | .user = OCP_USER_MPU, |
1219 | }; | |
1220 | ||
24da741c | 1221 | static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = { |
7e1b11d1 TL |
1222 | .master = &dm81xx_tptc0_hwmod, |
1223 | .slave = &dm81xx_alwon_l3_fast_hwmod, | |
4d38bd12 | 1224 | .clk = "sysclk4_ck", |
7e1b11d1 | 1225 | .addr = dm81xx_tptc0_addr_space, |
4d38bd12 TL |
1226 | .user = OCP_USER_MPU, |
1227 | }; | |
1228 | ||
7e1b11d1 | 1229 | static struct omap_hwmod_addr_space dm81xx_tptc1_addr_space[] = { |
4d38bd12 TL |
1230 | { |
1231 | .pa_start = 0x49900000, | |
1232 | .pa_end = 0x49900000 + SZ_8K - 1, | |
1233 | .flags = ADDR_TYPE_RT, | |
1234 | }, | |
1235 | { }, | |
1236 | }; | |
1237 | ||
7e1b11d1 | 1238 | static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = { |
4d38bd12 TL |
1239 | .name = "tptc1", |
1240 | }; | |
1241 | ||
24da741c | 1242 | static struct omap_hwmod dm81xx_tptc1_hwmod = { |
4d38bd12 | 1243 | .name = "tptc1", |
7e1b11d1 | 1244 | .class = &dm81xx_tptc1_hwmod_class, |
4d38bd12 TL |
1245 | .clkdm_name = "alwon_l3s_clkdm", |
1246 | .main_clk = "sysclk4_ck", | |
1247 | .prcm = { | |
1248 | .omap4 = { | |
7e1b11d1 | 1249 | .clkctrl_offs = DM81XX_CM_ALWON_TPTC1_CLKCTRL, |
4d38bd12 TL |
1250 | .modulemode = MODULEMODE_SWCTRL, |
1251 | }, | |
1252 | }, | |
1253 | }; | |
1254 | ||
24da741c | 1255 | static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = { |
7e1b11d1 TL |
1256 | .master = &dm81xx_alwon_l3_fast_hwmod, |
1257 | .slave = &dm81xx_tptc1_hwmod, | |
4d38bd12 | 1258 | .clk = "sysclk4_ck", |
7e1b11d1 | 1259 | .addr = dm81xx_tptc1_addr_space, |
4d38bd12 TL |
1260 | .user = OCP_USER_MPU, |
1261 | }; | |
1262 | ||
24da741c | 1263 | static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = { |
7e1b11d1 TL |
1264 | .master = &dm81xx_tptc1_hwmod, |
1265 | .slave = &dm81xx_alwon_l3_fast_hwmod, | |
4d38bd12 | 1266 | .clk = "sysclk4_ck", |
7e1b11d1 | 1267 | .addr = dm81xx_tptc1_addr_space, |
4d38bd12 TL |
1268 | .user = OCP_USER_MPU, |
1269 | }; | |
1270 | ||
7e1b11d1 | 1271 | static struct omap_hwmod_addr_space dm81xx_tptc2_addr_space[] = { |
4d38bd12 TL |
1272 | { |
1273 | .pa_start = 0x49a00000, | |
1274 | .pa_end = 0x49a00000 + SZ_8K - 1, | |
1275 | .flags = ADDR_TYPE_RT, | |
1276 | }, | |
1277 | { }, | |
1278 | }; | |
1279 | ||
7e1b11d1 | 1280 | static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = { |
4d38bd12 TL |
1281 | .name = "tptc2", |
1282 | }; | |
1283 | ||
24da741c | 1284 | static struct omap_hwmod dm81xx_tptc2_hwmod = { |
4d38bd12 | 1285 | .name = "tptc2", |
7e1b11d1 | 1286 | .class = &dm81xx_tptc2_hwmod_class, |
4d38bd12 TL |
1287 | .clkdm_name = "alwon_l3s_clkdm", |
1288 | .main_clk = "sysclk4_ck", | |
1289 | .prcm = { | |
1290 | .omap4 = { | |
7e1b11d1 | 1291 | .clkctrl_offs = DM81XX_CM_ALWON_TPTC2_CLKCTRL, |
4d38bd12 TL |
1292 | .modulemode = MODULEMODE_SWCTRL, |
1293 | }, | |
1294 | }, | |
1295 | }; | |
1296 | ||
24da741c | 1297 | static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = { |
7e1b11d1 TL |
1298 | .master = &dm81xx_alwon_l3_fast_hwmod, |
1299 | .slave = &dm81xx_tptc2_hwmod, | |
4d38bd12 | 1300 | .clk = "sysclk4_ck", |
7e1b11d1 | 1301 | .addr = dm81xx_tptc2_addr_space, |
4d38bd12 TL |
1302 | .user = OCP_USER_MPU, |
1303 | }; | |
1304 | ||
24da741c | 1305 | static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = { |
7e1b11d1 TL |
1306 | .master = &dm81xx_tptc2_hwmod, |
1307 | .slave = &dm81xx_alwon_l3_fast_hwmod, | |
4d38bd12 | 1308 | .clk = "sysclk4_ck", |
7e1b11d1 | 1309 | .addr = dm81xx_tptc2_addr_space, |
4d38bd12 TL |
1310 | .user = OCP_USER_MPU, |
1311 | }; | |
1312 | ||
7e1b11d1 | 1313 | static struct omap_hwmod_addr_space dm81xx_tptc3_addr_space[] = { |
4d38bd12 TL |
1314 | { |
1315 | .pa_start = 0x49b00000, | |
1316 | .pa_end = 0x49b00000 + SZ_8K - 1, | |
1317 | .flags = ADDR_TYPE_RT, | |
1318 | }, | |
1319 | { }, | |
1320 | }; | |
1321 | ||
7e1b11d1 | 1322 | static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = { |
4d38bd12 TL |
1323 | .name = "tptc3", |
1324 | }; | |
1325 | ||
24da741c | 1326 | static struct omap_hwmod dm81xx_tptc3_hwmod = { |
4d38bd12 | 1327 | .name = "tptc3", |
7e1b11d1 | 1328 | .class = &dm81xx_tptc3_hwmod_class, |
4d38bd12 TL |
1329 | .clkdm_name = "alwon_l3s_clkdm", |
1330 | .main_clk = "sysclk4_ck", | |
1331 | .prcm = { | |
1332 | .omap4 = { | |
7e1b11d1 | 1333 | .clkctrl_offs = DM81XX_CM_ALWON_TPTC3_CLKCTRL, |
4d38bd12 TL |
1334 | .modulemode = MODULEMODE_SWCTRL, |
1335 | }, | |
1336 | }, | |
1337 | }; | |
1338 | ||
24da741c | 1339 | static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = { |
7e1b11d1 TL |
1340 | .master = &dm81xx_alwon_l3_fast_hwmod, |
1341 | .slave = &dm81xx_tptc3_hwmod, | |
4d38bd12 | 1342 | .clk = "sysclk4_ck", |
7e1b11d1 | 1343 | .addr = dm81xx_tptc3_addr_space, |
4d38bd12 TL |
1344 | .user = OCP_USER_MPU, |
1345 | }; | |
1346 | ||
24da741c | 1347 | static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = { |
7e1b11d1 TL |
1348 | .master = &dm81xx_tptc3_hwmod, |
1349 | .slave = &dm81xx_alwon_l3_fast_hwmod, | |
4d38bd12 | 1350 | .clk = "sysclk4_ck", |
7e1b11d1 | 1351 | .addr = dm81xx_tptc3_addr_space, |
4d38bd12 TL |
1352 | .user = OCP_USER_MPU, |
1353 | }; | |
1354 | ||
0f3ccb24 TL |
1355 | /* |
1356 | * REVISIT: Test and enable the following once clocks work: | |
0f3ccb24 | 1357 | * dm81xx_l4_ls__mailbox |
0f3ccb24 TL |
1358 | * |
1359 | * Also note that some devices share a single clkctrl_offs.. | |
1360 | * For example, i2c1 and 3 share one, and i2c2 and 4 share one. | |
1361 | */ | |
1362 | static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = { | |
1363 | &dm814x_mpu__alwon_l3_slow, | |
1364 | &dm814x_mpu__alwon_l3_med, | |
1365 | &dm81xx_alwon_l3_slow__l4_ls, | |
1366 | &dm81xx_alwon_l3_slow__l4_hs, | |
1367 | &dm81xx_l4_ls__uart1, | |
1368 | &dm81xx_l4_ls__uart2, | |
1369 | &dm81xx_l4_ls__uart3, | |
1370 | &dm81xx_l4_ls__wd_timer1, | |
1371 | &dm81xx_l4_ls__i2c1, | |
1372 | &dm81xx_l4_ls__i2c2, | |
3022b29d TL |
1373 | &dm81xx_l4_ls__gpio1, |
1374 | &dm81xx_l4_ls__gpio2, | |
0f3ccb24 TL |
1375 | &dm81xx_l4_ls__elm, |
1376 | &dm81xx_l4_ls__mcspi1, | |
c757fda8 TL |
1377 | &dm814x_l4_ls__mmc1, |
1378 | &dm814x_l4_ls__mmc2, | |
0f3ccb24 TL |
1379 | &dm81xx_alwon_l3_fast__tpcc, |
1380 | &dm81xx_alwon_l3_fast__tptc0, | |
1381 | &dm81xx_alwon_l3_fast__tptc1, | |
1382 | &dm81xx_alwon_l3_fast__tptc2, | |
1383 | &dm81xx_alwon_l3_fast__tptc3, | |
1384 | &dm81xx_tptc0__alwon_l3_fast, | |
1385 | &dm81xx_tptc1__alwon_l3_fast, | |
1386 | &dm81xx_tptc2__alwon_l3_fast, | |
1387 | &dm81xx_tptc3__alwon_l3_fast, | |
1388 | &dm814x_l4_ls__timer1, | |
1389 | &dm814x_l4_ls__timer2, | |
1390 | &dm814x_l4_hs__cpgmac0, | |
1391 | &dm814x_cpgmac0__mdio, | |
f53850b5 TL |
1392 | &dm81xx_alwon_l3_slow__gpmc, |
1393 | &dm814x_default_l3_slow__usbss, | |
c757fda8 | 1394 | &dm814x_alwon_l3_med__mmc3, |
0f3ccb24 TL |
1395 | NULL, |
1396 | }; | |
1397 | ||
1398 | int __init dm814x_hwmod_init(void) | |
1399 | { | |
1400 | omap_hwmod_init(); | |
1401 | return omap_hwmod_register_links(dm814x_hwmod_ocp_ifs); | |
1402 | } | |
1403 | ||
4d38bd12 TL |
1404 | static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = { |
1405 | &dm816x_mpu__alwon_l3_slow, | |
1406 | &dm816x_mpu__alwon_l3_med, | |
7e1b11d1 TL |
1407 | &dm81xx_alwon_l3_slow__l4_ls, |
1408 | &dm81xx_alwon_l3_slow__l4_hs, | |
1409 | &dm81xx_l4_ls__uart1, | |
1410 | &dm81xx_l4_ls__uart2, | |
1411 | &dm81xx_l4_ls__uart3, | |
1412 | &dm81xx_l4_ls__wd_timer1, | |
1413 | &dm81xx_l4_ls__i2c1, | |
1414 | &dm81xx_l4_ls__i2c2, | |
4d38bd12 TL |
1415 | &dm81xx_l4_ls__gpio1, |
1416 | &dm81xx_l4_ls__gpio2, | |
1417 | &dm81xx_l4_ls__elm, | |
1418 | &dm816x_l4_ls__mmc1, | |
1419 | &dm816x_l4_ls__timer1, | |
1420 | &dm816x_l4_ls__timer2, | |
1421 | &dm816x_l4_ls__timer3, | |
1422 | &dm816x_l4_ls__timer4, | |
1423 | &dm816x_l4_ls__timer5, | |
1424 | &dm816x_l4_ls__timer6, | |
1425 | &dm816x_l4_ls__timer7, | |
7e1b11d1 TL |
1426 | &dm81xx_l4_ls__mcspi1, |
1427 | &dm81xx_l4_ls__mailbox, | |
1539569b | 1428 | &dm81xx_l4_ls__spinbox, |
7e1b11d1 TL |
1429 | &dm81xx_l4_hs__emac0, |
1430 | &dm81xx_emac0__mdio, | |
4d38bd12 | 1431 | &dm816x_l4_hs__emac1, |
7e1b11d1 TL |
1432 | &dm81xx_alwon_l3_fast__tpcc, |
1433 | &dm81xx_alwon_l3_fast__tptc0, | |
1434 | &dm81xx_alwon_l3_fast__tptc1, | |
1435 | &dm81xx_alwon_l3_fast__tptc2, | |
1436 | &dm81xx_alwon_l3_fast__tptc3, | |
1437 | &dm81xx_tptc0__alwon_l3_fast, | |
1438 | &dm81xx_tptc1__alwon_l3_fast, | |
1439 | &dm81xx_tptc2__alwon_l3_fast, | |
1440 | &dm81xx_tptc3__alwon_l3_fast, | |
4d38bd12 | 1441 | &dm81xx_alwon_l3_slow__gpmc, |
f53850b5 | 1442 | &dm816x_default_l3_slow__usbss, |
4d38bd12 TL |
1443 | NULL, |
1444 | }; | |
1445 | ||
0f3ccb24 | 1446 | int __init dm816x_hwmod_init(void) |
4d38bd12 TL |
1447 | { |
1448 | omap_hwmod_init(); | |
1449 | return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs); | |
1450 | } |