Commit | Line | Data |
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fbc319f6 TG |
1 | /** |
2 | * OMAP and TWL PMIC specific intializations. | |
3 | * | |
4 | * Copyright (C) 2010 Texas Instruments Incorporated. | |
5 | * Thara Gopinath | |
6 | * Copyright (C) 2009 Texas Instruments Incorporated. | |
7 | * Nishanth Menon | |
8 | * Copyright (C) 2009 Nokia Corporation | |
9 | * Paul Walmsley | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/err.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/kernel.h> | |
7bc3ed9a | 19 | #include <linux/i2c/twl.h> |
fbc319f6 | 20 | |
e4c060db | 21 | #include "soc.h" |
e1d6f472 | 22 | #include "voltage.h" |
fbc319f6 | 23 | |
dda0aea7 NM |
24 | #include "pm.h" |
25 | ||
fbc319f6 TG |
26 | #define OMAP3_SRI2C_SLAVE_ADDR 0x12 |
27 | #define OMAP3_VDD_MPU_SR_CONTROL_REG 0x00 | |
28 | #define OMAP3_VDD_CORE_SR_CONTROL_REG 0x01 | |
29 | #define OMAP3_VP_CONFIG_ERROROFFSET 0x00 | |
30 | #define OMAP3_VP_VSTEPMIN_VSTEPMIN 0x1 | |
31 | #define OMAP3_VP_VSTEPMAX_VSTEPMAX 0x04 | |
32 | #define OMAP3_VP_VLIMITTO_TIMEOUT_US 200 | |
33 | ||
34 | #define OMAP3430_VP1_VLIMITTO_VDDMIN 0x14 | |
35 | #define OMAP3430_VP1_VLIMITTO_VDDMAX 0x42 | |
36 | #define OMAP3430_VP2_VLIMITTO_VDDMIN 0x18 | |
37 | #define OMAP3430_VP2_VLIMITTO_VDDMAX 0x2c | |
38 | ||
39 | #define OMAP3630_VP1_VLIMITTO_VDDMIN 0x18 | |
40 | #define OMAP3630_VP1_VLIMITTO_VDDMAX 0x3c | |
41 | #define OMAP3630_VP2_VLIMITTO_VDDMIN 0x18 | |
42 | #define OMAP3630_VP2_VLIMITTO_VDDMAX 0x30 | |
43 | ||
7bc3ed9a TG |
44 | #define OMAP4_SRI2C_SLAVE_ADDR 0x12 |
45 | #define OMAP4_VDD_MPU_SR_VOLT_REG 0x55 | |
ee7fbba6 | 46 | #define OMAP4_VDD_MPU_SR_CMD_REG 0x56 |
7bc3ed9a | 47 | #define OMAP4_VDD_IVA_SR_VOLT_REG 0x5B |
ee7fbba6 | 48 | #define OMAP4_VDD_IVA_SR_CMD_REG 0x5C |
7bc3ed9a | 49 | #define OMAP4_VDD_CORE_SR_VOLT_REG 0x61 |
ee7fbba6 | 50 | #define OMAP4_VDD_CORE_SR_CMD_REG 0x62 |
7bc3ed9a TG |
51 | |
52 | #define OMAP4_VP_CONFIG_ERROROFFSET 0x00 | |
53 | #define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01 | |
54 | #define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04 | |
55 | #define OMAP4_VP_VLIMITTO_TIMEOUT_US 200 | |
56 | ||
57 | #define OMAP4_VP_MPU_VLIMITTO_VDDMIN 0xA | |
58 | #define OMAP4_VP_MPU_VLIMITTO_VDDMAX 0x39 | |
59 | #define OMAP4_VP_IVA_VLIMITTO_VDDMIN 0xA | |
60 | #define OMAP4_VP_IVA_VLIMITTO_VDDMAX 0x2D | |
61 | #define OMAP4_VP_CORE_VLIMITTO_VDDMIN 0xA | |
62 | #define OMAP4_VP_CORE_VLIMITTO_VDDMAX 0x28 | |
63 | ||
64 | static bool is_offset_valid; | |
65 | static u8 smps_offset; | |
40713189 TG |
66 | /* |
67 | * Flag to ensure Smartreflex bit in TWL | |
68 | * being cleared in board file is not overwritten. | |
69 | */ | |
70 | static bool __initdata twl_sr_enable_autoinit; | |
7bc3ed9a | 71 | |
40713189 | 72 | #define TWL4030_DCDC_GLOBAL_CFG 0x06 |
7bc3ed9a | 73 | #define REG_SMPS_OFFSET 0xE0 |
40713189 | 74 | #define SMARTREFLEX_ENABLE BIT(3) |
7bc3ed9a | 75 | |
c84ff1cc | 76 | static unsigned long twl4030_vsel_to_uv(const u8 vsel) |
fbc319f6 TG |
77 | { |
78 | return (((vsel * 125) + 6000)) * 100; | |
79 | } | |
80 | ||
c84ff1cc | 81 | static u8 twl4030_uv_to_vsel(unsigned long uv) |
fbc319f6 TG |
82 | { |
83 | return DIV_ROUND_UP(uv - 600000, 12500); | |
84 | } | |
85 | ||
c84ff1cc | 86 | static unsigned long twl6030_vsel_to_uv(const u8 vsel) |
7bc3ed9a TG |
87 | { |
88 | /* | |
89 | * In TWL6030 depending on the value of SMPS_OFFSET | |
90 | * efuse register the voltage range supported in | |
91 | * standard mode can be either between 0.6V - 1.3V or | |
92 | * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse | |
93 | * is programmed to all 0's where as starting from | |
94 | * TWL6030 ES1.1 the efuse is programmed to 1 | |
95 | */ | |
96 | if (!is_offset_valid) { | |
97 | twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset, | |
98 | REG_SMPS_OFFSET); | |
99 | is_offset_valid = true; | |
100 | } | |
101 | ||
2aed5b9e NM |
102 | if (!vsel) |
103 | return 0; | |
7bc3ed9a TG |
104 | /* |
105 | * There is no specific formula for voltage to vsel | |
106 | * conversion above 1.3V. There are special hardcoded | |
107 | * values for voltages above 1.3V. Currently we are | |
108 | * hardcoding only for 1.35 V which is used for 1GH OPP for | |
109 | * OMAP4430. | |
110 | */ | |
111 | if (vsel == 0x3A) | |
112 | return 1350000; | |
113 | ||
114 | if (smps_offset & 0x8) | |
58e241f7 | 115 | return ((((vsel - 1) * 1266) + 70900)) * 10; |
7bc3ed9a | 116 | else |
58e241f7 | 117 | return ((((vsel - 1) * 1266) + 60770)) * 10; |
7bc3ed9a TG |
118 | } |
119 | ||
c84ff1cc | 120 | static u8 twl6030_uv_to_vsel(unsigned long uv) |
7bc3ed9a TG |
121 | { |
122 | /* | |
123 | * In TWL6030 depending on the value of SMPS_OFFSET | |
124 | * efuse register the voltage range supported in | |
125 | * standard mode can be either between 0.6V - 1.3V or | |
126 | * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse | |
127 | * is programmed to all 0's where as starting from | |
128 | * TWL6030 ES1.1 the efuse is programmed to 1 | |
129 | */ | |
130 | if (!is_offset_valid) { | |
131 | twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset, | |
132 | REG_SMPS_OFFSET); | |
133 | is_offset_valid = true; | |
134 | } | |
135 | ||
2aed5b9e NM |
136 | if (!uv) |
137 | return 0x00; | |
7bc3ed9a TG |
138 | /* |
139 | * There is no specific formula for voltage to vsel | |
140 | * conversion above 1.3V. There are special hardcoded | |
141 | * values for voltages above 1.3V. Currently we are | |
142 | * hardcoding only for 1.35 V which is used for 1GH OPP for | |
143 | * OMAP4430. | |
144 | */ | |
36649425 NM |
145 | if (uv > twl6030_vsel_to_uv(0x39)) { |
146 | if (uv == 1350000) | |
147 | return 0x3A; | |
148 | pr_err("%s:OUT OF RANGE! non mapped vsel for %ld Vs max %ld\n", | |
149 | __func__, uv, twl6030_vsel_to_uv(0x39)); | |
7bc3ed9a | 150 | return 0x3A; |
36649425 | 151 | } |
7bc3ed9a TG |
152 | |
153 | if (smps_offset & 0x8) | |
58e241f7 | 154 | return DIV_ROUND_UP(uv - 709000, 12660) + 1; |
7bc3ed9a | 155 | else |
58e241f7 | 156 | return DIV_ROUND_UP(uv - 607700, 12660) + 1; |
7bc3ed9a TG |
157 | } |
158 | ||
ce8ebe0d | 159 | static struct omap_voltdm_pmic omap3_mpu_pmic = { |
fbc319f6 TG |
160 | .slew_rate = 4000, |
161 | .step_size = 12500, | |
162 | .on_volt = 1200000, | |
163 | .onlp_volt = 1000000, | |
164 | .ret_volt = 975000, | |
165 | .off_volt = 600000, | |
166 | .volt_setup_time = 0xfff, | |
167 | .vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET, | |
168 | .vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN, | |
169 | .vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX, | |
170 | .vp_vddmin = OMAP3430_VP1_VLIMITTO_VDDMIN, | |
171 | .vp_vddmax = OMAP3430_VP1_VLIMITTO_VDDMAX, | |
172 | .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US, | |
173 | .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR, | |
e74e4405 | 174 | .volt_reg_addr = OMAP3_VDD_MPU_SR_CONTROL_REG, |
f5395480 | 175 | .i2c_high_speed = true, |
fbc319f6 TG |
176 | .vsel_to_uv = twl4030_vsel_to_uv, |
177 | .uv_to_vsel = twl4030_uv_to_vsel, | |
178 | }; | |
179 | ||
ce8ebe0d | 180 | static struct omap_voltdm_pmic omap3_core_pmic = { |
fbc319f6 TG |
181 | .slew_rate = 4000, |
182 | .step_size = 12500, | |
183 | .on_volt = 1200000, | |
184 | .onlp_volt = 1000000, | |
185 | .ret_volt = 975000, | |
186 | .off_volt = 600000, | |
187 | .volt_setup_time = 0xfff, | |
188 | .vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET, | |
189 | .vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN, | |
190 | .vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX, | |
191 | .vp_vddmin = OMAP3430_VP2_VLIMITTO_VDDMIN, | |
192 | .vp_vddmax = OMAP3430_VP2_VLIMITTO_VDDMAX, | |
193 | .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US, | |
194 | .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR, | |
e74e4405 | 195 | .volt_reg_addr = OMAP3_VDD_CORE_SR_CONTROL_REG, |
f5395480 | 196 | .i2c_high_speed = true, |
fbc319f6 TG |
197 | .vsel_to_uv = twl4030_vsel_to_uv, |
198 | .uv_to_vsel = twl4030_uv_to_vsel, | |
199 | }; | |
200 | ||
ce8ebe0d | 201 | static struct omap_voltdm_pmic omap4_mpu_pmic = { |
7bc3ed9a | 202 | .slew_rate = 4000, |
58e241f7 | 203 | .step_size = 12660, |
63f60a43 PT |
204 | .on_volt = 1375000, |
205 | .onlp_volt = 1375000, | |
206 | .ret_volt = 830000, | |
207 | .off_volt = 0, | |
7bc3ed9a TG |
208 | .volt_setup_time = 0, |
209 | .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET, | |
210 | .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN, | |
211 | .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX, | |
212 | .vp_vddmin = OMAP4_VP_MPU_VLIMITTO_VDDMIN, | |
213 | .vp_vddmax = OMAP4_VP_MPU_VLIMITTO_VDDMAX, | |
214 | .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US, | |
215 | .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR, | |
e74e4405 | 216 | .volt_reg_addr = OMAP4_VDD_MPU_SR_VOLT_REG, |
ee7fbba6 | 217 | .cmd_reg_addr = OMAP4_VDD_MPU_SR_CMD_REG, |
f5395480 | 218 | .i2c_high_speed = true, |
7bc3ed9a TG |
219 | .vsel_to_uv = twl6030_vsel_to_uv, |
220 | .uv_to_vsel = twl6030_uv_to_vsel, | |
221 | }; | |
222 | ||
ce8ebe0d | 223 | static struct omap_voltdm_pmic omap4_iva_pmic = { |
7bc3ed9a | 224 | .slew_rate = 4000, |
58e241f7 | 225 | .step_size = 12660, |
63f60a43 PT |
226 | .on_volt = 1188000, |
227 | .onlp_volt = 1188000, | |
228 | .ret_volt = 830000, | |
229 | .off_volt = 0, | |
7bc3ed9a TG |
230 | .volt_setup_time = 0, |
231 | .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET, | |
232 | .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN, | |
233 | .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX, | |
234 | .vp_vddmin = OMAP4_VP_IVA_VLIMITTO_VDDMIN, | |
235 | .vp_vddmax = OMAP4_VP_IVA_VLIMITTO_VDDMAX, | |
236 | .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US, | |
237 | .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR, | |
e74e4405 | 238 | .volt_reg_addr = OMAP4_VDD_IVA_SR_VOLT_REG, |
ee7fbba6 | 239 | .cmd_reg_addr = OMAP4_VDD_IVA_SR_CMD_REG, |
f5395480 | 240 | .i2c_high_speed = true, |
7bc3ed9a TG |
241 | .vsel_to_uv = twl6030_vsel_to_uv, |
242 | .uv_to_vsel = twl6030_uv_to_vsel, | |
243 | }; | |
244 | ||
ce8ebe0d | 245 | static struct omap_voltdm_pmic omap4_core_pmic = { |
7bc3ed9a | 246 | .slew_rate = 4000, |
58e241f7 | 247 | .step_size = 12660, |
63f60a43 PT |
248 | .on_volt = 1200000, |
249 | .onlp_volt = 1200000, | |
250 | .ret_volt = 830000, | |
251 | .off_volt = 0, | |
7bc3ed9a TG |
252 | .volt_setup_time = 0, |
253 | .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET, | |
254 | .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN, | |
255 | .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX, | |
256 | .vp_vddmin = OMAP4_VP_CORE_VLIMITTO_VDDMIN, | |
257 | .vp_vddmax = OMAP4_VP_CORE_VLIMITTO_VDDMAX, | |
258 | .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US, | |
259 | .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR, | |
e74e4405 | 260 | .volt_reg_addr = OMAP4_VDD_CORE_SR_VOLT_REG, |
ee7fbba6 | 261 | .cmd_reg_addr = OMAP4_VDD_CORE_SR_CMD_REG, |
7bc3ed9a TG |
262 | .vsel_to_uv = twl6030_vsel_to_uv, |
263 | .uv_to_vsel = twl6030_uv_to_vsel, | |
264 | }; | |
265 | ||
266 | int __init omap4_twl_init(void) | |
267 | { | |
268 | struct voltagedomain *voltdm; | |
269 | ||
270 | if (!cpu_is_omap44xx()) | |
271 | return -ENODEV; | |
272 | ||
81a60482 | 273 | voltdm = voltdm_lookup("mpu"); |
ce8ebe0d | 274 | omap_voltage_register_pmic(voltdm, &omap4_mpu_pmic); |
7bc3ed9a | 275 | |
81a60482 | 276 | voltdm = voltdm_lookup("iva"); |
ce8ebe0d | 277 | omap_voltage_register_pmic(voltdm, &omap4_iva_pmic); |
7bc3ed9a | 278 | |
81a60482 | 279 | voltdm = voltdm_lookup("core"); |
ce8ebe0d | 280 | omap_voltage_register_pmic(voltdm, &omap4_core_pmic); |
7bc3ed9a TG |
281 | |
282 | return 0; | |
283 | } | |
284 | ||
fbc319f6 TG |
285 | int __init omap3_twl_init(void) |
286 | { | |
287 | struct voltagedomain *voltdm; | |
288 | ||
289 | if (!cpu_is_omap34xx()) | |
290 | return -ENODEV; | |
291 | ||
292 | if (cpu_is_omap3630()) { | |
ce8ebe0d KH |
293 | omap3_mpu_pmic.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN; |
294 | omap3_mpu_pmic.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX; | |
295 | omap3_core_pmic.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN; | |
296 | omap3_core_pmic.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX; | |
fbc319f6 TG |
297 | } |
298 | ||
40713189 TG |
299 | /* |
300 | * The smartreflex bit on twl4030 specifies if the setting of voltage | |
301 | * is done over the I2C_SR path. Since this setting is independent of | |
302 | * the actual usage of smartreflex AVS module, we enable TWL SR bit | |
303 | * by default irrespective of whether smartreflex AVS module is enabled | |
304 | * on the OMAP side or not. This is because without this bit enabled, | |
305 | * the voltage scaling through vp forceupdate/bypass mechanism of | |
306 | * voltage scaling will not function on TWL over I2C_SR. | |
307 | */ | |
308 | if (!twl_sr_enable_autoinit) | |
309 | omap3_twl_set_sr_bit(true); | |
310 | ||
280a7275 | 311 | voltdm = voltdm_lookup("mpu_iva"); |
ce8ebe0d | 312 | omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic); |
fbc319f6 | 313 | |
81a60482 | 314 | voltdm = voltdm_lookup("core"); |
ce8ebe0d | 315 | omap_voltage_register_pmic(voltdm, &omap3_core_pmic); |
fbc319f6 TG |
316 | |
317 | return 0; | |
318 | } | |
40713189 TG |
319 | |
320 | /** | |
321 | * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL | |
322 | * @enable: enable SR mode in twl or not | |
323 | * | |
324 | * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure | |
325 | * voltage scaling through OMAP SR works. Else, the smartreflex bit | |
326 | * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but | |
327 | * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct | |
328 | * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages, | |
329 | * in those scenarios this bit is to be cleared (enable = false). | |
330 | * | |
25985edc | 331 | * Returns 0 on success, error is returned if I2C read/write fails. |
40713189 TG |
332 | */ |
333 | int __init omap3_twl_set_sr_bit(bool enable) | |
334 | { | |
335 | u8 temp; | |
336 | int ret; | |
337 | if (twl_sr_enable_autoinit) | |
338 | pr_warning("%s: unexpected multiple calls\n", __func__); | |
339 | ||
340 | ret = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &temp, | |
341 | TWL4030_DCDC_GLOBAL_CFG); | |
342 | if (ret) | |
343 | goto err; | |
344 | ||
345 | if (enable) | |
346 | temp |= SMARTREFLEX_ENABLE; | |
347 | else | |
348 | temp &= ~SMARTREFLEX_ENABLE; | |
349 | ||
350 | ret = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp, | |
351 | TWL4030_DCDC_GLOBAL_CFG); | |
352 | if (!ret) { | |
353 | twl_sr_enable_autoinit = true; | |
354 | return 0; | |
355 | } | |
356 | err: | |
357 | pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret); | |
358 | return ret; | |
359 | } |