Commit | Line | Data |
---|---|---|
6f88e9bc KH |
1 | /* |
2 | * pm.c - Common OMAP2+ power management-related code | |
3 | * | |
4 | * Copyright (C) 2010 Texas Instruments, Inc. | |
5 | * Copyright (C) 2010 Nokia Corporation | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/err.h> | |
1482d8be | 16 | #include <linux/opp.h> |
dc28094b | 17 | #include <linux/export.h> |
1416408d | 18 | #include <linux/suspend.h> |
24d7b40a | 19 | #include <linux/cpu.h> |
6f88e9bc | 20 | |
335aece5 G |
21 | #include <asm/system_misc.h> |
22 | ||
1d5aef49 | 23 | #include "omap-pm.h" |
25c7d49e | 24 | #include "omap_device.h" |
4e65331c | 25 | #include "common.h" |
6f88e9bc | 26 | |
e4c060db | 27 | #include "soc.h" |
1416408d | 28 | #include "prcm-common.h" |
e1d6f472 | 29 | #include "voltage.h" |
72e06d08 | 30 | #include "powerdomain.h" |
1540f214 | 31 | #include "clockdomain.h" |
0c0a5d61 | 32 | #include "pm.h" |
46232a36 | 33 | #include "twl-common.h" |
eb6a2c75 | 34 | |
6f88e9bc KH |
35 | static struct omap_device_pm_latency *pm_lats; |
36 | ||
1416408d PW |
37 | /* |
38 | * omap_pm_suspend: points to a function that does the SoC-specific | |
39 | * suspend work | |
40 | */ | |
41 | int (*omap_pm_suspend)(void); | |
42 | ||
9cf793f9 | 43 | static int __init _init_omap_device(char *name) |
6f88e9bc KH |
44 | { |
45 | struct omap_hwmod *oh; | |
3528c58e | 46 | struct platform_device *pdev; |
6f88e9bc KH |
47 | |
48 | oh = omap_hwmod_lookup(name); | |
49 | if (WARN(!oh, "%s: could not find omap_hwmod for %s\n", | |
50 | __func__, name)) | |
51 | return -ENODEV; | |
52 | ||
3528c58e KH |
53 | pdev = omap_device_build(oh->name, 0, oh, NULL, 0, pm_lats, 0, false); |
54 | if (WARN(IS_ERR(pdev), "%s: could not build omap_device for %s\n", | |
6f88e9bc KH |
55 | __func__, name)) |
56 | return -ENODEV; | |
57 | ||
6f88e9bc KH |
58 | return 0; |
59 | } | |
60 | ||
61 | /* | |
62 | * Build omap_devices for processors and bus. | |
63 | */ | |
1f3b372b | 64 | static void __init omap2_init_processor_devices(void) |
6f88e9bc | 65 | { |
766e7afc | 66 | _init_omap_device("mpu"); |
2de0baef | 67 | if (omap3_has_iva()) |
766e7afc | 68 | _init_omap_device("iva"); |
2de0baef | 69 | |
cbf27660 | 70 | if (cpu_is_omap44xx()) { |
766e7afc BC |
71 | _init_omap_device("l3_main_1"); |
72 | _init_omap_device("dsp"); | |
73 | _init_omap_device("iva"); | |
cbf27660 | 74 | } else { |
766e7afc | 75 | _init_omap_device("l3_main"); |
cbf27660 | 76 | } |
6f88e9bc KH |
77 | } |
78 | ||
71a488db RN |
79 | /* Types of sleep_switch used in omap_set_pwrdm_state */ |
80 | #define FORCEWAKEUP_SWITCH 0 | |
81 | #define LOWPOWERSTATE_SWITCH 1 | |
82 | ||
92206fd2 PW |
83 | int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused) |
84 | { | |
b71c7217 PW |
85 | if ((clkdm->flags & CLKDM_CAN_ENABLE_AUTO) && |
86 | !(clkdm->flags & CLKDM_MISSING_IDLE_REPORTING)) | |
92206fd2 PW |
87 | clkdm_allow_idle(clkdm); |
88 | else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && | |
89 | atomic_read(&clkdm->usecount) == 0) | |
90 | clkdm_sleep(clkdm); | |
91 | return 0; | |
92 | } | |
93 | ||
eb6a2c75 SS |
94 | /* |
95 | * This sets pwrdm state (other than mpu & core. Currently only ON & | |
33de32b3 | 96 | * RET are supported. |
eb6a2c75 | 97 | */ |
e68e8093 | 98 | int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 pwrst) |
eb6a2c75 | 99 | { |
e68e8093 PW |
100 | u8 curr_pwrst, next_pwrst; |
101 | int sleep_switch = -1, ret = 0, hwsup = 0; | |
eb6a2c75 | 102 | |
e68e8093 | 103 | if (!pwrdm || IS_ERR(pwrdm)) |
eb6a2c75 SS |
104 | return -EINVAL; |
105 | ||
e68e8093 PW |
106 | while (!(pwrdm->pwrsts & (1 << pwrst))) { |
107 | if (pwrst == PWRDM_POWER_OFF) | |
eb6a2c75 | 108 | return ret; |
e68e8093 | 109 | pwrst--; |
eb6a2c75 SS |
110 | } |
111 | ||
e68e8093 PW |
112 | next_pwrst = pwrdm_read_next_pwrst(pwrdm); |
113 | if (next_pwrst == pwrst) | |
eb6a2c75 SS |
114 | return ret; |
115 | ||
e68e8093 PW |
116 | curr_pwrst = pwrdm_read_pwrst(pwrdm); |
117 | if (curr_pwrst < PWRDM_POWER_ON) { | |
118 | if ((curr_pwrst > pwrst) && | |
71a488db RN |
119 | (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) { |
120 | sleep_switch = LOWPOWERSTATE_SWITCH; | |
121 | } else { | |
b86cfb52 | 122 | hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]); |
68b921ad | 123 | clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); |
71a488db RN |
124 | sleep_switch = FORCEWAKEUP_SWITCH; |
125 | } | |
eb6a2c75 SS |
126 | } |
127 | ||
e68e8093 PW |
128 | ret = pwrdm_set_next_pwrst(pwrdm, pwrst); |
129 | if (ret) | |
130 | pr_err("%s: unable to set power state of powerdomain: %s\n", | |
e9a5190a | 131 | __func__, pwrdm->name); |
eb6a2c75 | 132 | |
71a488db RN |
133 | switch (sleep_switch) { |
134 | case FORCEWAKEUP_SWITCH: | |
b86cfb52 | 135 | if (hwsup) |
5cd1937b | 136 | clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); |
33de32b3 | 137 | else |
68b921ad | 138 | clkdm_sleep(pwrdm->pwrdm_clkdms[0]); |
71a488db RN |
139 | break; |
140 | case LOWPOWERSTATE_SWITCH: | |
141 | pwrdm_set_lowpwrstchange(pwrdm); | |
e68e8093 PW |
142 | pwrdm_wait_transition(pwrdm); |
143 | pwrdm_state_switch(pwrdm); | |
71a488db | 144 | break; |
eb6a2c75 SS |
145 | } |
146 | ||
eb6a2c75 SS |
147 | return ret; |
148 | } | |
149 | ||
1416408d PW |
150 | |
151 | ||
1482d8be | 152 | /* |
1e2d2df3 | 153 | * This API is to be called during init to set the various voltage |
1482d8be TG |
154 | * domains to the voltage as per the opp table. Typically we boot up |
155 | * at the nominal voltage. So this function finds out the rate of | |
156 | * the clock associated with the voltage domain, finds out the correct | |
1e2d2df3 | 157 | * opp entry and sets the voltage domain to the voltage specified |
1482d8be TG |
158 | * in the opp entry |
159 | */ | |
160 | static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, | |
0f7aa005 | 161 | const char *oh_name) |
1482d8be TG |
162 | { |
163 | struct voltagedomain *voltdm; | |
164 | struct clk *clk; | |
165 | struct opp *opp; | |
166 | unsigned long freq, bootup_volt; | |
0f7aa005 | 167 | struct device *dev; |
1482d8be | 168 | |
0f7aa005 | 169 | if (!vdd_name || !clk_name || !oh_name) { |
e9a5190a | 170 | pr_err("%s: invalid parameters\n", __func__); |
1482d8be TG |
171 | goto exit; |
172 | } | |
173 | ||
24d7b40a KH |
174 | if (!strncmp(oh_name, "mpu", 3)) |
175 | /* | |
176 | * All current OMAPs share voltage rail and clock | |
177 | * source, so CPU0 is used to represent the MPU-SS. | |
178 | */ | |
179 | dev = get_cpu_device(0); | |
180 | else | |
181 | dev = omap_device_get_by_hwmod_name(oh_name); | |
182 | ||
0f7aa005 BC |
183 | if (IS_ERR(dev)) { |
184 | pr_err("%s: Unable to get dev pointer for hwmod %s\n", | |
185 | __func__, oh_name); | |
186 | goto exit; | |
187 | } | |
188 | ||
81a60482 | 189 | voltdm = voltdm_lookup(vdd_name); |
93b44bea | 190 | if (!voltdm) { |
e9a5190a | 191 | pr_err("%s: unable to get vdd pointer for vdd_%s\n", |
1482d8be TG |
192 | __func__, vdd_name); |
193 | goto exit; | |
194 | } | |
195 | ||
196 | clk = clk_get(NULL, clk_name); | |
197 | if (IS_ERR(clk)) { | |
e9a5190a | 198 | pr_err("%s: unable to get clk %s\n", __func__, clk_name); |
1482d8be TG |
199 | goto exit; |
200 | } | |
201 | ||
5dcc3b97 | 202 | freq = clk_get_rate(clk); |
1482d8be TG |
203 | clk_put(clk); |
204 | ||
6369fd41 | 205 | rcu_read_lock(); |
1482d8be TG |
206 | opp = opp_find_freq_ceil(dev, &freq); |
207 | if (IS_ERR(opp)) { | |
6369fd41 | 208 | rcu_read_unlock(); |
e9a5190a | 209 | pr_err("%s: unable to find boot up OPP for vdd_%s\n", |
1482d8be TG |
210 | __func__, vdd_name); |
211 | goto exit; | |
212 | } | |
213 | ||
214 | bootup_volt = opp_get_voltage(opp); | |
6369fd41 | 215 | rcu_read_unlock(); |
1482d8be | 216 | if (!bootup_volt) { |
7852ec05 PW |
217 | pr_err("%s: unable to find voltage corresponding to the bootup OPP for vdd_%s\n", |
218 | __func__, vdd_name); | |
1482d8be TG |
219 | goto exit; |
220 | } | |
221 | ||
5e5651be | 222 | voltdm_scale(voltdm, bootup_volt); |
1482d8be TG |
223 | return 0; |
224 | ||
225 | exit: | |
e9a5190a | 226 | pr_err("%s: unable to set vdd_%s\n", __func__, vdd_name); |
1482d8be TG |
227 | return -EINVAL; |
228 | } | |
229 | ||
1416408d PW |
230 | #ifdef CONFIG_SUSPEND |
231 | static int omap_pm_enter(suspend_state_t suspend_state) | |
232 | { | |
233 | int ret = 0; | |
234 | ||
235 | if (!omap_pm_suspend) | |
236 | return -ENOENT; /* XXX doublecheck */ | |
237 | ||
238 | switch (suspend_state) { | |
239 | case PM_SUSPEND_STANDBY: | |
240 | case PM_SUSPEND_MEM: | |
241 | ret = omap_pm_suspend(); | |
242 | break; | |
243 | default: | |
244 | ret = -EINVAL; | |
245 | } | |
246 | ||
247 | return ret; | |
248 | } | |
249 | ||
250 | static int omap_pm_begin(suspend_state_t state) | |
251 | { | |
252 | disable_hlt(); | |
253 | if (cpu_is_omap34xx()) | |
254 | omap_prcm_irq_prepare(); | |
255 | return 0; | |
256 | } | |
257 | ||
258 | static void omap_pm_end(void) | |
259 | { | |
260 | enable_hlt(); | |
261 | return; | |
262 | } | |
263 | ||
264 | static void omap_pm_finish(void) | |
265 | { | |
266 | if (cpu_is_omap34xx()) | |
267 | omap_prcm_irq_complete(); | |
268 | } | |
269 | ||
270 | static const struct platform_suspend_ops omap_pm_ops = { | |
271 | .begin = omap_pm_begin, | |
272 | .end = omap_pm_end, | |
273 | .enter = omap_pm_enter, | |
274 | .finish = omap_pm_finish, | |
275 | .valid = suspend_valid_only_mem, | |
276 | }; | |
277 | ||
278 | #endif /* CONFIG_SUSPEND */ | |
279 | ||
1482d8be TG |
280 | static void __init omap3_init_voltages(void) |
281 | { | |
282 | if (!cpu_is_omap34xx()) | |
283 | return; | |
284 | ||
0f7aa005 BC |
285 | omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu"); |
286 | omap2_set_init_voltage("core", "l3_ick", "l3_main"); | |
1482d8be TG |
287 | } |
288 | ||
1376ee1d TG |
289 | static void __init omap4_init_voltages(void) |
290 | { | |
291 | if (!cpu_is_omap44xx()) | |
292 | return; | |
293 | ||
0f7aa005 BC |
294 | omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu"); |
295 | omap2_set_init_voltage("core", "l3_div_ck", "l3_main_1"); | |
296 | omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva"); | |
1376ee1d TG |
297 | } |
298 | ||
6f88e9bc KH |
299 | static int __init omap2_common_pm_init(void) |
300 | { | |
476b679a BC |
301 | if (!of_have_populated_dt()) |
302 | omap2_init_processor_devices(); | |
6f88e9bc KH |
303 | omap_pm_if_init(); |
304 | ||
305 | return 0; | |
306 | } | |
1cbbe37a | 307 | postcore_initcall(omap2_common_pm_init); |
6f88e9bc | 308 | |
bbd707ac | 309 | int __init omap2_common_pm_late_init(void) |
2f34ce81 | 310 | { |
506d81ef BC |
311 | /* |
312 | * In the case of DT, the PMIC and SR initialization will be done using | |
313 | * a completely different mechanism. | |
314 | * Disable this part if a DT blob is available. | |
315 | */ | |
316 | if (of_have_populated_dt()) | |
317 | return 0; | |
318 | ||
fbc319f6 | 319 | /* Init the voltage layer */ |
46232a36 | 320 | omap_pmic_late_init(); |
2f34ce81 | 321 | omap_voltage_late_init(); |
1482d8be TG |
322 | |
323 | /* Initialize the voltages */ | |
324 | omap3_init_voltages(); | |
1376ee1d | 325 | omap4_init_voltages(); |
1482d8be | 326 | |
fbc319f6 | 327 | /* Smartreflex device init */ |
0c0a5d61 | 328 | omap_devinit_smartreflex(); |
2f34ce81 | 329 | |
1416408d PW |
330 | #ifdef CONFIG_SUSPEND |
331 | suspend_set_ops(&omap_pm_ops); | |
332 | #endif | |
333 | ||
2f34ce81 TG |
334 | return 0; |
335 | } |