[deliverable/linux.git] / arch / arm / mach-omap2 / pm.h

/*
 * OMAP2/3 Power Management Routines
 *
 * Copyright (C) 2008 Nokia Corporation
 * Jouni Hogander
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef __ARCH_ARM_MACH_OMAP2_PM_H
#define __ARCH_ARM_MACH_OMAP2_PM_H

#include <linux/err.h>

#include "powerdomain.h"

#ifdef CONFIG_CPU_IDLE
extern int __init omap3_idle_init(void);
extern int __init omap4_idle_init(void);
#else
static inline int omap3_idle_init(void)
{
	return 0;
}

static inline int omap4_idle_init(void)
{
	return 0;
}
#endif

extern void *omap3_secure_ram_storage;
extern void omap3_pm_off_mode_enable(int);
extern void omap_sram_idle(void);
extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused);

#if defined(CONFIG_PM_OPP)
extern int omap3_opp_init(void);
extern int omap4_opp_init(void);
#else
static inline int omap3_opp_init(void)
{
	return -EINVAL;
}
static inline int omap4_opp_init(void)
{
	return -EINVAL;
}
#endif

extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);

#ifdef CONFIG_PM_DEBUG
extern u32 enable_off_mode;
#else
#define enable_off_mode 0
#endif

#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
#else
#define pm_dbg_update_time(pwrdm, prev) do {} while (0);
#endif /* CONFIG_PM_DEBUG */

/* 24xx */
extern void omap24xx_idle_loop_suspend(void);
extern unsigned int omap24xx_idle_loop_suspend_sz;

extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
					void __iomem *sdrc_power);
extern unsigned int omap24xx_cpu_suspend_sz;

/* 3xxx */
extern void omap34xx_cpu_suspend(int save_state);

/* omap3_do_wfi function pointer and size, for copy to SRAM */
extern void omap3_do_wfi(void);
extern unsigned int omap3_do_wfi_sz;
/* ... and its pointer from SRAM after copy */
extern void (*omap3_do_wfi_sram)(void);

/* save_secure_ram_context function pointer and size, for copy to SRAM */
extern int save_secure_ram_context(u32 *addr);
extern unsigned int save_secure_ram_context_sz;

extern void omap3_save_scratchpad_contents(void);

#define PM_RTA_ERRATUM_i608		(1 << 0)
#define PM_SDRC_WAKEUP_ERRATUM_i583	(1 << 1)
#define PM_PER_MEMORIES_ERRATUM_i582	(1 << 2)

#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
extern u16 pm34xx_errata;
#define IS_PM34XX_ERRATUM(id)		(pm34xx_errata & (id))
extern void enable_omap3630_toggle_l2_on_restore(void);
#else
#define IS_PM34XX_ERRATUM(id)		0
static inline void enable_omap3630_toggle_l2_on_restore(void) { }
#endif		/* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */

#define PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD	(1 << 0)
#define PM_OMAP4_CPU_OSWR_DISABLE		(1 << 1)

#if defined(CONFIG_PM) && (defined(CONFIG_ARCH_OMAP4) ||\
	   defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX))
extern u16 pm44xx_errata;
#define IS_PM44XX_ERRATUM(id)		(pm44xx_errata & (id))
#else
#define IS_PM44XX_ERRATUM(id)		0
#endif

#ifdef CONFIG_POWER_AVS_OMAP
extern int omap_devinit_smartreflex(void);
extern void omap_enable_smartreflex_on_init(void);
#else
static inline int omap_devinit_smartreflex(void)
{
	return -EINVAL;
}

static inline void omap_enable_smartreflex_on_init(void) {}
#endif

#ifdef CONFIG_TWL4030_CORE
extern int omap3_twl_init(void);
extern int omap4_twl_init(void);
extern int omap3_twl_set_sr_bit(bool enable);
#else
static inline int omap3_twl_init(void)
{
	return -EINVAL;
}
static inline int omap4_twl_init(void)
{
	return -EINVAL;
}
#endif

#ifdef CONFIG_PM
extern void omap_pm_setup_oscillator(u32 tstart, u32 tshut);
extern void omap_pm_get_oscillator(u32 *tstart, u32 *tshut);
extern void omap_pm_setup_sr_i2c_pcb_length(u32 mm);
#else
static inline void omap_pm_setup_oscillator(u32 tstart, u32 tshut) { }
static inline void omap_pm_get_oscillator(u32 *tstart, u32 *tshut) { *tstart = *tshut = 0; }
static inline void omap_pm_setup_sr_i2c_pcb_length(u32 mm) { }
#endif

#ifdef CONFIG_SUSPEND
void omap_common_suspend_init(void *pm_suspend);
#else
static inline void omap_common_suspend_init(void *pm_suspend)
{
}
#endif /* CONFIG_SUSPEND */
#endif
Commit	Line	Data
8bd22949 KH	1	/*
	2	* OMAP2/3 Power Management Routines
	3	*
	4	* Copyright (C) 2008 Nokia Corporation
	5	* Jouni Hogander
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	#ifndef __ARCH_ARM_MACH_OMAP2_PM_H
	12	#define __ARCH_ARM_MACH_OMAP2_PM_H
	13
0c0a5d61 TG	14	#include <linux/err.h>
0c0a5d61 TG	15
72e06d08	16	#include "powerdomain.h"
331b93f4	17
164e0cbf DL	18	#ifdef CONFIG_CPU_IDLE
	19	extern int __init omap3_idle_init(void);
	20	extern int __init omap4_idle_init(void);
	21	#else
	22	static inline int omap3_idle_init(void)
	23	{
	24	return 0;
	25	}
	26
	27	static inline int omap4_idle_init(void)
	28	{
	29	return 0;
	30	}
	31	#endif
	32
27d59a4a	33	extern void *omap3_secure_ram_storage;
c40552bc	34	extern void omap3_pm_off_mode_enable(int);
99e6a4d2	35	extern void omap_sram_idle(void);
92206fd2	36	extern int omap_pm_clkdms_setup(struct clockdomain clkdm, void unused);
27d59a4a	37
fd1478cd NM	38	#if defined(CONFIG_PM_OPP)
fd1478cd NM	39	extern int omap3_opp_init(void);
f5a6422d	40	extern int omap4_opp_init(void);
fd1478cd NM	41	#else
	42	static inline int omap3_opp_init(void)
	43	{
	44	return -EINVAL;
	45	}
f5a6422d NM	46	static inline int omap4_opp_init(void)
	47	{
	48	return -EINVAL;
	49	}
fd1478cd NM	50	#endif
fd1478cd NM	51
68d4778c TK	52	extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
	53	extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
	54
8bd22949	55	#ifdef CONFIG_PM_DEBUG
ebfa88cf	56	extern u32 enable_off_mode;
ae559d87	57	#else
ebfa88cf	58	#define enable_off_mode 0
ae559d87 MG	59	#endif
	60
	61	#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
331b93f4	62	extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
8bd22949	63	#else
331b93f4	64	#define pm_dbg_update_time(pwrdm, prev) do {} while (0);
8bd22949 KH	65	#endif /* CONFIG_PM_DEBUG */
8bd22949 KH	66
46e130d2	67	/* 24xx */
8bd22949	68	extern void omap24xx_idle_loop_suspend(void);
46e130d2	69	extern unsigned int omap24xx_idle_loop_suspend_sz;
8bd22949 KH	70
	71	extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
	72	void __iomem *sdrc_power);
46e130d2 JP	73	extern unsigned int omap24xx_cpu_suspend_sz;
	74
	75	/* 3xxx */
cbe26349	76	extern void omap34xx_cpu_suspend(int save_state);
8bd22949	77
46e130d2 JP	78	/* omap3_do_wfi function pointer and size, for copy to SRAM */
	79	extern void omap3_do_wfi(void);
	80	extern unsigned int omap3_do_wfi_sz;
	81	/* ... and its pointer from SRAM after copy */
	82	extern void (*omap3_do_wfi_sram)(void);
	83
	84	/* save_secure_ram_context function pointer and size, for copy to SRAM */
	85	extern int save_secure_ram_context(u32 *addr);
8bd22949	86	extern unsigned int save_secure_ram_context_sz;
46e130d2 JP	87
46e130d2 JP	88	extern void omap3_save_scratchpad_contents(void);
8bd22949	89
458e999e	90	#define PM_RTA_ERRATUM_i608 (1 << 0)
cc1b6028	91	#define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1)
856c3c5b	92	#define PM_PER_MEMORIES_ERRATUM_i582 (1 << 2)
458e999e	93
8cdfd834 NM	94	#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
	95	extern u16 pm34xx_errata;
	96	#define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id))
c4236d2e	97	extern void enable_omap3630_toggle_l2_on_restore(void);
8cdfd834 NM	98	#else
8cdfd834 NM	99	#define IS_PM34XX_ERRATUM(id) 0
c4236d2e	100	static inline void enable_omap3630_toggle_l2_on_restore(void) { }
8cdfd834 NM	101	#endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
8cdfd834 NM	102
ff999b8a	103	#define PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD (1 << 0)
6099dd37	104	#define PM_OMAP4_CPU_OSWR_DISABLE (1 << 1)
ff999b8a	105
6d785c96 NM	106	#if defined(CONFIG_PM) && (defined(CONFIG_ARCH_OMAP4) \|\|\
6d785c96 NM	107	defined(CONFIG_SOC_OMAP5) \|\| defined(CONFIG_SOC_DRA7XX))
c9621844 TK	108	extern u16 pm44xx_errata;
	109	#define IS_PM44XX_ERRATUM(id) (pm44xx_errata & (id))
	110	#else
	111	#define IS_PM44XX_ERRATUM(id) 0
	112	#endif
	113
7fb149ff	114	#ifdef CONFIG_POWER_AVS_OMAP
0c0a5d61 TG	115	extern int omap_devinit_smartreflex(void);
	116	extern void omap_enable_smartreflex_on_init(void);
	117	#else
	118	static inline int omap_devinit_smartreflex(void)
	119	{
	120	return -EINVAL;
	121	}
	122
	123	static inline void omap_enable_smartreflex_on_init(void) {}
	124	#endif
	125
fbc319f6 TG	126	#ifdef CONFIG_TWL4030_CORE
fbc319f6 TG	127	extern int omap3_twl_init(void);
7bc3ed9a	128	extern int omap4_twl_init(void);
40713189	129	extern int omap3_twl_set_sr_bit(bool enable);
fbc319f6 TG	130	#else
	131	static inline int omap3_twl_init(void)
	132	{
	133	return -EINVAL;
	134	}
7bc3ed9a TG	135	static inline int omap4_twl_init(void)
	136	{
	137	return -EINVAL;
	138	}
fbc319f6 TG	139	#endif
fbc319f6 TG	140
908b75e8 TK	141	#ifdef CONFIG_PM
	142	extern void omap_pm_setup_oscillator(u32 tstart, u32 tshut);
	143	extern void omap_pm_get_oscillator(u32 tstart, u32 tshut);
00bd228e	144	extern void omap_pm_setup_sr_i2c_pcb_length(u32 mm);
908b75e8 TK	145	#else
908b75e8 TK	146	static inline void omap_pm_setup_oscillator(u32 tstart, u32 tshut) { }
74d29168	147	static inline void omap_pm_get_oscillator(u32 tstart, u32 tshut) { tstart = tshut = 0; }
00bd228e	148	static inline void omap_pm_setup_sr_i2c_pcb_length(u32 mm) { }
908b75e8 TK	149	#endif
908b75e8 TK	150
2e4b62dc DG	151	#ifdef CONFIG_SUSPEND
	152	void omap_common_suspend_init(void *pm_suspend);
	153	#else
	154	static inline void omap_common_suspend_init(void *pm_suspend)
	155	{
	156	}
	157	#endif /* CONFIG_SUSPEND */
8bd22949	158	#endif