Commit | Line | Data |
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8bd22949 KH |
1 | /* |
2 | * OMAP2/3 Power Management Routines | |
3 | * | |
4 | * Copyright (C) 2008 Nokia Corporation | |
5 | * Jouni Hogander | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #ifndef __ARCH_ARM_MACH_OMAP2_PM_H | |
12 | #define __ARCH_ARM_MACH_OMAP2_PM_H | |
13 | ||
0c0a5d61 TG |
14 | #include <linux/err.h> |
15 | ||
72e06d08 | 16 | #include "powerdomain.h" |
331b93f4 | 17 | |
164e0cbf DL |
18 | #ifdef CONFIG_CPU_IDLE |
19 | extern int __init omap3_idle_init(void); | |
20 | extern int __init omap4_idle_init(void); | |
21 | #else | |
22 | static inline int omap3_idle_init(void) | |
23 | { | |
24 | return 0; | |
25 | } | |
26 | ||
27 | static inline int omap4_idle_init(void) | |
28 | { | |
29 | return 0; | |
30 | } | |
31 | #endif | |
32 | ||
27d59a4a | 33 | extern void *omap3_secure_ram_storage; |
c40552bc | 34 | extern void omap3_pm_off_mode_enable(int); |
99e6a4d2 | 35 | extern void omap_sram_idle(void); |
eb6a2c75 | 36 | extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state); |
92206fd2 | 37 | extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused); |
1416408d | 38 | extern int (*omap_pm_suspend)(void); |
27d59a4a | 39 | |
fd1478cd NM |
40 | #if defined(CONFIG_PM_OPP) |
41 | extern int omap3_opp_init(void); | |
f5a6422d | 42 | extern int omap4_opp_init(void); |
fd1478cd NM |
43 | #else |
44 | static inline int omap3_opp_init(void) | |
45 | { | |
46 | return -EINVAL; | |
47 | } | |
f5a6422d NM |
48 | static inline int omap4_opp_init(void) |
49 | { | |
50 | return -EINVAL; | |
51 | } | |
fd1478cd NM |
52 | #endif |
53 | ||
68d4778c TK |
54 | extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm); |
55 | extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state); | |
56 | ||
8bd22949 | 57 | #ifdef CONFIG_PM_DEBUG |
ebfa88cf | 58 | extern u32 enable_off_mode; |
ae559d87 | 59 | #else |
ebfa88cf | 60 | #define enable_off_mode 0 |
ae559d87 MG |
61 | #endif |
62 | ||
63 | #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) | |
331b93f4 | 64 | extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev); |
8bd22949 | 65 | #else |
331b93f4 | 66 | #define pm_dbg_update_time(pwrdm, prev) do {} while (0); |
8bd22949 KH |
67 | #endif /* CONFIG_PM_DEBUG */ |
68 | ||
46e130d2 | 69 | /* 24xx */ |
8bd22949 | 70 | extern void omap24xx_idle_loop_suspend(void); |
46e130d2 | 71 | extern unsigned int omap24xx_idle_loop_suspend_sz; |
8bd22949 KH |
72 | |
73 | extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl, | |
74 | void __iomem *sdrc_power); | |
46e130d2 JP |
75 | extern unsigned int omap24xx_cpu_suspend_sz; |
76 | ||
77 | /* 3xxx */ | |
cbe26349 | 78 | extern void omap34xx_cpu_suspend(int save_state); |
8bd22949 | 79 | |
46e130d2 JP |
80 | /* omap3_do_wfi function pointer and size, for copy to SRAM */ |
81 | extern void omap3_do_wfi(void); | |
82 | extern unsigned int omap3_do_wfi_sz; | |
83 | /* ... and its pointer from SRAM after copy */ | |
84 | extern void (*omap3_do_wfi_sram)(void); | |
85 | ||
86 | /* save_secure_ram_context function pointer and size, for copy to SRAM */ | |
87 | extern int save_secure_ram_context(u32 *addr); | |
8bd22949 | 88 | extern unsigned int save_secure_ram_context_sz; |
46e130d2 JP |
89 | |
90 | extern void omap3_save_scratchpad_contents(void); | |
8bd22949 | 91 | |
458e999e | 92 | #define PM_RTA_ERRATUM_i608 (1 << 0) |
cc1b6028 | 93 | #define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1) |
856c3c5b | 94 | #define PM_PER_MEMORIES_ERRATUM_i582 (1 << 2) |
458e999e | 95 | |
8cdfd834 NM |
96 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) |
97 | extern u16 pm34xx_errata; | |
98 | #define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id)) | |
c4236d2e | 99 | extern void enable_omap3630_toggle_l2_on_restore(void); |
8cdfd834 NM |
100 | #else |
101 | #define IS_PM34XX_ERRATUM(id) 0 | |
c4236d2e | 102 | static inline void enable_omap3630_toggle_l2_on_restore(void) { } |
8cdfd834 NM |
103 | #endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */ |
104 | ||
ff999b8a SS |
105 | #define PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD (1 << 0) |
106 | ||
c9621844 TK |
107 | #if defined(CONFIG_ARCH_OMAP4) |
108 | extern u16 pm44xx_errata; | |
109 | #define IS_PM44XX_ERRATUM(id) (pm44xx_errata & (id)) | |
110 | #else | |
111 | #define IS_PM44XX_ERRATUM(id) 0 | |
112 | #endif | |
113 | ||
7fb149ff | 114 | #ifdef CONFIG_POWER_AVS_OMAP |
0c0a5d61 TG |
115 | extern int omap_devinit_smartreflex(void); |
116 | extern void omap_enable_smartreflex_on_init(void); | |
117 | #else | |
118 | static inline int omap_devinit_smartreflex(void) | |
119 | { | |
120 | return -EINVAL; | |
121 | } | |
122 | ||
123 | static inline void omap_enable_smartreflex_on_init(void) {} | |
124 | #endif | |
125 | ||
fbc319f6 TG |
126 | #ifdef CONFIG_TWL4030_CORE |
127 | extern int omap3_twl_init(void); | |
7bc3ed9a | 128 | extern int omap4_twl_init(void); |
40713189 | 129 | extern int omap3_twl_set_sr_bit(bool enable); |
fbc319f6 TG |
130 | #else |
131 | static inline int omap3_twl_init(void) | |
132 | { | |
133 | return -EINVAL; | |
134 | } | |
7bc3ed9a TG |
135 | static inline int omap4_twl_init(void) |
136 | { | |
137 | return -EINVAL; | |
138 | } | |
fbc319f6 TG |
139 | #endif |
140 | ||
908b75e8 TK |
141 | #ifdef CONFIG_PM |
142 | extern void omap_pm_setup_oscillator(u32 tstart, u32 tshut); | |
143 | extern void omap_pm_get_oscillator(u32 *tstart, u32 *tshut); | |
00bd228e | 144 | extern void omap_pm_setup_sr_i2c_pcb_length(u32 mm); |
908b75e8 TK |
145 | #else |
146 | static inline void omap_pm_setup_oscillator(u32 tstart, u32 tshut) { } | |
74d29168 | 147 | static inline void omap_pm_get_oscillator(u32 *tstart, u32 *tshut) { *tstart = *tshut = 0; } |
00bd228e | 148 | static inline void omap_pm_setup_sr_i2c_pcb_length(u32 mm) { } |
908b75e8 TK |
149 | #endif |
150 | ||
8bd22949 | 151 | #endif |