Commit | Line | Data |
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8bd22949 KH |
1 | /* |
2 | * OMAP2/3 Power Management Routines | |
3 | * | |
4 | * Copyright (C) 2008 Nokia Corporation | |
5 | * Jouni Hogander | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #ifndef __ARCH_ARM_MACH_OMAP2_PM_H | |
12 | #define __ARCH_ARM_MACH_OMAP2_PM_H | |
13 | ||
0c0a5d61 TG |
14 | #include <linux/err.h> |
15 | ||
72e06d08 | 16 | #include "powerdomain.h" |
331b93f4 | 17 | |
27d59a4a | 18 | extern void *omap3_secure_ram_storage; |
c40552bc | 19 | extern void omap3_pm_off_mode_enable(int); |
99e6a4d2 | 20 | extern void omap_sram_idle(void); |
20b01669 | 21 | extern int omap3_can_sleep(void); |
eb6a2c75 | 22 | extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state); |
0343371e | 23 | extern int omap3_idle_init(void); |
27d59a4a | 24 | |
fd1478cd NM |
25 | #if defined(CONFIG_PM_OPP) |
26 | extern int omap3_opp_init(void); | |
f5a6422d | 27 | extern int omap4_opp_init(void); |
fd1478cd NM |
28 | #else |
29 | static inline int omap3_opp_init(void) | |
30 | { | |
31 | return -EINVAL; | |
32 | } | |
f5a6422d NM |
33 | static inline int omap4_opp_init(void) |
34 | { | |
35 | return -EINVAL; | |
36 | } | |
fd1478cd NM |
37 | #endif |
38 | ||
bb4de3df | 39 | struct cpuidle_params { |
709731bb | 40 | u8 valid; |
bb4de3df KH |
41 | u32 sleep_latency; |
42 | u32 wake_latency; | |
43 | u32 threshold; | |
44 | }; | |
45 | ||
46 | #if defined(CONFIG_PM) && defined(CONFIG_CPU_IDLE) | |
47 | extern void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params); | |
48 | #else | |
49 | static | |
50 | inline void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params) | |
51 | { | |
52 | } | |
53 | #endif | |
54 | ||
68d4778c TK |
55 | extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm); |
56 | extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state); | |
57 | ||
d7814e4d | 58 | extern u32 wakeup_timer_seconds; |
8e2efde9 | 59 | extern u32 wakeup_timer_milliseconds; |
d7814e4d KH |
60 | extern struct omap_dm_timer *gptimer_wakeup; |
61 | ||
8bd22949 KH |
62 | #ifdef CONFIG_PM_DEBUG |
63 | extern void omap2_pm_dump(int mode, int resume, unsigned int us); | |
86b0c1e3 | 64 | extern void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds); |
8bd22949 | 65 | extern int omap2_pm_debug; |
ebfa88cf LM |
66 | extern u32 enable_off_mode; |
67 | extern u32 sleep_while_idle; | |
ae559d87 MG |
68 | #else |
69 | #define omap2_pm_dump(mode, resume, us) do {} while (0); | |
86b0c1e3 | 70 | #define omap2_pm_wakeup_on_timer(seconds, milliseconds) do {} while (0); |
ae559d87 | 71 | #define omap2_pm_debug 0 |
ebfa88cf LM |
72 | #define enable_off_mode 0 |
73 | #define sleep_while_idle 0 | |
ae559d87 MG |
74 | #endif |
75 | ||
6af83b38 | 76 | #if defined(CONFIG_CPU_IDLE) |
80723c3f | 77 | extern void omap3_cpuidle_update_states(u32, u32); |
6af83b38 SP |
78 | #endif |
79 | ||
ae559d87 | 80 | #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) |
331b93f4 | 81 | extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev); |
2811d6b3 TK |
82 | extern int pm_dbg_regset_save(int reg_set); |
83 | extern int pm_dbg_regset_init(int reg_set); | |
8bd22949 | 84 | #else |
331b93f4 | 85 | #define pm_dbg_update_time(pwrdm, prev) do {} while (0); |
2811d6b3 TK |
86 | #define pm_dbg_regset_save(reg_set) do {} while (0); |
87 | #define pm_dbg_regset_init(reg_set) do {} while (0); | |
8bd22949 KH |
88 | #endif /* CONFIG_PM_DEBUG */ |
89 | ||
90 | extern void omap24xx_idle_loop_suspend(void); | |
91 | ||
92 | extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl, | |
93 | void __iomem *sdrc_power); | |
94 | extern void omap34xx_cpu_suspend(u32 *addr, int save_state); | |
95 | extern void save_secure_ram_context(u32 *addr); | |
27d59a4a | 96 | extern void omap3_save_scratchpad_contents(void); |
8bd22949 KH |
97 | |
98 | extern unsigned int omap24xx_idle_loop_suspend_sz; | |
8bd22949 KH |
99 | extern unsigned int save_secure_ram_context_sz; |
100 | extern unsigned int omap24xx_cpu_suspend_sz; | |
101 | extern unsigned int omap34xx_cpu_suspend_sz; | |
102 | ||
458e999e | 103 | #define PM_RTA_ERRATUM_i608 (1 << 0) |
cc1b6028 | 104 | #define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1) |
458e999e | 105 | |
8cdfd834 NM |
106 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) |
107 | extern u16 pm34xx_errata; | |
108 | #define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id)) | |
c4236d2e | 109 | extern void enable_omap3630_toggle_l2_on_restore(void); |
8cdfd834 NM |
110 | #else |
111 | #define IS_PM34XX_ERRATUM(id) 0 | |
c4236d2e | 112 | static inline void enable_omap3630_toggle_l2_on_restore(void) { } |
8cdfd834 NM |
113 | #endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */ |
114 | ||
0c0a5d61 TG |
115 | #ifdef CONFIG_OMAP_SMARTREFLEX |
116 | extern int omap_devinit_smartreflex(void); | |
117 | extern void omap_enable_smartreflex_on_init(void); | |
118 | #else | |
119 | static inline int omap_devinit_smartreflex(void) | |
120 | { | |
121 | return -EINVAL; | |
122 | } | |
123 | ||
124 | static inline void omap_enable_smartreflex_on_init(void) {} | |
125 | #endif | |
126 | ||
8bd22949 | 127 | #endif |