Commit | Line | Data |
---|---|---|
8bd22949 KH |
1 | /* |
2 | * OMAP2 Power Management Routines | |
3 | * | |
4 | * Copyright (C) 2005 Texas Instruments, Inc. | |
5 | * Copyright (C) 2006-2008 Nokia Corporation | |
6 | * | |
7 | * Written by: | |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
9 | * Tony Lindgren | |
10 | * Juha Yrjola | |
11 | * Amit Kucheria <amit.kucheria@nokia.com> | |
12 | * Igor Stoppa <igor.stoppa@nokia.com> | |
13 | * | |
14 | * Based on pm.c for omap1 | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/suspend.h> | |
22 | #include <linux/sched.h> | |
23 | #include <linux/proc_fs.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/sysfs.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/clk.h> | |
29 | #include <linux/io.h> | |
30 | #include <linux/irq.h> | |
31 | #include <linux/time.h> | |
32 | #include <linux/gpio.h> | |
0d8e2d0d | 33 | #include <linux/console.h> |
8bd22949 KH |
34 | |
35 | #include <asm/mach/time.h> | |
36 | #include <asm/mach/irq.h> | |
37 | #include <asm/mach-types.h> | |
38 | ||
39 | #include <mach/irqs.h> | |
ce491cf8 TL |
40 | #include <plat/clock.h> |
41 | #include <plat/sram.h> | |
ce491cf8 TL |
42 | #include <plat/dma.h> |
43 | #include <plat/board.h> | |
8bd22949 | 44 | |
59fb659b | 45 | #include "prm2xxx_3xxx.h" |
8bd22949 | 46 | #include "prm-regbits-24xx.h" |
59fb659b | 47 | #include "cm2xxx_3xxx.h" |
8bd22949 KH |
48 | #include "cm-regbits-24xx.h" |
49 | #include "sdrc.h" | |
50 | #include "pm.h" | |
4814ced5 | 51 | #include "control.h" |
8bd22949 | 52 | |
72e06d08 | 53 | #include "powerdomain.h" |
1540f214 | 54 | #include "clockdomain.h" |
8bd22949 | 55 | |
e83df17f KH |
56 | #ifdef CONFIG_SUSPEND |
57 | static suspend_state_t suspend_state = PM_SUSPEND_ON; | |
58 | static inline bool is_suspending(void) | |
59 | { | |
60 | return (suspend_state != PM_SUSPEND_ON); | |
61 | } | |
62 | #else | |
63 | static inline bool is_suspending(void) | |
64 | { | |
65 | return false; | |
66 | } | |
67 | #endif | |
68 | ||
8bd22949 KH |
69 | static void (*omap2_sram_idle)(void); |
70 | static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl, | |
71 | void __iomem *sdrc_power); | |
72 | ||
369d5614 PW |
73 | static struct powerdomain *mpu_pwrdm, *core_pwrdm; |
74 | static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm; | |
8bd22949 KH |
75 | |
76 | static struct clk *osc_ck, *emul_ck; | |
77 | ||
78 | static int omap2_fclks_active(void) | |
79 | { | |
80 | u32 f1, f2; | |
81 | ||
c4d7e58f PW |
82 | f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); |
83 | f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); | |
4af4016c KH |
84 | |
85 | /* Ignore UART clocks. These are handled by UART core (serial.c) */ | |
2fd0f75c PW |
86 | f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK); |
87 | f2 &= ~OMAP24XX_EN_UART3_MASK; | |
4af4016c | 88 | |
8bd22949 KH |
89 | if (f1 | f2) |
90 | return 1; | |
91 | return 0; | |
92 | } | |
93 | ||
8bd22949 KH |
94 | static void omap2_enter_full_retention(void) |
95 | { | |
96 | u32 l; | |
97 | struct timespec ts_preidle, ts_postidle, ts_idle; | |
98 | ||
99 | /* There is 1 reference hold for all children of the oscillator | |
100 | * clock, the following will remove it. If no one else uses the | |
101 | * oscillator itself it will be disabled if/when we enter retention | |
102 | * mode. | |
103 | */ | |
104 | clk_disable(osc_ck); | |
105 | ||
106 | /* Clear old wake-up events */ | |
107 | /* REVISIT: These write to reserved bits? */ | |
c4d7e58f PW |
108 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); |
109 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); | |
110 | omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); | |
8bd22949 KH |
111 | |
112 | /* | |
113 | * Set MPU powerdomain's next power state to RETENTION; | |
114 | * preserve logic state during retention | |
115 | */ | |
116 | pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET); | |
117 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); | |
118 | ||
119 | /* Workaround to kill USB */ | |
120 | l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL; | |
121 | omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0); | |
122 | ||
72e06d08 | 123 | omap2_gpio_prepare_for_idle(0); |
8bd22949 KH |
124 | |
125 | if (omap2_pm_debug) { | |
126 | omap2_pm_dump(0, 0, 0); | |
127 | getnstimeofday(&ts_preidle); | |
128 | } | |
129 | ||
130 | /* One last check for pending IRQs to avoid extra latency due | |
131 | * to sleeping unnecessarily. */ | |
94434535 | 132 | if (omap_irq_pending()) |
8bd22949 KH |
133 | goto no_sleep; |
134 | ||
0d8e2d0d | 135 | /* Block console output in case it is on one of the OMAP UARTs */ |
e83df17f | 136 | if (!is_suspending()) |
ac751efa | 137 | if (!console_trylock()) |
e83df17f | 138 | goto no_sleep; |
0d8e2d0d | 139 | |
4af4016c KH |
140 | omap_uart_prepare_idle(0); |
141 | omap_uart_prepare_idle(1); | |
142 | omap_uart_prepare_idle(2); | |
143 | ||
8bd22949 KH |
144 | /* Jump to SRAM suspend code */ |
145 | omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL), | |
146 | OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL), | |
147 | OMAP_SDRC_REGADDR(SDRC_POWER)); | |
8bd22949 | 148 | |
4af4016c KH |
149 | omap_uart_resume_idle(2); |
150 | omap_uart_resume_idle(1); | |
151 | omap_uart_resume_idle(0); | |
152 | ||
e83df17f | 153 | if (!is_suspending()) |
ac751efa | 154 | console_unlock(); |
0d8e2d0d | 155 | |
4af4016c | 156 | no_sleep: |
8bd22949 KH |
157 | if (omap2_pm_debug) { |
158 | unsigned long long tmp; | |
159 | ||
160 | getnstimeofday(&ts_postidle); | |
161 | ts_idle = timespec_sub(ts_postidle, ts_preidle); | |
162 | tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC; | |
163 | omap2_pm_dump(0, 1, tmp); | |
164 | } | |
43ffcd9a | 165 | omap2_gpio_resume_after_idle(); |
8bd22949 KH |
166 | |
167 | clk_enable(osc_ck); | |
168 | ||
169 | /* clear CORE wake-up events */ | |
c4d7e58f PW |
170 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); |
171 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); | |
8bd22949 KH |
172 | |
173 | /* wakeup domain events - bit 1: GPT1, bit5 GPIO */ | |
c4d7e58f | 174 | omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); |
8bd22949 KH |
175 | |
176 | /* MPU domain wake events */ | |
c4d7e58f | 177 | l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
8bd22949 | 178 | if (l & 0x01) |
c4d7e58f | 179 | omap2_prm_write_mod_reg(0x01, OCP_MOD, |
8bd22949 KH |
180 | OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
181 | if (l & 0x20) | |
c4d7e58f | 182 | omap2_prm_write_mod_reg(0x20, OCP_MOD, |
8bd22949 KH |
183 | OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
184 | ||
185 | /* Mask future PRCM-to-MPU interrupts */ | |
c4d7e58f | 186 | omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
8bd22949 KH |
187 | } |
188 | ||
189 | static int omap2_i2c_active(void) | |
190 | { | |
191 | u32 l; | |
192 | ||
c4d7e58f | 193 | l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); |
f38ca10a | 194 | return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK); |
8bd22949 KH |
195 | } |
196 | ||
197 | static int sti_console_enabled; | |
198 | ||
199 | static int omap2_allow_mpu_retention(void) | |
200 | { | |
201 | u32 l; | |
202 | ||
203 | /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */ | |
c4d7e58f | 204 | l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); |
2fd0f75c PW |
205 | if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK | |
206 | OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK | | |
207 | OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK)) | |
8bd22949 KH |
208 | return 0; |
209 | /* Check for UART3. */ | |
c4d7e58f | 210 | l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); |
2fd0f75c | 211 | if (l & OMAP24XX_EN_UART3_MASK) |
8bd22949 KH |
212 | return 0; |
213 | if (sti_console_enabled) | |
214 | return 0; | |
215 | ||
216 | return 1; | |
217 | } | |
218 | ||
219 | static void omap2_enter_mpu_retention(void) | |
220 | { | |
221 | int only_idle = 0; | |
222 | struct timespec ts_preidle, ts_postidle, ts_idle; | |
223 | ||
224 | /* Putting MPU into the WFI state while a transfer is active | |
225 | * seems to cause the I2C block to timeout. Why? Good question. */ | |
226 | if (omap2_i2c_active()) | |
227 | return; | |
228 | ||
229 | /* The peripherals seem not to be able to wake up the MPU when | |
230 | * it is in retention mode. */ | |
231 | if (omap2_allow_mpu_retention()) { | |
232 | /* REVISIT: These write to reserved bits? */ | |
c4d7e58f PW |
233 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); |
234 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); | |
235 | omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); | |
8bd22949 KH |
236 | |
237 | /* Try to enter MPU retention */ | |
c4d7e58f | 238 | omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | |
2fd0f75c | 239 | OMAP_LOGICRETSTATE_MASK, |
37903009 | 240 | MPU_MOD, OMAP2_PM_PWSTCTRL); |
8bd22949 KH |
241 | } else { |
242 | /* Block MPU retention */ | |
243 | ||
c4d7e58f | 244 | omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD, |
37903009 | 245 | OMAP2_PM_PWSTCTRL); |
8bd22949 KH |
246 | only_idle = 1; |
247 | } | |
248 | ||
249 | if (omap2_pm_debug) { | |
250 | omap2_pm_dump(only_idle ? 2 : 1, 0, 0); | |
251 | getnstimeofday(&ts_preidle); | |
252 | } | |
253 | ||
254 | omap2_sram_idle(); | |
255 | ||
256 | if (omap2_pm_debug) { | |
257 | unsigned long long tmp; | |
258 | ||
259 | getnstimeofday(&ts_postidle); | |
260 | ts_idle = timespec_sub(ts_postidle, ts_preidle); | |
261 | tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC; | |
262 | omap2_pm_dump(only_idle ? 2 : 1, 1, tmp); | |
263 | } | |
264 | } | |
265 | ||
266 | static int omap2_can_sleep(void) | |
267 | { | |
268 | if (omap2_fclks_active()) | |
269 | return 0; | |
503923ee KH |
270 | if (!omap_uart_can_sleep()) |
271 | return 0; | |
8bd22949 KH |
272 | if (osc_ck->usecount > 1) |
273 | return 0; | |
274 | if (omap_dma_running()) | |
275 | return 0; | |
276 | ||
277 | return 1; | |
278 | } | |
279 | ||
280 | static void omap2_pm_idle(void) | |
281 | { | |
282 | local_irq_disable(); | |
283 | local_fiq_disable(); | |
284 | ||
285 | if (!omap2_can_sleep()) { | |
94434535 | 286 | if (omap_irq_pending()) |
8bd22949 KH |
287 | goto out; |
288 | omap2_enter_mpu_retention(); | |
289 | goto out; | |
290 | } | |
291 | ||
94434535 | 292 | if (omap_irq_pending()) |
8bd22949 KH |
293 | goto out; |
294 | ||
295 | omap2_enter_full_retention(); | |
296 | ||
297 | out: | |
298 | local_fiq_enable(); | |
299 | local_irq_enable(); | |
300 | } | |
301 | ||
05fad3e7 | 302 | #ifdef CONFIG_SUSPEND |
e83df17f KH |
303 | static int omap2_pm_begin(suspend_state_t state) |
304 | { | |
8bd22949 | 305 | disable_hlt(); |
c166381d | 306 | suspend_state = state; |
8bd22949 KH |
307 | return 0; |
308 | } | |
309 | ||
310 | static int omap2_pm_suspend(void) | |
311 | { | |
312 | u32 wken_wkup, mir1; | |
313 | ||
c4d7e58f | 314 | wken_wkup = omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); |
2fd0f75c | 315 | wken_wkup &= ~OMAP24XX_EN_GPT1_MASK; |
c4d7e58f | 316 | omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); |
8bd22949 KH |
317 | |
318 | /* Mask GPT1 */ | |
319 | mir1 = omap_readl(0x480fe0a4); | |
320 | omap_writel(1 << 5, 0x480fe0ac); | |
321 | ||
4af4016c | 322 | omap_uart_prepare_suspend(); |
8bd22949 KH |
323 | omap2_enter_full_retention(); |
324 | ||
325 | omap_writel(mir1, 0x480fe0a4); | |
c4d7e58f | 326 | omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); |
8bd22949 KH |
327 | |
328 | return 0; | |
329 | } | |
330 | ||
331 | static int omap2_pm_enter(suspend_state_t state) | |
332 | { | |
333 | int ret = 0; | |
334 | ||
335 | switch (state) { | |
336 | case PM_SUSPEND_STANDBY: | |
337 | case PM_SUSPEND_MEM: | |
338 | ret = omap2_pm_suspend(); | |
339 | break; | |
340 | default: | |
341 | ret = -EINVAL; | |
342 | } | |
343 | ||
344 | return ret; | |
345 | } | |
346 | ||
e83df17f KH |
347 | static void omap2_pm_end(void) |
348 | { | |
349 | suspend_state = PM_SUSPEND_ON; | |
c166381d | 350 | enable_hlt(); |
e83df17f KH |
351 | } |
352 | ||
2f55ac07 | 353 | static const struct platform_suspend_ops omap_pm_ops = { |
e83df17f | 354 | .begin = omap2_pm_begin, |
8bd22949 | 355 | .enter = omap2_pm_enter, |
e83df17f | 356 | .end = omap2_pm_end, |
8bd22949 KH |
357 | .valid = suspend_valid_only_mem, |
358 | }; | |
05fad3e7 KH |
359 | #else |
360 | static const struct platform_suspend_ops __initdata omap_pm_ops; | |
361 | #endif /* CONFIG_SUSPEND */ | |
8bd22949 | 362 | |
369d5614 PW |
363 | /* XXX This function should be shareable between OMAP2xxx and OMAP3 */ |
364 | static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) | |
8bd22949 | 365 | { |
369d5614 PW |
366 | clkdm_clear_all_wkdeps(clkdm); |
367 | clkdm_clear_all_sleepdeps(clkdm); | |
368 | ||
369 | if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) | |
370 | omap2_clkdm_allow_idle(clkdm); | |
371 | else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && | |
372 | atomic_read(&clkdm->usecount) == 0) | |
373 | omap2_clkdm_sleep(clkdm); | |
8bd22949 KH |
374 | return 0; |
375 | } | |
376 | ||
377 | static void __init prcm_setup_regs(void) | |
378 | { | |
379 | int i, num_mem_banks; | |
380 | struct powerdomain *pwrdm; | |
381 | ||
382 | /* Enable autoidle */ | |
c4d7e58f | 383 | omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD, |
8bd22949 KH |
384 | OMAP2_PRCM_SYSCONFIG_OFFSET); |
385 | ||
8bd22949 KH |
386 | /* |
387 | * Set CORE powerdomain memory banks to retain their contents | |
388 | * during RETENTION | |
389 | */ | |
390 | num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm); | |
391 | for (i = 0; i < num_mem_banks; i++) | |
392 | pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET); | |
393 | ||
394 | /* Set CORE powerdomain's next power state to RETENTION */ | |
395 | pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET); | |
396 | ||
397 | /* | |
398 | * Set MPU powerdomain's next power state to RETENTION; | |
399 | * preserve logic state during retention | |
400 | */ | |
401 | pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET); | |
402 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); | |
403 | ||
404 | /* Force-power down DSP, GFX powerdomains */ | |
405 | ||
406 | pwrdm = clkdm_get_pwrdm(dsp_clkdm); | |
407 | pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); | |
408 | omap2_clkdm_sleep(dsp_clkdm); | |
409 | ||
410 | pwrdm = clkdm_get_pwrdm(gfx_clkdm); | |
411 | pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); | |
412 | omap2_clkdm_sleep(gfx_clkdm); | |
413 | ||
369d5614 PW |
414 | /* |
415 | * Clear clockdomain wakeup dependencies and enable | |
416 | * hardware-supervised idle for all clkdms | |
417 | */ | |
418 | clkdm_for_each(clkdms_setup, NULL); | |
419 | clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); | |
8bd22949 KH |
420 | |
421 | /* Enable clock autoidle for all domains */ | |
c4d7e58f PW |
422 | omap2_cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK | |
423 | OMAP24XX_AUTO_MAILBOXES_MASK | | |
424 | OMAP24XX_AUTO_WDT4_MASK | | |
425 | OMAP2420_AUTO_WDT3_MASK | | |
426 | OMAP24XX_AUTO_MSPRO_MASK | | |
427 | OMAP2420_AUTO_MMC_MASK | | |
428 | OMAP24XX_AUTO_FAC_MASK | | |
429 | OMAP2420_AUTO_EAC_MASK | | |
430 | OMAP24XX_AUTO_HDQ_MASK | | |
431 | OMAP24XX_AUTO_UART2_MASK | | |
432 | OMAP24XX_AUTO_UART1_MASK | | |
433 | OMAP24XX_AUTO_I2C2_MASK | | |
434 | OMAP24XX_AUTO_I2C1_MASK | | |
435 | OMAP24XX_AUTO_MCSPI2_MASK | | |
436 | OMAP24XX_AUTO_MCSPI1_MASK | | |
437 | OMAP24XX_AUTO_MCBSP2_MASK | | |
438 | OMAP24XX_AUTO_MCBSP1_MASK | | |
439 | OMAP24XX_AUTO_GPT12_MASK | | |
440 | OMAP24XX_AUTO_GPT11_MASK | | |
441 | OMAP24XX_AUTO_GPT10_MASK | | |
442 | OMAP24XX_AUTO_GPT9_MASK | | |
443 | OMAP24XX_AUTO_GPT8_MASK | | |
444 | OMAP24XX_AUTO_GPT7_MASK | | |
445 | OMAP24XX_AUTO_GPT6_MASK | | |
446 | OMAP24XX_AUTO_GPT5_MASK | | |
447 | OMAP24XX_AUTO_GPT4_MASK | | |
448 | OMAP24XX_AUTO_GPT3_MASK | | |
449 | OMAP24XX_AUTO_GPT2_MASK | | |
450 | OMAP2420_AUTO_VLYNQ_MASK | | |
451 | OMAP24XX_AUTO_DSS_MASK, | |
452 | CORE_MOD, CM_AUTOIDLE1); | |
453 | omap2_cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK | | |
454 | OMAP24XX_AUTO_SSI_MASK | | |
455 | OMAP24XX_AUTO_USB_MASK, | |
456 | CORE_MOD, CM_AUTOIDLE2); | |
457 | omap2_cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK | | |
458 | OMAP24XX_AUTO_GPMC_MASK | | |
459 | OMAP24XX_AUTO_SDMA_MASK, | |
460 | CORE_MOD, CM_AUTOIDLE3); | |
461 | omap2_cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK | | |
462 | OMAP24XX_AUTO_AES_MASK | | |
463 | OMAP24XX_AUTO_RNG_MASK | | |
464 | OMAP24XX_AUTO_SHA_MASK | | |
465 | OMAP24XX_AUTO_DES_MASK, | |
466 | CORE_MOD, OMAP24XX_CM_AUTOIDLE4); | |
467 | ||
468 | omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD, | |
469 | CM_AUTOIDLE); | |
8bd22949 KH |
470 | |
471 | /* Put DPLL and both APLLs into autoidle mode */ | |
c4d7e58f PW |
472 | omap2_cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) | |
473 | (0x03 << OMAP24XX_AUTO_96M_SHIFT) | | |
474 | (0x03 << OMAP24XX_AUTO_54M_SHIFT), | |
475 | PLL_MOD, CM_AUTOIDLE); | |
476 | ||
477 | omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK | | |
478 | OMAP24XX_AUTO_WDT1_MASK | | |
479 | OMAP24XX_AUTO_MPU_WDT_MASK | | |
480 | OMAP24XX_AUTO_GPIOS_MASK | | |
481 | OMAP24XX_AUTO_32KSYNC_MASK | | |
482 | OMAP24XX_AUTO_GPT1_MASK, | |
483 | WKUP_MOD, CM_AUTOIDLE); | |
8bd22949 KH |
484 | |
485 | /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk | |
486 | * stabilisation */ | |
c4d7e58f PW |
487 | omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, |
488 | OMAP2_PRCM_CLKSSETUP_OFFSET); | |
8bd22949 KH |
489 | |
490 | /* Configure automatic voltage transition */ | |
c4d7e58f PW |
491 | omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, |
492 | OMAP2_PRCM_VOLTSETUP_OFFSET); | |
493 | omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK | | |
494 | (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | | |
495 | OMAP24XX_MEMRETCTRL_MASK | | |
496 | (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | | |
497 | (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT), | |
498 | OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET); | |
8bd22949 KH |
499 | |
500 | /* Enable wake-up events */ | |
c4d7e58f PW |
501 | omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK, |
502 | WKUP_MOD, PM_WKEN); | |
8bd22949 KH |
503 | } |
504 | ||
7cc515f7 | 505 | static int __init omap2_pm_init(void) |
8bd22949 KH |
506 | { |
507 | u32 l; | |
508 | ||
509 | if (!cpu_is_omap24xx()) | |
510 | return -ENODEV; | |
511 | ||
512 | printk(KERN_INFO "Power Management for OMAP2 initializing\n"); | |
c4d7e58f | 513 | l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET); |
8bd22949 KH |
514 | printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); |
515 | ||
369d5614 | 516 | /* Look up important powerdomains */ |
8bd22949 KH |
517 | |
518 | mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); | |
519 | if (!mpu_pwrdm) | |
520 | pr_err("PM: mpu_pwrdm not found\n"); | |
521 | ||
522 | core_pwrdm = pwrdm_lookup("core_pwrdm"); | |
523 | if (!core_pwrdm) | |
524 | pr_err("PM: core_pwrdm not found\n"); | |
525 | ||
369d5614 PW |
526 | /* Look up important clockdomains */ |
527 | ||
528 | mpu_clkdm = clkdm_lookup("mpu_clkdm"); | |
529 | if (!mpu_clkdm) | |
530 | pr_err("PM: mpu_clkdm not found\n"); | |
531 | ||
532 | wkup_clkdm = clkdm_lookup("wkup_clkdm"); | |
533 | if (!wkup_clkdm) | |
534 | pr_err("PM: wkup_clkdm not found\n"); | |
535 | ||
8bd22949 KH |
536 | dsp_clkdm = clkdm_lookup("dsp_clkdm"); |
537 | if (!dsp_clkdm) | |
369d5614 | 538 | pr_err("PM: dsp_clkdm not found\n"); |
8bd22949 KH |
539 | |
540 | gfx_clkdm = clkdm_lookup("gfx_clkdm"); | |
541 | if (!gfx_clkdm) | |
542 | pr_err("PM: gfx_clkdm not found\n"); | |
543 | ||
544 | ||
545 | osc_ck = clk_get(NULL, "osc_ck"); | |
546 | if (IS_ERR(osc_ck)) { | |
547 | printk(KERN_ERR "could not get osc_ck\n"); | |
548 | return -ENODEV; | |
549 | } | |
550 | ||
551 | if (cpu_is_omap242x()) { | |
552 | emul_ck = clk_get(NULL, "emul_ck"); | |
553 | if (IS_ERR(emul_ck)) { | |
554 | printk(KERN_ERR "could not get emul_ck\n"); | |
555 | clk_put(osc_ck); | |
556 | return -ENODEV; | |
557 | } | |
558 | } | |
559 | ||
560 | prcm_setup_regs(); | |
561 | ||
562 | /* Hack to prevent MPU retention when STI console is enabled. */ | |
563 | { | |
564 | const struct omap_sti_console_config *sti; | |
565 | ||
566 | sti = omap_get_config(OMAP_TAG_STI_CONSOLE, | |
567 | struct omap_sti_console_config); | |
568 | if (sti != NULL && sti->enable) | |
569 | sti_console_enabled = 1; | |
570 | } | |
571 | ||
572 | /* | |
573 | * We copy the assembler sleep/wakeup routines to SRAM. | |
574 | * These routines need to be in SRAM as that's the only | |
575 | * memory the MPU can see when it wakes up. | |
576 | */ | |
577 | if (cpu_is_omap24xx()) { | |
578 | omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend, | |
579 | omap24xx_idle_loop_suspend_sz); | |
580 | ||
581 | omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend, | |
582 | omap24xx_cpu_suspend_sz); | |
583 | } | |
584 | ||
585 | suspend_set_ops(&omap_pm_ops); | |
586 | pm_idle = omap2_pm_idle; | |
587 | ||
588 | return 0; | |
589 | } | |
590 | ||
591 | late_initcall(omap2_pm_init); |