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8bd22949 KH |
1 | /* |
2 | * OMAP2 Power Management Routines | |
3 | * | |
4 | * Copyright (C) 2005 Texas Instruments, Inc. | |
5 | * Copyright (C) 2006-2008 Nokia Corporation | |
6 | * | |
7 | * Written by: | |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
9 | * Tony Lindgren | |
10 | * Juha Yrjola | |
11 | * Amit Kucheria <amit.kucheria@nokia.com> | |
12 | * Igor Stoppa <igor.stoppa@nokia.com> | |
13 | * | |
14 | * Based on pm.c for omap1 | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/suspend.h> | |
22 | #include <linux/sched.h> | |
23 | #include <linux/proc_fs.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/sysfs.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/delay.h> | |
ed1ebc49 | 28 | #include <linux/clk-provider.h> |
8bd22949 KH |
29 | #include <linux/irq.h> |
30 | #include <linux/time.h> | |
31 | #include <linux/gpio.h> | |
4b25408f | 32 | #include <linux/platform_data/gpio-omap.h> |
8bd22949 | 33 | |
bf027ca1 TL |
34 | #include <asm/fncpy.h> |
35 | ||
8bd22949 KH |
36 | #include <asm/mach/time.h> |
37 | #include <asm/mach/irq.h> | |
38 | #include <asm/mach-types.h> | |
9f97da78 | 39 | #include <asm/system_misc.h> |
8bd22949 | 40 | |
45c3eb7d | 41 | #include <linux/omap-dma.h> |
8bd22949 | 42 | |
e4c060db | 43 | #include "soc.h" |
4e65331c | 44 | #include "common.h" |
a135eaae | 45 | #include "clock.h" |
139563ad | 46 | #include "prm2xxx.h" |
8bd22949 | 47 | #include "prm-regbits-24xx.h" |
ff4ae5d9 | 48 | #include "cm2xxx.h" |
8bd22949 KH |
49 | #include "cm-regbits-24xx.h" |
50 | #include "sdrc.h" | |
bf027ca1 | 51 | #include "sram.h" |
8bd22949 | 52 | #include "pm.h" |
4814ced5 | 53 | #include "control.h" |
72e06d08 | 54 | #include "powerdomain.h" |
1540f214 | 55 | #include "clockdomain.h" |
8bd22949 | 56 | |
8bd22949 KH |
57 | static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl, |
58 | void __iomem *sdrc_power); | |
59 | ||
369d5614 PW |
60 | static struct powerdomain *mpu_pwrdm, *core_pwrdm; |
61 | static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm; | |
8bd22949 KH |
62 | |
63 | static struct clk *osc_ck, *emul_ck; | |
64 | ||
1416408d | 65 | static int omap2_enter_full_retention(void) |
8bd22949 KH |
66 | { |
67 | u32 l; | |
8bd22949 KH |
68 | |
69 | /* There is 1 reference hold for all children of the oscillator | |
70 | * clock, the following will remove it. If no one else uses the | |
71 | * oscillator itself it will be disabled if/when we enter retention | |
72 | * mode. | |
73 | */ | |
74 | clk_disable(osc_ck); | |
75 | ||
76 | /* Clear old wake-up events */ | |
77 | /* REVISIT: These write to reserved bits? */ | |
c4d7e58f PW |
78 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); |
79 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); | |
80 | omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); | |
8bd22949 | 81 | |
f653b298 | 82 | pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET); |
8bd22949 KH |
83 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); |
84 | ||
85 | /* Workaround to kill USB */ | |
86 | l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL; | |
87 | omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0); | |
88 | ||
72e06d08 | 89 | omap2_gpio_prepare_for_idle(0); |
8bd22949 | 90 | |
8bd22949 KH |
91 | /* One last check for pending IRQs to avoid extra latency due |
92 | * to sleeping unnecessarily. */ | |
94434535 | 93 | if (omap_irq_pending()) |
8bd22949 KH |
94 | goto no_sleep; |
95 | ||
96 | /* Jump to SRAM suspend code */ | |
97 | omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL), | |
98 | OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL), | |
99 | OMAP_SDRC_REGADDR(SDRC_POWER)); | |
8bd22949 | 100 | |
4af4016c | 101 | no_sleep: |
43ffcd9a | 102 | omap2_gpio_resume_after_idle(); |
8bd22949 KH |
103 | |
104 | clk_enable(osc_ck); | |
105 | ||
106 | /* clear CORE wake-up events */ | |
c4d7e58f PW |
107 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); |
108 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); | |
8bd22949 KH |
109 | |
110 | /* wakeup domain events - bit 1: GPT1, bit5 GPIO */ | |
c4d7e58f | 111 | omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); |
8bd22949 KH |
112 | |
113 | /* MPU domain wake events */ | |
c4d7e58f | 114 | l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
8bd22949 | 115 | if (l & 0x01) |
c4d7e58f | 116 | omap2_prm_write_mod_reg(0x01, OCP_MOD, |
8bd22949 KH |
117 | OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
118 | if (l & 0x20) | |
c4d7e58f | 119 | omap2_prm_write_mod_reg(0x20, OCP_MOD, |
8bd22949 KH |
120 | OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
121 | ||
122 | /* Mask future PRCM-to-MPU interrupts */ | |
c4d7e58f | 123 | omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
1416408d | 124 | |
f653b298 PW |
125 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); |
126 | pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON); | |
127 | ||
1416408d | 128 | return 0; |
8bd22949 KH |
129 | } |
130 | ||
8bd22949 KH |
131 | static int sti_console_enabled; |
132 | ||
133 | static int omap2_allow_mpu_retention(void) | |
134 | { | |
cd6e9db2 | 135 | if (!omap2xxx_cm_mpu_retention_allowed()) |
8bd22949 KH |
136 | return 0; |
137 | if (sti_console_enabled) | |
138 | return 0; | |
139 | ||
140 | return 1; | |
141 | } | |
142 | ||
143 | static void omap2_enter_mpu_retention(void) | |
144 | { | |
088e8806 PW |
145 | const int zero = 0; |
146 | ||
8bd22949 KH |
147 | /* The peripherals seem not to be able to wake up the MPU when |
148 | * it is in retention mode. */ | |
149 | if (omap2_allow_mpu_retention()) { | |
150 | /* REVISIT: These write to reserved bits? */ | |
c4d7e58f PW |
151 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); |
152 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); | |
153 | omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); | |
8bd22949 KH |
154 | |
155 | /* Try to enter MPU retention */ | |
f653b298 PW |
156 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); |
157 | ||
8bd22949 KH |
158 | } else { |
159 | /* Block MPU retention */ | |
f653b298 | 160 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); |
8bd22949 KH |
161 | } |
162 | ||
088e8806 PW |
163 | /* WFI */ |
164 | asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (zero) : "memory", "cc"); | |
f653b298 PW |
165 | |
166 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); | |
8bd22949 KH |
167 | } |
168 | ||
169 | static int omap2_can_sleep(void) | |
170 | { | |
cd6e9db2 | 171 | if (omap2xxx_cm_fclks_active()) |
8bd22949 | 172 | return 0; |
ed1ebc49 | 173 | if (__clk_is_enabled(osc_ck)) |
8bd22949 KH |
174 | return 0; |
175 | if (omap_dma_running()) | |
176 | return 0; | |
177 | ||
178 | return 1; | |
179 | } | |
180 | ||
181 | static void omap2_pm_idle(void) | |
182 | { | |
8bd22949 | 183 | if (!omap2_can_sleep()) { |
94434535 | 184 | if (omap_irq_pending()) |
6b85638b | 185 | return; |
8bd22949 | 186 | omap2_enter_mpu_retention(); |
6b85638b | 187 | return; |
8bd22949 KH |
188 | } |
189 | ||
94434535 | 190 | if (omap_irq_pending()) |
6b85638b | 191 | return; |
8bd22949 KH |
192 | |
193 | omap2_enter_full_retention(); | |
8bd22949 KH |
194 | } |
195 | ||
8bd22949 KH |
196 | static void __init prcm_setup_regs(void) |
197 | { | |
198 | int i, num_mem_banks; | |
199 | struct powerdomain *pwrdm; | |
200 | ||
4ef70c06 PW |
201 | /* |
202 | * Enable autoidle | |
203 | * XXX This should be handled by hwmod code or PRCM init code | |
204 | */ | |
c4d7e58f | 205 | omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD, |
8bd22949 KH |
206 | OMAP2_PRCM_SYSCONFIG_OFFSET); |
207 | ||
8bd22949 KH |
208 | /* |
209 | * Set CORE powerdomain memory banks to retain their contents | |
210 | * during RETENTION | |
211 | */ | |
212 | num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm); | |
213 | for (i = 0; i < num_mem_banks; i++) | |
214 | pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET); | |
215 | ||
f653b298 | 216 | pwrdm_set_logic_retst(core_pwrdm, PWRDM_POWER_RET); |
8bd22949 | 217 | |
8bd22949 | 218 | pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET); |
8bd22949 KH |
219 | |
220 | /* Force-power down DSP, GFX powerdomains */ | |
221 | ||
222 | pwrdm = clkdm_get_pwrdm(dsp_clkdm); | |
223 | pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); | |
8bd22949 KH |
224 | |
225 | pwrdm = clkdm_get_pwrdm(gfx_clkdm); | |
226 | pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); | |
8bd22949 | 227 | |
51d070af | 228 | /* Enable hardware-supervised idle for all clkdms */ |
92206fd2 | 229 | clkdm_for_each(omap_pm_clkdms_setup, NULL); |
369d5614 | 230 | clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); |
8bd22949 | 231 | |
2e4b62dc | 232 | omap_common_suspend_init(omap2_enter_full_retention); |
1416408d | 233 | |
8bd22949 KH |
234 | /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk |
235 | * stabilisation */ | |
c4d7e58f PW |
236 | omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, |
237 | OMAP2_PRCM_CLKSSETUP_OFFSET); | |
8bd22949 KH |
238 | |
239 | /* Configure automatic voltage transition */ | |
c4d7e58f PW |
240 | omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, |
241 | OMAP2_PRCM_VOLTSETUP_OFFSET); | |
242 | omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK | | |
243 | (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | | |
244 | OMAP24XX_MEMRETCTRL_MASK | | |
245 | (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | | |
246 | (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT), | |
247 | OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET); | |
8bd22949 KH |
248 | |
249 | /* Enable wake-up events */ | |
c4d7e58f PW |
250 | omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK, |
251 | WKUP_MOD, PM_WKEN); | |
8bd22949 KH |
252 | } |
253 | ||
bbd707ac | 254 | int __init omap2_pm_init(void) |
8bd22949 KH |
255 | { |
256 | u32 l; | |
257 | ||
8bd22949 | 258 | printk(KERN_INFO "Power Management for OMAP2 initializing\n"); |
c4d7e58f | 259 | l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET); |
8bd22949 KH |
260 | printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); |
261 | ||
369d5614 | 262 | /* Look up important powerdomains */ |
8bd22949 KH |
263 | |
264 | mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); | |
265 | if (!mpu_pwrdm) | |
266 | pr_err("PM: mpu_pwrdm not found\n"); | |
267 | ||
268 | core_pwrdm = pwrdm_lookup("core_pwrdm"); | |
269 | if (!core_pwrdm) | |
270 | pr_err("PM: core_pwrdm not found\n"); | |
271 | ||
369d5614 PW |
272 | /* Look up important clockdomains */ |
273 | ||
274 | mpu_clkdm = clkdm_lookup("mpu_clkdm"); | |
275 | if (!mpu_clkdm) | |
276 | pr_err("PM: mpu_clkdm not found\n"); | |
277 | ||
278 | wkup_clkdm = clkdm_lookup("wkup_clkdm"); | |
279 | if (!wkup_clkdm) | |
280 | pr_err("PM: wkup_clkdm not found\n"); | |
281 | ||
8bd22949 KH |
282 | dsp_clkdm = clkdm_lookup("dsp_clkdm"); |
283 | if (!dsp_clkdm) | |
369d5614 | 284 | pr_err("PM: dsp_clkdm not found\n"); |
8bd22949 KH |
285 | |
286 | gfx_clkdm = clkdm_lookup("gfx_clkdm"); | |
287 | if (!gfx_clkdm) | |
288 | pr_err("PM: gfx_clkdm not found\n"); | |
289 | ||
290 | ||
291 | osc_ck = clk_get(NULL, "osc_ck"); | |
292 | if (IS_ERR(osc_ck)) { | |
293 | printk(KERN_ERR "could not get osc_ck\n"); | |
294 | return -ENODEV; | |
295 | } | |
296 | ||
297 | if (cpu_is_omap242x()) { | |
298 | emul_ck = clk_get(NULL, "emul_ck"); | |
299 | if (IS_ERR(emul_ck)) { | |
300 | printk(KERN_ERR "could not get emul_ck\n"); | |
301 | clk_put(osc_ck); | |
302 | return -ENODEV; | |
303 | } | |
304 | } | |
305 | ||
306 | prcm_setup_regs(); | |
307 | ||
8bd22949 KH |
308 | /* |
309 | * We copy the assembler sleep/wakeup routines to SRAM. | |
310 | * These routines need to be in SRAM as that's the only | |
088e8806 PW |
311 | * memory the MPU can see when it wakes up after the entire |
312 | * chip enters idle. | |
8bd22949 | 313 | */ |
bbd707ac SG |
314 | omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend, |
315 | omap24xx_cpu_suspend_sz); | |
8bd22949 | 316 | |
0bcd24b0 | 317 | arm_pm_idle = omap2_pm_idle; |
8bd22949 KH |
318 | |
319 | return 0; | |
320 | } |