[deliverable/linux.git] / arch / arm / mach-omap2 / pm24xx.c

/*
 * OMAP2 Power Management Routines
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Copyright (C) 2006-2008 Nokia Corporation
 *
 * Written by:
 * Richard Woodruff <r-woodruff2@ti.com>
 * Tony Lindgren
 * Juha Yrjola
 * Amit Kucheria <amit.kucheria@nokia.com>
 * Igor Stoppa <igor.stoppa@nokia.com>
 *
 * Based on pm.c for omap1
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/suspend.h>
#include <linux/sched.h>
#include <linux/proc_fs.h>
#include <linux/interrupt.h>
#include <linux/sysfs.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/clk-provider.h>
#include <linux/irq.h>
#include <linux/time.h>
#include <linux/gpio.h>
#include <linux/platform_data/gpio-omap.h>

#include <asm/fncpy.h>

#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <asm/mach-types.h>
#include <asm/system_misc.h>

#include <linux/omap-dma.h>

#include "soc.h"
#include "common.h"
#include "clock.h"
#include "prm2xxx.h"
#include "prm-regbits-24xx.h"
#include "cm2xxx.h"
#include "cm-regbits-24xx.h"
#include "sdrc.h"
#include "sram.h"
#include "pm.h"
#include "control.h"
#include "powerdomain.h"
#include "clockdomain.h"

static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
				  void __iomem *sdrc_power);

static struct powerdomain *mpu_pwrdm, *core_pwrdm;
static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;

static struct clk *osc_ck, *emul_ck;

static int omap2_fclks_active(void)
{
	u32 f1, f2;

	f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);

	return (f1 | f2) ? 1 : 0;
}

static int omap2_enter_full_retention(void)
{
	u32 l;

	/* There is 1 reference hold for all children of the oscillator
	 * clock, the following will remove it. If no one else uses the
	 * oscillator itself it will be disabled if/when we enter retention
	 * mode.
	 */
	clk_disable(osc_ck);

	/* Clear old wake-up events */
	/* REVISIT: These write to reserved bits? */
	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
	omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);

	pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);

	/* Workaround to kill USB */
	l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
	omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);

	omap2_gpio_prepare_for_idle(0);

	/* One last check for pending IRQs to avoid extra latency due
	 * to sleeping unnecessarily. */
	if (omap_irq_pending())
		goto no_sleep;

	/* Jump to SRAM suspend code */
	omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
			   OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
			   OMAP_SDRC_REGADDR(SDRC_POWER));

no_sleep:
	omap2_gpio_resume_after_idle();

	clk_enable(osc_ck);

	/* clear CORE wake-up events */
	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);

	/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
	omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);

	/* MPU domain wake events */
	l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	if (l & 0x01)
		omap2_prm_write_mod_reg(0x01, OCP_MOD,
				  OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	if (l & 0x20)
		omap2_prm_write_mod_reg(0x20, OCP_MOD,
				  OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);

	/* Mask future PRCM-to-MPU interrupts */
	omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);

	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
	pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);

	return 0;
}

static int sti_console_enabled;

static int omap2_allow_mpu_retention(void)
{
	u32 l;

	/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
	l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
		 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
		 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
		return 0;
	/* Check for UART3. */
	l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
	if (l & OMAP24XX_EN_UART3_MASK)
		return 0;
	if (sti_console_enabled)
		return 0;

	return 1;
}

static void omap2_enter_mpu_retention(void)
{
	const int zero = 0;

	/* The peripherals seem not to be able to wake up the MPU when
	 * it is in retention mode. */
	if (omap2_allow_mpu_retention()) {
		/* REVISIT: These write to reserved bits? */
		omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
		omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
		omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);

		/* Try to enter MPU retention */
		pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);

	} else {
		/* Block MPU retention */
		pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
	}

	/* WFI */
	asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (zero) : "memory", "cc");

	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
}

static int omap2_can_sleep(void)
{
	if (omap2_fclks_active())
		return 0;
	if (__clk_is_enabled(osc_ck))
		return 0;
	if (omap_dma_running())
		return 0;

	return 1;
}

static void omap2_pm_idle(void)
{
	local_fiq_disable();

	if (!omap2_can_sleep()) {
		if (omap_irq_pending())
			goto out;
		omap2_enter_mpu_retention();
		goto out;
	}

	if (omap_irq_pending())
		goto out;

	omap2_enter_full_retention();

out:
	local_fiq_enable();
}

static void __init prcm_setup_regs(void)
{
	int i, num_mem_banks;
	struct powerdomain *pwrdm;

	/*
	 * Enable autoidle
	 * XXX This should be handled by hwmod code or PRCM init code
	 */
	omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
			  OMAP2_PRCM_SYSCONFIG_OFFSET);

	/*
	 * Set CORE powerdomain memory banks to retain their contents
	 * during RETENTION
	 */
	num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
	for (i = 0; i < num_mem_banks; i++)
		pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);

	pwrdm_set_logic_retst(core_pwrdm, PWRDM_POWER_RET);

	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);

	/* Force-power down DSP, GFX powerdomains */

	pwrdm = clkdm_get_pwrdm(dsp_clkdm);
	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);

	pwrdm = clkdm_get_pwrdm(gfx_clkdm);
	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);

	/* Enable hardware-supervised idle for all clkdms */
	clkdm_for_each(omap_pm_clkdms_setup, NULL);
	clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);

#ifdef CONFIG_SUSPEND
	omap_pm_suspend = omap2_enter_full_retention;
#endif

	/* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
	 * stabilisation */
	omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
				OMAP2_PRCM_CLKSSETUP_OFFSET);

	/* Configure automatic voltage transition */
	omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
				OMAP2_PRCM_VOLTSETUP_OFFSET);
	omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
				(0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
				OMAP24XX_MEMRETCTRL_MASK |
				(0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
				(0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
				OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);

	/* Enable wake-up events */
	omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
				WKUP_MOD, PM_WKEN);
}

int __init omap2_pm_init(void)
{
	u32 l;

	printk(KERN_INFO "Power Management for OMAP2 initializing\n");
	l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
	printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);

	/* Look up important powerdomains */

	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
	if (!mpu_pwrdm)
		pr_err("PM: mpu_pwrdm not found\n");

	core_pwrdm = pwrdm_lookup("core_pwrdm");
	if (!core_pwrdm)
		pr_err("PM: core_pwrdm not found\n");

	/* Look up important clockdomains */

	mpu_clkdm = clkdm_lookup("mpu_clkdm");
	if (!mpu_clkdm)
		pr_err("PM: mpu_clkdm not found\n");

	wkup_clkdm = clkdm_lookup("wkup_clkdm");
	if (!wkup_clkdm)
		pr_err("PM: wkup_clkdm not found\n");

	dsp_clkdm = clkdm_lookup("dsp_clkdm");
	if (!dsp_clkdm)
		pr_err("PM: dsp_clkdm not found\n");

	gfx_clkdm = clkdm_lookup("gfx_clkdm");
	if (!gfx_clkdm)
		pr_err("PM: gfx_clkdm not found\n");


	osc_ck = clk_get(NULL, "osc_ck");
	if (IS_ERR(osc_ck)) {
		printk(KERN_ERR "could not get osc_ck\n");
		return -ENODEV;
	}

	if (cpu_is_omap242x()) {
		emul_ck = clk_get(NULL, "emul_ck");
		if (IS_ERR(emul_ck)) {
			printk(KERN_ERR "could not get emul_ck\n");
			clk_put(osc_ck);
			return -ENODEV;
		}
	}

	prcm_setup_regs();

	/*
	 * We copy the assembler sleep/wakeup routines to SRAM.
	 * These routines need to be in SRAM as that's the only
	 * memory the MPU can see when it wakes up after the entire
	 * chip enters idle.
	 */
	omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
					    omap24xx_cpu_suspend_sz);

	arm_pm_idle = omap2_pm_idle;

	return 0;
}
Commit	Line	Data
8bd22949 KH	1	/*
	2	* OMAP2 Power Management Routines
	3	*
	4	* Copyright (C) 2005 Texas Instruments, Inc.
	5	* Copyright (C) 2006-2008 Nokia Corporation
	6	*
	7	* Written by:
	8	* Richard Woodruff <r-woodruff2@ti.com>
	9	* Tony Lindgren
	10	* Juha Yrjola
	11	* Amit Kucheria <amit.kucheria@nokia.com>
	12	* Igor Stoppa <igor.stoppa@nokia.com>
	13	*
	14	* Based on pm.c for omap1
	15	*
	16	* This program is free software; you can redistribute it and/or modify
	17	* it under the terms of the GNU General Public License version 2 as
	18	* published by the Free Software Foundation.
	19	*/
	20
	21	#include <linux/suspend.h>
	22	#include <linux/sched.h>
	23	#include <linux/proc_fs.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/sysfs.h>
	26	#include <linux/module.h>
	27	#include <linux/delay.h>
ed1ebc49	28	#include <linux/clk-provider.h>
8bd22949 KH	29	#include <linux/irq.h>
	30	#include <linux/time.h>
	31	#include <linux/gpio.h>
4b25408f	32	#include <linux/platform_data/gpio-omap.h>
8bd22949	33
bf027ca1 TL	34	#include <asm/fncpy.h>
bf027ca1 TL	35
8bd22949 KH	36	#include <asm/mach/time.h>
	37	#include <asm/mach/irq.h>
	38	#include <asm/mach-types.h>
9f97da78	39	#include <asm/system_misc.h>
8bd22949	40
45c3eb7d	41	#include <linux/omap-dma.h>
8bd22949	42
e4c060db	43	#include "soc.h"
4e65331c	44	#include "common.h"
a135eaae	45	#include "clock.h"
139563ad	46	#include "prm2xxx.h"
8bd22949	47	#include "prm-regbits-24xx.h"
ff4ae5d9	48	#include "cm2xxx.h"
8bd22949 KH	49	#include "cm-regbits-24xx.h"
8bd22949 KH	50	#include "sdrc.h"
bf027ca1	51	#include "sram.h"
8bd22949	52	#include "pm.h"
4814ced5	53	#include "control.h"
72e06d08	54	#include "powerdomain.h"
1540f214	55	#include "clockdomain.h"
8bd22949	56
8bd22949 KH	57	static void (omap2_sram_suspend)(u32 dllctrl, void __iomem sdrc_dlla_ctrl,
	58	void __iomem *sdrc_power);
	59
369d5614 PW	60	static struct powerdomain mpu_pwrdm, core_pwrdm;
369d5614 PW	61	static struct clockdomain dsp_clkdm, mpu_clkdm, wkup_clkdm, gfx_clkdm;
8bd22949 KH	62
	63	static struct clk osc_ck, emul_ck;
	64
	65	static int omap2_fclks_active(void)
	66	{
	67	u32 f1, f2;
	68
c4d7e58f PW	69	f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
c4d7e58f PW	70	f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
4af4016c	71
1e056ddd	72	return (f1 \| f2) ? 1 : 0;
8bd22949 KH	73	}
8bd22949 KH	74
1416408d	75	static int omap2_enter_full_retention(void)
8bd22949 KH	76	{
8bd22949 KH	77	u32 l;
8bd22949 KH	78
	79	/* There is 1 reference hold for all children of the oscillator
	80	* clock, the following will remove it. If no one else uses the
	81	* oscillator itself it will be disabled if/when we enter retention
	82	* mode.
	83	*/
	84	clk_disable(osc_ck);
	85
	86	/* Clear old wake-up events */
	87	/* REVISIT: These write to reserved bits? */
c4d7e58f PW	88	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	89	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
	90	omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
8bd22949	91
f653b298	92	pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
8bd22949 KH	93	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
	94
	95	/* Workaround to kill USB */
	96	l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) \| OMAP24XX_USBSTANDBYCTRL;
	97	omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
	98
72e06d08	99	omap2_gpio_prepare_for_idle(0);
8bd22949	100
8bd22949 KH	101	/* One last check for pending IRQs to avoid extra latency due
8bd22949 KH	102	* to sleeping unnecessarily. */
94434535	103	if (omap_irq_pending())
8bd22949 KH	104	goto no_sleep;
	105
	106	/* Jump to SRAM suspend code */
	107	omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
	108	OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
	109	OMAP_SDRC_REGADDR(SDRC_POWER));
8bd22949	110
4af4016c	111	no_sleep:
43ffcd9a	112	omap2_gpio_resume_after_idle();
8bd22949 KH	113
	114	clk_enable(osc_ck);
	115
	116	/* clear CORE wake-up events */
c4d7e58f PW	117	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
c4d7e58f PW	118	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
8bd22949 KH	119
8bd22949 KH	120	/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
c4d7e58f	121	omap2_prm_clear_mod_reg_bits(0x4 \| 0x1, WKUP_MOD, PM_WKST);
8bd22949 KH	122
8bd22949 KH	123	/* MPU domain wake events */
c4d7e58f	124	l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
8bd22949	125	if (l & 0x01)
c4d7e58f	126	omap2_prm_write_mod_reg(0x01, OCP_MOD,
8bd22949 KH	127	OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
8bd22949 KH	128	if (l & 0x20)
c4d7e58f	129	omap2_prm_write_mod_reg(0x20, OCP_MOD,
8bd22949 KH	130	OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	131
	132	/* Mask future PRCM-to-MPU interrupts */
c4d7e58f	133	omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
1416408d	134
f653b298 PW	135	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
	136	pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
	137
1416408d	138	return 0;
8bd22949 KH	139	}
8bd22949 KH	140
8bd22949 KH	141	static int sti_console_enabled;
	142
	143	static int omap2_allow_mpu_retention(void)
	144	{
	145	u32 l;
	146
	147	/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
c4d7e58f	148	l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
2fd0f75c PW	149	if (l & (OMAP2420_EN_MMC_MASK \| OMAP24XX_EN_UART2_MASK \|
	150	OMAP24XX_EN_UART1_MASK \| OMAP24XX_EN_MCSPI2_MASK \|
	151	OMAP24XX_EN_MCSPI1_MASK \| OMAP24XX_EN_DSS1_MASK))
8bd22949 KH	152	return 0;
8bd22949 KH	153	/* Check for UART3. */
c4d7e58f	154	l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
2fd0f75c	155	if (l & OMAP24XX_EN_UART3_MASK)
8bd22949 KH	156	return 0;
	157	if (sti_console_enabled)
	158	return 0;
	159
	160	return 1;
	161	}
	162
	163	static void omap2_enter_mpu_retention(void)
	164	{
088e8806 PW	165	const int zero = 0;
088e8806 PW	166
8bd22949 KH	167	/* The peripherals seem not to be able to wake up the MPU when
	168	* it is in retention mode. */
	169	if (omap2_allow_mpu_retention()) {
	170	/* REVISIT: These write to reserved bits? */
c4d7e58f PW	171	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	172	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
	173	omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
8bd22949 KH	174
8bd22949 KH	175	/* Try to enter MPU retention */
f653b298 PW	176	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
f653b298 PW	177
8bd22949 KH	178	} else {
8bd22949 KH	179	/* Block MPU retention */
f653b298	180	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
8bd22949 KH	181	}
8bd22949 KH	182
088e8806 PW	183	/* WFI */
088e8806 PW	184	asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (zero) : "memory", "cc");
f653b298 PW	185
f653b298 PW	186	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
8bd22949 KH	187	}
	188
	189	static int omap2_can_sleep(void)
	190	{
	191	if (omap2_fclks_active())
	192	return 0;
ed1ebc49	193	if (__clk_is_enabled(osc_ck))
8bd22949 KH	194	return 0;
	195	if (omap_dma_running())
	196	return 0;
	197
	198	return 1;
	199	}
	200
	201	static void omap2_pm_idle(void)
	202	{
8bd22949 KH	203	local_fiq_disable();
	204
	205	if (!omap2_can_sleep()) {
94434535	206	if (omap_irq_pending())
8bd22949 KH	207	goto out;
	208	omap2_enter_mpu_retention();
	209	goto out;
	210	}
	211
94434535	212	if (omap_irq_pending())
8bd22949 KH	213	goto out;
	214
	215	omap2_enter_full_retention();
	216
	217	out:
	218	local_fiq_enable();
8bd22949 KH	219	}
8bd22949 KH	220
8bd22949 KH	221	static void __init prcm_setup_regs(void)
	222	{
	223	int i, num_mem_banks;
	224	struct powerdomain *pwrdm;
	225
4ef70c06 PW	226	/*
	227	* Enable autoidle
	228	* XXX This should be handled by hwmod code or PRCM init code
	229	*/
c4d7e58f	230	omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
8bd22949 KH	231	OMAP2_PRCM_SYSCONFIG_OFFSET);
8bd22949 KH	232
8bd22949 KH	233	/*
	234	* Set CORE powerdomain memory banks to retain their contents
	235	* during RETENTION
	236	*/
	237	num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
	238	for (i = 0; i < num_mem_banks; i++)
	239	pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
	240
f653b298	241	pwrdm_set_logic_retst(core_pwrdm, PWRDM_POWER_RET);
8bd22949	242
8bd22949	243	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
8bd22949 KH	244
	245	/* Force-power down DSP, GFX powerdomains */
	246
	247	pwrdm = clkdm_get_pwrdm(dsp_clkdm);
	248	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
8bd22949 KH	249
	250	pwrdm = clkdm_get_pwrdm(gfx_clkdm);
	251	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
8bd22949	252
51d070af	253	/* Enable hardware-supervised idle for all clkdms */
92206fd2	254	clkdm_for_each(omap_pm_clkdms_setup, NULL);
369d5614	255	clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
8bd22949	256
1416408d PW	257	#ifdef CONFIG_SUSPEND
	258	omap_pm_suspend = omap2_enter_full_retention;
	259	#endif
	260
8bd22949 KH	261	/* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
8bd22949 KH	262	* stabilisation */
c4d7e58f PW	263	omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
c4d7e58f PW	264	OMAP2_PRCM_CLKSSETUP_OFFSET);
8bd22949 KH	265
8bd22949 KH	266	/* Configure automatic voltage transition */
c4d7e58f PW	267	omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
	268	OMAP2_PRCM_VOLTSETUP_OFFSET);
	269	omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK \|
	270	(0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) \|
	271	OMAP24XX_MEMRETCTRL_MASK \|
	272	(0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) \|
	273	(0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
	274	OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
8bd22949 KH	275
8bd22949 KH	276	/* Enable wake-up events */
c4d7e58f PW	277	omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK \| OMAP24XX_EN_GPT1_MASK,
c4d7e58f PW	278	WKUP_MOD, PM_WKEN);
8bd22949 KH	279	}
8bd22949 KH	280
bbd707ac	281	int __init omap2_pm_init(void)
8bd22949 KH	282	{
	283	u32 l;
	284
8bd22949	285	printk(KERN_INFO "Power Management for OMAP2 initializing\n");
c4d7e58f	286	l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
8bd22949 KH	287	printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
8bd22949 KH	288
369d5614	289	/* Look up important powerdomains */
8bd22949 KH	290
	291	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
	292	if (!mpu_pwrdm)
	293	pr_err("PM: mpu_pwrdm not found\n");
	294
	295	core_pwrdm = pwrdm_lookup("core_pwrdm");
	296	if (!core_pwrdm)
	297	pr_err("PM: core_pwrdm not found\n");
	298
369d5614 PW	299	/* Look up important clockdomains */
	300
	301	mpu_clkdm = clkdm_lookup("mpu_clkdm");
	302	if (!mpu_clkdm)
	303	pr_err("PM: mpu_clkdm not found\n");
	304
	305	wkup_clkdm = clkdm_lookup("wkup_clkdm");
	306	if (!wkup_clkdm)
	307	pr_err("PM: wkup_clkdm not found\n");
	308
8bd22949 KH	309	dsp_clkdm = clkdm_lookup("dsp_clkdm");
8bd22949 KH	310	if (!dsp_clkdm)
369d5614	311	pr_err("PM: dsp_clkdm not found\n");
8bd22949 KH	312
	313	gfx_clkdm = clkdm_lookup("gfx_clkdm");
	314	if (!gfx_clkdm)
	315	pr_err("PM: gfx_clkdm not found\n");
	316
	317
	318	osc_ck = clk_get(NULL, "osc_ck");
	319	if (IS_ERR(osc_ck)) {
	320	printk(KERN_ERR "could not get osc_ck\n");
	321	return -ENODEV;
	322	}
	323
	324	if (cpu_is_omap242x()) {
	325	emul_ck = clk_get(NULL, "emul_ck");
	326	if (IS_ERR(emul_ck)) {
	327	printk(KERN_ERR "could not get emul_ck\n");
	328	clk_put(osc_ck);
	329	return -ENODEV;
	330	}
	331	}
	332
	333	prcm_setup_regs();
	334
8bd22949 KH	335	/*
	336	* We copy the assembler sleep/wakeup routines to SRAM.
	337	* These routines need to be in SRAM as that's the only
088e8806 PW	338	* memory the MPU can see when it wakes up after the entire
088e8806 PW	339	* chip enters idle.
8bd22949	340	*/
bbd707ac SG	341	omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
bbd707ac SG	342	omap24xx_cpu_suspend_sz);
8bd22949	343
0bcd24b0	344	arm_pm_idle = omap2_pm_idle;
8bd22949 KH	345
	346	return 0;
	347	}