Commit | Line | Data |
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8bd22949 KH |
1 | /* |
2 | * OMAP2 Power Management Routines | |
3 | * | |
4 | * Copyright (C) 2005 Texas Instruments, Inc. | |
5 | * Copyright (C) 2006-2008 Nokia Corporation | |
6 | * | |
7 | * Written by: | |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
9 | * Tony Lindgren | |
10 | * Juha Yrjola | |
11 | * Amit Kucheria <amit.kucheria@nokia.com> | |
12 | * Igor Stoppa <igor.stoppa@nokia.com> | |
13 | * | |
14 | * Based on pm.c for omap1 | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/suspend.h> | |
22 | #include <linux/sched.h> | |
23 | #include <linux/proc_fs.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/sysfs.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/delay.h> | |
ed1ebc49 | 28 | #include <linux/clk-provider.h> |
8bd22949 KH |
29 | #include <linux/irq.h> |
30 | #include <linux/time.h> | |
31 | #include <linux/gpio.h> | |
4b25408f | 32 | #include <linux/platform_data/gpio-omap.h> |
8bd22949 | 33 | |
bf027ca1 TL |
34 | #include <asm/fncpy.h> |
35 | ||
8bd22949 KH |
36 | #include <asm/mach/time.h> |
37 | #include <asm/mach/irq.h> | |
38 | #include <asm/mach-types.h> | |
9f97da78 | 39 | #include <asm/system_misc.h> |
8bd22949 | 40 | |
45c3eb7d | 41 | #include <linux/omap-dma.h> |
8bd22949 | 42 | |
e4c060db | 43 | #include "soc.h" |
4e65331c | 44 | #include "common.h" |
a135eaae | 45 | #include "clock.h" |
139563ad | 46 | #include "prm2xxx.h" |
8bd22949 | 47 | #include "prm-regbits-24xx.h" |
ff4ae5d9 | 48 | #include "cm2xxx.h" |
8bd22949 KH |
49 | #include "cm-regbits-24xx.h" |
50 | #include "sdrc.h" | |
bf027ca1 | 51 | #include "sram.h" |
8bd22949 | 52 | #include "pm.h" |
4814ced5 | 53 | #include "control.h" |
72e06d08 | 54 | #include "powerdomain.h" |
1540f214 | 55 | #include "clockdomain.h" |
8bd22949 | 56 | |
8bd22949 KH |
57 | static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl, |
58 | void __iomem *sdrc_power); | |
59 | ||
369d5614 PW |
60 | static struct powerdomain *mpu_pwrdm, *core_pwrdm; |
61 | static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm; | |
8bd22949 KH |
62 | |
63 | static struct clk *osc_ck, *emul_ck; | |
64 | ||
65 | static int omap2_fclks_active(void) | |
66 | { | |
67 | u32 f1, f2; | |
68 | ||
c4d7e58f PW |
69 | f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); |
70 | f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); | |
4af4016c | 71 | |
1e056ddd | 72 | return (f1 | f2) ? 1 : 0; |
8bd22949 KH |
73 | } |
74 | ||
1416408d | 75 | static int omap2_enter_full_retention(void) |
8bd22949 KH |
76 | { |
77 | u32 l; | |
8bd22949 KH |
78 | |
79 | /* There is 1 reference hold for all children of the oscillator | |
80 | * clock, the following will remove it. If no one else uses the | |
81 | * oscillator itself it will be disabled if/when we enter retention | |
82 | * mode. | |
83 | */ | |
84 | clk_disable(osc_ck); | |
85 | ||
86 | /* Clear old wake-up events */ | |
87 | /* REVISIT: These write to reserved bits? */ | |
c4d7e58f PW |
88 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); |
89 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); | |
90 | omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); | |
8bd22949 | 91 | |
f653b298 | 92 | pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET); |
8bd22949 KH |
93 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); |
94 | ||
95 | /* Workaround to kill USB */ | |
96 | l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL; | |
97 | omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0); | |
98 | ||
72e06d08 | 99 | omap2_gpio_prepare_for_idle(0); |
8bd22949 | 100 | |
8bd22949 KH |
101 | /* One last check for pending IRQs to avoid extra latency due |
102 | * to sleeping unnecessarily. */ | |
94434535 | 103 | if (omap_irq_pending()) |
8bd22949 KH |
104 | goto no_sleep; |
105 | ||
106 | /* Jump to SRAM suspend code */ | |
107 | omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL), | |
108 | OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL), | |
109 | OMAP_SDRC_REGADDR(SDRC_POWER)); | |
8bd22949 | 110 | |
4af4016c | 111 | no_sleep: |
43ffcd9a | 112 | omap2_gpio_resume_after_idle(); |
8bd22949 KH |
113 | |
114 | clk_enable(osc_ck); | |
115 | ||
116 | /* clear CORE wake-up events */ | |
c4d7e58f PW |
117 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); |
118 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); | |
8bd22949 KH |
119 | |
120 | /* wakeup domain events - bit 1: GPT1, bit5 GPIO */ | |
c4d7e58f | 121 | omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); |
8bd22949 KH |
122 | |
123 | /* MPU domain wake events */ | |
c4d7e58f | 124 | l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
8bd22949 | 125 | if (l & 0x01) |
c4d7e58f | 126 | omap2_prm_write_mod_reg(0x01, OCP_MOD, |
8bd22949 KH |
127 | OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
128 | if (l & 0x20) | |
c4d7e58f | 129 | omap2_prm_write_mod_reg(0x20, OCP_MOD, |
8bd22949 KH |
130 | OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
131 | ||
132 | /* Mask future PRCM-to-MPU interrupts */ | |
c4d7e58f | 133 | omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
1416408d | 134 | |
f653b298 PW |
135 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); |
136 | pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON); | |
137 | ||
1416408d | 138 | return 0; |
8bd22949 KH |
139 | } |
140 | ||
8bd22949 KH |
141 | static int sti_console_enabled; |
142 | ||
143 | static int omap2_allow_mpu_retention(void) | |
144 | { | |
145 | u32 l; | |
146 | ||
147 | /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */ | |
c4d7e58f | 148 | l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); |
2fd0f75c PW |
149 | if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK | |
150 | OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK | | |
151 | OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK)) | |
8bd22949 KH |
152 | return 0; |
153 | /* Check for UART3. */ | |
c4d7e58f | 154 | l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); |
2fd0f75c | 155 | if (l & OMAP24XX_EN_UART3_MASK) |
8bd22949 KH |
156 | return 0; |
157 | if (sti_console_enabled) | |
158 | return 0; | |
159 | ||
160 | return 1; | |
161 | } | |
162 | ||
163 | static void omap2_enter_mpu_retention(void) | |
164 | { | |
088e8806 PW |
165 | const int zero = 0; |
166 | ||
8bd22949 KH |
167 | /* The peripherals seem not to be able to wake up the MPU when |
168 | * it is in retention mode. */ | |
169 | if (omap2_allow_mpu_retention()) { | |
170 | /* REVISIT: These write to reserved bits? */ | |
c4d7e58f PW |
171 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); |
172 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); | |
173 | omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); | |
8bd22949 KH |
174 | |
175 | /* Try to enter MPU retention */ | |
f653b298 PW |
176 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); |
177 | ||
8bd22949 KH |
178 | } else { |
179 | /* Block MPU retention */ | |
f653b298 | 180 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); |
8bd22949 KH |
181 | } |
182 | ||
088e8806 PW |
183 | /* WFI */ |
184 | asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (zero) : "memory", "cc"); | |
f653b298 PW |
185 | |
186 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); | |
8bd22949 KH |
187 | } |
188 | ||
189 | static int omap2_can_sleep(void) | |
190 | { | |
191 | if (omap2_fclks_active()) | |
192 | return 0; | |
ed1ebc49 | 193 | if (__clk_is_enabled(osc_ck)) |
8bd22949 KH |
194 | return 0; |
195 | if (omap_dma_running()) | |
196 | return 0; | |
197 | ||
198 | return 1; | |
199 | } | |
200 | ||
201 | static void omap2_pm_idle(void) | |
202 | { | |
8bd22949 | 203 | if (!omap2_can_sleep()) { |
94434535 | 204 | if (omap_irq_pending()) |
6b85638b | 205 | return; |
8bd22949 | 206 | omap2_enter_mpu_retention(); |
6b85638b | 207 | return; |
8bd22949 KH |
208 | } |
209 | ||
94434535 | 210 | if (omap_irq_pending()) |
6b85638b | 211 | return; |
8bd22949 KH |
212 | |
213 | omap2_enter_full_retention(); | |
8bd22949 KH |
214 | } |
215 | ||
8bd22949 KH |
216 | static void __init prcm_setup_regs(void) |
217 | { | |
218 | int i, num_mem_banks; | |
219 | struct powerdomain *pwrdm; | |
220 | ||
4ef70c06 PW |
221 | /* |
222 | * Enable autoidle | |
223 | * XXX This should be handled by hwmod code or PRCM init code | |
224 | */ | |
c4d7e58f | 225 | omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD, |
8bd22949 KH |
226 | OMAP2_PRCM_SYSCONFIG_OFFSET); |
227 | ||
8bd22949 KH |
228 | /* |
229 | * Set CORE powerdomain memory banks to retain their contents | |
230 | * during RETENTION | |
231 | */ | |
232 | num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm); | |
233 | for (i = 0; i < num_mem_banks; i++) | |
234 | pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET); | |
235 | ||
f653b298 | 236 | pwrdm_set_logic_retst(core_pwrdm, PWRDM_POWER_RET); |
8bd22949 | 237 | |
8bd22949 | 238 | pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET); |
8bd22949 KH |
239 | |
240 | /* Force-power down DSP, GFX powerdomains */ | |
241 | ||
242 | pwrdm = clkdm_get_pwrdm(dsp_clkdm); | |
243 | pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); | |
8bd22949 KH |
244 | |
245 | pwrdm = clkdm_get_pwrdm(gfx_clkdm); | |
246 | pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); | |
8bd22949 | 247 | |
51d070af | 248 | /* Enable hardware-supervised idle for all clkdms */ |
92206fd2 | 249 | clkdm_for_each(omap_pm_clkdms_setup, NULL); |
369d5614 | 250 | clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); |
8bd22949 | 251 | |
1416408d PW |
252 | #ifdef CONFIG_SUSPEND |
253 | omap_pm_suspend = omap2_enter_full_retention; | |
254 | #endif | |
255 | ||
8bd22949 KH |
256 | /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk |
257 | * stabilisation */ | |
c4d7e58f PW |
258 | omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, |
259 | OMAP2_PRCM_CLKSSETUP_OFFSET); | |
8bd22949 KH |
260 | |
261 | /* Configure automatic voltage transition */ | |
c4d7e58f PW |
262 | omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, |
263 | OMAP2_PRCM_VOLTSETUP_OFFSET); | |
264 | omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK | | |
265 | (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | | |
266 | OMAP24XX_MEMRETCTRL_MASK | | |
267 | (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | | |
268 | (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT), | |
269 | OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET); | |
8bd22949 KH |
270 | |
271 | /* Enable wake-up events */ | |
c4d7e58f PW |
272 | omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK, |
273 | WKUP_MOD, PM_WKEN); | |
8bd22949 KH |
274 | } |
275 | ||
bbd707ac | 276 | int __init omap2_pm_init(void) |
8bd22949 KH |
277 | { |
278 | u32 l; | |
279 | ||
8bd22949 | 280 | printk(KERN_INFO "Power Management for OMAP2 initializing\n"); |
c4d7e58f | 281 | l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET); |
8bd22949 KH |
282 | printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); |
283 | ||
369d5614 | 284 | /* Look up important powerdomains */ |
8bd22949 KH |
285 | |
286 | mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); | |
287 | if (!mpu_pwrdm) | |
288 | pr_err("PM: mpu_pwrdm not found\n"); | |
289 | ||
290 | core_pwrdm = pwrdm_lookup("core_pwrdm"); | |
291 | if (!core_pwrdm) | |
292 | pr_err("PM: core_pwrdm not found\n"); | |
293 | ||
369d5614 PW |
294 | /* Look up important clockdomains */ |
295 | ||
296 | mpu_clkdm = clkdm_lookup("mpu_clkdm"); | |
297 | if (!mpu_clkdm) | |
298 | pr_err("PM: mpu_clkdm not found\n"); | |
299 | ||
300 | wkup_clkdm = clkdm_lookup("wkup_clkdm"); | |
301 | if (!wkup_clkdm) | |
302 | pr_err("PM: wkup_clkdm not found\n"); | |
303 | ||
8bd22949 KH |
304 | dsp_clkdm = clkdm_lookup("dsp_clkdm"); |
305 | if (!dsp_clkdm) | |
369d5614 | 306 | pr_err("PM: dsp_clkdm not found\n"); |
8bd22949 KH |
307 | |
308 | gfx_clkdm = clkdm_lookup("gfx_clkdm"); | |
309 | if (!gfx_clkdm) | |
310 | pr_err("PM: gfx_clkdm not found\n"); | |
311 | ||
312 | ||
313 | osc_ck = clk_get(NULL, "osc_ck"); | |
314 | if (IS_ERR(osc_ck)) { | |
315 | printk(KERN_ERR "could not get osc_ck\n"); | |
316 | return -ENODEV; | |
317 | } | |
318 | ||
319 | if (cpu_is_omap242x()) { | |
320 | emul_ck = clk_get(NULL, "emul_ck"); | |
321 | if (IS_ERR(emul_ck)) { | |
322 | printk(KERN_ERR "could not get emul_ck\n"); | |
323 | clk_put(osc_ck); | |
324 | return -ENODEV; | |
325 | } | |
326 | } | |
327 | ||
328 | prcm_setup_regs(); | |
329 | ||
8bd22949 KH |
330 | /* |
331 | * We copy the assembler sleep/wakeup routines to SRAM. | |
332 | * These routines need to be in SRAM as that's the only | |
088e8806 PW |
333 | * memory the MPU can see when it wakes up after the entire |
334 | * chip enters idle. | |
8bd22949 | 335 | */ |
bbd707ac SG |
336 | omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend, |
337 | omap24xx_cpu_suspend_sz); | |
8bd22949 | 338 | |
0bcd24b0 | 339 | arm_pm_idle = omap2_pm_idle; |
8bd22949 KH |
340 | |
341 | return 0; | |
342 | } |