[deliverable/linux.git] / arch / arm / mach-omap2 / pm24xx.c

/*
 * OMAP2 Power Management Routines
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Copyright (C) 2006-2008 Nokia Corporation
 *
 * Written by:
 * Richard Woodruff <r-woodruff2@ti.com>
 * Tony Lindgren
 * Juha Yrjola
 * Amit Kucheria <amit.kucheria@nokia.com>
 * Igor Stoppa <igor.stoppa@nokia.com>
 *
 * Based on pm.c for omap1
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/suspend.h>
#include <linux/sched.h>
#include <linux/proc_fs.h>
#include <linux/interrupt.h>
#include <linux/sysfs.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/clk-provider.h>
#include <linux/irq.h>
#include <linux/time.h>
#include <linux/gpio.h>
#include <linux/platform_data/gpio-omap.h>

#include <asm/fncpy.h>

#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <asm/mach-types.h>
#include <asm/system_misc.h>

#include <linux/omap-dma.h>

#include "soc.h"
#include "common.h"
#include "clock.h"
#include "prm2xxx.h"
#include "prm-regbits-24xx.h"
#include "cm2xxx.h"
#include "cm-regbits-24xx.h"
#include "sdrc.h"
#include "sram.h"
#include "pm.h"
#include "control.h"
#include "powerdomain.h"
#include "clockdomain.h"

static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
				  void __iomem *sdrc_power);

static struct powerdomain *mpu_pwrdm, *core_pwrdm;
static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;

static struct clk *osc_ck, *emul_ck;

static int omap2_enter_full_retention(void)
{
	u32 l;

	/* There is 1 reference hold for all children of the oscillator
	 * clock, the following will remove it. If no one else uses the
	 * oscillator itself it will be disabled if/when we enter retention
	 * mode.
	 */
	clk_disable(osc_ck);

	/* Clear old wake-up events */
	/* REVISIT: These write to reserved bits? */
	omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
	omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
	omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);

	pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);

	/* Workaround to kill USB */
	l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
	omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);

	omap2_gpio_prepare_for_idle(0);

	/* One last check for pending IRQs to avoid extra latency due
	 * to sleeping unnecessarily. */
	if (omap_irq_pending())
		goto no_sleep;

	/* Jump to SRAM suspend code */
	omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
			   OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
			   OMAP_SDRC_REGADDR(SDRC_POWER));

no_sleep:
	omap2_gpio_resume_after_idle();

	clk_enable(osc_ck);

	/* clear CORE wake-up events */
	omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
	omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);

	/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
	omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1);

	/* MPU domain wake events */
	omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
				    0x1);

	omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
				    0x20);

	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
	pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);

	return 0;
}

static int sti_console_enabled;

static int omap2_allow_mpu_retention(void)
{
	if (!omap2xxx_cm_mpu_retention_allowed())
		return 0;
	if (sti_console_enabled)
		return 0;

	return 1;
}

static void omap2_enter_mpu_retention(void)
{
	const int zero = 0;

	/* The peripherals seem not to be able to wake up the MPU when
	 * it is in retention mode. */
	if (omap2_allow_mpu_retention()) {
		/* REVISIT: These write to reserved bits? */
		omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
		omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
		omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);

		/* Try to enter MPU retention */
		pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);

	} else {
		/* Block MPU retention */
		pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
	}

	/* WFI */
	asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (zero) : "memory", "cc");

	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
}

static int omap2_can_sleep(void)
{
	if (omap2xxx_cm_fclks_active())
		return 0;
	if (__clk_is_enabled(osc_ck))
		return 0;
	if (omap_dma_running())
		return 0;

	return 1;
}

static void omap2_pm_idle(void)
{
	if (!omap2_can_sleep()) {
		if (omap_irq_pending())
			return;
		omap2_enter_mpu_retention();
		return;
	}

	if (omap_irq_pending())
		return;

	omap2_enter_full_retention();
}

static void __init prcm_setup_regs(void)
{
	int i, num_mem_banks;
	struct powerdomain *pwrdm;

	/*
	 * Enable autoidle
	 * XXX This should be handled by hwmod code or PRCM init code
	 */
	omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
			  OMAP2_PRCM_SYSCONFIG_OFFSET);

	/*
	 * Set CORE powerdomain memory banks to retain their contents
	 * during RETENTION
	 */
	num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
	for (i = 0; i < num_mem_banks; i++)
		pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);

	pwrdm_set_logic_retst(core_pwrdm, PWRDM_POWER_RET);

	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);

	/* Force-power down DSP, GFX powerdomains */

	pwrdm = clkdm_get_pwrdm(dsp_clkdm);
	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);

	pwrdm = clkdm_get_pwrdm(gfx_clkdm);
	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);

	/* Enable hardware-supervised idle for all clkdms */
	clkdm_for_each(omap_pm_clkdms_setup, NULL);
	clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);

	omap_common_suspend_init(omap2_enter_full_retention);

	/* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
	 * stabilisation */
	omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
				OMAP2_PRCM_CLKSSETUP_OFFSET);

	/* Configure automatic voltage transition */
	omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
				OMAP2_PRCM_VOLTSETUP_OFFSET);
	omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
				(0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
				OMAP24XX_MEMRETCTRL_MASK |
				(0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
				(0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
				OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);

	/* Enable wake-up events */
	omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
				WKUP_MOD, PM_WKEN);

	/* Enable SYS_CLKEN control when all domains idle */
	omap2_prm_set_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP24XX_GR_MOD,
				   OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
}

int __init omap2_pm_init(void)
{
	u32 l;

	printk(KERN_INFO "Power Management for OMAP2 initializing\n");
	l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
	printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);

	/* Look up important powerdomains */

	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
	if (!mpu_pwrdm)
		pr_err("PM: mpu_pwrdm not found\n");

	core_pwrdm = pwrdm_lookup("core_pwrdm");
	if (!core_pwrdm)
		pr_err("PM: core_pwrdm not found\n");

	/* Look up important clockdomains */

	mpu_clkdm = clkdm_lookup("mpu_clkdm");
	if (!mpu_clkdm)
		pr_err("PM: mpu_clkdm not found\n");

	wkup_clkdm = clkdm_lookup("wkup_clkdm");
	if (!wkup_clkdm)
		pr_err("PM: wkup_clkdm not found\n");

	dsp_clkdm = clkdm_lookup("dsp_clkdm");
	if (!dsp_clkdm)
		pr_err("PM: dsp_clkdm not found\n");

	gfx_clkdm = clkdm_lookup("gfx_clkdm");
	if (!gfx_clkdm)
		pr_err("PM: gfx_clkdm not found\n");


	osc_ck = clk_get(NULL, "osc_ck");
	if (IS_ERR(osc_ck)) {
		printk(KERN_ERR "could not get osc_ck\n");
		return -ENODEV;
	}

	if (cpu_is_omap242x()) {
		emul_ck = clk_get(NULL, "emul_ck");
		if (IS_ERR(emul_ck)) {
			printk(KERN_ERR "could not get emul_ck\n");
			clk_put(osc_ck);
			return -ENODEV;
		}
	}

	prcm_setup_regs();

	/*
	 * We copy the assembler sleep/wakeup routines to SRAM.
	 * These routines need to be in SRAM as that's the only
	 * memory the MPU can see when it wakes up after the entire
	 * chip enters idle.
	 */
	omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
					    omap24xx_cpu_suspend_sz);

	arm_pm_idle = omap2_pm_idle;

	return 0;
}
Commit	Line	Data
8bd22949 KH	1	/*
	2	* OMAP2 Power Management Routines
	3	*
	4	* Copyright (C) 2005 Texas Instruments, Inc.
	5	* Copyright (C) 2006-2008 Nokia Corporation
	6	*
	7	* Written by:
	8	* Richard Woodruff <r-woodruff2@ti.com>
	9	* Tony Lindgren
	10	* Juha Yrjola
	11	* Amit Kucheria <amit.kucheria@nokia.com>
	12	* Igor Stoppa <igor.stoppa@nokia.com>
	13	*
	14	* Based on pm.c for omap1
	15	*
	16	* This program is free software; you can redistribute it and/or modify
	17	* it under the terms of the GNU General Public License version 2 as
	18	* published by the Free Software Foundation.
	19	*/
	20
	21	#include <linux/suspend.h>
	22	#include <linux/sched.h>
	23	#include <linux/proc_fs.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/sysfs.h>
	26	#include <linux/module.h>
	27	#include <linux/delay.h>
ed1ebc49	28	#include <linux/clk-provider.h>
8bd22949 KH	29	#include <linux/irq.h>
	30	#include <linux/time.h>
	31	#include <linux/gpio.h>
4b25408f	32	#include <linux/platform_data/gpio-omap.h>
8bd22949	33
bf027ca1 TL	34	#include <asm/fncpy.h>
bf027ca1 TL	35
8bd22949 KH	36	#include <asm/mach/time.h>
	37	#include <asm/mach/irq.h>
	38	#include <asm/mach-types.h>
9f97da78	39	#include <asm/system_misc.h>
8bd22949	40
45c3eb7d	41	#include <linux/omap-dma.h>
8bd22949	42
e4c060db	43	#include "soc.h"
4e65331c	44	#include "common.h"
a135eaae	45	#include "clock.h"
139563ad	46	#include "prm2xxx.h"
8bd22949	47	#include "prm-regbits-24xx.h"
ff4ae5d9	48	#include "cm2xxx.h"
8bd22949 KH	49	#include "cm-regbits-24xx.h"
8bd22949 KH	50	#include "sdrc.h"
bf027ca1	51	#include "sram.h"
8bd22949	52	#include "pm.h"
4814ced5	53	#include "control.h"
72e06d08	54	#include "powerdomain.h"
1540f214	55	#include "clockdomain.h"
8bd22949	56
8bd22949 KH	57	static void (omap2_sram_suspend)(u32 dllctrl, void __iomem sdrc_dlla_ctrl,
	58	void __iomem *sdrc_power);
	59
369d5614 PW	60	static struct powerdomain mpu_pwrdm, core_pwrdm;
369d5614 PW	61	static struct clockdomain dsp_clkdm, mpu_clkdm, wkup_clkdm, gfx_clkdm;
8bd22949 KH	62
	63	static struct clk osc_ck, emul_ck;
	64
1416408d	65	static int omap2_enter_full_retention(void)
8bd22949 KH	66	{
8bd22949 KH	67	u32 l;
8bd22949 KH	68
	69	/* There is 1 reference hold for all children of the oscillator
	70	* clock, the following will remove it. If no one else uses the
	71	* oscillator itself it will be disabled if/when we enter retention
	72	* mode.
	73	*/
	74	clk_disable(osc_ck);
	75
	76	/* Clear old wake-up events */
	77	/* REVISIT: These write to reserved bits? */
6bdc4b44 TK	78	omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
	79	omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
	80	omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
8bd22949	81
f653b298	82	pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
8bd22949 KH	83	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
	84
	85	/* Workaround to kill USB */
	86	l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) \| OMAP24XX_USBSTANDBYCTRL;
	87	omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
	88
72e06d08	89	omap2_gpio_prepare_for_idle(0);
8bd22949	90
8bd22949 KH	91	/* One last check for pending IRQs to avoid extra latency due
8bd22949 KH	92	* to sleeping unnecessarily. */
94434535	93	if (omap_irq_pending())
8bd22949 KH	94	goto no_sleep;
	95
	96	/* Jump to SRAM suspend code */
	97	omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
	98	OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
	99	OMAP_SDRC_REGADDR(SDRC_POWER));
8bd22949	100
4af4016c	101	no_sleep:
43ffcd9a	102	omap2_gpio_resume_after_idle();
8bd22949 KH	103
	104	clk_enable(osc_ck);
	105
	106	/* clear CORE wake-up events */
6bdc4b44 TK	107	omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
6bdc4b44 TK	108	omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
8bd22949 KH	109
8bd22949 KH	110	/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
6bdc4b44	111	omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 \| 0x1);
8bd22949 KH	112
8bd22949 KH	113	/* MPU domain wake events */
6bdc4b44 TK	114	omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
6bdc4b44 TK	115	0x1);
8bd22949	116
6bdc4b44 TK	117	omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
6bdc4b44 TK	118	0x20);
1416408d	119
f653b298 PW	120	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
	121	pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
	122
1416408d	123	return 0;
8bd22949 KH	124	}
8bd22949 KH	125
8bd22949 KH	126	static int sti_console_enabled;
	127
	128	static int omap2_allow_mpu_retention(void)
	129	{
cd6e9db2	130	if (!omap2xxx_cm_mpu_retention_allowed())
8bd22949 KH	131	return 0;
	132	if (sti_console_enabled)
	133	return 0;
	134
	135	return 1;
	136	}
	137
	138	static void omap2_enter_mpu_retention(void)
	139	{
088e8806 PW	140	const int zero = 0;
088e8806 PW	141
8bd22949 KH	142	/* The peripherals seem not to be able to wake up the MPU when
	143	* it is in retention mode. */
	144	if (omap2_allow_mpu_retention()) {
	145	/* REVISIT: These write to reserved bits? */
6bdc4b44 TK	146	omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
	147	omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
	148	omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
8bd22949 KH	149
8bd22949 KH	150	/* Try to enter MPU retention */
f653b298 PW	151	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
f653b298 PW	152
8bd22949 KH	153	} else {
8bd22949 KH	154	/* Block MPU retention */
f653b298	155	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
8bd22949 KH	156	}
8bd22949 KH	157
088e8806 PW	158	/* WFI */
088e8806 PW	159	asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (zero) : "memory", "cc");
f653b298 PW	160
f653b298 PW	161	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
8bd22949 KH	162	}
	163
	164	static int omap2_can_sleep(void)
	165	{
cd6e9db2	166	if (omap2xxx_cm_fclks_active())
8bd22949	167	return 0;
ed1ebc49	168	if (__clk_is_enabled(osc_ck))
8bd22949 KH	169	return 0;
	170	if (omap_dma_running())
	171	return 0;
	172
	173	return 1;
	174	}
	175
	176	static void omap2_pm_idle(void)
	177	{
8bd22949	178	if (!omap2_can_sleep()) {
94434535	179	if (omap_irq_pending())
6b85638b	180	return;
8bd22949	181	omap2_enter_mpu_retention();
6b85638b	182	return;
8bd22949 KH	183	}
8bd22949 KH	184
94434535	185	if (omap_irq_pending())
6b85638b	186	return;
8bd22949 KH	187
8bd22949 KH	188	omap2_enter_full_retention();
8bd22949 KH	189	}
8bd22949 KH	190
8bd22949 KH	191	static void __init prcm_setup_regs(void)
	192	{
	193	int i, num_mem_banks;
	194	struct powerdomain *pwrdm;
	195
4ef70c06 PW	196	/*
	197	* Enable autoidle
	198	* XXX This should be handled by hwmod code or PRCM init code
	199	*/
c4d7e58f	200	omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
8bd22949 KH	201	OMAP2_PRCM_SYSCONFIG_OFFSET);
8bd22949 KH	202
8bd22949 KH	203	/*
	204	* Set CORE powerdomain memory banks to retain their contents
	205	* during RETENTION
	206	*/
	207	num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
	208	for (i = 0; i < num_mem_banks; i++)
	209	pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
	210
f653b298	211	pwrdm_set_logic_retst(core_pwrdm, PWRDM_POWER_RET);
8bd22949	212
8bd22949	213	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
8bd22949 KH	214
	215	/* Force-power down DSP, GFX powerdomains */
	216
	217	pwrdm = clkdm_get_pwrdm(dsp_clkdm);
	218	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
8bd22949 KH	219
	220	pwrdm = clkdm_get_pwrdm(gfx_clkdm);
	221	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
8bd22949	222
51d070af	223	/* Enable hardware-supervised idle for all clkdms */
92206fd2	224	clkdm_for_each(omap_pm_clkdms_setup, NULL);
369d5614	225	clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
8bd22949	226
2e4b62dc	227	omap_common_suspend_init(omap2_enter_full_retention);
1416408d	228
8bd22949 KH	229	/* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
8bd22949 KH	230	* stabilisation */
c4d7e58f PW	231	omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
c4d7e58f PW	232	OMAP2_PRCM_CLKSSETUP_OFFSET);
8bd22949 KH	233
8bd22949 KH	234	/* Configure automatic voltage transition */
c4d7e58f PW	235	omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
	236	OMAP2_PRCM_VOLTSETUP_OFFSET);
	237	omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK \|
	238	(0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) \|
	239	OMAP24XX_MEMRETCTRL_MASK \|
	240	(0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) \|
	241	(0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
	242	OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
8bd22949 KH	243
8bd22949 KH	244	/* Enable wake-up events */
c4d7e58f PW	245	omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK \| OMAP24XX_EN_GPT1_MASK,
c4d7e58f PW	246	WKUP_MOD, PM_WKEN);
944ee5dc TK	247
	248	/* Enable SYS_CLKEN control when all domains idle */
	249	omap2_prm_set_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP24XX_GR_MOD,
	250	OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
8bd22949 KH	251	}
8bd22949 KH	252
bbd707ac	253	int __init omap2_pm_init(void)
8bd22949 KH	254	{
	255	u32 l;
	256
8bd22949	257	printk(KERN_INFO "Power Management for OMAP2 initializing\n");
c4d7e58f	258	l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
8bd22949 KH	259	printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
8bd22949 KH	260
369d5614	261	/* Look up important powerdomains */
8bd22949 KH	262
	263	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
	264	if (!mpu_pwrdm)
	265	pr_err("PM: mpu_pwrdm not found\n");
	266
	267	core_pwrdm = pwrdm_lookup("core_pwrdm");
	268	if (!core_pwrdm)
	269	pr_err("PM: core_pwrdm not found\n");
	270
369d5614 PW	271	/* Look up important clockdomains */
	272
	273	mpu_clkdm = clkdm_lookup("mpu_clkdm");
	274	if (!mpu_clkdm)
	275	pr_err("PM: mpu_clkdm not found\n");
	276
	277	wkup_clkdm = clkdm_lookup("wkup_clkdm");
	278	if (!wkup_clkdm)
	279	pr_err("PM: wkup_clkdm not found\n");
	280
8bd22949 KH	281	dsp_clkdm = clkdm_lookup("dsp_clkdm");
8bd22949 KH	282	if (!dsp_clkdm)
369d5614	283	pr_err("PM: dsp_clkdm not found\n");
8bd22949 KH	284
	285	gfx_clkdm = clkdm_lookup("gfx_clkdm");
	286	if (!gfx_clkdm)
	287	pr_err("PM: gfx_clkdm not found\n");
	288
	289
	290	osc_ck = clk_get(NULL, "osc_ck");
	291	if (IS_ERR(osc_ck)) {
	292	printk(KERN_ERR "could not get osc_ck\n");
	293	return -ENODEV;
	294	}
	295
	296	if (cpu_is_omap242x()) {
	297	emul_ck = clk_get(NULL, "emul_ck");
	298	if (IS_ERR(emul_ck)) {
	299	printk(KERN_ERR "could not get emul_ck\n");
	300	clk_put(osc_ck);
	301	return -ENODEV;
	302	}
	303	}
	304
	305	prcm_setup_regs();
	306
8bd22949 KH	307	/*
	308	* We copy the assembler sleep/wakeup routines to SRAM.
	309	* These routines need to be in SRAM as that's the only
088e8806 PW	310	* memory the MPU can see when it wakes up after the entire
088e8806 PW	311	* chip enters idle.
8bd22949	312	*/
bbd707ac SG	313	omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
bbd707ac SG	314	omap24xx_cpu_suspend_sz);
8bd22949	315
0bcd24b0	316	arm_pm_idle = omap2_pm_idle;
8bd22949 KH	317
	318	return 0;
	319	}